diff options
| author | Greg Kroah-Hartman <greg@kroah.com> | 2003-02-26 21:49:57 -0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <greg@kroah.com> | 2003-02-26 21:49:57 -0800 |
| commit | fffd915522cb703e95381fc52c0ac3843f013f18 (patch) | |
| tree | 7efd17b1bd1a584a7fa10633d26b4b5e99283deb /arch | |
| parent | a6cc5237a1f189c30cd06d05e2955e5bc63d8913 (diff) | |
| parent | be8013e867207d570f33cc1c66bd06797f1eed6b (diff) | |
Merge kroah.com:/home/greg/linux/BK/bleed-2.5
into kroah.com:/home/greg/linux/BK/pci-2.5
Diffstat (limited to 'arch')
208 files changed, 848 insertions, 270 deletions
diff --git a/arch/alpha/boot/tools/objstrip.c b/arch/alpha/boot/tools/objstrip.c index bbda40330708..b454091d7b6f 100644 --- a/arch/alpha/boot/tools/objstrip.c +++ b/arch/alpha/boot/tools/objstrip.c @@ -7,7 +7,7 @@ */ /* * Converts an ECOFF or ELF object file into a bootable file. The - * object file must be a OMAGIC file (i.e., data and bss follow immediatly + * object file must be a OMAGIC file (i.e., data and bss follow immediately * behind the text). See DEC "Assembly Language Programmer's Guide" * documentation for details. The SRM boot process is documented in * the Alpha AXP Architecture Reference Manual, Second Edition by diff --git a/arch/alpha/kernel/pci_iommu.c b/arch/alpha/kernel/pci_iommu.c index 436502888e12..614aa87cb94f 100644 --- a/arch/alpha/kernel/pci_iommu.c +++ b/arch/alpha/kernel/pci_iommu.c @@ -318,7 +318,7 @@ pci_map_page(struct pci_dev *pdev, struct page *page, unsigned long offset, /* Unmap a single streaming mode DMA translation. The DMA_ADDR and SIZE must match what was provided for in a previous pci_map_single call. All other usages are undefined. After this call, reads by - the cpu to the buffer are guarenteed to see whatever the device + the cpu to the buffer are guaranteed to see whatever the device wrote there. */ void diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c index 224ddf8b9ca2..16631bf1034a 100644 --- a/arch/alpha/kernel/sys_marvel.c +++ b/arch/alpha/kernel/sys_marvel.c @@ -440,7 +440,7 @@ marvel_smp_callin(void) return; /* - * There is a local IO7 - redirect all of it's interrupts here. + * There is a local IO7 - redirect all of its interrupts here. */ printk("Redirecting IO7 interrupts to local CPU at PE %u\n", cpuid); diff --git a/arch/alpha/kernel/time.c b/arch/alpha/kernel/time.c index 0d56b55e52e6..9f0bd3cdaac6 100644 --- a/arch/alpha/kernel/time.c +++ b/arch/alpha/kernel/time.c @@ -50,7 +50,7 @@ #include "proto.h" #include "irq_impl.h" -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; extern unsigned long wall_jiffies; /* kernel/timer.c */ diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c index 9803b8ca0670..4cfbd4e27786 100644 --- a/arch/alpha/kernel/traps.c +++ b/arch/alpha/kernel/traps.c @@ -411,7 +411,7 @@ do_entIF(unsigned long type, struct pt_regs *regs) } /* There is an ifdef in the PALcode in MILO that enables a - "kernel debugging entry point" as an unpriviledged call_pal. + "kernel debugging entry point" as an unprivileged call_pal. We don't want to have anything to do with it, but unfortunately several versions of MILO included in distributions have it enabled, diff --git a/arch/alpha/lib/checksum.c b/arch/alpha/lib/checksum.c index 7f29ac81c7f3..9f2daa0301fe 100644 --- a/arch/alpha/lib/checksum.c +++ b/arch/alpha/lib/checksum.c @@ -63,7 +63,7 @@ unsigned int csum_tcpudp_nofold(unsigned long saddr, ((unsigned long) ntohs(len) << 16) + ((unsigned long) proto << 8)); - /* Fold down to 32-bits so we don't loose in the typedef-less + /* Fold down to 32-bits so we don't lose in the typedef-less network stack. */ /* 64 to 33 */ result = (result & 0xffffffff) + (result >> 32); diff --git a/arch/arm/kernel/entry-armo.S b/arch/arm/kernel/entry-armo.S index c204f080a304..f081ad9af786 100644 --- a/arch/arm/kernel/entry-armo.S +++ b/arch/arm/kernel/entry-armo.S @@ -426,7 +426,7 @@ Ldata_do: mov r3, sp mov r2, #0 tst r4, #1 << 20 @ Check to see if it is a write instruction orreq r2, r2, #FAULT_CODE_WRITE @ Indicate write instruction - mov r1, r4, lsr #22 @ Now branch to the relevent processing routine + mov r1, r4, lsr #22 @ Now branch to the relevant processing routine and r1, r1, #15 << 2 add pc, pc, r1 movs pc, lr diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 72245e91600c..c300acd5a385 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -1026,7 +1026,7 @@ vector_IRQ: @ mrs lr, spsr str lr, [r13, #4] @ save spsr_IRQ @ - @ now branch to the relevent MODE handling routine + @ now branch to the relevant MODE handling routine @ mov r13, #PSR_I_BIT | MODE_SVC msr spsr_c, r13 @ switch to SVC_32 mode @@ -1067,7 +1067,7 @@ vector_data: @ mrs lr, spsr str lr, [r13, #4] @ - @ now branch to the relevent MODE handling routine + @ now branch to the relevant MODE handling routine @ mov r13, #PSR_I_BIT | MODE_SVC msr spsr_c, r13 @ switch to SVC_32 mode @@ -1109,7 +1109,7 @@ vector_prefetch: mrs lr, spsr str lr, [r13, #4] @ save spsr_ABT @ - @ now branch to the relevent MODE handling routine + @ now branch to the relevant MODE handling routine @ mov r13, #PSR_I_BIT | MODE_SVC msr spsr_c, r13 @ switch to SVC_32 mode @@ -1150,7 +1150,7 @@ vector_undefinstr: mrs lr, spsr str lr, [r13, #4] @ save spsr_UND @ - @ now branch to the relevent MODE handling routine + @ now branch to the relevant MODE handling routine @ mov r13, #PSR_I_BIT | MODE_SVC msr spsr_c, r13 @ switch to SVC_32 mode diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index eee41a18b7e4..473a27aa39d0 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c @@ -435,7 +435,7 @@ void ptrace_set_bpt(struct task_struct *child) * be receiving a prefetch abort shortly. * * If we don't set this breakpoint here, then we can - * loose control of the thread during single stepping. + * lose control of the thread during single stepping. */ if (!alt || predicate(insn) != PREDICATE_ALWAYS) add_breakpoint(child, dbg, pc + 4); diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 1cb54c5d5204..f7dbb73f8064 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -32,7 +32,7 @@ #include <asm/irq.h> #include <asm/leds.h> -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; extern unsigned long wall_jiffies; diff --git a/arch/arm/mach-iop310/iop310-pci.c b/arch/arm/mach-iop310/iop310-pci.c index 3cf19682f279..30a48f98a8df 100644 --- a/arch/arm/mach-iop310/iop310-pci.c +++ b/arch/arm/mach-iop310/iop310-pci.c @@ -296,7 +296,7 @@ static struct pci_ops iop310_secondary_ops = { * within 3 instructions." * * This does not appear to be the case. With 8 NOPs after the load, we - * see the imprecise abort occuring on the STM of iop310_sec_pci_status() + * see the imprecise abort occurring on the STM of iop310_sec_pci_status() * which is about 10 instructions away. * * Always trust reality! diff --git a/arch/arm/mach-iop310/mm.c b/arch/arm/mach-iop310/mm.c index 2b09969e53b1..59200937c0f8 100644 --- a/arch/arm/mach-iop310/mm.c +++ b/arch/arm/mach-iop310/mm.c @@ -1,7 +1,7 @@ /* * linux/arch/arm/mach-iop310/mm.c * - * Low level memory intialization for IOP310 based systems + * Low level memory initialization for IOP310 based systems * * Author: Nicolas Pitre <npitre@mvista.com> * diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S index 2c5bf39ab0a4..76b6eed5366c 100644 --- a/arch/arm/mm/proc-arm6_7.S +++ b/arch/arm/mm/proc-arm6_7.S @@ -97,7 +97,7 @@ ENTRY(cpu_arm7_data_abort) tst r4, r4, lsr #21 @ C = bit 20 sbc r1, r1, r1 @ r1 = C - 1 and r2, r4, #15 << 24 - add pc, pc, r2, lsr #22 @ Now branch to the relevent processing routine + add pc, pc, r2, lsr #22 @ Now branch to the relevant processing routine movs pc, lr b Ldata_unknown diff --git a/arch/cris/boot/rescue/head.S b/arch/cris/boot/rescue/head.S index 40f9af6b6ef4..52881742da43 100644 --- a/arch/cris/boot/rescue/head.S +++ b/arch/cris/boot/rescue/head.S @@ -130,7 +130,7 @@ in_cache: ;; first put a jump test to give a possibility of upgrading the rescue code ;; without erasing/reflashing the sector. we put a longword of -1 here and if - ;; its not -1, we jump using the value as jump target. since we can always + ;; it is not -1, we jump using the value as jump target. since we can always ;; change 1's to 0's without erasing the sector, it is possible to add new ;; code after this and altering the jumptarget in an upgrade. diff --git a/arch/cris/drivers/eeprom.c b/arch/cris/drivers/eeprom.c index eb5aa7db784b..7a94c4cbac4c 100644 --- a/arch/cris/drivers/eeprom.c +++ b/arch/cris/drivers/eeprom.c @@ -815,7 +815,7 @@ static int read_from_eeprom(char * buf, int count) i2c_outbyte( eeprom.select_cmd | 1 ); } - if(i2c_getack()); + if(i2c_getack()) { break; } diff --git a/arch/cris/drivers/ethernet.c b/arch/cris/drivers/ethernet.c index e22f35d1fcdf..31c918563f76 100644 --- a/arch/cris/drivers/ethernet.c +++ b/arch/cris/drivers/ethernet.c @@ -236,7 +236,7 @@ static unsigned int network_rec_config_shadow = 0; /* Network speed indication. */ static struct timer_list speed_timer = TIMER_INITIALIZER(NULL, 0, 0); static struct timer_list clear_led_timer = TIMER_INITIALIZER(NULL, 0, 0); -static int current_speed; /* Speed read from tranceiver */ +static int current_speed; /* Speed read from transceiver */ static int current_speed_selection; /* Speed selected by user */ static int led_next_time; static int led_active; @@ -276,7 +276,7 @@ static unsigned short e100_get_mdio_reg(unsigned char reg_num); static void e100_send_mdio_cmd(unsigned short cmd, int write_cmd); static void e100_send_mdio_bit(unsigned char bit); static unsigned char e100_receive_mdio_bit(void); -static void e100_reset_tranceiver(void); +static void e100_reset_transceiver(void); static void e100_clear_network_leds(unsigned long dummy); static void e100_set_network_leds(int active); @@ -786,7 +786,7 @@ e100_receive_mdio_bit() } static void -e100_reset_tranceiver(void) +e100_reset_transceiver(void) { unsigned short cmd; unsigned short data; @@ -826,9 +826,9 @@ e100_tx_timeout(struct net_device *dev) RESET_DMA(NETWORK_TX_DMA_NBR); WAIT_DMA(NETWORK_TX_DMA_NBR); - /* Reset the tranceiver. */ + /* Reset the transceiver. */ - e100_reset_tranceiver(); + e100_reset_transceiver(); /* and get rid of the packet that never got an interrupt */ diff --git a/arch/cris/drivers/lpslave/e100lpslavenet.c b/arch/cris/drivers/lpslave/e100lpslavenet.c index c802187c1194..5555809bdc40 100644 --- a/arch/cris/drivers/lpslave/e100lpslavenet.c +++ b/arch/cris/drivers/lpslave/e100lpslavenet.c @@ -129,7 +129,7 @@ static void set_multicast_list(struct net_device *dev); static void e100_hardware_send_packet(unsigned long hostcmd, char *buf, int length); static void update_rx_stats(struct net_device_stats *); static void update_tx_stats(struct net_device_stats *); -static void e100_reset_tranceiver(void); +static void e100_reset_transceiver(void); static void boot_slave(unsigned char *code); @@ -528,7 +528,7 @@ e100_open(struct net_device *dev) } static void -e100_reset_tranceiver(void) +e100_reset_transceiver(void) { /* To do: Reboot and setup slave Etrax */ } @@ -554,9 +554,9 @@ e100_tx_timeout(struct net_device *dev) RESET_DMA(4); WAIT_DMA(4); - /* Reset the tranceiver. */ + /* Reset the transceiver. */ - e100_reset_tranceiver(); + e100_reset_transceiver(); /* and get rid of the packet that never got an interrupt */ diff --git a/arch/cris/drivers/serial.c b/arch/cris/drivers/serial.c index edeed9fe241b..5fb7b45d0e94 100644 --- a/arch/cris/drivers/serial.c +++ b/arch/cris/drivers/serial.c @@ -132,7 +132,7 @@ * Items worth noticing: * * No Etrax100 port 1 workarounds (does only compile on 2.4 anyway now) - * RS485 is not ported (why cant it be done in userspace as on x86 ?) + * RS485 is not ported (why can't it be done in userspace as on x86 ?) * Statistics done through async_icount - if any more stats are needed, * that's the place to put them or in an arch-dep version of it. * timeout_interrupt and the other fast timeout stuff not ported yet @@ -1766,7 +1766,7 @@ will look differently: B= Break character (0x00) with framing error. E= Error byte with parity error received after B characters. -F= "Faked" valid byte received immediatly after B characters. +F= "Faked" valid byte received immediately after B characters. V= Valid byte 1. @@ -2802,7 +2802,7 @@ send_break(struct e100_serial * info, int duration) info->tx_ctrl |= (0x80 | 0x40); /* Set bit 7 (txd) and 6 (tr_enable) */ info->port[REG_TR_CTRL] = info->tx_ctrl; - /* the DMA gets awfully confused if we toggle the tranceiver like this + /* the DMA gets awfully confused if we toggle the transceiver like this * so we need to reset it */ *info->ocmdadr = 4; diff --git a/arch/cris/kernel/kgdb.c b/arch/cris/kernel/kgdb.c index 5d5c9d4bbfdc..c88eb88013b1 100644 --- a/arch/cris/kernel/kgdb.c +++ b/arch/cris/kernel/kgdb.c @@ -1486,7 +1486,7 @@ kgdb_handle_serial: move.d $r0,[reg+0x62] ; Save the return address in BRP move $usp,[reg+0x66] ; USP -;; get the serial character (from debugport.c) and check if its a ctrl-c +;; get the serial character (from debugport.c) and check if it is a ctrl-c jsr getDebugChar cmp.b 3, $r10 diff --git a/arch/cris/kernel/process.c b/arch/cris/kernel/process.c index 9eb5b73519c5..60441877ef2f 100644 --- a/arch/cris/kernel/process.c +++ b/arch/cris/kernel/process.c @@ -154,7 +154,7 @@ void hard_reset_now (void) #if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM) cause_of_death = 0xbedead; #else - /* Since we dont plan to keep on reseting the watchdog, + /* Since we don't plan to keep on reseting the watchdog, the key can be arbitrary hence three */ *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, 3) | IO_STATE(R_WATCHDOG, enable, start); @@ -226,7 +226,7 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp, swstack = ((struct switch_stack *)childregs) - 1; - swstack->r9 = 0; /* parameter to ret_from_sys_call, 0 == dont restart the syscall */ + swstack->r9 = 0; /* parameter to ret_from_sys_call, 0 == don't restart the syscall */ /* we want to return into ret_from_sys_call after the _resume */ diff --git a/arch/cris/kernel/setup.c b/arch/cris/kernel/setup.c index 6ab8d7bc0feb..a97ce40542fd 100644 --- a/arch/cris/kernel/setup.c +++ b/arch/cris/kernel/setup.c @@ -164,7 +164,7 @@ setup_arch(char **cmdline_p) paging_init(); - /* We dont use a command line yet, so just re-initialize it without + /* We don't use a command line yet, so just re-initialize it without saving anything that might be there. */ *cmdline_p = command_line; diff --git a/arch/cris/kernel/signal.c b/arch/cris/kernel/signal.c index a04726efc889..678281dae205 100644 --- a/arch/cris/kernel/signal.c +++ b/arch/cris/kernel/signal.c @@ -494,7 +494,7 @@ handle_signal(int canrestart, unsigned long sig, case -ERESTARTNOHAND: /* ERESTARTNOHAND means that the syscall should only be restarted if there was no handler for the signal, and since - we only get here if there is a handler, we dont restart */ + we only get here if there is a handler, we don't restart */ regs->r10 = -EINTR; break; diff --git a/arch/cris/kernel/time.c b/arch/cris/kernel/time.c index 0541e25a48aa..f42806219c68 100644 --- a/arch/cris/kernel/time.c +++ b/arch/cris/kernel/time.c @@ -45,7 +45,7 @@ #include <asm/svinto.h> -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; static int have_rtc; /* used to remember if we have an RTC or not */ diff --git a/arch/cris/mm/fault.c b/arch/cris/mm/fault.c index fa0a6934eed1..2e4d91e40cf9 100644 --- a/arch/cris/mm/fault.c +++ b/arch/cris/mm/fault.c @@ -170,7 +170,7 @@ handle_mmu_bus_fault(struct pt_regs *regs) if (miss) { /* see if the pte exists at all - * refer through current_pgd, dont use mm->pgd + * refer through current_pgd, don't use mm->pgd */ pmd = (pmd_t *)(current_pgd + pgd_index(address)); diff --git a/arch/cris/mm/tlb.c b/arch/cris/mm/tlb.c index 9d5e588d8028..f5a97c9799fd 100644 --- a/arch/cris/mm/tlb.c +++ b/arch/cris/mm/tlb.c @@ -58,7 +58,7 @@ flush_tlb_all(void) int i; unsigned long flags; - /* the vpn of i & 0xf is so we dont write similar TLB entries + /* the vpn of i & 0xf is so we don't write similar TLB entries * in the same 4-way entry group. details.. */ diff --git a/arch/i386/Kconfig b/arch/i386/Kconfig index e9098fd1e3f0..d0977e4e74d9 100644 --- a/arch/i386/Kconfig +++ b/arch/i386/Kconfig @@ -75,6 +75,11 @@ config X86_SUMMIT If you don't have one of these computers, you should say N here. +config ACPI_SRAT + bool + default y + depends on NUMA && X86_SUMMIT + config X86_BIGSMP bool "Support for other sub-arch SMP systems with more than 8 CPUs" help @@ -483,7 +488,7 @@ config NR_CPUS # Common NUMA Features config NUMA bool "Numa Memory Allocation Support" - depends on X86_NUMAQ + depends on (HIGHMEM64G && (X86_NUMAQ || (X86_SUMMIT && ACPI && !ACPI_HT_ONLY))) config DISCONTIGMEM bool @@ -752,6 +757,13 @@ config HAVE_DEC_LOCK depends on (SMP || PREEMPT) && X86_CMPXCHG default y +# turning this on wastes a bunch of space. +# Summit needs it only when NUMA is on +config BOOT_IOREMAP + bool + depends on (X86_SUMMIT && NUMA) + default y + endmenu diff --git a/arch/i386/boot/bootsect.S b/arch/i386/boot/bootsect.S index a99ffbbbe905..ebaa2556fd13 100644 --- a/arch/i386/boot/bootsect.S +++ b/arch/i386/boot/bootsect.S @@ -405,7 +405,7 @@ kill_motor: ret sectors: .word 0 -disksizes: .byte 36, 18, 15, 9 +disksizes: .byte 36, 21, 18, 15, 9 msg1: .byte 13, 10 .ascii "Loading" diff --git a/arch/i386/kernel/Makefile b/arch/i386/kernel/Makefile index 400829ad9e89..c423f788cf7f 100644 --- a/arch/i386/kernel/Makefile +++ b/arch/i386/kernel/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_X86_NUMAQ) += numaq.o obj-$(CONFIG_EDD) += edd.o obj-$(CONFIG_MODULES) += module.o obj-y += sysenter.o +obj-$(CONFIG_ACPI_SRAT) += srat.o EXTRA_AFLAGS := -traditional diff --git a/arch/i386/kernel/acpi/boot.c b/arch/i386/kernel/acpi/boot.c index 6e94298acae8..2f945403d38d 100644 --- a/arch/i386/kernel/acpi/boot.c +++ b/arch/i386/kernel/acpi/boot.c @@ -24,6 +24,7 @@ */ #include <linux/init.h> +#include <linux/config.h> #include <linux/acpi.h> #include <asm/pgalloc.h> #include <asm/apic.h> diff --git a/arch/i386/kernel/apic.c b/arch/i386/kernel/apic.c index 921e49ee3a3d..af9ec6bbf5ba 100644 --- a/arch/i386/kernel/apic.c +++ b/arch/i386/kernel/apic.c @@ -665,7 +665,6 @@ static int __init detect_init_APIC (void) } set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability); mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; - boot_cpu_physical_apicid = 0; if (nmi_watchdog != NMI_NONE) nmi_watchdog = NMI_LOCAL_APIC; @@ -1154,8 +1153,7 @@ int __init APIC_init_uniprocessor (void) connect_bsp_APIC(); - phys_cpu_present_map = 1; - apic_write_around(APIC_ID, boot_cpu_physical_apicid); + phys_cpu_present_map = 1 << boot_cpu_physical_apicid; apic_pm_init2(); diff --git a/arch/i386/kernel/apm.c b/arch/i386/kernel/apm.c index d21b59a85ede..67e9015e6400 100644 --- a/arch/i386/kernel/apm.c +++ b/arch/i386/kernel/apm.c @@ -1096,7 +1096,7 @@ static int apm_engage_power_management(u_short device, int enable) * @blank: on/off * * Attempt to blank the console, firstly by blanking just video device - * zero, and if that fails (some BIOSes dont support it) then it blanks + * zero, and if that fails (some BIOSes don't support it) then it blanks * all video devices. Typically the BIOS will do laptop backlight and * monitor powerdown for us. */ diff --git a/arch/i386/kernel/cpu/amd.c b/arch/i386/kernel/cpu/amd.c index 762a1a8d8c01..fc57a582354e 100644 --- a/arch/i386/kernel/cpu/amd.c +++ b/arch/i386/kernel/cpu/amd.c @@ -151,11 +151,10 @@ static void __init init_amd(struct cpuinfo_x86 *c) case 6: /* An Athlon/Duron */ /* Bit 15 of Athlon specific MSR 15, needs to be 0 - * to enable SSE on Palomino/Morgan CPU's. - * If the BIOS didn't enable it already, enable it - * here. + * to enable SSE on Palomino/Morgan/Barton CPU's. + * If the BIOS didn't enable it already, enable it here. */ - if (c->x86_model == 6 || c->x86_model == 7) { + if (c->x86_model >= 6 && c->x86_model <= 10) { if (!cpu_has(c, X86_FEATURE_XMM)) { printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); rdmsr(MSR_K7_HWCR, l, h); diff --git a/arch/i386/kernel/cpu/centaur.c b/arch/i386/kernel/cpu/centaur.c index 5d6e84590b22..20d4cda0e427 100644 --- a/arch/i386/kernel/cpu/centaur.c +++ b/arch/i386/kernel/cpu/centaur.c @@ -412,8 +412,9 @@ static unsigned int centaur_size_cache(struct cpuinfo_x86 * c, unsigned int size size >>= 8; /* VIA also screwed up Nehemiah stepping 1, and made - it return '65KB' instead of '64KB' */ - if ((c->x86==6) && (c->x86_model==9) && (c->x86_mask==1)) + it return '65KB' instead of '64KB' + - Note, it seems this may only be in engineering samples. */ + if ((c->x86==6) && (c->x86_model==9) && (c->x86_mask==1) && (size==65)) size -=1; return size; diff --git a/arch/i386/kernel/cpu/cpufreq/longrun.c b/arch/i386/kernel/cpu/cpufreq/longrun.c index e7755e874eb9..c86b0c466744 100644 --- a/arch/i386/kernel/cpu/cpufreq/longrun.c +++ b/arch/i386/kernel/cpu/cpufreq/longrun.c @@ -133,7 +133,7 @@ static int longrun_verify_policy(struct cpufreq_policy *policy) * longrun_determine_freqs - determines the lowest and highest possible core frequency * * Determines the lowest and highest possible core frequencies on this CPU. - * This is neccessary to calculate the performance percentage according to + * This is necessary to calculate the performance percentage according to * TMTA rules: * performance_pctg = (target_freq - low_freq)/(high_freq - low_freq) */ diff --git a/arch/i386/kernel/cpu/cyrix.c b/arch/i386/kernel/cpu/cyrix.c index a91dbda9c0db..a09e70fa105a 100644 --- a/arch/i386/kernel/cpu/cyrix.c +++ b/arch/i386/kernel/cpu/cyrix.c @@ -49,7 +49,7 @@ void __init do_cyrix_devid(unsigned char *dir0, unsigned char *dir1) * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in * order to identify the Cyrix CPU model after we're out of setup.c * - * Actually since bugs.h doesnt even reference this perhaps someone should + * Actually since bugs.h doesn't even reference this perhaps someone should * fix the documentation ??? */ static unsigned char Cx86_dir0_msb __initdata = 0; @@ -77,7 +77,7 @@ static char cyrix_model_mult2[] __initdata = "12233445"; * BIOSes for compatibility with DOS games. This makes the udelay loop * work correctly, and improves performance. * - * FIXME: our newer udelay uses the tsc. We dont need to frob with SLOP + * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP */ extern void calibrate_delay(void) __init; diff --git a/arch/i386/kernel/cpu/intel.c b/arch/i386/kernel/cpu/intel.c index 99e34048350a..3bd0a2fa986c 100644 --- a/arch/i386/kernel/cpu/intel.c +++ b/arch/i386/kernel/cpu/intel.c @@ -151,7 +151,7 @@ static void __init init_intel(struct cpuinfo_x86 *c) #ifdef CONFIG_X86_F00F_BUG /* * All current models of Pentium and Pentium with MMX technology CPUs - * have the F0 0F bug, which lets nonpriviledged users lock up the system. + * have the F0 0F bug, which lets nonprivileged users lock up the system. * Note that the workaround only should be initialized once... */ c->f00f_bug = 0; diff --git a/arch/i386/kernel/cpu/mcheck/non-fatal.c b/arch/i386/kernel/cpu/mcheck/non-fatal.c index 57035340e783..9bbb02ba6abc 100644 --- a/arch/i386/kernel/cpu/mcheck/non-fatal.c +++ b/arch/i386/kernel/cpu/mcheck/non-fatal.c @@ -33,7 +33,7 @@ static void mce_checkregs (void *info) rdmsr (MSR_IA32_MC0_STATUS+i*4, low, high); if (high & (1<<31)) { - printk (KERN_EMERG "MCE: The hardware reports a non fatal, correctable incident occured on CPU %d.\n", + printk (KERN_EMERG "MCE: The hardware reports a non fatal, correctable incident occurred on CPU %d.\n", smp_processor_id()); printk (KERN_EMERG "Bank %d: %08x%08x\n", i, high, low); diff --git a/arch/i386/kernel/dmi_scan.c b/arch/i386/kernel/dmi_scan.c index 57495ec0d263..179579a1df20 100644 --- a/arch/i386/kernel/dmi_scan.c +++ b/arch/i386/kernel/dmi_scan.c @@ -440,7 +440,7 @@ static __init int broken_pirq(struct dmi_blacklist *d) { printk(KERN_INFO " *** Possibly defective BIOS detected (irqtable)\n"); printk(KERN_INFO " *** Many BIOSes matching this signature have incorrect IRQ routing tables.\n"); - printk(KERN_INFO " *** If you see IRQ problems, in paticular SCSI resets and hangs at boot\n"); + printk(KERN_INFO " *** If you see IRQ problems, in particular SCSI resets and hangs at boot\n"); printk(KERN_INFO " *** contact your hardware vendor and ask about updates.\n"); printk(KERN_INFO " *** Building an SMP kernel may evade the bug some of the time.\n"); #ifdef CONFIG_X86_IO_APIC diff --git a/arch/i386/kernel/entry.S b/arch/i386/kernel/entry.S index edfb712a2ba0..cd0dd133a572 100644 --- a/arch/i386/kernel/entry.S +++ b/arch/i386/kernel/entry.S @@ -228,7 +228,6 @@ need_resched: #define SYSENTER_RETURN 0xffffe010 # sysenter call handler stub - ALIGN ENTRY(sysenter_entry) sti pushl $(__USER_DS) @@ -271,7 +270,6 @@ ENTRY(sysenter_entry) # system call handler stub - ALIGN ENTRY(system_call) pushl %eax # save orig_eax SAVE_ALL diff --git a/arch/i386/kernel/io_apic.c b/arch/i386/kernel/io_apic.c index 556f2237ee13..7f2892e1e35e 100644 --- a/arch/i386/kernel/io_apic.c +++ b/arch/i386/kernel/io_apic.c @@ -46,7 +46,7 @@ static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED; /* * Is the SiS APIC rmw bug present ? - * -1 = dont know, 0 = no, 1 = yes + * -1 = don't know, 0 = no, 1 = yes */ int sis_apic_bug = -1; @@ -223,7 +223,7 @@ static void set_ioapic_affinity (unsigned int irq, unsigned long mask) extern unsigned long irq_affinity [NR_IRQS]; int __cacheline_aligned pending_irq_balance_apicid [NR_IRQS]; -static int irqbalance_disabled __initdata = 0; +static int irqbalance_disabled = NO_BALANCE_IRQ; static int physical_balance = 0; struct irq_cpu_info { @@ -492,7 +492,7 @@ static inline void balance_irq (int cpu, int irq) unsigned long allowed_mask; unsigned int new_cpu; - if (no_balance_irq) + if (irqbalance_disabled) return; allowed_mask = cpu_online_map & irq_affinity[irq]; diff --git a/arch/i386/kernel/irq.c b/arch/i386/kernel/irq.c index 50025095c075..6760e8f41aa3 100644 --- a/arch/i386/kernel/irq.c +++ b/arch/i386/kernel/irq.c @@ -87,7 +87,7 @@ static void ack_none(unsigned int irq) { /* * 'what should we do if we get a hw irq event on an illegal vector'. - * each architecture has to answer this themselves, it doesnt deserve + * each architecture has to answer this themselves, it doesn't deserve * a generic callback i think. */ #if CONFIG_X86 diff --git a/arch/i386/kernel/nmi.c b/arch/i386/kernel/nmi.c index 682446a5c050..ed31b7804c06 100644 --- a/arch/i386/kernel/nmi.c +++ b/arch/i386/kernel/nmi.c @@ -325,7 +325,7 @@ static spinlock_t nmi_print_lock = SPIN_LOCK_UNLOCKED; * as these watchdog NMI IRQs are generated on every CPU, we only * have to check the current processor. * - * since NMIs dont listen to _any_ locks, we have to be extremely + * since NMIs don't listen to _any_ locks, we have to be extremely * careful not to rely on unsafe variables. The printk might lock * up though, so we have to break up any console locks first ... * [when there will be more tty-related locks, break them up diff --git a/arch/i386/kernel/setup.c b/arch/i386/kernel/setup.c index 37444600d272..ccbb374944b2 100644 --- a/arch/i386/kernel/setup.c +++ b/arch/i386/kernel/setup.c @@ -14,6 +14,9 @@ * Moved CPU detection code to cpu/${cpu}.c * Patrick Mochel <mochel@osdl.org>, March 2002 * + * Provisions for empty E820 memory regions (reported by certain BIOSes). + * Alex Achenbach <xela@slit.de>, December 2002. + * */ /* @@ -279,7 +282,7 @@ static int __init sanitize_e820_map(struct e820entry * biosmap, char * pnr_map) int chgidx, still_changing; int overlap_entries; int new_bios_entry; - int old_nr, new_nr; + int old_nr, new_nr, chg_nr; int i; /* @@ -333,20 +336,24 @@ static int __init sanitize_e820_map(struct e820entry * biosmap, char * pnr_map) for (i=0; i < 2*old_nr; i++) change_point[i] = &change_point_list[i]; - /* record all known change-points (starting and ending addresses) */ + /* record all known change-points (starting and ending addresses), + omitting those that are for empty memory regions */ chgidx = 0; for (i=0; i < old_nr; i++) { - change_point[chgidx]->addr = biosmap[i].addr; - change_point[chgidx++]->pbios = &biosmap[i]; - change_point[chgidx]->addr = biosmap[i].addr + biosmap[i].size; - change_point[chgidx++]->pbios = &biosmap[i]; + if (biosmap[i].size != 0) { + change_point[chgidx]->addr = biosmap[i].addr; + change_point[chgidx++]->pbios = &biosmap[i]; + change_point[chgidx]->addr = biosmap[i].addr + biosmap[i].size; + change_point[chgidx++]->pbios = &biosmap[i]; + } } + chg_nr = chgidx; /* true number of change-points */ /* sort change-point list by memory addresses (low -> high) */ still_changing = 1; while (still_changing) { still_changing = 0; - for (i=1; i < 2*old_nr; i++) { + for (i=1; i < chg_nr; i++) { /* if <current_addr> > <last_addr>, swap */ /* or, if current=<start_addr> & last=<end_addr>, swap */ if ((change_point[i]->addr < change_point[i-1]->addr) || @@ -369,7 +376,7 @@ static int __init sanitize_e820_map(struct e820entry * biosmap, char * pnr_map) last_type = 0; /* start with undefined memory type */ last_addr = 0; /* start with 0 as last starting address */ /* loop through change-points, determining affect on the new bios map */ - for (chgidx=0; chgidx < 2*old_nr; chgidx++) + for (chgidx=0; chgidx < chg_nr; chgidx++) { /* keep track of all overlapping bios entries */ if (change_point[chgidx]->addr == change_point[chgidx]->pbios->addr) @@ -818,7 +825,7 @@ static void __init register_memory(unsigned long max_low_pfn) request_resource(&iomem_resource, res); if (e820.map[i].type == E820_RAM) { /* - * We dont't know which RAM region contains kernel data, + * We don't know which RAM region contains kernel data, * so we try it repeatedly and let the resource manager * test it. */ diff --git a/arch/i386/kernel/smpboot.c b/arch/i386/kernel/smpboot.c index 01259d1f21ad..9068867ab6d3 100644 --- a/arch/i386/kernel/smpboot.c +++ b/arch/i386/kernel/smpboot.c @@ -170,7 +170,7 @@ valid_k7: /* * TSC synchronization. * - * We first check wether all CPUs have their TSC's synchronized, + * We first check whether all CPUs have their TSC's synchronized, * then we print a warning if not, and always resync. */ @@ -956,7 +956,7 @@ static void __init smp_boot_cpus(unsigned int max_cpus) smp_tune_scheduling(); /* - * If we couldnt find an SMP configuration at boot time, + * If we couldn't find an SMP configuration at boot time, * get out of here now! */ if (!smp_found_config) { diff --git a/arch/i386/kernel/srat.c b/arch/i386/kernel/srat.c new file mode 100644 index 000000000000..899dee610170 --- /dev/null +++ b/arch/i386/kernel/srat.c @@ -0,0 +1,448 @@ +/* + * Some of the code in this file has been gleaned from the 64 bit + * discontigmem support code base. + * + * Copyright (C) 2002, IBM Corp. + * + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Send feedback to Pat Gaughen <gone@us.ibm.com> + */ +#include <linux/config.h> +#include <linux/mm.h> +#include <linux/bootmem.h> +#include <linux/mmzone.h> +#include <linux/acpi.h> +#include <asm/srat.h> + +/* + * proximity macros and definitions + */ +#define NODE_ARRAY_INDEX(x) ((x) / 8) /* 8 bits/char */ +#define NODE_ARRAY_OFFSET(x) ((x) % 8) /* 8 bits/char */ +#define BMAP_SET(bmap, bit) ((bmap)[NODE_ARRAY_INDEX(bit)] |= 1 << NODE_ARRAY_OFFSET(bit)) +#define BMAP_TEST(bmap, bit) ((bmap)[NODE_ARRAY_INDEX(bit)] & (1 << NODE_ARRAY_OFFSET(bit))) +#define MAX_PXM_DOMAINS 256 /* 1 byte and no promises about values */ +/* bitmap length; _PXM is at most 255 */ +#define PXM_BITMAP_LEN (MAX_PXM_DOMAINS / 8) +static u8 pxm_bitmap[PXM_BITMAP_LEN]; /* bitmap of proximity domains */ + +#define MAX_CHUNKS_PER_NODE 4 +#define MAXCHUNKS (MAX_CHUNKS_PER_NODE * MAX_NUMNODES) +struct node_memory_chunk_s { + unsigned long start_pfn; + unsigned long end_pfn; + u8 pxm; // proximity domain of node + u8 nid; // which cnode contains this chunk? + u8 bank; // which mem bank on this node +}; +static struct node_memory_chunk_s node_memory_chunk[MAXCHUNKS]; + +static int num_memory_chunks; /* total number of memory chunks */ +static int zholes_size_init; +static unsigned long zholes_size[MAX_NUMNODES * MAX_NR_ZONES]; + +unsigned long node_start_pfn[MAX_NUMNODES]; +unsigned long node_end_pfn[MAX_NUMNODES]; + +extern void * boot_ioremap(unsigned long, unsigned long); + +/* Identify CPU proximity domains */ +static void __init parse_cpu_affinity_structure(char *p) +{ + struct acpi_table_processor_affinity *cpu_affinity = + (struct acpi_table_processor_affinity *) p; + + if (!cpu_affinity->flags.enabled) + return; /* empty entry */ + + /* mark this node as "seen" in node bitmap */ + BMAP_SET(pxm_bitmap, cpu_affinity->proximity_domain); + + printk("CPU 0x%02X in proximity domain 0x%02X\n", + cpu_affinity->apic_id, cpu_affinity->proximity_domain); +} + +/* + * Identify memory proximity domains and hot-remove capabilities. + * Fill node memory chunk list structure. + */ +static void __init parse_memory_affinity_structure (char *sratp) +{ + unsigned long long paddr, size; + unsigned long start_pfn, end_pfn; + u8 pxm; + struct node_memory_chunk_s *p, *q, *pend; + struct acpi_table_memory_affinity *memory_affinity = + (struct acpi_table_memory_affinity *) sratp; + + if (!memory_affinity->flags.enabled) + return; /* empty entry */ + + /* mark this node as "seen" in node bitmap */ + BMAP_SET(pxm_bitmap, memory_affinity->proximity_domain); + + /* calculate info for memory chunk structure */ + paddr = memory_affinity->base_addr_hi; + paddr = (paddr << 32) | memory_affinity->base_addr_lo; + size = memory_affinity->length_hi; + size = (size << 32) | memory_affinity->length_lo; + + start_pfn = paddr >> PAGE_SHIFT; + end_pfn = (paddr + size) >> PAGE_SHIFT; + + pxm = memory_affinity->proximity_domain; + + if (num_memory_chunks >= MAXCHUNKS) { + printk("Too many mem chunks in SRAT. Ignoring %lld MBytes at %llx\n", + size/(1024*1024), paddr); + return; + } + + /* Insertion sort based on base address */ + pend = &node_memory_chunk[num_memory_chunks]; + for (p = &node_memory_chunk[0]; p < pend; p++) { + if (start_pfn < p->start_pfn) + break; + } + if (p < pend) { + for (q = pend; q >= p; q--) + *(q + 1) = *q; + } + p->start_pfn = start_pfn; + p->end_pfn = end_pfn; + p->pxm = pxm; + + num_memory_chunks++; + + printk("Memory range 0x%lX to 0x%lX (type 0x%X) in proximity domain 0x%02X %s\n", + start_pfn, end_pfn, + memory_affinity->memory_type, + memory_affinity->proximity_domain, + (memory_affinity->flags.hot_pluggable ? + "enabled and removable" : "enabled" ) ); +} + +#if MAX_NR_ZONES != 3 +#error "MAX_NR_ZONES != 3, chunk_to_zone requires review" +#endif +/* Take a chunk of pages from page frame cstart to cend and count the number + * of pages in each zone, returned via zones[]. + */ +static __init void chunk_to_zones(unsigned long cstart, unsigned long cend, + unsigned long *zones) +{ + unsigned long max_dma; + extern unsigned long max_low_pfn; + + int z; + unsigned long rend; + + /* FIXME: MAX_DMA_ADDRESS and max_low_pfn are trying to provide + * similarly scoped information and should be handled in a consistant + * manner. + */ + max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT; + + /* Split the hole into the zones in which it falls. Repeatedly + * take the segment in which the remaining hole starts, round it + * to the end of that zone. + */ + memset(zones, 0, MAX_NR_ZONES * sizeof(long)); + while (cstart < cend) { + if (cstart < max_dma) { + z = ZONE_DMA; + rend = (cend < max_dma)? cend : max_dma; + + } else if (cstart < max_low_pfn) { + z = ZONE_NORMAL; + rend = (cend < max_low_pfn)? cend : max_low_pfn; + + } else { + z = ZONE_HIGHMEM; + rend = cend; + } + zones[z] += rend - cstart; + cstart = rend; + } +} + +/* + * physnode_map keeps track of the physical memory layout of the + * numaq nodes on a 256Mb break (each element of the array will + * represent 256Mb of memory and will be marked by the node id. so, + * if the first gig is on node 0, and the second gig is on node 1 + * physnode_map will contain: + * physnode_map[0-3] = 0; + * physnode_map[4-7] = 1; + * physnode_map[8- ] = -1; + */ +int pfnnode_map[MAX_ELEMENTS] = { [0 ... (MAX_ELEMENTS - 1)] = -1}; +EXPORT_SYMBOL(pfnnode_map); + +static void __init initialize_pfnnode_map(void) +{ + unsigned long topofchunk, cur = 0; + int i; + + for (i = 0; i < num_memory_chunks; i++) { + cur = node_memory_chunk[i].start_pfn; + topofchunk = node_memory_chunk[i].end_pfn; + while (cur < topofchunk) { + pfnnode_map[PFN_TO_ELEMENT(cur)] = node_memory_chunk[i].nid; + cur ++; + } + } +} + +/* Parse the ACPI Static Resource Affinity Table */ +static int __init acpi20_parse_srat(struct acpi_table_srat *sratp) +{ + u8 *start, *end, *p; + int i, j, nid; + u8 pxm_to_nid_map[MAX_PXM_DOMAINS];/* _PXM to logical node ID map */ + u8 nid_to_pxm_map[MAX_NUMNODES];/* logical node ID to _PXM map */ + + start = (u8 *)(&(sratp->reserved) + 1); /* skip header */ + p = start; + end = (u8 *)sratp + sratp->header.length; + + memset(pxm_bitmap, 0, sizeof(pxm_bitmap)); /* init proximity domain bitmap */ + memset(node_memory_chunk, 0, sizeof(node_memory_chunk)); + memset(zholes_size, 0, sizeof(zholes_size)); + + /* -1 in these maps means not available */ + memset(pxm_to_nid_map, -1, sizeof(pxm_to_nid_map)); + memset(nid_to_pxm_map, -1, sizeof(nid_to_pxm_map)); + + num_memory_chunks = 0; + while (p < end) { + switch (*p) { + case ACPI_SRAT_PROCESSOR_AFFINITY: + parse_cpu_affinity_structure(p); + break; + case ACPI_SRAT_MEMORY_AFFINITY: + parse_memory_affinity_structure(p); + break; + default: + printk("ACPI 2.0 SRAT: unknown entry skipped: type=0x%02X, len=%d\n", p[0], p[1]); + break; + } + p += p[1]; + if (p[1] == 0) { + printk("acpi20_parse_srat: Entry length value is zero;" + " can't parse any further!\n"); + break; + } + } + + /* Calculate total number of nodes in system from PXM bitmap and create + * a set of sequential node IDs starting at zero. (ACPI doesn't seem + * to specify the range of _PXM values.) + */ + numnodes = 0; /* init total nodes in system */ + for (i = 0; i < MAX_PXM_DOMAINS; i++) { + if (BMAP_TEST(pxm_bitmap, i)) { + pxm_to_nid_map[i] = numnodes; + nid_to_pxm_map[numnodes] = i; + node_set_online(numnodes); + ++numnodes; + } + } + + if (numnodes == 0) + BUG(); + + /* set cnode id in memory chunk structure */ + for (i = 0; i < num_memory_chunks; i++) + node_memory_chunk[i].nid = pxm_to_nid_map[node_memory_chunk[i].pxm]; + + initialize_pfnnode_map(); + + printk("pxm bitmap: "); + for (i = 0; i < sizeof(pxm_bitmap); i++) { + printk("%02X ", pxm_bitmap[i]); + } + printk("\n"); + printk("Number of logical nodes in system = %d\n", numnodes); + printk("Number of memory chunks in system = %d\n", num_memory_chunks); + + for (j = 0; j < num_memory_chunks; j++){ + printk("chunk %d nid %d start_pfn %08lx end_pfn %08lx\n", + j, node_memory_chunk[j].nid, + node_memory_chunk[j].start_pfn, + node_memory_chunk[j].end_pfn); + } + + /*calculate node_start_pfn/node_end_pfn arrays*/ + for (nid = 0; nid < numnodes; nid++) { + int been_here_before = 0; + + for (j = 0; j < num_memory_chunks; j++){ + if (node_memory_chunk[j].nid == nid) { + if (been_here_before == 0) { + node_start_pfn[nid] = node_memory_chunk[j].start_pfn; + node_end_pfn[nid] = node_memory_chunk[j].end_pfn; + been_here_before = 1; + } else { /* We've found another chunk of memory for the node */ + if (node_start_pfn[nid] < node_memory_chunk[j].start_pfn) { + node_end_pfn[nid] = node_memory_chunk[j].end_pfn; + } + } + } + } + } + return 0; +} + +void __init get_memcfg_from_srat(void) +{ + struct acpi_table_header *header = NULL; + struct acpi_table_rsdp *rsdp = NULL; + struct acpi_table_rsdt *rsdt = NULL; + struct acpi_pointer *rsdp_address = NULL; + struct acpi_table_rsdt saved_rsdt; + int tables = 0; + int i = 0; + + acpi_find_root_pointer(ACPI_PHYSICAL_ADDRESSING, rsdp_address); + + if (rsdp_address->pointer_type == ACPI_PHYSICAL_POINTER) { + printk("%s: assigning address to rsdp\n", __FUNCTION__); + rsdp = (struct acpi_table_rsdp *)rsdp_address->pointer.physical; + } else { + printk("%s: rsdp_address is not a physical pointer\n", __FUNCTION__); + return; + } + if (!rsdp) { + printk("%s: Didn't find ACPI root!\n", __FUNCTION__); + return; + } + + printk(KERN_INFO "%.8s v%d [%.6s]\n", rsdp->signature, rsdp->revision, + rsdp->oem_id); + + if (strncmp(rsdp->signature, RSDP_SIG,strlen(RSDP_SIG))) { + printk(KERN_WARNING "%s: RSDP table signature incorrect\n", __FUNCTION__); + return; + } + + rsdt = (struct acpi_table_rsdt *) + boot_ioremap(rsdp->rsdt_address, sizeof(struct acpi_table_rsdt)); + + if (!rsdt) { + printk(KERN_WARNING + "%s: ACPI: Invalid root system description tables (RSDT)\n", + __FUNCTION__); + return; + } + + header = & rsdt->header; + + if (strncmp(header->signature, RSDT_SIG, strlen(RSDT_SIG))) { + printk(KERN_WARNING "ACPI: RSDT signature incorrect\n"); + return; + } + + /* + * The number of tables is computed by taking the + * size of all entries (header size minus total + * size of RSDT) divided by the size of each entry + * (4-byte table pointers). + */ + tables = (header->length - sizeof(struct acpi_table_header)) / 4; + + memcpy(&saved_rsdt, rsdt, sizeof(saved_rsdt)); + + if (saved_rsdt.header.length > sizeof(saved_rsdt)) { + printk(KERN_WARNING "ACPI: Too big length in RSDT: %d\n", + saved_rsdt.header.length); + return; + } + +printk("Begin table scan....\n"); + + for (i = 0; i < tables; i++) { + /* Map in header, then map in full table length. */ + header = (struct acpi_table_header *) + boot_ioremap(saved_rsdt.entry[i], sizeof(struct acpi_table_header)); + if (!header) + break; + header = (struct acpi_table_header *) + boot_ioremap(saved_rsdt.entry[i], header->length); + if (!header) + break; + + if (strncmp((char *) &header->signature, "SRAT", 4)) + continue; + acpi20_parse_srat((struct acpi_table_srat *)header); + /* we've found the srat table. don't need to look at any more tables */ + break; + } +} + +/* For each node run the memory list to determine whether there are + * any memory holes. For each hole determine which ZONE they fall + * into. + * + * NOTE#1: this requires knowledge of the zone boundries and so + * _cannot_ be performed before those are calculated in setup_memory. + * + * NOTE#2: we rely on the fact that the memory chunks are ordered by + * start pfn number during setup. + */ +static void __init get_zholes_init(void) +{ + int nid; + int c; + int first; + unsigned long end = 0; + + for (nid = 0; nid < numnodes; nid++) { + first = 1; + for (c = 0; c < num_memory_chunks; c++){ + if (node_memory_chunk[c].nid == nid) { + if (first) { + end = node_memory_chunk[c].end_pfn; + first = 0; + + } else { + /* Record any gap between this chunk + * and the previous chunk on this node + * against the zones it spans. + */ + chunk_to_zones(end, + node_memory_chunk[c].start_pfn, + &zholes_size[nid * MAX_NR_ZONES]); + } + } + } + } +} + +unsigned long * __init get_zholes_size(int nid) +{ + if (!zholes_size_init) { + zholes_size_init++; + get_zholes_init(); + } + if((nid >= numnodes) | (nid >= MAX_NUMNODES)) + printk("%s: nid = %d is invalid. numnodes = %d", + __FUNCTION__, nid, numnodes); + return &zholes_size[nid * MAX_NR_ZONES]; +} diff --git a/arch/i386/kernel/suspend.c b/arch/i386/kernel/suspend.c index cca0d136f36c..427b387efcf7 100644 --- a/arch/i386/kernel/suspend.c +++ b/arch/i386/kernel/suspend.c @@ -113,7 +113,7 @@ void fix_processor_context(void) int cpu = smp_processor_id(); struct tss_struct * t = init_tss + cpu; - set_tss_desc(cpu,t); /* This just modifies memory; should not be neccessary. But... This is neccessary, because 386 hardware has concept of busy TSS or some similar stupidity. */ + set_tss_desc(cpu,t); /* This just modifies memory; should not be necessary. But... This is necessary, because 386 hardware has concept of busy TSS or some similar stupidity. */ cpu_gdt_table[cpu][GDT_ENTRY_TSS].b &= 0xfffffdff; load_TR_desc(); /* This does ltr */ diff --git a/arch/i386/kernel/time.c b/arch/i386/kernel/time.c index b14b181779f7..79389a99e06f 100644 --- a/arch/i386/kernel/time.c +++ b/arch/i386/kernel/time.c @@ -66,7 +66,7 @@ int pit_latch_buggy; /* extern */ #include "do_timer.h" -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; unsigned long cpu_khz; /* Detected as we calibrate the TSC */ diff --git a/arch/i386/kernel/timers/timer_tsc.c b/arch/i386/kernel/timers/timer_tsc.c index b21a7fbfdc06..aedbefce21e1 100644 --- a/arch/i386/kernel/timers/timer_tsc.c +++ b/arch/i386/kernel/timers/timer_tsc.c @@ -264,7 +264,7 @@ static int init_tsc(void) * the ident/bugs checks so we must run this hook as it * may turn off the TSC flag. * - * NOTE: this doesnt yet handle SMP 486 machines where only + * NOTE: this doesn't yet handle SMP 486 machines where only * some CPU's have a TSC. Thats never worked and nobody has * moaned if you have the only one in the world - you fix it! */ diff --git a/arch/i386/lib/mmx.c b/arch/i386/lib/mmx.c index 8a49853d00de..d6fc84f375e3 100644 --- a/arch/i386/lib/mmx.c +++ b/arch/i386/lib/mmx.c @@ -15,7 +15,7 @@ * (reported so on K6-III) * We should use a better code neutral filler for the short jump * leal ebx. [ebx] is apparently best for K6-2, but Cyrix ?? - * We also want to clobber the filler register so we dont get any + * We also want to clobber the filler register so we don't get any * register forwarding stalls on the filler. * * Add *user handling. Checksums are not a win with MMX on any CPU diff --git a/arch/i386/mach-visws/visws_apic.c b/arch/i386/mach-visws/visws_apic.c index 2c4b5efaf4d4..3d20387637f2 100644 --- a/arch/i386/mach-visws/visws_apic.c +++ b/arch/i386/mach-visws/visws_apic.c @@ -190,7 +190,7 @@ static struct hw_interrupt_type piix4_virtual_irq_type = { * the 'master' interrupt source: CO_IRQ_8259. * * When the 8259 interrupts its handler figures out which of these - * devices is interrupting and dispatches to it's handler. + * devices is interrupting and dispatches to its handler. * * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/ * enable_irq gets the right irq. This 'master' irq is never directly diff --git a/arch/i386/mach-voyager/voyager_smp.c b/arch/i386/mach-voyager/voyager_smp.c index 83f8655f862b..6463639d5b26 100644 --- a/arch/i386/mach-voyager/voyager_smp.c +++ b/arch/i386/mach-voyager/voyager_smp.c @@ -1230,9 +1230,10 @@ flush_tlb_all_function(void* info) void flush_tlb_all(void) { + preempt_disable(); smp_call_function (flush_tlb_all_function, 0, 1, 1); - do_flush_tlb_all_local(); + preempt_enable(); } /* used to set up the trampoline for other CPUs when the memory manager @@ -1453,7 +1454,7 @@ smp_intr_init(void) } /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per - * processor to recieve CPI */ + * processor to receive CPI */ static void send_CPI(__u32 cpuset, __u8 cpi) { diff --git a/arch/i386/mm/Makefile b/arch/i386/mm/Makefile index 183d802bf494..87dd63c9802a 100644 --- a/arch/i386/mm/Makefile +++ b/arch/i386/mm/Makefile @@ -2,8 +2,9 @@ # Makefile for the linux i386-specific parts of the memory manager. # -obj-y := init.o pgtable.o fault.o ioremap.o extable.o pageattr.o +obj-y := init.o pgtable.o fault.o ioremap.o extable.o pageattr.o obj-$(CONFIG_DISCONTIGMEM) += discontig.o obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o obj-$(CONFIG_HIGHMEM) += highmem.o +obj-$(CONFIG_BOOT_IOREMAP) += boot_ioremap.o diff --git a/arch/i386/mm/boot_ioremap.c b/arch/i386/mm/boot_ioremap.c new file mode 100644 index 000000000000..43f66c3ac340 --- /dev/null +++ b/arch/i386/mm/boot_ioremap.c @@ -0,0 +1,94 @@ +/* + * arch/i386/mm/boot_ioremap.c + * + * Re-map functions for early boot-time before paging_init() when the + * boot-time pagetables are still in use + * + * Written by Dave Hansen <haveblue@us.ibm.com> + */ + + +/* + * We need to use the 2-level pagetable functions, but CONFIG_X86_PAE + * keeps that from happenning. If anyone has a better way, I'm listening. + * + * boot_pte_t is defined only if this all works correctly + */ + +#include <linux/config.h> +#undef CONFIG_X86_PAE +#include <asm/page.h> +#include <asm/pgtable.h> +#include <linux/init.h> +#include <linux/stddef.h> + +/* + * I'm cheating here. It is known that the two boot PTE pages are + * allocated next to each other. I'm pretending that they're just + * one big array. + */ + +#define BOOT_PTE_PTRS (PTRS_PER_PTE*2) +#define boot_pte_index(address) \ + (((address) >> PAGE_SHIFT) & (BOOT_PTE_PTRS - 1)) + +static inline boot_pte_t* boot_vaddr_to_pte(void *address) +{ + boot_pte_t* boot_pg = (boot_pte_t*)pg0; + return &boot_pg[boot_pte_index((unsigned long)address)]; +} + +/* + * This is only for a caller who is clever enough to page-align + * phys_addr and virtual_source, and who also has a preference + * about which virtual address from which to steal ptes + */ +static void __boot_ioremap(unsigned long phys_addr, unsigned long nrpages, + void* virtual_source) +{ + boot_pte_t* pte; + int i; + + pte = boot_vaddr_to_pte(virtual_source); + for (i=0; i < nrpages; i++, phys_addr += PAGE_SIZE, pte++) { + set_pte(pte, pfn_pte(phys_addr>>PAGE_SHIFT, PAGE_KERNEL)); + } +} + +/* the virtual space we're going to remap comes from this array */ +#define BOOT_IOREMAP_PAGES 4 +#define BOOT_IOREMAP_SIZE (BOOT_IOREMAP_PAGES*PAGE_SIZE) +__initdata char boot_ioremap_space[BOOT_IOREMAP_SIZE] + __attribute__ ((aligned (PAGE_SIZE))); + +/* + * This only applies to things which need to ioremap before paging_init() + * bt_ioremap() and plain ioremap() are both useless at this point. + * + * When used, we're still using the boot-time pagetables, which only + * have 2 PTE pages mapping the first 8MB + * + * There is no unmap. The boot-time PTE pages aren't used after boot. + * If you really want the space back, just remap it yourself. + * boot_ioremap(&ioremap_space-PAGE_OFFSET, BOOT_IOREMAP_SIZE) + */ +__init void* boot_ioremap(unsigned long phys_addr, unsigned long size) +{ + unsigned long last_addr, offset; + unsigned int nrpages; + + last_addr = phys_addr + size - 1; + + /* page align the requested address */ + offset = phys_addr & ~PAGE_MASK; + phys_addr &= PAGE_MASK; + size = PAGE_ALIGN(last_addr) - phys_addr; + + nrpages = size >> PAGE_SHIFT; + if (nrpages > BOOT_IOREMAP_PAGES) + return NULL; + + __boot_ioremap(phys_addr, nrpages, boot_ioremap_space); + + return &boot_ioremap_space[offset]; +} diff --git a/arch/i386/mm/discontig.c b/arch/i386/mm/discontig.c index ce54c1886dbc..0f136b70678d 100644 --- a/arch/i386/mm/discontig.c +++ b/arch/i386/mm/discontig.c @@ -284,6 +284,7 @@ void __init zone_sizes_init(void) for (nid = 0; nid < numnodes; nid++) { unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0}; + unsigned long *zholes_size; unsigned int max_dma; unsigned long low = max_low_pfn; @@ -307,6 +308,7 @@ void __init zone_sizes_init(void) #endif } } + zholes_size = get_zholes_size(nid); /* * We let the lmem_map for node 0 be allocated from the * normal bootmem allocator, but other nodes come from the @@ -315,10 +317,10 @@ void __init zone_sizes_init(void) if (nid) free_area_init_node(nid, NODE_DATA(nid), node_remap_start_vaddr[nid], zones_size, - start, 0); + start, zholes_size); else free_area_init_node(nid, NODE_DATA(nid), 0, - zones_size, start, 0); + zones_size, start, zholes_size); } return; } diff --git a/arch/i386/mm/hugetlbpage.c b/arch/i386/mm/hugetlbpage.c index 071097273504..6b37833292aa 100644 --- a/arch/i386/mm/hugetlbpage.c +++ b/arch/i386/mm/hugetlbpage.c @@ -29,6 +29,8 @@ static long htlbzone_pages; static LIST_HEAD(htlbpage_freelist); static spinlock_t htlbpage_lock = SPIN_LOCK_UNLOCKED; +void free_huge_page(struct page *page); + static struct page *alloc_hugetlb_page(void) { int i; @@ -45,7 +47,7 @@ static struct page *alloc_hugetlb_page(void) htlbpagemem--; spin_unlock(&htlbpage_lock); set_page_count(page, 1); - page->lru.prev = (void *)huge_page_release; + page->lru.prev = (void *)free_huge_page; for (i = 0; i < (HPAGE_SIZE/PAGE_SIZE); ++i) clear_highpage(&page[i]); return page; diff --git a/arch/i386/mm/ioremap.c b/arch/i386/mm/ioremap.c index 8a6809bd624e..f5ed94a11bce 100644 --- a/arch/i386/mm/ioremap.c +++ b/arch/i386/mm/ioremap.c @@ -205,6 +205,7 @@ void *ioremap_nocache (unsigned long phys_addr, unsigned long size) iounmap(p); p = NULL; } + global_flush_tlb(); } return p; @@ -226,6 +227,7 @@ void iounmap(void *addr) change_page_attr(virt_to_page(__va(p->phys_addr)), p->size >> PAGE_SHIFT, PAGE_KERNEL); + global_flush_tlb(); } kfree(p); } diff --git a/arch/i386/pci/visws.c b/arch/i386/pci/visws.c index 50b8df7dd138..c6b4c17f10fa 100644 --- a/arch/i386/pci/visws.c +++ b/arch/i386/pci/visws.c @@ -52,7 +52,7 @@ static int __init visws_map_irq(struct pci_dev *dev, u8 slot, u8 pin) pin--; - /* Nothing usefull at PIIX4 pin 1 */ + /* Nothing useful at PIIX4 pin 1 */ if (bus == pci_bus0 && slot == 4 && pin == 0) return -1; diff --git a/arch/ia64/ia32/ia32_signal.c b/arch/ia64/ia32/ia32_signal.c index de4213cf1a5a..6715c8ad2456 100644 --- a/arch/ia64/ia32/ia32_signal.c +++ b/arch/ia64/ia32/ia32_signal.c @@ -338,7 +338,7 @@ restore_ia32_fpstate_live (struct _fpstate_ia32 *save) /* * Updating fsr, fcr, fir, fdr. * Just a bit more complicated than save. - * - Need to make sure that we dont write any value other than the + * - Need to make sure that we don't write any value other than the * specific fpstate info * - Need to make sure that the untouched part of frs, fdr, fir, fcr * should remain same while writing. diff --git a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c index 91ac80986823..a35b32f48655 100644 --- a/arch/ia64/kernel/irq.c +++ b/arch/ia64/kernel/irq.c @@ -104,7 +104,7 @@ static void ack_none(unsigned int irq) { /* * 'what should we do if we get a hw irq event on an illegal vector'. - * each architecture has to answer this themselves, it doesnt deserve + * each architecture has to answer this themselves, it doesn't deserve * a generic callback i think. */ #if CONFIG_X86 diff --git a/arch/ia64/kernel/minstate.h b/arch/ia64/kernel/minstate.h index ed1d91daafac..800c929e93d4 100644 --- a/arch/ia64/kernel/minstate.h +++ b/arch/ia64/kernel/minstate.h @@ -26,7 +26,7 @@ */ /* - * For ivt.s we want to access the stack virtually so we dont have to disable translation + * For ivt.s we want to access the stack virtually so we don't have to disable translation * on interrupts. */ #define MINSTATE_START_SAVE_MIN_VIRT \ @@ -52,7 +52,7 @@ /* * For mca_asm.S we want to access the stack physically since the state is saved before we - * go virtual and dont want to destroy the iip or ipsr. + * go virtual and don't want to destroy the iip or ipsr. */ #define MINSTATE_START_SAVE_MIN_PHYS \ (pKStk) movl sp=ia64_init_stack+IA64_STK_OFFSET-IA64_PT_REGS_SIZE; \ diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c index 4a63c27ac26d..9dfd3968dd64 100644 --- a/arch/ia64/kernel/perfmon.c +++ b/arch/ia64/kernel/perfmon.c @@ -718,7 +718,7 @@ pfm_remap_buffer(struct vm_area_struct *vma, unsigned long buf, unsigned long ad /* * counts the number of PMDS to save per entry. - * This code is generic enough to accomodate more than 64 PMDS when they become available + * This code is generic enough to accommodate more than 64 PMDS when they become available */ static unsigned long pfm_smpl_entry_size(unsigned long *which, unsigned long size) diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c index b85fe8b701b2..bf603c142328 100644 --- a/arch/ia64/kernel/time.c +++ b/arch/ia64/kernel/time.c @@ -27,7 +27,7 @@ extern unsigned long wall_jiffies; extern unsigned long last_time_offset; -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; #ifdef CONFIG_IA64_DEBUG_IRQ diff --git a/arch/ia64/lib/checksum.c b/arch/ia64/lib/checksum.c index c642c346adb3..f4b64765ecbf 100644 --- a/arch/ia64/lib/checksum.c +++ b/arch/ia64/lib/checksum.c @@ -50,7 +50,7 @@ csum_tcpudp_nofold (unsigned long saddr, unsigned long daddr, unsigned short len ((unsigned long) ntohs(len) << 16) + ((unsigned long) proto << 8)); - /* Fold down to 32-bits so we don't loose in the typedef-less network stack. */ + /* Fold down to 32-bits so we don't lose in the typedef-less network stack. */ /* 64 to 33 */ result = (result & 0xffffffff) + (result >> 32); /* 33 to 32 */ diff --git a/arch/ia64/lib/do_csum.S b/arch/ia64/lib/do_csum.S index 5eed93665a40..c3bc67df7f7b 100644 --- a/arch/ia64/lib/do_csum.S +++ b/arch/ia64/lib/do_csum.S @@ -41,7 +41,7 @@ // into one 8 byte word. In this case we have only one entry in the pipeline. // // We use a (LOAD_LATENCY+2)-stage pipeline in the loop to account for -// possible load latency and also to accomodate for head and tail. +// possible load latency and also to accommodate for head and tail. // // The end of the function deals with folding the checksum from 64bits // down to 16bits taking care of the carry. diff --git a/arch/ia64/lib/swiotlb.c b/arch/ia64/lib/swiotlb.c index f390da81d018..52a9df383b22 100644 --- a/arch/ia64/lib/swiotlb.c +++ b/arch/ia64/lib/swiotlb.c @@ -359,7 +359,7 @@ mark_clean (void *addr, size_t size) * was provided for in a previous swiotlb_map_single call. All other usages are * undefined. * - * After this call, reads by the cpu to the buffer are guarenteed to see whatever the + * After this call, reads by the cpu to the buffer are guaranteed to see whatever the * device wrote there. */ void diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c index f855cb69db21..e39bd20123a7 100644 --- a/arch/ia64/mm/discontig.c +++ b/arch/ia64/mm/discontig.c @@ -241,7 +241,7 @@ discontig_mem_init(void) * - build the nodedir for the node. This contains pointers to * the per-bank mem_map entries. * - fix the page struct "virtual" pointers. These are bank specific - * values that the paging system doesnt understand. + * values that the paging system doesn't understand. * - replicate the nodedir structure to other nodes */ diff --git a/arch/ia64/mm/hugetlbpage.c b/arch/ia64/mm/hugetlbpage.c index c71ed65b5a2d..44b2f0cfd148 100644 --- a/arch/ia64/mm/hugetlbpage.c +++ b/arch/ia64/mm/hugetlbpage.c @@ -26,6 +26,8 @@ static long htlbzone_pages; static LIST_HEAD(htlbpage_freelist); static spinlock_t htlbpage_lock = SPIN_LOCK_UNLOCKED; +void free_huge_page(struct page *page); + static struct page *alloc_hugetlb_page(void) { int i; @@ -42,6 +44,7 @@ static struct page *alloc_hugetlb_page(void) htlbpagemem--; spin_unlock(&htlbpage_lock); set_page_count(page, 1); + page->lru.prev = (void *)free_huge_page; for (i = 0; i < (HPAGE_SIZE/PAGE_SIZE); ++i) clear_highpage(&page[i]); return page; diff --git a/arch/ia64/sn/fakeprom/fpmem.c b/arch/ia64/sn/fakeprom/fpmem.c index 041bf851ef0f..2c58cd9a1884 100644 --- a/arch/ia64/sn/fakeprom/fpmem.c +++ b/arch/ia64/sn/fakeprom/fpmem.c @@ -218,7 +218,7 @@ build_efi_memmap(void *md, int mdsize) } /* - * Check for the node 0 hole. Since banks cant + * Check for the node 0 hole. Since banks can't * span the hole, we only need to check if the end of * the range is the end of the hole. */ @@ -226,7 +226,7 @@ build_efi_memmap(void *md, int mdsize) numbytes -= NODE0_HOLE_SIZE; /* * UGLY hack - we must skip overr the kernel and - * PROM runtime services but we dont exactly where it is. + * PROM runtime services but we don't exactly where it is. * So lets just reserve: * node 0 * 0-1MB for PAL diff --git a/arch/ia64/sn/fakeprom/fw-emu.c b/arch/ia64/sn/fakeprom/fw-emu.c index 8ba4632dbb33..792abb0a59b9 100644 --- a/arch/ia64/sn/fakeprom/fw-emu.c +++ b/arch/ia64/sn/fakeprom/fw-emu.c @@ -757,7 +757,7 @@ sys_fw_init (const char *args, int arglen, int bsp) sal_systab->checksum = -checksum; /* If the checksum is correct, the kernel tries to use the - * table. We dont build enough table & the kernel aborts. + * table. We don't build enough table & the kernel aborts. * Note that the PROM hasd thhhe same problem!! */ diff --git a/arch/ia64/sn/io/hcl.c b/arch/ia64/sn/io/hcl.c index 22d8dda7309b..a8b8b98a6f81 100644 --- a/arch/ia64/sn/io/hcl.c +++ b/arch/ia64/sn/io/hcl.c @@ -467,7 +467,7 @@ hwgraph_register(devfs_handle_t de, const char *name, /* * We need to clean up! */ - printk(KERN_WARNING "HCL: Unable to set the connect point to it's parent 0x%p\n", + printk(KERN_WARNING "HCL: Unable to set the connect point to its parent 0x%p\n", (void *)new_devfs_handle); } diff --git a/arch/ia64/sn/io/sn1/pcibr.c b/arch/ia64/sn/io/sn1/pcibr.c index 6029f26613fe..92594ce11da6 100644 --- a/arch/ia64/sn/io/sn1/pcibr.c +++ b/arch/ia64/sn/io/sn1/pcibr.c @@ -2647,7 +2647,7 @@ pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl, /* * The Adaptec 1160 FC Controller WAR #767995: * The part incorrectly ignores the upper 32 bits of a 64 bit - * address when decoding references to it's registers so to + * address when decoding references to its registers so to * keep it from responding to a bus cycle that it shouldn't * we only use I/O space to get at it's registers. Don't * enable memory space accesses on that PCI device. @@ -5113,7 +5113,7 @@ ate_freeze(pcibr_dmamap_t pcibr_dmamap, /* Bridge Hardware Bug WAR #484930: * Bridge can't handle updating External ATEs - * while DMA is occuring that uses External ATEs, + * while DMA is occurring that uses External ATEs, * even if the particular ATEs involved are disjoint. */ @@ -6844,7 +6844,7 @@ pcibr_xintr_preset(void *which_widget, * * This is the pcibr interrupt "wrapper" function that is called, * in interrupt context, to initiate the interrupt handler(s) registered - * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded + * (via pcibr_intr_alloc/connect) for the occurring interrupt. Non-threaded * handlers will be called directly, and threaded handlers will have their * thread woken up. */ diff --git a/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c index a2d2ff2cab0b..5b8460ee01d1 100644 --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c @@ -362,7 +362,7 @@ ate_freeze(pcibr_dmamap_t pcibr_dmamap, /* Bridge Hardware Bug WAR #484930: * Bridge can't handle updating External ATEs - * while DMA is occuring that uses External ATEs, + * while DMA is occurring that uses External ATEs, * even if the particular ATEs involved are disjoint. */ diff --git a/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c index b4ebde013027..9b2ce991d5f1 100644 --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c @@ -849,7 +849,7 @@ pcibr_device_info_new( * will set the c_slot (which is suppose to represent the external * slot (i.e the slot number silk screened on the back of the I/O * brick)). So for PIC we need to adjust this "internal slot" num - * passed into us, into it's external representation. See comment + * passed into us, into its external representation. See comment * for the PCIBR_DEVICE_TO_SLOT macro for more information. */ NEW(pcibr_info); @@ -1527,7 +1527,7 @@ pcibr_attach2(devfs_handle_t xconn_vhdl, bridge_t *bridge, /* enable parity checking on PICs internal RAM */ pic_ctrl_reg |= PIC_CTRL_PAR_EN_RESP; pic_ctrl_reg |= PIC_CTRL_PAR_EN_ATE; - /* PIC BRINGUP WAR (PV# 862253): dont enable write request + /* PIC BRINGUP WAR (PV# 862253): don't enable write request * parity checking. */ if (!PCIBR_WAR_ENABLED(PV862253, pcibr_soft)) { diff --git a/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c index 857c98abe97a..4295a33e916d 100644 --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c @@ -1806,7 +1806,7 @@ pcibr_pioerror( * * CAUTION: Resetting bit BRIDGE_IRR_PCI_GRP_CLR, acknowledges * a group of interrupts. If while handling this error, - * some other error has occured, that would be + * some other error has occurred, that would be * implicitly cleared by this write. * Need a way to ensure we don't inadvertently clear some * other errors. diff --git a/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c index 01324f3511db..22b679e9d8ab 100644 --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c @@ -842,7 +842,7 @@ printk("pcibr_xintr_preset: b_wid_int_upper 0x%lx b_wid_int_lower 0x%lx b_int_ho * * This is the pcibr interrupt "wrapper" function that is called, * in interrupt context, to initiate the interrupt handler(s) registered - * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded + * (via pcibr_intr_alloc/connect) for the occurring interrupt. Non-threaded * handlers will be called directly, and threaded handlers will have their * thread woken up. */ diff --git a/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c index 3f9735725182..3d3fda15c7b3 100644 --- a/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c +++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c @@ -803,7 +803,7 @@ pcibr_slot_info_init(devfs_handle_t pcibr_vhdl, * 'min_gnt' and attempt to calculate a latency time. * * NOTE: For now if the device is on the 'real time' arbitration - * ring we dont set the latency timer. + * ring we don't set the latency timer. * * WAR: SGI's IOC3 and RAD devices target abort if you write a * single byte into their config space. So don't set the Latency @@ -852,7 +852,7 @@ pcibr_slot_info_init(devfs_handle_t pcibr_vhdl, } /* Get the PCI-X capability if running in PCI-X mode. If the func - * doesnt have a pcix capability, allocate a PCIIO_VENDOR_ID_NONE + * doesn't have a pcix capability, allocate a PCIIO_VENDOR_ID_NONE * pcibr_info struct so the device driver for that function is not * called. */ @@ -1449,7 +1449,7 @@ pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl, /* * The Adaptec 1160 FC Controller WAR #767995: * The part incorrectly ignores the upper 32 bits of a 64 bit - * address when decoding references to it's registers so to + * address when decoding references to its registers so to * keep it from responding to a bus cycle that it shouldn't * we only use I/O space to get at it's registers. Don't * enable memory space accesses on that PCI device. diff --git a/arch/ia64/sn/kernel/llsc4.c b/arch/ia64/sn/kernel/llsc4.c index bc4ba40372f2..38373739789d 100644 --- a/arch/ia64/sn/kernel/llsc4.c +++ b/arch/ia64/sn/kernel/llsc4.c @@ -301,7 +301,7 @@ ran_conf_llsc(int thread) */ linei = randn(linecount, &seed); sharei = randn(2, &seed); - slinei = (linei + (linecount/2))%linecount; /* I dont like this - fix later */ + slinei = (linei + (linecount/2))%linecount; /* I don't like this - fix later */ linep = (dataline_t *)blocks[linei]; slinep = (dataline_t *)blocks[slinei]; diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c index fab2d66140ca..f35daeb1b7ab 100644 --- a/arch/ia64/sn/kernel/setup.c +++ b/arch/ia64/sn/kernel/setup.c @@ -153,7 +153,7 @@ sn_map_nr (unsigned long addr) /** * early_sn_setup - early setup routine for SN platforms * - * Sets up an intial console to aid debugging. Intended primarily + * Sets up an initial console to aid debugging. Intended primarily * for bringup, it's only called if %BRINGUP and %CONFIG_IA64_EARLY_PRINTK * are turned on. See start_kernel() in init/main.c. */ @@ -172,7 +172,7 @@ early_sn_setup(void) /* * Parse enough of the SAL tables to locate the SAL entry point. Since, console - * IO on SN2 is done via SAL calls, early_printk wont work without this. + * IO on SN2 is done via SAL calls, early_printk won't work without this. * * This code duplicates some of the ACPI table parsing that is in efi.c & sal.c. * Any changes to those file may have to be made hereas well. diff --git a/arch/ia64/sn/kernel/sn1/sn1_smp.c b/arch/ia64/sn/kernel/sn1/sn1_smp.c index affeb952350f..e24f97eba657 100644 --- a/arch/ia64/sn/kernel/sn1/sn1_smp.c +++ b/arch/ia64/sn/kernel/sn1/sn1_smp.c @@ -100,7 +100,7 @@ extern void smp_send_flush_tlb (void) __attribute((weak)); /* * The following table/struct is for remembering PTC coherency domains. It - * is also used to translate sapicid into cpuids. We dont want to start + * is also used to translate sapicid into cpuids. We don't want to start * cpus unless we know their cache domain. */ #ifdef PTC_NOTYET diff --git a/arch/ia64/sn/kernel/sn2/sn2_smp.c b/arch/ia64/sn/kernel/sn2/sn2_smp.c index e0182d31d13d..1850229970c1 100644 --- a/arch/ia64/sn/kernel/sn2/sn2_smp.c +++ b/arch/ia64/sn/kernel/sn2/sn2_smp.c @@ -395,7 +395,7 @@ sn2_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbit mycnode = local_nodeid; /* - * For now, we dont want to spin uninterruptibly waiting + * For now, we don't want to spin uninterruptibly waiting * for the lock. Makes hangs hard to debug. */ local_irq_save(flags); @@ -506,7 +506,7 @@ sn_send_IPI_phys(long physid, int vector, int delivery_mode) pio_phys_write_mmr(p, val); #ifndef CONFIG_SHUB_1_0_SPECIFIC - /* doesnt work on shub 1.0 */ + /* doesn't work on shub 1.0 */ wait_piowc(); #endif } diff --git a/arch/m68k/ifpsp060/src/fpsp.S b/arch/m68k/ifpsp060/src/fpsp.S index 3dab89211bb1..73805f8304bf 100644 --- a/arch/m68k/ifpsp060/src/fpsp.S +++ b/arch/m68k/ifpsp060/src/fpsp.S @@ -2201,7 +2201,7 @@ fu_snan_s_p: mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) -# now, we copy the default result to it's proper location +# now, we copy the default result to its proper location mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) @@ -2241,7 +2241,7 @@ fu_operr_p_s: mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) -# now, we copy the default result to it's proper location +# now, we copy the default result to its proper location mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) @@ -2281,7 +2281,7 @@ fu_inex_s_p2: mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) -# now, we copy the default result to it's proper location +# now, we copy the default result to its proper location mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) diff --git a/arch/m68k/ifpsp060/src/isp.S b/arch/m68k/ifpsp060/src/isp.S index 4f29187c29aa..5a1e6fdc5c90 100644 --- a/arch/m68k/ifpsp060/src/isp.S +++ b/arch/m68k/ifpsp060/src/isp.S @@ -843,7 +843,7 @@ isp_acc_exit2: bra.l _real_access # if the addressing mode was (an)+ or -(an), the address register must -# be restored to it's pre-exception value before entering _real_access. +# be restored to its pre-exception value before entering _real_access. isp_restore: cmpi.b SPCOND_FLG(%a6),&restore_flg # do we need a restore? bne.b isp_restore_done # no diff --git a/arch/m68k/ifpsp060/src/pfpsp.S b/arch/m68k/ifpsp060/src/pfpsp.S index acc45c58c084..fbf9d6448315 100644 --- a/arch/m68k/ifpsp060/src/pfpsp.S +++ b/arch/m68k/ifpsp060/src/pfpsp.S @@ -2200,7 +2200,7 @@ fu_snan_s_p: mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) -# now, we copy the default result to it's proper location +# now, we copy the default result to its proper location mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) @@ -2240,7 +2240,7 @@ fu_operr_p_s: mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) -# now, we copy the default result to it's proper location +# now, we copy the default result to its proper location mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) @@ -2280,7 +2280,7 @@ fu_inex_s_p2: mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp) mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp) -# now, we copy the default result to it's proper location +# now, we copy the default result to its proper location mov.l LOCAL_SIZE+FP_DST_EX(%sp),LOCAL_SIZE+0x4(%sp) mov.l LOCAL_SIZE+FP_DST_HI(%sp),LOCAL_SIZE+0x8(%sp) mov.l LOCAL_SIZE+FP_DST_LO(%sp),LOCAL_SIZE+0xc(%sp) diff --git a/arch/m68k/kernel/head.S b/arch/m68k/kernel/head.S index a2ee7f8b4b3c..bbeeb3c4e744 100644 --- a/arch/m68k/kernel/head.S +++ b/arch/m68k/kernel/head.S @@ -3127,7 +3127,7 @@ func_start serial_putc,%d0/%d1/%a0/%a1 moveb %d0,M162_SCC_CTRL_A jra 3f 5: - /* 166/167/177; its a CD2401 */ + /* 166/167/177; it's a CD2401 */ moveb #0,M167_CYCAR moveb M167_CYIER,%d2 moveb #0x02,M167_CYIER diff --git a/arch/m68k/kernel/time.c b/arch/m68k/kernel/time.c index 03a38781e59e..ecae7f16d614 100644 --- a/arch/m68k/kernel/time.c +++ b/arch/m68k/kernel/time.c @@ -26,7 +26,7 @@ #include <linux/timex.h> #include <linux/profile.h> -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; static inline int set_rtc_mmss(unsigned long nowtime) { diff --git a/arch/m68k/math-emu/fp_util.S b/arch/m68k/math-emu/fp_util.S index 12e1e7863e1e..efe7981939a7 100644 --- a/arch/m68k/math-emu/fp_util.S +++ b/arch/m68k/math-emu/fp_util.S @@ -49,7 +49,7 @@ * is currently at that time unused, be careful if you want change * something here. %d0 and %d1 is always usable, sometimes %d2 (or * only the lower half) most function have to return the %a0 - * unmodified, so that the caller can immediatly reuse it. + * unmodified, so that the caller can immediately reuse it. */ .globl fp_ill, fp_end diff --git a/arch/m68k/q40/README b/arch/m68k/q40/README index 8bab59512ddf..79a46b054d00 100644 --- a/arch/m68k/q40/README +++ b/arch/m68k/q40/README @@ -16,7 +16,7 @@ For a list of kernel command-line options read the documentation for the particular device drivers. The floppy imposes a very high interrupt load on the CPU, approx 30K/s. -When something blocks interrupts (HD) it will loose some of them, so far +When something blocks interrupts (HD) it will lose some of them, so far this is not known to have caused any data loss. On highly loaded systems it can make the floppy very slow or practically stop. Other Q40 OS' simply poll the floppy for this reason - something that can't be done in Linux. diff --git a/arch/m68k/sun3/config.c b/arch/m68k/sun3/config.c index 2c21cfb5337f..caf8a22d2498 100644 --- a/arch/m68k/sun3/config.c +++ b/arch/m68k/sun3/config.c @@ -119,7 +119,7 @@ void __init sun3_bootmem_alloc(unsigned long memory_start, unsigned long memory_ { unsigned long start_page; - /* align start/end to page boundries */ + /* align start/end to page boundaries */ memory_start = ((memory_start + (PAGE_SIZE-1)) & PAGE_MASK); memory_end = memory_end & PAGE_MASK; diff --git a/arch/m68knommu/kernel/ints.c b/arch/m68knommu/kernel/ints.c index f7a8eda2522d..290ad865b556 100644 --- a/arch/m68knommu/kernel/ints.c +++ b/arch/m68knommu/kernel/ints.c @@ -214,7 +214,7 @@ void sys_free_irq(unsigned int irq, void *dev_id) /* * Do we need these probe functions on the m68k? * - * ... may be usefull with ISA devices + * ... may be useful with ISA devices */ unsigned long probe_irq_on (void) { diff --git a/arch/m68knommu/kernel/syscalltable.S b/arch/m68knommu/kernel/syscalltable.S index 7e50085c2840..43f1413494fa 100644 --- a/arch/m68knommu/kernel/syscalltable.S +++ b/arch/m68knommu/kernel/syscalltable.S @@ -14,6 +14,7 @@ #include <linux/config.h> #include <linux/sys.h> #include <linux/linkage.h> +#include <asm/unistd.h> .text ALIGN diff --git a/arch/m68knommu/kernel/time.c b/arch/m68knommu/kernel/time.c index c12fb4af61fc..4f7e59167293 100644 --- a/arch/m68knommu/kernel/time.c +++ b/arch/m68knommu/kernel/time.c @@ -26,7 +26,7 @@ #define TICK_SIZE (tick_nsec / 1000) -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; static inline int set_rtc_mmss(unsigned long nowtime) { diff --git a/arch/m68knommu/platform/5307/entry.S b/arch/m68knommu/platform/5307/entry.S index 026871952fa1..2ea3f741e2b4 100644 --- a/arch/m68knommu/platform/5307/entry.S +++ b/arch/m68knommu/platform/5307/entry.S @@ -27,6 +27,7 @@ #include <linux/config.h> #include <linux/sys.h> #include <linux/linkage.h> +#include <asm/unistd.h> #include <asm/thread_info.h> #include <asm/errno.h> #include <asm/setup.h> diff --git a/arch/m68knommu/platform/5307/vectors.c b/arch/m68knommu/platform/5307/vectors.c index 01fd2ecd2f58..6c0813d203d7 100644 --- a/arch/m68knommu/platform/5307/vectors.c +++ b/arch/m68knommu/platform/5307/vectors.c @@ -13,6 +13,7 @@ #include <linux/sched.h> #include <linux/param.h> #include <linux/init.h> +#include <linux/unistd.h> #include <asm/irq.h> #include <asm/dma.h> #include <asm/traps.h> diff --git a/arch/m68knommu/platform/68360/ints.c b/arch/m68knommu/platform/68360/ints.c index c209d406cb99..7885623f2d5c 100644 --- a/arch/m68knommu/platform/68360/ints.c +++ b/arch/m68knommu/platform/68360/ints.c @@ -291,7 +291,7 @@ void M68360_do_irq(int vec, struct pt_regs *fp) /* unsigned long pend = *(volatile unsigned long *)pquicc->intr_cipr; */ - /* Bugger all that wierdness. For the moment, I seem to know where I came from; + /* Bugger all that weirdness. For the moment, I seem to know where I came from; * vec is passed from a specific ISR, so I'll use it. */ if (int_irq_list[irq] && int_irq_list[irq]->handler) { diff --git a/arch/mips/au1000/common/serial.c b/arch/mips/au1000/common/serial.c index 64d0ae0299ed..84a926570f13 100644 --- a/arch/mips/au1000/common/serial.c +++ b/arch/mips/au1000/common/serial.c @@ -2703,7 +2703,7 @@ static int __init rs_init(void) * port exists and is in use an error is returned. If the port * is not currently in the table it is added. * - * The port is then probed and if neccessary the IRQ is autodetected + * The port is then probed and if necessary the IRQ is autodetected * If this fails an error is returned. * * On success the port is ready to use and the line number is returned. diff --git a/arch/mips/baget/wbflush.c b/arch/mips/baget/wbflush.c index 64c60bc7100f..db3308a3b3de 100644 --- a/arch/mips/baget/wbflush.c +++ b/arch/mips/baget/wbflush.c @@ -17,7 +17,7 @@ void __init wbflush_setup(void) } /* - * Baget/MIPS doesnt need to write back the WB. + * Baget/MIPS doesn't need to write back the WB. */ static void wbflush_baget(void) { diff --git a/arch/mips/ddb5xxx/common/pci.c b/arch/mips/ddb5xxx/common/pci.c index 17aeea278804..5c1e07f6edbb 100644 --- a/arch/mips/ddb5xxx/common/pci.c +++ b/arch/mips/ddb5xxx/common/pci.c @@ -20,7 +20,7 @@ * Strategies: * * . We rely on pci_auto.c file to assign PCI resources (MEM and IO) - * TODO: this shold be optional for some machines where they do have + * TODO: this should be optional for some machines where they do have * a real "pcibios" that does resource assignment. * * . We then use pci_scan_bus() to "discover" all the resources for diff --git a/arch/mips/dec/boot/decstation.c b/arch/mips/dec/boot/decstation.c index b8f8c2e05728..f7e3dc36656d 100644 --- a/arch/mips/dec/boot/decstation.c +++ b/arch/mips/dec/boot/decstation.c @@ -70,7 +70,7 @@ void dec_entry(int argc, char **argv, #ifdef RELOC /* - * Now copy kernel image to it's destination. + * Now copy kernel image to its destination. */ len = ((unsigned long) (&_end) - k_start); memcpy((void *)k_start, &_ftext, len); diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 446f28d33c7f..cf6fb793e8e0 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -44,7 +44,7 @@ static void ack_none(unsigned int irq) { /* * 'what should we do if we get a hw irq event on an illegal vector'. - * each architecture has to answer this themselves, it doesnt deserve + * each architecture has to answer this themselves, it doesn't deserve * a generic callback i think. */ printk("unexpected interrupt %d\n", irq); diff --git a/arch/mips/kernel/pci.c b/arch/mips/kernel/pci.c index e13151386427..81aea7026fa2 100644 --- a/arch/mips/kernel/pci.c +++ b/arch/mips/kernel/pci.c @@ -19,7 +19,7 @@ * Strategies: * * . We rely on pci_auto.c file to assign PCI resources (MEM and IO) - * TODO: this shold be optional for some machines where they do have + * TODO: this should be optional for some machines where they do have * a real "pcibios" that does resource assignment. * * . We then use pci_scan_bus() to "discover" all the resources for diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c index a775854fd64c..2511f9d4f630 100644 --- a/arch/mips/kernel/process.c +++ b/arch/mips/kernel/process.c @@ -112,7 +112,7 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp, p->thread.reg31 = (unsigned long) ret_from_fork; /* - * New tasks loose permission to use the fpu. This accelerates context + * New tasks lose permission to use the fpu. This accelerates context * switching for most programs since they don't use the fpu. */ p->thread.cp0_status = read_32bit_cp0_register(CP0_STATUS) & diff --git a/arch/mips/kernel/r2300_misc.S b/arch/mips/kernel/r2300_misc.S index 30031e295b8d..8ef3683f983d 100644 --- a/arch/mips/kernel/r2300_misc.S +++ b/arch/mips/kernel/r2300_misc.S @@ -76,7 +76,7 @@ /* Check is PTE is present, if not then jump to LABEL. * PTR points to the page table where this PTE is located, * when the macro is done executing PTE will be restored - * with it's original value. + * with its original value. */ #define PTE_PRESENT(pte, ptr, label) \ andi pte, pte, (_PAGE_PRESENT | _PAGE_READ); \ diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S index 973dbb271da7..aefdff8645e7 100644 --- a/arch/mips/kernel/r2300_switch.S +++ b/arch/mips/kernel/r2300_switch.S @@ -80,7 +80,7 @@ LEAF(lazy_fpu_switch) beqz a0, 2f # Save floating point state nor t3, zero, t3 .set reorder - lw t1, ST_OFF(a0) # last thread looses fpu + lw t1, ST_OFF(a0) # last thread loses fpu and t1, t3 sw t1, ST_OFF(a0) FPU_SAVE_SINGLE(a0, t1) # clobbers t1 @@ -108,7 +108,7 @@ LEAF(restore_fp) /* * Load the FPU with signalling NANS. This bit pattern we're using has - * the property that no matter wether considered as single or as double + * the property that no matter whether considered as single or as double * precission represents signaling NANS. * * We initialize fcr31 to rounding to nearest, no exceptions. diff --git a/arch/mips/kernel/r4k_misc.S b/arch/mips/kernel/r4k_misc.S index e16820f889c0..510b08ca9d16 100644 --- a/arch/mips/kernel/r4k_misc.S +++ b/arch/mips/kernel/r4k_misc.S @@ -93,7 +93,7 @@ /* Check is PTE is present, if not then jump to LABEL. * PTR points to the page table where this PTE is located, * when the macro is done executing PTE will be restored - * with it's original value. + * with its original value. */ #define PTE_PRESENT(pte, ptr, label) \ andi pte, pte, (_PAGE_PRESENT | _PAGE_READ); \ diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index c455538a9ebe..18d5ae71abe3 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S @@ -85,7 +85,7 @@ LEAF(lazy_fpu_switch) beqz a0, 2f # Save floating point state nor t3, zero, t3 - lw t1, ST_OFF(a0) # last thread looses fpu + lw t1, ST_OFF(a0) # last thread loses fpu and t1, t3 sw t1, ST_OFF(a0) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 30634e314992..26a70f6d1a13 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -775,7 +775,7 @@ void __init setup_arch(char **cmdline_p) request_resource(&iomem_resource, res); /* - * We dont't know which RAM region contains kernel data, + * We don't know which RAM region contains kernel data, * so we try it repeatedly and let the resource manager * test it. */ diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 6adf09fdf6ad..f7551d197dfb 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -32,7 +32,7 @@ #define USECS_PER_JIFFY (1000000/HZ) #define USECS_PER_JIFFY_FRAC ((1000000ULL << 32) / HZ & 0xffffffff) -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; /* * forward reference diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 5a25242b368d..ea3d490934f0 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -793,7 +793,7 @@ void __init trap_init(void) /* Some firmware leaves the BEV flag set, clear it. */ clear_cp0_status(ST0_BEV); - /* Copy the generic exception handler code to it's final destination. */ + /* Copy the generic exception handler code to its final destination. */ memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80); memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80); memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80); @@ -805,7 +805,7 @@ void __init trap_init(void) set_except_vector(i, handle_reserved); /* - * Copy the EJTAG debug exception vector handler code to it's final + * Copy the EJTAG debug exception vector handler code to its final * destination. */ memcpy((void *)(KSEG0 + 0x300), &except_vec_ejtag_debug, 0x80); diff --git a/arch/mips/math-emu/dp_add.c b/arch/mips/math-emu/dp_add.c index 5a3158bbbc26..0c96f9b39de9 100644 --- a/arch/mips/math-emu/dp_add.c +++ b/arch/mips/math-emu/dp_add.c @@ -73,7 +73,7 @@ ieee754dp ieee754dp_add(ieee754dp x, ieee754dp y) return x; - /* Inifity handeling + /* Inifity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -92,7 +92,7 @@ ieee754dp ieee754dp_add(ieee754dp x, ieee754dp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return x; - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips/math-emu/dp_div.c b/arch/mips/math-emu/dp_div.c index fea2a0c13db9..2d3df92de6f5 100644 --- a/arch/mips/math-emu/dp_div.c +++ b/arch/mips/math-emu/dp_div.c @@ -72,7 +72,7 @@ ieee754dp ieee754dp_div(ieee754dp x, ieee754dp y) return x; - /* Infinity handeling + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -89,7 +89,7 @@ ieee754dp ieee754dp_div(ieee754dp x, ieee754dp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return ieee754dp_inf(xs ^ ys); - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c index 9ec5d40605c7..51fc87ff52b6 100644 --- a/arch/mips/math-emu/dp_mul.c +++ b/arch/mips/math-emu/dp_mul.c @@ -72,7 +72,7 @@ ieee754dp ieee754dp_mul(ieee754dp x, ieee754dp y) return x; - /* Infinity handeling */ + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): diff --git a/arch/mips/math-emu/dp_sub.c b/arch/mips/math-emu/dp_sub.c index a56d352fc156..6af7edaa18ed 100644 --- a/arch/mips/math-emu/dp_sub.c +++ b/arch/mips/math-emu/dp_sub.c @@ -72,7 +72,7 @@ ieee754dp ieee754dp_sub(ieee754dp x, ieee754dp y) return x; - /* Inifity handeling + /* Inifity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -91,7 +91,7 @@ ieee754dp ieee754dp_sub(ieee754dp x, ieee754dp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return x; - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c index 5e86e40c678f..3571107088b1 100644 --- a/arch/mips/math-emu/ieee754.c +++ b/arch/mips/math-emu/ieee754.c @@ -3,7 +3,7 @@ * * BUGS * not much dp done - * doesnt generate IEEE754_INEXACT + * doesn't generate IEEE754_INEXACT * */ /* diff --git a/arch/mips/math-emu/ieee754dp.c b/arch/mips/math-emu/ieee754dp.c index 0943d56ecfe1..f1647fb0318c 100644 --- a/arch/mips/math-emu/ieee754dp.c +++ b/arch/mips/math-emu/ieee754dp.c @@ -99,14 +99,14 @@ ieee754dp ieee754dp_bestnan(ieee754dp x, ieee754dp y) } -/* generate a normal/denormal number with over,under handeling +/* generate a normal/denormal number with over,under handling * sn is sign * xe is an unbiased exponent * xm is 3bit extended precision value. */ ieee754dp ieee754dp_format(int sn, int xe, unsigned long long xm) { - assert(xm); /* we dont gen exact zeros (probably should) */ + assert(xm); /* we don't gen exact zeros (probably should) */ assert((xm >> (DP_MBITS + 1 + 3)) == 0); /* no execess */ assert(xm & (DP_HIDDEN_BIT << 3)); diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c index 511ec8de5b27..29546fcf0d05 100644 --- a/arch/mips/math-emu/ieee754sp.c +++ b/arch/mips/math-emu/ieee754sp.c @@ -100,14 +100,14 @@ ieee754sp ieee754sp_bestnan(ieee754sp x, ieee754sp y) } -/* generate a normal/denormal number with over,under handeling +/* generate a normal/denormal number with over,under handling * sn is sign * xe is an unbiased exponent * xm is 3bit extended precision value. */ ieee754sp ieee754sp_format(int sn, int xe, unsigned xm) { - assert(xm); /* we dont gen exact zeros (probably should) */ + assert(xm); /* we don't gen exact zeros (probably should) */ assert((xm >> (SP_MBITS + 1 + 3)) == 0); /* no execess */ assert(xm & (SP_HIDDEN_BIT << 3)); diff --git a/arch/mips/math-emu/sp_add.c b/arch/mips/math-emu/sp_add.c index 61a050bf052d..af192ebb73fb 100644 --- a/arch/mips/math-emu/sp_add.c +++ b/arch/mips/math-emu/sp_add.c @@ -72,7 +72,7 @@ ieee754sp ieee754sp_add(ieee754sp x, ieee754sp y) return x; - /* Inifity handeling + /* Inifity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -91,7 +91,7 @@ ieee754sp ieee754sp_add(ieee754sp x, ieee754sp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return x; - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips/math-emu/sp_div.c b/arch/mips/math-emu/sp_div.c index 14a87a5503a3..6023377037f5 100644 --- a/arch/mips/math-emu/sp_div.c +++ b/arch/mips/math-emu/sp_div.c @@ -72,7 +72,7 @@ ieee754sp ieee754sp_div(ieee754sp x, ieee754sp y) return x; - /* Infinity handeling + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -89,7 +89,7 @@ ieee754sp ieee754sp_div(ieee754sp x, ieee754sp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return ieee754sp_inf(xs ^ ys); - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips/math-emu/sp_fdp.c b/arch/mips/math-emu/sp_fdp.c index a7ce2f0e05e5..ea467be52b58 100644 --- a/arch/mips/math-emu/sp_fdp.c +++ b/arch/mips/math-emu/sp_fdp.c @@ -49,7 +49,7 @@ ieee754sp ieee754sp_fdp(ieee754dp x) case IEEE754_CLASS_ZERO: return ieee754sp_zero(xs); case IEEE754_CLASS_DNORM: - /* cant possibly be sp representable */ + /* can't possibly be sp representable */ SETCX(IEEE754_UNDERFLOW); return ieee754sp_xcpt(ieee754sp_zero(xs), "fdp", x); case IEEE754_CLASS_NORM: diff --git a/arch/mips/math-emu/sp_mul.c b/arch/mips/math-emu/sp_mul.c index cecf18fd65ee..9bcd5449be0d 100644 --- a/arch/mips/math-emu/sp_mul.c +++ b/arch/mips/math-emu/sp_mul.c @@ -72,7 +72,7 @@ ieee754sp ieee754sp_mul(ieee754sp x, ieee754sp y) return x; - /* Infinity handeling */ + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): diff --git a/arch/mips/math-emu/sp_sub.c b/arch/mips/math-emu/sp_sub.c index c28fc89351a3..e87e804f572d 100644 --- a/arch/mips/math-emu/sp_sub.c +++ b/arch/mips/math-emu/sp_sub.c @@ -72,7 +72,7 @@ ieee754sp ieee754sp_sub(ieee754sp x, ieee754sp y) return x; - /* Inifity handeling + /* Inifity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -91,7 +91,7 @@ ieee754sp ieee754sp_sub(ieee754sp x, ieee754sp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return x; - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c index 0a8ba48f3c4a..c9e84b11d87e 100644 --- a/arch/mips/mips-boards/generic/pci.c +++ b/arch/mips/mips-boards/generic/pci.c @@ -81,7 +81,7 @@ mips_pcibios_config_access(unsigned char access_type, struct pci_bus *bus_dev, u if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { - /* Error occured */ + /* Error occurred */ /* Clear bits */ GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | diff --git a/arch/mips64/kernel/process.c b/arch/mips64/kernel/process.c index ee38f3512ae8..345aa74894ad 100644 --- a/arch/mips64/kernel/process.c +++ b/arch/mips64/kernel/process.c @@ -105,7 +105,7 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp, p->thread.reg31 = (unsigned long) ret_from_fork; /* - * New tasks loose permission to use the fpu. This accelerates context + * New tasks lose permission to use the fpu. This accelerates context * switching for most programs since they don't use the fpu. */ p->thread.cp0_status = read_32bit_cp0_register(CP0_STATUS) & diff --git a/arch/mips64/kernel/r4k_switch.S b/arch/mips64/kernel/r4k_switch.S index 24db4edcc98d..a7b7edce73c0 100644 --- a/arch/mips64/kernel/r4k_switch.S +++ b/arch/mips64/kernel/r4k_switch.S @@ -79,7 +79,7 @@ LEAF(lazy_fpu_switch) beqz a0, 2f # Save floating point state nor t3, zero, t3 - ld t1, ST_OFF(a0) # last thread looses fpu + ld t1, ST_OFF(a0) # last thread loses fpu and t1, t3 sd t1, ST_OFF(a0) sll t2, t1, 5 diff --git a/arch/mips64/kernel/traps.c b/arch/mips64/kernel/traps.c index 7161c7f967af..023435ac92aa 100644 --- a/arch/mips64/kernel/traps.c +++ b/arch/mips64/kernel/traps.c @@ -497,7 +497,7 @@ void __init trap_init(void) /* Some firmware leaves the BEV flag set, clear it. */ set_cp0_status(ST0_BEV, 0); - /* Copy the generic exception handler code to it's final destination. */ + /* Copy the generic exception handler code to its final destination. */ memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80); memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80); diff --git a/arch/mips64/math-emu/dp_add.c b/arch/mips64/math-emu/dp_add.c index 5a3158bbbc26..0c96f9b39de9 100644 --- a/arch/mips64/math-emu/dp_add.c +++ b/arch/mips64/math-emu/dp_add.c @@ -73,7 +73,7 @@ ieee754dp ieee754dp_add(ieee754dp x, ieee754dp y) return x; - /* Inifity handeling + /* Inifity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -92,7 +92,7 @@ ieee754dp ieee754dp_add(ieee754dp x, ieee754dp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return x; - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips64/math-emu/dp_div.c b/arch/mips64/math-emu/dp_div.c index fea2a0c13db9..2d3df92de6f5 100644 --- a/arch/mips64/math-emu/dp_div.c +++ b/arch/mips64/math-emu/dp_div.c @@ -72,7 +72,7 @@ ieee754dp ieee754dp_div(ieee754dp x, ieee754dp y) return x; - /* Infinity handeling + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -89,7 +89,7 @@ ieee754dp ieee754dp_div(ieee754dp x, ieee754dp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return ieee754dp_inf(xs ^ ys); - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips64/math-emu/dp_mul.c b/arch/mips64/math-emu/dp_mul.c index 9ec5d40605c7..51fc87ff52b6 100644 --- a/arch/mips64/math-emu/dp_mul.c +++ b/arch/mips64/math-emu/dp_mul.c @@ -72,7 +72,7 @@ ieee754dp ieee754dp_mul(ieee754dp x, ieee754dp y) return x; - /* Infinity handeling */ + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): diff --git a/arch/mips64/math-emu/dp_sub.c b/arch/mips64/math-emu/dp_sub.c index a56d352fc156..6af7edaa18ed 100644 --- a/arch/mips64/math-emu/dp_sub.c +++ b/arch/mips64/math-emu/dp_sub.c @@ -72,7 +72,7 @@ ieee754dp ieee754dp_sub(ieee754dp x, ieee754dp y) return x; - /* Inifity handeling + /* Inifity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -91,7 +91,7 @@ ieee754dp ieee754dp_sub(ieee754dp x, ieee754dp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return x; - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips64/math-emu/ieee754dp.c b/arch/mips64/math-emu/ieee754dp.c index 0943d56ecfe1..f1647fb0318c 100644 --- a/arch/mips64/math-emu/ieee754dp.c +++ b/arch/mips64/math-emu/ieee754dp.c @@ -99,14 +99,14 @@ ieee754dp ieee754dp_bestnan(ieee754dp x, ieee754dp y) } -/* generate a normal/denormal number with over,under handeling +/* generate a normal/denormal number with over,under handling * sn is sign * xe is an unbiased exponent * xm is 3bit extended precision value. */ ieee754dp ieee754dp_format(int sn, int xe, unsigned long long xm) { - assert(xm); /* we dont gen exact zeros (probably should) */ + assert(xm); /* we don't gen exact zeros (probably should) */ assert((xm >> (DP_MBITS + 1 + 3)) == 0); /* no execess */ assert(xm & (DP_HIDDEN_BIT << 3)); diff --git a/arch/mips64/math-emu/ieee754sp.c b/arch/mips64/math-emu/ieee754sp.c index 511ec8de5b27..29546fcf0d05 100644 --- a/arch/mips64/math-emu/ieee754sp.c +++ b/arch/mips64/math-emu/ieee754sp.c @@ -100,14 +100,14 @@ ieee754sp ieee754sp_bestnan(ieee754sp x, ieee754sp y) } -/* generate a normal/denormal number with over,under handeling +/* generate a normal/denormal number with over,under handling * sn is sign * xe is an unbiased exponent * xm is 3bit extended precision value. */ ieee754sp ieee754sp_format(int sn, int xe, unsigned xm) { - assert(xm); /* we dont gen exact zeros (probably should) */ + assert(xm); /* we don't gen exact zeros (probably should) */ assert((xm >> (SP_MBITS + 1 + 3)) == 0); /* no execess */ assert(xm & (SP_HIDDEN_BIT << 3)); diff --git a/arch/mips64/math-emu/sp_add.c b/arch/mips64/math-emu/sp_add.c index 61a050bf052d..af192ebb73fb 100644 --- a/arch/mips64/math-emu/sp_add.c +++ b/arch/mips64/math-emu/sp_add.c @@ -72,7 +72,7 @@ ieee754sp ieee754sp_add(ieee754sp x, ieee754sp y) return x; - /* Inifity handeling + /* Inifity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -91,7 +91,7 @@ ieee754sp ieee754sp_add(ieee754sp x, ieee754sp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return x; - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips64/math-emu/sp_div.c b/arch/mips64/math-emu/sp_div.c index 14a87a5503a3..6023377037f5 100644 --- a/arch/mips64/math-emu/sp_div.c +++ b/arch/mips64/math-emu/sp_div.c @@ -72,7 +72,7 @@ ieee754sp ieee754sp_div(ieee754sp x, ieee754sp y) return x; - /* Infinity handeling + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -89,7 +89,7 @@ ieee754sp ieee754sp_div(ieee754sp x, ieee754sp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return ieee754sp_inf(xs ^ ys); - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips64/math-emu/sp_fdp.c b/arch/mips64/math-emu/sp_fdp.c index a7ce2f0e05e5..ea467be52b58 100644 --- a/arch/mips64/math-emu/sp_fdp.c +++ b/arch/mips64/math-emu/sp_fdp.c @@ -49,7 +49,7 @@ ieee754sp ieee754sp_fdp(ieee754dp x) case IEEE754_CLASS_ZERO: return ieee754sp_zero(xs); case IEEE754_CLASS_DNORM: - /* cant possibly be sp representable */ + /* can't possibly be sp representable */ SETCX(IEEE754_UNDERFLOW); return ieee754sp_xcpt(ieee754sp_zero(xs), "fdp", x); case IEEE754_CLASS_NORM: diff --git a/arch/mips64/math-emu/sp_mul.c b/arch/mips64/math-emu/sp_mul.c index cecf18fd65ee..9bcd5449be0d 100644 --- a/arch/mips64/math-emu/sp_mul.c +++ b/arch/mips64/math-emu/sp_mul.c @@ -72,7 +72,7 @@ ieee754sp ieee754sp_mul(ieee754sp x, ieee754sp y) return x; - /* Infinity handeling */ + /* Infinity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): diff --git a/arch/mips64/math-emu/sp_sub.c b/arch/mips64/math-emu/sp_sub.c index c28fc89351a3..e87e804f572d 100644 --- a/arch/mips64/math-emu/sp_sub.c +++ b/arch/mips64/math-emu/sp_sub.c @@ -72,7 +72,7 @@ ieee754sp ieee754sp_sub(ieee754sp x, ieee754sp y) return x; - /* Inifity handeling + /* Inifity handling */ case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): @@ -91,7 +91,7 @@ ieee754sp ieee754sp_sub(ieee754sp x, ieee754sp y) case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): return x; - /* Zero handeling + /* Zero handling */ case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): diff --git a/arch/mips64/mips-boards/generic/pci.c b/arch/mips64/mips-boards/generic/pci.c index 513042d8bbf6..4e377c3e9716 100644 --- a/arch/mips64/mips-boards/generic/pci.c +++ b/arch/mips64/mips-boards/generic/pci.c @@ -87,7 +87,7 @@ mips_pcibios_config_access(unsigned char access_type, struct pci_dev *dev, if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)) { - /* Error occured */ + /* Error occurred */ /* Clear bits */ GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT | diff --git a/arch/mips64/sgi-ip27/ip27-nmi.c b/arch/mips64/sgi-ip27/ip27-nmi.c index 8b03918f817a..8ba5ff58da0a 100644 --- a/arch/mips64/sgi-ip27/ip27-nmi.c +++ b/arch/mips64/sgi-ip27/ip27-nmi.c @@ -127,7 +127,7 @@ cont_nmi_dump(void) * This is for 2 reasons: * - sometimes a MMSC fail to NMI all cpus. * - on 512p SN0 system, the MMSC will only send NMIs to - * half the cpus. Unfortunately, we dont know which cpus may be + * half the cpus. Unfortunately, we don't know which cpus may be * NMIed - it depends on how the site chooses to configure. * * Note: it has been measure that it takes the MMSC up to 2.3 secs to diff --git a/arch/mips64/sgi-ip27/ip27-pci-dma.c b/arch/mips64/sgi-ip27/ip27-pci-dma.c index 88388cadf95e..fcb71869c6a4 100644 --- a/arch/mips64/sgi-ip27/ip27-pci-dma.c +++ b/arch/mips64/sgi-ip27/ip27-pci-dma.c @@ -74,7 +74,7 @@ dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, * must match what was provided for in a previous pci_map_single call. All * other usages are undefined. * - * After this call, reads by the cpu to the buffer are guarenteed to see + * After this call, reads by the cpu to the buffer are guaranteed to see * whatever the device wrote there. */ void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index 805debfbd2b7..d618a3bec3cc 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c @@ -349,7 +349,7 @@ txn_alloc_addr(int virt_irq) /* -** The alloc process needs to accept a parameter to accomodate limitations +** The alloc process needs to accept a parameter to accommodate limitations ** of the HW/SW which use these bits: ** Legacy PA I/O (GSC/NIO): 5 bits (architected EIM register) ** V-class (EPIC): 6 bits diff --git a/arch/parisc/kernel/perf.c b/arch/parisc/kernel/perf.c index 4de269b94c13..30f85ffa26ea 100644 --- a/arch/parisc/kernel/perf.c +++ b/arch/parisc/kernel/perf.c @@ -255,7 +255,7 @@ printk("Preparing to start counters\n"); } /* - * Open the device and initialize all of it's memory. The device is only + * Open the device and initialize all of its memory. The device is only * opened once, but can be "queried" by multiple processes that know its * file descriptor. */ diff --git a/arch/parisc/kernel/perf_images.h b/arch/parisc/kernel/perf_images.h index 5af3a2072288..d53ee4f06cff 100644 --- a/arch/parisc/kernel/perf_images.h +++ b/arch/parisc/kernel/perf_images.h @@ -1556,7 +1556,7 @@ static uint32_t onyx_images[][PCXU_IMAGE_SIZE/sizeof(uint32_t)] = { * IRTN_AV fires twice for every I-cache miss returning from RIB to the IFU. * It will not fire if a second I-cache miss is issued from the IFU to RIB * before the first returns. Therefore, if the IRTN_AV count is much less - * than 2x the ICORE_AV count, many speculative I-cache misses are occuring + * than 2x the ICORE_AV count, many speculative I-cache misses are occurring * which are "discovered" to be incorrect fairly quickly. * The ratio of I-cache miss transactions on Runway to the ICORE_AV count is * a measure of the effectiveness of instruction prefetching. This ratio diff --git a/arch/parisc/kernel/ptrace.c b/arch/parisc/kernel/ptrace.c index 2ab7cd2ef50c..213c9a349673 100644 --- a/arch/parisc/kernel/ptrace.c +++ b/arch/parisc/kernel/ptrace.c @@ -242,7 +242,7 @@ long sys_ptrace(long request, pid_t pid, long addr, long data) * * Allow writing to Nullify, Divide-step-correction, * and carry/borrow bits. - * BEWARE, if you set N, and then single step, it wont + * BEWARE, if you set N, and then single step, it won't * stop on the nullified instruction. */ DBG(("sys_ptrace(POKEUSR, %d, %lx, %lx)\n", diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c index f45c62784333..9c3f03f25415 100644 --- a/arch/parisc/kernel/time.c +++ b/arch/parisc/kernel/time.c @@ -32,7 +32,7 @@ #include <linux/timex.h> -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; /* xtime and wall_jiffies keep wall-clock time */ extern unsigned long wall_jiffies; diff --git a/arch/ppc/4xx_io/serial_sicc.c b/arch/ppc/4xx_io/serial_sicc.c index a4558ff37fbe..e09a211576a1 100644 --- a/arch/ppc/4xx_io/serial_sicc.c +++ b/arch/ppc/4xx_io/serial_sicc.c @@ -139,7 +139,7 @@ #define _LSR_RX_ERR (_LSR_LB_BREAK | _LSR_FE_MASK | _LSR_OE_MASK | \ _LSR_PE_MASK ) -/* serial port reciever command register */ +/* serial port receiver command register */ #define _RCR_ER_MASK 0x80 /* enable receiver mask */ #define _RCR_DME_MASK 0x60 /* dma mode */ diff --git a/arch/ppc/8xx_io/cs4218_tdm.c b/arch/ppc/8xx_io/cs4218_tdm.c index b63d6b46ab54..3b2aa8b10570 100644 --- a/arch/ppc/8xx_io/cs4218_tdm.c +++ b/arch/ppc/8xx_io/cs4218_tdm.c @@ -2495,7 +2495,7 @@ int __init tdm8xx_sound_init(void) cp->cp_simode &= ~0x00000fff; /* Enable common receive/transmit clock pins, use IDL format. - * Sync on falling edge, transmit rising clock, recieve falling + * Sync on falling edge, transmit rising clock, receive falling * clock, delay 1 bit on both Tx and Rx. Common Tx/Rx clocks and * sync. * Connect SMC2 to TSA. diff --git a/arch/ppc/kernel/l2cr.S b/arch/ppc/kernel/l2cr.S index 4625af465870..6a94c425a537 100644 --- a/arch/ppc/kernel/l2cr.S +++ b/arch/ppc/kernel/l2cr.S @@ -136,7 +136,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) /**** Might be a good idea to set L2DO here - to prevent instructions from getting into the cache. But since we invalidate the next time we enable the cache it doesn't really matter. - Don't do this unless you accomodate all processor variations. + Don't do this unless you accommodate all processor variations. The bit moved on the 7450..... ****/ diff --git a/arch/ppc/kernel/time.c b/arch/ppc/kernel/time.c index 3fef611a7df8..da774859939b 100644 --- a/arch/ppc/kernel/time.c +++ b/arch/ppc/kernel/time.c @@ -68,7 +68,7 @@ #include <asm/time.h> /* XXX false sharing with below? */ -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; unsigned long disarm_decr[NR_CPUS]; diff --git a/arch/ppc/mm/mem_pieces.c b/arch/ppc/mm/mem_pieces.c index 149d31773aad..196da48ccbf3 100644 --- a/arch/ppc/mm/mem_pieces.c +++ b/arch/ppc/mm/mem_pieces.c @@ -1,6 +1,6 @@ /* * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> - * Changes to accomodate Power Macintoshes. + * Changes to accommodate Power Macintoshes. * Cort Dougan <cort@cs.nmt.edu> * Rewrites. * Grant Erickson <grant@lcse.umn.edu> diff --git a/arch/ppc/mm/mem_pieces.h b/arch/ppc/mm/mem_pieces.h index bc8e2861c405..cd481c6b3e75 100644 --- a/arch/ppc/mm/mem_pieces.h +++ b/arch/ppc/mm/mem_pieces.h @@ -1,6 +1,6 @@ /* * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au> - * Changes to accomodate Power Macintoshes. + * Changes to accommodate Power Macintoshes. * Cort Dougan <cort@cs.nmt.edu> * Rewrites. * Grant Erickson <grant@lcse.umn.edu> diff --git a/arch/ppc/platforms/4xx/ibmstbx25.h b/arch/ppc/platforms/4xx/ibmstbx25.h index 954831398c63..9a2efc366e9c 100644 --- a/arch/ppc/platforms/4xx/ibmstbx25.h +++ b/arch/ppc/platforms/4xx/ibmstbx25.h @@ -164,7 +164,7 @@ #define IBM_CPM_CPU 0x10000000 /* PPC405B3 clock control */ #define IBM_CPM_AUD 0x08000000 /* Audio Decoder */ #define IBM_CPM_EBIU 0x04000000 /* External Bus Interface Unit */ -#define IBM_CPM_IRR 0x02000000 /* Infrared reciever */ +#define IBM_CPM_IRR 0x02000000 /* Infrared receiver */ #define IBM_CPM_DMA 0x01000000 /* DMA controller */ #define IBM_CPM_UART2 0x00200000 /* Serial Control Port */ #define IBM_CPM_UART1 0x00100000 /* Serial 1 / Infrared */ diff --git a/arch/ppc/platforms/pmac_feature.c b/arch/ppc/platforms/pmac_feature.c index 04140eda53ab..c36b8c34c405 100644 --- a/arch/ppc/platforms/pmac_feature.c +++ b/arch/ppc/platforms/pmac_feature.c @@ -50,7 +50,7 @@ extern unsigned long powersave_nap; /* * We use a single global lock to protect accesses. Each driver has - * to take care of it's own locking + * to take care of its own locking */ static spinlock_t feature_lock __pmacdata = SPIN_LOCK_UNLOCKED; diff --git a/arch/ppc/syslib/mpc10x_common.c b/arch/ppc/syslib/mpc10x_common.c index 151e6f825860..630976fd53fb 100644 --- a/arch/ppc/syslib/mpc10x_common.c +++ b/arch/ppc/syslib/mpc10x_common.c @@ -109,7 +109,7 @@ mpc10x_bridge_init(struct pci_controller *hose, return -1; } - /* Make sure its a supported bridge */ + /* Make sure it's a supported bridge */ early_read_config_dword(hose, 0, PCI_DEVFN(0,0), diff --git a/arch/ppc64/boot/addRamDisk.c b/arch/ppc64/boot/addRamDisk.c index f940d0f99177..7f2c09473394 100644 --- a/arch/ppc64/boot/addRamDisk.c +++ b/arch/ppc64/boot/addRamDisk.c @@ -154,7 +154,7 @@ int main(int argc, char **argv) /* Process the Sysmap file to determine where _end is */ sysmapPages = sysmapLen / 4096; - /* read the whole file line by line, expect that it doesnt fail */ + /* read the whole file line by line, expect that it doesn't fail */ while ( fgets(inbuf, 4096, sysmap) ) ; /* search for _end in the last page of the system map */ ptr_end = strstr(inbuf, " _end"); diff --git a/arch/ppc64/boot/addSystemMap.c b/arch/ppc64/boot/addSystemMap.c index 03b9187d0c00..0faf37551da9 100644 --- a/arch/ppc64/boot/addSystemMap.c +++ b/arch/ppc64/boot/addSystemMap.c @@ -146,7 +146,7 @@ int main(int argc, char **argv) /* Process the Sysmap file to determine the true end of the kernel */ sysmapPages = sysmapLen / 4096; printf("System map pages to copy = %ld\n", sysmapPages); - /* read the whole file line by line, expect that it doesnt fail */ + /* read the whole file line by line, expect that it doesn't fail */ while ( fgets(inbuf, 4096, sysmap) ) ; /* search for _end in the last page of the system map */ ptr_end = strstr(inbuf, " _end"); diff --git a/arch/ppc64/kernel/head.S b/arch/ppc64/kernel/head.S index 6264f3155ca2..8a36c641f07e 100644 --- a/arch/ppc64/kernel/head.S +++ b/arch/ppc64/kernel/head.S @@ -109,7 +109,7 @@ __secondary_hold_spinloop: .llong 0x0 /* Secondary processors write this value with their cpu # */ - /* after they enter the spin loop immediatly below. */ + /* after they enter the spin loop immediately below. */ .globl __secondary_hold_acknowledge __secondary_hold_acknowledge: .llong 0x0 diff --git a/arch/ppc64/kernel/ioctl32.c b/arch/ppc64/kernel/ioctl32.c index 7e0f5aa3f670..788effdc19a6 100644 --- a/arch/ppc64/kernel/ioctl32.c +++ b/arch/ppc64/kernel/ioctl32.c @@ -3315,7 +3315,7 @@ out: * * But how to keep track of these kernel buffers? We'd need to either * keep track of them in some table _or_ know about usbdevicefs internals - * (ie. the exact layout of it's file private, which is actually defined + * (ie. the exact layout of its file private, which is actually defined * in linux/usbdevice_fs.h, the layout of the async queues are private to * devio.c) * diff --git a/arch/ppc64/kernel/lmb.c b/arch/ppc64/kernel/lmb.c index b07040587c8b..81d3ed1ad964 100644 --- a/arch/ppc64/kernel/lmb.c +++ b/arch/ppc64/kernel/lmb.c @@ -73,7 +73,7 @@ lmb_init(void) _lmb->reserved.cnt = 1; } -/* This is only used here, it doesnt deserve to be in bitops.h */ +/* This is only used here, it doesn't deserve to be in bitops.h */ static __inline__ long cnt_trailing_zeros(unsigned long mask) { long cnt; diff --git a/arch/ppc64/kernel/pSeries_lpar.c b/arch/ppc64/kernel/pSeries_lpar.c index f1e9f2d3f8a4..653759fcde14 100644 --- a/arch/ppc64/kernel/pSeries_lpar.c +++ b/arch/ppc64/kernel/pSeries_lpar.c @@ -461,7 +461,7 @@ long pSeries_lpar_hpte_insert(unsigned long hpte_group, return -1; /* - * Since we try and ioremap PHBs we dont own, the pte insert + * Since we try and ioremap PHBs we don't own, the pte insert * will fail. However we must catch the failure in hash_page * or we will loop forever, so return -2 in this case. */ @@ -485,7 +485,7 @@ static long pSeries_lpar_hpte_remove(unsigned long hpte_group) for (i = 0; i < HPTES_PER_GROUP; i++) { - /* dont remove a bolted entry */ + /* don't remove a bolted entry */ lpar_rc = plpar_pte_remove(H_ANDCOND, hpte_group + slot_offset, (0x1UL << 4), &dummy1, &dummy2); diff --git a/arch/ppc64/kernel/pci_dn.c b/arch/ppc64/kernel/pci_dn.c index 9f7b1651934d..f19cefd32715 100644 --- a/arch/ppc64/kernel/pci_dn.c +++ b/arch/ppc64/kernel/pci_dn.c @@ -150,7 +150,7 @@ is_devfn_node(struct device_node *dn, void *data) } /* This is the "slow" path for looking up a device_node from a - * pci_dev. It will hunt for the device under it's parent's + * pci_dev. It will hunt for the device under its parent's * phb and then update sysdata for a future fastpath. * * It may also do fixups on the actual device since this happens diff --git a/arch/ppc64/kernel/ras.c b/arch/ppc64/kernel/ras.c index c54143ed326e..d0af354a7701 100644 --- a/arch/ppc64/kernel/ras.c +++ b/arch/ppc64/kernel/ras.c @@ -94,7 +94,7 @@ void init_ras_IRQ(void) { /* * Handle power subsystem events (EPOW). * - * Presently we just log the event has occured. This should be fixed + * Presently we just log the event has occurred. This should be fixed * to examine the type of power failure and take appropriate action where * the time horizon permits something useful to be done. */ diff --git a/arch/ppc64/kernel/smp.c b/arch/ppc64/kernel/smp.c index 389ac2d78eef..44bd8bb70914 100644 --- a/arch/ppc64/kernel/smp.c +++ b/arch/ppc64/kernel/smp.c @@ -51,7 +51,7 @@ int smp_threads_ready = 0; unsigned long cache_decay_ticks; -/* initialised so it doesnt end up in bss */ +/* initialised so it doesn't end up in bss */ unsigned long cpu_online_map = 0; static struct smp_ops_t *smp_ops; diff --git a/arch/ppc64/kernel/time.c b/arch/ppc64/kernel/time.c index f534ae598edd..d008d5c6b39e 100644 --- a/arch/ppc64/kernel/time.c +++ b/arch/ppc64/kernel/time.c @@ -65,7 +65,7 @@ void smp_local_timer_interrupt(struct pt_regs *); -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; /* keep track of when we need to update the rtc */ time_t last_rtc_update; diff --git a/arch/ppc64/xmon/xmon.c b/arch/ppc64/xmon/xmon.c index 4318a6c7318d..a2d0f517177b 100644 --- a/arch/ppc64/xmon/xmon.c +++ b/arch/ppc64/xmon/xmon.c @@ -2072,7 +2072,7 @@ find_tb_table(unsigned long codeaddr, struct tbtable *tab) int instr; int num_parms; - /* dont look for traceback table in userspace */ + /* don't look for traceback table in userspace */ if (codeaddr < PAGE_OFFSET) return 0; diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index 800bbeb8016b..60f8059c5afa 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c @@ -46,7 +46,7 @@ #define TICK_SIZE tick -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; static ext_int_info_t ext_int_info_timer; static uint64_t xtime_cc; diff --git a/arch/s390x/kernel/time.c b/arch/s390x/kernel/time.c index 66115fc37677..53809f47e4b3 100644 --- a/arch/s390x/kernel/time.c +++ b/arch/s390x/kernel/time.c @@ -45,7 +45,7 @@ #define TICK_SIZE tick -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; static ext_int_info_t ext_int_info_timer; static uint64_t xtime_cc; diff --git a/arch/sh/kernel/fpu.c b/arch/sh/kernel/fpu.c index 70cac48db933..15abcfee266b 100644 --- a/arch/sh/kernel/fpu.c +++ b/arch/sh/kernel/fpu.c @@ -118,7 +118,7 @@ restore_fpu(struct task_struct *tsk) /* * Load the FPU with signalling NANS. This bit pattern we're using - * has the property that no matter wether considered as single or as + * has the property that no matter whether considered as single or as * double precission represents signaling NANS. */ diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c index e44a5e5cf68b..ce84bd4af266 100644 --- a/arch/sh/kernel/irq.c +++ b/arch/sh/kernel/irq.c @@ -61,7 +61,7 @@ static void ack_none(unsigned int irq) { /* * 'what should we do if we get a hw irq event on an illegal vector'. - * each architecture has to answer this themselves, it doesnt deserve + * each architecture has to answer this themselves, it doesn't deserve * a generic callback i think. */ printk("unexpected IRQ trap at vector %02x\n", irq); diff --git a/arch/sh/kernel/pci-dma.c b/arch/sh/kernel/pci-dma.c index f941c3332e92..be0745b162c1 100644 --- a/arch/sh/kernel/pci-dma.c +++ b/arch/sh/kernel/pci-dma.c @@ -24,7 +24,7 @@ void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, ret = (void *) __get_free_pages(gfp, get_order(size)); if (ret != NULL) { - /* Is it neccessary to do the memset? */ + /* Is it necessary to do the memset? */ memset(ret, 0, size); *dma_handle = virt_to_bus(ret); } diff --git a/arch/sh/kernel/pci-sh7751.c b/arch/sh/kernel/pci-sh7751.c index 7159ecca92fc..9db302503b0a 100644 --- a/arch/sh/kernel/pci-sh7751.c +++ b/arch/sh/kernel/pci-sh7751.c @@ -285,7 +285,7 @@ void __init pcibios_init(void) struct pci_ops *bios = NULL; struct pci_ops *dir = NULL; - PCIDBG(1,"PCI: Starting intialization.\n"); + PCIDBG(1,"PCI: Starting initialization.\n"); #ifdef CONFIG_PCI_BIOS if ((pci_probe & PCI_PROBE_BIOS) && ((bios = pci_find_bios()))) { pci_probe |= PCI_BIOS_SORT; diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c index 5a17b0510284..3042f8483988 100644 --- a/arch/sh/kernel/time.c +++ b/arch/sh/kernel/time.c @@ -70,7 +70,7 @@ #endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */ #endif /* __sh3__ or __SH4__ */ -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; extern unsigned long wall_jiffies; #define TICK_SIZE tick diff --git a/arch/sh/stboards/pcidma.c b/arch/sh/stboards/pcidma.c index 475311390fd6..bbaaded9cff5 100644 --- a/arch/sh/stboards/pcidma.c +++ b/arch/sh/stboards/pcidma.c @@ -24,7 +24,7 @@ void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, ret = (void *) __get_free_pages(gfp, get_order(size)); if (ret != NULL) { - /* Is it neccessary to do the memset? */ + /* Is it necessary to do the memset? */ memset(ret, 0, size); *dma_handle = virt_to_bus(ret); } diff --git a/arch/sparc/kernel/init_task.c b/arch/sparc/kernel/init_task.c index e20422c9688e..814ea28ad6bf 100644 --- a/arch/sparc/kernel/init_task.c +++ b/arch/sparc/kernel/init_task.c @@ -12,7 +12,7 @@ static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); struct mm_struct init_mm = INIT_MM(init_mm); struct task_struct init_task = INIT_TASK(init_task); -/* .text section in head.S is aligned at 8k boundry and this gets linked +/* .text section in head.S is aligned at 8k boundary and this gets linked * right after that so that the init_thread_union is aligned properly as well. * If this is not aligned on a 8k boundry, then you should change code * in etrap.S which assumes it. diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c index 0c2d23b36896..3066f0cbc83b 100644 --- a/arch/sparc/kernel/ioport.c +++ b/arch/sparc/kernel/ioport.c @@ -599,7 +599,7 @@ dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, * must match what was provided for in a previous pci_map_single call. All * other usages are undefined. * - * After this call, reads by the cpu to the buffer are guarenteed to see + * After this call, reads by the cpu to the buffer are guaranteed to see * whatever the device wrote there. */ void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t ba, size_t size, diff --git a/arch/sparc/kernel/time.c b/arch/sparc/kernel/time.c index 0254734f1745..77e829f405bf 100644 --- a/arch/sparc/kernel/time.c +++ b/arch/sparc/kernel/time.c @@ -45,7 +45,7 @@ extern unsigned long wall_jiffies; -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED; enum sparc_clock_type sp_clock_typ; diff --git a/arch/sparc/lib/blockops.S b/arch/sparc/lib/blockops.S index 3f09ec1dbaab..b018d18c79e2 100644 --- a/arch/sparc/lib/blockops.S +++ b/arch/sparc/lib/blockops.S @@ -38,7 +38,7 @@ * and (2 * PAGE_SIZE) (for kernel stacks) * and with a second arg of zero. We assume in * all of these cases that the buffer is aligned - * on at least an 8 byte boundry. + * on at least an 8 byte boundary. * * Therefore we special case them to make them * as fast as possible. diff --git a/arch/sparc/lib/checksum.S b/arch/sparc/lib/checksum.S index d02b6dfb2d87..3dc582592d8f 100644 --- a/arch/sparc/lib/checksum.S +++ b/arch/sparc/lib/checksum.S @@ -336,7 +336,7 @@ C_LABEL(__csum_partial_copy_sparc_generic): bne cc_dword_align ! yes, we check for short lengths there andcc %g1, 0xffffff80, %g0 ! can we use unrolled loop? 3: be 3f ! nope, less than one loop remains - andcc %o1, 4, %g0 ! dest aligned on 4 or 8 byte boundry? + andcc %o1, 4, %g0 ! dest aligned on 4 or 8 byte boundary? be ccdbl + 4 ! 8 byte aligned, kick ass 5: CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x00,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3) CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x20,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3) diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c index e9aab3723ad1..9a55259ae6b2 100644 --- a/arch/sparc/mm/srmmu.c +++ b/arch/sparc/mm/srmmu.c @@ -2120,7 +2120,7 @@ static void __init get_srmmu_type(void) srmmu_is_bad(); } -/* dont laugh, static pagetables */ +/* don't laugh, static pagetables */ static void srmmu_check_pgt_cache(int low, int high) { } diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c index 5b165f0d3b1b..1096a2df5e44 100644 --- a/arch/sparc/mm/sun4c.c +++ b/arch/sparc/mm/sun4c.c @@ -533,7 +533,7 @@ static inline void sun4c_init_ss2_cache_bug(void) } } -/* Addr is always aligned on a page boundry for us already. */ +/* Addr is always aligned on a page boundary for us already. */ static void sun4c_map_dma_area(unsigned long va, u32 addr, int len) { unsigned long page, end; @@ -1042,7 +1042,7 @@ static struct thread_info *sun4c_alloc_thread_info(void) get_locked_segment(addr); /* We are changing the virtual color of the page(s) - * so we must flush the cache to guarentee consistency. + * so we must flush the cache to guarantee consistency. */ sun4c_flush_page(pages); #ifndef CONFIG_SUN4 diff --git a/arch/sparc64/kernel/init_task.c b/arch/sparc64/kernel/init_task.c index 15f5c900bdc2..e0712ddcdcb6 100644 --- a/arch/sparc64/kernel/init_task.c +++ b/arch/sparc64/kernel/init_task.c @@ -12,7 +12,7 @@ static struct signal_struct init_signals = INIT_SIGNALS(init_signals); static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); struct mm_struct init_mm = INIT_MM(init_mm); -/* .text section in head.S is aligned at 2 page boundry and this gets linked +/* .text section in head.S is aligned at 2 page boundary and this gets linked * right after that so that the init_thread_union is aligned properly as well. * We really don't need this special alignment like the Intel does, but * I do it anyways for completeness. diff --git a/arch/sparc64/kernel/ioctl32.c b/arch/sparc64/kernel/ioctl32.c index 4ca993184908..f31834f017dd 100644 --- a/arch/sparc64/kernel/ioctl32.c +++ b/arch/sparc64/kernel/ioctl32.c @@ -3947,7 +3947,7 @@ out: * * But how to keep track of these kernel buffers? We'd need to either * keep track of them in some table _or_ know about usbdevicefs internals - * (ie. the exact layout of it's file private, which is actually defined + * (ie. the exact layout of its file private, which is actually defined * in linux/usbdevice_fs.h, the layout of the async queues are private to * devio.c) * diff --git a/arch/sparc64/kernel/iommu_common.h b/arch/sparc64/kernel/iommu_common.h index 039744070ff6..ad791014419c 100644 --- a/arch/sparc64/kernel/iommu_common.h +++ b/arch/sparc64/kernel/iommu_common.h @@ -40,7 +40,7 @@ extern void verify_sglist(struct scatterlist *sg, int nents, iopte_t *iopte, int /* Two addresses are "virtually contiguous" if and only if: * 1) They are equal, or... - * 2) They are both on a page boundry + * 2) They are both on a page boundary */ #define VCONTIG(__X, __Y) (((__X) == (__Y)) || \ (((__X) | (__Y)) << (64UL - PAGE_SHIFT)) == 0UL) diff --git a/arch/sparc64/kernel/pci_common.c b/arch/sparc64/kernel/pci_common.c index 5cc9117952e3..025639222b65 100644 --- a/arch/sparc64/kernel/pci_common.c +++ b/arch/sparc64/kernel/pci_common.c @@ -583,7 +583,7 @@ static int __init pci_intmap_match(struct pci_dev *pdev, unsigned int *interrupt * the PBM. * * However if that parent bridge has interrupt map/mask - * properties of it's own we use the PROM register property + * properties of its own we use the PROM register property * of the next child device on the path to PDEV. * * In detail the two cases are (note that the 'X' below is the diff --git a/arch/sparc64/kernel/sbus.c b/arch/sparc64/kernel/sbus.c index 9a5f8a99cfdc..18b1997e1c64 100644 --- a/arch/sparc64/kernel/sbus.c +++ b/arch/sparc64/kernel/sbus.c @@ -24,7 +24,7 @@ #include "iommu_common.h" /* These should be allocated on an SMP_CACHE_BYTES - * aligned boundry for optimal performance. + * aligned boundary for optimal performance. * * On SYSIO, using an 8K page size we have 1GB of SBUS * DMA space mapped. We divide this space into equally diff --git a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c index 3d716914b158..7503513d4bdc 100644 --- a/arch/sparc64/kernel/time.c +++ b/arch/sparc64/kernel/time.c @@ -47,7 +47,7 @@ unsigned long ds1287_regs = 0UL; extern unsigned long wall_jiffies; -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; static unsigned long mstk48t08_regs = 0UL; static unsigned long mstk48t59_regs = 0UL; diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c index 23e5a862f088..78901988b1ae 100644 --- a/arch/sparc64/kernel/traps.c +++ b/arch/sparc64/kernel/traps.c @@ -571,7 +571,7 @@ unsigned long __init cheetah_tune_scheduling(void) unsigned long flush_linesize = ecache_flush_linesize; unsigned long flush_size = ecache_flush_size; - /* Run through the whole cache to guarentee the timed loop + /* Run through the whole cache to guarantee the timed loop * is really displacing cache lines. */ __asm__ __volatile__("1: subcc %0, %4, %0\n\t" diff --git a/arch/sparc64/lib/U3copy_from_user.S b/arch/sparc64/lib/U3copy_from_user.S index a367d40e5854..c2ae2f4f4b8b 100644 --- a/arch/sparc64/lib/U3copy_from_user.S +++ b/arch/sparc64/lib/U3copy_from_user.S @@ -416,7 +416,7 @@ U3copy_from_user_toosmall: 2: VISEntryHalf ! MS+MS - /* Compute (len - (len % 8)) into %g2. This is guarenteed + /* Compute (len - (len % 8)) into %g2. This is guaranteed * to be nonzero. */ andn %o2, 0x7, %g2 ! A0 Group @@ -425,7 +425,7 @@ U3copy_from_user_toosmall: * one 8-byte longword past the end of src. It actually * does not, as %g2 is subtracted as loads are done from * src, so we always stop before running off the end. - * Also, we are guarenteed to have at least 0x10 bytes + * Also, we are guaranteed to have at least 0x10 bytes * to move here. */ sub %g2, 0x8, %g2 ! A0 Group (reg-dep) diff --git a/arch/sparc64/lib/U3copy_in_user.S b/arch/sparc64/lib/U3copy_in_user.S index e28d34ac05af..674e232b0a6b 100644 --- a/arch/sparc64/lib/U3copy_in_user.S +++ b/arch/sparc64/lib/U3copy_in_user.S @@ -447,7 +447,7 @@ U3copy_in_user_toosmall: 2: VISEntryHalf ! MS+MS - /* Compute (len - (len % 8)) into %g2. This is guarenteed + /* Compute (len - (len % 8)) into %g2. This is guaranteed * to be nonzero. */ andn %o2, 0x7, %g2 ! A0 Group @@ -456,7 +456,7 @@ U3copy_in_user_toosmall: * one 8-byte longword past the end of src. It actually * does not, as %g2 is subtracted as loads are done from * src, so we always stop before running off the end. - * Also, we are guarenteed to have at least 0x10 bytes + * Also, we are guaranteed to have at least 0x10 bytes * to move here. */ sub %g2, 0x8, %g2 ! A0 Group (reg-dep) diff --git a/arch/sparc64/lib/U3copy_to_user.S b/arch/sparc64/lib/U3copy_to_user.S index 055a61dc04b2..6b421fc2f12e 100644 --- a/arch/sparc64/lib/U3copy_to_user.S +++ b/arch/sparc64/lib/U3copy_to_user.S @@ -463,7 +463,7 @@ U3copy_to_user_toosmall: 2: VISEntryHalf ! MS+MS - /* Compute (len - (len % 8)) into %g2. This is guarenteed + /* Compute (len - (len % 8)) into %g2. This is guaranteed * to be nonzero. */ andn %o2, 0x7, %g2 ! A0 Group @@ -472,7 +472,7 @@ U3copy_to_user_toosmall: * one 8-byte longword past the end of src. It actually * does not, as %g2 is subtracted as loads are done from * src, so we always stop before running off the end. - * Also, we are guarenteed to have at least 0x10 bytes + * Also, we are guaranteed to have at least 0x10 bytes * to move here. */ sub %g2, 0x8, %g2 ! A0 Group (reg-dep) diff --git a/arch/sparc64/lib/U3memcpy.S b/arch/sparc64/lib/U3memcpy.S index a2f6bffedff8..45994010399e 100644 --- a/arch/sparc64/lib/U3memcpy.S +++ b/arch/sparc64/lib/U3memcpy.S @@ -344,7 +344,7 @@ U3memcpy_toosmall: 2: VISEntryHalf ! MS+MS - /* Compute (len - (len % 8)) into %g2. This is guarenteed + /* Compute (len - (len % 8)) into %g2. This is guaranteed * to be nonzero. */ andn %o2, 0x7, %g2 ! A0 Group @@ -353,7 +353,7 @@ U3memcpy_toosmall: * one 8-byte longword past the end of src. It actually * does not, as %g2 is subtracted as loads are done from * src, so we always stop before running off the end. - * Also, we are guarenteed to have at least 0x10 bytes + * Also, we are guaranteed to have at least 0x10 bytes * to move here. */ sub %g2, 0x8, %g2 ! A0 Group (reg-dep) diff --git a/arch/sparc64/mm/hugetlbpage.c b/arch/sparc64/mm/hugetlbpage.c index 63895ce0202f..1c7138d4c174 100644 --- a/arch/sparc64/mm/hugetlbpage.c +++ b/arch/sparc64/mm/hugetlbpage.c @@ -25,6 +25,7 @@ spinlock_t htlbpage_lock = SPIN_LOCK_UNLOCKED; extern long htlbpagemem; static void zap_hugetlb_resources(struct vm_area_struct *); +void free_huge_page(struct page *page); #define MAX_ID 32 struct htlbpagekey { @@ -64,6 +65,7 @@ static struct page *alloc_hugetlb_page(void) spin_unlock(&htlbpage_lock); set_page_count(page, 1); + page->lru.prev = (void *)free_huge_page; memset(page_address(page), 0, HPAGE_SIZE); return page; diff --git a/arch/sparc64/prom/misc.c b/arch/sparc64/prom/misc.c index 7315aa68e963..19c44e97e9ee 100644 --- a/arch/sparc64/prom/misc.c +++ b/arch/sparc64/prom/misc.c @@ -142,7 +142,7 @@ int prom_getprev(void) return prom_prev; } -/* Install Linux trap table so PROM uses that instead of it's own. */ +/* Install Linux trap table so PROM uses that instead of its own. */ void prom_set_trap_table(unsigned long tba) { p1275_cmd("SUNW,set-trap-table", P1275_INOUT(1, 0), tba); diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c index 53a79e319b20..ed749a24988b 100644 --- a/arch/um/kernel/irq.c +++ b/arch/um/kernel/irq.c @@ -45,7 +45,7 @@ static void ack_none(unsigned int irq) { /* * 'what should we do if we get a hw irq event on an illegal vector'. - * each architecture has to answer this themselves, it doesnt deserve + * each architecture has to answer this themselves, it doesn't deserve * a generic callback i think. */ #if CONFIG_X86 diff --git a/arch/v850/kernel/irq.c b/arch/v850/kernel/irq.c index 57b933476b80..7433c7f46653 100644 --- a/arch/v850/kernel/irq.c +++ b/arch/v850/kernel/irq.c @@ -48,7 +48,7 @@ static void ack_none(unsigned int irq) { /* * 'what should we do if we get a hw irq event on an illegal vector'. - * each architecture has to answer this themselves, it doesnt deserve + * each architecture has to answer this themselves, it doesn't deserve * a generic callback i think. */ printk("received IRQ %d with unknown interrupt type\n", irq); diff --git a/arch/v850/kernel/ma.c b/arch/v850/kernel/ma.c index 15a5c8fec137..0a44ed532823 100644 --- a/arch/v850/kernel/ma.c +++ b/arch/v850/kernel/ma.c @@ -61,7 +61,7 @@ void ma_uart_pre_configure (unsigned chan, unsigned cflags, unsigned baud) specific chips may have more). */ if (chan < 2) { unsigned bits = 0x3 << (chan * 3); - /* Specify that the relevent pins on the chip should do + /* Specify that the relevant pins on the chip should do serial I/O, not direct I/O. */ MA_PORT4_PMC |= bits; /* Specify that we're using the UART, not the CSI device. */ diff --git a/arch/v850/kernel/rte_cb_multi.c b/arch/v850/kernel/rte_cb_multi.c index 13db814a8919..b423efaf6411 100644 --- a/arch/v850/kernel/rte_cb_multi.c +++ b/arch/v850/kernel/rte_cb_multi.c @@ -67,7 +67,7 @@ void __init multi_init (void) if ((word & 0xFC0) == 0x780) { /* A `jr' insn, fix up its offset (and yes, the - wierd half-word swapping is intentional). */ + weird half-word swapping is intentional). */ unsigned short hi = word & 0xFFFF; unsigned short lo = word >> 16; unsigned long udisp22 diff --git a/arch/v850/kernel/rte_ma1_cb.c b/arch/v850/kernel/rte_ma1_cb.c index d4fb14e9b6a4..f22edc1af8fb 100644 --- a/arch/v850/kernel/rte_ma1_cb.c +++ b/arch/v850/kernel/rte_ma1_cb.c @@ -93,7 +93,7 @@ void __init mach_init_irqs (void) /* Turn on the timer. */ NB85E_TIMER_C_TMCC0 (tc) |= NB85E_TIMER_C_TMCC0_CAE; - /* Make sure the relevent port0/port1 pins are assigned + /* Make sure the relevant port0/port1 pins are assigned interrupt duty. We used INTP001-INTP011 (don't screw with INTP000 because the monitor uses it). */ MA_PORT0_PMC |= 0x4; /* P02 (INTP001) in IRQ mode. */ diff --git a/arch/v850/kernel/time.c b/arch/v850/kernel/time.c index a1ecf796407c..5558f6ca4145 100644 --- a/arch/v850/kernel/time.c +++ b/arch/v850/kernel/time.c @@ -25,7 +25,7 @@ #include "mach.h" -u64 jiffies_64; +u64 jiffies_64 = INITIAL_JIFFIES; #define TICK_SIZE (tick_nsec / 1000) diff --git a/arch/x86_64/ia32/ia32_ioctl.c b/arch/x86_64/ia32/ia32_ioctl.c index a23409cf940f..9da5296018a5 100644 --- a/arch/x86_64/ia32/ia32_ioctl.c +++ b/arch/x86_64/ia32/ia32_ioctl.c @@ -3196,7 +3196,7 @@ out: * * But how to keep track of these kernel buffers? We'd need to either * keep track of them in some table _or_ know about usbdevicefs internals - * (ie. the exact layout of it's file private, which is actually defined + * (ie. the exact layout of its file private, which is actually defined * in linux/usbdevice_fs.h, the layout of the async queues are private to * devio.c) * diff --git a/arch/x86_64/kernel/apic.c b/arch/x86_64/kernel/apic.c index 0c2233e6d448..4f3520d829c9 100644 --- a/arch/x86_64/kernel/apic.c +++ b/arch/x86_64/kernel/apic.c @@ -292,7 +292,7 @@ void __init setup_local_APIC (void) __error_in_apic_c(); /* - * Double-check wether this APIC is really registered. + * Double-check whether this APIC is really registered. * This is meaningless in clustered apic mode, so we skip it. */ if (!clustered_apic_mode && @@ -948,7 +948,7 @@ void smp_local_timer_interrupt(struct pt_regs *regs) /* * Local APIC timer interrupt. This is the most natural way for doing * local interrupts, but local timer interrupts can be emulated by - * broadcast interrupts too. [in case the hw doesnt support APIC timers] + * broadcast interrupts too. [in case the hw doesn't support APIC timers] * * [ if a single-CPU system runs an SMP kernel then we call the local * interrupt as well. Thus we cannot inline the local irq ... ] diff --git a/arch/x86_64/kernel/bluesmoke.c b/arch/x86_64/kernel/bluesmoke.c index 12c339655be6..4a60fa6003a5 100644 --- a/arch/x86_64/kernel/bluesmoke.c +++ b/arch/x86_64/kernel/bluesmoke.c @@ -120,7 +120,7 @@ static void mce_checkregs (void *info) rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high); if ((low | high) != 0) { - printk (KERN_EMERG "MCE: The hardware reports a non fatal, correctable incident occured on CPU %d.\n", smp_processor_id()); + printk (KERN_EMERG "MCE: The hardware reports a non fatal, correctable incident occurred on CPU %d.\n", smp_processor_id()); printk (KERN_EMERG "Bank %d: %08x%08x\n", i, high, low); /* Scrub the error so we don't pick it up in MCE_RATE seconds time. */ diff --git a/arch/x86_64/kernel/e820.c b/arch/x86_64/kernel/e820.c index c82c2332b73b..2ead9043b5aa 100644 --- a/arch/x86_64/kernel/e820.c +++ b/arch/x86_64/kernel/e820.c @@ -204,7 +204,7 @@ void __init e820_reserve_resources(void) request_resource(&iomem_resource, res); if (e820.map[i].type == E820_RAM) { /* - * We dont't know which RAM region contains kernel data, + * We don't know which RAM region contains kernel data, * so we try it repeatedly and let the resource manager * test it. */ diff --git a/arch/x86_64/kernel/io_apic.c b/arch/x86_64/kernel/io_apic.c index 0eed1e0c5913..02be6caeecc8 100644 --- a/arch/x86_64/kernel/io_apic.c +++ b/arch/x86_64/kernel/io_apic.c @@ -685,7 +685,7 @@ void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector) entry.vector = vector; /* - * The timer IRQ doesnt have to know that behind the + * The timer IRQ doesn't have to know that behind the * scene we have a 8259A-master in AEOI mode ... */ irq_desc[0].handler = &ioapic_edge_irq_type; @@ -1539,7 +1539,7 @@ static inline void check_timer(void) printk(" failed.\n"); if (nmi_watchdog) { - printk(KERN_WARNING "timer doesnt work through the IO-APIC - disabling NMI Watchdog!\n"); + printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); nmi_watchdog = 0; } diff --git a/arch/x86_64/kernel/irq.c b/arch/x86_64/kernel/irq.c index ed43656b524e..a5c268e9ecc3 100644 --- a/arch/x86_64/kernel/irq.c +++ b/arch/x86_64/kernel/irq.c @@ -87,7 +87,7 @@ static void ack_none(unsigned int irq) { /* * 'what should we do if we get a hw irq event on an illegal vector'. - * each architecture has to answer this themselves, it doesnt deserve + * each architecture has to answer this themselves, it doesn't deserve * a generic callback i think. */ #if CONFIG_X86 diff --git a/arch/x86_64/kernel/nmi.c b/arch/x86_64/kernel/nmi.c index 50523c5f9d2d..0d749d4e8fef 100644 --- a/arch/x86_64/kernel/nmi.c +++ b/arch/x86_64/kernel/nmi.c @@ -228,7 +228,7 @@ static spinlock_t nmi_print_lock = SPIN_LOCK_UNLOCKED; * as these watchdog NMI IRQs are generated on every CPU, we only * have to check the current processor. * - * since NMIs dont listen to _any_ locks, we have to be extremely + * since NMIs don't listen to _any_ locks, we have to be extremely * careful not to rely on unsafe variables. The printk might lock * up though, so we have to break up any console locks first ... * [when there will be more tty-related locks, break them up diff --git a/arch/x86_64/kernel/pci-gart.c b/arch/x86_64/kernel/pci-gart.c index 695fa5e59264..bbd2fbdd6d26 100644 --- a/arch/x86_64/kernel/pci-gart.c +++ b/arch/x86_64/kernel/pci-gart.c @@ -437,6 +437,7 @@ static __init int init_k8_gatt(agp_kern_info *info) } flush_gart(); + global_flush_tlb(); printk("PCI-DMA: aperture base @ %x size %u KB\n", aper_base, aper_size>>10); return 0; diff --git a/arch/x86_64/kernel/smpboot.c b/arch/x86_64/kernel/smpboot.c index 30e8405fd42d..f6449d6194c5 100644 --- a/arch/x86_64/kernel/smpboot.c +++ b/arch/x86_64/kernel/smpboot.c @@ -104,7 +104,7 @@ static void __init smp_store_cpu_info(int id) /* * TSC synchronization. * - * We first check wether all CPUs have their TSC's synchronized, + * We first check whether all CPUs have their TSC's synchronized, * then we print a warning if not, and always resync. */ @@ -774,7 +774,7 @@ static void __init smp_boot_cpus(unsigned int max_cpus) } /* - * If we couldnt find an SMP configuration at boot time, + * If we couldn't find an SMP configuration at boot time, * get out of here now! */ if (!smp_found_config) { diff --git a/arch/x86_64/kernel/time.c b/arch/x86_64/kernel/time.c index 5abb00455897..31ec31fc6408 100644 --- a/arch/x86_64/kernel/time.c +++ b/arch/x86_64/kernel/time.c @@ -30,7 +30,7 @@ #include <asm/apic.h> #endif -u64 jiffies_64; +u64 jiffies_64; extern int using_apic_timer; diff --git a/arch/x86_64/mm/ioremap.c b/arch/x86_64/mm/ioremap.c index 2f10ba92beaf..f0503c3badc2 100644 --- a/arch/x86_64/mm/ioremap.c +++ b/arch/x86_64/mm/ioremap.c @@ -205,6 +205,7 @@ void *ioremap_nocache (unsigned long phys_addr, unsigned long size) iounmap(p); p = NULL; } + global_flush_tlb(); } return p; @@ -226,6 +227,7 @@ void iounmap(void *addr) change_page_attr(virt_to_page(__va(p->phys_addr)), p->size >> PAGE_SHIFT, PAGE_KERNEL); + global_flush_tlb(); } kfree(p); } |