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| author | André Draszik <andre.draszik@linaro.org> | 2025-11-14 14:10:59 +0000 |
|---|---|---|
| committer | Lee Jones <lee@kernel.org> | 2025-11-20 10:29:20 +0000 |
| commit | ee19b52c31b3b111f140c1affd88eca1ed11edd0 (patch) | |
| tree | 457eb318eac268bd32564b13103f5257be096183 /drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | |
| parent | 56c1245d51faab70bf68cc3a5cd3925768e6375b (diff) | |
mfd: sec: Use chained IRQs for s2mpg10
On S2MPG10 (and similar like S2MPG11), top-level interrupt status and
mask registers exist which need to be unmasked to get the PMIC
interrupts. This additional status doesn't seem to exist on other PMICs
in the S2MP* family, and the S2MPG10 driver is manually dealing with
masking and unmasking currently.
The correct approach here is to register this hierarchy as chained
interrupts, though, without any additional manual steps. Doing so will
also simplify addition of other, similar, PMICs (like S2MPG11) in the
future.
Update the driver to do just that.
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20251114-s2mpg10-chained-irq-v1-1-34ddfa49c4cd@linaro.org
Signed-off-by: Lee Jones <lee@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c')
0 files changed, 0 insertions, 0 deletions