diff options
| author | Stanley.Yang <Stanley.Yang@amd.com> | 2023-06-12 15:25:05 +0800 | 
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2023-06-15 11:06:59 -0400 | 
| commit | 38298ce6fc35c65ba1364e4221a289dfa07bf5ea (patch) | |
| tree | 058c3741275f97fafa0e8f0dc53b93470ba54b91 /drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | |
| parent | 6fac3964a9092f0ac797cb30cce5fd44f80e5a09 (diff) | |
drm/amdgpu: Optimize checking ras supported
Using "is_app_apu" to identify device in the native
APU mode or carveout mode.
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 34 | 
1 files changed, 19 insertions, 15 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index 1edf8e6aeb16..db0d94ca4ffc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -169,27 +169,31 @@ int amdgpu_umc_poison_handler(struct amdgpu_device *adev, bool reset)  {  	int ret = AMDGPU_RAS_SUCCESS; -	if (!amdgpu_sriov_vf(adev)) { -		if (!adev->gmc.xgmi.connected_to_cpu) { -			struct ras_err_data err_data = {0, 0, 0, NULL}; -			struct ras_common_if head = { -				.block = AMDGPU_RAS_BLOCK__UMC, -			}; -			struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head); - -			ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset); - -			if (ret == AMDGPU_RAS_SUCCESS && obj) { -				obj->err_data.ue_count += err_data.ue_count; -				obj->err_data.ce_count += err_data.ce_count; -			} -		} else if (reset) { +	if (adev->gmc.xgmi.connected_to_cpu || +		adev->gmc.is_app_apu) { +		if (reset) {  			/* MCA poison handler is only responsible for GPU reset,  			 * let MCA notifier do page retirement.  			 */  			kgd2kfd_set_sram_ecc_flag(adev->kfd.dev);  			amdgpu_ras_reset_gpu(adev);  		} +		return ret; +	} + +	if (!amdgpu_sriov_vf(adev)) { +		struct ras_err_data err_data = {0, 0, 0, NULL}; +		struct ras_common_if head = { +			.block = AMDGPU_RAS_BLOCK__UMC, +		}; +		struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head); + +		ret = amdgpu_umc_do_page_retirement(adev, &err_data, NULL, reset); + +		if (ret == AMDGPU_RAS_SUCCESS && obj) { +			obj->err_data.ue_count += err_data.ue_count; +			obj->err_data.ce_count += err_data.ce_count; +		}  	} else {  		if (adev->virt.ops && adev->virt.ops->ras_poison_handler)  			adev->virt.ops->ras_poison_handler(adev);  | 
