diff options
| author | Jack Xiao <Jack.Xiao@amd.com> | 2025-07-10 16:42:01 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-12-16 13:29:01 -0500 |
| commit | b9a0716a93abb03be79bdb52d9ac4bb98053f06e (patch) | |
| tree | ad0da045a92ab3cbaaf88ac3068cf61f8d4d860c /drivers/gpu/drm/amd/amdgpu | |
| parent | c63a52018675e75a19a04c2417ffaaf0ab1856f5 (diff) | |
drm/amdgpu/mes_v12_1: fix mes access xcd register
Fix to use local register offset inside die for mes fw accessing
local/remote xcd register.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/mes_v12_1.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c index 6a454d5eb1a3..b0b1df5f1d4b 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c @@ -546,6 +546,10 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes, mes_v12_1_get_rrmt(input->read_reg.reg_offset, GET_INST(GC, input->xcc_id), &misc_pkt.read_reg.rrmt_opt); + if (misc_pkt.read_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) { + misc_pkt.read_reg.reg_offset = + NORMALIZE_XCC_REG_OFFSET(misc_pkt.read_reg.reg_offset); + } break; case MES_MISC_OP_WRITE_REG: misc_pkt.opcode = MESAPI_MISC__WRITE_REG; @@ -554,6 +558,10 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes, mes_v12_1_get_rrmt(input->write_reg.reg_offset, GET_INST(GC, input->xcc_id), &misc_pkt.write_reg.rrmt_opt); + if (misc_pkt.write_reg.rrmt_opt.mode != MES_RRMT_MODE_REMOTE_MID) { + misc_pkt.write_reg.reg_offset = + NORMALIZE_XCC_REG_OFFSET(misc_pkt.write_reg.reg_offset); + } break; case MES_MISC_OP_WRM_REG_WAIT: misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; @@ -565,6 +573,10 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes, mes_v12_1_get_rrmt(input->wrm_reg.reg0, GET_INST(GC, input->xcc_id), &misc_pkt.wait_reg_mem.rrmt_opt1); + if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) { + misc_pkt.wait_reg_mem.reg_offset1 = + NORMALIZE_XCC_REG_OFFSET(misc_pkt.wait_reg_mem.reg_offset1); + } break; case MES_MISC_OP_WRM_REG_WR_WAIT: misc_pkt.opcode = MESAPI_MISC__WAIT_REG_MEM; @@ -579,6 +591,14 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes, mes_v12_1_get_rrmt(input->wrm_reg.reg1, GET_INST(GC, input->xcc_id), &misc_pkt.wait_reg_mem.rrmt_opt2); + if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) { + misc_pkt.wait_reg_mem.reg_offset1 = + NORMALIZE_XCC_REG_OFFSET(misc_pkt.wait_reg_mem.reg_offset1); + } + if (misc_pkt.wait_reg_mem.rrmt_opt2.mode != MES_RRMT_MODE_REMOTE_MID) { + misc_pkt.wait_reg_mem.reg_offset2 = + NORMALIZE_XCC_REG_OFFSET(misc_pkt.wait_reg_mem.reg_offset2); + } break; case MES_MISC_OP_SET_SHADER_DEBUGGER: pipe = AMDGPU_MES_SCHED_PIPE; |