diff options
| author | Hawking Zhang <Hawking.Zhang@amd.com> | 2025-08-29 13:39:11 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2025-12-08 13:56:35 -0500 |
| commit | 91c93c090dfc58a3dcc97bb5e43b27892e043e9f (patch) | |
| tree | 70d7a4676cdbd4826f8bf7593cf64e722c33e9f1 /drivers/gpu/drm/amd/include | |
| parent | 755b5591739cc5c66158da596cf30853b613af5b (diff) | |
drm/amdgpu: Add gc v12_1_0 ip headers v4
Add header files for gc v12_1_0 register offsets
and shift masks
v2: Update gc v12_1_0 ip headers
v3: Update gc v12_1_0 ip headers
v4, v5: Clean up registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h | 12407 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h | 44620 |
2 files changed, 57027 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h new file mode 100644 index 000000000000..69731dcc324a --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h @@ -0,0 +1,12407 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_12_1_0_OFFSET_HEADER +#define _gc_12_1_0_OFFSET_HEADER + + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmadec +// base address: 0x4980 +#define regSDMA0_SDMA_DEC_START 0x0000 +#define regSDMA0_SDMA_DEC_START_BASE_IDX 0 +#define regSDMA0_SDMA_MCU_MISC_CNTL 0x0001 +#define regSDMA0_SDMA_MCU_MISC_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_UCODE_REV 0x0003 +#define regSDMA0_SDMA_UCODE_REV_BASE_IDX 0 +#define regSDMA0_SDMA_GLOBAL_TIMESTAMP_LO 0x0005 +#define regSDMA0_SDMA_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 +#define regSDMA0_SDMA_GLOBAL_TIMESTAMP_HI 0x0006 +#define regSDMA0_SDMA_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 +#define regSDMA0_SDMA_POWER_CNTL 0x000c +#define regSDMA0_SDMA_POWER_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_CNTL 0x000d +#define regSDMA0_SDMA_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_CHICKEN_BITS 0x000e +#define regSDMA0_SDMA_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA0_SDMA_CACHE_CNTL 0x000f +#define regSDMA0_SDMA_CACHE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_RB_RPTR_FETCH 0x0020 +#define regSDMA0_SDMA_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA0_SDMA_RB_RPTR_FETCH_HI 0x0021 +#define regSDMA0_SDMA_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA0_SDMA_IB_OFFSET_FETCH 0x0022 +#define regSDMA0_SDMA_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA0_SDMA_PROGRAM 0x0023 +#define regSDMA0_SDMA_PROGRAM_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS_REG 0x0024 +#define regSDMA0_SDMA_STATUS_REG_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS1_REG 0x0025 +#define regSDMA0_SDMA_STATUS1_REG_BASE_IDX 0 +#define regSDMA0_SDMA_CNTL1 0x0026 +#define regSDMA0_SDMA_CNTL1_BASE_IDX 0 +#define regSDMA0_SDMA_HBM_PAGE_CONFIG 0x0027 +#define regSDMA0_SDMA_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA0_SDMA_FREEZE 0x0028 +#define regSDMA0_SDMA_FREEZE_BASE_IDX 0 +#define regSDMA0_SDMA_PROCESS_QUANTUM0 0x0029 +#define regSDMA0_SDMA_PROCESS_QUANTUM0_BASE_IDX 0 +#define regSDMA0_SDMA_PROCESS_QUANTUM1 0x002a +#define regSDMA0_SDMA_PROCESS_QUANTUM1_BASE_IDX 0 +#define regSDMA0_SDMA_WATCHDOG_CNTL 0x002b +#define regSDMA0_SDMA_WATCHDOG_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE_STATUS0 0x002c +#define regSDMA0_SDMA_QUEUE_STATUS0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE_STATUS1 0x002d +#define regSDMA0_SDMA_QUEUE_STATUS1_BASE_IDX 0 +#define regSDMA0_SDMA_ID 0x002e +#define regSDMA0_SDMA_ID_BASE_IDX 0 +#define regSDMA0_SDMA_VERSION 0x002f +#define regSDMA0_SDMA_VERSION_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS2_REG 0x0030 +#define regSDMA0_SDMA_STATUS2_REG_BASE_IDX 0 +#define regSDMA0_SDMA_ATOMIC_CNTL 0x0031 +#define regSDMA0_SDMA_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_ATOMIC_PERMS_CNTL 0x0032 +#define regSDMA0_SDMA_ATOMIC_PERMS_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_ATOMIC_PREOP_LO 0x0033 +#define regSDMA0_SDMA_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA0_SDMA_ATOMIC_PREOP_HI 0x0034 +#define regSDMA0_SDMA_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA0_SDMA_DCC_CNTL 0x0035 +#define regSDMA0_SDMA_DCC_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_WARMUPL2_CNTL 0x0036 +#define regSDMA0_SDMA_UTCL1_WARMUPL2_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_CNTL 0x0037 +#define regSDMA0_SDMA_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_WATERMK 0x0038 +#define regSDMA0_SDMA_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_TIMEOUT 0x0039 +#define regSDMA0_SDMA_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_PAGE 0x003a +#define regSDMA0_SDMA_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA0_SDMA_EXTERNAL_FROZEN 0x003b +#define regSDMA0_SDMA_EXTERNAL_FROZEN_BASE_IDX 0 +#define regSDMA0_SDMA_FREEZE_TRIGGER 0x003c +#define regSDMA0_SDMA_FREEZE_TRIGGER_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_CACHE_CNTL 0x0040 +#define regSDMA0_SDMA_UTCL1_CACHE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_RD_STATUS 0x0041 +#define regSDMA0_SDMA_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_WR_STATUS 0x0042 +#define regSDMA0_SDMA_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_INV0 0x0043 +#define regSDMA0_SDMA_UTCL1_INV0_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_INV1 0x0044 +#define regSDMA0_SDMA_UTCL1_INV1_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_INV2 0x0045 +#define regSDMA0_SDMA_UTCL1_INV2_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_RD_XNACK0 0x0046 +#define regSDMA0_SDMA_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_RD_XNACK1 0x0047 +#define regSDMA0_SDMA_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_WR_XNACK0 0x0048 +#define regSDMA0_SDMA_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA0_SDMA_UTCL1_WR_XNACK1 0x0049 +#define regSDMA0_SDMA_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA0_SDMA_CHICKEN_BITS_2 0x004a +#define regSDMA0_SDMA_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS3_REG 0x004b +#define regSDMA0_SDMA_STATUS3_REG_BASE_IDX 0 +#define regSDMA0_SDMA_GLOBAL_QUANTUM 0x004c +#define regSDMA0_SDMA_GLOBAL_QUANTUM_BASE_IDX 0 +#define regSDMA0_SDMA_ERROR_LOG 0x004d +#define regSDMA0_SDMA_ERROR_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_PUB_DUMMY_REG0 0x004e +#define regSDMA0_SDMA_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA0_SDMA_PUB_DUMMY_REG1 0x004f +#define regSDMA0_SDMA_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_PUB_DUMMY_REG2 0x0050 +#define regSDMA0_SDMA_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_PUB_DUMMY_REG3 0x0051 +#define regSDMA0_SDMA_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA0_SDMA_MCU_COUNTER 0x0052 +#define regSDMA0_SDMA_MCU_COUNTER_BASE_IDX 0 +#define regSDMA0_SDMA_CRD_CNTL 0x0053 +#define regSDMA0_SDMA_CRD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_RLC_CGCG_CTRL 0x0054 +#define regSDMA0_SDMA_RLC_CGCG_CTRL_BASE_IDX 0 +#define regSDMA0_SDMA_GPU_IOV_VIOLATION_LOG 0x0055 +#define regSDMA0_SDMA_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_AQL_STATUS 0x0057 +#define regSDMA0_SDMA_AQL_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_TLBI_GCR_CNTL 0x0060 +#define regSDMA0_SDMA_TLBI_GCR_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_INT_STATUS 0x0061 +#define regSDMA0_SDMA_INT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_GPU_IOV_VIOLATION_LOG2 0x0062 +#define regSDMA0_SDMA_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 +#define regSDMA0_SDMA_INVALID_ADDR_LO 0x0063 +#define regSDMA0_SDMA_INVALID_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_INVALID_ADDR_HI 0x0064 +#define regSDMA0_SDMA_INVALID_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_INVALID_ADDR_SOURCE 0x0065 +#define regSDMA0_SDMA_INVALID_ADDR_SOURCE_BASE_IDX 0 +#define regSDMA0_SDMA_CLOCK_GATING_STATUS 0x0066 +#define regSDMA0_SDMA_CLOCK_GATING_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS4_REG 0x0067 +#define regSDMA0_SDMA_STATUS4_REG_BASE_IDX 0 +#define regSDMA0_SDMA_SCRATCH_RAM_DATA 0x0068 +#define regSDMA0_SDMA_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA0_SDMA_SCRATCH_RAM_ADDR 0x0069 +#define regSDMA0_SDMA_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA0_SDMA_TIMESTAMP_CNTL 0x006a +#define regSDMA0_SDMA_TIMESTAMP_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS5_REG 0x006b +#define regSDMA0_SDMA_STATUS5_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE_RESET_REQ 0x006c +#define regSDMA0_SDMA_QUEUE_RESET_REQ_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE_DEQUEUE_REQUEST 0x006d +#define regSDMA0_SDMA_QUEUE_DEQUEUE_REQUEST_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS6_REG 0x006e +#define regSDMA0_SDMA_STATUS6_REG_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS7_REG 0x006f +#define regSDMA0_SDMA_STATUS7_REG_BASE_IDX 0 +#define regSDMA0_SDMA_STATUS8_REG 0x0070 +#define regSDMA0_SDMA_STATUS8_REG_BASE_IDX 0 +#define regSDMA0_SDMA_CE_CTRL 0x0071 +#define regSDMA0_SDMA_CE_CTRL_BASE_IDX 0 +#define regSDMA0_SDMA_RAS_STATUS 0x0072 +#define regSDMA0_SDMA_RAS_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_POISON_INFO 0x0073 +#define regSDMA0_SDMA_POISON_INFO_BASE_IDX 0 +#define regSDMA0_SDMA_MEMHUB_CNTL 0x0074 +#define regSDMA0_SDMA_MEMHUB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_CNTL 0x0200 +#define regSDMA0_SDMA_QUEUE0_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_BASE 0x0201 +#define regSDMA0_SDMA_QUEUE0_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_BASE_HI 0x0202 +#define regSDMA0_SDMA_QUEUE0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR 0x0203 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_HI 0x0204 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR 0x0205 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_HI 0x0206 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO 0x0207 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI 0x0208 +#define regSDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_CNTL 0x0209 +#define regSDMA0_SDMA_QUEUE0_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_RPTR 0x020a +#define regSDMA0_SDMA_QUEUE0_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_OFFSET 0x020b +#define regSDMA0_SDMA_QUEUE0_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_BASE_LO 0x020c +#define regSDMA0_SDMA_QUEUE0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_BASE_HI 0x020d +#define regSDMA0_SDMA_QUEUE0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_SIZE 0x020e +#define regSDMA0_SDMA_QUEUE0_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DOORBELL 0x020f +#define regSDMA0_SDMA_QUEUE0_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DOORBELL_LOG 0x0210 +#define regSDMA0_SDMA_QUEUE0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DOORBELL_OFFSET 0x0211 +#define regSDMA0_SDMA_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_CSA_ADDR_LO 0x0212 +#define regSDMA0_SDMA_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_CSA_ADDR_HI 0x0213 +#define regSDMA0_SDMA_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_SCHEDULE_CNTL 0x0214 +#define regSDMA0_SDMA_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_IB_SUB_REMAIN 0x0215 +#define regSDMA0_SDMA_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_PREEMPT 0x0216 +#define regSDMA0_SDMA_QUEUE0_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG 0x0217 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x0218 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x0219 +#define regSDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_RB_AQL_CNTL 0x021a +#define regSDMA0_SDMA_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE 0x021b +#define regSDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS 0x021e +#define regSDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_CNTL 0x021f +#define regSDMA0_SDMA_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA0 0x0220 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA1 0x0221 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA2 0x0222 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA3 0x0223 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA4 0x0224 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA5 0x0225 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA6 0x0226 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA7 0x0227 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA8 0x0228 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA9 0x0229 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA10 0x022a +#define regSDMA0_SDMA_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_UTILIZATION_LO 0x022b +#define regSDMA0_SDMA_QUEUE0_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_UTILIZATION_HI 0x022c +#define regSDMA0_SDMA_QUEUE0_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_WAIT_UNSATISFIED_THD 0x022d +#define regSDMA0_SDMA_QUEUE0_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_LO 0x022e +#define regSDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_HI 0x022f +#define regSDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_MQD_CONTROL 0x0230 +#define regSDMA0_SDMA_QUEUE0_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_CONTEXT_STATUS 0x0231 +#define regSDMA0_SDMA_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG1 0x0232 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG2 0x0233 +#define regSDMA0_SDMA_QUEUE0_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_CNTL 0x023c +#define regSDMA0_SDMA_QUEUE1_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_BASE 0x023d +#define regSDMA0_SDMA_QUEUE1_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_BASE_HI 0x023e +#define regSDMA0_SDMA_QUEUE1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR 0x023f +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_HI 0x0240 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR 0x0241 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_HI 0x0242 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_LO 0x0243 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_HI 0x0244 +#define regSDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_CNTL 0x0245 +#define regSDMA0_SDMA_QUEUE1_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_RPTR 0x0246 +#define regSDMA0_SDMA_QUEUE1_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_OFFSET 0x0247 +#define regSDMA0_SDMA_QUEUE1_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_BASE_LO 0x0248 +#define regSDMA0_SDMA_QUEUE1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_BASE_HI 0x0249 +#define regSDMA0_SDMA_QUEUE1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_SIZE 0x024a +#define regSDMA0_SDMA_QUEUE1_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DOORBELL 0x024b +#define regSDMA0_SDMA_QUEUE1_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DOORBELL_LOG 0x024c +#define regSDMA0_SDMA_QUEUE1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DOORBELL_OFFSET 0x024d +#define regSDMA0_SDMA_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_CSA_ADDR_LO 0x024e +#define regSDMA0_SDMA_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_CSA_ADDR_HI 0x024f +#define regSDMA0_SDMA_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_SCHEDULE_CNTL 0x0250 +#define regSDMA0_SDMA_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_IB_SUB_REMAIN 0x0251 +#define regSDMA0_SDMA_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_PREEMPT 0x0252 +#define regSDMA0_SDMA_QUEUE1_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG 0x0253 +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x0254 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x0255 +#define regSDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_RB_AQL_CNTL 0x0256 +#define regSDMA0_SDMA_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MINOR_PTR_UPDATE 0x0257 +#define regSDMA0_SDMA_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS 0x025a +#define regSDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_CNTL 0x025b +#define regSDMA0_SDMA_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA0 0x025c +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA1 0x025d +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA2 0x025e +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA3 0x025f +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA4 0x0260 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA5 0x0261 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA6 0x0262 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA7 0x0263 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA8 0x0264 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA9 0x0265 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA10 0x0266 +#define regSDMA0_SDMA_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_UTILIZATION_LO 0x0267 +#define regSDMA0_SDMA_QUEUE1_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_UTILIZATION_HI 0x0268 +#define regSDMA0_SDMA_QUEUE1_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_WAIT_UNSATISFIED_THD 0x0269 +#define regSDMA0_SDMA_QUEUE1_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_LO 0x026a +#define regSDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_HI 0x026b +#define regSDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_MQD_CONTROL 0x026c +#define regSDMA0_SDMA_QUEUE1_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_CONTEXT_STATUS 0x026d +#define regSDMA0_SDMA_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG1 0x026e +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG2 0x026f +#define regSDMA0_SDMA_QUEUE1_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_CNTL 0x0278 +#define regSDMA0_SDMA_QUEUE2_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_BASE 0x0279 +#define regSDMA0_SDMA_QUEUE2_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_BASE_HI 0x027a +#define regSDMA0_SDMA_QUEUE2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_RPTR 0x027b +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_HI 0x027c +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR 0x027d +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_HI 0x027e +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_LO 0x027f +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_HI 0x0280 +#define regSDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_CNTL 0x0281 +#define regSDMA0_SDMA_QUEUE2_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_RPTR 0x0282 +#define regSDMA0_SDMA_QUEUE2_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_OFFSET 0x0283 +#define regSDMA0_SDMA_QUEUE2_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_BASE_LO 0x0284 +#define regSDMA0_SDMA_QUEUE2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_BASE_HI 0x0285 +#define regSDMA0_SDMA_QUEUE2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_SIZE 0x0286 +#define regSDMA0_SDMA_QUEUE2_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DOORBELL 0x0287 +#define regSDMA0_SDMA_QUEUE2_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DOORBELL_LOG 0x0288 +#define regSDMA0_SDMA_QUEUE2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DOORBELL_OFFSET 0x0289 +#define regSDMA0_SDMA_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_CSA_ADDR_LO 0x028a +#define regSDMA0_SDMA_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_CSA_ADDR_HI 0x028b +#define regSDMA0_SDMA_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_SCHEDULE_CNTL 0x028c +#define regSDMA0_SDMA_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_IB_SUB_REMAIN 0x028d +#define regSDMA0_SDMA_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_PREEMPT 0x028e +#define regSDMA0_SDMA_QUEUE2_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG 0x028f +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0290 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0291 +#define regSDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_RB_AQL_CNTL 0x0292 +#define regSDMA0_SDMA_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MINOR_PTR_UPDATE 0x0293 +#define regSDMA0_SDMA_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS 0x0296 +#define regSDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_CNTL 0x0297 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA0 0x0298 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA1 0x0299 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA2 0x029a +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA3 0x029b +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA4 0x029c +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA5 0x029d +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA6 0x029e +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA7 0x029f +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA8 0x02a0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA9 0x02a1 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA10 0x02a2 +#define regSDMA0_SDMA_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_UTILIZATION_LO 0x02a3 +#define regSDMA0_SDMA_QUEUE2_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_UTILIZATION_HI 0x02a4 +#define regSDMA0_SDMA_QUEUE2_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_WAIT_UNSATISFIED_THD 0x02a5 +#define regSDMA0_SDMA_QUEUE2_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_LO 0x02a6 +#define regSDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_HI 0x02a7 +#define regSDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_MQD_CONTROL 0x02a8 +#define regSDMA0_SDMA_QUEUE2_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_CONTEXT_STATUS 0x02a9 +#define regSDMA0_SDMA_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG1 0x02aa +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG2 0x02ab +#define regSDMA0_SDMA_QUEUE2_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_CNTL 0x02b4 +#define regSDMA0_SDMA_QUEUE3_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_BASE 0x02b5 +#define regSDMA0_SDMA_QUEUE3_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_BASE_HI 0x02b6 +#define regSDMA0_SDMA_QUEUE3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR 0x02b7 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_HI 0x02b8 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_WPTR 0x02b9 +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_HI 0x02ba +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_LO 0x02bb +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_HI 0x02bc +#define regSDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_CNTL 0x02bd +#define regSDMA0_SDMA_QUEUE3_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_RPTR 0x02be +#define regSDMA0_SDMA_QUEUE3_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_OFFSET 0x02bf +#define regSDMA0_SDMA_QUEUE3_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_BASE_LO 0x02c0 +#define regSDMA0_SDMA_QUEUE3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_BASE_HI 0x02c1 +#define regSDMA0_SDMA_QUEUE3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_SIZE 0x02c2 +#define regSDMA0_SDMA_QUEUE3_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DOORBELL 0x02c3 +#define regSDMA0_SDMA_QUEUE3_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DOORBELL_LOG 0x02c4 +#define regSDMA0_SDMA_QUEUE3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DOORBELL_OFFSET 0x02c5 +#define regSDMA0_SDMA_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_CSA_ADDR_LO 0x02c6 +#define regSDMA0_SDMA_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_CSA_ADDR_HI 0x02c7 +#define regSDMA0_SDMA_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_SCHEDULE_CNTL 0x02c8 +#define regSDMA0_SDMA_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_IB_SUB_REMAIN 0x02c9 +#define regSDMA0_SDMA_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_PREEMPT 0x02ca +#define regSDMA0_SDMA_QUEUE3_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG 0x02cb +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x02cc +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x02cd +#define regSDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_RB_AQL_CNTL 0x02ce +#define regSDMA0_SDMA_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MINOR_PTR_UPDATE 0x02cf +#define regSDMA0_SDMA_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS 0x02d2 +#define regSDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_CNTL 0x02d3 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA0 0x02d4 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA1 0x02d5 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA2 0x02d6 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA3 0x02d7 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA4 0x02d8 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA5 0x02d9 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA6 0x02da +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA7 0x02db +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA8 0x02dc +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA9 0x02dd +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA10 0x02de +#define regSDMA0_SDMA_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_UTILIZATION_LO 0x02df +#define regSDMA0_SDMA_QUEUE3_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_UTILIZATION_HI 0x02e0 +#define regSDMA0_SDMA_QUEUE3_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_WAIT_UNSATISFIED_THD 0x02e1 +#define regSDMA0_SDMA_QUEUE3_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_LO 0x02e2 +#define regSDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_HI 0x02e3 +#define regSDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_MQD_CONTROL 0x02e4 +#define regSDMA0_SDMA_QUEUE3_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_CONTEXT_STATUS 0x02e5 +#define regSDMA0_SDMA_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG1 0x02e6 +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG2 0x02e7 +#define regSDMA0_SDMA_QUEUE3_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_CNTL 0x02f0 +#define regSDMA0_SDMA_QUEUE4_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_BASE 0x02f1 +#define regSDMA0_SDMA_QUEUE4_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_BASE_HI 0x02f2 +#define regSDMA0_SDMA_QUEUE4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR 0x02f3 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_HI 0x02f4 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR 0x02f5 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_HI 0x02f6 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_LO 0x02f7 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_HI 0x02f8 +#define regSDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_CNTL 0x02f9 +#define regSDMA0_SDMA_QUEUE4_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_RPTR 0x02fa +#define regSDMA0_SDMA_QUEUE4_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_OFFSET 0x02fb +#define regSDMA0_SDMA_QUEUE4_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_BASE_LO 0x02fc +#define regSDMA0_SDMA_QUEUE4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_BASE_HI 0x02fd +#define regSDMA0_SDMA_QUEUE4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_SIZE 0x02fe +#define regSDMA0_SDMA_QUEUE4_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DOORBELL 0x02ff +#define regSDMA0_SDMA_QUEUE4_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DOORBELL_LOG 0x0300 +#define regSDMA0_SDMA_QUEUE4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DOORBELL_OFFSET 0x0301 +#define regSDMA0_SDMA_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_CSA_ADDR_LO 0x0302 +#define regSDMA0_SDMA_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_CSA_ADDR_HI 0x0303 +#define regSDMA0_SDMA_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_SCHEDULE_CNTL 0x0304 +#define regSDMA0_SDMA_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_IB_SUB_REMAIN 0x0305 +#define regSDMA0_SDMA_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_PREEMPT 0x0306 +#define regSDMA0_SDMA_QUEUE4_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG 0x0307 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0308 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0309 +#define regSDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_RB_AQL_CNTL 0x030a +#define regSDMA0_SDMA_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MINOR_PTR_UPDATE 0x030b +#define regSDMA0_SDMA_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS 0x030e +#define regSDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_CNTL 0x030f +#define regSDMA0_SDMA_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA0 0x0310 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA1 0x0311 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA2 0x0312 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA3 0x0313 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA4 0x0314 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA5 0x0315 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA6 0x0316 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA7 0x0317 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA8 0x0318 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA9 0x0319 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA10 0x031a +#define regSDMA0_SDMA_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_UTILIZATION_LO 0x031b +#define regSDMA0_SDMA_QUEUE4_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_UTILIZATION_HI 0x031c +#define regSDMA0_SDMA_QUEUE4_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_WAIT_UNSATISFIED_THD 0x031d +#define regSDMA0_SDMA_QUEUE4_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_LO 0x031e +#define regSDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_HI 0x031f +#define regSDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_MQD_CONTROL 0x0320 +#define regSDMA0_SDMA_QUEUE4_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_CONTEXT_STATUS 0x0321 +#define regSDMA0_SDMA_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG1 0x0322 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG2 0x0323 +#define regSDMA0_SDMA_QUEUE4_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_CNTL 0x032c +#define regSDMA0_SDMA_QUEUE5_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_BASE 0x032d +#define regSDMA0_SDMA_QUEUE5_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_BASE_HI 0x032e +#define regSDMA0_SDMA_QUEUE5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR 0x032f +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_HI 0x0330 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR 0x0331 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_HI 0x0332 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_LO 0x0333 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_HI 0x0334 +#define regSDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_CNTL 0x0335 +#define regSDMA0_SDMA_QUEUE5_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_RPTR 0x0336 +#define regSDMA0_SDMA_QUEUE5_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_OFFSET 0x0337 +#define regSDMA0_SDMA_QUEUE5_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_BASE_LO 0x0338 +#define regSDMA0_SDMA_QUEUE5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_BASE_HI 0x0339 +#define regSDMA0_SDMA_QUEUE5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_SIZE 0x033a +#define regSDMA0_SDMA_QUEUE5_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DOORBELL 0x033b +#define regSDMA0_SDMA_QUEUE5_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DOORBELL_LOG 0x033c +#define regSDMA0_SDMA_QUEUE5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DOORBELL_OFFSET 0x033d +#define regSDMA0_SDMA_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_CSA_ADDR_LO 0x033e +#define regSDMA0_SDMA_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_CSA_ADDR_HI 0x033f +#define regSDMA0_SDMA_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_SCHEDULE_CNTL 0x0340 +#define regSDMA0_SDMA_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_IB_SUB_REMAIN 0x0341 +#define regSDMA0_SDMA_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_PREEMPT 0x0342 +#define regSDMA0_SDMA_QUEUE5_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG 0x0343 +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x0344 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x0345 +#define regSDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_RB_AQL_CNTL 0x0346 +#define regSDMA0_SDMA_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MINOR_PTR_UPDATE 0x0347 +#define regSDMA0_SDMA_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS 0x034a +#define regSDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_CNTL 0x034b +#define regSDMA0_SDMA_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA0 0x034c +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA1 0x034d +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA2 0x034e +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA3 0x034f +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA4 0x0350 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA5 0x0351 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA6 0x0352 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA7 0x0353 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA8 0x0354 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA9 0x0355 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA10 0x0356 +#define regSDMA0_SDMA_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_UTILIZATION_LO 0x0357 +#define regSDMA0_SDMA_QUEUE5_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_UTILIZATION_HI 0x0358 +#define regSDMA0_SDMA_QUEUE5_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_WAIT_UNSATISFIED_THD 0x0359 +#define regSDMA0_SDMA_QUEUE5_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_LO 0x035a +#define regSDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_HI 0x035b +#define regSDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_MQD_CONTROL 0x035c +#define regSDMA0_SDMA_QUEUE5_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_CONTEXT_STATUS 0x035d +#define regSDMA0_SDMA_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG1 0x035e +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG2 0x035f +#define regSDMA0_SDMA_QUEUE5_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_CNTL 0x0368 +#define regSDMA0_SDMA_QUEUE6_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_BASE 0x0369 +#define regSDMA0_SDMA_QUEUE6_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_BASE_HI 0x036a +#define regSDMA0_SDMA_QUEUE6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_RPTR 0x036b +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_HI 0x036c +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR 0x036d +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_HI 0x036e +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_LO 0x036f +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_HI 0x0370 +#define regSDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_CNTL 0x0371 +#define regSDMA0_SDMA_QUEUE6_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_RPTR 0x0372 +#define regSDMA0_SDMA_QUEUE6_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_OFFSET 0x0373 +#define regSDMA0_SDMA_QUEUE6_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_BASE_LO 0x0374 +#define regSDMA0_SDMA_QUEUE6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_BASE_HI 0x0375 +#define regSDMA0_SDMA_QUEUE6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_SIZE 0x0376 +#define regSDMA0_SDMA_QUEUE6_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DOORBELL 0x0377 +#define regSDMA0_SDMA_QUEUE6_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DOORBELL_LOG 0x0378 +#define regSDMA0_SDMA_QUEUE6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DOORBELL_OFFSET 0x0379 +#define regSDMA0_SDMA_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_CSA_ADDR_LO 0x037a +#define regSDMA0_SDMA_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_CSA_ADDR_HI 0x037b +#define regSDMA0_SDMA_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_SCHEDULE_CNTL 0x037c +#define regSDMA0_SDMA_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_IB_SUB_REMAIN 0x037d +#define regSDMA0_SDMA_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_PREEMPT 0x037e +#define regSDMA0_SDMA_QUEUE6_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG 0x037f +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x0380 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x0381 +#define regSDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_RB_AQL_CNTL 0x0382 +#define regSDMA0_SDMA_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MINOR_PTR_UPDATE 0x0383 +#define regSDMA0_SDMA_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS 0x0386 +#define regSDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_CNTL 0x0387 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA0 0x0388 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA1 0x0389 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA2 0x038a +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA3 0x038b +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA4 0x038c +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA5 0x038d +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA6 0x038e +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA7 0x038f +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA8 0x0390 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA9 0x0391 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA10 0x0392 +#define regSDMA0_SDMA_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_UTILIZATION_LO 0x0393 +#define regSDMA0_SDMA_QUEUE6_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_UTILIZATION_HI 0x0394 +#define regSDMA0_SDMA_QUEUE6_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_WAIT_UNSATISFIED_THD 0x0395 +#define regSDMA0_SDMA_QUEUE6_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_LO 0x0396 +#define regSDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_HI 0x0397 +#define regSDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_MQD_CONTROL 0x0398 +#define regSDMA0_SDMA_QUEUE6_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_CONTEXT_STATUS 0x0399 +#define regSDMA0_SDMA_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG1 0x039a +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG2 0x039b +#define regSDMA0_SDMA_QUEUE6_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_CNTL 0x03a4 +#define regSDMA0_SDMA_QUEUE7_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_BASE 0x03a5 +#define regSDMA0_SDMA_QUEUE7_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_BASE_HI 0x03a6 +#define regSDMA0_SDMA_QUEUE7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR 0x03a7 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_HI 0x03a8 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_WPTR 0x03a9 +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_HI 0x03aa +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_LO 0x03ab +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_HI 0x03ac +#define regSDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_CNTL 0x03ad +#define regSDMA0_SDMA_QUEUE7_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_RPTR 0x03ae +#define regSDMA0_SDMA_QUEUE7_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_OFFSET 0x03af +#define regSDMA0_SDMA_QUEUE7_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_BASE_LO 0x03b0 +#define regSDMA0_SDMA_QUEUE7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_BASE_HI 0x03b1 +#define regSDMA0_SDMA_QUEUE7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_SIZE 0x03b2 +#define regSDMA0_SDMA_QUEUE7_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DOORBELL 0x03b3 +#define regSDMA0_SDMA_QUEUE7_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DOORBELL_LOG 0x03b4 +#define regSDMA0_SDMA_QUEUE7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DOORBELL_OFFSET 0x03b5 +#define regSDMA0_SDMA_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_CSA_ADDR_LO 0x03b6 +#define regSDMA0_SDMA_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_CSA_ADDR_HI 0x03b7 +#define regSDMA0_SDMA_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_SCHEDULE_CNTL 0x03b8 +#define regSDMA0_SDMA_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_IB_SUB_REMAIN 0x03b9 +#define regSDMA0_SDMA_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_PREEMPT 0x03ba +#define regSDMA0_SDMA_QUEUE7_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG 0x03bb +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x03bc +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x03bd +#define regSDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_RB_AQL_CNTL 0x03be +#define regSDMA0_SDMA_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MINOR_PTR_UPDATE 0x03bf +#define regSDMA0_SDMA_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS 0x03c2 +#define regSDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_CNTL 0x03c3 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA0 0x03c4 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA1 0x03c5 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA2 0x03c6 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA3 0x03c7 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA4 0x03c8 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA5 0x03c9 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA6 0x03ca +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA7 0x03cb +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA8 0x03cc +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA9 0x03cd +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA10 0x03ce +#define regSDMA0_SDMA_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_UTILIZATION_LO 0x03cf +#define regSDMA0_SDMA_QUEUE7_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_UTILIZATION_HI 0x03d0 +#define regSDMA0_SDMA_QUEUE7_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_WAIT_UNSATISFIED_THD 0x03d1 +#define regSDMA0_SDMA_QUEUE7_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_LO 0x03d2 +#define regSDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_HI 0x03d3 +#define regSDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_MQD_CONTROL 0x03d4 +#define regSDMA0_SDMA_QUEUE7_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_CONTEXT_STATUS 0x03d5 +#define regSDMA0_SDMA_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG1 0x03d6 +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG2 0x03d7 +#define regSDMA0_SDMA_QUEUE7_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_CNTL 0x03e0 +#define regSDMA0_SDMA_QUEUE8_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_BASE 0x03e1 +#define regSDMA0_SDMA_QUEUE8_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_BASE_HI 0x03e2 +#define regSDMA0_SDMA_QUEUE8_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR 0x03e3 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_HI 0x03e4 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR 0x03e5 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_HI 0x03e6 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_LO 0x03e7 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_HI 0x03e8 +#define regSDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_CNTL 0x03e9 +#define regSDMA0_SDMA_QUEUE8_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_RPTR 0x03ea +#define regSDMA0_SDMA_QUEUE8_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_OFFSET 0x03eb +#define regSDMA0_SDMA_QUEUE8_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_BASE_LO 0x03ec +#define regSDMA0_SDMA_QUEUE8_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_BASE_HI 0x03ed +#define regSDMA0_SDMA_QUEUE8_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_SIZE 0x03ee +#define regSDMA0_SDMA_QUEUE8_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DOORBELL 0x03ef +#define regSDMA0_SDMA_QUEUE8_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DOORBELL_LOG 0x03f0 +#define regSDMA0_SDMA_QUEUE8_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DOORBELL_OFFSET 0x03f1 +#define regSDMA0_SDMA_QUEUE8_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_CSA_ADDR_LO 0x03f2 +#define regSDMA0_SDMA_QUEUE8_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_CSA_ADDR_HI 0x03f3 +#define regSDMA0_SDMA_QUEUE8_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_SCHEDULE_CNTL 0x03f4 +#define regSDMA0_SDMA_QUEUE8_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_IB_SUB_REMAIN 0x03f5 +#define regSDMA0_SDMA_QUEUE8_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_PREEMPT 0x03f6 +#define regSDMA0_SDMA_QUEUE8_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG 0x03f7 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO 0x03f8 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI 0x03f9 +#define regSDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_RB_AQL_CNTL 0x03fa +#define regSDMA0_SDMA_QUEUE8_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MINOR_PTR_UPDATE 0x03fb +#define regSDMA0_SDMA_QUEUE8_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS 0x03fe +#define regSDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_CNTL 0x03ff +#define regSDMA0_SDMA_QUEUE8_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA0 0x0400 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA1 0x0401 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA2 0x0402 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA3 0x0403 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA4 0x0404 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA5 0x0405 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA6 0x0406 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA7 0x0407 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA8 0x0408 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA9 0x0409 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA10 0x040a +#define regSDMA0_SDMA_QUEUE8_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_UTILIZATION_LO 0x040b +#define regSDMA0_SDMA_QUEUE8_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_UTILIZATION_HI 0x040c +#define regSDMA0_SDMA_QUEUE8_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_WAIT_UNSATISFIED_THD 0x040d +#define regSDMA0_SDMA_QUEUE8_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_LO 0x040e +#define regSDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_HI 0x040f +#define regSDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_MQD_CONTROL 0x0410 +#define regSDMA0_SDMA_QUEUE8_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_CONTEXT_STATUS 0x0411 +#define regSDMA0_SDMA_QUEUE8_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG1 0x0412 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG2 0x0413 +#define regSDMA0_SDMA_QUEUE8_DUMMY_REG2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_CNTL 0x041c +#define regSDMA0_SDMA_QUEUE9_RB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_BASE 0x041d +#define regSDMA0_SDMA_QUEUE9_RB_BASE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_BASE_HI 0x041e +#define regSDMA0_SDMA_QUEUE9_RB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR 0x041f +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_HI 0x0420 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR 0x0421 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_HI 0x0422 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_LO 0x0423 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_HI 0x0424 +#define regSDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_CNTL 0x0425 +#define regSDMA0_SDMA_QUEUE9_IB_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_RPTR 0x0426 +#define regSDMA0_SDMA_QUEUE9_IB_RPTR_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_OFFSET 0x0427 +#define regSDMA0_SDMA_QUEUE9_IB_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_BASE_LO 0x0428 +#define regSDMA0_SDMA_QUEUE9_IB_BASE_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_BASE_HI 0x0429 +#define regSDMA0_SDMA_QUEUE9_IB_BASE_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_SIZE 0x042a +#define regSDMA0_SDMA_QUEUE9_IB_SIZE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DOORBELL 0x042b +#define regSDMA0_SDMA_QUEUE9_DOORBELL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DOORBELL_LOG 0x042c +#define regSDMA0_SDMA_QUEUE9_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DOORBELL_OFFSET 0x042d +#define regSDMA0_SDMA_QUEUE9_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_CSA_ADDR_LO 0x042e +#define regSDMA0_SDMA_QUEUE9_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_CSA_ADDR_HI 0x042f +#define regSDMA0_SDMA_QUEUE9_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_SCHEDULE_CNTL 0x0430 +#define regSDMA0_SDMA_QUEUE9_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_IB_SUB_REMAIN 0x0431 +#define regSDMA0_SDMA_QUEUE9_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_PREEMPT 0x0432 +#define regSDMA0_SDMA_QUEUE9_PREEMPT_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG 0x0433 +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO 0x0434 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI 0x0435 +#define regSDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_RB_AQL_CNTL 0x0436 +#define regSDMA0_SDMA_QUEUE9_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MINOR_PTR_UPDATE 0x0437 +#define regSDMA0_SDMA_QUEUE9_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS 0x043a +#define regSDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_CNTL 0x043b +#define regSDMA0_SDMA_QUEUE9_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA0 0x043c +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA1 0x043d +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA2 0x043e +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA3 0x043f +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA4 0x0440 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA5 0x0441 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA6 0x0442 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA7 0x0443 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA8 0x0444 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA9 0x0445 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA10 0x0446 +#define regSDMA0_SDMA_QUEUE9_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_UTILIZATION_LO 0x0447 +#define regSDMA0_SDMA_QUEUE9_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_UTILIZATION_HI 0x0448 +#define regSDMA0_SDMA_QUEUE9_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_WAIT_UNSATISFIED_THD 0x0449 +#define regSDMA0_SDMA_QUEUE9_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_LO 0x044a +#define regSDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_HI 0x044b +#define regSDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_MQD_CONTROL 0x044c +#define regSDMA0_SDMA_QUEUE9_MQD_CONTROL_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_CONTEXT_STATUS 0x044d +#define regSDMA0_SDMA_QUEUE9_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG1 0x044e +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG1_BASE_IDX 0 +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG2 0x044f +#define regSDMA0_SDMA_QUEUE9_DUMMY_REG2_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmahypdec +// base address: 0x3e200 +#define regSDMA0_SDMA_VM_CTX_LO 0x5880 +#define regSDMA0_SDMA_VM_CTX_LO_BASE_IDX 1 +#define regSDMA0_SDMA_VM_CTX_HI 0x5881 +#define regSDMA0_SDMA_VM_CTX_HI_BASE_IDX 1 +#define regSDMA0_SDMA_ACTIVE_FCN_ID 0x5882 +#define regSDMA0_SDMA_ACTIVE_FCN_ID_BASE_IDX 1 +#define regSDMA0_SDMA_VM_CTX_CNTL 0x5883 +#define regSDMA0_SDMA_VM_CTX_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_VIRT_RESET_REQ 0x5884 +#define regSDMA0_SDMA_VIRT_RESET_REQ_BASE_IDX 1 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE0 0x5885 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE1 0x5886 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE2 0x5887 +#define regSDMA0_SDMA_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define regSDMA0_SDMA_PUB_REG_TYPE0 0x5888 +#define regSDMA0_SDMA_PUB_REG_TYPE0_BASE_IDX 1 +#define regSDMA0_SDMA_PUB_REG_TYPE1 0x5889 +#define regSDMA0_SDMA_PUB_REG_TYPE1_BASE_IDX 1 +#define regSDMA0_SDMA_PUB_REG_TYPE2 0x588a +#define regSDMA0_SDMA_PUB_REG_TYPE2_BASE_IDX 1 +#define regSDMA0_SDMA_PUB_REG_TYPE3 0x588b +#define regSDMA0_SDMA_PUB_REG_TYPE3_BASE_IDX 1 +#define regSDMA0_SDMA_VM_CNTL 0x588d +#define regSDMA0_SDMA_VM_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_MCU_CNTL 0x588e +#define regSDMA0_SDMA_MCU_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_IC_BASE_LO 0x589a +#define regSDMA0_SDMA_IC_BASE_LO_BASE_IDX 1 +#define regSDMA0_SDMA_IC_BASE_HI 0x589b +#define regSDMA0_SDMA_IC_BASE_HI_BASE_IDX 1 +#define regSDMA0_SDMA_IC_BASE_CNTL 0x589c +#define regSDMA0_SDMA_IC_BASE_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_IC_OP_CNTL 0x589d +#define regSDMA0_SDMA_IC_OP_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_IC_CNTL 0x589f +#define regSDMA0_SDMA_IC_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapspdec +// base address: 0x3f200 +#define regSDMA0_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET 0x5cc4 +#define regSDMA0_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfsdec +// base address: 0x37880 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG 0x3e20 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG 0x3e21 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG 0x3e22 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e23 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCNT_MISC_CNTL 0x3e24 +#define regSDMA0_SDMA_PERFCNT_MISC_CNTL_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER0_SELECT 0x3e25 +#define regSDMA0_SDMA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER0_SELECT1 0x3e26 +#define regSDMA0_SDMA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER1_SELECT 0x3e27 +#define regSDMA0_SDMA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER1_SELECT1 0x3e28 +#define regSDMA0_SDMA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER2_SELECT 0x3e29 +#define regSDMA0_SDMA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER2_SELECT1 0x3e2a +#define regSDMA0_SDMA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER3_SELECT 0x3e2b +#define regSDMA0_SDMA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER3_SELECT1 0x3e2c +#define regSDMA0_SDMA_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER4_SELECT 0x3e2d +#define regSDMA0_SDMA_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER4_SELECT1 0x3e2e +#define regSDMA0_SDMA_PERFCOUNTER4_SELECT1_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER5_SELECT 0x3e2f +#define regSDMA0_SDMA_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER5_SELECT1 0x3e30 +#define regSDMA0_SDMA_PERFCOUNTER5_SELECT1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfddec +// base address: 0x35980 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_LO 0x3660 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_HI 0x3661 +#define regSDMA0_SDMA_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER0_LO 0x3662 +#define regSDMA0_SDMA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER0_HI 0x3663 +#define regSDMA0_SDMA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER1_LO 0x3664 +#define regSDMA0_SDMA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER1_HI 0x3665 +#define regSDMA0_SDMA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER2_LO 0x3666 +#define regSDMA0_SDMA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER2_HI 0x3667 +#define regSDMA0_SDMA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER3_LO 0x3668 +#define regSDMA0_SDMA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER3_HI 0x3669 +#define regSDMA0_SDMA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER4_LO 0x366a +#define regSDMA0_SDMA_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER4_HI 0x366b +#define regSDMA0_SDMA_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER5_LO 0x366c +#define regSDMA0_SDMA_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSDMA0_SDMA_PERFCOUNTER5_HI 0x366d +#define regSDMA0_SDMA_PERFCOUNTER5_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapwrdec +// base address: 0x3c430 +#define regSDMA0_GFX_ICG_SDMA_CTRL 0x510c +#define regSDMA0_GFX_ICG_SDMA_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmadec:1 +// base address: 0x6180 +#define regSDMA1_SDMA_DEC_START 0x0600 +#define regSDMA1_SDMA_DEC_START_BASE_IDX 0 +#define regSDMA1_SDMA_MCU_MISC_CNTL 0x0601 +#define regSDMA1_SDMA_MCU_MISC_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_UCODE_REV 0x0603 +#define regSDMA1_SDMA_UCODE_REV_BASE_IDX 0 +#define regSDMA1_SDMA_GLOBAL_TIMESTAMP_LO 0x0605 +#define regSDMA1_SDMA_GLOBAL_TIMESTAMP_LO_BASE_IDX 0 +#define regSDMA1_SDMA_GLOBAL_TIMESTAMP_HI 0x0606 +#define regSDMA1_SDMA_GLOBAL_TIMESTAMP_HI_BASE_IDX 0 +#define regSDMA1_SDMA_POWER_CNTL 0x060c +#define regSDMA1_SDMA_POWER_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_CNTL 0x060d +#define regSDMA1_SDMA_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_CHICKEN_BITS 0x060e +#define regSDMA1_SDMA_CHICKEN_BITS_BASE_IDX 0 +#define regSDMA1_SDMA_CACHE_CNTL 0x060f +#define regSDMA1_SDMA_CACHE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_RB_RPTR_FETCH 0x0620 +#define regSDMA1_SDMA_RB_RPTR_FETCH_BASE_IDX 0 +#define regSDMA1_SDMA_RB_RPTR_FETCH_HI 0x0621 +#define regSDMA1_SDMA_RB_RPTR_FETCH_HI_BASE_IDX 0 +#define regSDMA1_SDMA_IB_OFFSET_FETCH 0x0622 +#define regSDMA1_SDMA_IB_OFFSET_FETCH_BASE_IDX 0 +#define regSDMA1_SDMA_PROGRAM 0x0623 +#define regSDMA1_SDMA_PROGRAM_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS_REG 0x0624 +#define regSDMA1_SDMA_STATUS_REG_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS1_REG 0x0625 +#define regSDMA1_SDMA_STATUS1_REG_BASE_IDX 0 +#define regSDMA1_SDMA_CNTL1 0x0626 +#define regSDMA1_SDMA_CNTL1_BASE_IDX 0 +#define regSDMA1_SDMA_HBM_PAGE_CONFIG 0x0627 +#define regSDMA1_SDMA_HBM_PAGE_CONFIG_BASE_IDX 0 +#define regSDMA1_SDMA_FREEZE 0x0628 +#define regSDMA1_SDMA_FREEZE_BASE_IDX 0 +#define regSDMA1_SDMA_PROCESS_QUANTUM0 0x0629 +#define regSDMA1_SDMA_PROCESS_QUANTUM0_BASE_IDX 0 +#define regSDMA1_SDMA_PROCESS_QUANTUM1 0x062a +#define regSDMA1_SDMA_PROCESS_QUANTUM1_BASE_IDX 0 +#define regSDMA1_SDMA_WATCHDOG_CNTL 0x062b +#define regSDMA1_SDMA_WATCHDOG_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE_STATUS0 0x062c +#define regSDMA1_SDMA_QUEUE_STATUS0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE_STATUS1 0x062d +#define regSDMA1_SDMA_QUEUE_STATUS1_BASE_IDX 0 +#define regSDMA1_SDMA_ID 0x062e +#define regSDMA1_SDMA_ID_BASE_IDX 0 +#define regSDMA1_SDMA_VERSION 0x062f +#define regSDMA1_SDMA_VERSION_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS2_REG 0x0630 +#define regSDMA1_SDMA_STATUS2_REG_BASE_IDX 0 +#define regSDMA1_SDMA_ATOMIC_CNTL 0x0631 +#define regSDMA1_SDMA_ATOMIC_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_ATOMIC_PERMS_CNTL 0x0632 +#define regSDMA1_SDMA_ATOMIC_PERMS_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_ATOMIC_PREOP_LO 0x0633 +#define regSDMA1_SDMA_ATOMIC_PREOP_LO_BASE_IDX 0 +#define regSDMA1_SDMA_ATOMIC_PREOP_HI 0x0634 +#define regSDMA1_SDMA_ATOMIC_PREOP_HI_BASE_IDX 0 +#define regSDMA1_SDMA_DCC_CNTL 0x0635 +#define regSDMA1_SDMA_DCC_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_WARMUPL2_CNTL 0x0636 +#define regSDMA1_SDMA_UTCL1_WARMUPL2_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_CNTL 0x0637 +#define regSDMA1_SDMA_UTCL1_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_WATERMK 0x0638 +#define regSDMA1_SDMA_UTCL1_WATERMK_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_TIMEOUT 0x0639 +#define regSDMA1_SDMA_UTCL1_TIMEOUT_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_PAGE 0x063a +#define regSDMA1_SDMA_UTCL1_PAGE_BASE_IDX 0 +#define regSDMA1_SDMA_EXTERNAL_FROZEN 0x063b +#define regSDMA1_SDMA_EXTERNAL_FROZEN_BASE_IDX 0 +#define regSDMA1_SDMA_FREEZE_TRIGGER 0x063c +#define regSDMA1_SDMA_FREEZE_TRIGGER_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_CACHE_CNTL 0x0640 +#define regSDMA1_SDMA_UTCL1_CACHE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_RD_STATUS 0x0641 +#define regSDMA1_SDMA_UTCL1_RD_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_WR_STATUS 0x0642 +#define regSDMA1_SDMA_UTCL1_WR_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_INV0 0x0643 +#define regSDMA1_SDMA_UTCL1_INV0_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_INV1 0x0644 +#define regSDMA1_SDMA_UTCL1_INV1_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_INV2 0x0645 +#define regSDMA1_SDMA_UTCL1_INV2_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_RD_XNACK0 0x0646 +#define regSDMA1_SDMA_UTCL1_RD_XNACK0_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_RD_XNACK1 0x0647 +#define regSDMA1_SDMA_UTCL1_RD_XNACK1_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_WR_XNACK0 0x0648 +#define regSDMA1_SDMA_UTCL1_WR_XNACK0_BASE_IDX 0 +#define regSDMA1_SDMA_UTCL1_WR_XNACK1 0x0649 +#define regSDMA1_SDMA_UTCL1_WR_XNACK1_BASE_IDX 0 +#define regSDMA1_SDMA_CHICKEN_BITS_2 0x064a +#define regSDMA1_SDMA_CHICKEN_BITS_2_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS3_REG 0x064b +#define regSDMA1_SDMA_STATUS3_REG_BASE_IDX 0 +#define regSDMA1_SDMA_GLOBAL_QUANTUM 0x064c +#define regSDMA1_SDMA_GLOBAL_QUANTUM_BASE_IDX 0 +#define regSDMA1_SDMA_ERROR_LOG 0x064d +#define regSDMA1_SDMA_ERROR_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_PUB_DUMMY_REG0 0x064e +#define regSDMA1_SDMA_PUB_DUMMY_REG0_BASE_IDX 0 +#define regSDMA1_SDMA_PUB_DUMMY_REG1 0x064f +#define regSDMA1_SDMA_PUB_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_PUB_DUMMY_REG2 0x0650 +#define regSDMA1_SDMA_PUB_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_PUB_DUMMY_REG3 0x0651 +#define regSDMA1_SDMA_PUB_DUMMY_REG3_BASE_IDX 0 +#define regSDMA1_SDMA_MCU_COUNTER 0x0652 +#define regSDMA1_SDMA_MCU_COUNTER_BASE_IDX 0 +#define regSDMA1_SDMA_CRD_CNTL 0x0653 +#define regSDMA1_SDMA_CRD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_RLC_CGCG_CTRL 0x0654 +#define regSDMA1_SDMA_RLC_CGCG_CTRL_BASE_IDX 0 +#define regSDMA1_SDMA_GPU_IOV_VIOLATION_LOG 0x0655 +#define regSDMA1_SDMA_GPU_IOV_VIOLATION_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_AQL_STATUS 0x0657 +#define regSDMA1_SDMA_AQL_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_TLBI_GCR_CNTL 0x0660 +#define regSDMA1_SDMA_TLBI_GCR_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_INT_STATUS 0x0661 +#define regSDMA1_SDMA_INT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_GPU_IOV_VIOLATION_LOG2 0x0662 +#define regSDMA1_SDMA_GPU_IOV_VIOLATION_LOG2_BASE_IDX 0 +#define regSDMA1_SDMA_INVALID_ADDR_LO 0x0663 +#define regSDMA1_SDMA_INVALID_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_INVALID_ADDR_HI 0x0664 +#define regSDMA1_SDMA_INVALID_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_INVALID_ADDR_SOURCE 0x0665 +#define regSDMA1_SDMA_INVALID_ADDR_SOURCE_BASE_IDX 0 +#define regSDMA1_SDMA_CLOCK_GATING_STATUS 0x0666 +#define regSDMA1_SDMA_CLOCK_GATING_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS4_REG 0x0667 +#define regSDMA1_SDMA_STATUS4_REG_BASE_IDX 0 +#define regSDMA1_SDMA_SCRATCH_RAM_DATA 0x0668 +#define regSDMA1_SDMA_SCRATCH_RAM_DATA_BASE_IDX 0 +#define regSDMA1_SDMA_SCRATCH_RAM_ADDR 0x0669 +#define regSDMA1_SDMA_SCRATCH_RAM_ADDR_BASE_IDX 0 +#define regSDMA1_SDMA_TIMESTAMP_CNTL 0x066a +#define regSDMA1_SDMA_TIMESTAMP_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS5_REG 0x066b +#define regSDMA1_SDMA_STATUS5_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE_RESET_REQ 0x066c +#define regSDMA1_SDMA_QUEUE_RESET_REQ_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE_DEQUEUE_REQUEST 0x066d +#define regSDMA1_SDMA_QUEUE_DEQUEUE_REQUEST_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS6_REG 0x066e +#define regSDMA1_SDMA_STATUS6_REG_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS7_REG 0x066f +#define regSDMA1_SDMA_STATUS7_REG_BASE_IDX 0 +#define regSDMA1_SDMA_STATUS8_REG 0x0670 +#define regSDMA1_SDMA_STATUS8_REG_BASE_IDX 0 +#define regSDMA1_SDMA_CE_CTRL 0x0671 +#define regSDMA1_SDMA_CE_CTRL_BASE_IDX 0 +#define regSDMA1_SDMA_RAS_STATUS 0x0672 +#define regSDMA1_SDMA_RAS_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_POISON_INFO 0x0673 +#define regSDMA1_SDMA_POISON_INFO_BASE_IDX 0 +#define regSDMA1_SDMA_MEMHUB_CNTL 0x0674 +#define regSDMA1_SDMA_MEMHUB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_CNTL 0x0800 +#define regSDMA1_SDMA_QUEUE0_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_BASE 0x0801 +#define regSDMA1_SDMA_QUEUE0_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_BASE_HI 0x0802 +#define regSDMA1_SDMA_QUEUE0_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR 0x0803 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_HI 0x0804 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR 0x0805 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_HI 0x0806 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_LO 0x0807 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_HI 0x0808 +#define regSDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_CNTL 0x0809 +#define regSDMA1_SDMA_QUEUE0_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_RPTR 0x080a +#define regSDMA1_SDMA_QUEUE0_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_OFFSET 0x080b +#define regSDMA1_SDMA_QUEUE0_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_BASE_LO 0x080c +#define regSDMA1_SDMA_QUEUE0_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_BASE_HI 0x080d +#define regSDMA1_SDMA_QUEUE0_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_SIZE 0x080e +#define regSDMA1_SDMA_QUEUE0_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DOORBELL 0x080f +#define regSDMA1_SDMA_QUEUE0_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DOORBELL_LOG 0x0810 +#define regSDMA1_SDMA_QUEUE0_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DOORBELL_OFFSET 0x0811 +#define regSDMA1_SDMA_QUEUE0_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_CSA_ADDR_LO 0x0812 +#define regSDMA1_SDMA_QUEUE0_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_CSA_ADDR_HI 0x0813 +#define regSDMA1_SDMA_QUEUE0_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_SCHEDULE_CNTL 0x0814 +#define regSDMA1_SDMA_QUEUE0_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_IB_SUB_REMAIN 0x0815 +#define regSDMA1_SDMA_QUEUE0_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_PREEMPT 0x0816 +#define regSDMA1_SDMA_QUEUE0_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG 0x0817 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO 0x0818 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI 0x0819 +#define regSDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_RB_AQL_CNTL 0x081a +#define regSDMA1_SDMA_QUEUE0_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MINOR_PTR_UPDATE 0x081b +#define regSDMA1_SDMA_QUEUE0_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS 0x081e +#define regSDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_CNTL 0x081f +#define regSDMA1_SDMA_QUEUE0_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA0 0x0820 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA1 0x0821 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA2 0x0822 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA3 0x0823 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA4 0x0824 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA5 0x0825 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA6 0x0826 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA7 0x0827 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA8 0x0828 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA9 0x0829 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA10 0x082a +#define regSDMA1_SDMA_QUEUE0_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_UTILIZATION_LO 0x082b +#define regSDMA1_SDMA_QUEUE0_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_UTILIZATION_HI 0x082c +#define regSDMA1_SDMA_QUEUE0_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_WAIT_UNSATISFIED_THD 0x082d +#define regSDMA1_SDMA_QUEUE0_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_LO 0x082e +#define regSDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_HI 0x082f +#define regSDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_MQD_CONTROL 0x0830 +#define regSDMA1_SDMA_QUEUE0_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_CONTEXT_STATUS 0x0831 +#define regSDMA1_SDMA_QUEUE0_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG1 0x0832 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG2 0x0833 +#define regSDMA1_SDMA_QUEUE0_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_CNTL 0x083c +#define regSDMA1_SDMA_QUEUE1_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_BASE 0x083d +#define regSDMA1_SDMA_QUEUE1_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_BASE_HI 0x083e +#define regSDMA1_SDMA_QUEUE1_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR 0x083f +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_HI 0x0840 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR 0x0841 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_HI 0x0842 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_LO 0x0843 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_HI 0x0844 +#define regSDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_CNTL 0x0845 +#define regSDMA1_SDMA_QUEUE1_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_RPTR 0x0846 +#define regSDMA1_SDMA_QUEUE1_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_OFFSET 0x0847 +#define regSDMA1_SDMA_QUEUE1_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_BASE_LO 0x0848 +#define regSDMA1_SDMA_QUEUE1_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_BASE_HI 0x0849 +#define regSDMA1_SDMA_QUEUE1_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_SIZE 0x084a +#define regSDMA1_SDMA_QUEUE1_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DOORBELL 0x084b +#define regSDMA1_SDMA_QUEUE1_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DOORBELL_LOG 0x084c +#define regSDMA1_SDMA_QUEUE1_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DOORBELL_OFFSET 0x084d +#define regSDMA1_SDMA_QUEUE1_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_CSA_ADDR_LO 0x084e +#define regSDMA1_SDMA_QUEUE1_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_CSA_ADDR_HI 0x084f +#define regSDMA1_SDMA_QUEUE1_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_SCHEDULE_CNTL 0x0850 +#define regSDMA1_SDMA_QUEUE1_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_IB_SUB_REMAIN 0x0851 +#define regSDMA1_SDMA_QUEUE1_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_PREEMPT 0x0852 +#define regSDMA1_SDMA_QUEUE1_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG 0x0853 +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO 0x0854 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI 0x0855 +#define regSDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_RB_AQL_CNTL 0x0856 +#define regSDMA1_SDMA_QUEUE1_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MINOR_PTR_UPDATE 0x0857 +#define regSDMA1_SDMA_QUEUE1_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS 0x085a +#define regSDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_CNTL 0x085b +#define regSDMA1_SDMA_QUEUE1_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA0 0x085c +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA1 0x085d +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA2 0x085e +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA3 0x085f +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA4 0x0860 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA5 0x0861 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA6 0x0862 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA7 0x0863 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA8 0x0864 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA9 0x0865 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA10 0x0866 +#define regSDMA1_SDMA_QUEUE1_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_UTILIZATION_LO 0x0867 +#define regSDMA1_SDMA_QUEUE1_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_UTILIZATION_HI 0x0868 +#define regSDMA1_SDMA_QUEUE1_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_WAIT_UNSATISFIED_THD 0x0869 +#define regSDMA1_SDMA_QUEUE1_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_LO 0x086a +#define regSDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_HI 0x086b +#define regSDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_MQD_CONTROL 0x086c +#define regSDMA1_SDMA_QUEUE1_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_CONTEXT_STATUS 0x086d +#define regSDMA1_SDMA_QUEUE1_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG1 0x086e +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG2 0x086f +#define regSDMA1_SDMA_QUEUE1_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_CNTL 0x0878 +#define regSDMA1_SDMA_QUEUE2_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_BASE 0x0879 +#define regSDMA1_SDMA_QUEUE2_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_BASE_HI 0x087a +#define regSDMA1_SDMA_QUEUE2_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_RPTR 0x087b +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_HI 0x087c +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR 0x087d +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_HI 0x087e +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_LO 0x087f +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_HI 0x0880 +#define regSDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_CNTL 0x0881 +#define regSDMA1_SDMA_QUEUE2_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_RPTR 0x0882 +#define regSDMA1_SDMA_QUEUE2_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_OFFSET 0x0883 +#define regSDMA1_SDMA_QUEUE2_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_BASE_LO 0x0884 +#define regSDMA1_SDMA_QUEUE2_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_BASE_HI 0x0885 +#define regSDMA1_SDMA_QUEUE2_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_SIZE 0x0886 +#define regSDMA1_SDMA_QUEUE2_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DOORBELL 0x0887 +#define regSDMA1_SDMA_QUEUE2_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DOORBELL_LOG 0x0888 +#define regSDMA1_SDMA_QUEUE2_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DOORBELL_OFFSET 0x0889 +#define regSDMA1_SDMA_QUEUE2_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_CSA_ADDR_LO 0x088a +#define regSDMA1_SDMA_QUEUE2_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_CSA_ADDR_HI 0x088b +#define regSDMA1_SDMA_QUEUE2_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_SCHEDULE_CNTL 0x088c +#define regSDMA1_SDMA_QUEUE2_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_IB_SUB_REMAIN 0x088d +#define regSDMA1_SDMA_QUEUE2_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_PREEMPT 0x088e +#define regSDMA1_SDMA_QUEUE2_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG 0x088f +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO 0x0890 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI 0x0891 +#define regSDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_RB_AQL_CNTL 0x0892 +#define regSDMA1_SDMA_QUEUE2_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MINOR_PTR_UPDATE 0x0893 +#define regSDMA1_SDMA_QUEUE2_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS 0x0896 +#define regSDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_CNTL 0x0897 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA0 0x0898 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA1 0x0899 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA2 0x089a +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA3 0x089b +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA4 0x089c +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA5 0x089d +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA6 0x089e +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA7 0x089f +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA8 0x08a0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA9 0x08a1 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA10 0x08a2 +#define regSDMA1_SDMA_QUEUE2_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_UTILIZATION_LO 0x08a3 +#define regSDMA1_SDMA_QUEUE2_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_UTILIZATION_HI 0x08a4 +#define regSDMA1_SDMA_QUEUE2_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_WAIT_UNSATISFIED_THD 0x08a5 +#define regSDMA1_SDMA_QUEUE2_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_LO 0x08a6 +#define regSDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_HI 0x08a7 +#define regSDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_MQD_CONTROL 0x08a8 +#define regSDMA1_SDMA_QUEUE2_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_CONTEXT_STATUS 0x08a9 +#define regSDMA1_SDMA_QUEUE2_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG1 0x08aa +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG2 0x08ab +#define regSDMA1_SDMA_QUEUE2_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_CNTL 0x08b4 +#define regSDMA1_SDMA_QUEUE3_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_BASE 0x08b5 +#define regSDMA1_SDMA_QUEUE3_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_BASE_HI 0x08b6 +#define regSDMA1_SDMA_QUEUE3_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR 0x08b7 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_HI 0x08b8 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_WPTR 0x08b9 +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_HI 0x08ba +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_LO 0x08bb +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_HI 0x08bc +#define regSDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_CNTL 0x08bd +#define regSDMA1_SDMA_QUEUE3_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_RPTR 0x08be +#define regSDMA1_SDMA_QUEUE3_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_OFFSET 0x08bf +#define regSDMA1_SDMA_QUEUE3_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_BASE_LO 0x08c0 +#define regSDMA1_SDMA_QUEUE3_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_BASE_HI 0x08c1 +#define regSDMA1_SDMA_QUEUE3_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_SIZE 0x08c2 +#define regSDMA1_SDMA_QUEUE3_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DOORBELL 0x08c3 +#define regSDMA1_SDMA_QUEUE3_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DOORBELL_LOG 0x08c4 +#define regSDMA1_SDMA_QUEUE3_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DOORBELL_OFFSET 0x08c5 +#define regSDMA1_SDMA_QUEUE3_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_CSA_ADDR_LO 0x08c6 +#define regSDMA1_SDMA_QUEUE3_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_CSA_ADDR_HI 0x08c7 +#define regSDMA1_SDMA_QUEUE3_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_SCHEDULE_CNTL 0x08c8 +#define regSDMA1_SDMA_QUEUE3_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_IB_SUB_REMAIN 0x08c9 +#define regSDMA1_SDMA_QUEUE3_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_PREEMPT 0x08ca +#define regSDMA1_SDMA_QUEUE3_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG 0x08cb +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO 0x08cc +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI 0x08cd +#define regSDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_RB_AQL_CNTL 0x08ce +#define regSDMA1_SDMA_QUEUE3_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MINOR_PTR_UPDATE 0x08cf +#define regSDMA1_SDMA_QUEUE3_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS 0x08d2 +#define regSDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_CNTL 0x08d3 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA0 0x08d4 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA1 0x08d5 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA2 0x08d6 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA3 0x08d7 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA4 0x08d8 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA5 0x08d9 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA6 0x08da +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA7 0x08db +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA8 0x08dc +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA9 0x08dd +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA10 0x08de +#define regSDMA1_SDMA_QUEUE3_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_UTILIZATION_LO 0x08df +#define regSDMA1_SDMA_QUEUE3_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_UTILIZATION_HI 0x08e0 +#define regSDMA1_SDMA_QUEUE3_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_WAIT_UNSATISFIED_THD 0x08e1 +#define regSDMA1_SDMA_QUEUE3_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_LO 0x08e2 +#define regSDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_HI 0x08e3 +#define regSDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_MQD_CONTROL 0x08e4 +#define regSDMA1_SDMA_QUEUE3_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_CONTEXT_STATUS 0x08e5 +#define regSDMA1_SDMA_QUEUE3_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG1 0x08e6 +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG2 0x08e7 +#define regSDMA1_SDMA_QUEUE3_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_CNTL 0x08f0 +#define regSDMA1_SDMA_QUEUE4_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_BASE 0x08f1 +#define regSDMA1_SDMA_QUEUE4_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_BASE_HI 0x08f2 +#define regSDMA1_SDMA_QUEUE4_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR 0x08f3 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_HI 0x08f4 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR 0x08f5 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_HI 0x08f6 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_LO 0x08f7 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_HI 0x08f8 +#define regSDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_CNTL 0x08f9 +#define regSDMA1_SDMA_QUEUE4_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_RPTR 0x08fa +#define regSDMA1_SDMA_QUEUE4_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_OFFSET 0x08fb +#define regSDMA1_SDMA_QUEUE4_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_BASE_LO 0x08fc +#define regSDMA1_SDMA_QUEUE4_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_BASE_HI 0x08fd +#define regSDMA1_SDMA_QUEUE4_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_SIZE 0x08fe +#define regSDMA1_SDMA_QUEUE4_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DOORBELL 0x08ff +#define regSDMA1_SDMA_QUEUE4_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DOORBELL_LOG 0x0900 +#define regSDMA1_SDMA_QUEUE4_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DOORBELL_OFFSET 0x0901 +#define regSDMA1_SDMA_QUEUE4_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_CSA_ADDR_LO 0x0902 +#define regSDMA1_SDMA_QUEUE4_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_CSA_ADDR_HI 0x0903 +#define regSDMA1_SDMA_QUEUE4_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_SCHEDULE_CNTL 0x0904 +#define regSDMA1_SDMA_QUEUE4_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_IB_SUB_REMAIN 0x0905 +#define regSDMA1_SDMA_QUEUE4_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_PREEMPT 0x0906 +#define regSDMA1_SDMA_QUEUE4_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG 0x0907 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO 0x0908 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI 0x0909 +#define regSDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_RB_AQL_CNTL 0x090a +#define regSDMA1_SDMA_QUEUE4_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MINOR_PTR_UPDATE 0x090b +#define regSDMA1_SDMA_QUEUE4_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS 0x090e +#define regSDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_CNTL 0x090f +#define regSDMA1_SDMA_QUEUE4_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA0 0x0910 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA1 0x0911 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA2 0x0912 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA3 0x0913 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA4 0x0914 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA5 0x0915 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA6 0x0916 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA7 0x0917 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA8 0x0918 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA9 0x0919 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA10 0x091a +#define regSDMA1_SDMA_QUEUE4_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_UTILIZATION_LO 0x091b +#define regSDMA1_SDMA_QUEUE4_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_UTILIZATION_HI 0x091c +#define regSDMA1_SDMA_QUEUE4_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_WAIT_UNSATISFIED_THD 0x091d +#define regSDMA1_SDMA_QUEUE4_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_LO 0x091e +#define regSDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_HI 0x091f +#define regSDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_MQD_CONTROL 0x0920 +#define regSDMA1_SDMA_QUEUE4_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_CONTEXT_STATUS 0x0921 +#define regSDMA1_SDMA_QUEUE4_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG1 0x0922 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG2 0x0923 +#define regSDMA1_SDMA_QUEUE4_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_CNTL 0x092c +#define regSDMA1_SDMA_QUEUE5_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_BASE 0x092d +#define regSDMA1_SDMA_QUEUE5_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_BASE_HI 0x092e +#define regSDMA1_SDMA_QUEUE5_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR 0x092f +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_HI 0x0930 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR 0x0931 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_HI 0x0932 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_LO 0x0933 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_HI 0x0934 +#define regSDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_CNTL 0x0935 +#define regSDMA1_SDMA_QUEUE5_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_RPTR 0x0936 +#define regSDMA1_SDMA_QUEUE5_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_OFFSET 0x0937 +#define regSDMA1_SDMA_QUEUE5_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_BASE_LO 0x0938 +#define regSDMA1_SDMA_QUEUE5_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_BASE_HI 0x0939 +#define regSDMA1_SDMA_QUEUE5_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_SIZE 0x093a +#define regSDMA1_SDMA_QUEUE5_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DOORBELL 0x093b +#define regSDMA1_SDMA_QUEUE5_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DOORBELL_LOG 0x093c +#define regSDMA1_SDMA_QUEUE5_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DOORBELL_OFFSET 0x093d +#define regSDMA1_SDMA_QUEUE5_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_CSA_ADDR_LO 0x093e +#define regSDMA1_SDMA_QUEUE5_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_CSA_ADDR_HI 0x093f +#define regSDMA1_SDMA_QUEUE5_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_SCHEDULE_CNTL 0x0940 +#define regSDMA1_SDMA_QUEUE5_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_IB_SUB_REMAIN 0x0941 +#define regSDMA1_SDMA_QUEUE5_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_PREEMPT 0x0942 +#define regSDMA1_SDMA_QUEUE5_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG 0x0943 +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO 0x0944 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI 0x0945 +#define regSDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_RB_AQL_CNTL 0x0946 +#define regSDMA1_SDMA_QUEUE5_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MINOR_PTR_UPDATE 0x0947 +#define regSDMA1_SDMA_QUEUE5_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS 0x094a +#define regSDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_CNTL 0x094b +#define regSDMA1_SDMA_QUEUE5_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA0 0x094c +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA1 0x094d +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA2 0x094e +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA3 0x094f +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA4 0x0950 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA5 0x0951 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA6 0x0952 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA7 0x0953 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA8 0x0954 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA9 0x0955 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA10 0x0956 +#define regSDMA1_SDMA_QUEUE5_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_UTILIZATION_LO 0x0957 +#define regSDMA1_SDMA_QUEUE5_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_UTILIZATION_HI 0x0958 +#define regSDMA1_SDMA_QUEUE5_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_WAIT_UNSATISFIED_THD 0x0959 +#define regSDMA1_SDMA_QUEUE5_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_LO 0x095a +#define regSDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_HI 0x095b +#define regSDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_MQD_CONTROL 0x095c +#define regSDMA1_SDMA_QUEUE5_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_CONTEXT_STATUS 0x095d +#define regSDMA1_SDMA_QUEUE5_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG1 0x095e +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG2 0x095f +#define regSDMA1_SDMA_QUEUE5_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_CNTL 0x0968 +#define regSDMA1_SDMA_QUEUE6_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_BASE 0x0969 +#define regSDMA1_SDMA_QUEUE6_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_BASE_HI 0x096a +#define regSDMA1_SDMA_QUEUE6_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_RPTR 0x096b +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_HI 0x096c +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR 0x096d +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_HI 0x096e +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_LO 0x096f +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_HI 0x0970 +#define regSDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_CNTL 0x0971 +#define regSDMA1_SDMA_QUEUE6_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_RPTR 0x0972 +#define regSDMA1_SDMA_QUEUE6_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_OFFSET 0x0973 +#define regSDMA1_SDMA_QUEUE6_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_BASE_LO 0x0974 +#define regSDMA1_SDMA_QUEUE6_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_BASE_HI 0x0975 +#define regSDMA1_SDMA_QUEUE6_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_SIZE 0x0976 +#define regSDMA1_SDMA_QUEUE6_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DOORBELL 0x0977 +#define regSDMA1_SDMA_QUEUE6_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DOORBELL_LOG 0x0978 +#define regSDMA1_SDMA_QUEUE6_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DOORBELL_OFFSET 0x0979 +#define regSDMA1_SDMA_QUEUE6_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_CSA_ADDR_LO 0x097a +#define regSDMA1_SDMA_QUEUE6_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_CSA_ADDR_HI 0x097b +#define regSDMA1_SDMA_QUEUE6_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_SCHEDULE_CNTL 0x097c +#define regSDMA1_SDMA_QUEUE6_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_IB_SUB_REMAIN 0x097d +#define regSDMA1_SDMA_QUEUE6_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_PREEMPT 0x097e +#define regSDMA1_SDMA_QUEUE6_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG 0x097f +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO 0x0980 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI 0x0981 +#define regSDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_RB_AQL_CNTL 0x0982 +#define regSDMA1_SDMA_QUEUE6_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MINOR_PTR_UPDATE 0x0983 +#define regSDMA1_SDMA_QUEUE6_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS 0x0986 +#define regSDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_CNTL 0x0987 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA0 0x0988 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA1 0x0989 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA2 0x098a +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA3 0x098b +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA4 0x098c +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA5 0x098d +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA6 0x098e +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA7 0x098f +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA8 0x0990 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA9 0x0991 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA10 0x0992 +#define regSDMA1_SDMA_QUEUE6_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_UTILIZATION_LO 0x0993 +#define regSDMA1_SDMA_QUEUE6_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_UTILIZATION_HI 0x0994 +#define regSDMA1_SDMA_QUEUE6_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_WAIT_UNSATISFIED_THD 0x0995 +#define regSDMA1_SDMA_QUEUE6_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_LO 0x0996 +#define regSDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_HI 0x0997 +#define regSDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_MQD_CONTROL 0x0998 +#define regSDMA1_SDMA_QUEUE6_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_CONTEXT_STATUS 0x0999 +#define regSDMA1_SDMA_QUEUE6_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG1 0x099a +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG2 0x099b +#define regSDMA1_SDMA_QUEUE6_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_CNTL 0x09a4 +#define regSDMA1_SDMA_QUEUE7_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_BASE 0x09a5 +#define regSDMA1_SDMA_QUEUE7_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_BASE_HI 0x09a6 +#define regSDMA1_SDMA_QUEUE7_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR 0x09a7 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_HI 0x09a8 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_WPTR 0x09a9 +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_HI 0x09aa +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_LO 0x09ab +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_HI 0x09ac +#define regSDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_CNTL 0x09ad +#define regSDMA1_SDMA_QUEUE7_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_RPTR 0x09ae +#define regSDMA1_SDMA_QUEUE7_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_OFFSET 0x09af +#define regSDMA1_SDMA_QUEUE7_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_BASE_LO 0x09b0 +#define regSDMA1_SDMA_QUEUE7_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_BASE_HI 0x09b1 +#define regSDMA1_SDMA_QUEUE7_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_SIZE 0x09b2 +#define regSDMA1_SDMA_QUEUE7_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DOORBELL 0x09b3 +#define regSDMA1_SDMA_QUEUE7_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DOORBELL_LOG 0x09b4 +#define regSDMA1_SDMA_QUEUE7_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DOORBELL_OFFSET 0x09b5 +#define regSDMA1_SDMA_QUEUE7_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_CSA_ADDR_LO 0x09b6 +#define regSDMA1_SDMA_QUEUE7_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_CSA_ADDR_HI 0x09b7 +#define regSDMA1_SDMA_QUEUE7_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_SCHEDULE_CNTL 0x09b8 +#define regSDMA1_SDMA_QUEUE7_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_IB_SUB_REMAIN 0x09b9 +#define regSDMA1_SDMA_QUEUE7_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_PREEMPT 0x09ba +#define regSDMA1_SDMA_QUEUE7_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG 0x09bb +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO 0x09bc +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI 0x09bd +#define regSDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_RB_AQL_CNTL 0x09be +#define regSDMA1_SDMA_QUEUE7_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MINOR_PTR_UPDATE 0x09bf +#define regSDMA1_SDMA_QUEUE7_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS 0x09c2 +#define regSDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_CNTL 0x09c3 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA0 0x09c4 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA1 0x09c5 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA2 0x09c6 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA3 0x09c7 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA4 0x09c8 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA5 0x09c9 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA6 0x09ca +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA7 0x09cb +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA8 0x09cc +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA9 0x09cd +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA10 0x09ce +#define regSDMA1_SDMA_QUEUE7_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_UTILIZATION_LO 0x09cf +#define regSDMA1_SDMA_QUEUE7_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_UTILIZATION_HI 0x09d0 +#define regSDMA1_SDMA_QUEUE7_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_WAIT_UNSATISFIED_THD 0x09d1 +#define regSDMA1_SDMA_QUEUE7_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_LO 0x09d2 +#define regSDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_HI 0x09d3 +#define regSDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_MQD_CONTROL 0x09d4 +#define regSDMA1_SDMA_QUEUE7_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_CONTEXT_STATUS 0x09d5 +#define regSDMA1_SDMA_QUEUE7_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG1 0x09d6 +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG2 0x09d7 +#define regSDMA1_SDMA_QUEUE7_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_CNTL 0x09e0 +#define regSDMA1_SDMA_QUEUE8_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_BASE 0x09e1 +#define regSDMA1_SDMA_QUEUE8_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_BASE_HI 0x09e2 +#define regSDMA1_SDMA_QUEUE8_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR 0x09e3 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_HI 0x09e4 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR 0x09e5 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_HI 0x09e6 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_LO 0x09e7 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_HI 0x09e8 +#define regSDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_CNTL 0x09e9 +#define regSDMA1_SDMA_QUEUE8_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_RPTR 0x09ea +#define regSDMA1_SDMA_QUEUE8_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_OFFSET 0x09eb +#define regSDMA1_SDMA_QUEUE8_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_BASE_LO 0x09ec +#define regSDMA1_SDMA_QUEUE8_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_BASE_HI 0x09ed +#define regSDMA1_SDMA_QUEUE8_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_SIZE 0x09ee +#define regSDMA1_SDMA_QUEUE8_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DOORBELL 0x09ef +#define regSDMA1_SDMA_QUEUE8_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DOORBELL_LOG 0x09f0 +#define regSDMA1_SDMA_QUEUE8_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DOORBELL_OFFSET 0x09f1 +#define regSDMA1_SDMA_QUEUE8_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_CSA_ADDR_LO 0x09f2 +#define regSDMA1_SDMA_QUEUE8_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_CSA_ADDR_HI 0x09f3 +#define regSDMA1_SDMA_QUEUE8_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_SCHEDULE_CNTL 0x09f4 +#define regSDMA1_SDMA_QUEUE8_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_IB_SUB_REMAIN 0x09f5 +#define regSDMA1_SDMA_QUEUE8_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_PREEMPT 0x09f6 +#define regSDMA1_SDMA_QUEUE8_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG 0x09f7 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO 0x09f8 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI 0x09f9 +#define regSDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_RB_AQL_CNTL 0x09fa +#define regSDMA1_SDMA_QUEUE8_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MINOR_PTR_UPDATE 0x09fb +#define regSDMA1_SDMA_QUEUE8_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS 0x09fe +#define regSDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_CNTL 0x09ff +#define regSDMA1_SDMA_QUEUE8_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA0 0x0a00 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA1 0x0a01 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA2 0x0a02 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA3 0x0a03 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA4 0x0a04 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA5 0x0a05 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA6 0x0a06 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA7 0x0a07 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA8 0x0a08 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA9 0x0a09 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA10 0x0a0a +#define regSDMA1_SDMA_QUEUE8_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_UTILIZATION_LO 0x0a0b +#define regSDMA1_SDMA_QUEUE8_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_UTILIZATION_HI 0x0a0c +#define regSDMA1_SDMA_QUEUE8_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_WAIT_UNSATISFIED_THD 0x0a0d +#define regSDMA1_SDMA_QUEUE8_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_LO 0x0a0e +#define regSDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_HI 0x0a0f +#define regSDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_MQD_CONTROL 0x0a10 +#define regSDMA1_SDMA_QUEUE8_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_CONTEXT_STATUS 0x0a11 +#define regSDMA1_SDMA_QUEUE8_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG1 0x0a12 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG2 0x0a13 +#define regSDMA1_SDMA_QUEUE8_DUMMY_REG2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_CNTL 0x0a1c +#define regSDMA1_SDMA_QUEUE9_RB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_BASE 0x0a1d +#define regSDMA1_SDMA_QUEUE9_RB_BASE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_BASE_HI 0x0a1e +#define regSDMA1_SDMA_QUEUE9_RB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR 0x0a1f +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_HI 0x0a20 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR 0x0a21 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_HI 0x0a22 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_LO 0x0a23 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_HI 0x0a24 +#define regSDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_CNTL 0x0a25 +#define regSDMA1_SDMA_QUEUE9_IB_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_RPTR 0x0a26 +#define regSDMA1_SDMA_QUEUE9_IB_RPTR_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_OFFSET 0x0a27 +#define regSDMA1_SDMA_QUEUE9_IB_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_BASE_LO 0x0a28 +#define regSDMA1_SDMA_QUEUE9_IB_BASE_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_BASE_HI 0x0a29 +#define regSDMA1_SDMA_QUEUE9_IB_BASE_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_SIZE 0x0a2a +#define regSDMA1_SDMA_QUEUE9_IB_SIZE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DOORBELL 0x0a2b +#define regSDMA1_SDMA_QUEUE9_DOORBELL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DOORBELL_LOG 0x0a2c +#define regSDMA1_SDMA_QUEUE9_DOORBELL_LOG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DOORBELL_OFFSET 0x0a2d +#define regSDMA1_SDMA_QUEUE9_DOORBELL_OFFSET_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_CSA_ADDR_LO 0x0a2e +#define regSDMA1_SDMA_QUEUE9_CSA_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_CSA_ADDR_HI 0x0a2f +#define regSDMA1_SDMA_QUEUE9_CSA_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_SCHEDULE_CNTL 0x0a30 +#define regSDMA1_SDMA_QUEUE9_SCHEDULE_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_IB_SUB_REMAIN 0x0a31 +#define regSDMA1_SDMA_QUEUE9_IB_SUB_REMAIN_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_PREEMPT 0x0a32 +#define regSDMA1_SDMA_QUEUE9_PREEMPT_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG 0x0a33 +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO 0x0a34 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI 0x0a35 +#define regSDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_RB_AQL_CNTL 0x0a36 +#define regSDMA1_SDMA_QUEUE9_RB_AQL_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MINOR_PTR_UPDATE 0x0a37 +#define regSDMA1_SDMA_QUEUE9_MINOR_PTR_UPDATE_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS 0x0a3a +#define regSDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_CNTL 0x0a3b +#define regSDMA1_SDMA_QUEUE9_MIDCMD_CNTL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA0 0x0a3c +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA0_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA1 0x0a3d +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA2 0x0a3e +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA2_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA3 0x0a3f +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA3_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA4 0x0a40 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA4_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA5 0x0a41 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA5_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA6 0x0a42 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA6_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA7 0x0a43 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA7_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA8 0x0a44 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA8_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA9 0x0a45 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA9_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA10 0x0a46 +#define regSDMA1_SDMA_QUEUE9_MIDCMD_DATA10_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_UTILIZATION_LO 0x0a47 +#define regSDMA1_SDMA_QUEUE9_UTILIZATION_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_UTILIZATION_HI 0x0a48 +#define regSDMA1_SDMA_QUEUE9_UTILIZATION_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_WAIT_UNSATISFIED_THD 0x0a49 +#define regSDMA1_SDMA_QUEUE9_WAIT_UNSATISFIED_THD_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_LO 0x0a4a +#define regSDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_LO_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_HI 0x0a4b +#define regSDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_MQD_CONTROL 0x0a4c +#define regSDMA1_SDMA_QUEUE9_MQD_CONTROL_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_CONTEXT_STATUS 0x0a4d +#define regSDMA1_SDMA_QUEUE9_CONTEXT_STATUS_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG1 0x0a4e +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG1_BASE_IDX 0 +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG2 0x0a4f +#define regSDMA1_SDMA_QUEUE9_DUMMY_REG2_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmahypdec:1 +// base address: 0x3e2c0 +#define regSDMA1_SDMA_VM_CTX_LO 0x58b0 +#define regSDMA1_SDMA_VM_CTX_LO_BASE_IDX 1 +#define regSDMA1_SDMA_VM_CTX_HI 0x58b1 +#define regSDMA1_SDMA_VM_CTX_HI_BASE_IDX 1 +#define regSDMA1_SDMA_ACTIVE_FCN_ID 0x58b2 +#define regSDMA1_SDMA_ACTIVE_FCN_ID_BASE_IDX 1 +#define regSDMA1_SDMA_VM_CTX_CNTL 0x58b3 +#define regSDMA1_SDMA_VM_CTX_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_VIRT_RESET_REQ 0x58b4 +#define regSDMA1_SDMA_VIRT_RESET_REQ_BASE_IDX 1 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE0 0x58b5 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE0_BASE_IDX 1 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE1 0x58b6 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE1_BASE_IDX 1 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE2 0x58b7 +#define regSDMA1_SDMA_CONTEXT_REG_TYPE2_BASE_IDX 1 +#define regSDMA1_SDMA_PUB_REG_TYPE0 0x58b8 +#define regSDMA1_SDMA_PUB_REG_TYPE0_BASE_IDX 1 +#define regSDMA1_SDMA_PUB_REG_TYPE1 0x58b9 +#define regSDMA1_SDMA_PUB_REG_TYPE1_BASE_IDX 1 +#define regSDMA1_SDMA_PUB_REG_TYPE2 0x58ba +#define regSDMA1_SDMA_PUB_REG_TYPE2_BASE_IDX 1 +#define regSDMA1_SDMA_PUB_REG_TYPE3 0x58bb +#define regSDMA1_SDMA_PUB_REG_TYPE3_BASE_IDX 1 +#define regSDMA1_SDMA_VM_CNTL 0x58bd +#define regSDMA1_SDMA_VM_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_MCU_CNTL 0x58be +#define regSDMA1_SDMA_MCU_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_IC_BASE_LO 0x58ca +#define regSDMA1_SDMA_IC_BASE_LO_BASE_IDX 1 +#define regSDMA1_SDMA_IC_BASE_HI 0x58cb +#define regSDMA1_SDMA_IC_BASE_HI_BASE_IDX 1 +#define regSDMA1_SDMA_IC_BASE_CNTL 0x58cc +#define regSDMA1_SDMA_IC_BASE_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_IC_OP_CNTL 0x58cd +#define regSDMA1_SDMA_IC_OP_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_IC_CNTL 0x58cf +#define regSDMA1_SDMA_IC_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapspdec:1 +// base address: 0x3f340 +#define regSDMA1_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET 0x5d14 +#define regSDMA1_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfsdec:1 +// base address: 0x378e0 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG 0x3e38 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG 0x3e39 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG 0x3e3a +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL 0x3e3b +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCNT_MISC_CNTL 0x3e3c +#define regSDMA1_SDMA_PERFCNT_MISC_CNTL_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER0_SELECT 0x3e3d +#define regSDMA1_SDMA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER0_SELECT1 0x3e3e +#define regSDMA1_SDMA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER1_SELECT 0x3e3f +#define regSDMA1_SDMA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER1_SELECT1 0x3e40 +#define regSDMA1_SDMA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER2_SELECT 0x3e41 +#define regSDMA1_SDMA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER2_SELECT1 0x3e42 +#define regSDMA1_SDMA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER3_SELECT 0x3e43 +#define regSDMA1_SDMA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER3_SELECT1 0x3e44 +#define regSDMA1_SDMA_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER4_SELECT 0x3e45 +#define regSDMA1_SDMA_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER4_SELECT1 0x3e46 +#define regSDMA1_SDMA_PERFCOUNTER4_SELECT1_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER5_SELECT 0x3e47 +#define regSDMA1_SDMA_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER5_SELECT1 0x3e48 +#define regSDMA1_SDMA_PERFCOUNTER5_SELECT1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfddec:1 +// base address: 0x359e0 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_LO 0x3678 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_HI 0x3679 +#define regSDMA1_SDMA_PERFCNT_PERFCOUNTER_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER0_LO 0x367a +#define regSDMA1_SDMA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER0_HI 0x367b +#define regSDMA1_SDMA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER1_LO 0x367c +#define regSDMA1_SDMA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER1_HI 0x367d +#define regSDMA1_SDMA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER2_LO 0x367e +#define regSDMA1_SDMA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER2_HI 0x367f +#define regSDMA1_SDMA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER3_LO 0x3680 +#define regSDMA1_SDMA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER3_HI 0x3681 +#define regSDMA1_SDMA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER4_LO 0x3682 +#define regSDMA1_SDMA_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER4_HI 0x3683 +#define regSDMA1_SDMA_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER5_LO 0x3684 +#define regSDMA1_SDMA_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSDMA1_SDMA_PERFCOUNTER5_HI 0x3685 +#define regSDMA1_SDMA_PERFCOUNTER5_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapwrdec:1 +// base address: 0x3c434 +#define regSDMA1_GFX_ICG_SDMA_CTRL 0x510d +#define regSDMA1_GFX_ICG_SDMA_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_grbmdec +// base address: 0x8000 +#define regGRBM_CNTL 0x0da0 +#define regGRBM_CNTL_BASE_IDX 0 +#define regGRBM_SKEW_CNTL 0x0da1 +#define regGRBM_SKEW_CNTL_BASE_IDX 0 +#define regGRBM_STATUS2 0x0da2 +#define regGRBM_STATUS2_BASE_IDX 0 +#define regGRBM_PWR_CNTL 0x0da3 +#define regGRBM_PWR_CNTL_BASE_IDX 0 +#define regGRBM_STATUS 0x0da4 +#define regGRBM_STATUS_BASE_IDX 0 +#define regGRBM_STATUS_SE0 0x0da5 +#define regGRBM_STATUS_SE0_BASE_IDX 0 +#define regGRBM_STATUS_SE1 0x0da6 +#define regGRBM_STATUS_SE1_BASE_IDX 0 +#define regGRBM_STATUS3 0x0da7 +#define regGRBM_STATUS3_BASE_IDX 0 +#define regGRBM_SOFT_RESET 0x0da8 +#define regGRBM_SOFT_RESET_BASE_IDX 0 +#define regGRBM_FAO_CNT 0x0dab +#define regGRBM_FAO_CNT_BASE_IDX 0 +#define regGRBM_GFX_CLKEN_CNTL 0x0dac +#define regGRBM_GFX_CLKEN_CNTL_BASE_IDX 0 +#define regGRBM_WAIT_IDLE_CLOCKS 0x0dad +#define regGRBM_WAIT_IDLE_CLOCKS_BASE_IDX 0 +#define regGRBM_READ_ERROR 0x0db6 +#define regGRBM_READ_ERROR_BASE_IDX 0 +#define regGRBM_READ_ERROR2 0x0db7 +#define regGRBM_READ_ERROR2_BASE_IDX 0 +#define regGRBM_INT_CNTL 0x0db8 +#define regGRBM_INT_CNTL_BASE_IDX 0 +#define regGRBM_TRAP_OP 0x0db9 +#define regGRBM_TRAP_OP_BASE_IDX 0 +#define regGRBM_TRAP_ADDR 0x0dba +#define regGRBM_TRAP_ADDR_BASE_IDX 0 +#define regGRBM_TRAP_ADDR_MSK 0x0dbb +#define regGRBM_TRAP_ADDR_MSK_BASE_IDX 0 +#define regGRBM_TRAP_WD 0x0dbc +#define regGRBM_TRAP_WD_BASE_IDX 0 +#define regGRBM_TRAP_WD_MSK 0x0dbd +#define regGRBM_TRAP_WD_MSK_BASE_IDX 0 +#define regGRBM_DSM_BYPASS 0x0dbe +#define regGRBM_DSM_BYPASS_BASE_IDX 0 +#define regGRBM_WRITE_ERROR 0x0dbf +#define regGRBM_WRITE_ERROR_BASE_IDX 0 +#define regGRBM_IOV_ERROR_FIFO 0x0dc0 +#define regGRBM_IOV_ERROR_FIFO_BASE_IDX 0 +#define regGRBM_CHIP_REVISION 0x0dc1 +#define regGRBM_CHIP_REVISION_BASE_IDX 0 +#define regGRBM_RSMU_CFG 0x0dc3 +#define regGRBM_RSMU_CFG_BASE_IDX 0 +#define regGRBM_IH_CREDIT 0x0dc4 +#define regGRBM_IH_CREDIT_BASE_IDX 0 +#define regGRBM_PWR_CNTL2 0x0dc5 +#define regGRBM_PWR_CNTL2_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_START 0x0dc6 +#define regGRBM_UTCL2_INVAL_RANGE_START_BASE_IDX 0 +#define regGRBM_UTCL2_INVAL_RANGE_END 0x0dc7 +#define regGRBM_UTCL2_INVAL_RANGE_END_BASE_IDX 0 +#define regGRBM_RSMU_READ_ERROR 0x0dc8 +#define regGRBM_RSMU_READ_ERROR_BASE_IDX 0 +#define regGRBM_INVALID_PIPE 0x0dc9 +#define regGRBM_INVALID_PIPE_BASE_IDX 0 +#define regGRBM_FENCE_RANGE0 0x0dca +#define regGRBM_FENCE_RANGE0_BASE_IDX 0 +#define regGRBM_FENCE_RANGE1 0x0dcb +#define regGRBM_FENCE_RANGE1_BASE_IDX 0 +#define regGRBM_CHICKEN_BITS0 0x0dcc +#define regGRBM_CHICKEN_BITS0_BASE_IDX 0 +#define regGRBM_CHICKEN_BITS1 0x0dcd +#define regGRBM_CHICKEN_BITS1_BASE_IDX 0 +#define regCC_GC_FULL_SA_UNIT_DISABLE 0x0dd9 +#define regCC_GC_FULL_SA_UNIT_DISABLE_BASE_IDX 0 +#define regGRBM_SCRATCH_REG0 0x0de0 +#define regGRBM_SCRATCH_REG0_BASE_IDX 0 +#define regGRBM_SCRATCH_REG1 0x0de1 +#define regGRBM_SCRATCH_REG1_BASE_IDX 0 +#define regGRBM_SCRATCH_REG2 0x0de2 +#define regGRBM_SCRATCH_REG2_BASE_IDX 0 +#define regGRBM_SCRATCH_REG3 0x0de3 +#define regGRBM_SCRATCH_REG3_BASE_IDX 0 +#define regGRBM_SCRATCH_REG4 0x0de4 +#define regGRBM_SCRATCH_REG4_BASE_IDX 0 +#define regGRBM_SCRATCH_REG5 0x0de5 +#define regGRBM_SCRATCH_REG5_BASE_IDX 0 +#define regGRBM_SCRATCH_REG6 0x0de6 +#define regGRBM_SCRATCH_REG6_BASE_IDX 0 +#define regGRBM_SCRATCH_REG7 0x0de7 +#define regGRBM_SCRATCH_REG7_BASE_IDX 0 +#define regVIOLATION_DATA_ASYNC_VF_PROG 0x0df1 +#define regVIOLATION_DATA_ASYNC_VF_PROG_BASE_IDX 0 +#define regGRBM_INTF_CNTL 0x0df6 +#define regGRBM_INTF_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cpdec +// base address: 0x8200 +#define regCP_CPC_DEBUG_CNTL 0x0e20 +#define regCP_CPC_DEBUG_CNTL_BASE_IDX 0 +#define regCP_CPC_DEBUG_DATA 0x0e21 +#define regCP_CPC_DEBUG_DATA_BASE_IDX 0 +#define regCP_CPF_DEBUG_CNTL 0x0e22 +#define regCP_CPF_DEBUG_CNTL_BASE_IDX 0 +#define regCP_CPF_DEBUG_DATA 0x0e23 +#define regCP_CPF_DEBUG_DATA_BASE_IDX 0 +#define regCP_CPC_STATUS 0x0e24 +#define regCP_CPC_STATUS_BASE_IDX 0 +#define regCP_CPC_BUSY_STAT 0x0e25 +#define regCP_CPC_BUSY_STAT_BASE_IDX 0 +#define regCP_CPC_STALLED_STAT1 0x0e26 +#define regCP_CPC_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPF_STATUS 0x0e27 +#define regCP_CPF_STATUS_BASE_IDX 0 +#define regCP_CPF_BUSY_STAT 0x0e28 +#define regCP_CPF_BUSY_STAT_BASE_IDX 0 +#define regCP_CPF_STALLED_STAT1 0x0e29 +#define regCP_CPF_STALLED_STAT1_BASE_IDX 0 +#define regCP_CPC_BUSY_STAT2 0x0e2a +#define regCP_CPC_BUSY_STAT2_BASE_IDX 0 +#define regCP_CPC_GRBM_FREE_COUNT 0x0e2b +#define regCP_CPC_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPC_PRIV_VIOLATION_ADDR 0x0e2c +#define regCP_CPC_PRIV_VIOLATION_ADDR_BASE_IDX 0 +#define regCP_CPC_PRIV_VIOLATION_ADDR_HI 0x0e2d +#define regCP_CPC_PRIV_VIOLATION_ADDR_HI_BASE_IDX 0 +#define regCP_MEC_ME1_HEADER_DUMP 0x0e2e +#define regCP_MEC_ME1_HEADER_DUMP_BASE_IDX 0 +#define regCP_CPC_SCRATCH_INDEX 0x0e30 +#define regCP_CPC_SCRATCH_INDEX_BASE_IDX 0 +#define regCP_CPC_SCRATCH_DATA 0x0e31 +#define regCP_CPC_SCRATCH_DATA_BASE_IDX 0 +#define regCP_CPF_GRBM_FREE_COUNT 0x0e32 +#define regCP_CPF_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_CPF_BUSY_STAT2 0x0e33 +#define regCP_CPF_BUSY_STAT2_BASE_IDX 0 +#define regCP_CPC_HALT_HYST_COUNT 0x0e47 +#define regCP_CPC_HALT_HYST_COUNT_BASE_IDX 0 +#define regCP_STALLED_STAT3 0x0f3c +#define regCP_STALLED_STAT3_BASE_IDX 0 +#define regCP_STALLED_STAT1 0x0f3d +#define regCP_STALLED_STAT1_BASE_IDX 0 +#define regCP_STALLED_STAT2 0x0f3e +#define regCP_STALLED_STAT2_BASE_IDX 0 +#define regCP_BUSY_STAT 0x0f3f +#define regCP_BUSY_STAT_BASE_IDX 0 +#define regCP_STAT 0x0f40 +#define regCP_STAT_BASE_IDX 0 +#define regCP_ME_HEADER_DUMP 0x0f41 +#define regCP_ME_HEADER_DUMP_BASE_IDX 0 +#define regCP_PFP_HEADER_DUMP 0x0f42 +#define regCP_PFP_HEADER_DUMP_BASE_IDX 0 +#define regCP_GRBM_FREE_COUNT 0x0f43 +#define regCP_GRBM_FREE_COUNT_BASE_IDX 0 +#define regCP_PFP_INSTR_PNTR 0x0f45 +#define regCP_PFP_INSTR_PNTR_BASE_IDX 0 +#define regCP_ME_INSTR_PNTR 0x0f46 +#define regCP_ME_INSTR_PNTR_BASE_IDX 0 +#define regCP_CSF_STAT 0x0f54 +#define regCP_CSF_STAT_BASE_IDX 0 +#define regCP_CNTX_STAT 0x0f58 +#define regCP_CNTX_STAT_BASE_IDX 0 +#define regCP_ME_PREEMPTION 0x0f59 +#define regCP_ME_PREEMPTION_BASE_IDX 0 +#define regCP_RB0_RPTR 0x0f60 +#define regCP_RB0_RPTR_BASE_IDX 0 +#define regCP_RB_RPTR 0x0f60 +#define regCP_RB_RPTR_BASE_IDX 0 +#define regCP_RB_WPTR_DELAY 0x0f61 +#define regCP_RB_WPTR_DELAY_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_CNTL 0x0f62 +#define regCP_RB_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_ROQ1_THRESHOLDS 0x0f75 +#define regCP_ROQ1_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ2_THRESHOLDS 0x0f76 +#define regCP_ROQ2_THRESHOLDS_BASE_IDX 0 +#define regCP_STQ_THRESHOLDS 0x0f77 +#define regCP_STQ_THRESHOLDS_BASE_IDX 0 +#define regCP_MEQ_THRESHOLDS 0x0f79 +#define regCP_MEQ_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ_AVAIL 0x0f7a +#define regCP_ROQ_AVAIL_BASE_IDX 0 +#define regCP_STQ_AVAIL 0x0f7b +#define regCP_STQ_AVAIL_BASE_IDX 0 +#define regCP_ROQ2_AVAIL 0x0f7c +#define regCP_ROQ2_AVAIL_BASE_IDX 0 +#define regCP_MEQ_AVAIL 0x0f7d +#define regCP_MEQ_AVAIL_BASE_IDX 0 +#define regCP_CMD_INDEX 0x0f7e +#define regCP_CMD_INDEX_BASE_IDX 0 +#define regCP_CMD_DATA 0x0f7f +#define regCP_CMD_DATA_BASE_IDX 0 +#define regCP_ROQ_RB_STAT 0x0f80 +#define regCP_ROQ_RB_STAT_BASE_IDX 0 +#define regCP_ROQ_IB1_STAT 0x0f81 +#define regCP_ROQ_IB1_STAT_BASE_IDX 0 +#define regCP_ROQ_IB2_STAT 0x0f82 +#define regCP_ROQ_IB2_STAT_BASE_IDX 0 +#define regCP_STQ_STAT 0x0f83 +#define regCP_STQ_STAT_BASE_IDX 0 +#define regCP_STQ_WR_STAT 0x0f84 +#define regCP_STQ_WR_STAT_BASE_IDX 0 +#define regCP_MEQ_STAT 0x0f85 +#define regCP_MEQ_STAT_BASE_IDX 0 +#define regCP_ROQ3_THRESHOLDS 0x0f8c +#define regCP_ROQ3_THRESHOLDS_BASE_IDX 0 +#define regCP_ROQ_DB_STAT 0x0f8d +#define regCP_ROQ_DB_STAT_BASE_IDX 0 +#define regCP_INT_STAT_DEBUG 0x0f97 +#define regCP_INT_STAT_DEBUG_BASE_IDX 0 +#define regCP_DEBUG_CNTL 0x0f98 +#define regCP_DEBUG_CNTL_BASE_IDX 0 +#define regCP_DEBUG_DATA 0x0f99 +#define regCP_DEBUG_DATA_BASE_IDX 0 +#define regCP_PRIV_VIOLATION_ADDR 0x0f9a +#define regCP_PRIV_VIOLATION_ADDR_BASE_IDX 0 +#define regCP_PRIV_VIOLATION_ADDR_HI 0x0f9b +#define regCP_PRIV_VIOLATION_ADDR_HI_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_padec +// base address: 0x8800 +#define regVGT_DMA_DATA_FIFO_DEPTH 0x0fcd +#define regVGT_DMA_DATA_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DMA_REQ_FIFO_DEPTH 0x0fce +#define regVGT_DMA_REQ_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_DRAW_INIT_FIFO_DEPTH 0x0fcf +#define regVGT_DRAW_INIT_FIFO_DEPTH_BASE_IDX 0 +#define regVGT_MC_LAT_CNTL 0x0fd6 +#define regVGT_MC_LAT_CNTL_BASE_IDX 0 +#define regIA_UTCL1_STATUS_2 0x0fd7 +#define regIA_UTCL1_STATUS_2_BASE_IDX 0 +#define regGE_WD_CNTL_STATUS 0x0fdf +#define regGE_WD_CNTL_STATUS_BASE_IDX 0 +#define regWD_UTCL1_CNTL 0x0fe3 +#define regWD_UTCL1_CNTL_BASE_IDX 0 +#define regWD_UTCL1_STATUS 0x0fe4 +#define regWD_UTCL1_STATUS_BASE_IDX 0 +#define regIA_UTCL1_CNTL 0x0fe6 +#define regIA_UTCL1_CNTL_BASE_IDX 0 +#define regIA_UTCL1_STATUS 0x0fe7 +#define regIA_UTCL1_STATUS_BASE_IDX 0 +#define regCC_GC_SA_UNIT_DISABLE 0x0fe9 +#define regCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 +#define regGE_FED_STATUS 0x0fea +#define regGE_FED_STATUS_BASE_IDX 0 +#define regGE_PRIV_CONTROL 0x1004 +#define regGE_PRIV_CONTROL_BASE_IDX 0 +#define regGE_STATUS 0x1005 +#define regGE_STATUS_BASE_IDX 0 +#define regVGT_GS_MAX_WAVE_ID 0x1009 +#define regVGT_GS_MAX_WAVE_ID_BASE_IDX 0 +#define regGFX_PIPE_CONTROL 0x100d +#define regGFX_PIPE_CONTROL_BASE_IDX 0 +#define regVGT_RESET_DEBUG 0x1014 +#define regVGT_RESET_DEBUG_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_shdec +// base address: 0xb000 +#define regCOMPUTE_DISPATCH_INITIATOR 0x1ba0 +#define regCOMPUTE_DISPATCH_INITIATOR_BASE_IDX 0 +#define regCOMPUTE_DIM_X 0x1ba1 +#define regCOMPUTE_DIM_X_BASE_IDX 0 +#define regCOMPUTE_DIM_Y 0x1ba2 +#define regCOMPUTE_DIM_Y_BASE_IDX 0 +#define regCOMPUTE_DIM_Z 0x1ba3 +#define regCOMPUTE_DIM_Z_BASE_IDX 0 +#define regCOMPUTE_START_X 0x1ba4 +#define regCOMPUTE_START_X_BASE_IDX 0 +#define regCOMPUTE_START_Y 0x1ba5 +#define regCOMPUTE_START_Y_BASE_IDX 0 +#define regCOMPUTE_START_Z 0x1ba6 +#define regCOMPUTE_START_Z_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_X 0x1ba7 +#define regCOMPUTE_NUM_THREAD_X_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Y 0x1ba8 +#define regCOMPUTE_NUM_THREAD_Y_BASE_IDX 0 +#define regCOMPUTE_NUM_THREAD_Z 0x1ba9 +#define regCOMPUTE_NUM_THREAD_Z_BASE_IDX 0 +#define regCOMPUTE_PIPELINESTAT_ENABLE 0x1baa +#define regCOMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PERFCOUNT_ENABLE 0x1bab +#define regCOMPUTE_PERFCOUNT_ENABLE_BASE_IDX 0 +#define regCOMPUTE_PGM_LO 0x1bac +#define regCOMPUTE_PGM_LO_BASE_IDX 0 +#define regCOMPUTE_PGM_HI 0x1bad +#define regCOMPUTE_PGM_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO 0x1bae +#define regCOMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI 0x1baf +#define regCOMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO 0x1bb0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI 0x1bb1 +#define regCOMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC1 0x1bb2 +#define regCOMPUTE_PGM_RSRC1_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC2 0x1bb3 +#define regCOMPUTE_PGM_RSRC2_BASE_IDX 0 +#define regCOMPUTE_VMID 0x1bb4 +#define regCOMPUTE_VMID_BASE_IDX 0 +#define regCOMPUTE_RESOURCE_LIMITS 0x1bb5 +#define regCOMPUTE_RESOURCE_LIMITS_BASE_IDX 0 +#define regCOMPUTE_TMPRING_SIZE 0x1bb6 +#define regCOMPUTE_TMPRING_SIZE_BASE_IDX 0 +#define regCOMPUTE_RESTART_X 0x1bb7 +#define regCOMPUTE_RESTART_X_BASE_IDX 0 +#define regCOMPUTE_RESTART_Y 0x1bb8 +#define regCOMPUTE_RESTART_Y_BASE_IDX 0 +#define regCOMPUTE_RESTART_Z 0x1bb9 +#define regCOMPUTE_RESTART_Z_BASE_IDX 0 +#define regCOMPUTE_THREAD_TRACE_ENABLE 0x1bba +#define regCOMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 0 +#define regCOMPUTE_MISC_RESERVED 0x1bbb +#define regCOMPUTE_MISC_RESERVED_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_ID 0x1bbc +#define regCOMPUTE_DISPATCH_ID_BASE_IDX 0 +#define regCOMPUTE_THREADGROUP_ID 0x1bbd +#define regCOMPUTE_THREADGROUP_ID_BASE_IDX 0 +#define regCOMPUTE_REQ_CTRL 0x1bbe +#define regCOMPUTE_REQ_CTRL_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_0 0x1bbf +#define regCOMPUTE_USER_ACCUM_0_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_1 0x1bc0 +#define regCOMPUTE_USER_ACCUM_1_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_2 0x1bc1 +#define regCOMPUTE_USER_ACCUM_2_BASE_IDX 0 +#define regCOMPUTE_USER_ACCUM_3 0x1bc2 +#define regCOMPUTE_USER_ACCUM_3_BASE_IDX 0 +#define regCOMPUTE_PGM_RSRC3 0x1bc3 +#define regCOMPUTE_PGM_RSRC3_BASE_IDX 0 +#define regCOMPUTE_DDID_INDEX 0x1bc4 +#define regCOMPUTE_DDID_INDEX_BASE_IDX 0 +#define regCOMPUTE_SHADER_CHKSUM 0x1bc5 +#define regCOMPUTE_SHADER_CHKSUM_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_INTERLEAVE 0x1bc6 +#define regCOMPUTE_DISPATCH_INTERLEAVE_BASE_IDX 0 +#define regCOMPUTE_CURRENT_LOGICAL_XCC_ID 0x1bc7 +#define regCOMPUTE_CURRENT_LOGICAL_XCC_ID_BASE_IDX 0 +#define regCOMPUTE_RESTART_CG_TG_ID 0x1bc8 +#define regCOMPUTE_RESTART_CG_TG_ID_BASE_IDX 0 +#define regCOMPUTE_TG_CHUNK_SIZE 0x1bc9 +#define regCOMPUTE_TG_CHUNK_SIZE_BASE_IDX 0 +#define regCOMPUTE_RESTORE_TG_CHUNK_SIZE 0x1bca +#define regCOMPUTE_RESTORE_TG_CHUNK_SIZE_BASE_IDX 0 +#define regCOMPUTE_SPARE_1 0x1bcb +#define regCOMPUTE_SPARE_1_BASE_IDX 0 +#define regCOMPUTE_SPARE_2 0x1bcc +#define regCOMPUTE_SPARE_2_BASE_IDX 0 +#define regCOMPUTE_PRESCALED_DIM_X 0x1bcd +#define regCOMPUTE_PRESCALED_DIM_X_BASE_IDX 0 +#define regCOMPUTE_PRESCALED_DIM_Y 0x1bce +#define regCOMPUTE_PRESCALED_DIM_Y_BASE_IDX 0 +#define regCOMPUTE_PRESCALED_DIM_Z 0x1bcf +#define regCOMPUTE_PRESCALED_DIM_Z_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE0 0x1bd0 +#define regCOMPUTE_DESTINATION_EN_SE0_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0 0x1bd0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE1 0x1bd1 +#define regCOMPUTE_DESTINATION_EN_SE1_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1 0x1bd1 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE2 0x1bd2 +#define regCOMPUTE_DESTINATION_EN_SE2_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2 0x1bd2 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 0 +#define regCOMPUTE_DESTINATION_EN_SE3 0x1bd3 +#define regCOMPUTE_DESTINATION_EN_SE3_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3 0x1bd3 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE4 0x1bd4 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE5 0x1bd5 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE6 0x1bd6 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE7 0x1bd7 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 0 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE8 0x1bd8 +#define regCOMPUTE_STATIC_THREAD_MGMT_SE8_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_0 0x1be0 +#define regCOMPUTE_USER_DATA_0_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_1 0x1be1 +#define regCOMPUTE_USER_DATA_1_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_2 0x1be2 +#define regCOMPUTE_USER_DATA_2_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_3 0x1be3 +#define regCOMPUTE_USER_DATA_3_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_4 0x1be4 +#define regCOMPUTE_USER_DATA_4_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_5 0x1be5 +#define regCOMPUTE_USER_DATA_5_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_6 0x1be6 +#define regCOMPUTE_USER_DATA_6_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_7 0x1be7 +#define regCOMPUTE_USER_DATA_7_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_8 0x1be8 +#define regCOMPUTE_USER_DATA_8_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_9 0x1be9 +#define regCOMPUTE_USER_DATA_9_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_10 0x1bea +#define regCOMPUTE_USER_DATA_10_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_11 0x1beb +#define regCOMPUTE_USER_DATA_11_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_12 0x1bec +#define regCOMPUTE_USER_DATA_12_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_13 0x1bed +#define regCOMPUTE_USER_DATA_13_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_14 0x1bee +#define regCOMPUTE_USER_DATA_14_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_15 0x1bef +#define regCOMPUTE_USER_DATA_15_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_16 0x1bf0 +#define regCOMPUTE_USER_DATA_16_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_17 0x1bf1 +#define regCOMPUTE_USER_DATA_17_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_18 0x1bf2 +#define regCOMPUTE_USER_DATA_18_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_19 0x1bf3 +#define regCOMPUTE_USER_DATA_19_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_20 0x1bf4 +#define regCOMPUTE_USER_DATA_20_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_21 0x1bf5 +#define regCOMPUTE_USER_DATA_21_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_22 0x1bf6 +#define regCOMPUTE_USER_DATA_22_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_23 0x1bf7 +#define regCOMPUTE_USER_DATA_23_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_24 0x1bf8 +#define regCOMPUTE_USER_DATA_24_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_25 0x1bf9 +#define regCOMPUTE_USER_DATA_25_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_26 0x1bfa +#define regCOMPUTE_USER_DATA_26_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_27 0x1bfb +#define regCOMPUTE_USER_DATA_27_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_28 0x1bfc +#define regCOMPUTE_USER_DATA_28_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_29 0x1bfd +#define regCOMPUTE_USER_DATA_29_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_30 0x1bfe +#define regCOMPUTE_USER_DATA_30_BASE_IDX 0 +#define regCOMPUTE_USER_DATA_31 0x1bff +#define regCOMPUTE_USER_DATA_31_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH 0x1c0d +#define regCOMPUTE_RELAUNCH_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH_STATE_PAYLOAD 0x1c0d +#define regCOMPUTE_RELAUNCH_STATE_PAYLOAD_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO 0x1c0e +#define regCOMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 0 +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI 0x1c0f +#define regCOMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH2 0x1c10 +#define regCOMPUTE_RELAUNCH2_BASE_IDX 0 +#define regCOMPUTE_RELAUNCH2_STATE_PAYLOAD 0x1c10 +#define regCOMPUTE_RELAUNCH2_STATE_PAYLOAD_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_TUNNEL 0x1c1d +#define regCOMPUTE_DISPATCH_TUNNEL_BASE_IDX 0 +#define regCOMPUTE_DISPATCH_END 0x1c1e +#define regCOMPUTE_DISPATCH_END_BASE_IDX 0 +#define regCOMPUTE_NOWHERE 0x1c1f +#define regCOMPUTE_NOWHERE_BASE_IDX 0 +#define regSH_RESERVED_REG0 0x1c20 +#define regSH_RESERVED_REG0_BASE_IDX 0 +#define regSH_RESERVED_REG1 0x1c21 +#define regSH_RESERVED_REG1_BASE_IDX 0 +#define regCOMPUTE_PREALLOC_CR_DB_BUFFER_SIZE 0x1c22 +#define regCOMPUTE_PREALLOC_CR_DB_BUFFER_SIZE_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_gccacdec +// base address: 0x2eb40 +#define regGC_CAC_CTRL_1 0x1ad0 +#define regGC_CAC_CTRL_1_BASE_IDX 1 +#define regGC_CAC_CTRL_2 0x1ad1 +#define regGC_CAC_CTRL_2_BASE_IDX 1 +#define regGC_CAC_AGGR_LOWER 0x1ad2 +#define regGC_CAC_AGGR_LOWER_BASE_IDX 1 +#define regGC_CAC_AGGR_UPPER 0x1ad3 +#define regGC_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE0_CAC_AGGR_LOWER 0x1ad4 +#define regSE0_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE0_CAC_AGGR_UPPER 0x1ad5 +#define regSE0_CAC_AGGR_UPPER_BASE_IDX 1 +#define regSE1_CAC_AGGR_LOWER 0x1ad6 +#define regSE1_CAC_AGGR_LOWER_BASE_IDX 1 +#define regSE1_CAC_AGGR_UPPER 0x1ad7 +#define regSE1_CAC_AGGR_UPPER_BASE_IDX 1 +#define regGC_CAC_AGGR_GFXCLK_CYCLE 0x1ae6 +#define regGC_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE0_CAC_AGGR_GFXCLK_CYCLE 0x1ae7 +#define regSE0_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regSE1_CAC_AGGR_GFXCLK_CYCLE 0x1ae8 +#define regSE1_CAC_AGGR_GFXCLK_CYCLE_BASE_IDX 1 +#define regGC_CAC_OVR_VAL_LOWER 0x1af0 +#define regGC_CAC_OVR_VAL_LOWER_BASE_IDX 1 +#define regGC_CAC_OVR_VAL_UPPER 0x1af1 +#define regGC_CAC_OVR_VAL_UPPER_BASE_IDX 1 +#define regGC_EDC_CTRL 0x1af4 +#define regGC_EDC_CTRL_BASE_IDX 1 +#define regGC_EDC_STRETCH_CTRL 0x1af5 +#define regGC_EDC_STRETCH_CTRL_BASE_IDX 1 +#define regGC_EDC_THRESHOLD_LO 0x1af6 +#define regGC_EDC_THRESHOLD_LO_BASE_IDX 1 +#define regGC_EDC_THRESHOLD_HI 0x1af7 +#define regGC_EDC_THRESHOLD_HI_BASE_IDX 1 +#define regGC_EDC_STRETCH_THRESHOLD_LO 0x1af8 +#define regGC_EDC_STRETCH_THRESHOLD_LO_BASE_IDX 1 +#define regGC_EDC_STRETCH_THRESHOLD_HI 0x1af9 +#define regGC_EDC_STRETCH_THRESHOLD_HI_BASE_IDX 1 +#define regEDC_HYSTERESIS_CNTL 0x1afa +#define regEDC_HYSTERESIS_CNTL_BASE_IDX 1 +#define regGC_THROTTLE_CTRL 0x1afb +#define regGC_THROTTLE_CTRL_BASE_IDX 1 +#define regGC_THROTTLE_CTRL1 0x1afc +#define regGC_THROTTLE_CTRL1_BASE_IDX 1 +#define regGC_THROTTLE_CTRL2 0x1afd +#define regGC_THROTTLE_CTRL2_BASE_IDX 1 +#define regEDC_STALL_PATTERN_CTRL 0x1afe +#define regEDC_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regPCC_STALL_PATTERN_CTRL 0x1aff +#define regPCC_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_CTRL 0x1b00 +#define regPWRBRK_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regEDC_STALL_PATTERN_1_2 0x1b01 +#define regEDC_STALL_PATTERN_1_2_BASE_IDX 1 +#define regEDC_STALL_PATTERN_3_4 0x1b02 +#define regEDC_STALL_PATTERN_3_4_BASE_IDX 1 +#define regEDC_STALL_PATTERN_5_6 0x1b03 +#define regEDC_STALL_PATTERN_5_6_BASE_IDX 1 +#define regEDC_STALL_PATTERN_7 0x1b04 +#define regEDC_STALL_PATTERN_7_BASE_IDX 1 +#define regPCC_STALL_PATTERN_1_2 0x1b05 +#define regPCC_STALL_PATTERN_1_2_BASE_IDX 1 +#define regPCC_STALL_PATTERN_3_4 0x1b06 +#define regPCC_STALL_PATTERN_3_4_BASE_IDX 1 +#define regPCC_STALL_PATTERN_5_6 0x1b07 +#define regPCC_STALL_PATTERN_5_6_BASE_IDX 1 +#define regPCC_STALL_PATTERN_7 0x1b08 +#define regPCC_STALL_PATTERN_7_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_1_2 0x1b09 +#define regPWRBRK_STALL_PATTERN_1_2_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_3_4 0x1b0a +#define regPWRBRK_STALL_PATTERN_3_4_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_5_6 0x1b0b +#define regPWRBRK_STALL_PATTERN_5_6_BASE_IDX 1 +#define regPWRBRK_STALL_PATTERN_7 0x1b0c +#define regPWRBRK_STALL_PATTERN_7_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_CTRL 0x1b0d +#define regDIDT_STALL_PATTERN_CTRL_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_1_2 0x1b0e +#define regDIDT_STALL_PATTERN_1_2_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_3_4 0x1b0f +#define regDIDT_STALL_PATTERN_3_4_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_5_6 0x1b10 +#define regDIDT_STALL_PATTERN_5_6_BASE_IDX 1 +#define regDIDT_STALL_PATTERN_7 0x1b11 +#define regDIDT_STALL_PATTERN_7_BASE_IDX 1 +#define regPCC_PWRBRK_HYSTERESIS_CTRL 0x1b12 +#define regPCC_PWRBRK_HYSTERESIS_CTRL_BASE_IDX 1 +#define regEDC_STRETCH_PERF_COUNTER 0x1b13 +#define regEDC_STRETCH_PERF_COUNTER_BASE_IDX 1 +#define regEDC_UNSTRETCH_PERF_COUNTER 0x1b14 +#define regEDC_UNSTRETCH_PERF_COUNTER_BASE_IDX 1 +#define regEDC_STRETCH_NUM_PERF_COUNTER 0x1b15 +#define regEDC_STRETCH_NUM_PERF_COUNTER_BASE_IDX 1 +#define regGC_EDC_STATUS 0x1b16 +#define regGC_EDC_STATUS_BASE_IDX 1 +#define regGC_EDC_OVERFLOW 0x1b17 +#define regGC_EDC_OVERFLOW_BASE_IDX 1 +#define regGC_EDC_ROLLING_POWER_DELTA_LO 0x1b18 +#define regGC_EDC_ROLLING_POWER_DELTA_LO_BASE_IDX 1 +#define regGC_EDC_ROLLING_POWER_DELTA_HI 0x1b19 +#define regGC_EDC_ROLLING_POWER_DELTA_HI_BASE_IDX 1 +#define regGC_EDC_AVG_POWER_DELTA_LO 0x1b1a +#define regGC_EDC_AVG_POWER_DELTA_LO_BASE_IDX 1 +#define regGC_EDC_AVG_POWER_DELTA_HI 0x1b1b +#define regGC_EDC_AVG_POWER_DELTA_HI_BASE_IDX 1 +#define regGC_THROTTLE_STATUS 0x1b1c +#define regGC_THROTTLE_STATUS_BASE_IDX 1 +#define regEDC_PERF_COUNTER 0x1b1d +#define regEDC_PERF_COUNTER_BASE_IDX 1 +#define regPCC_PERF_COUNTER 0x1b1e +#define regPCC_PERF_COUNTER_BASE_IDX 1 +#define regPWRBRK_PERF_COUNTER 0x1b1f +#define regPWRBRK_PERF_COUNTER_BASE_IDX 1 +#define regEDC_HYSTERESIS_STAT 0x1b20 +#define regEDC_HYSTERESIS_STAT_BASE_IDX 1 +#define regDIDT_HYSTERESIS_STAT 0x1b21 +#define regDIDT_HYSTERESIS_STAT_BASE_IDX 1 +#define regDIDT_PERF_COUNTER 0x1b22 +#define regDIDT_PERF_COUNTER_BASE_IDX 1 +#define regGC_EDC_CLK_MONITOR_CTRL 0x1b23 +#define regGC_EDC_CLK_MONITOR_CTRL_BASE_IDX 1 +#define regGC_CAC_SOFT_CTRL 0x1b24 +#define regGC_CAC_SOFT_CTRL_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CP_0 0x1b30 +#define regGC_CAC_WEIGHT_CP_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CP_1 0x1b31 +#define regGC_CAC_WEIGHT_CP_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_PMM_0 0x1b4b +#define regGC_CAC_WEIGHT_PMM_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_0 0x1b50 +#define regGC_CAC_WEIGHT_SDMA_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_1 0x1b51 +#define regGC_CAC_WEIGHT_SDMA_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_2 0x1b52 +#define regGC_CAC_WEIGHT_SDMA_2_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_3 0x1b53 +#define regGC_CAC_WEIGHT_SDMA_3_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_4 0x1b54 +#define regGC_CAC_WEIGHT_SDMA_4_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_5 0x1b55 +#define regGC_CAC_WEIGHT_SDMA_5_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CHC_0 0x1b56 +#define regGC_CAC_WEIGHT_CHC_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_CHC_1 0x1b57 +#define regGC_CAC_WEIGHT_CHC_1_BASE_IDX 1 +#define regGC_CAC_WEIGHT_RLC_0 0x1b5a +#define regGC_CAC_WEIGHT_RLC_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GRBM_0 0x1b5e +#define regGC_CAC_WEIGHT_GRBM_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_6 0x1b76 +#define regGC_CAC_WEIGHT_SDMA_6_BASE_IDX 1 +#define regGC_CAC_WEIGHT_SDMA_7 0x1b77 +#define regGC_CAC_WEIGHT_SDMA_7_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GLARB_0 0x1b78 +#define regGC_CAC_WEIGHT_GLARB_0_BASE_IDX 1 +#define regGC_CAC_WEIGHT_GLARB_1 0x1b79 +#define regGC_CAC_WEIGHT_GLARB_1_BASE_IDX 1 +#define regXCD_TOTAL_CAC_AGGR_LOWER 0x1b7c +#define regXCD_TOTAL_CAC_AGGR_LOWER_BASE_IDX 1 +#define regXCD_TOTAL_CAC_AGGR_UPPER 0x1b7d +#define regXCD_TOTAL_CAC_AGGR_UPPER_BASE_IDX 1 +#define regGC_EDC_WEIGHTED_DATA_MULTIPLIER 0x1b7e +#define regGC_EDC_WEIGHTED_DATA_MULTIPLIER_BASE_IDX 1 +#define regGC_CAC_IND_INDEX 0x1b8e +#define regGC_CAC_IND_INDEX_BASE_IDX 1 +#define regGC_CAC_IND_DATA 0x1b8f +#define regGC_CAC_IND_DATA_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gc_ea_cpwd_gceadec +// base address: 0xa800 +#define regGC_EA_CPWD_VC_MAP 0x17a0 +#define regGC_EA_CPWD_VC_MAP_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_ARB_FINAL 0x17a1 +#define regGC_EA_CPWD_SDP_ARB_FINAL_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_PRIORITY 0x17a2 +#define regGC_EA_CPWD_SDP_PRIORITY_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_CREDITS 0x17a3 +#define regGC_EA_CPWD_SDP_CREDITS_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_TAG_RESERVE0 0x17a4 +#define regGC_EA_CPWD_SDP_TAG_RESERVE0_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_TAG_RESERVE1 0x17a5 +#define regGC_EA_CPWD_SDP_TAG_RESERVE1_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_TAG_RESERVE2 0x17a6 +#define regGC_EA_CPWD_SDP_TAG_RESERVE2_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_VCC_RESERVE0 0x17a7 +#define regGC_EA_CPWD_SDP_VCC_RESERVE0_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_VCC_RESERVE1 0x17a8 +#define regGC_EA_CPWD_SDP_VCC_RESERVE1_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_VCD_RESERVE0 0x17a9 +#define regGC_EA_CPWD_SDP_VCD_RESERVE0_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_VCD_RESERVE1 0x17aa +#define regGC_EA_CPWD_SDP_VCD_RESERVE1_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_REQ_CNTL 0x17ab +#define regGC_EA_CPWD_SDP_REQ_CNTL_BASE_IDX 0 +#define regGC_EA_CPWD_MISC 0x17ac +#define regGC_EA_CPWD_MISC_BASE_IDX 0 +#define regGC_EA_CPWD_ERR_STATUS 0x17ad +#define regGC_EA_CPWD_ERR_STATUS_BASE_IDX 0 +#define regGC_EA_CPWD_MISC2 0x17ae +#define regGC_EA_CPWD_MISC2_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0 0x17af +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE 0x17b0 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1 0x17b1 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE 0x17b2 +#define regGC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0 0x17b3 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE 0x17b4 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1 0x17b5 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE 0x17b6 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2 0x17b7 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE 0x17b8 +#define regGC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL 0x17b9 +#define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE 0x17ba +#define regGC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE_BASE_IDX 0 +#define regGC_EA_CPWD_INVALID_OPCODE 0x17bb +#define regGC_EA_CPWD_INVALID_OPCODE_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL 0x17bc +#define regGC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_POISON_ERR_LOG 0x17bd +#define regGC_EA_CPWD_SDP_POISON_ERR_LOG_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL 0x17be +#define regGC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_PARITY_ERR_LOG 0x17bf +#define regGC_EA_CPWD_SDP_PARITY_ERR_LOG_BASE_IDX 0 +#define regGC_EA_CPWD_SDP_ENABLE 0x181f +#define regGC_EA_CPWD_SDP_ENABLE_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gcrdec +// base address: 0x9f80 +#define regGCR_PIO_CNTL 0x1580 +#define regGCR_PIO_CNTL_BASE_IDX 0 +#define regGCR_PIO_DATA 0x1581 +#define regGCR_PIO_DATA_BASE_IDX 0 +#define regGCR_NHTOE_CNTL 0x1584 +#define regGCR_NHTOE_CNTL_BASE_IDX 0 +#define regGCR_NHTOE_DATA 0x1585 +#define regGCR_NHTOE_DATA_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cppdec +// base address: 0xc080 +#define regCPC_INT_ADDR1 0x1dd1 +#define regCPC_INT_ADDR1_BASE_IDX 0 +#define regCP_CU_MASK_ADDR_LO 0x1dd2 +#define regCP_CU_MASK_ADDR_LO_BASE_IDX 0 +#define regCP_CU_MASK_ADDR_HI 0x1dd3 +#define regCP_CU_MASK_ADDR_HI_BASE_IDX 0 +#define regCP_CU_MASK_CNTL 0x1dd4 +#define regCP_CU_MASK_CNTL_BASE_IDX 0 +#define regCP_EOPQ_WAIT_TIME 0x1dd5 +#define regCP_EOPQ_WAIT_TIME_BASE_IDX 0 +#define regCP_CPC_MGCG_SYNC_CNTL 0x1dd6 +#define regCP_CPC_MGCG_SYNC_CNTL_BASE_IDX 0 +#define regCPC_INT_INFO 0x1dd7 +#define regCPC_INT_INFO_BASE_IDX 0 +#define regCP_VIRT_STATUS 0x1dd8 +#define regCP_VIRT_STATUS_BASE_IDX 0 +#define regCPC_INT_ADDR 0x1dd9 +#define regCPC_INT_ADDR_BASE_IDX 0 +#define regCPC_INT_PASID 0x1dda +#define regCPC_INT_PASID_BASE_IDX 0 +#define regCP_GFX_ERROR 0x1ddb +#define regCP_GFX_ERROR_BASE_IDX 0 +#define regCPG_UTCL1_CNTL 0x1ddc +#define regCPG_UTCL1_CNTL_BASE_IDX 0 +#define regCPC_UTCL1_CNTL 0x1ddd +#define regCPC_UTCL1_CNTL_BASE_IDX 0 +#define regCPF_UTCL1_CNTL 0x1dde +#define regCPF_UTCL1_CNTL_BASE_IDX 0 +#define regCP_AQL_SMM_STATUS 0x1ddf +#define regCP_AQL_SMM_STATUS_BASE_IDX 0 +#define regCP_RB0_BASE 0x1de0 +#define regCP_RB0_BASE_BASE_IDX 0 +#define regCP_RB_BASE 0x1de0 +#define regCP_RB_BASE_BASE_IDX 0 +#define regCP_RB0_CNTL 0x1de1 +#define regCP_RB0_CNTL_BASE_IDX 0 +#define regCP_RB_CNTL 0x1de1 +#define regCP_RB_CNTL_BASE_IDX 0 +#define regCP_RB_RPTR_WR 0x1de2 +#define regCP_RB_RPTR_WR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR 0x1de3 +#define regCP_RB0_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR 0x1de3 +#define regCP_RB_RPTR_ADDR_BASE_IDX 0 +#define regCP_RB0_RPTR_ADDR_HI 0x1de4 +#define regCP_RB0_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_RPTR_ADDR_HI 0x1de4 +#define regCP_RB_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB0_BUFSZ_MASK 0x1de5 +#define regCP_RB0_BUFSZ_MASK_BASE_IDX 0 +#define regCP_RB_BUFSZ_MASK 0x1de5 +#define regCP_RB_BUFSZ_MASK_BASE_IDX 0 +#define regCP_ME3_INT_STAT_DEBUG 0x1de6 +#define regCP_ME3_INT_STAT_DEBUG_BASE_IDX 0 +#define regGC_PRIV_MODE 0x1de8 +#define regGC_PRIV_MODE_BASE_IDX 0 +#define regCP_INT_CNTL 0x1de9 +#define regCP_INT_CNTL_BASE_IDX 0 +#define regCP_INT_STATUS 0x1dea +#define regCP_INT_STATUS_BASE_IDX 0 +#define regCP_DEVICE_ID 0x1deb +#define regCP_DEVICE_ID_BASE_IDX 0 +#define regCP_ME0_PIPE_PRIORITY_CNTS 0x1dec +#define regCP_ME0_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_RING_PRIORITY_CNTS 0x1dec +#define regCP_RING_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME0_PIPE0_PRIORITY 0x1ded +#define regCP_ME0_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_RING0_PRIORITY 0x1ded +#define regCP_RING0_PRIORITY_BASE_IDX 0 +#define regCP_FATAL_ERROR 0x1df0 +#define regCP_FATAL_ERROR_BASE_IDX 0 +#define regCP_RB_VMID 0x1df1 +#define regCP_RB_VMID_BASE_IDX 0 +#define regCP_ME0_PIPE0_VMID 0x1df2 +#define regCP_ME0_PIPE0_VMID_BASE_IDX 0 +#define regCP_RB0_WPTR 0x1df4 +#define regCP_RB0_WPTR_BASE_IDX 0 +#define regCP_RB_WPTR 0x1df4 +#define regCP_RB_WPTR_BASE_IDX 0 +#define regCP_RB0_WPTR_HI 0x1df5 +#define regCP_RB0_WPTR_HI_BASE_IDX 0 +#define regCP_RB_WPTR_HI 0x1df5 +#define regCP_RB_WPTR_HI_BASE_IDX 0 +#define regCP_PROCESS_QUANTUM 0x1df9 +#define regCP_PROCESS_QUANTUM_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_LOWER 0x1dfa +#define regCP_RB_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_RB_DOORBELL_RANGE_UPPER 0x1dfb +#define regCP_RB_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_LOWER 0x1dfc +#define regCP_MEC_DOORBELL_RANGE_LOWER_BASE_IDX 0 +#define regCP_MEC_DOORBELL_RANGE_UPPER 0x1dfd +#define regCP_MEC_DOORBELL_RANGE_UPPER_BASE_IDX 0 +#define regCPG_UTCL1_ERROR 0x1dfe +#define regCPG_UTCL1_ERROR_BASE_IDX 0 +#define regCPC_UTCL1_ERROR 0x1dff +#define regCPC_UTCL1_ERROR_BASE_IDX 0 +#define regCPF_FED_STATUS 0x1e05 +#define regCPF_FED_STATUS_BASE_IDX 0 +#define regCPC_FED_STATUS 0x1e06 +#define regCPC_FED_STATUS_BASE_IDX 0 +#define regCPG_FED_STATUS 0x1e07 +#define regCPG_FED_STATUS_BASE_IDX 0 +#define regCP_IB1_BUFFER_COUNT 0x1e08 +#define regCP_IB1_BUFFER_COUNT_BASE_IDX 0 +#define regCP_IB2_BUFFER_COUNT 0x1e09 +#define regCP_IB2_BUFFER_COUNT_BASE_IDX 0 +#define regCP_INT_CNTL_RING0 0x1e0a +#define regCP_INT_CNTL_RING0_BASE_IDX 0 +#define regCP_DEBUG_2 0x1e0c +#define regCP_DEBUG_2_BASE_IDX 0 +#define regCP_INT_STATUS_RING0 0x1e0d +#define regCP_INT_STATUS_RING0_BASE_IDX 0 +#define regCP_ME_F32_INTERRUPT 0x1e13 +#define regCP_ME_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PFP_F32_INTERRUPT 0x1e14 +#define regCP_PFP_F32_INTERRUPT_BASE_IDX 0 +#define regCP_MEC1_F32_INTERRUPT 0x1e16 +#define regCP_MEC1_F32_INTERRUPT_BASE_IDX 0 +#define regCP_PWR_CNTL 0x1e18 +#define regCP_PWR_CNTL_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE 0x1e1a +#define regCP_ECC_FIRSTOCCURRENCE_BASE_IDX 0 +#define regCP_ECC_FIRSTOCCURRENCE_RING0 0x1e1b +#define regCP_ECC_FIRSTOCCURRENCE_RING0_BASE_IDX 0 +#define regGB_EDC_MODE 0x1e1e +#define regGB_EDC_MODE_BASE_IDX 0 +#define regCP_DEBUG 0x1e1f +#define regCP_DEBUG_BASE_IDX 0 +#define regCP_CPF_DEBUG 0x1e20 +#define regCP_CPF_DEBUG_BASE_IDX 0 +#define regCP_CPC_DEBUG 0x1e21 +#define regCP_CPC_DEBUG_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL 0x1e23 +#define regCP_PQ_WPTR_POLL_CNTL_BASE_IDX 0 +#define regCP_PQ_WPTR_POLL_CNTL1 0x1e24 +#define regCP_PQ_WPTR_POLL_CNTL1_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_CNTL 0x1e25 +#define regCP_ME1_PIPE0_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_CNTL 0x1e26 +#define regCP_ME1_PIPE1_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_CNTL 0x1e27 +#define regCP_ME1_PIPE2_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_CNTL 0x1e28 +#define regCP_ME1_PIPE3_INT_CNTL_BASE_IDX 0 +#define regCP_ME1_PIPE0_INT_STATUS 0x1e2d +#define regCP_ME1_PIPE0_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE1_INT_STATUS 0x1e2e +#define regCP_ME1_PIPE1_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE2_INT_STATUS 0x1e2f +#define regCP_ME1_PIPE2_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_PIPE3_INT_STATUS 0x1e30 +#define regCP_ME1_PIPE3_INT_STATUS_BASE_IDX 0 +#define regCP_ME1_INT_STAT_DEBUG 0x1e35 +#define regCP_ME1_INT_STAT_DEBUG_BASE_IDX 0 +#define regCP_GFX_QUEUE_INDEX 0x1e37 +#define regCP_GFX_QUEUE_INDEX_BASE_IDX 0 +#define regCC_GC_EDC_CONFIG 0x1e38 +#define regCC_GC_EDC_CONFIG_BASE_IDX 0 +#define regCP_ME1_PIPE_PRIORITY_CNTS 0x1e39 +#define regCP_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 0 +#define regCP_ME1_PIPE0_PRIORITY 0x1e3a +#define regCP_ME1_PIPE0_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE1_PRIORITY 0x1e3b +#define regCP_ME1_PIPE1_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE2_PRIORITY 0x1e3c +#define regCP_ME1_PIPE2_PRIORITY_BASE_IDX 0 +#define regCP_ME1_PIPE3_PRIORITY 0x1e3d +#define regCP_ME1_PIPE3_PRIORITY_BASE_IDX 0 +#define regCP_PFP_PRGRM_CNTR_START 0x1e44 +#define regCP_PFP_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_ME_PRGRM_CNTR_START 0x1e45 +#define regCP_ME_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_MEC1_PRGRM_CNTR_START 0x1e46 +#define regCP_MEC1_PRGRM_CNTR_START_BASE_IDX 0 +#define regCP_PFP_INTR_ROUTINE_START 0x1e49 +#define regCP_PFP_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_ME_INTR_ROUTINE_START 0x1e4a +#define regCP_ME_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_MEC1_INTR_ROUTINE_START 0x1e4b +#define regCP_MEC1_INTR_ROUTINE_START_BASE_IDX 0 +#define regCP_CONTEXT_CNTL 0x1e4d +#define regCP_CONTEXT_CNTL_BASE_IDX 0 +#define regCP_MAX_CONTEXT 0x1e4e +#define regCP_MAX_CONTEXT_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME1 0x1e4f +#define regCP_IQ_WAIT_TIME1_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME2 0x1e50 +#define regCP_IQ_WAIT_TIME2_BASE_IDX 0 +#define regCP_RB0_BASE_HI 0x1e51 +#define regCP_RB0_BASE_HI_BASE_IDX 0 +#define regCP_VMID_RESET 0x1e53 +#define regCP_VMID_RESET_BASE_IDX 0 +#define regCPC_INT_CNTL 0x1e54 +#define regCPC_INT_CNTL_BASE_IDX 0 +#define regCPC_INT_STATUS 0x1e55 +#define regCPC_INT_STATUS_BASE_IDX 0 +#define regCP_VMID_PREEMPT 0x1e56 +#define regCP_VMID_PREEMPT_BASE_IDX 0 +#define regCPC_INT_CNTX_ID 0x1e57 +#define regCPC_INT_CNTX_ID_BASE_IDX 0 +#define regCP_PQ_STATUS 0x1e58 +#define regCP_PQ_STATUS_BASE_IDX 0 +#define regCP_PFP_PRGRM_CNTR_START_HI 0x1e59 +#define regCP_PFP_PRGRM_CNTR_START_HI_BASE_IDX 0 +#define regCP_MAX_DRAW_COUNT 0x1e5c +#define regCP_MAX_DRAW_COUNT_BASE_IDX 0 +#define regCP_VMID_STATUS 0x1e5f +#define regCP_VMID_STATUS_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO 0x1e60 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI 0x1e61 +#define regCPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_CONTROL 0x1e62 +#define regCPC_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX 0 +#define regCPC_SUSPEND_CNTL_STACK_OFFSET 0x1e63 +#define regCPC_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCPC_SUSPEND_CNTL_STACK_SIZE 0x1e64 +#define regCPC_SUSPEND_CNTL_STACK_SIZE_BASE_IDX 0 +#define regCPC_SUSPEND_WG_STATE_OFFSET 0x1e65 +#define regCPC_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 +#define regCPC_SUSPEND_CTX_SAVE_SIZE 0x1e66 +#define regCPC_SUSPEND_CTX_SAVE_SIZE_BASE_IDX 0 +#define regCPC_OS_PIPES 0x1e67 +#define regCPC_OS_PIPES_BASE_IDX 0 +#define regCP_SUSPEND_RESUME_REQ 0x1e68 +#define regCP_SUSPEND_RESUME_REQ_BASE_IDX 0 +#define regCP_SUSPEND_CNTL 0x1e69 +#define regCP_SUSPEND_CNTL_BASE_IDX 0 +#define regCP_IQ_WAIT_TIME3 0x1e6a +#define regCP_IQ_WAIT_TIME3_BASE_IDX 0 +#define regCPC_DDID_BASE_ADDR_LO 0x1e6b +#define regCPC_DDID_BASE_ADDR_LO_BASE_IDX 0 +#define regCP_DDID_BASE_ADDR_LO 0x1e6b +#define regCP_DDID_BASE_ADDR_LO_BASE_IDX 0 +#define regCPC_DDID_BASE_ADDR_HI 0x1e6c +#define regCPC_DDID_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_DDID_BASE_ADDR_HI 0x1e6c +#define regCP_DDID_BASE_ADDR_HI_BASE_IDX 0 +#define regCPC_DDID_CNTL 0x1e6d +#define regCPC_DDID_CNTL_BASE_IDX 0 +#define regCP_DDID_CNTL 0x1e6d +#define regCP_DDID_CNTL_BASE_IDX 0 +#define regCP_GFX_DDID_INFLIGHT_COUNT 0x1e6e +#define regCP_GFX_DDID_INFLIGHT_COUNT_BASE_IDX 0 +#define regCP_GFX_DDID_WPTR 0x1e6f +#define regCP_GFX_DDID_WPTR_BASE_IDX 0 +#define regCP_GFX_DDID_RPTR 0x1e70 +#define regCP_GFX_DDID_RPTR_BASE_IDX 0 +#define regCP_GFX_DDID_DELTA_RPT_COUNT 0x1e71 +#define regCP_GFX_DDID_DELTA_RPT_COUNT_BASE_IDX 0 +#define regCP_GFX_HPD_STATUS0 0x1e72 +#define regCP_GFX_HPD_STATUS0_BASE_IDX 0 +#define regCP_GFX_HPD_CONTROL0 0x1e73 +#define regCP_GFX_HPD_CONTROL0_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO 0x1e74 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_LO_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI 0x1e75 +#define regCP_GFX_HPD_OSPRE_FENCE_ADDR_HI_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO 0x1e76 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_LO_BASE_IDX 0 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI 0x1e77 +#define regCP_GFX_HPD_OSPRE_FENCE_DATA_HI_BASE_IDX 0 +#define regCP_GFX_INDEX_MUTEX 0x1e78 +#define regCP_GFX_INDEX_MUTEX_BASE_IDX 0 +#define regCP_ME_PRGRM_CNTR_START_HI 0x1e79 +#define regCP_ME_PRGRM_CNTR_START_HI_BASE_IDX 0 +#define regCP_PFP_INTR_ROUTINE_START_HI 0x1e7a +#define regCP_PFP_INTR_ROUTINE_START_HI_BASE_IDX 0 +#define regCP_ME_INTR_ROUTINE_START_HI 0x1e7b +#define regCP_ME_INTR_ROUTINE_START_HI_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR 0x1e7e +#define regCP_GFX_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_GFX_MQD_BASE_ADDR_HI 0x1e7f +#define regCP_GFX_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_GFX_HQD_ACTIVE 0x1e80 +#define regCP_GFX_HQD_ACTIVE_BASE_IDX 0 +#define regCP_GFX_HQD_VMID 0x1e81 +#define regCP_GFX_HQD_VMID_BASE_IDX 0 +#define regCP_GFX_HQD_QUEUE_PRIORITY 0x1e84 +#define regCP_GFX_HQD_QUEUE_PRIORITY_BASE_IDX 0 +#define regCP_GFX_HQD_QUANTUM 0x1e85 +#define regCP_GFX_HQD_QUANTUM_BASE_IDX 0 +#define regCP_GFX_HQD_BASE 0x1e86 +#define regCP_GFX_HQD_BASE_BASE_IDX 0 +#define regCP_GFX_HQD_BASE_HI 0x1e87 +#define regCP_GFX_HQD_BASE_HI_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR 0x1e88 +#define regCP_GFX_HQD_RPTR_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR_ADDR 0x1e89 +#define regCP_GFX_HQD_RPTR_ADDR_BASE_IDX 0 +#define regCP_GFX_HQD_RPTR_ADDR_HI 0x1e8a +#define regCP_GFX_HQD_RPTR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_LO 0x1e8b +#define regCP_RB_WPTR_POLL_ADDR_LO_BASE_IDX 0 +#define regCP_RB_WPTR_POLL_ADDR_HI 0x1e8c +#define regCP_RB_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regCP_RB_DOORBELL_CONTROL 0x1e8d +#define regCP_RB_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_GFX_HQD_OFFSET 0x1e8e +#define regCP_GFX_HQD_OFFSET_BASE_IDX 0 +#define regCP_GFX_HQD_CNTL 0x1e8f +#define regCP_GFX_HQD_CNTL_BASE_IDX 0 +#define regCP_GFX_HQD_CSMD_RPTR 0x1e90 +#define regCP_GFX_HQD_CSMD_RPTR_BASE_IDX 0 +#define regCP_GFX_HQD_WPTR 0x1e91 +#define regCP_GFX_HQD_WPTR_BASE_IDX 0 +#define regCP_GFX_HQD_WPTR_HI 0x1e92 +#define regCP_GFX_HQD_WPTR_HI_BASE_IDX 0 +#define regCP_GFX_HQD_DEQUEUE_REQUEST 0x1e93 +#define regCP_GFX_HQD_DEQUEUE_REQUEST_BASE_IDX 0 +#define regCP_GFX_HQD_MAPPED 0x1e94 +#define regCP_GFX_HQD_MAPPED_BASE_IDX 0 +#define regCP_GFX_HQD_QUE_MGR_CONTROL 0x1e95 +#define regCP_GFX_HQD_QUE_MGR_CONTROL_BASE_IDX 0 +#define regCP_GFX_HQD_IQ_TIMER 0x1e96 +#define regCP_GFX_HQD_IQ_TIMER_BASE_IDX 0 +#define regCP_GFX_HQD_HQ_STATUS0 0x1e98 +#define regCP_GFX_HQD_HQ_STATUS0_BASE_IDX 0 +#define regCP_GFX_HQD_HQ_CONTROL0 0x1e99 +#define regCP_GFX_HQD_HQ_CONTROL0_BASE_IDX 0 +#define regCP_GFX_MQD_CONTROL 0x1e9a +#define regCP_GFX_MQD_CONTROL_BASE_IDX 0 +#define regCP_HQD_GFX_CONTROL 0x1e9f +#define regCP_HQD_GFX_CONTROL_BASE_IDX 0 +#define regCP_HQD_GFX_STATUS 0x1ea0 +#define regCP_HQD_GFX_STATUS_BASE_IDX 0 +#define regCP_DMA_WATCH0_ADDR_LO 0x1ec0 +#define regCP_DMA_WATCH0_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH0_ADDR_HI 0x1ec1 +#define regCP_DMA_WATCH0_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH0_MASK 0x1ec2 +#define regCP_DMA_WATCH0_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH0_CNTL 0x1ec3 +#define regCP_DMA_WATCH0_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH1_ADDR_LO 0x1ec4 +#define regCP_DMA_WATCH1_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH1_ADDR_HI 0x1ec5 +#define regCP_DMA_WATCH1_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH1_MASK 0x1ec6 +#define regCP_DMA_WATCH1_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH1_CNTL 0x1ec7 +#define regCP_DMA_WATCH1_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH2_ADDR_LO 0x1ec8 +#define regCP_DMA_WATCH2_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH2_ADDR_HI 0x1ec9 +#define regCP_DMA_WATCH2_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH2_MASK 0x1eca +#define regCP_DMA_WATCH2_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH2_CNTL 0x1ecb +#define regCP_DMA_WATCH2_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH3_ADDR_LO 0x1ecc +#define regCP_DMA_WATCH3_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH3_ADDR_HI 0x1ecd +#define regCP_DMA_WATCH3_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH3_MASK 0x1ece +#define regCP_DMA_WATCH3_MASK_BASE_IDX 0 +#define regCP_DMA_WATCH3_CNTL 0x1ecf +#define regCP_DMA_WATCH3_CNTL_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT_ADDR_LO 0x1ed0 +#define regCP_DMA_WATCH_STAT_ADDR_LO_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT_ADDR_HI 0x1ed1 +#define regCP_DMA_WATCH_STAT_ADDR_HI_BASE_IDX 0 +#define regCP_DMA_WATCH_STAT 0x1ed2 +#define regCP_DMA_WATCH_STAT_BASE_IDX 0 +#define regCP_PFP_JT_STAT 0x1ed3 +#define regCP_PFP_JT_STAT_BASE_IDX 0 +#define regCP_MEC_JT_STAT 0x1ed5 +#define regCP_MEC_JT_STAT_BASE_IDX 0 +#define regCP_CPC_BUSY_HYSTERESIS 0x1edb +#define regCP_CPC_BUSY_HYSTERESIS_BASE_IDX 0 +#define regCP_CPF_BUSY_HYSTERESIS1 0x1edc +#define regCP_CPF_BUSY_HYSTERESIS1_BASE_IDX 0 +#define regCP_CPF_BUSY_HYSTERESIS2 0x1edd +#define regCP_CPF_BUSY_HYSTERESIS2_BASE_IDX 0 +#define regCP_CPG_BUSY_HYSTERESIS1 0x1ede +#define regCP_CPG_BUSY_HYSTERESIS1_BASE_IDX 0 +#define regCP_CPG_BUSY_HYSTERESIS2 0x1edf +#define regCP_CPG_BUSY_HYSTERESIS2_BASE_IDX 0 +#define regCPF_FED_ERROR_ADDR_LO 0x1ee0 +#define regCPF_FED_ERROR_ADDR_LO_BASE_IDX 0 +#define regCPF_FED_ERROR_ADDR_HI 0x1ee1 +#define regCPF_FED_ERROR_ADDR_HI_BASE_IDX 0 +#define regCPC_FED_ERROR_ADDR_LO 0x1ee2 +#define regCPC_FED_ERROR_ADDR_LO_BASE_IDX 0 +#define regCPC_FED_ERROR_ADDR_HI 0x1ee3 +#define regCPC_FED_ERROR_ADDR_HI_BASE_IDX 0 +#define regCPG_FED_ERROR_ADDR_LO 0x1ee4 +#define regCPG_FED_ERROR_ADDR_LO_BASE_IDX 0 +#define regCPG_FED_ERROR_ADDR_HI 0x1ee5 +#define regCPG_FED_ERROR_ADDR_HI_BASE_IDX 0 +#define regCP_RB_DOORBELL_CLEAR 0x1f28 +#define regCP_RB_DOORBELL_CLEAR_BASE_IDX 0 +#define regCP_RB0_ACTIVE 0x1f40 +#define regCP_RB0_ACTIVE_BASE_IDX 0 +#define regCP_RB_ACTIVE 0x1f40 +#define regCP_RB_ACTIVE_BASE_IDX 0 +#define regCP_RB_STATUS 0x1f43 +#define regCP_RB_STATUS_BASE_IDX 0 +#define regCPG_RCIU_CAM_INDEX 0x1f44 +#define regCPG_RCIU_CAM_INDEX_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA 0x1f45 +#define regCPG_RCIU_CAM_DATA_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE0 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE0_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE1 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE1_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE2 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE2_BASE_IDX 0 +#define regCPG_RCIU_CAM_DATA_PHASE3 0x1f45 +#define regCPG_RCIU_CAM_DATA_PHASE3_BASE_IDX 0 +#define regCP_GPU_TIMESTAMP_OFFSET_LO 0x1f4c +#define regCP_GPU_TIMESTAMP_OFFSET_LO_BASE_IDX 0 +#define regCP_GPU_TIMESTAMP_OFFSET_HI 0x1f4d +#define regCP_GPU_TIMESTAMP_OFFSET_HI_BASE_IDX 0 +#define regCP_SDMA_DMA_DONE 0x1f4e +#define regCP_SDMA_DMA_DONE_BASE_IDX 0 +#define regCP_PFP_SDMA_CS 0x1f4f +#define regCP_PFP_SDMA_CS_BASE_IDX 0 +#define regCP_ME_SDMA_CS 0x1f50 +#define regCP_ME_SDMA_CS_BASE_IDX 0 +#define regCPF_GCR_CNTL 0x1f53 +#define regCPF_GCR_CNTL_BASE_IDX 0 +#define regCPG_UTCL1_STATUS 0x1f54 +#define regCPG_UTCL1_STATUS_BASE_IDX 0 +#define regCPC_UTCL1_STATUS 0x1f55 +#define regCPC_UTCL1_STATUS_BASE_IDX 0 +#define regCPF_UTCL1_STATUS 0x1f56 +#define regCPF_UTCL1_STATUS_BASE_IDX 0 +#define regCP_SD_CNTL 0x1f57 +#define regCP_SD_CNTL_BASE_IDX 0 +#define regCP_SOFT_RESET_CNTL 0x1f59 +#define regCP_SOFT_RESET_CNTL_BASE_IDX 0 +#define regCP_CPC_GFX_CNTL 0x1f5a +#define regCP_CPC_GFX_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cpphqddec +// base address: 0xc800 +#define regCP_HPD_UTCL1_CNTL 0x1fa3 +#define regCP_HPD_UTCL1_CNTL_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR 0x1fa7 +#define regCP_HPD_UTCL1_ERROR_BASE_IDX 0 +#define regCP_HPD_UTCL1_ERROR_ADDR 0x1fa8 +#define regCP_HPD_UTCL1_ERROR_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR 0x1fa9 +#define regCP_MQD_BASE_ADDR_BASE_IDX 0 +#define regCP_MQD_BASE_ADDR_HI 0x1faa +#define regCP_MQD_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_ACTIVE 0x1fab +#define regCP_HQD_ACTIVE_BASE_IDX 0 +#define regCP_HQD_VMID 0x1fac +#define regCP_HQD_VMID_BASE_IDX 0 +#define regCP_HQD_PERSISTENT_STATE 0x1fad +#define regCP_HQD_PERSISTENT_STATE_BASE_IDX 0 +#define regCP_HQD_PIPE_PRIORITY 0x1fae +#define regCP_HQD_PIPE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUEUE_PRIORITY 0x1faf +#define regCP_HQD_QUEUE_PRIORITY_BASE_IDX 0 +#define regCP_HQD_QUANTUM 0x1fb0 +#define regCP_HQD_QUANTUM_BASE_IDX 0 +#define regCP_HQD_PQ_BASE 0x1fb1 +#define regCP_HQD_PQ_BASE_BASE_IDX 0 +#define regCP_HQD_PQ_BASE_HI 0x1fb2 +#define regCP_HQD_PQ_BASE_HI_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR 0x1fb3 +#define regCP_HQD_PQ_RPTR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR 0x1fb4 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x1fb5 +#define regCP_HQD_PQ_RPTR_REPORT_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR 0x1fb6 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x1fb7 +#define regCP_HQD_PQ_WPTR_POLL_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_PQ_DOORBELL_CONTROL 0x1fb8 +#define regCP_HQD_PQ_DOORBELL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_CONTROL 0x1fba +#define regCP_HQD_PQ_CONTROL_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR 0x1fbb +#define regCP_HQD_IB_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_IB_BASE_ADDR_HI 0x1fbc +#define regCP_HQD_IB_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_IB_RPTR 0x1fbd +#define regCP_HQD_IB_RPTR_BASE_IDX 0 +#define regCP_HQD_IB_CONTROL 0x1fbe +#define regCP_HQD_IB_CONTROL_BASE_IDX 0 +#define regCP_HQD_IQ_TIMER 0x1fbf +#define regCP_HQD_IQ_TIMER_BASE_IDX 0 +#define regCP_HQD_IQ_RPTR 0x1fc0 +#define regCP_HQD_IQ_RPTR_BASE_IDX 0 +#define regCP_HQD_DEQUEUE_REQUEST 0x1fc1 +#define regCP_HQD_DEQUEUE_REQUEST_BASE_IDX 0 +#define regCP_HQD_DMA_OFFLOAD 0x1fc2 +#define regCP_HQD_DMA_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_OFFLOAD 0x1fc2 +#define regCP_HQD_OFFLOAD_BASE_IDX 0 +#define regCP_HQD_MSG_TYPE 0x1fc4 +#define regCP_HQD_MSG_TYPE_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_LO 0x1fc5 +#define regCP_HQD_ATOMIC0_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC0_PREOP_HI 0x1fc6 +#define regCP_HQD_ATOMIC0_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_LO 0x1fc7 +#define regCP_HQD_ATOMIC1_PREOP_LO_BASE_IDX 0 +#define regCP_HQD_ATOMIC1_PREOP_HI 0x1fc8 +#define regCP_HQD_ATOMIC1_PREOP_HI_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER0 0x1fc9 +#define regCP_HQD_HQ_SCHEDULER0_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS0 0x1fc9 +#define regCP_HQD_HQ_STATUS0_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL0 0x1fca +#define regCP_HQD_HQ_CONTROL0_BASE_IDX 0 +#define regCP_HQD_HQ_SCHEDULER1 0x1fca +#define regCP_HQD_HQ_SCHEDULER1_BASE_IDX 0 +#define regCP_MQD_CONTROL 0x1fcb +#define regCP_MQD_CONTROL_BASE_IDX 0 +#define regCP_HQD_HQ_STATUS1 0x1fcc +#define regCP_HQD_HQ_STATUS1_BASE_IDX 0 +#define regCP_HQD_HQ_CONTROL1 0x1fcd +#define regCP_HQD_HQ_CONTROL1_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR 0x1fce +#define regCP_HQD_EOP_BASE_ADDR_BASE_IDX 0 +#define regCP_HQD_EOP_BASE_ADDR_HI 0x1fcf +#define regCP_HQD_EOP_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_EOP_CONTROL 0x1fd0 +#define regCP_HQD_EOP_CONTROL_BASE_IDX 0 +#define regCP_HQD_EOP_RPTR 0x1fd1 +#define regCP_HQD_EOP_RPTR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR 0x1fd2 +#define regCP_HQD_EOP_WPTR_BASE_IDX 0 +#define regCP_HQD_EOP_EVENTS 0x1fd3 +#define regCP_HQD_EOP_EVENTS_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x1fd4 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x1fd5 +#define regCP_HQD_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_CONTROL 0x1fd6 +#define regCP_HQD_CTX_SAVE_CONTROL_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_OFFSET 0x1fd7 +#define regCP_HQD_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCP_HQD_CNTL_STACK_SIZE 0x1fd8 +#define regCP_HQD_CNTL_STACK_SIZE_BASE_IDX 0 +#define regCP_HQD_WG_STATE_OFFSET 0x1fd9 +#define regCP_HQD_WG_STATE_OFFSET_BASE_IDX 0 +#define regCP_HQD_CTX_SAVE_SIZE 0x1fda +#define regCP_HQD_CTX_SAVE_SIZE_BASE_IDX 0 +#define regCP_HQD_GDS_RESOURCE_STATE 0x1fdb +#define regCP_HQD_GDS_RESOURCE_STATE_BASE_IDX 0 +#define regCP_HQD_ERROR 0x1fdc +#define regCP_HQD_ERROR_BASE_IDX 0 +#define regCP_HQD_EOP_WPTR_MEM 0x1fdd +#define regCP_HQD_EOP_WPTR_MEM_BASE_IDX 0 +#define regCP_HQD_AQL_CONTROL 0x1fde +#define regCP_HQD_AQL_CONTROL_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_LO 0x1fdf +#define regCP_HQD_PQ_WPTR_LO_BASE_IDX 0 +#define regCP_HQD_PQ_WPTR_HI 0x1fe0 +#define regCP_HQD_PQ_WPTR_HI_BASE_IDX 0 +#define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET 0x1fe1 +#define regCP_HQD_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 0 +#define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT 0x1fe2 +#define regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT_BASE_IDX 0 +#define regCP_HQD_SUSPEND_WG_STATE_OFFSET 0x1fe3 +#define regCP_HQD_SUSPEND_WG_STATE_OFFSET_BASE_IDX 0 +#define regCP_HQD_DDID_RPTR 0x1fe4 +#define regCP_HQD_DDID_RPTR_BASE_IDX 0 +#define regCP_HQD_DDID_WPTR 0x1fe5 +#define regCP_HQD_DDID_WPTR_BASE_IDX 0 +#define regCP_HQD_DDID_INFLIGHT_COUNT 0x1fe6 +#define regCP_HQD_DDID_INFLIGHT_COUNT_BASE_IDX 0 +#define regCP_HQD_DDID_DELTA_RPT_COUNT 0x1fe7 +#define regCP_HQD_DDID_DELTA_RPT_COUNT_BASE_IDX 0 +#define regCP_HQD_DEQUEUE_STATUS 0x1fe8 +#define regCP_HQD_DEQUEUE_STATUS_BASE_IDX 0 +#define regCP_HQD_AQL_CONTROL_1 0x1fe9 +#define regCP_HQD_AQL_CONTROL_1_BASE_IDX 0 +#define regCP_HQD_AQL_DISPATCH_ID 0x1fea +#define regCP_HQD_AQL_DISPATCH_ID_BASE_IDX 0 +#define regCP_HQD_AQL_DISPATCH_ID_HI 0x1feb +#define regCP_HQD_AQL_DISPATCH_ID_HI_BASE_IDX 0 +#define regCP_HQD_KD_BASE 0x1fec +#define regCP_HQD_KD_BASE_BASE_IDX 0 +#define regCP_HQD_KD_BASE_HI 0x1fed +#define regCP_HQD_KD_BASE_HI_BASE_IDX 0 +#define regCP_HQD_KD_CNTL 0x1fee +#define regCP_HQD_KD_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gfxdec0 +// base address: 0x28000 +#define regCOHER_DEST_BASE_HI_0 0x007a +#define regCOHER_DEST_BASE_HI_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_1 0x007b +#define regCOHER_DEST_BASE_HI_1_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_2 0x007c +#define regCOHER_DEST_BASE_HI_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_HI_3 0x007d +#define regCOHER_DEST_BASE_HI_3_BASE_IDX 1 +#define regCOHER_DEST_BASE_2 0x007e +#define regCOHER_DEST_BASE_2_BASE_IDX 1 +#define regCOHER_DEST_BASE_3 0x007f +#define regCOHER_DEST_BASE_3_BASE_IDX 1 +#define regCOHER_DEST_BASE_0 0x0092 +#define regCOHER_DEST_BASE_0_BASE_IDX 1 +#define regCOHER_DEST_BASE_1 0x0093 +#define regCOHER_DEST_BASE_1_BASE_IDX 1 +#define regCP_PERFMON_CNTX_CNTL 0x00d8 +#define regCP_PERFMON_CNTX_CNTL_BASE_IDX 1 +#define regCP_PIPEID 0x00d9 +#define regCP_PIPEID_BASE_IDX 1 +#define regCP_RINGID 0x00d9 +#define regCP_RINGID_BASE_IDX 1 +#define regCP_VMID 0x00da +#define regCP_VMID_BASE_IDX 1 +#define regCONTEXT_RESERVED_REG0 0x00db +#define regCONTEXT_RESERVED_REG0_BASE_IDX 1 +#define regCONTEXT_RESERVED_REG1 0x00dc +#define regCONTEXT_RESERVED_REG1_BASE_IDX 1 +#define regVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 +#define regVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 +#define regGFX_COPY_STATE 0x01f4 +#define regGFX_COPY_STATE_BASE_IDX 1 +#define regVGT_DMA_BASE_HI 0x01f9 +#define regVGT_DMA_BASE_HI_BASE_IDX 1 +#define regVGT_DMA_BASE 0x01fa +#define regVGT_DMA_BASE_BASE_IDX 1 +#define regVGT_DRAW_INITIATOR 0x01fc +#define regVGT_DRAW_INITIATOR_BASE_IDX 1 +#define regVGT_EVENT_ADDRESS_REG 0x01fe +#define regVGT_EVENT_ADDRESS_REG_BASE_IDX 1 +#define regVGT_HOS_MAX_TESS_LEVEL 0x0286 +#define regVGT_HOS_MAX_TESS_LEVEL_BASE_IDX 1 +#define regVGT_HOS_MIN_TESS_LEVEL 0x0287 +#define regVGT_HOS_MIN_TESS_LEVEL_BASE_IDX 1 +#define regGE_IA_ENHANCE 0x029c +#define regGE_IA_ENHANCE_BASE_IDX 1 +#define regVGT_DMA_SIZE 0x029d +#define regVGT_DMA_SIZE_BASE_IDX 1 +#define regVGT_DMA_MAX_SIZE 0x029e +#define regVGT_DMA_MAX_SIZE_BASE_IDX 1 +#define regVGT_DMA_INDEX_TYPE 0x029f +#define regVGT_DMA_INDEX_TYPE_BASE_IDX 1 +#define regGE_WD_ENHANCE 0x02a0 +#define regGE_WD_ENHANCE_BASE_IDX 1 +#define regVGT_DMA_NUM_INSTANCES 0x02a2 +#define regVGT_DMA_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_EVENT_INITIATOR 0x02a4 +#define regVGT_EVENT_INITIATOR_BASE_IDX 1 +#define regVGT_SHADER_STAGES_EN 0x02a6 +#define regVGT_SHADER_STAGES_EN_BASE_IDX 1 +#define regVGT_TF_PARAM 0x02a9 +#define regVGT_TF_PARAM_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0x02ca +#define regVGT_STRMOUT_DRAW_OPAQUE_OFFSET_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0x02cb +#define regVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE_BASE_IDX 1 +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0x02cc +#define regVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE_BASE_IDX 1 +#define regVGT_TESS_DISTRIBUTION 0x02d4 +#define regVGT_TESS_DISTRIBUTION_BASE_IDX 1 +#define regVGT_LS_HS_CONFIG 0x02d6 +#define regVGT_LS_HS_CONFIG_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvf_cpdec +// base address: 0x2a000 +#define regCONFIG_RESERVED_REG0 0x0800 +#define regCONFIG_RESERVED_REG0_BASE_IDX 1 +#define regCONFIG_RESERVED_REG1 0x0801 +#define regCONFIG_RESERVED_REG1_BASE_IDX 1 +#define regCP_MEC_CNTL 0x0802 +#define regCP_MEC_CNTL_BASE_IDX 1 +#define regCP_ME_CNTL 0x0803 +#define regCP_ME_CNTL_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE0 0x0840 +#define regCP_UNMAPPED_QUEUE0_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE1 0x0841 +#define regCP_UNMAPPED_QUEUE1_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE2 0x0842 +#define regCP_UNMAPPED_QUEUE2_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE3 0x0843 +#define regCP_UNMAPPED_QUEUE3_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE4 0x0844 +#define regCP_UNMAPPED_QUEUE4_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE5 0x0845 +#define regCP_UNMAPPED_QUEUE5_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE6 0x0846 +#define regCP_UNMAPPED_QUEUE6_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE7 0x0847 +#define regCP_UNMAPPED_QUEUE7_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE8 0x0848 +#define regCP_UNMAPPED_QUEUE8_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE9 0x0849 +#define regCP_UNMAPPED_QUEUE9_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE10 0x084a +#define regCP_UNMAPPED_QUEUE10_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE11 0x084b +#define regCP_UNMAPPED_QUEUE11_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE12 0x084c +#define regCP_UNMAPPED_QUEUE12_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE13 0x084d +#define regCP_UNMAPPED_QUEUE13_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE14 0x084e +#define regCP_UNMAPPED_QUEUE14_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE15 0x084f +#define regCP_UNMAPPED_QUEUE15_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE16 0x0850 +#define regCP_UNMAPPED_QUEUE16_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE17 0x0851 +#define regCP_UNMAPPED_QUEUE17_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE18 0x0852 +#define regCP_UNMAPPED_QUEUE18_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE19 0x0853 +#define regCP_UNMAPPED_QUEUE19_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE20 0x0854 +#define regCP_UNMAPPED_QUEUE20_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE21 0x0855 +#define regCP_UNMAPPED_QUEUE21_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE22 0x0856 +#define regCP_UNMAPPED_QUEUE22_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE23 0x0857 +#define regCP_UNMAPPED_QUEUE23_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE24 0x0858 +#define regCP_UNMAPPED_QUEUE24_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE25 0x0859 +#define regCP_UNMAPPED_QUEUE25_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE26 0x085a +#define regCP_UNMAPPED_QUEUE26_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE27 0x085b +#define regCP_UNMAPPED_QUEUE27_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE28 0x085c +#define regCP_UNMAPPED_QUEUE28_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE29 0x085d +#define regCP_UNMAPPED_QUEUE29_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE30 0x085e +#define regCP_UNMAPPED_QUEUE30_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE31 0x085f +#define regCP_UNMAPPED_QUEUE31_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE32 0x0860 +#define regCP_UNMAPPED_QUEUE32_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE33 0x0861 +#define regCP_UNMAPPED_QUEUE33_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE34 0x0862 +#define regCP_UNMAPPED_QUEUE34_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE35 0x0863 +#define regCP_UNMAPPED_QUEUE35_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE36 0x0864 +#define regCP_UNMAPPED_QUEUE36_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE37 0x0865 +#define regCP_UNMAPPED_QUEUE37_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE38 0x0866 +#define regCP_UNMAPPED_QUEUE38_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE39 0x0867 +#define regCP_UNMAPPED_QUEUE39_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE40 0x0868 +#define regCP_UNMAPPED_QUEUE40_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE41 0x0869 +#define regCP_UNMAPPED_QUEUE41_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE42 0x086a +#define regCP_UNMAPPED_QUEUE42_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE43 0x086b +#define regCP_UNMAPPED_QUEUE43_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE44 0x086c +#define regCP_UNMAPPED_QUEUE44_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE45 0x086d +#define regCP_UNMAPPED_QUEUE45_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE46 0x086e +#define regCP_UNMAPPED_QUEUE46_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE47 0x086f +#define regCP_UNMAPPED_QUEUE47_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE48 0x0870 +#define regCP_UNMAPPED_QUEUE48_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE49 0x0871 +#define regCP_UNMAPPED_QUEUE49_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE50 0x0872 +#define regCP_UNMAPPED_QUEUE50_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE51 0x0873 +#define regCP_UNMAPPED_QUEUE51_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE52 0x0874 +#define regCP_UNMAPPED_QUEUE52_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE53 0x0875 +#define regCP_UNMAPPED_QUEUE53_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE54 0x0876 +#define regCP_UNMAPPED_QUEUE54_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE55 0x0877 +#define regCP_UNMAPPED_QUEUE55_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE56 0x0878 +#define regCP_UNMAPPED_QUEUE56_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE57 0x0879 +#define regCP_UNMAPPED_QUEUE57_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE58 0x087a +#define regCP_UNMAPPED_QUEUE58_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE59 0x087b +#define regCP_UNMAPPED_QUEUE59_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE60 0x087c +#define regCP_UNMAPPED_QUEUE60_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE61 0x087d +#define regCP_UNMAPPED_QUEUE61_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE62 0x087e +#define regCP_UNMAPPED_QUEUE62_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE63 0x087f +#define regCP_UNMAPPED_QUEUE63_BASE_IDX 1 +#define regCP_UNMAPPED_DOORBELL 0x0880 +#define regCP_UNMAPPED_DOORBELL_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE_BANK0 0x0881 +#define regCP_UNMAPPED_QUEUE_BANK0_BASE_IDX 1 +#define regCP_UNMAPPED_QUEUE_BANK1 0x0882 +#define regCP_UNMAPPED_QUEUE_BANK1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvf_grbmdec +// base address: 0x2a400 +#define regGRBM_GFX_CNTL 0x0900 +#define regGRBM_GFX_CNTL_BASE_IDX 1 +#define regGRBM_NOWHERE 0x0901 +#define regGRBM_NOWHERE_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_cpdec +// base address: 0x2e000 +#define regCP_FETCHER_SOURCE 0x1801 +#define regCP_FETCHER_SOURCE_BASE_IDX 1 +#define regCP_DFY_CNTL 0x1804 +#define regCP_DFY_CNTL_BASE_IDX 1 +#define regCP_DFY_STAT 0x1805 +#define regCP_DFY_STAT_BASE_IDX 1 +#define regCP_DFY_ADDR_HI 0x1806 +#define regCP_DFY_ADDR_HI_BASE_IDX 1 +#define regCP_DFY_ADDR_LO 0x1807 +#define regCP_DFY_ADDR_LO_BASE_IDX 1 +#define regCP_DFY_DATA_0 0x1808 +#define regCP_DFY_DATA_0_BASE_IDX 1 +#define regCP_DFY_DATA_1 0x1809 +#define regCP_DFY_DATA_1_BASE_IDX 1 +#define regCP_DFY_DATA_2 0x180a +#define regCP_DFY_DATA_2_BASE_IDX 1 +#define regCP_DFY_DATA_3 0x180b +#define regCP_DFY_DATA_3_BASE_IDX 1 +#define regCP_DFY_DATA_4 0x180c +#define regCP_DFY_DATA_4_BASE_IDX 1 +#define regCP_DFY_DATA_5 0x180d +#define regCP_DFY_DATA_5_BASE_IDX 1 +#define regCP_DFY_DATA_6 0x180e +#define regCP_DFY_DATA_6_BASE_IDX 1 +#define regCP_DFY_DATA_7 0x180f +#define regCP_DFY_DATA_7_BASE_IDX 1 +#define regCP_DFY_DATA_8 0x1810 +#define regCP_DFY_DATA_8_BASE_IDX 1 +#define regCP_DFY_DATA_9 0x1811 +#define regCP_DFY_DATA_9_BASE_IDX 1 +#define regCP_DFY_DATA_10 0x1812 +#define regCP_DFY_DATA_10_BASE_IDX 1 +#define regCP_DFY_DATA_11 0x1813 +#define regCP_DFY_DATA_11_BASE_IDX 1 +#define regCP_DFY_DATA_12 0x1814 +#define regCP_DFY_DATA_12_BASE_IDX 1 +#define regCP_DFY_DATA_13 0x1815 +#define regCP_DFY_DATA_13_BASE_IDX 1 +#define regCP_DFY_DATA_14 0x1816 +#define regCP_DFY_DATA_14_BASE_IDX 1 +#define regCP_DFY_DATA_15 0x1817 +#define regCP_DFY_DATA_15_BASE_IDX 1 +#define regCP_DFY_CMD 0x1818 +#define regCP_DFY_CMD_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_cpphqddec +// base address: 0x2e080 +#define regCP_HPD_MES_ROQ_OFFSETS 0x1821 +#define regCP_HPD_MES_ROQ_OFFSETS_BASE_IDX 1 +#define regCP_HPD_ROQ_OFFSETS 0x1821 +#define regCP_HPD_ROQ_OFFSETS_BASE_IDX 1 +#define regCP_HPD_STATUS0 0x1822 +#define regCP_HPD_STATUS0_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_gcrdec +// base address: 0x2e640 +#define regGCR_GENERAL_CNTL 0x1990 +#define regGCR_GENERAL_CNTL_BASE_IDX 1 +#define regGCR_TARGET_DISABLE 0x1991 +#define regGCR_TARGET_DISABLE_BASE_IDX 1 +#define regGCR_CMD_STATUS 0x1992 +#define regGCR_CMD_STATUS_BASE_IDX 1 +#define regGCR_SPARE 0x1993 +#define regGCR_SPARE_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gfxudec +// base address: 0x30000 +#define regCP_EOP_DONE_ADDR_LO 0x2000 +#define regCP_EOP_DONE_ADDR_LO_BASE_IDX 1 +#define regCP_EOP_DONE_ADDR_HI 0x2001 +#define regCP_EOP_DONE_ADDR_HI_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_LO 0x2002 +#define regCP_EOP_DONE_DATA_LO_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_HI 0x2003 +#define regCP_EOP_DONE_DATA_HI_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_LO 0x2004 +#define regCP_EOP_LAST_FENCE_LO_BASE_IDX 1 +#define regCP_EOP_LAST_FENCE_HI 0x2005 +#define regCP_EOP_LAST_FENCE_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_LO 0x2018 +#define regCP_PIPE_STATS_ADDR_LO_BASE_IDX 1 +#define regCP_PIPE_STATS_ADDR_HI 0x2019 +#define regCP_PIPE_STATS_ADDR_HI_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_LO 0x201a +#define regCP_VGT_IAVERT_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAVERT_COUNT_HI 0x201b +#define regCP_VGT_IAVERT_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_LO 0x201c +#define regCP_VGT_IAPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_IAPRIM_COUNT_HI 0x201d +#define regCP_VGT_IAPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_LO 0x201e +#define regCP_VGT_GSPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSPRIM_COUNT_HI 0x201f +#define regCP_VGT_GSPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_LO 0x2020 +#define regCP_VGT_VSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_VSINVOC_COUNT_HI 0x2021 +#define regCP_VGT_VSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_LO 0x2022 +#define regCP_VGT_GSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_GSINVOC_COUNT_HI 0x2023 +#define regCP_VGT_GSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_LO 0x2024 +#define regCP_VGT_HSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_HSINVOC_COUNT_HI 0x2025 +#define regCP_VGT_HSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_LO 0x2026 +#define regCP_VGT_DSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_DSINVOC_COUNT_HI 0x2027 +#define regCP_VGT_DSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_LO 0x2028 +#define regCP_PA_CINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CINVOC_COUNT_HI 0x2029 +#define regCP_PA_CINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_LO 0x202a +#define regCP_PA_CPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_PA_CPRIM_COUNT_HI 0x202b +#define regCP_PA_CPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_LO 0x202c +#define regCP_SC_PSINVOC_COUNT0_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT0_HI 0x202d +#define regCP_SC_PSINVOC_COUNT0_HI_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_LO 0x202e +#define regCP_SC_PSINVOC_COUNT1_LO_BASE_IDX 1 +#define regCP_SC_PSINVOC_COUNT1_HI 0x202f +#define regCP_SC_PSINVOC_COUNT1_HI_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_LO 0x2030 +#define regCP_VGT_CSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_CSINVOC_COUNT_HI 0x2031 +#define regCP_VGT_CSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_VGT_ASINVOC_COUNT_LO 0x2032 +#define regCP_VGT_ASINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_VGT_ASINVOC_COUNT_HI 0x2033 +#define regCP_VGT_ASINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_PIPE_STATS_CONTROL 0x203d +#define regCP_PIPE_STATS_CONTROL_BASE_IDX 1 +#define regSCRATCH_REG0 0x2040 +#define regSCRATCH_REG0_BASE_IDX 1 +#define regSCRATCH_REG1 0x2041 +#define regSCRATCH_REG1_BASE_IDX 1 +#define regSCRATCH_REG2 0x2042 +#define regSCRATCH_REG2_BASE_IDX 1 +#define regSCRATCH_REG3 0x2043 +#define regSCRATCH_REG3_BASE_IDX 1 +#define regSCRATCH_REG4 0x2044 +#define regSCRATCH_REG4_BASE_IDX 1 +#define regSCRATCH_REG5 0x2045 +#define regSCRATCH_REG5_BASE_IDX 1 +#define regSCRATCH_REG6 0x2046 +#define regSCRATCH_REG6_BASE_IDX 1 +#define regSCRATCH_REG7 0x2047 +#define regSCRATCH_REG7_BASE_IDX 1 +#define regSCRATCH_REG_ATOMIC 0x2048 +#define regSCRATCH_REG_ATOMIC_BASE_IDX 1 +#define regSCRATCH_REG_CMPSWAP_ATOMIC 0x2048 +#define regSCRATCH_REG_CMPSWAP_ATOMIC_BASE_IDX 1 +#define regCP_APPEND_DDID_CNT 0x204b +#define regCP_APPEND_DDID_CNT_BASE_IDX 1 +#define regCP_APPEND_DATA_HI 0x204c +#define regCP_APPEND_DATA_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_HI 0x204d +#define regCP_APPEND_LAST_CS_FENCE_HI_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_HI 0x204e +#define regCP_APPEND_LAST_PS_FENCE_HI_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_LO 0x2052 +#define regCP_PFP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_PFP_ATOMIC_PREOP_HI 0x2053 +#define regCP_PFP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_APPEND_ADDR_LO 0x2058 +#define regCP_APPEND_ADDR_LO_BASE_IDX 1 +#define regCP_APPEND_ADDR_HI 0x2059 +#define regCP_APPEND_ADDR_HI_BASE_IDX 1 +#define regCP_APPEND_DATA 0x205a +#define regCP_APPEND_DATA_BASE_IDX 1 +#define regCP_APPEND_DATA_LO 0x205a +#define regCP_APPEND_DATA_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE 0x205b +#define regCP_APPEND_LAST_CS_FENCE_BASE_IDX 1 +#define regCP_APPEND_LAST_CS_FENCE_LO 0x205b +#define regCP_APPEND_LAST_CS_FENCE_LO_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE 0x205c +#define regCP_APPEND_LAST_PS_FENCE_BASE_IDX 1 +#define regCP_APPEND_LAST_PS_FENCE_LO 0x205c +#define regCP_APPEND_LAST_PS_FENCE_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_LO 0x205d +#define regCP_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_LO 0x205d +#define regCP_ME_ATOMIC_PREOP_LO_BASE_IDX 1 +#define regCP_ATOMIC_PREOP_HI 0x205e +#define regCP_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_ME_ATOMIC_PREOP_HI 0x205e +#define regCP_ME_ATOMIC_PREOP_HI_BASE_IDX 1 +#define regCP_ME_MC_WADDR_LO 0x2069 +#define regCP_ME_MC_WADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_WADDR_HI 0x206a +#define regCP_ME_MC_WADDR_HI_BASE_IDX 1 +#define regCP_ME_MC_WDATA_LO 0x206b +#define regCP_ME_MC_WDATA_LO_BASE_IDX 1 +#define regCP_ME_MC_WDATA_HI 0x206c +#define regCP_ME_MC_WDATA_HI_BASE_IDX 1 +#define regCP_ME_MC_RADDR_LO 0x206d +#define regCP_ME_MC_RADDR_LO_BASE_IDX 1 +#define regCP_ME_MC_RADDR_HI 0x206e +#define regCP_ME_MC_RADDR_HI_BASE_IDX 1 +#define regCP_WAIT_REG_MEM_TIMEOUT 0x2074 +#define regCP_WAIT_REG_MEM_TIMEOUT_BASE_IDX 1 +#define regCP_DMA_PFP_CONTROL 0x2077 +#define regCP_DMA_PFP_CONTROL_BASE_IDX 1 +#define regCP_DMA_ME_CONTROL 0x2078 +#define regCP_DMA_ME_CONTROL_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR 0x2080 +#define regCP_DMA_ME_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_SRC_ADDR_HI 0x2081 +#define regCP_DMA_ME_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR 0x2082 +#define regCP_DMA_ME_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_ME_DST_ADDR_HI 0x2083 +#define regCP_DMA_ME_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_ME_COMMAND 0x2084 +#define regCP_DMA_ME_COMMAND_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR 0x2085 +#define regCP_DMA_PFP_SRC_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_SRC_ADDR_HI 0x2086 +#define regCP_DMA_PFP_SRC_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR 0x2087 +#define regCP_DMA_PFP_DST_ADDR_BASE_IDX 1 +#define regCP_DMA_PFP_DST_ADDR_HI 0x2088 +#define regCP_DMA_PFP_DST_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_COMMAND 0x2089 +#define regCP_DMA_PFP_COMMAND_BASE_IDX 1 +#define regCP_DMA_CNTL 0x208a +#define regCP_DMA_CNTL_BASE_IDX 1 +#define regCP_DMA_READ_TAGS 0x208b +#define regCP_DMA_READ_TAGS_BASE_IDX 1 +#define regCP_PFP_IB_CONTROL 0x208d +#define regCP_PFP_IB_CONTROL_BASE_IDX 1 +#define regCP_PFP_LOAD_CONTROL 0x208e +#define regCP_PFP_LOAD_CONTROL_BASE_IDX 1 +#define regCP_SCRATCH_INDEX 0x208f +#define regCP_SCRATCH_INDEX_BASE_IDX 1 +#define regCP_SCRATCH_DATA 0x2090 +#define regCP_SCRATCH_DATA_BASE_IDX 1 +#define regCP_RB_OFFSET 0x2091 +#define regCP_RB_OFFSET_BASE_IDX 1 +#define regCP_IB1_OFFSET 0x2092 +#define regCP_IB1_OFFSET_BASE_IDX 1 +#define regCP_IB2_OFFSET 0x2093 +#define regCP_IB2_OFFSET_BASE_IDX 1 +#define regCP_IB1_PREAMBLE_BEGIN 0x2094 +#define regCP_IB1_PREAMBLE_BEGIN_BASE_IDX 1 +#define regCP_IB1_PREAMBLE_END 0x2095 +#define regCP_IB1_PREAMBLE_END_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_BEGIN 0x2096 +#define regCP_IB2_PREAMBLE_BEGIN_BASE_IDX 1 +#define regCP_IB2_PREAMBLE_END 0x2097 +#define regCP_IB2_PREAMBLE_END_BASE_IDX 1 +#define regCP_DMA_ME_CMD_ADDR_LO 0x209c +#define regCP_DMA_ME_CMD_ADDR_LO_BASE_IDX 1 +#define regCP_DMA_ME_CMD_ADDR_HI 0x209d +#define regCP_DMA_ME_CMD_ADDR_HI_BASE_IDX 1 +#define regCP_DMA_PFP_CMD_ADDR_LO 0x209e +#define regCP_DMA_PFP_CMD_ADDR_LO_BASE_IDX 1 +#define regCP_DMA_PFP_CMD_ADDR_HI 0x209f +#define regCP_DMA_PFP_CMD_ADDR_HI_BASE_IDX 1 +#define regUCONFIG_RESERVED_REG0 0x20a2 +#define regUCONFIG_RESERVED_REG0_BASE_IDX 1 +#define regUCONFIG_RESERVED_REG1 0x20a3 +#define regUCONFIG_RESERVED_REG1_BASE_IDX 1 +#define regCP_PA_MSPRIM_COUNT_LO 0x20a4 +#define regCP_PA_MSPRIM_COUNT_LO_BASE_IDX 1 +#define regCP_PA_MSPRIM_COUNT_HI 0x20a5 +#define regCP_PA_MSPRIM_COUNT_HI_BASE_IDX 1 +#define regCP_GE_MSINVOC_COUNT_LO 0x20a6 +#define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX 1 +#define regCP_GE_MSINVOC_COUNT_HI 0x20a7 +#define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX 1 +#define regCP_IB1_CMD_BUFSZ 0x20c0 +#define regCP_IB1_CMD_BUFSZ_BASE_IDX 1 +#define regCP_IB2_CMD_BUFSZ 0x20c1 +#define regCP_IB2_CMD_BUFSZ_BASE_IDX 1 +#define regCP_ST_CMD_BUFSZ 0x20c2 +#define regCP_ST_CMD_BUFSZ_BASE_IDX 1 +#define regCP_IB1_BASE_LO 0x20cc +#define regCP_IB1_BASE_LO_BASE_IDX 1 +#define regCP_IB1_BASE_HI 0x20cd +#define regCP_IB1_BASE_HI_BASE_IDX 1 +#define regCP_IB1_BUFSZ 0x20ce +#define regCP_IB1_BUFSZ_BASE_IDX 1 +#define regCP_IB2_BASE_LO 0x20cf +#define regCP_IB2_BASE_LO_BASE_IDX 1 +#define regCP_IB2_BASE_HI 0x20d0 +#define regCP_IB2_BASE_HI_BASE_IDX 1 +#define regCP_IB2_BUFSZ 0x20d1 +#define regCP_IB2_BUFSZ_BASE_IDX 1 +#define regCP_ST_BASE_LO 0x20d2 +#define regCP_ST_BASE_LO_BASE_IDX 1 +#define regCP_ST_BASE_HI 0x20d3 +#define regCP_ST_BASE_HI_BASE_IDX 1 +#define regCP_ST_BUFSZ 0x20d4 +#define regCP_ST_BUFSZ_BASE_IDX 1 +#define regCP_EOP_DONE_EVENT_CNTL 0x20d5 +#define regCP_EOP_DONE_EVENT_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_DATA_CNTL 0x20d6 +#define regCP_EOP_DONE_DATA_CNTL_BASE_IDX 1 +#define regCP_EOP_DONE_CNTX_ID 0x20d7 +#define regCP_EOP_DONE_CNTX_ID_BASE_IDX 1 +#define regCP_DB_BASE_LO 0x20d8 +#define regCP_DB_BASE_LO_BASE_IDX 1 +#define regCP_DB_BASE_HI 0x20d9 +#define regCP_DB_BASE_HI_BASE_IDX 1 +#define regCP_DB_BUFSZ 0x20da +#define regCP_DB_BUFSZ_BASE_IDX 1 +#define regCP_DB_CMD_BUFSZ 0x20db +#define regCP_DB_CMD_BUFSZ_BASE_IDX 1 +#define regCP_PFP_COMPLETION_STATUS 0x20ec +#define regCP_PFP_COMPLETION_STATUS_BASE_IDX 1 +#define regCP_PRED_NOT_VISIBLE 0x20ee +#define regCP_PRED_NOT_VISIBLE_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR 0x20f0 +#define regCP_PFP_METADATA_BASE_ADDR_BASE_IDX 1 +#define regCP_PFP_METADATA_BASE_ADDR_HI 0x20f1 +#define regCP_PFP_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR 0x20f4 +#define regCP_DRAW_INDX_INDR_ADDR_BASE_IDX 1 +#define regCP_DRAW_INDX_INDR_ADDR_HI 0x20f5 +#define regCP_DRAW_INDX_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR 0x20f6 +#define regCP_DISPATCH_INDR_ADDR_BASE_IDX 1 +#define regCP_DISPATCH_INDR_ADDR_HI 0x20f7 +#define regCP_DISPATCH_INDR_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR 0x20f8 +#define regCP_INDEX_BASE_ADDR_BASE_IDX 1 +#define regCP_INDEX_BASE_ADDR_HI 0x20f9 +#define regCP_INDEX_BASE_ADDR_HI_BASE_IDX 1 +#define regCP_INDEX_TYPE 0x20fa +#define regCP_INDEX_TYPE_BASE_IDX 1 +#define regCP_SAMPLE_STATUS 0x20fd +#define regCP_SAMPLE_STATUS_BASE_IDX 1 +#define regCP_ME_COHER_CNTL 0x20fe +#define regCP_ME_COHER_CNTL_BASE_IDX 1 +#define regCP_ME_COHER_SIZE 0x20ff +#define regCP_ME_COHER_SIZE_BASE_IDX 1 +#define regCP_ME_COHER_SIZE_HI 0x2100 +#define regCP_ME_COHER_SIZE_HI_BASE_IDX 1 +#define regCP_ME_COHER_BASE 0x2101 +#define regCP_ME_COHER_BASE_BASE_IDX 1 +#define regCP_ME_COHER_BASE_HI 0x2102 +#define regCP_ME_COHER_BASE_HI_BASE_IDX 1 +#define regCP_ME_COHER_STATUS 0x2103 +#define regCP_ME_COHER_STATUS_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_0 0x2140 +#define regRLC_GPM_PERF_COUNT_0_BASE_IDX 1 +#define regRLC_GPM_PERF_COUNT_1 0x2141 +#define regRLC_GPM_PERF_COUNT_1_BASE_IDX 1 +#define regGRBM_GFX_INDEX 0x2200 +#define regGRBM_GFX_INDEX_BASE_IDX 1 +#define regGRBM_NOWHERE_2 0x2201 +#define regGRBM_NOWHERE_2_BASE_IDX 1 +#define regVGT_PRIMITIVE_TYPE 0x2242 +#define regVGT_PRIMITIVE_TYPE_BASE_IDX 1 +#define regVGT_INDEX_TYPE 0x2243 +#define regVGT_INDEX_TYPE_BASE_IDX 1 +#define regGE_MIN_VTX_INDX 0x2249 +#define regGE_MIN_VTX_INDX_BASE_IDX 1 +#define regGE_INDX_OFFSET 0x224a +#define regGE_INDX_OFFSET_BASE_IDX 1 +#define regGE_MULTI_PRIM_IB_RESET_EN 0x224b +#define regGE_MULTI_PRIM_IB_RESET_EN_BASE_IDX 1 +#define regVGT_NUM_INDICES 0x224c +#define regVGT_NUM_INDICES_BASE_IDX 1 +#define regVGT_NUM_INSTANCES 0x224d +#define regVGT_NUM_INSTANCES_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE 0x2250 +#define regVGT_TF_MEMORY_BASE_BASE_IDX 1 +#define regGE_GS_THROTTLE 0x2254 +#define regGE_GS_THROTTLE_BASE_IDX 1 +#define regGE_MAX_VTX_INDX 0x2259 +#define regGE_MAX_VTX_INDX_BASE_IDX 1 +#define regVGT_INSTANCE_BASE_ID 0x225a +#define regVGT_INSTANCE_BASE_ID_BASE_IDX 1 +#define regGE_CNTL 0x225b +#define regGE_CNTL_BASE_IDX 1 +#define regGE_USER_VGPR1 0x225c +#define regGE_USER_VGPR1_BASE_IDX 1 +#define regGE_USER_VGPR2 0x225d +#define regGE_USER_VGPR2_BASE_IDX 1 +#define regGE_USER_VGPR3 0x225e +#define regGE_USER_VGPR3_BASE_IDX 1 +#define regGE_STEREO_CNTL 0x225f +#define regGE_STEREO_CNTL_BASE_IDX 1 +#define regGE_USER_VGPR_EN 0x2260 +#define regGE_USER_VGPR_EN_BASE_IDX 1 +#define regVGT_PRIMITIVEID_EN 0x2262 +#define regVGT_PRIMITIVEID_EN_BASE_IDX 1 +#define regGE_VRS_RATE 0x2263 +#define regGE_VRS_RATE_BASE_IDX 1 +#define regGE_GS_FAST_LAUNCH_WG_DIM 0x2264 +#define regGE_GS_FAST_LAUNCH_WG_DIM_BASE_IDX 1 +#define regGE_GS_FAST_LAUNCH_WG_DIM_1 0x2265 +#define regGE_GS_FAST_LAUNCH_WG_DIM_1_BASE_IDX 1 +#define regVGT_GS_OUT_PRIM_TYPE 0x2266 +#define regVGT_GS_OUT_PRIM_TYPE_BASE_IDX 1 +#define regVGT_TF_MEMORY_BASE_HI 0x2267 +#define regVGT_TF_MEMORY_BASE_HI_BASE_IDX 1 +#define regGE_GS_ORDERED_ID_BASE 0x226c +#define regGE_GS_ORDERED_ID_BASE_BASE_IDX 1 +#define regVGT_PRIMITIVEID_RESET 0x226d +#define regVGT_PRIMITIVEID_RESET_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cprs64dec +// base address: 0x32000 +#define regCP_MES_PRGRM_CNTR_START 0x2800 +#define regCP_MES_PRGRM_CNTR_START_BASE_IDX 1 +#define regCP_MES_INTR_ROUTINE_START 0x2801 +#define regCP_MES_INTR_ROUTINE_START_BASE_IDX 1 +#define regCP_MES_MTVEC_LO 0x2801 +#define regCP_MES_MTVEC_LO_BASE_IDX 1 +#define regCP_MES_INTR_ROUTINE_START_HI 0x2802 +#define regCP_MES_INTR_ROUTINE_START_HI_BASE_IDX 1 +#define regCP_MES_MTVEC_HI 0x2802 +#define regCP_MES_MTVEC_HI_BASE_IDX 1 +#define regCP_MES_CNTL 0x2807 +#define regCP_MES_CNTL_BASE_IDX 1 +#define regCP_MES_PIPE_PRIORITY_CNTS 0x2808 +#define regCP_MES_PIPE_PRIORITY_CNTS_BASE_IDX 1 +#define regCP_MES_PIPE0_PRIORITY 0x2809 +#define regCP_MES_PIPE0_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE1_PRIORITY 0x280a +#define regCP_MES_PIPE1_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE2_PRIORITY 0x280b +#define regCP_MES_PIPE2_PRIORITY_BASE_IDX 1 +#define regCP_MES_PIPE3_PRIORITY 0x280c +#define regCP_MES_PIPE3_PRIORITY_BASE_IDX 1 +#define regCP_MES_HEADER_DUMP 0x280d +#define regCP_MES_HEADER_DUMP_BASE_IDX 1 +#define regCP_MES_MIE_LO 0x280e +#define regCP_MES_MIE_LO_BASE_IDX 1 +#define regCP_MES_MIE_HI 0x280f +#define regCP_MES_MIE_HI_BASE_IDX 1 +#define regCP_MES_INTERRUPT 0x2810 +#define regCP_MES_INTERRUPT_BASE_IDX 1 +#define regCP_MES_SCRATCH_INDEX 0x2811 +#define regCP_MES_SCRATCH_INDEX_BASE_IDX 1 +#define regCP_MES_SCRATCH_DATA 0x2812 +#define regCP_MES_SCRATCH_DATA_BASE_IDX 1 +#define regCP_MES_INSTR_PNTR 0x2813 +#define regCP_MES_INSTR_PNTR_BASE_IDX 1 +#define regCP_MES_MSCRATCH_HI 0x2814 +#define regCP_MES_MSCRATCH_HI_BASE_IDX 1 +#define regCP_MES_MSCRATCH_LO 0x2815 +#define regCP_MES_MSCRATCH_LO_BASE_IDX 1 +#define regCP_MES_MSTATUS_LO 0x2816 +#define regCP_MES_MSTATUS_LO_BASE_IDX 1 +#define regCP_MES_MSTATUS_HI 0x2817 +#define regCP_MES_MSTATUS_HI_BASE_IDX 1 +#define regCP_MES_MEPC_LO 0x2818 +#define regCP_MES_MEPC_LO_BASE_IDX 1 +#define regCP_MES_MEPC_HI 0x2819 +#define regCP_MES_MEPC_HI_BASE_IDX 1 +#define regCP_MES_MCAUSE_LO 0x281a +#define regCP_MES_MCAUSE_LO_BASE_IDX 1 +#define regCP_MES_MCAUSE_HI 0x281b +#define regCP_MES_MCAUSE_HI_BASE_IDX 1 +#define regCP_MES_MBADADDR_LO 0x281c +#define regCP_MES_MBADADDR_LO_BASE_IDX 1 +#define regCP_MES_MBADADDR_HI 0x281d +#define regCP_MES_MBADADDR_HI_BASE_IDX 1 +#define regCP_MES_MIP_LO 0x281e +#define regCP_MES_MIP_LO_BASE_IDX 1 +#define regCP_MES_MIP_HI 0x281f +#define regCP_MES_MIP_HI_BASE_IDX 1 +#define regCP_MES_IC_OP_CNTL 0x2820 +#define regCP_MES_IC_OP_CNTL_BASE_IDX 1 +#define regCP_MES_MCYCLE_LO 0x2826 +#define regCP_MES_MCYCLE_LO_BASE_IDX 1 +#define regCP_MES_MCYCLE_HI 0x2827 +#define regCP_MES_MCYCLE_HI_BASE_IDX 1 +#define regCP_MES_MTIME_LO 0x2828 +#define regCP_MES_MTIME_LO_BASE_IDX 1 +#define regCP_MES_MTIME_HI 0x2829 +#define regCP_MES_MTIME_HI_BASE_IDX 1 +#define regCP_MES_MINSTRET_LO 0x282a +#define regCP_MES_MINSTRET_LO_BASE_IDX 1 +#define regCP_MES_MINSTRET_HI 0x282b +#define regCP_MES_MINSTRET_HI_BASE_IDX 1 +#define regCP_MES_MISA_LO 0x282c +#define regCP_MES_MISA_LO_BASE_IDX 1 +#define regCP_MES_MISA_HI 0x282d +#define regCP_MES_MISA_HI_BASE_IDX 1 +#define regCP_MES_MVENDORID_LO 0x282e +#define regCP_MES_MVENDORID_LO_BASE_IDX 1 +#define regCP_MES_MVENDORID_HI 0x282f +#define regCP_MES_MVENDORID_HI_BASE_IDX 1 +#define regCP_MES_MARCHID_LO 0x2830 +#define regCP_MES_MARCHID_LO_BASE_IDX 1 +#define regCP_MES_MARCHID_HI 0x2831 +#define regCP_MES_MARCHID_HI_BASE_IDX 1 +#define regCP_MES_MIMPID_LO 0x2832 +#define regCP_MES_MIMPID_LO_BASE_IDX 1 +#define regCP_MES_MIMPID_HI 0x2833 +#define regCP_MES_MIMPID_HI_BASE_IDX 1 +#define regCP_MES_MHARTID_LO 0x2834 +#define regCP_MES_MHARTID_LO_BASE_IDX 1 +#define regCP_MES_MHARTID_HI 0x2835 +#define regCP_MES_MHARTID_HI_BASE_IDX 1 +#define regCP_MES_DC_BASE_CNTL 0x2836 +#define regCP_MES_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_DC_OP_CNTL 0x2837 +#define regCP_MES_DC_OP_CNTL_BASE_IDX 1 +#define regCP_MES_MTIMECMP_LO 0x2838 +#define regCP_MES_MTIMECMP_LO_BASE_IDX 1 +#define regCP_MES_MTIMECMP_HI 0x2839 +#define regCP_MES_MTIMECMP_HI_BASE_IDX 1 +#define regCP_MES_PROCESS_QUANTUM_PIPE0 0x283a +#define regCP_MES_PROCESS_QUANTUM_PIPE0_BASE_IDX 1 +#define regCP_MES_PROCESS_QUANTUM_PIPE1 0x283b +#define regCP_MES_PROCESS_QUANTUM_PIPE1_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL1 0x283c +#define regCP_MES_DOORBELL_CONTROL1_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL2 0x283d +#define regCP_MES_DOORBELL_CONTROL2_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL3 0x283e +#define regCP_MES_DOORBELL_CONTROL3_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL4 0x283f +#define regCP_MES_DOORBELL_CONTROL4_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL5 0x2840 +#define regCP_MES_DOORBELL_CONTROL5_BASE_IDX 1 +#define regCP_MES_DOORBELL_CONTROL6 0x2841 +#define regCP_MES_DOORBELL_CONTROL6_BASE_IDX 1 +#define regCP_MES_GP0_LO 0x2843 +#define regCP_MES_GP0_LO_BASE_IDX 1 +#define regCP_MES_GP0_HI 0x2844 +#define regCP_MES_GP0_HI_BASE_IDX 1 +#define regCP_MES_GP1_LO 0x2845 +#define regCP_MES_GP1_LO_BASE_IDX 1 +#define regCP_MES_GP1_HI 0x2846 +#define regCP_MES_GP1_HI_BASE_IDX 1 +#define regCP_MES_GP2_LO 0x2847 +#define regCP_MES_GP2_LO_BASE_IDX 1 +#define regCP_MES_GP2_HI 0x2848 +#define regCP_MES_GP2_HI_BASE_IDX 1 +#define regCP_MES_GP3_LO 0x2849 +#define regCP_MES_GP3_LO_BASE_IDX 1 +#define regCP_MES_GP3_HI 0x284a +#define regCP_MES_GP3_HI_BASE_IDX 1 +#define regCP_MES_GP4_LO 0x284b +#define regCP_MES_GP4_LO_BASE_IDX 1 +#define regCP_MES_GP4_HI 0x284c +#define regCP_MES_GP4_HI_BASE_IDX 1 +#define regCP_MES_GP5_LO 0x284d +#define regCP_MES_GP5_LO_BASE_IDX 1 +#define regCP_MES_GP5_HI 0x284e +#define regCP_MES_GP5_HI_BASE_IDX 1 +#define regCP_MES_GP6_LO 0x284f +#define regCP_MES_GP6_LO_BASE_IDX 1 +#define regCP_MES_GP6_HI 0x2850 +#define regCP_MES_GP6_HI_BASE_IDX 1 +#define regCP_MES_GP7_LO 0x2851 +#define regCP_MES_GP7_LO_BASE_IDX 1 +#define regCP_MES_GP7_HI 0x2852 +#define regCP_MES_GP7_HI_BASE_IDX 1 +#define regCP_MES_GP8_LO 0x2853 +#define regCP_MES_GP8_LO_BASE_IDX 1 +#define regCP_MES_GP8_HI 0x2854 +#define regCP_MES_GP8_HI_BASE_IDX 1 +#define regCP_MES_GP9_LO 0x2855 +#define regCP_MES_GP9_LO_BASE_IDX 1 +#define regCP_MES_GP9_HI 0x2856 +#define regCP_MES_GP9_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_BASE0_LO 0x2883 +#define regCP_MES_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_BASE0_HI 0x2884 +#define regCP_MES_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_MASK0_LO 0x2885 +#define regCP_MES_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_MASK0_HI 0x2886 +#define regCP_MES_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_APERTURE 0x2887 +#define regCP_MES_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_BASE_LO 0x2888 +#define regCP_MES_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_BASE_HI 0x2889 +#define regCP_MES_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_MASK_LO 0x288a +#define regCP_MES_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_MASK_HI 0x288b +#define regCP_MES_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_MES_LOCAL_INSTR_APERTURE 0x288c +#define regCP_MES_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_APERTURE 0x288d +#define regCP_MES_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_BASE_LO 0x288e +#define regCP_MES_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_MES_LOCAL_SCRATCH_BASE_HI 0x288f +#define regCP_MES_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_MES_PERFCOUNT_CNTL 0x2899 +#define regCP_MES_PERFCOUNT_CNTL_BASE_IDX 1 +#define regCP_MES_PENDING_INTERRUPT 0x289a +#define regCP_MES_PENDING_INTERRUPT_BASE_IDX 1 +#define regCP_MES_RS64_EXCEPTION_STATUS 0x289c +#define regCP_MES_RS64_EXCEPTION_STATUS_BASE_IDX 1 +#define regCP_MES_PRGRM_CNTR_START_HI 0x289d +#define regCP_MES_PRGRM_CNTR_START_HI_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_16 0x289f +#define regCP_MES_INTERRUPT_DATA_16_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_17 0x28a0 +#define regCP_MES_INTERRUPT_DATA_17_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_18 0x28a1 +#define regCP_MES_INTERRUPT_DATA_18_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_19 0x28a2 +#define regCP_MES_INTERRUPT_DATA_19_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_20 0x28a3 +#define regCP_MES_INTERRUPT_DATA_20_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_21 0x28a4 +#define regCP_MES_INTERRUPT_DATA_21_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_22 0x28a5 +#define regCP_MES_INTERRUPT_DATA_22_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_23 0x28a6 +#define regCP_MES_INTERRUPT_DATA_23_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_24 0x28a7 +#define regCP_MES_INTERRUPT_DATA_24_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_25 0x28a8 +#define regCP_MES_INTERRUPT_DATA_25_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_26 0x28a9 +#define regCP_MES_INTERRUPT_DATA_26_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_27 0x28aa +#define regCP_MES_INTERRUPT_DATA_27_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_28 0x28ab +#define regCP_MES_INTERRUPT_DATA_28_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_29 0x28ac +#define regCP_MES_INTERRUPT_DATA_29_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_30 0x28ad +#define regCP_MES_INTERRUPT_DATA_30_BASE_IDX 1 +#define regCP_MES_INTERRUPT_DATA_31 0x28ae +#define regCP_MES_INTERRUPT_DATA_31_BASE_IDX 1 +#define regCP_MES_METADATA_CNTL 0x28df +#define regCP_MES_METADATA_CNTL_BASE_IDX 1 +#define regCP_MEC_RS64_PRGRM_CNTR_START 0x2900 +#define regCP_MEC_RS64_PRGRM_CNTR_START_BASE_IDX 1 +#define regCP_MEC_MTVEC_LO 0x2901 +#define regCP_MEC_MTVEC_LO_BASE_IDX 1 +#define regCP_MEC_MTVEC_HI 0x2902 +#define regCP_MEC_MTVEC_HI_BASE_IDX 1 +#define regCP_MEC_RS64_CNTL 0x2904 +#define regCP_MEC_RS64_CNTL_BASE_IDX 1 +#define regCP_MEC_MIE_LO 0x2905 +#define regCP_MEC_MIE_LO_BASE_IDX 1 +#define regCP_MEC_MIE_HI 0x2906 +#define regCP_MEC_MIE_HI_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT 0x2907 +#define regCP_MEC_RS64_INTERRUPT_BASE_IDX 1 +#define regCP_MEC_RS64_INSTR_PNTR 0x2908 +#define regCP_MEC_RS64_INSTR_PNTR_BASE_IDX 1 +#define regCP_MEC_MIP_LO 0x2909 +#define regCP_MEC_MIP_LO_BASE_IDX 1 +#define regCP_MEC_MIP_HI 0x290a +#define regCP_MEC_MIP_HI_BASE_IDX 1 +#define regCP_MEC_DC_BASE_CNTL 0x290b +#define regCP_MEC_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_MEC_DC_OP_CNTL 0x290c +#define regCP_MEC_DC_OP_CNTL_BASE_IDX 1 +#define regCP_MEC_MTIMECMP_LO 0x290d +#define regCP_MEC_MTIMECMP_LO_BASE_IDX 1 +#define regCP_MEC_MTIMECMP_HI 0x290e +#define regCP_MEC_MTIMECMP_HI_BASE_IDX 1 +#define regCP_MEC_GP0_LO 0x2910 +#define regCP_MEC_GP0_LO_BASE_IDX 1 +#define regCP_MEC_GP0_HI 0x2911 +#define regCP_MEC_GP0_HI_BASE_IDX 1 +#define regCP_MEC_GP1_LO 0x2912 +#define regCP_MEC_GP1_LO_BASE_IDX 1 +#define regCP_MEC_GP1_HI 0x2913 +#define regCP_MEC_GP1_HI_BASE_IDX 1 +#define regCP_MEC_GP2_LO 0x2914 +#define regCP_MEC_GP2_LO_BASE_IDX 1 +#define regCP_MEC_GP2_HI 0x2915 +#define regCP_MEC_GP2_HI_BASE_IDX 1 +#define regCP_MEC_GP3_LO 0x2916 +#define regCP_MEC_GP3_LO_BASE_IDX 1 +#define regCP_MEC_GP3_HI 0x2917 +#define regCP_MEC_GP3_HI_BASE_IDX 1 +#define regCP_MEC_GP4_LO 0x2918 +#define regCP_MEC_GP4_LO_BASE_IDX 1 +#define regCP_MEC_GP4_HI 0x2919 +#define regCP_MEC_GP4_HI_BASE_IDX 1 +#define regCP_MEC_GP5_LO 0x291a +#define regCP_MEC_GP5_LO_BASE_IDX 1 +#define regCP_MEC_GP5_HI 0x291b +#define regCP_MEC_GP5_HI_BASE_IDX 1 +#define regCP_MEC_GP6_LO 0x291c +#define regCP_MEC_GP6_LO_BASE_IDX 1 +#define regCP_MEC_GP6_HI 0x291d +#define regCP_MEC_GP6_HI_BASE_IDX 1 +#define regCP_MEC_GP7_LO 0x291e +#define regCP_MEC_GP7_LO_BASE_IDX 1 +#define regCP_MEC_GP7_HI 0x291f +#define regCP_MEC_GP7_HI_BASE_IDX 1 +#define regCP_MEC_GP8_LO 0x2920 +#define regCP_MEC_GP8_LO_BASE_IDX 1 +#define regCP_MEC_GP8_HI 0x2921 +#define regCP_MEC_GP8_HI_BASE_IDX 1 +#define regCP_MEC_GP9_LO 0x2922 +#define regCP_MEC_GP9_LO_BASE_IDX 1 +#define regCP_MEC_GP9_HI 0x2923 +#define regCP_MEC_GP9_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_BASE0_LO 0x2927 +#define regCP_MEC_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_BASE0_HI 0x2928 +#define regCP_MEC_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_MASK0_LO 0x2929 +#define regCP_MEC_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_MASK0_HI 0x292a +#define regCP_MEC_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_APERTURE 0x292b +#define regCP_MEC_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_BASE_LO 0x292c +#define regCP_MEC_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_BASE_HI 0x292d +#define regCP_MEC_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_MASK_LO 0x292e +#define regCP_MEC_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_MASK_HI 0x292f +#define regCP_MEC_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_MEC_LOCAL_INSTR_APERTURE 0x2930 +#define regCP_MEC_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_APERTURE 0x2931 +#define regCP_MEC_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_BASE_LO 0x2932 +#define regCP_MEC_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_MEC_LOCAL_SCRATCH_BASE_HI 0x2933 +#define regCP_MEC_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_MEC_RS64_PERFCOUNT_CNTL 0x2934 +#define regCP_MEC_RS64_PERFCOUNT_CNTL_BASE_IDX 1 +#define regCP_MEC_RS64_PENDING_INTERRUPT 0x2935 +#define regCP_MEC_RS64_PENDING_INTERRUPT_BASE_IDX 1 +#define regCP_MEC_RS64_EXCEPTION_STATUS 0x2937 +#define regCP_MEC_RS64_EXCEPTION_STATUS_BASE_IDX 1 +#define regCP_MEC_RS64_PRGRM_CNTR_START_HI 0x2938 +#define regCP_MEC_RS64_PRGRM_CNTR_START_HI_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_16 0x293a +#define regCP_MEC_RS64_INTERRUPT_DATA_16_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_17 0x293b +#define regCP_MEC_RS64_INTERRUPT_DATA_17_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_18 0x293c +#define regCP_MEC_RS64_INTERRUPT_DATA_18_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_19 0x293d +#define regCP_MEC_RS64_INTERRUPT_DATA_19_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_20 0x293e +#define regCP_MEC_RS64_INTERRUPT_DATA_20_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_21 0x293f +#define regCP_MEC_RS64_INTERRUPT_DATA_21_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_22 0x2940 +#define regCP_MEC_RS64_INTERRUPT_DATA_22_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_23 0x2941 +#define regCP_MEC_RS64_INTERRUPT_DATA_23_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_24 0x2942 +#define regCP_MEC_RS64_INTERRUPT_DATA_24_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_25 0x2943 +#define regCP_MEC_RS64_INTERRUPT_DATA_25_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_26 0x2944 +#define regCP_MEC_RS64_INTERRUPT_DATA_26_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_27 0x2945 +#define regCP_MEC_RS64_INTERRUPT_DATA_27_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_28 0x2946 +#define regCP_MEC_RS64_INTERRUPT_DATA_28_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_29 0x2947 +#define regCP_MEC_RS64_INTERRUPT_DATA_29_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_30 0x2948 +#define regCP_MEC_RS64_INTERRUPT_DATA_30_BASE_IDX 1 +#define regCP_MEC_RS64_INTERRUPT_DATA_31 0x2949 +#define regCP_MEC_RS64_INTERRUPT_DATA_31_BASE_IDX 1 +#define regCP_CPC_IC_OP_CNTL 0x297a +#define regCP_CPC_IC_OP_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_INTERRUPT0 0x2a01 +#define regCP_GFX_RS64_INTERRUPT0_BASE_IDX 1 +#define regCP_GFX_RS64_INTR_EN0 0x2a02 +#define regCP_GFX_RS64_INTR_EN0_BASE_IDX 1 +#define regCP_GFX_RS64_INTR_EN1 0x2a03 +#define regCP_GFX_RS64_INTR_EN1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE_CNTL 0x2a08 +#define regCP_GFX_RS64_DC_BASE_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_DC_OP_CNTL 0x2a09 +#define regCP_GFX_RS64_DC_OP_CNTL_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_BASE0_LO 0x2a0a +#define regCP_GFX_RS64_LOCAL_BASE0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_BASE0_HI 0x2a0b +#define regCP_GFX_RS64_LOCAL_BASE0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_MASK0_LO 0x2a0c +#define regCP_GFX_RS64_LOCAL_MASK0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_MASK0_HI 0x2a0d +#define regCP_GFX_RS64_LOCAL_MASK0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_APERTURE 0x2a0e +#define regCP_GFX_RS64_LOCAL_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO 0x2a0f +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI 0x2a10 +#define regCP_GFX_RS64_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO 0x2a11 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI 0x2a12 +#define regCP_GFX_RS64_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_INSTR_APERTURE 0x2a13 +#define regCP_GFX_RS64_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE 0x2a14 +#define regCP_GFX_RS64_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO 0x2a15 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI 0x2a16 +#define regCP_GFX_RS64_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regCP_PFP_RS64_EXCEPTION_STATUS 0x2a19 +#define regCP_PFP_RS64_EXCEPTION_STATUS_BASE_IDX 1 +#define regCP_GFX_RS64_PERFCOUNT_CNTL0 0x2a1a +#define regCP_GFX_RS64_PERFCOUNT_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_PERFCOUNT_CNTL1 0x2a1b +#define regCP_GFX_RS64_PERFCOUNT_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_LO0 0x2a1c +#define regCP_GFX_RS64_MIP_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_LO1 0x2a1d +#define regCP_GFX_RS64_MIP_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_HI0 0x2a1e +#define regCP_GFX_RS64_MIP_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_MIP_HI1 0x2a1f +#define regCP_GFX_RS64_MIP_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_LO0 0x2a20 +#define regCP_GFX_RS64_MTIMECMP_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_LO1 0x2a21 +#define regCP_GFX_RS64_MTIMECMP_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_HI0 0x2a22 +#define regCP_GFX_RS64_MTIMECMP_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_MTIMECMP_HI1 0x2a23 +#define regCP_GFX_RS64_MTIMECMP_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_LO0 0x2a24 +#define regCP_GFX_RS64_GP0_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_LO1 0x2a25 +#define regCP_GFX_RS64_GP0_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_HI0 0x2a26 +#define regCP_GFX_RS64_GP0_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP0_HI1 0x2a27 +#define regCP_GFX_RS64_GP0_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_LO0 0x2a28 +#define regCP_GFX_RS64_GP1_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_LO1 0x2a29 +#define regCP_GFX_RS64_GP1_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_HI0 0x2a2a +#define regCP_GFX_RS64_GP1_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP1_HI1 0x2a2b +#define regCP_GFX_RS64_GP1_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_LO0 0x2a2c +#define regCP_GFX_RS64_GP2_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_LO1 0x2a2d +#define regCP_GFX_RS64_GP2_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_HI0 0x2a2e +#define regCP_GFX_RS64_GP2_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP2_HI1 0x2a2f +#define regCP_GFX_RS64_GP2_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_LO0 0x2a30 +#define regCP_GFX_RS64_GP3_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_LO1 0x2a31 +#define regCP_GFX_RS64_GP3_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_HI0 0x2a32 +#define regCP_GFX_RS64_GP3_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP3_HI1 0x2a33 +#define regCP_GFX_RS64_GP3_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_LO0 0x2a34 +#define regCP_GFX_RS64_GP4_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_LO1 0x2a35 +#define regCP_GFX_RS64_GP4_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_HI0 0x2a36 +#define regCP_GFX_RS64_GP4_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP4_HI1 0x2a37 +#define regCP_GFX_RS64_GP4_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_LO0 0x2a38 +#define regCP_GFX_RS64_GP5_LO0_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_LO1 0x2a39 +#define regCP_GFX_RS64_GP5_LO1_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_HI0 0x2a3a +#define regCP_GFX_RS64_GP5_HI0_BASE_IDX 1 +#define regCP_GFX_RS64_GP5_HI1 0x2a3b +#define regCP_GFX_RS64_GP5_HI1_BASE_IDX 1 +#define regCP_GFX_RS64_GP6_LO 0x2a3c +#define regCP_GFX_RS64_GP6_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP6_HI 0x2a3d +#define regCP_GFX_RS64_GP6_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP7_LO 0x2a3e +#define regCP_GFX_RS64_GP7_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP7_HI 0x2a3f +#define regCP_GFX_RS64_GP7_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP8_LO 0x2a40 +#define regCP_GFX_RS64_GP8_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP8_HI 0x2a41 +#define regCP_GFX_RS64_GP8_HI_BASE_IDX 1 +#define regCP_GFX_RS64_GP9_LO 0x2a42 +#define regCP_GFX_RS64_GP9_LO_BASE_IDX 1 +#define regCP_GFX_RS64_GP9_HI 0x2a43 +#define regCP_GFX_RS64_GP9_HI_BASE_IDX 1 +#define regCP_GFX_RS64_INSTR_PNTR0 0x2a44 +#define regCP_GFX_RS64_INSTR_PNTR0_BASE_IDX 1 +#define regCP_GFX_RS64_INSTR_PNTR1 0x2a45 +#define regCP_GFX_RS64_INSTR_PNTR1_BASE_IDX 1 +#define regCP_GFX_RS64_PENDING_INTERRUPT0 0x2a46 +#define regCP_GFX_RS64_PENDING_INTERRUPT0_BASE_IDX 1 +#define regCP_GFX_RS64_PENDING_INTERRUPT1 0x2a47 +#define regCP_GFX_RS64_PENDING_INTERRUPT1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_BASE0 0x2a49 +#define regCP_GFX_RS64_DC_APERTURE0_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_MASK0 0x2a4a +#define regCP_GFX_RS64_DC_APERTURE0_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_CNTL0 0x2a4b +#define regCP_GFX_RS64_DC_APERTURE0_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_BASE0 0x2a4c +#define regCP_GFX_RS64_DC_APERTURE1_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_MASK0 0x2a4d +#define regCP_GFX_RS64_DC_APERTURE1_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_CNTL0 0x2a4e +#define regCP_GFX_RS64_DC_APERTURE1_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_BASE0 0x2a4f +#define regCP_GFX_RS64_DC_APERTURE2_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_MASK0 0x2a50 +#define regCP_GFX_RS64_DC_APERTURE2_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL0 0x2a51 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_BASE0 0x2a52 +#define regCP_GFX_RS64_DC_APERTURE3_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_MASK0 0x2a53 +#define regCP_GFX_RS64_DC_APERTURE3_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL0 0x2a54 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_BASE0 0x2a55 +#define regCP_GFX_RS64_DC_APERTURE4_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_MASK0 0x2a56 +#define regCP_GFX_RS64_DC_APERTURE4_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL0 0x2a57 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_BASE0 0x2a58 +#define regCP_GFX_RS64_DC_APERTURE5_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_MASK0 0x2a59 +#define regCP_GFX_RS64_DC_APERTURE5_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_CNTL0 0x2a5a +#define regCP_GFX_RS64_DC_APERTURE5_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_BASE0 0x2a5b +#define regCP_GFX_RS64_DC_APERTURE6_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_MASK0 0x2a5c +#define regCP_GFX_RS64_DC_APERTURE6_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_CNTL0 0x2a5d +#define regCP_GFX_RS64_DC_APERTURE6_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_BASE0 0x2a5e +#define regCP_GFX_RS64_DC_APERTURE7_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_MASK0 0x2a5f +#define regCP_GFX_RS64_DC_APERTURE7_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL0 0x2a60 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_BASE0 0x2a61 +#define regCP_GFX_RS64_DC_APERTURE8_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_MASK0 0x2a62 +#define regCP_GFX_RS64_DC_APERTURE8_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL0 0x2a63 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_BASE0 0x2a64 +#define regCP_GFX_RS64_DC_APERTURE9_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_MASK0 0x2a65 +#define regCP_GFX_RS64_DC_APERTURE9_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL0 0x2a66 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_BASE0 0x2a67 +#define regCP_GFX_RS64_DC_APERTURE10_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_MASK0 0x2a68 +#define regCP_GFX_RS64_DC_APERTURE10_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL0 0x2a69 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_BASE0 0x2a6a +#define regCP_GFX_RS64_DC_APERTURE11_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_MASK0 0x2a6b +#define regCP_GFX_RS64_DC_APERTURE11_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_CNTL0 0x2a6c +#define regCP_GFX_RS64_DC_APERTURE11_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_BASE0 0x2a6d +#define regCP_GFX_RS64_DC_APERTURE12_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_MASK0 0x2a6e +#define regCP_GFX_RS64_DC_APERTURE12_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_CNTL0 0x2a6f +#define regCP_GFX_RS64_DC_APERTURE12_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_BASE0 0x2a70 +#define regCP_GFX_RS64_DC_APERTURE13_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK0 0x2a71 +#define regCP_GFX_RS64_DC_APERTURE13_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL0 0x2a72 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_BASE0 0x2a73 +#define regCP_GFX_RS64_DC_APERTURE14_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_MASK0 0x2a74 +#define regCP_GFX_RS64_DC_APERTURE14_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL0 0x2a75 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_BASE0 0x2a76 +#define regCP_GFX_RS64_DC_APERTURE15_BASE0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_MASK0 0x2a77 +#define regCP_GFX_RS64_DC_APERTURE15_MASK0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL0 0x2a78 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL0_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_BASE1 0x2a79 +#define regCP_GFX_RS64_DC_APERTURE0_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_MASK1 0x2a7a +#define regCP_GFX_RS64_DC_APERTURE0_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE0_CNTL1 0x2a7b +#define regCP_GFX_RS64_DC_APERTURE0_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_BASE1 0x2a7c +#define regCP_GFX_RS64_DC_APERTURE1_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_MASK1 0x2a7d +#define regCP_GFX_RS64_DC_APERTURE1_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE1_CNTL1 0x2a7e +#define regCP_GFX_RS64_DC_APERTURE1_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_BASE1 0x2a7f +#define regCP_GFX_RS64_DC_APERTURE2_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_MASK1 0x2a80 +#define regCP_GFX_RS64_DC_APERTURE2_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL1 0x2a81 +#define regCP_GFX_RS64_DC_APERTURE2_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_BASE1 0x2a82 +#define regCP_GFX_RS64_DC_APERTURE3_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_MASK1 0x2a83 +#define regCP_GFX_RS64_DC_APERTURE3_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL1 0x2a84 +#define regCP_GFX_RS64_DC_APERTURE3_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_BASE1 0x2a85 +#define regCP_GFX_RS64_DC_APERTURE4_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_MASK1 0x2a86 +#define regCP_GFX_RS64_DC_APERTURE4_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL1 0x2a87 +#define regCP_GFX_RS64_DC_APERTURE4_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_BASE1 0x2a88 +#define regCP_GFX_RS64_DC_APERTURE5_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_MASK1 0x2a89 +#define regCP_GFX_RS64_DC_APERTURE5_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE5_CNTL1 0x2a8a +#define regCP_GFX_RS64_DC_APERTURE5_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_BASE1 0x2a8b +#define regCP_GFX_RS64_DC_APERTURE6_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_MASK1 0x2a8c +#define regCP_GFX_RS64_DC_APERTURE6_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE6_CNTL1 0x2a8d +#define regCP_GFX_RS64_DC_APERTURE6_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_BASE1 0x2a8e +#define regCP_GFX_RS64_DC_APERTURE7_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_MASK1 0x2a8f +#define regCP_GFX_RS64_DC_APERTURE7_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL1 0x2a90 +#define regCP_GFX_RS64_DC_APERTURE7_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_BASE1 0x2a91 +#define regCP_GFX_RS64_DC_APERTURE8_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_MASK1 0x2a92 +#define regCP_GFX_RS64_DC_APERTURE8_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL1 0x2a93 +#define regCP_GFX_RS64_DC_APERTURE8_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_BASE1 0x2a94 +#define regCP_GFX_RS64_DC_APERTURE9_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_MASK1 0x2a95 +#define regCP_GFX_RS64_DC_APERTURE9_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL1 0x2a96 +#define regCP_GFX_RS64_DC_APERTURE9_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_BASE1 0x2a97 +#define regCP_GFX_RS64_DC_APERTURE10_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_MASK1 0x2a98 +#define regCP_GFX_RS64_DC_APERTURE10_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL1 0x2a99 +#define regCP_GFX_RS64_DC_APERTURE10_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_BASE1 0x2a9a +#define regCP_GFX_RS64_DC_APERTURE11_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_MASK1 0x2a9b +#define regCP_GFX_RS64_DC_APERTURE11_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE11_CNTL1 0x2a9c +#define regCP_GFX_RS64_DC_APERTURE11_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_BASE1 0x2a9d +#define regCP_GFX_RS64_DC_APERTURE12_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_MASK1 0x2a9e +#define regCP_GFX_RS64_DC_APERTURE12_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE12_CNTL1 0x2a9f +#define regCP_GFX_RS64_DC_APERTURE12_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_BASE1 0x2aa0 +#define regCP_GFX_RS64_DC_APERTURE13_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK1 0x2aa1 +#define regCP_GFX_RS64_DC_APERTURE13_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL1 0x2aa2 +#define regCP_GFX_RS64_DC_APERTURE13_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_BASE1 0x2aa3 +#define regCP_GFX_RS64_DC_APERTURE14_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_MASK1 0x2aa4 +#define regCP_GFX_RS64_DC_APERTURE14_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL1 0x2aa5 +#define regCP_GFX_RS64_DC_APERTURE14_CNTL1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_BASE1 0x2aa6 +#define regCP_GFX_RS64_DC_APERTURE15_BASE1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_MASK1 0x2aa7 +#define regCP_GFX_RS64_DC_APERTURE15_MASK1_BASE_IDX 1 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL1 0x2aa8 +#define regCP_GFX_RS64_DC_APERTURE15_CNTL1_BASE_IDX 1 +#define regCP_ME_RS64_EXCEPTION_STATUS 0x2aaa +#define regCP_ME_RS64_EXCEPTION_STATUS_BASE_IDX 1 +#define regCP_GFX_RS64_INTERRUPT1 0x2aac +#define regCP_GFX_RS64_INTERRUPT1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_chdec +// base address: 0x33600 +#define regCH_ARB_CTRL 0x2d80 +#define regCH_ARB_CTRL_BASE_IDX 1 +#define regCH_DRAM_BURST_MASK 0x2d82 +#define regCH_DRAM_BURST_MASK_BASE_IDX 1 +#define regCH_ARB_STATUS 0x2d83 +#define regCH_ARB_STATUS_BASE_IDX 1 +#define regCH_DRAM_BURST_CTRL 0x2d84 +#define regCH_DRAM_BURST_CTRL_BASE_IDX 1 +#define regCHA_CHC_CREDITS 0x2d88 +#define regCHA_CHC_CREDITS_BASE_IDX 1 +#define regCHA_CLIENT_FREE_DELAY 0x2d89 +#define regCHA_CLIENT_FREE_DELAY_BASE_IDX 1 +#define regCHI_CHR_REP_FGCG_OVERRIDE 0x2d8c +#define regCHI_CHR_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regCHC_CTRL 0x2dc0 +#define regCHC_CTRL_BASE_IDX 1 +#define regCHC_STATUS 0x2dc1 +#define regCHC_STATUS_BASE_IDX 1 +#define regCHC_STATUS2 0x2dc3 +#define regCHC_STATUS2_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_glarbdec +// base address: 0x33c00 +#define regGLARB_ARB_CTRL 0x2f00 +#define regGLARB_ARB_CTRL_BASE_IDX 1 +#define regGLARB_DRAM_BURST_MASK 0x2f02 +#define regGLARB_DRAM_BURST_MASK_BASE_IDX 1 +#define regGLARB_ARB_STATUS 0x2f03 +#define regGLARB_ARB_STATUS_BASE_IDX 1 +#define regGLARB_DRAM_BURST_CTRL 0x2f04 +#define regGLARB_DRAM_BURST_CTRL_BASE_IDX 1 +#define regGLARBA_GLARBC_CREDITS 0x2f08 +#define regGLARBA_GLARBC_CREDITS_BASE_IDX 1 +#define regGLARBA_CLIENT_FREE_DELAY 0x2f09 +#define regGLARBA_CLIENT_FREE_DELAY_BASE_IDX 1 +#define regGLARBI_GLARBR_REP_FGCG_OVERRIDE 0x2f0c +#define regGLARBI_GLARBR_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regGLARBC_CTRL 0x2f40 +#define regGLARBC_CTRL_BASE_IDX 1 +#define regGLARBC_STATUS 0x2f41 +#define regGLARBC_STATUS_BASE_IDX 1 +#define regGLARBC_CTRL2 0x2f42 +#define regGLARBC_CTRL2_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfddec +// base address: 0x34000 +#define regCPG_PERFCOUNTER1_LO 0x3000 +#define regCPG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER1_HI 0x3001 +#define regCPG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_LO 0x3002 +#define regCPG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_HI 0x3003 +#define regCPG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_LO 0x3004 +#define regCPC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_HI 0x3005 +#define regCPC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_LO 0x3006 +#define regCPC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_HI 0x3007 +#define regCPC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_LO 0x3008 +#define regCPF_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_HI 0x3009 +#define regCPF_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_LO 0x300a +#define regCPF_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_HI 0x300b +#define regCPF_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCPF_LATENCY_STATS_DATA 0x300c +#define regCPF_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPG_LATENCY_STATS_DATA 0x300d +#define regCPG_LATENCY_STATS_DATA_BASE_IDX 1 +#define regCPC_LATENCY_STATS_DATA 0x300e +#define regCPC_LATENCY_STATS_DATA_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_LO 0x3040 +#define regGRBM_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_HI 0x3041 +#define regGRBM_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_LO 0x3043 +#define regGRBM_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_HI 0x3044 +#define regGRBM_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_LO 0x30a4 +#define regGE1_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_HI 0x30a5 +#define regGE1_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_LO 0x30a6 +#define regGE1_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_HI 0x30a7 +#define regGE1_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_LO 0x30a8 +#define regGE1_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_HI 0x30a9 +#define regGE1_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_LO 0x30aa +#define regGE1_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_HI 0x30ab +#define regGE1_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_LO 0x30ac +#define regGE2_DIST_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_HI 0x30ad +#define regGE2_DIST_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_LO 0x30ae +#define regGE2_DIST_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_HI 0x30af +#define regGE2_DIST_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_LO 0x30b0 +#define regGE2_DIST_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_HI 0x30b1 +#define regGE2_DIST_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_LO 0x30b2 +#define regGE2_DIST_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_HI 0x30b3 +#define regGE2_DIST_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER0_LO 0x3270 +#define regGC_EA_CPWD_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER0_HI 0x3271 +#define regGC_EA_CPWD_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER1_LO 0x3272 +#define regGC_EA_CPWD_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER1_HI 0x3273 +#define regGC_EA_CPWD_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_LO 0x33c0 +#define regCHC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_HI 0x33c1 +#define regCHC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_LO 0x33c2 +#define regCHC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_HI 0x33c3 +#define regCHC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_LO 0x33c4 +#define regCHC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_HI 0x33c5 +#define regCHC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_LO 0x33c6 +#define regCHC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_HI 0x33c7 +#define regCHC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER0_LO 0x33e0 +#define regGLARBA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER0_HI 0x33e1 +#define regGLARBA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER1_LO 0x33e2 +#define regGLARBA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER1_HI 0x33e3 +#define regGLARBA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER2_LO 0x33e4 +#define regGLARBA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER2_HI 0x33e5 +#define regGLARBA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER3_LO 0x33e6 +#define regGLARBA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER3_HI 0x33e7 +#define regGLARBA_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER0_LO 0x33f0 +#define regGLARBC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER0_HI 0x33f1 +#define regGLARBC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER1_LO 0x33f2 +#define regGLARBC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER1_HI 0x33f3 +#define regGLARBC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER2_LO 0x33f4 +#define regGLARBC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER2_HI 0x33f5 +#define regGLARBC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER3_LO 0x33f6 +#define regGLARBC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER3_HI 0x33f7 +#define regGLARBC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_LO 0x3480 +#define regRLC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_HI 0x3481 +#define regRLC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_LO 0x3482 +#define regRLC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_HI 0x3483 +#define regRLC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_LO 0x3520 +#define regGCR_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_HI 0x3521 +#define regGCR_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_LO 0x3522 +#define regGCR_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_HI 0x3523 +#define regGCR_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_LO 0x3600 +#define regCHA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_HI 0x3601 +#define regCHA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_LO 0x3602 +#define regCHA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_HI 0x3603 +#define regCHA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_LO 0x3604 +#define regCHA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_HI 0x3605 +#define regCHA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_LO 0x3606 +#define regCHA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_HI 0x3607 +#define regCHA_PERFCOUNTER3_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfsdec +// base address: 0x36000 +#define regCPG_PERFCOUNTER1_SELECT 0x3800 +#define regCPG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT1 0x3801 +#define regCPG_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPG_PERFCOUNTER0_SELECT 0x3802 +#define regCPG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER1_SELECT 0x3803 +#define regCPC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT1 0x3804 +#define regCPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER1_SELECT 0x3805 +#define regCPF_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT1 0x3806 +#define regCPF_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCPF_PERFCOUNTER0_SELECT 0x3807 +#define regCPF_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCP_PERFMON_CNTL 0x3808 +#define regCP_PERFMON_CNTL_BASE_IDX 1 +#define regCPC_PERFCOUNTER0_SELECT 0x3809 +#define regCPC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT 0x380a +#define regCPF_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT 0x380b +#define regCPG_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCPF_LATENCY_STATS_SELECT 0x380c +#define regCPF_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPG_LATENCY_STATS_SELECT 0x380d +#define regCPG_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPC_LATENCY_STATS_SELECT 0x380e +#define regCPC_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regCPC_TC_PERF_COUNTER_WINDOW_SELECT 0x380f +#define regCPC_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT 0x3810 +#define regCP_DRAW_OBJECT_BASE_IDX 1 +#define regCP_DRAW_OBJECT_COUNTER 0x3811 +#define regCP_DRAW_OBJECT_COUNTER_BASE_IDX 1 +#define regCP_DRAW_WINDOW_MASK_HI 0x3812 +#define regCP_DRAW_WINDOW_MASK_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_HI 0x3813 +#define regCP_DRAW_WINDOW_HI_BASE_IDX 1 +#define regCP_DRAW_WINDOW_LO 0x3814 +#define regCP_DRAW_WINDOW_LO_BASE_IDX 1 +#define regCP_DRAW_WINDOW_CNTL 0x3815 +#define regCP_DRAW_WINDOW_CNTL_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_SELECT 0x3840 +#define regGRBM_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_SELECT 0x3841 +#define regGRBM_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGRBM_PERFCOUNTER0_SELECT_HI 0x384d +#define regGRBM_PERFCOUNTER0_SELECT_HI_BASE_IDX 1 +#define regGRBM_PERFCOUNTER1_SELECT_HI 0x384e +#define regGRBM_PERFCOUNTER1_SELECT_HI_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_SELECT 0x38a4 +#define regGE1_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER0_SELECT1 0x38a5 +#define regGE1_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_SELECT 0x38a6 +#define regGE1_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER1_SELECT1 0x38a7 +#define regGE1_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_SELECT 0x38a8 +#define regGE1_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER2_SELECT1 0x38a9 +#define regGE1_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_SELECT 0x38aa +#define regGE1_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE1_PERFCOUNTER3_SELECT1 0x38ab +#define regGE1_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_SELECT 0x38ac +#define regGE2_DIST_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER0_SELECT1 0x38ad +#define regGE2_DIST_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_SELECT 0x38ae +#define regGE2_DIST_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER1_SELECT1 0x38af +#define regGE2_DIST_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_SELECT 0x38b0 +#define regGE2_DIST_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER2_SELECT1 0x38b1 +#define regGE2_DIST_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_SELECT 0x38b2 +#define regGE2_DIST_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE2_DIST_PERFCOUNTER3_SELECT1 0x38b3 +#define regGE2_DIST_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER0_SELECT 0x3a20 +#define regGC_EA_CPWD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER0_SELECT1 0x3a21 +#define regGC_EA_CPWD_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGC_EA_CPWD_PERFCOUNTER1_SELECT 0x3a22 +#define regGC_EA_CPWD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_SELECT 0x3bc0 +#define regCHC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER0_SELECT1 0x3bc1 +#define regCHC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_SELECT 0x3bc2 +#define regCHC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER1_SELECT1 0x3bc3 +#define regCHC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_SELECT 0x3bc4 +#define regCHC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER2_SELECT1 0x3bc5 +#define regCHC_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_SELECT 0x3bc6 +#define regCHC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCHC_PERFCOUNTER3_SELECT1 0x3bc7 +#define regCHC_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER0_SELECT 0x3be0 +#define regGLARBA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER0_SELECT1 0x3be1 +#define regGLARBA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER1_SELECT 0x3be2 +#define regGLARBA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER1_SELECT1 0x3be3 +#define regGLARBA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER2_SELECT 0x3be4 +#define regGLARBA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER2_SELECT1 0x3be5 +#define regGLARBA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER3_SELECT 0x3be6 +#define regGLARBA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGLARBA_PERFCOUNTER3_SELECT1 0x3be7 +#define regGLARBA_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER0_SELECT 0x3bf0 +#define regGLARBC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER0_SELECT1 0x3bf1 +#define regGLARBC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER1_SELECT 0x3bf2 +#define regGLARBC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER1_SELECT1 0x3bf3 +#define regGLARBC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER2_SELECT 0x3bf4 +#define regGLARBC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER2_SELECT1 0x3bf5 +#define regGLARBC_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER3_SELECT 0x3bf6 +#define regGLARBC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGLARBC_PERFCOUNTER3_SELECT1 0x3bf7 +#define regGLARBC_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regRLC_SPM_PERFMON_CNTL 0x3c80 +#define regRLC_SPM_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_LO 0x3c81 +#define regRLC_SPM_PERFMON_RING_BASE_LO_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_BASE_HI 0x3c82 +#define regRLC_SPM_PERFMON_RING_BASE_HI_BASE_IDX 1 +#define regRLC_SPM_PERFMON_RING_SIZE 0x3c83 +#define regRLC_SPM_PERFMON_RING_SIZE_BASE_IDX 1 +#define regRLC_SPM_RING_WRPTR 0x3c84 +#define regRLC_SPM_RING_WRPTR_BASE_IDX 1 +#define regRLC_SPM_RING_RDPTR 0x3c85 +#define regRLC_SPM_RING_RDPTR_BASE_IDX 1 +#define regRLC_SPM_SEGMENT_THRESHOLD 0x3c86 +#define regRLC_SPM_SEGMENT_THRESHOLD_BASE_IDX 1 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE 0x3c87 +#define regRLC_SPM_PERFMON_SEGMENT_SIZE_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR 0x3c88 +#define regRLC_SPM_GLOBAL_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_MUXSEL_DATA 0x3c89 +#define regRLC_SPM_GLOBAL_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_ADDR 0x3c8a +#define regRLC_SPM_SE_MUXSEL_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_MUXSEL_DATA 0x3c8b +#define regRLC_SPM_SE_MUXSEL_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_USER_DATA_0 0x3c8c +#define regRLC_SPM_SE_USER_DATA_0_BASE_IDX 1 +#define regRLC_SPM_SE_USER_DATA_1 0x3c8d +#define regRLC_SPM_SE_USER_DATA_1_BASE_IDX 1 +#define regRLC_SPM_SE_USER_DATA_2 0x3c8e +#define regRLC_SPM_SE_USER_DATA_2_BASE_IDX 1 +#define regRLC_SPM_SE_USER_DATA_3 0x3c8f +#define regRLC_SPM_SE_USER_DATA_3_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_ADDR 0x3c92 +#define regRLC_SPM_ACCUM_DATARAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_DATA 0x3c93 +#define regRLC_SPM_ACCUM_DATARAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR 0x3c94 +#define regRLC_SPM_ACCUM_SWA_DATARAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SWA_DATARAM_DATA 0x3c95 +#define regRLC_SPM_ACCUM_SWA_DATARAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR 0x3c96 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_DATA 0x3c97 +#define regRLC_SPM_ACCUM_CTRLRAM_DATA_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET 0x3c98 +#define regRLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET_BASE_IDX 1 +#define regRLC_SPM_ACCUM_STATUS 0x3c99 +#define regRLC_SPM_ACCUM_STATUS_BASE_IDX 1 +#define regRLC_SPM_ACCUM_CTRL 0x3c9a +#define regRLC_SPM_ACCUM_CTRL_BASE_IDX 1 +#define regRLC_SPM_ACCUM_MODE 0x3c9b +#define regRLC_SPM_ACCUM_MODE_BASE_IDX 1 +#define regRLC_SPM_ACCUM_THRESHOLD 0x3c9c +#define regRLC_SPM_ACCUM_THRESHOLD_BASE_IDX 1 +#define regRLC_SPM_ACCUM_SAMPLES_REQUESTED 0x3c9d +#define regRLC_SPM_ACCUM_SAMPLES_REQUESTED_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_WRCOUNT 0x3c9e +#define regRLC_SPM_ACCUM_DATARAM_WRCOUNT_BASE_IDX 1 +#define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS 0x3c9f +#define regRLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS_BASE_IDX 1 +#define regRLC_SPM_PAUSE 0x3ca2 +#define regRLC_SPM_PAUSE_BASE_IDX 1 +#define regRLC_SPM_STATUS 0x3ca3 +#define regRLC_SPM_STATUS_BASE_IDX 1 +#define regRLC_SPM_GFXCLOCK_LOWCOUNT 0x3ca4 +#define regRLC_SPM_GFXCLOCK_LOWCOUNT_BASE_IDX 1 +#define regRLC_SPM_GFXCLOCK_HIGHCOUNT 0x3ca5 +#define regRLC_SPM_GFXCLOCK_HIGHCOUNT_BASE_IDX 1 +#define regRLC_SPM_GTS_TRIGGER_VALUE_LO 0x3ca6 +#define regRLC_SPM_GTS_TRIGGER_VALUE_LO_BASE_IDX 1 +#define regRLC_SPM_GTS_TRIGGER_VALUE_HI 0x3ca7 +#define regRLC_SPM_GTS_TRIGGER_VALUE_HI_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_USER_DATA_0 0x3ca8 +#define regRLC_SPM_GLOBAL_USER_DATA_0_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_USER_DATA_1 0x3ca9 +#define regRLC_SPM_GLOBAL_USER_DATA_1_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_USER_DATA_2 0x3caa +#define regRLC_SPM_GLOBAL_USER_DATA_2_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_USER_DATA_3 0x3cab +#define regRLC_SPM_GLOBAL_USER_DATA_3_BASE_IDX 1 +#define regRLC_SPM_MODE 0x3cad +#define regRLC_SPM_MODE_BASE_IDX 1 +#define regRLC_SPM_RSPM_REQ_DATA 0x3cae +#define regRLC_SPM_RSPM_REQ_DATA_BASE_IDX 1 +#define regRLC_SPM_RSPM_REQ_OP 0x3cb0 +#define regRLC_SPM_RSPM_REQ_OP_BASE_IDX 1 +#define regRLC_SPM_RSPM_RET_DATA 0x3cb1 +#define regRLC_SPM_RSPM_RET_DATA_BASE_IDX 1 +#define regRLC_SPM_RSPM_RET_OP 0x3cb2 +#define regRLC_SPM_RSPM_RET_OP_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_REQ_DATA 0x3cb3 +#define regRLC_SPM_SE_RSPM_REQ_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_REQ_OP 0x3cb5 +#define regRLC_SPM_SE_RSPM_REQ_OP_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_RET_DATA 0x3cb6 +#define regRLC_SPM_SE_RSPM_RET_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_RSPM_RET_OP 0x3cb7 +#define regRLC_SPM_SE_RSPM_RET_OP_BASE_IDX 1 +#define regRLC_SPM_RSPM_CMD 0x3cb8 +#define regRLC_SPM_RSPM_CMD_BASE_IDX 1 +#define regRLC_SPM_RSPM_CMD_ACK 0x3cb9 +#define regRLC_SPM_RSPM_CMD_ACK_BASE_IDX 1 +#define regRLC_SPM_SPARE 0x3cbf +#define regRLC_SPM_SPARE_BASE_IDX 1 +#define regRLC_PERFMON_CNTL 0x3cc0 +#define regRLC_PERFMON_CNTL_BASE_IDX 1 +#define regRLC_PERFCOUNTER0_SELECT 0x3cc1 +#define regRLC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRLC_PERFCOUNTER1_SELECT 0x3cc2 +#define regRLC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_CNTL 0x3cc3 +#define regRLC_GPU_IOV_PERF_CNT_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR 0x3cc4 +#define regRLC_GPU_IOV_PERF_CNT_WR_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA 0x3cc5 +#define regRLC_GPU_IOV_PERF_CNT_WR_DATA_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR 0x3cc6 +#define regRLC_GPU_IOV_PERF_CNT_RD_ADDR_BASE_IDX 1 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA 0x3cc7 +#define regRLC_GPU_IOV_PERF_CNT_RD_DATA_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_SELECT 0x3d60 +#define regGCR_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGCR_PERFCOUNTER0_SELECT1 0x3d61 +#define regGCR_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_SELECT 0x3d62 +#define regGCR_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGCR_PERFCOUNTER1_SELECT1 0x3d63 +#define regGCR_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_SELECT 0x3de0 +#define regCHA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER0_SELECT1 0x3de1 +#define regCHA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_SELECT 0x3de2 +#define regCHA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER1_SELECT1 0x3de3 +#define regCHA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_SELECT 0x3de4 +#define regCHA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER2_SELECT1 0x3de5 +#define regCHA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_SELECT 0x3de6 +#define regCHA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regCHA_PERFCOUNTER3_SELECT1 0x3de7 +#define regCHA_PERFCOUNTER3_SELECT1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gdfll_xvmin_xvmin_xvmin_reg_blk +// base address: 0x3a014 +#define regXVMIN_XVMIN_WR_DATA 0x4806 +#define regXVMIN_XVMIN_WR_DATA_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_hypdec +// base address: 0x3e000 +#define regRLC_GPU_IOV_VF_ENABLE 0x5b00 +#define regRLC_GPU_IOV_VF_ENABLE_BASE_IDX 1 +#define regRLC_FED_DRVR_STATUS 0x5b04 +#define regRLC_FED_DRVR_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG6 0x5b06 +#define regRLC_GPU_IOV_CFG_REG6_BASE_IDX 1 +#define regRLC_SDMA0_STATUS 0x5b18 +#define regRLC_SDMA0_STATUS_BASE_IDX 1 +#define regRLC_SDMA1_STATUS 0x5b19 +#define regRLC_SDMA1_STATUS_BASE_IDX 1 +#define regRLC_SDMA2_STATUS 0x5b1a +#define regRLC_SDMA2_STATUS_BASE_IDX 1 +#define regRLC_SDMA3_STATUS 0x5b1b +#define regRLC_SDMA3_STATUS_BASE_IDX 1 +#define regRLC_SDMA0_BUSY_STATUS 0x5b1c +#define regRLC_SDMA0_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA1_BUSY_STATUS 0x5b1d +#define regRLC_SDMA1_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA2_BUSY_STATUS 0x5b1e +#define regRLC_SDMA2_BUSY_STATUS_BASE_IDX 1 +#define regRLC_SDMA3_BUSY_STATUS 0x5b1f +#define regRLC_SDMA3_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG8 0x5b20 +#define regRLC_GPU_IOV_CFG_REG8_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS 0x5b2a +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET 0x5b2b +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_SET_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR 0x5b2c +#define regRLC_GPU_IOV_VF_DOORBELL_STATUS_CLR_BASE_IDX 1 +#define regRLC_GPU_IOV_VF_MASK 0x5b2d +#define regRLC_GPU_IOV_VF_MASK_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_0 0x5b2e +#define regRLC_HYP_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_1 0x5b2f +#define regRLC_HYP_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_BUSY_CLK_CNTL 0x5b30 +#define regRLC_BUSY_CLK_CNTL_BASE_IDX 1 +#define regRLC_CLK_CNTL 0x5b31 +#define regRLC_CLK_CNTL_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_BLOCK 0x5b34 +#define regRLC_GPU_IOV_SCH_BLOCK_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG1 0x5b35 +#define regRLC_GPU_IOV_CFG_REG1_BASE_IDX 1 +#define regRLC_GPU_IOV_CFG_REG2 0x5b36 +#define regRLC_GPU_IOV_CFG_REG2_BASE_IDX 1 +#define regRLC_GPU_IOV_VM_BUSY_STATUS 0x5b37 +#define regRLC_GPU_IOV_VM_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_0 0x5b38 +#define regRLC_GPU_IOV_SCH_0_BASE_IDX 1 +#define regRLC_GPU_IOV_ACTIVE_FCN_ID 0x5b39 +#define regRLC_GPU_IOV_ACTIVE_FCN_ID_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_3 0x5b3a +#define regRLC_GPU_IOV_SCH_3_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_1 0x5b3b +#define regRLC_GPU_IOV_SCH_1_BASE_IDX 1 +#define regRLC_GPU_IOV_SCH_2 0x5b3c +#define regRLC_GPU_IOV_SCH_2_BASE_IDX 1 +#define regRLC_IH_COOKIE 0x5b41 +#define regRLC_IH_COOKIE_BASE_IDX 1 +#define regRLC_IH_COOKIE_CNTL 0x5b42 +#define regRLC_IH_COOKIE_CNTL_BASE_IDX 1 +#define regRLC_HYP_RLCG_UCODE_CHKSUM 0x5b43 +#define regRLC_HYP_RLCG_UCODE_CHKSUM_BASE_IDX 1 +#define regRLC_GPU_IOV_SMU_RESPONSE 0x5b4a +#define regRLC_GPU_IOV_SMU_RESPONSE_BASE_IDX 1 +#define regRLC_GPU_IOV_VIRT_RESET_REQ 0x5b4c +#define regRLC_GPU_IOV_VIRT_RESET_REQ_BASE_IDX 1 +#define regRLC_GPU_IOV_RLC_RESPONSE 0x5b4d +#define regRLC_GPU_IOV_RLC_RESPONSE_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_2 0x5b52 +#define regRLC_HYP_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_HYP_SEMAPHORE_3 0x5b53 +#define regRLC_HYP_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_GPM_UCODE_ADDR 0x5b60 +#define regRLC_GPM_UCODE_ADDR_BASE_IDX 1 +#define regRLC_GPM_UCODE_DATA 0x5b61 +#define regRLC_GPM_UCODE_DATA_BASE_IDX 1 +#define regRLC_GPM_IRAM_ADDR 0x5b62 +#define regRLC_GPM_IRAM_ADDR_BASE_IDX 1 +#define regRLC_GPM_IRAM_DATA 0x5b63 +#define regRLC_GPM_IRAM_DATA_BASE_IDX 1 +#define regRLC_LX6_DRAM_ADDR 0x5b68 +#define regRLC_LX6_DRAM_ADDR_BASE_IDX 1 +#define regRLC_LX6_DRAM_DATA 0x5b69 +#define regRLC_LX6_DRAM_DATA_BASE_IDX 1 +#define regRLC_LX6_IRAM_ADDR 0x5b6a +#define regRLC_LX6_IRAM_ADDR_BASE_IDX 1 +#define regRLC_LX6_IRAM_DATA 0x5b6b +#define regRLC_LX6_IRAM_DATA_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_ADDR 0x5b6e +#define regRLC_GPM_SCRATCH_ADDR_BASE_IDX 1 +#define regRLC_GPM_SCRATCH_DATA 0x5b6f +#define regRLC_GPM_SCRATCH_DATA_BASE_IDX 1 +#define regRLC_SRM_DRAM_ADDR 0x5b71 +#define regRLC_SRM_DRAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_DRAM_DATA 0x5b72 +#define regRLC_SRM_DRAM_DATA_BASE_IDX 1 +#define regRLC_SRM_ARAM_ADDR 0x5b73 +#define regRLC_SRM_ARAM_ADDR_BASE_IDX 1 +#define regRLC_SRM_ARAM_DATA 0x5b74 +#define regRLC_SRM_ARAM_DATA_BASE_IDX 1 +#define regRLC_GTS_OFFSET_LSB 0x5b79 +#define regRLC_GTS_OFFSET_LSB_BASE_IDX 1 +#define regRLC_GTS_OFFSET_MSB 0x5b7a +#define regRLC_GTS_OFFSET_MSB_BASE_IDX 1 +#define regRLC_GTS_OFFSET_SNAP_LSB 0x5b7b +#define regRLC_GTS_OFFSET_SNAP_LSB_BASE_IDX 1 +#define regRLC_GTS_OFFSET_SNAP_MSB 0x5b7c +#define regRLC_GTS_OFFSET_SNAP_MSB_BASE_IDX 1 +#define regRLC_GAP_PWROK 0x5b7d +#define regRLC_GAP_PWROK_BASE_IDX 1 +#define regRLC_GAP_PWROK_COUNT 0x5b7e +#define regRLC_GAP_PWROK_COUNT_BASE_IDX 1 +#define regGLARB_HASH_CFG 0x5b87 +#define regGLARB_HASH_CFG_BASE_IDX 1 +#define regCH_PIPE_STEER 0x5b88 +#define regCH_PIPE_STEER_BASE_IDX 1 +#define regGLARB_PIPE_STEER_LSB 0x5b89 +#define regGLARB_PIPE_STEER_LSB_BASE_IDX 1 +#define regGLARB_PIPE_STEER_MSB 0x5b8a +#define regGLARB_PIPE_STEER_MSB_BASE_IDX 1 +#define regCH_HASH_CFG 0x5b8b +#define regCH_HASH_CFG_BASE_IDX 1 +#define regGLARB_LPDDR_PIPE_STEER_LSB 0x5b8c +#define regGLARB_LPDDR_PIPE_STEER_LSB_BASE_IDX 1 +#define regGLARB_LPDDR_PIPE_STEER_MSB 0x5b8d +#define regGLARB_LPDDR_PIPE_STEER_MSB_BASE_IDX 1 +#define regGLARB_LOCAL_CAC 0x5b8e +#define regGLARB_LOCAL_CAC_BASE_IDX 1 +#define regGLARB_AID_SEL_CFG 0x5b8f +#define regGLARB_AID_SEL_CFG_BASE_IDX 1 +#define regGC_USER_FULL_SA_UNIT_DISABLE 0x5b91 +#define regGC_USER_FULL_SA_UNIT_DISABLE_BASE_IDX 1 +#define regGC_USER_SA_UNIT_DISABLE 0x5b92 +#define regGC_USER_SA_UNIT_DISABLE_BASE_IDX 1 +#define regGC_USER_HBM_DISABLE 0x5b93 +#define regGC_USER_HBM_DISABLE_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_STATUS 0x5bc0 +#define regRLC_GPU_IOV_SDMA0_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_STATUS 0x5bc1 +#define regRLC_GPU_IOV_SDMA1_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_STATUS 0x5bc2 +#define regRLC_GPU_IOV_SDMA2_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_STATUS 0x5bc3 +#define regRLC_GPU_IOV_SDMA3_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_STATUS 0x5bc4 +#define regRLC_GPU_IOV_SDMA4_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_STATUS 0x5bc5 +#define regRLC_GPU_IOV_SDMA5_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_STATUS 0x5bc6 +#define regRLC_GPU_IOV_SDMA6_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_STATUS 0x5bc7 +#define regRLC_GPU_IOV_SDMA7_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS 0x5bc8 +#define regRLC_GPU_IOV_SDMA0_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS 0x5bc9 +#define regRLC_GPU_IOV_SDMA1_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS 0x5bca +#define regRLC_GPU_IOV_SDMA2_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS 0x5bcb +#define regRLC_GPU_IOV_SDMA3_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS 0x5bcc +#define regRLC_GPU_IOV_SDMA4_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS 0x5bcd +#define regRLC_GPU_IOV_SDMA5_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS 0x5bce +#define regRLC_GPU_IOV_SDMA6_BUSY_STATUS_BASE_IDX 1 +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS 0x5bcf +#define regRLC_GPU_IOV_SDMA7_BUSY_STATUS_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cphypdec +// base address: 0x3e000 +#define regCP_HYP_CONTEXT_RANGE_BASE 0x580a +#define regCP_HYP_CONTEXT_RANGE_BASE_BASE_IDX 1 +#define regCP_HYP_CONTEXT_RANGE_END 0x580b +#define regCP_HYP_CONTEXT_RANGE_END_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_ADDR 0x5814 +#define regCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_PFP_UCODE_ADDR 0x5814 +#define regCP_PFP_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_DATA 0x5815 +#define regCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_PFP_UCODE_DATA 0x5815 +#define regCP_PFP_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_ADDR 0x5816 +#define regCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 +#define regCP_ME_RAM_RADDR 0x5816 +#define regCP_ME_RAM_RADDR_BASE_IDX 1 +#define regCP_ME_RAM_WADDR 0x5816 +#define regCP_ME_RAM_WADDR_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_DATA 0x5817 +#define regCP_HYP_ME_UCODE_DATA_BASE_IDX 1 +#define regCP_ME_RAM_DATA 0x5817 +#define regCP_ME_RAM_DATA_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_ADDR 0x581a +#define regCP_HYP_MEC1_UCODE_ADDR_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_ADDR 0x581a +#define regCP_MEC_ME1_UCODE_ADDR_BASE_IDX 1 +#define regCP_HYP_MEC1_UCODE_DATA 0x581b +#define regCP_HYP_MEC1_UCODE_DATA_BASE_IDX 1 +#define regCP_MEC_ME1_UCODE_DATA 0x581b +#define regCP_MEC_ME1_UCODE_DATA_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_CHKSUM 0x581e +#define regCP_HYP_PFP_UCODE_CHKSUM_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_CHKSUM 0x5820 +#define regCP_HYP_ME_UCODE_CHKSUM_BASE_IDX 1 +#define regCP_HYP_MEC_ME1_UCODE_CHKSUM 0x5821 +#define regCP_HYP_MEC_ME1_UCODE_CHKSUM_BASE_IDX 1 +#define regCP_PFP_IC_BASE_LO 0x5840 +#define regCP_PFP_IC_BASE_LO_BASE_IDX 1 +#define regCP_PFP_IC_BASE_HI 0x5841 +#define regCP_PFP_IC_BASE_HI_BASE_IDX 1 +#define regCP_PFP_IC_BASE_CNTL 0x5842 +#define regCP_PFP_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_PFP_IC_OP_CNTL 0x5843 +#define regCP_PFP_IC_OP_CNTL_BASE_IDX 1 +#define regCP_ME_IC_BASE_LO 0x5844 +#define regCP_ME_IC_BASE_LO_BASE_IDX 1 +#define regCP_ME_IC_BASE_HI 0x5845 +#define regCP_ME_IC_BASE_HI_BASE_IDX 1 +#define regCP_ME_IC_BASE_CNTL 0x5846 +#define regCP_ME_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_ME_IC_OP_CNTL 0x5847 +#define regCP_ME_IC_OP_CNTL_BASE_IDX 1 +#define regCP_CPC_IC_BASE_LO 0x584c +#define regCP_CPC_IC_BASE_LO_BASE_IDX 1 +#define regCP_CPC_IC_BASE_HI 0x584d +#define regCP_CPC_IC_BASE_HI_BASE_IDX 1 +#define regCP_CPC_IC_BASE_CNTL 0x584e +#define regCP_CPC_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_IC_BASE_LO 0x5850 +#define regCP_MES_IC_BASE_LO_BASE_IDX 1 +#define regCP_MES_MIBASE_LO 0x5850 +#define regCP_MES_MIBASE_LO_BASE_IDX 1 +#define regCP_MES_IC_BASE_HI 0x5851 +#define regCP_MES_IC_BASE_HI_BASE_IDX 1 +#define regCP_MES_MIBASE_HI 0x5851 +#define regCP_MES_MIBASE_HI_BASE_IDX 1 +#define regCP_MES_IC_BASE_CNTL 0x5852 +#define regCP_MES_IC_BASE_CNTL_BASE_IDX 1 +#define regCP_MES_DC_BASE_LO 0x5854 +#define regCP_MES_DC_BASE_LO_BASE_IDX 1 +#define regCP_MES_MDBASE_LO 0x5854 +#define regCP_MES_MDBASE_LO_BASE_IDX 1 +#define regCP_MES_DC_BASE_HI 0x5855 +#define regCP_MES_DC_BASE_HI_BASE_IDX 1 +#define regCP_MES_MDBASE_HI 0x5855 +#define regCP_MES_MDBASE_HI_BASE_IDX 1 +#define regCP_MES_MIBOUND_LO 0x585b +#define regCP_MES_MIBOUND_LO_BASE_IDX 1 +#define regCP_MES_MIBOUND_HI 0x585c +#define regCP_MES_MIBOUND_HI_BASE_IDX 1 +#define regCP_MES_MDBOUND_LO 0x585d +#define regCP_MES_MDBOUND_LO_BASE_IDX 1 +#define regCP_MES_MDBOUND_HI 0x585e +#define regCP_MES_MDBOUND_HI_BASE_IDX 1 +#define regCP_HYP_PFP_UCODE_VERS 0x5861 +#define regCP_HYP_PFP_UCODE_VERS_BASE_IDX 1 +#define regCP_HYP_ME_UCODE_VERS 0x5862 +#define regCP_HYP_ME_UCODE_VERS_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE0_LO 0x5863 +#define regCP_GFX_RS64_DC_BASE0_LO_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE1_LO 0x5864 +#define regCP_GFX_RS64_DC_BASE1_LO_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE0_HI 0x5865 +#define regCP_GFX_RS64_DC_BASE0_HI_BASE_IDX 1 +#define regCP_GFX_RS64_DC_BASE1_HI 0x5866 +#define regCP_GFX_RS64_DC_BASE1_HI_BASE_IDX 1 +#define regCP_GFX_RS64_MIBOUND_LO 0x586c +#define regCP_GFX_RS64_MIBOUND_LO_BASE_IDX 1 +#define regCP_GFX_RS64_MIBOUND_HI 0x586d +#define regCP_GFX_RS64_MIBOUND_HI_BASE_IDX 1 +#define regCP_MEC_DC_BASE_LO 0x5870 +#define regCP_MEC_DC_BASE_LO_BASE_IDX 1 +#define regCP_MEC_MDBASE_LO 0x5870 +#define regCP_MEC_MDBASE_LO_BASE_IDX 1 +#define regCP_MEC_DC_BASE_HI 0x5871 +#define regCP_MEC_DC_BASE_HI_BASE_IDX 1 +#define regCP_MEC_MDBASE_HI 0x5871 +#define regCP_MEC_MDBASE_HI_BASE_IDX 1 +#define regCP_MEC_MIBOUND_LO 0x5872 +#define regCP_MEC_MIBOUND_LO_BASE_IDX 1 +#define regCP_MEC_MIBOUND_HI 0x5873 +#define regCP_MEC_MIBOUND_HI_BASE_IDX 1 +#define regCP_MEC_MDBOUND_LO 0x5874 +#define regCP_MEC_MDBOUND_LO_BASE_IDX 1 +#define regCP_MEC_MDBOUND_HI 0x5875 +#define regCP_MEC_MDBOUND_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_grbm_hypdec +// base address: 0x3eea0 +#define regGRBM_GFX_INDEX_SR_SELECT 0x5ba8 +#define regGRBM_GFX_INDEX_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_INDEX_SR_DATA 0x5ba9 +#define regGRBM_GFX_INDEX_SR_DATA_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_SELECT 0x5baa +#define regGRBM_GFX_CNTL_SR_SELECT_BASE_IDX 1 +#define regGRBM_GFX_CNTL_SR_DATA 0x5bab +#define regGRBM_GFX_CNTL_SR_DATA_BASE_IDX 1 +#define regGC_IH_COOKIE_0_PTR_HIGH 0x5bac +#define regGC_IH_COOKIE_0_PTR_HIGH_BASE_IDX 1 +#define regGC_IH_COOKIE_0_PTR 0x5baf +#define regGC_IH_COOKIE_0_PTR_BASE_IDX 1 +#define regGRBM_SE_REMAP_CNTL 0x5bb0 +#define regGRBM_SE_REMAP_CNTL_BASE_IDX 1 +#define regGRBM_SA_REMAP_CNTL 0x5bb1 +#define regGRBM_SA_REMAP_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcdec +// base address: 0x3b000 +#define regRLC_CNTL 0x4c00 +#define regRLC_CNTL_BASE_IDX 1 +#define regRLC_F32_UCODE_VERSION 0x4c03 +#define regRLC_F32_UCODE_VERSION_BASE_IDX 1 +#define regRLC_STAT 0x4c04 +#define regRLC_STAT_BASE_IDX 1 +#define regRLC_ACTIVE_MASK 0x4c05 +#define regRLC_ACTIVE_MASK_BASE_IDX 1 +#define regRLC_GFX_SE_STATUS 0x4c06 +#define regRLC_GFX_SE_STATUS_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_LSB 0x4c0c +#define regRLC_REFCLOCK_TIMESTAMP_LSB_BASE_IDX 1 +#define regRLC_REFCLOCK_TIMESTAMP_MSB 0x4c0d +#define regRLC_REFCLOCK_TIMESTAMP_MSB_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_0 0x4c0e +#define regRLC_GPM_TIMER_INT_0_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_1 0x4c0f +#define regRLC_GPM_TIMER_INT_1_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_2 0x4c10 +#define regRLC_GPM_TIMER_INT_2_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_3 0x4c11 +#define regRLC_GPM_TIMER_INT_3_BASE_IDX 1 +#define regRLC_GPM_TIMER_INT_4 0x4c12 +#define regRLC_GPM_TIMER_INT_4_BASE_IDX 1 +#define regRLC_GPM_TIMER_CTRL 0x4c13 +#define regRLC_GPM_TIMER_CTRL_BASE_IDX 1 +#define regRLC_GPM_TIMER_STAT 0x4c14 +#define regRLC_GPM_TIMER_STAT_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_STAT 0x4c16 +#define regRLC_GPM_LEGACY_INT_STAT_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_CLEAR 0x4c17 +#define regRLC_GPM_LEGACY_INT_CLEAR_BASE_IDX 1 +#define regRLC_INT_STAT 0x4c18 +#define regRLC_INT_STAT_BASE_IDX 1 +#define regRLC_MGCG_CTRL 0x4c1a +#define regRLC_MGCG_CTRL_BASE_IDX 1 +#define regRLC_MCA_DF_RASINTRCTRL_REG_CTRL 0x4c1c +#define regRLC_MCA_DF_RASINTRCTRL_REG_CTRL_BASE_IDX 1 +#define regRLC_JUMP_TABLE_RESTORE 0x4c1e +#define regRLC_JUMP_TABLE_RESTORE_BASE_IDX 1 +#define regRLC_PG_DELAY_2 0x4c1f +#define regRLC_PG_DELAY_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB 0x4c24 +#define regRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB 0x4c25 +#define regRLC_GPU_CLOCK_COUNT_MSB_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT 0x4c26 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_BASE_IDX 1 +#define regRLC_UCODE_CNTL 0x4c27 +#define regRLC_UCODE_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_RESET 0x4c28 +#define regRLC_GPM_THREAD_RESET_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T0 0x4c29 +#define regRLC_GPM_CP_DMA_COMPLETE_T0_BASE_IDX 1 +#define regRLC_GPM_CP_DMA_COMPLETE_T1 0x4c2a +#define regRLC_GPM_CP_DMA_COMPLETE_T1_BASE_IDX 1 +#define regRLC_GPM_THREAD_INVALIDATE_CACHE 0x4c2b +#define regRLC_GPM_THREAD_INVALIDATE_CACHE_BASE_IDX 1 +#define regRLC_MCA_DF_RASINTRCTRL_REG_LO 0x4c2c +#define regRLC_MCA_DF_RASINTRCTRL_REG_LO_BASE_IDX 1 +#define regRLC_MCA_DF_RASINTRCTRL_REG_HI 0x4c2d +#define regRLC_MCA_DF_RASINTRCTRL_REG_HI_BASE_IDX 1 +#define regRLC_MCA_INTR_CTRL 0x4c2e +#define regRLC_MCA_INTR_CTRL_BASE_IDX 1 +#define regRLC_MCA_INTR_INFO 0x4c2f +#define regRLC_MCA_INTR_INFO_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_LSB 0x4c30 +#define regRLC_CLK_COUNT_GFXCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_GFXCLK_MSB 0x4c31 +#define regRLC_CLK_COUNT_GFXCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_LSB 0x4c32 +#define regRLC_CLK_COUNT_REFCLK_LSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_REFCLK_MSB 0x4c33 +#define regRLC_CLK_COUNT_REFCLK_MSB_BASE_IDX 1 +#define regRLC_CLK_COUNT_CTRL 0x4c34 +#define regRLC_CLK_COUNT_CTRL_BASE_IDX 1 +#define regRLC_CLK_COUNT_STAT 0x4c35 +#define regRLC_CLK_COUNT_STAT_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_CNTL 0x4c36 +#define regRLC_RLCG_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_STAT 0x4c37 +#define regRLC_RLCG_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_0_DATA_LO 0x4c38 +#define regRLC_RLCG_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_0_DATA_HI 0x4c39 +#define regRLC_RLCG_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_1_DATA_LO 0x4c3a +#define regRLC_RLCG_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_1_DATA_HI 0x4c3b +#define regRLC_RLCG_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_2_DATA_LO 0x4c3c +#define regRLC_RLCG_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_2_DATA_HI 0x4c3d +#define regRLC_RLCG_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_3_DATA_LO 0x4c3e +#define regRLC_RLCG_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_3_DATA_HI 0x4c3f +#define regRLC_RLCG_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32_RES_SEL 0x4c41 +#define regRLC_GPU_CLOCK_32_RES_SEL_BASE_IDX 1 +#define regRLC_GPU_CLOCK_32 0x4c42 +#define regRLC_GPU_CLOCK_32_BASE_IDX 1 +#define regRLC_PG_CNTL 0x4c43 +#define regRLC_PG_CNTL_BASE_IDX 1 +#define regRLC_GPM_THREAD_PRIORITY 0x4c44 +#define regRLC_GPM_THREAD_PRIORITY_BASE_IDX 1 +#define regRLC_GPM_THREAD_ENABLE 0x4c45 +#define regRLC_GPM_THREAD_ENABLE_BASE_IDX 1 +#define regRLC_RLCG_DOORBELL_RANGE 0x4c47 +#define regRLC_RLCG_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_CGTT_MGCG_OVERRIDE 0x4c48 +#define regRLC_CGTT_MGCG_OVERRIDE_BASE_IDX 1 +#define regRLC_CGCG_CGLS_CTRL 0x4c49 +#define regRLC_CGCG_CGLS_CTRL_BASE_IDX 1 +#define regRLC_CGCG_RAMP_CTRL 0x4c4a +#define regRLC_CGCG_RAMP_CTRL_BASE_IDX 1 +#define regRLC_DYN_PG_STATUS 0x4c4b +#define regRLC_DYN_PG_STATUS_BASE_IDX 1 +#define regRLC_DYN_PG_REQUEST 0x4c4c +#define regRLC_DYN_PG_REQUEST_BASE_IDX 1 +#define regRLC_PG_DELAY 0x4c4d +#define regRLC_PG_DELAY_BASE_IDX 1 +#define regRLC_CGCG_CGLS_CTRL_2 0x4c4e +#define regRLC_CGCG_CGLS_CTRL_2_BASE_IDX 1 +#define regRLC_PG_ALWAYS_ON_WGP_MASK 0x4c53 +#define regRLC_PG_ALWAYS_ON_WGP_MASK_BASE_IDX 1 +#define regRLC_MAX_PG_WGP 0x4c54 +#define regRLC_MAX_PG_WGP_BASE_IDX 1 +#define regRLC_AUTO_PG_CTRL 0x4c55 +#define regRLC_AUTO_PG_CTRL_BASE_IDX 1 +#define regRLC_SERDES_RD_INDEX 0x4c59 +#define regRLC_SERDES_RD_INDEX_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_0 0x4c5a +#define regRLC_SERDES_RD_DATA_0_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_1 0x4c5b +#define regRLC_SERDES_RD_DATA_1_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_2 0x4c5c +#define regRLC_SERDES_RD_DATA_2_BASE_IDX 1 +#define regRLC_SERDES_RD_DATA_3 0x4c5d +#define regRLC_SERDES_RD_DATA_3_BASE_IDX 1 +#define regRLC_SERDES_MASK 0x4c5e +#define regRLC_SERDES_MASK_BASE_IDX 1 +#define regRLC_SERDES_CTRL 0x4c5f +#define regRLC_SERDES_CTRL_BASE_IDX 1 +#define regRLC_SERDES_DATA 0x4c60 +#define regRLC_SERDES_DATA_BASE_IDX 1 +#define regRLC_SERDES_BUSY 0x4c61 +#define regRLC_SERDES_BUSY_BASE_IDX 1 +#define regRLC_GPM_GENERAL_0 0x4c63 +#define regRLC_GPM_GENERAL_0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_1 0x4c64 +#define regRLC_GPM_GENERAL_1_BASE_IDX 1 +#define regRLC_GPM_GENERAL_2 0x4c65 +#define regRLC_GPM_GENERAL_2_BASE_IDX 1 +#define regRLC_GPM_GENERAL_3 0x4c66 +#define regRLC_GPM_GENERAL_3_BASE_IDX 1 +#define regRLC_GPM_GENERAL_4 0x4c67 +#define regRLC_GPM_GENERAL_4_BASE_IDX 1 +#define regRLC_GPM_GENERAL_5 0x4c68 +#define regRLC_GPM_GENERAL_5_BASE_IDX 1 +#define regRLC_GPM_GENERAL_6 0x4c69 +#define regRLC_GPM_GENERAL_6_BASE_IDX 1 +#define regRLC_GPM_GENERAL_7 0x4c6a +#define regRLC_GPM_GENERAL_7_BASE_IDX 1 +#define regRLC_STATIC_PG_STATUS 0x4c6e +#define regRLC_STATIC_PG_STATUS_BASE_IDX 1 +#define regRLC_GPM_GENERAL_16 0x4c76 +#define regRLC_GPM_GENERAL_16_BASE_IDX 1 +#define regRLC_PG_DELAY_3 0x4c78 +#define regRLC_PG_DELAY_3_BASE_IDX 1 +#define regRLC_GPR_REG1 0x4c79 +#define regRLC_GPR_REG1_BASE_IDX 1 +#define regRLC_GPR_REG2 0x4c7a +#define regRLC_GPR_REG2_BASE_IDX 1 +#define regRLC_GPM_INT_DISABLE_TH0 0x4c7c +#define regRLC_GPM_INT_DISABLE_TH0_BASE_IDX 1 +#define regRLC_GPM_LEGACY_INT_DISABLE 0x4c7d +#define regRLC_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 +#define regRLC_GPM_INT_FORCE_TH0 0x4c7e +#define regRLC_GPM_INT_FORCE_TH0_BASE_IDX 1 +#define regRLC_SRM_CNTL 0x4c80 +#define regRLC_SRM_CNTL_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND_STATUS 0x4c88 +#define regRLC_SRM_GPM_COMMAND_STATUS_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b +#define regRLC_SRM_INDEX_CNTL_ADDR_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_1 0x4c8c +#define regRLC_SRM_INDEX_CNTL_ADDR_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_2 0x4c8d +#define regRLC_SRM_INDEX_CNTL_ADDR_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_3 0x4c8e +#define regRLC_SRM_INDEX_CNTL_ADDR_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_4 0x4c8f +#define regRLC_SRM_INDEX_CNTL_ADDR_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_5 0x4c90 +#define regRLC_SRM_INDEX_CNTL_ADDR_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_6 0x4c91 +#define regRLC_SRM_INDEX_CNTL_ADDR_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_ADDR_7 0x4c92 +#define regRLC_SRM_INDEX_CNTL_ADDR_7_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_0 0x4c93 +#define regRLC_SRM_INDEX_CNTL_DATA_0_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_1 0x4c94 +#define regRLC_SRM_INDEX_CNTL_DATA_1_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_2 0x4c95 +#define regRLC_SRM_INDEX_CNTL_DATA_2_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_3 0x4c96 +#define regRLC_SRM_INDEX_CNTL_DATA_3_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_4 0x4c97 +#define regRLC_SRM_INDEX_CNTL_DATA_4_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_5 0x4c98 +#define regRLC_SRM_INDEX_CNTL_DATA_5_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_6 0x4c99 +#define regRLC_SRM_INDEX_CNTL_DATA_6_BASE_IDX 1 +#define regRLC_SRM_INDEX_CNTL_DATA_7 0x4c9a +#define regRLC_SRM_INDEX_CNTL_DATA_7_BASE_IDX 1 +#define regRLC_SRM_STAT 0x4c9b +#define regRLC_SRM_STAT_BASE_IDX 1 +#define regRLC_LX6_UTCL1_ERROR_2 0x4ca8 +#define regRLC_LX6_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_GENERAL_8 0x4cad +#define regRLC_GPM_GENERAL_8_BASE_IDX 1 +#define regRLC_GPM_GENERAL_9 0x4cae +#define regRLC_GPM_GENERAL_9_BASE_IDX 1 +#define regRLC_GPM_GENERAL_10 0x4caf +#define regRLC_GPM_GENERAL_10_BASE_IDX 1 +#define regRLC_GPM_GENERAL_11 0x4cb0 +#define regRLC_GPM_GENERAL_11_BASE_IDX 1 +#define regRLC_GPM_GENERAL_12 0x4cb1 +#define regRLC_GPM_GENERAL_12_BASE_IDX 1 +#define regRLC_GPM_UTCL1_CNTL_0 0x4cb2 +#define regRLC_GPM_UTCL1_CNTL_0_BASE_IDX 1 +#define regRLC_SPM_UTCL1_CNTL 0x4cb5 +#define regRLC_SPM_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_UTCL1_STATUS_2 0x4cb6 +#define regRLC_UTCL1_STATUS_2_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_1 0x4cbc +#define regRLC_SPM_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_SPM_UTCL1_ERROR_2 0x4cbd +#define regRLC_SPM_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_1 0x4cbe +#define regRLC_GPM_UTCL1_TH0_ERROR_1_BASE_IDX 1 +#define regRLC_GPM_UTCL1_TH0_ERROR_2 0x4cc0 +#define regRLC_GPM_UTCL1_TH0_ERROR_2_BASE_IDX 1 +#define regRLC_SEMAPHORE_0 0x4cc7 +#define regRLC_SEMAPHORE_0_BASE_IDX 1 +#define regRLC_SEMAPHORE_1 0x4cc8 +#define regRLC_SEMAPHORE_1_BASE_IDX 1 +#define regRLC_SEMAPHORE_2 0x4cc9 +#define regRLC_SEMAPHORE_2_BASE_IDX 1 +#define regRLC_SEMAPHORE_3 0x4cca +#define regRLC_SEMAPHORE_3_BASE_IDX 1 +#define regRLC_SRM_UTCL1_CNTL 0x4ccc +#define regRLC_SRM_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_SRM_UTCL1_ERROR_1 0x4ccd +#define regRLC_SRM_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_SRM_UTCL1_ERROR_2 0x4cce +#define regRLC_SRM_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_DLG_UTCL1_ERROR_2 0x4cd1 +#define regRLC_DLG_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_UTCL1_STATUS 0x4cd4 +#define regRLC_UTCL1_STATUS_BASE_IDX 1 +#define regRLC_R2I_CNTL_0 0x4cd5 +#define regRLC_R2I_CNTL_0_BASE_IDX 1 +#define regRLC_R2I_CNTL_1 0x4cd6 +#define regRLC_R2I_CNTL_1_BASE_IDX 1 +#define regRLC_R2I_CNTL_2 0x4cd7 +#define regRLC_R2I_CNTL_2_BASE_IDX 1 +#define regRLC_R2I_CNTL_3 0x4cd8 +#define regRLC_R2I_CNTL_3_BASE_IDX 1 +#define regRLC_GPM_INT_STAT_TH0 0x4cdc +#define regRLC_GPM_INT_STAT_TH0_BASE_IDX 1 +#define regRLC_GPM_GENERAL_13 0x4cdd +#define regRLC_GPM_GENERAL_13_BASE_IDX 1 +#define regRLC_GPM_GENERAL_14 0x4cde +#define regRLC_GPM_GENERAL_14_BASE_IDX 1 +#define regRLC_GPM_GENERAL_15 0x4cdf +#define regRLC_GPM_GENERAL_15_BASE_IDX 1 +#define regRLC_LX6_UTCL1_ERROR_1 0x4ce3 +#define regRLC_LX6_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_LX6_UTCL1_CNTL 0x4ce4 +#define regRLC_LX6_UTCL1_CNTL_BASE_IDX 1 +#define regRLC_DMA_UTCL1_ERROR_1 0x4ce6 +#define regRLC_DMA_UTCL1_ERROR_1_BASE_IDX 1 +#define regRLC_DMA_UTCL1_ERROR_2 0x4ce7 +#define regRLC_DMA_UTCL1_ERROR_2_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1 0x4cea +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_2 0x4ceb +#define regRLC_GPU_CLOCK_COUNT_LSB_2_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_2 0x4cec +#define regRLC_GPU_CLOCK_COUNT_MSB_2_BASE_IDX 1 +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2 0x4cef +#define regRLC_CAPTURE_GPU_CLOCK_COUNT_2_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_RANGE 0x4cf0 +#define regRLC_RLCV_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_CNTL 0x4cf1 +#define regRLC_RLCV_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_STAT 0x4cf2 +#define regRLC_RLCV_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_0_DATA_LO 0x4cf3 +#define regRLC_RLCV_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_0_DATA_HI 0x4cf4 +#define regRLC_RLCV_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_1_DATA_LO 0x4cf5 +#define regRLC_RLCV_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_1_DATA_HI 0x4cf6 +#define regRLC_RLCV_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_2_DATA_LO 0x4cf7 +#define regRLC_RLCV_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_2_DATA_HI 0x4cf8 +#define regRLC_RLCV_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_3_DATA_LO 0x4cf9 +#define regRLC_RLCV_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_RLCV_DOORBELL_3_DATA_HI 0x4cfa +#define regRLC_RLCV_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_LSB_1 0x4cfb +#define regRLC_GPU_CLOCK_COUNT_LSB_1_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_MSB_1 0x4cfc +#define regRLC_GPU_CLOCK_COUNT_MSB_1_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT 0x4d00 +#define regRLC_RLCV_SPARE_INT_BASE_IDX 1 +#define regRLC_SMU_CLK_REQ 0x4d08 +#define regRLC_SMU_CLK_REQ_BASE_IDX 1 +#define regRLC_SPARE 0x4d0b +#define regRLC_SPARE_BASE_IDX 1 +#define regRLC_SPP_CTRL 0x4d0c +#define regRLC_SPP_CTRL_BASE_IDX 1 +#define regRLC_SPP_SHADER_PROFILE_EN 0x4d0d +#define regRLC_SPP_SHADER_PROFILE_EN_BASE_IDX 1 +#define regRLC_SPP_SSF_CAPTURE_EN 0x4d0e +#define regRLC_SPP_SSF_CAPTURE_EN_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_0 0x4d0f +#define regRLC_SPP_SSF_THRESHOLD_0_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_1 0x4d10 +#define regRLC_SPP_SSF_THRESHOLD_1_BASE_IDX 1 +#define regRLC_SPP_SSF_THRESHOLD_2 0x4d11 +#define regRLC_SPP_SSF_THRESHOLD_2_BASE_IDX 1 +#define regRLC_SPP_INFLIGHT_RD_ADDR 0x4d12 +#define regRLC_SPP_INFLIGHT_RD_ADDR_BASE_IDX 1 +#define regRLC_SPP_INFLIGHT_RD_DATA 0x4d13 +#define regRLC_SPP_INFLIGHT_RD_DATA_BASE_IDX 1 +#define regRLC_SPP_PROF_INFO_1 0x4d18 +#define regRLC_SPP_PROF_INFO_1_BASE_IDX 1 +#define regRLC_SPP_PROF_INFO_2 0x4d19 +#define regRLC_SPP_PROF_INFO_2_BASE_IDX 1 +#define regRLC_SPP_GLOBAL_SH_ID 0x4d1a +#define regRLC_SPP_GLOBAL_SH_ID_BASE_IDX 1 +#define regRLC_SPP_GLOBAL_SH_ID_VALID 0x4d1b +#define regRLC_SPP_GLOBAL_SH_ID_VALID_BASE_IDX 1 +#define regRLC_SPP_STATUS 0x4d1c +#define regRLC_SPP_STATUS_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_0 0x4d1d +#define regRLC_SPP_PVT_STAT_0_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_1 0x4d1e +#define regRLC_SPP_PVT_STAT_1_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_2 0x4d1f +#define regRLC_SPP_PVT_STAT_2_BASE_IDX 1 +#define regRLC_SPP_PVT_STAT_3 0x4d20 +#define regRLC_SPP_PVT_STAT_3_BASE_IDX 1 +#define regRLC_SPP_PVT_LEVEL_MAX 0x4d21 +#define regRLC_SPP_PVT_LEVEL_MAX_BASE_IDX 1 +#define regRLC_SPP_STALL_STATE_UPDATE 0x4d22 +#define regRLC_SPP_STALL_STATE_UPDATE_BASE_IDX 1 +#define regRLC_SPP_PBB_INFO 0x4d23 +#define regRLC_SPP_PBB_INFO_BASE_IDX 1 +#define regRLC_SPP_RESET 0x4d24 +#define regRLC_SPP_RESET_BASE_IDX 1 +#define regRLC_CAC_MASK_CNTL 0x4d45 +#define regRLC_CAC_MASK_CNTL_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_CNTR_CTRL 0x4d48 +#define regRLC_POWER_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_CNTR_CTRL 0x4d49 +#define regRLC_CLK_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_CNTR_CTRL 0x4d4a +#define regRLC_DS_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_CNTR_CTRL 0x4d4b +#define regRLC_ULV_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_CNTR_CTRL 0x4d4c +#define regRLC_PCC_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_CNTR_CTRL 0x4d4d +#define regRLC_GENERAL_RESIDENCY_CNTR_CTRL_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_EVENT_CNTR 0x4d50 +#define regRLC_POWER_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_EVENT_CNTR 0x4d51 +#define regRLC_CLK_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_EVENT_CNTR 0x4d52 +#define regRLC_DS_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_EVENT_CNTR 0x4d53 +#define regRLC_ULV_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_EVENT_CNTR 0x4d54 +#define regRLC_PCC_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_EVENT_CNTR 0x4d55 +#define regRLC_GENERAL_RESIDENCY_EVENT_CNTR_BASE_IDX 1 +#define regRLC_POWER_RESIDENCY_REF_CNTR 0x4d58 +#define regRLC_POWER_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_CLK_RESIDENCY_REF_CNTR 0x4d59 +#define regRLC_CLK_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_DS_RESIDENCY_REF_CNTR 0x4d5a +#define regRLC_DS_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_ULV_RESIDENCY_REF_CNTR 0x4d5b +#define regRLC_ULV_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_PCC_RESIDENCY_REF_CNTR 0x4d5c +#define regRLC_PCC_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_GENERAL_RESIDENCY_REF_CNTR 0x4d5d +#define regRLC_GENERAL_RESIDENCY_REF_CNTR_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_CTRL 0x4d5e +#define regRLC_GFX_IH_CLIENT_CTRL_BASE_IDX 1 +#define regRLC_GFX_IH_ARBITER_STAT 0x4d5f +#define regRLC_GFX_IH_ARBITER_STAT_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SE_STAT_L 0x4d60 +#define regRLC_GFX_IH_CLIENT_SE_STAT_L_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SE_STAT_H 0x4d61 +#define regRLC_GFX_IH_CLIENT_SE_STAT_H_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_SDMA_STAT 0x4d62 +#define regRLC_GFX_IH_CLIENT_SDMA_STAT_BASE_IDX 1 +#define regRLC_GFX_IH_CLIENT_OTHER_STAT 0x4d63 +#define regRLC_GFX_IH_CLIENT_OTHER_STAT_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_DELAY_IND_ADDR 0x4d64 +#define regRLC_SPM_GLOBAL_DELAY_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_DELAY_IND_DATA 0x4d65 +#define regRLC_SPM_GLOBAL_DELAY_IND_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_DELAY_IND_ADDR 0x4d66 +#define regRLC_SPM_SE_DELAY_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_DELAY_IND_DATA 0x4d67 +#define regRLC_SPM_SE_DELAY_IND_DATA_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_BLK_EN_MASK_IND_ADDR 0x4d68 +#define regRLC_SPM_GLOBAL_BLK_EN_MASK_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_GLOBAL_BLK_EN_MASK_IND_DATA 0x4d69 +#define regRLC_SPM_GLOBAL_BLK_EN_MASK_IND_DATA_BASE_IDX 1 +#define regRLC_SPM_SE_BLK_EN_MASK_IND_ADDR 0x4d6a +#define regRLC_SPM_SE_BLK_EN_MASK_IND_ADDR_BASE_IDX 1 +#define regRLC_SPM_SE_BLK_EN_MASK_IND_DATA 0x4d6b +#define regRLC_SPM_SE_BLK_EN_MASK_IND_DATA_BASE_IDX 1 +#define regRLC_GFX_IH_22BEAT_STAT 0x4d6c +#define regRLC_GFX_IH_22BEAT_STAT_BASE_IDX 1 +#define regRLC_GFX_IH_ARBITER_STAT_22BEAT 0x4d6d +#define regRLC_GFX_IH_ARBITER_STAT_22BEAT_BASE_IDX 1 +#define regRLC_LX6_CNTL 0x4d80 +#define regRLC_LX6_CNTL_BASE_IDX 1 +#define regRLC_LX6_STATUS 0x4d81 +#define regRLC_LX6_STATUS_BASE_IDX 1 +#define regRLC_LX6_FW_STATUS 0x4dcb +#define regRLC_LX6_FW_STATUS_BASE_IDX 1 +#define regRLC_LX6_FW_VERSION 0x4dcc +#define regRLC_LX6_FW_VERSION_BASE_IDX 1 +#define regRLC_XT_CORE_STATUS 0x4dd4 +#define regRLC_XT_CORE_STATUS_BASE_IDX 1 +#define regRLC_XT_CORE_INTERRUPT 0x4dd5 +#define regRLC_XT_CORE_INTERRUPT_BASE_IDX 1 +#define regRLC_XT_CORE_FAULT_INFO 0x4dd6 +#define regRLC_XT_CORE_FAULT_INFO_BASE_IDX 1 +#define regRLC_XT_CORE_ALT_RESET_VEC 0x4dd7 +#define regRLC_XT_CORE_ALT_RESET_VEC_BASE_IDX 1 +#define regRLC_XT_CORE_RESERVED 0x4dd8 +#define regRLC_XT_CORE_RESERVED_BASE_IDX 1 +#define regRLC_XT_INT_VEC_FORCE 0x4dd9 +#define regRLC_XT_INT_VEC_FORCE_BASE_IDX 1 +#define regRLC_XT_INT_VEC_CLEAR 0x4dda +#define regRLC_XT_INT_VEC_CLEAR_BASE_IDX 1 +#define regRLC_XT_INT_VEC_MUX_SEL 0x4ddb +#define regRLC_XT_INT_VEC_MUX_SEL_BASE_IDX 1 +#define regRLC_XT_INT_VEC_MUX_INT_SEL 0x4ddc +#define regRLC_XT_INT_VEC_MUX_INT_SEL_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_SPM_LSB 0x4de4 +#define regRLC_GPU_CLOCK_COUNT_SPM_LSB_BASE_IDX 1 +#define regRLC_GPU_CLOCK_COUNT_SPM_MSB 0x4de5 +#define regRLC_GPU_CLOCK_COUNT_SPM_MSB_BASE_IDX 1 +#define regRLC_SPM_THREAD_TRACE_CTRL 0x4de6 +#define regRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX 1 +#define regRLC_SPP_CAM_ADDR 0x4de8 +#define regRLC_SPP_CAM_ADDR_BASE_IDX 1 +#define regRLC_SPP_CAM_DATA 0x4de9 +#define regRLC_SPP_CAM_DATA_BASE_IDX 1 +#define regRLC_SPP_CAM_EXT_ADDR 0x4dea +#define regRLC_SPP_CAM_EXT_ADDR_BASE_IDX 1 +#define regRLC_SPP_CAM_EXT_DATA 0x4deb +#define regRLC_SPP_CAM_EXT_DATA_BASE_IDX 1 +#define regRLC_CPAXI_DOORBELL_MON_CTRL 0x4df1 +#define regRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX 1 +#define regRLC_CPAXI_DOORBELL_MON_STAT 0x4df2 +#define regRLC_CPAXI_DOORBELL_MON_STAT_BASE_IDX 1 +#define regRLC_CPAXI_DOORBELL_MON_DATA_LSB 0x4df3 +#define regRLC_CPAXI_DOORBELL_MON_DATA_LSB_BASE_IDX 1 +#define regRLC_CPAXI_DOORBELL_MON_DATA_MSB 0x4df4 +#define regRLC_CPAXI_DOORBELL_MON_DATA_MSB_BASE_IDX 1 +#define regRLC_XT_DOORBELL_RANGE 0x4df5 +#define regRLC_XT_DOORBELL_RANGE_BASE_IDX 1 +#define regRLC_XT_DOORBELL_CNTL 0x4df6 +#define regRLC_XT_DOORBELL_CNTL_BASE_IDX 1 +#define regRLC_XT_DOORBELL_STAT 0x4df7 +#define regRLC_XT_DOORBELL_STAT_BASE_IDX 1 +#define regRLC_XT_DOORBELL_0_DATA_LO 0x4df8 +#define regRLC_XT_DOORBELL_0_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_0_DATA_HI 0x4df9 +#define regRLC_XT_DOORBELL_0_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_1_DATA_LO 0x4dfa +#define regRLC_XT_DOORBELL_1_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_1_DATA_HI 0x4dfb +#define regRLC_XT_DOORBELL_1_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_2_DATA_LO 0x4dfc +#define regRLC_XT_DOORBELL_2_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_2_DATA_HI 0x4dfd +#define regRLC_XT_DOORBELL_2_DATA_HI_BASE_IDX 1 +#define regRLC_XT_DOORBELL_3_DATA_LO 0x4dfe +#define regRLC_XT_DOORBELL_3_DATA_LO_BASE_IDX 1 +#define regRLC_XT_DOORBELL_3_DATA_HI 0x4dff +#define regRLC_XT_DOORBELL_3_DATA_HI_BASE_IDX 1 +#define regRLC_MEM_SLP_CNTL 0x4e00 +#define regRLC_MEM_SLP_CNTL_BASE_IDX 1 +#define regRLC_RLCV_SAFE_MODE 0x4e02 +#define regRLC_RLCV_SAFE_MODE_BASE_IDX 1 +#define regRLC_SMU_SAFE_MODE 0x4e03 +#define regRLC_SMU_SAFE_MODE_BASE_IDX 1 +#define regRLC_RLCV_COMMAND 0x4e04 +#define regRLC_RLCV_COMMAND_BASE_IDX 1 +#define regRLC_SMU_MESSAGE 0x4e05 +#define regRLC_SMU_MESSAGE_BASE_IDX 1 +#define regRLC_SMU_MESSAGE_1 0x4e06 +#define regRLC_SMU_MESSAGE_1_BASE_IDX 1 +#define regRLC_SMU_MESSAGE_2 0x4e07 +#define regRLC_SMU_MESSAGE_2_BASE_IDX 1 +#define regRLC_SRM_GPM_COMMAND 0x4e08 +#define regRLC_SRM_GPM_COMMAND_BASE_IDX 1 +#define regRLC_SRM_GPM_ABORT 0x4e09 +#define regRLC_SRM_GPM_ABORT_BASE_IDX 1 +#define regRLC_SMU_COMMAND 0x4e0a +#define regRLC_SMU_COMMAND_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_1 0x4e0b +#define regRLC_SMU_ARGUMENT_1_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_2 0x4e0c +#define regRLC_SMU_ARGUMENT_2_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_3 0x4e0d +#define regRLC_SMU_ARGUMENT_3_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_4 0x4e0e +#define regRLC_SMU_ARGUMENT_4_BASE_IDX 1 +#define regRLC_SMU_ARGUMENT_5 0x4e0f +#define regRLC_SMU_ARGUMENT_5_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_ADDR_HI 0x4e10 +#define regRLC_IMU_BOOTLOAD_ADDR_HI_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_ADDR_LO 0x4e11 +#define regRLC_IMU_BOOTLOAD_ADDR_LO_BASE_IDX 1 +#define regRLC_IMU_BOOTLOAD_SIZE 0x4e12 +#define regRLC_IMU_BOOTLOAD_SIZE_BASE_IDX 1 +#define regRLC_IMU_MISC 0x4e16 +#define regRLC_IMU_MISC_BASE_IDX 1 +#define regRLC_IMU_RESET_VECTOR 0x4e17 +#define regRLC_IMU_RESET_VECTOR_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcsdec +// base address: 0x3b980 +#define regRLC_RLCS_DEC_START 0x4e60 +#define regRLC_RLCS_DEC_START_BASE_IDX 1 +#define regRLC_RLCS_DEC_DUMP_ADDR 0x4e61 +#define regRLC_RLCS_DEC_DUMP_ADDR_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_1 0x4e62 +#define regRLC_RLCS_EXCEPTION_REG_1_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_2 0x4e63 +#define regRLC_RLCS_EXCEPTION_REG_2_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_3 0x4e64 +#define regRLC_RLCS_EXCEPTION_REG_3_BASE_IDX 1 +#define regRLC_RLCS_EXCEPTION_REG_4 0x4e65 +#define regRLC_RLCS_EXCEPTION_REG_4_BASE_IDX 1 +#define regRLC_RLCS_FENCE_CNTL 0x4e66 +#define regRLC_RLCS_FENCE_CNTL_BASE_IDX 1 +#define regRLC_RLCS_CGCG_REQUEST 0x4e67 +#define regRLC_RLCS_CGCG_REQUEST_BASE_IDX 1 +#define regRLC_RLCS_CGCG_STATUS 0x4e68 +#define regRLC_RLCS_CGCG_STATUS_BASE_IDX 1 +#define regRLC_RLCS_SOC_DS_CNTL 0x4e69 +#define regRLC_RLCS_SOC_DS_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GFX_DS_CNTL 0x4e6a +#define regRLC_RLCS_GFX_DS_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL 0x4e6b +#define regRLC_RLCS_GFX_DS_ALLOW_MASK_CNTL_BASE_IDX 1 +#define regRLC_GPM_STAT 0x4e6c +#define regRLC_GPM_STAT_BASE_IDX 1 +#define regRLC_RLCS_GPM_STAT 0x4e6c +#define regRLC_RLCS_GPM_STAT_BASE_IDX 1 +#define regRLC_RLCS_ABORTED_PD_SEQUENCE 0x4e6d +#define regRLC_RLCS_ABORTED_PD_SEQUENCE_BASE_IDX 1 +#define regRLC_RLCS_IOV_CMD_STATUS 0x4e6e +#define regRLC_RLCS_IOV_CMD_STATUS_BASE_IDX 1 +#define regRLC_RLCS_IOV_CNTX_LOC_SIZE 0x4e6f +#define regRLC_RLCS_IOV_CNTX_LOC_SIZE_BASE_IDX 1 +#define regRLC_RLCS_IOV_SCH_BLOCK 0x4e70 +#define regRLC_RLCS_IOV_SCH_BLOCK_BASE_IDX 1 +#define regRLC_RLCS_IOV_VM_BUSY_STATUS 0x4e71 +#define regRLC_RLCS_IOV_VM_BUSY_STATUS_BASE_IDX 1 +#define regRLC_RLCS_GPM_STAT_2 0x4e72 +#define regRLC_RLCS_GPM_STAT_2_BASE_IDX 1 +#define regRLC_RLCS_GRBM_SOFT_RESET 0x4e73 +#define regRLC_RLCS_GRBM_SOFT_RESET_BASE_IDX 1 +#define regRLC_RLCS_PG_CHANGE_STATUS 0x4e74 +#define regRLC_RLCS_PG_CHANGE_STATUS_BASE_IDX 1 +#define regRLC_RLCS_PG_CHANGE_READ 0x4e75 +#define regRLC_RLCS_PG_CHANGE_READ_BASE_IDX 1 +#define regRLC_RLCS_IH_SEMAPHORE 0x4e76 +#define regRLC_RLCS_IH_SEMAPHORE_BASE_IDX 1 +#define regRLC_RLCS_IH_COOKIE_SEMAPHORE 0x4e77 +#define regRLC_RLCS_IH_COOKIE_SEMAPHORE_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_CTRL_1 0x4e78 +#define regRLC_RLCS_CP_INT_CTRL_1_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_CTRL_2 0x4e79 +#define regRLC_RLCS_CP_INT_CTRL_2_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_INFO_1 0x4e7a +#define regRLC_RLCS_CP_INT_INFO_1_BASE_IDX 1 +#define regRLC_RLCS_CP_INT_INFO_2 0x4e7b +#define regRLC_RLCS_CP_INT_INFO_2_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_CTRL 0x4e7c +#define regRLC_RLCS_SPM_INT_CTRL_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_INFO_1 0x4e7d +#define regRLC_RLCS_SPM_INT_INFO_1_BASE_IDX 1 +#define regRLC_RLCS_SPM_INT_INFO_2 0x4e7e +#define regRLC_RLCS_SPM_INT_INFO_2_BASE_IDX 1 +#define regRLC_RLCS_DSM_TRIG 0x4e7f +#define regRLC_RLCS_DSM_TRIG_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_STATUS 0x4e80 +#define regRLC_RLCS_BOOTLOAD_STATUS_BASE_IDX 1 +#define regRLC_RLCS_GRBM_IDLE_BUSY_STAT 0x4e81 +#define regRLC_RLCS_GRBM_IDLE_BUSY_STAT_BASE_IDX 1 +#define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL 0x4e82 +#define regRLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL_BASE_IDX 1 +#define regRLC_RLCS_CMP_IDLE_CNTL 0x4e83 +#define regRLC_RLCS_CMP_IDLE_CNTL_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_0 0x4e84 +#define regRLC_RLCS_GENERAL_0_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_1 0x4e85 +#define regRLC_RLCS_GENERAL_1_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_2 0x4e86 +#define regRLC_RLCS_GENERAL_2_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_3 0x4e87 +#define regRLC_RLCS_GENERAL_3_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_4 0x4e88 +#define regRLC_RLCS_GENERAL_4_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_5 0x4e89 +#define regRLC_RLCS_GENERAL_5_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_6 0x4e8a +#define regRLC_RLCS_GENERAL_6_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_7 0x4e8b +#define regRLC_RLCS_GENERAL_7_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_8 0x4e8c +#define regRLC_RLCS_GENERAL_8_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_9 0x4e8d +#define regRLC_RLCS_GENERAL_9_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_10 0x4e8e +#define regRLC_RLCS_GENERAL_10_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_11 0x4e8f +#define regRLC_RLCS_GENERAL_11_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_12 0x4e90 +#define regRLC_RLCS_GENERAL_12_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_13 0x4e91 +#define regRLC_RLCS_GENERAL_13_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_14 0x4e92 +#define regRLC_RLCS_GENERAL_14_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_15 0x4e93 +#define regRLC_RLCS_GENERAL_15_BASE_IDX 1 +#define regRLC_RLCS_GENERAL_16 0x4e94 +#define regRLC_RLCS_GENERAL_16_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_1 0x4ec1 +#define regRLC_RLCS_AUXILIARY_REG_1_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_2 0x4ec2 +#define regRLC_RLCS_AUXILIARY_REG_2_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_3 0x4ec3 +#define regRLC_RLCS_AUXILIARY_REG_3_BASE_IDX 1 +#define regRLC_RLCS_AUXILIARY_REG_4 0x4ec4 +#define regRLC_RLCS_AUXILIARY_REG_4_BASE_IDX 1 +#define regRLC_RLCS_SPM_SQTT_MODE 0x4ec5 +#define regRLC_RLCS_SPM_SQTT_MODE_BASE_IDX 1 +#define regRLC_RLCS_CP_DMA_SRCID_OVER 0x4ec6 +#define regRLC_RLCS_CP_DMA_SRCID_OVER_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS1 0x4ec7 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS1_BASE_IDX 1 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS2 0x4ec8 +#define regRLC_RLCS_BOOTLOAD_ID_STATUS2_BASE_IDX 1 +#define regRLC_RLCS_KMD_LOG_CNTL1 0x4ec9 +#define regRLC_RLCS_KMD_LOG_CNTL1_BASE_IDX 1 +#define regRLC_RLCS_KMD_LOG_CNTL2 0x4eca +#define regRLC_RLCS_KMD_LOG_CNTL2_BASE_IDX 1 +#define regRLC_RLCS_GPM_LEGACY_INT_STAT 0x4ecb +#define regRLC_RLCS_GPM_LEGACY_INT_STAT_BASE_IDX 1 +#define regRLC_RLCS_GPM_LEGACY_INT_DISABLE 0x4ecc +#define regRLC_RLCS_GPM_LEGACY_INT_DISABLE_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_0 0x4ed3 +#define regRLC_RLCS_GCR_DATA_0_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_1 0x4ed4 +#define regRLC_RLCS_GCR_DATA_1_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_2 0x4ed5 +#define regRLC_RLCS_GCR_DATA_2_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_3 0x4ed6 +#define regRLC_RLCS_GCR_DATA_3_BASE_IDX 1 +#define regRLC_RLCS_GCR_DATA_4 0x4ed7 +#define regRLC_RLCS_GCR_DATA_4_BASE_IDX 1 +#define regRLC_RLCS_GCR_STATUS 0x4ed8 +#define regRLC_RLCS_GCR_STATUS_BASE_IDX 1 +#define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE 0x4ed9 +#define regRLC_RLCS_PERFMON_CLK_CNTL_UCODE_BASE_IDX 1 +#define regRLC_RLCS_UTCL2_CNTL 0x4eda +#define regRLC_RLCS_UTCL2_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA0 0x4edb +#define regRLC_RLCS_IMU_RLC_MSG_DATA0_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA1 0x4edc +#define regRLC_RLCS_IMU_RLC_MSG_DATA1_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA2 0x4edd +#define regRLC_RLCS_IMU_RLC_MSG_DATA2_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA3 0x4ede +#define regRLC_RLCS_IMU_RLC_MSG_DATA3_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_DATA4 0x4edf +#define regRLC_RLCS_IMU_RLC_MSG_DATA4_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_CONTROL 0x4ee0 +#define regRLC_RLCS_IMU_RLC_MSG_CONTROL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MSG_CNTL 0x4ee1 +#define regRLC_RLCS_IMU_RLC_MSG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_DATA0 0x4ee2 +#define regRLC_RLCS_RLC_IMU_MSG_DATA0_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_CONTROL 0x4ee3 +#define regRLC_RLCS_RLC_IMU_MSG_CONTROL_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_MSG_CNTL 0x4ee4 +#define regRLC_RLCS_RLC_IMU_MSG_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_MUTEX_CNTL 0x4ee5 +#define regRLC_RLCS_IMU_RLC_MUTEX_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_RLC_STATUS 0x4ee6 +#define regRLC_RLCS_IMU_RLC_STATUS_BASE_IDX 1 +#define regRLC_RLCS_RLC_IMU_STATUS 0x4ee7 +#define regRLC_RLCS_RLC_IMU_STATUS_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_DATA_1 0x4ee8 +#define regRLC_RLCS_IMU_RAM_DATA_1_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_1_LSB 0x4ee9 +#define regRLC_RLCS_IMU_RAM_ADDR_1_LSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_1_MSB 0x4eea +#define regRLC_RLCS_IMU_RAM_ADDR_1_MSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_DATA_0 0x4eeb +#define regRLC_RLCS_IMU_RAM_DATA_0_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_0_LSB 0x4eec +#define regRLC_RLCS_IMU_RAM_ADDR_0_LSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_ADDR_0_MSB 0x4eed +#define regRLC_RLCS_IMU_RAM_ADDR_0_MSB_BASE_IDX 1 +#define regRLC_RLCS_IMU_RAM_CNTL 0x4eee +#define regRLC_RLCS_IMU_RAM_CNTL_BASE_IDX 1 +#define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE 0x4eef +#define regRLC_RLCS_IMU_GFX_DOORBELL_FENCE_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_CNTL_1 0x4ef1 +#define regRLC_RLCS_SDMA_INT_CNTL_1_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_CNTL_2 0x4ef2 +#define regRLC_RLCS_SDMA_INT_CNTL_2_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_STAT 0x4ef3 +#define regRLC_RLCS_SDMA_INT_STAT_BASE_IDX 1 +#define regRLC_RLCS_SDMA_INT_INFO 0x4ef4 +#define regRLC_RLCS_SDMA_INT_INFO_BASE_IDX 1 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_0 0x4ef5 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_0_BASE_IDX 1 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_1 0x4ef6 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_1_BASE_IDX 1 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_2 0x4ef7 +#define regRLC_RLCS_GFX_MEM_POWER_CTRL_2_BASE_IDX 1 +#define regRLC_RLCS_IH_CTRL_1 0x4f01 +#define regRLC_RLCS_IH_CTRL_1_BASE_IDX 1 +#define regRLC_RLCS_IH_CTRL_2 0x4f02 +#define regRLC_RLCS_IH_CTRL_2_BASE_IDX 1 +#define regRLC_RLCS_IH_CTRL_3 0x4f03 +#define regRLC_RLCS_IH_CTRL_3_BASE_IDX 1 +#define regRLC_RLCS_IH_STATUS 0x4f04 +#define regRLC_RLCS_IH_STATUS_BASE_IDX 1 +#define regRLC_RLCS_FED_STATUS 0x4f05 +#define regRLC_RLCS_FED_STATUS_BASE_IDX 1 +#define regRLC_RLCS_FED_RESP 0x4f06 +#define regRLC_RLCS_FED_RESP_BASE_IDX 1 +#define regRLC_RLCS_FED_INT_MASK 0x4f07 +#define regRLC_RLCS_FED_INT_MASK_BASE_IDX 1 +#define regRLC_RLCS_MEM_FED 0x4f08 +#define regRLC_RLCS_MEM_FED_BASE_IDX 1 +#define regRLC_RLCS_SE_PWR_CTRL 0x4f09 +#define regRLC_RLCS_SE_PWR_CTRL_BASE_IDX 1 +#define regRLC_UTCL2_FED_STATUS_SNAP 0x4f0a +#define regRLC_UTCL2_FED_STATUS_SNAP_BASE_IDX 1 +#define regRLC_SE0_FED_STATUS_SNAP 0x4f0b +#define regRLC_SE0_FED_STATUS_SNAP_BASE_IDX 1 +#define regRLC_SE1_FED_STATUS_SNAP 0x4f0c +#define regRLC_SE1_FED_STATUS_SNAP_BASE_IDX 1 +#define regRLC_CANE_FED_STATUS_SNAP 0x4f0d +#define regRLC_CANE_FED_STATUS_SNAP_BASE_IDX 1 +#define regRLC_CONSOLIDATED_FED_STS 0x4f0e +#define regRLC_CONSOLIDATED_FED_STS_BASE_IDX 1 +#define regRLC_HOST_FED_ACK 0x4f0f +#define regRLC_HOST_FED_ACK_BASE_IDX 1 +#define regRLC_RLCS_SB_RLC_ROM_STATUS 0x4f71 +#define regRLC_RLCS_SB_RLC_ROM_STATUS_BASE_IDX 1 +#define regRLC_RLCS_SB_ROM_STATUS 0x4f72 +#define regRLC_RLCS_SB_ROM_STATUS_BASE_IDX 1 +#define regRLC_RLCS_UTCL2_BUSY_CNTL 0x4f73 +#define regRLC_RLCS_UTCL2_BUSY_CNTL_BASE_IDX 1 +#define regRLC_RLCS_UTCL2_BUSY_STAT 0x4f74 +#define regRLC_RLCS_UTCL2_BUSY_STAT_BASE_IDX 1 +#define regRLC_RLCS_DEC_END 0x4fff +#define regRLC_RLCS_DEC_END_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvfdec_rlc +// base address: 0x2a600 +#define regRLC_SAFE_MODE 0x0980 +#define regRLC_SAFE_MODE_BASE_IDX 1 +#define regRLC_SPM_SAMPLE_CNT 0x0981 +#define regRLC_SPM_SAMPLE_CNT_BASE_IDX 1 +#define regRLC_SPM_MC_CNTL 0x0982 +#define regRLC_SPM_MC_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_CNTL 0x0983 +#define regRLC_SPM_INT_CNTL_BASE_IDX 1 +#define regRLC_SPM_INT_STATUS 0x0984 +#define regRLC_SPM_INT_STATUS_BASE_IDX 1 +#define regRLC_SPM_INT_INFO_1 0x0985 +#define regRLC_SPM_INT_INFO_1_BASE_IDX 1 +#define regRLC_SPM_INT_INFO_2 0x0986 +#define regRLC_SPM_INT_INFO_2_BASE_IDX 1 +#define regRLC_CSIB_ADDR_LO 0x0987 +#define regRLC_CSIB_ADDR_LO_BASE_IDX 1 +#define regRLC_CSIB_ADDR_HI 0x0988 +#define regRLC_CSIB_ADDR_HI_BASE_IDX 1 +#define regRLC_CSIB_LENGTH 0x0989 +#define regRLC_CSIB_LENGTH_BASE_IDX 1 +#define regRLC_CP_SCHEDULERS 0x098a +#define regRLC_CP_SCHEDULERS_BASE_IDX 1 +#define regRLC_CP_EOF_INT 0x098b +#define regRLC_CP_EOF_INT_BASE_IDX 1 +#define regRLC_CP_EOF_INT_CNTL 0x098c +#define regRLC_CP_EOF_INT_CNTL_BASE_IDX 1 +#define regRLC_SPARE_INT_0 0x098d +#define regRLC_SPARE_INT_0_BASE_IDX 1 +#define regRLC_SPARE_INT_1 0x098e +#define regRLC_SPARE_INT_1_BASE_IDX 1 +#define regRLC_SPARE_INT_2 0x098f +#define regRLC_SPARE_INT_2_BASE_IDX 1 +#define regRLC_RLCV_SPARE_INT_1 0x0992 +#define regRLC_RLCV_SPARE_INT_1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pwrdec +// base address: 0x3c000 +#define regGRBMX_GLARB_BUSY_MASK 0x504d +#define regGRBMX_GLARB_BUSY_MASK_BASE_IDX 1 +#define regCGTT_IA_CLK_CTRL 0x5085 +#define regCGTT_IA_CLK_CTRL_BASE_IDX 1 +#define regCGTT_WD_CLK_CTRL 0x5086 +#define regCGTT_WD_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CP_CLK_CTRL 0x50b0 +#define regCGTT_CP_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CPF_CLK_CTRL 0x50b1 +#define regCGTT_CPF_CLK_CTRL_BASE_IDX 1 +#define regCGTT_CPC_CLK_CTRL 0x50b2 +#define regCGTT_CPC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_RLC_CLK_CTRL 0x50b5 +#define regCGTT_RLC_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_GCR_CTRL 0x50c2 +#define regGFX_ICG_GCR_CTRL_BASE_IDX 1 +#define regGC_EA_CPWD_ICG_CTRL 0x50c6 +#define regGC_EA_CPWD_ICG_CTRL_BASE_IDX 1 +#define regGFX_ICG_GC_CAC_CLK_CTRL 0x50d8 +#define regGFX_ICG_GC_CAC_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_GRBM_CTRL 0x50e0 +#define regGFX_ICG_GRBM_CTRL_BASE_IDX 1 +#define regCC_GC_HBM_DISABLE 0x50e1 +#define regCC_GC_HBM_DISABLE_BASE_IDX 1 +#define regGRBMX_LPDDR_DISABLE_0 0x50e2 +#define regGRBMX_LPDDR_DISABLE_0_BASE_IDX 1 +#define regGRBMX_LPDDR_DISABLE_1 0x50e3 +#define regGRBMX_LPDDR_DISABLE_1_BASE_IDX 1 +#define regGLARBI_GLARBR_MGCG_OVERRIDE 0x50f4 +#define regGLARBI_GLARBR_MGCG_OVERRIDE_BASE_IDX 1 +#define regICG_GLARBA_CTRL 0x50f5 +#define regICG_GLARBA_CTRL_BASE_IDX 1 +#define regICG_GLARBC_CLK_CTRL 0x50f6 +#define regICG_GLARBC_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pspdec +// base address: 0x3f000 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0 0x5c61 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0_BASE_IDX 1 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1 0x5c62 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1_BASE_IDX 1 +#define regGC_EA_CPWD_SDP_ERR_CTRL 0x5c64 +#define regGC_EA_CPWD_SDP_ERR_CTRL_BASE_IDX 1 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2 0x5c66 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2_BASE_IDX 1 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3 0x5c67 +#define regGC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3_BASE_IDX 1 +#define regGRBM_SRCID_CAM_INDEX 0x5e00 +#define regGRBM_SRCID_CAM_INDEX_BASE_IDX 1 +#define regGRBM_SRCID_CAM_DATA 0x5e01 +#define regGRBM_SRCID_CAM_DATA_BASE_IDX 1 +#define regGRBM_IOV_RANGE_ENABLE 0x5e06 +#define regGRBM_IOV_RANGE_ENABLE_BASE_IDX 1 +#define regGRBM_IOV_RANGE_READ_BLOCK_ENABLE 0x5e08 +#define regGRBM_IOV_RANGE_READ_BLOCK_ENABLE_BASE_IDX 1 +#define regGRBM_SEC_CNTL 0x5e0d +#define regGRBM_SEC_CNTL_BASE_IDX 1 +#define regGRBM_IOV_SPARE_RANGE_START 0x5e0e +#define regGRBM_IOV_SPARE_RANGE_START_BASE_IDX 1 +#define regGRBM_IOV_SPARE_RANGE_END 0x5e0f +#define regGRBM_IOV_SPARE_RANGE_END_BASE_IDX 1 +#define regGRBM_CAM_INDEX 0x5e10 +#define regGRBM_CAM_INDEX_BASE_IDX 1 +#define regGRBM_CAM_DATA 0x5e11 +#define regGRBM_CAM_DATA_BASE_IDX 1 +#define regGRBM_CAM_DATA_UPPER 0x5e12 +#define regGRBM_CAM_DATA_UPPER_BASE_IDX 1 +#define regRLC_REG_SEC_INT_STATUS 0x5f3d +#define regRLC_REG_SEC_INT_STATUS_BASE_IDX 1 +#define regRLC_FWL_FIRST_VIOL_ADDR 0x5f3e +#define regRLC_FWL_FIRST_VIOL_ADDR_BASE_IDX 1 +#define regRLC_FWL_FIRST_VIOL_ADDR_HI 0x5f3f +#define regRLC_FWL_FIRST_VIOL_ADDR_HI_BASE_IDX 1 +#define regRLC_UTC_BYPASS_CNTL 0x5f42 +#define regRLC_UTC_BYPASS_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cp_pspdec +// base address: 0x3f000 +#define regCP_MES_DM_INDEX_ADDR 0x5c00 +#define regCP_MES_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_MES_DM_INDEX_DATA 0x5c01 +#define regCP_MES_DM_INDEX_DATA_BASE_IDX 1 +#define regCP_MEC_DM_INDEX_ADDR 0x5c02 +#define regCP_MEC_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_MEC_DM_INDEX_DATA 0x5c03 +#define regCP_MEC_DM_INDEX_DATA_BASE_IDX 1 +#define regCP_GFX_RS64_DM_INDEX_ADDR 0x5c04 +#define regCP_GFX_RS64_DM_INDEX_ADDR_BASE_IDX 1 +#define regCP_GFX_RS64_DM_INDEX_DATA 0x5c05 +#define regCP_GFX_RS64_DM_INDEX_DATA_BASE_IDX 1 +#define regCPG_PSP_DEBUG 0x5c10 +#define regCPG_PSP_DEBUG_BASE_IDX 1 +#define regCPC_PSP_DEBUG 0x5c11 +#define regCPC_PSP_DEBUG_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_ch_pwrdec +// base address: 0x3c3b0 +#define regCHI_CHR_MGCG_OVERRIDE 0x50ec +#define regCHI_CHR_MGCG_OVERRIDE_BASE_IDX 1 +#define regICG_CHA_CTRL 0x50ed +#define regICG_CHA_CTRL_BASE_IDX 1 +#define regICG_CHC_CLK_CTRL 0x50ee +#define regICG_CHC_CLK_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gfx_imu_cpwd_gfx_imudec +// base address: 0x38000 +#define regGFX_IMU_C2PMSG_0 0x4000 +#define regGFX_IMU_C2PMSG_0_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_1 0x4001 +#define regGFX_IMU_C2PMSG_1_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_2 0x4002 +#define regGFX_IMU_C2PMSG_2_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_3 0x4003 +#define regGFX_IMU_C2PMSG_3_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_4 0x4004 +#define regGFX_IMU_C2PMSG_4_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_5 0x4005 +#define regGFX_IMU_C2PMSG_5_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_6 0x4006 +#define regGFX_IMU_C2PMSG_6_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_7 0x4007 +#define regGFX_IMU_C2PMSG_7_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_8 0x4008 +#define regGFX_IMU_C2PMSG_8_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_9 0x4009 +#define regGFX_IMU_C2PMSG_9_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_10 0x400a +#define regGFX_IMU_C2PMSG_10_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_11 0x400b +#define regGFX_IMU_C2PMSG_11_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_12 0x400c +#define regGFX_IMU_C2PMSG_12_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_13 0x400d +#define regGFX_IMU_C2PMSG_13_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_14 0x400e +#define regGFX_IMU_C2PMSG_14_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_15 0x400f +#define regGFX_IMU_C2PMSG_15_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_16 0x4010 +#define regGFX_IMU_C2PMSG_16_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_17 0x4011 +#define regGFX_IMU_C2PMSG_17_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_18 0x4012 +#define regGFX_IMU_C2PMSG_18_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_19 0x4013 +#define regGFX_IMU_C2PMSG_19_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_20 0x4014 +#define regGFX_IMU_C2PMSG_20_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_21 0x4015 +#define regGFX_IMU_C2PMSG_21_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_22 0x4016 +#define regGFX_IMU_C2PMSG_22_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_23 0x4017 +#define regGFX_IMU_C2PMSG_23_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_24 0x4018 +#define regGFX_IMU_C2PMSG_24_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_25 0x4019 +#define regGFX_IMU_C2PMSG_25_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_26 0x401a +#define regGFX_IMU_C2PMSG_26_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_27 0x401b +#define regGFX_IMU_C2PMSG_27_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_28 0x401c +#define regGFX_IMU_C2PMSG_28_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_29 0x401d +#define regGFX_IMU_C2PMSG_29_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_30 0x401e +#define regGFX_IMU_C2PMSG_30_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_31 0x401f +#define regGFX_IMU_C2PMSG_31_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_32 0x4020 +#define regGFX_IMU_C2PMSG_32_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_33 0x4021 +#define regGFX_IMU_C2PMSG_33_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_34 0x4022 +#define regGFX_IMU_C2PMSG_34_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_35 0x4023 +#define regGFX_IMU_C2PMSG_35_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_36 0x4024 +#define regGFX_IMU_C2PMSG_36_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_37 0x4025 +#define regGFX_IMU_C2PMSG_37_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_38 0x4026 +#define regGFX_IMU_C2PMSG_38_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_39 0x4027 +#define regGFX_IMU_C2PMSG_39_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_40 0x4028 +#define regGFX_IMU_C2PMSG_40_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_41 0x4029 +#define regGFX_IMU_C2PMSG_41_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_42 0x402a +#define regGFX_IMU_C2PMSG_42_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_43 0x402b +#define regGFX_IMU_C2PMSG_43_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_44 0x402c +#define regGFX_IMU_C2PMSG_44_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_45 0x402d +#define regGFX_IMU_C2PMSG_45_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_46 0x402e +#define regGFX_IMU_C2PMSG_46_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_47 0x402f +#define regGFX_IMU_C2PMSG_47_BASE_IDX 1 +#define regGFX_IMU_MSG_FLAGS 0x403f +#define regGFX_IMU_MSG_FLAGS_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL0 0x4040 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL0_BASE_IDX 1 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL1 0x4041 +#define regGFX_IMU_C2PMSG_ACCESS_CTRL1_BASE_IDX 1 +#define regGFX_IMU_PWRMGT_IRQ_CTRL 0x4042 +#define regGFX_IMU_PWRMGT_IRQ_CTRL_BASE_IDX 1 +#define regGFX_IMU_MP1_MUTEX 0x4043 +#define regGFX_IMU_MP1_MUTEX_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_4 0x4046 +#define regGFX_IMU_RLC_DATA_4_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_3 0x4047 +#define regGFX_IMU_RLC_DATA_3_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_2 0x4048 +#define regGFX_IMU_RLC_DATA_2_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_1 0x4049 +#define regGFX_IMU_RLC_DATA_1_BASE_IDX 1 +#define regGFX_IMU_RLC_DATA_0 0x404a +#define regGFX_IMU_RLC_DATA_0_BASE_IDX 1 +#define regGFX_IMU_RLC_CMD 0x404b +#define regGFX_IMU_RLC_CMD_BASE_IDX 1 +#define regGFX_IMU_RLC_MUTEX 0x404c +#define regGFX_IMU_RLC_MUTEX_BASE_IDX 1 +#define regGFX_IMU_RLC_MSG_STATUS 0x404f +#define regGFX_IMU_RLC_MSG_STATUS_BASE_IDX 1 +#define regRLC_GFX_IMU_DATA_0 0x4052 +#define regRLC_GFX_IMU_DATA_0_BASE_IDX 1 +#define regRLC_GFX_IMU_CMD 0x4053 +#define regRLC_GFX_IMU_CMD_BASE_IDX 1 +#define regGFX_IMU_RLC_STATUS 0x4054 +#define regGFX_IMU_RLC_STATUS_BASE_IDX 1 +#define regGFX_IMU_STATUS 0x4055 +#define regGFX_IMU_STATUS_BASE_IDX 1 +#define regGFX_IMU_SOC_DATA 0x4059 +#define regGFX_IMU_SOC_DATA_BASE_IDX 1 +#define regGFX_IMU_SOC_ADDR 0x405a +#define regGFX_IMU_SOC_ADDR_BASE_IDX 1 +#define regGFX_IMU_SOC_REQ 0x405b +#define regGFX_IMU_SOC_REQ_BASE_IDX 1 +#define regGFX_IMU_VF_CTRL 0x405c +#define regGFX_IMU_VF_CTRL_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_0 0x4068 +#define regGFX_IMU_SCRATCH_0_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_1 0x4069 +#define regGFX_IMU_SCRATCH_1_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_2 0x406a +#define regGFX_IMU_SCRATCH_2_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_3 0x406b +#define regGFX_IMU_SCRATCH_3_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_4 0x406c +#define regGFX_IMU_SCRATCH_4_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_5 0x406d +#define regGFX_IMU_SCRATCH_5_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_6 0x406e +#define regGFX_IMU_SCRATCH_6_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_7 0x406f +#define regGFX_IMU_SCRATCH_7_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_8 0x4070 +#define regGFX_IMU_SCRATCH_8_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_9 0x4071 +#define regGFX_IMU_SCRATCH_9_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_10 0x4072 +#define regGFX_IMU_SCRATCH_10_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_11 0x4073 +#define regGFX_IMU_SCRATCH_11_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_12 0x4074 +#define regGFX_IMU_SCRATCH_12_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_13 0x4075 +#define regGFX_IMU_SCRATCH_13_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_14 0x4076 +#define regGFX_IMU_SCRATCH_14_BASE_IDX 1 +#define regGFX_IMU_SCRATCH_15 0x4077 +#define regGFX_IMU_SCRATCH_15_BASE_IDX 1 +#define regGFX_IMU_FW_GTS_LO 0x4078 +#define regGFX_IMU_FW_GTS_LO_BASE_IDX 1 +#define regGFX_IMU_FW_GTS_HI 0x4079 +#define regGFX_IMU_FW_GTS_HI_BASE_IDX 1 +#define regGFX_IMU_GTS_OFFSET_LO 0x407a +#define regGFX_IMU_GTS_OFFSET_LO_BASE_IDX 1 +#define regGFX_IMU_GTS_OFFSET_HI 0x407b +#define regGFX_IMU_GTS_OFFSET_HI_BASE_IDX 1 +#define regGFX_IMU_RLC_GTS_OFFSET_LO 0x407c +#define regGFX_IMU_RLC_GTS_OFFSET_LO_BASE_IDX 1 +#define regGFX_IMU_RLC_GTS_OFFSET_HI 0x407d +#define regGFX_IMU_RLC_GTS_OFFSET_HI_BASE_IDX 1 +#define regGFX_IMU_CORE_INT_STATUS 0x407f +#define regGFX_IMU_CORE_INT_STATUS_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_MASK 0x4080 +#define regGFX_IMU_PIC_INT_MASK_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_LVL 0x4081 +#define regGFX_IMU_PIC_INT_LVL_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_EDGE 0x4082 +#define regGFX_IMU_PIC_INT_EDGE_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_0 0x4083 +#define regGFX_IMU_PIC_INT_PRI_0_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_1 0x4084 +#define regGFX_IMU_PIC_INT_PRI_1_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_2 0x4085 +#define regGFX_IMU_PIC_INT_PRI_2_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_3 0x4086 +#define regGFX_IMU_PIC_INT_PRI_3_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_4 0x4087 +#define regGFX_IMU_PIC_INT_PRI_4_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_5 0x4088 +#define regGFX_IMU_PIC_INT_PRI_5_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_6 0x4089 +#define regGFX_IMU_PIC_INT_PRI_6_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_PRI_7 0x408a +#define regGFX_IMU_PIC_INT_PRI_7_BASE_IDX 1 +#define regGFX_IMU_PIC_INT_STATUS 0x408b +#define regGFX_IMU_PIC_INT_STATUS_BASE_IDX 1 +#define regGFX_IMU_PIC_INTR 0x408c +#define regGFX_IMU_PIC_INTR_BASE_IDX 1 +#define regGFX_IMU_PIC_INTR_ID 0x408d +#define regGFX_IMU_PIC_INTR_ID_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_1 0x4090 +#define regGFX_IMU_IH_CTRL_1_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_2 0x4091 +#define regGFX_IMU_IH_CTRL_2_BASE_IDX 1 +#define regGFX_IMU_IH_CTRL_3 0x4092 +#define regGFX_IMU_IH_CTRL_3_BASE_IDX 1 +#define regGFX_IMU_IH_STATUS 0x4093 +#define regGFX_IMU_IH_STATUS_BASE_IDX 1 +#define regGFX_IMU_FUSESTRAP 0x4094 +#define regGFX_IMU_FUSESTRAP_BASE_IDX 1 +#define regGFX_IMU_GFXCLK_BYPASS_CTRL 0x409c +#define regGFX_IMU_GFXCLK_BYPASS_CTRL_BASE_IDX 1 +#define regGFX_IMU_CLK_CTRL 0x409d +#define regGFX_IMU_CLK_CTRL_BASE_IDX 1 +#define regGFX_IMU_DOORBELL_CONTROL 0x409f +#define regGFX_IMU_DOORBELL_CONTROL_BASE_IDX 1 +#define regGFX_IMU_RLC_CG_CTRL 0x40a0 +#define regGFX_IMU_RLC_CG_CTRL_BASE_IDX 1 +#define regGFX_IMU_RLC_THROTTLE_GFX 0x40a1 +#define regGFX_IMU_RLC_THROTTLE_GFX_BASE_IDX 1 +#define regGFX_IMU_RLC_RESET_VECTOR 0x40a2 +#define regGFX_IMU_RLC_RESET_VECTOR_BASE_IDX 1 +#define regGFX_IMU_RLC_OVERRIDE 0x40a3 +#define regGFX_IMU_RLC_OVERRIDE_BASE_IDX 1 +#define regGFX_IMU_DPM_CONTROL 0x40a8 +#define regGFX_IMU_DPM_CONTROL_BASE_IDX 1 +#define regGFX_IMU_DPM_ACC 0x40a9 +#define regGFX_IMU_DPM_ACC_BASE_IDX 1 +#define regGFX_IMU_DPM_REF_COUNTER 0x40aa +#define regGFX_IMU_DPM_REF_COUNTER_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_INDEX 0x40ac +#define regGFX_IMU_RLC_RAM_INDEX_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_ADDR_HIGH 0x40ad +#define regGFX_IMU_RLC_RAM_ADDR_HIGH_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_ADDR_LOW 0x40ae +#define regGFX_IMU_RLC_RAM_ADDR_LOW_BASE_IDX 1 +#define regGFX_IMU_RLC_RAM_DATA 0x40af +#define regGFX_IMU_RLC_RAM_DATA_BASE_IDX 1 +#define regGFX_IMU_FENCE_CTRL 0x40b0 +#define regGFX_IMU_FENCE_CTRL_BASE_IDX 1 +#define regGFX_IMU_FENCE_LOG_INIT 0x40b1 +#define regGFX_IMU_FENCE_LOG_INIT_BASE_IDX 1 +#define regGFX_IMU_FENCE_LOG_ADDR 0x40b2 +#define regGFX_IMU_FENCE_LOG_ADDR_BASE_IDX 1 +#define regGFX_IMU_PROGRAM_CTR 0x40b5 +#define regGFX_IMU_PROGRAM_CTR_BASE_IDX 1 +#define regGFX_IMU_CORE_CTRL 0x40b6 +#define regGFX_IMU_CORE_CTRL_BASE_IDX 1 +#define regGFX_IMU_CORE_STATUS 0x40b7 +#define regGFX_IMU_CORE_STATUS_BASE_IDX 1 +#define regGFX_IMU_PWROKRAW 0x40b8 +#define regGFX_IMU_PWROKRAW_BASE_IDX 1 +#define regGFX_IMU_PWROK 0x40b9 +#define regGFX_IMU_PWROK_BASE_IDX 1 +#define regGFX_IMU_GAP_PWROK 0x40ba +#define regGFX_IMU_GAP_PWROK_BASE_IDX 1 +#define regGFX_IMU_RESETn 0x40bb +#define regGFX_IMU_RESETn_BASE_IDX 1 +#define regGFX_IMU_GFX_RESET_CTRL 0x40bc +#define regGFX_IMU_GFX_RESET_CTRL_BASE_IDX 1 +#define regGFX_IMU_VDCI_RESET_CTRL 0x40be +#define regGFX_IMU_VDCI_RESET_CTRL_BASE_IDX 1 +#define regGFX_IMU_GFX_ISO_CTRL 0x40bf +#define regGFX_IMU_GFX_ISO_CTRL_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CTRL0 0x40c0 +#define regGFX_IMU_TIMER0_CTRL0_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CTRL1 0x40c1 +#define regGFX_IMU_TIMER0_CTRL1_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP_AUTOINC 0x40c2 +#define regGFX_IMU_TIMER0_CMP_AUTOINC_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP_INTEN 0x40c3 +#define regGFX_IMU_TIMER0_CMP_INTEN_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP0 0x40c4 +#define regGFX_IMU_TIMER0_CMP0_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP1 0x40c5 +#define regGFX_IMU_TIMER0_CMP1_BASE_IDX 1 +#define regGFX_IMU_TIMER0_CMP3 0x40c7 +#define regGFX_IMU_TIMER0_CMP3_BASE_IDX 1 +#define regGFX_IMU_TIMER0_VALUE 0x40c8 +#define regGFX_IMU_TIMER0_VALUE_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CTRL0 0x40c9 +#define regGFX_IMU_TIMER1_CTRL0_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CTRL1 0x40ca +#define regGFX_IMU_TIMER1_CTRL1_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP_AUTOINC 0x40cb +#define regGFX_IMU_TIMER1_CMP_AUTOINC_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP_INTEN 0x40cc +#define regGFX_IMU_TIMER1_CMP_INTEN_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP0 0x40cd +#define regGFX_IMU_TIMER1_CMP0_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP1 0x40ce +#define regGFX_IMU_TIMER1_CMP1_BASE_IDX 1 +#define regGFX_IMU_TIMER1_CMP3 0x40d0 +#define regGFX_IMU_TIMER1_CMP3_BASE_IDX 1 +#define regGFX_IMU_TIMER1_VALUE 0x40d1 +#define regGFX_IMU_TIMER1_VALUE_BASE_IDX 1 +#define regGFX_IMU_FUSE_CTRL 0x40e0 +#define regGFX_IMU_FUSE_CTRL_BASE_IDX 1 +#define regGFX_IMU_D_RAM_ADDR 0x40fc +#define regGFX_IMU_D_RAM_ADDR_BASE_IDX 1 +#define regGFX_IMU_D_RAM_DATA 0x40fd +#define regGFX_IMU_D_RAM_DATA_BASE_IDX 1 +#define regGFX_IMU_GFX_IH_GASKET_CTRL 0x40ff +#define regGFX_IMU_GFX_IH_GASKET_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gfx_imu_cpwd_gfx_imu_pspdec +// base address: 0x3fe00 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI 0x5f81 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_HI_BASE_IDX 1 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO 0x5f82 +#define regGFX_IMU_RLC_BOOTLOADER_ADDR_LO_BASE_IDX 1 +#define regGFX_IMU_RLC_BOOTLOADER_SIZE 0x5f83 +#define regGFX_IMU_RLC_BOOTLOADER_SIZE_BASE_IDX 1 +#define regGFX_IMU_I_RAM_ADDR 0x5f90 +#define regGFX_IMU_I_RAM_ADDR_BASE_IDX 1 +#define regGFX_IMU_I_RAM_DATA 0x5f91 +#define regGFX_IMU_I_RAM_DATA_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_grbmhdec +// base address: 0x8180 +#define regGRBMH_CNTL 0x0e00 +#define regGRBMH_CNTL_BASE_IDX 0 +#define regGRBMH_INTF_CNTL 0x0e01 +#define regGRBMH_INTF_CNTL_BASE_IDX 0 +#define regGRBMH_STATUS 0x0e02 +#define regGRBMH_STATUS_BASE_IDX 0 +#define regGRBMH_FGCG0_TARG 0x0e04 +#define regGRBMH_FGCG0_TARG_BASE_IDX 0 +#define regGRBMH_SOFT_RESET 0x0e05 +#define regGRBMH_SOFT_RESET_BASE_IDX 0 +#define regGRBMH_READ_ERROR 0x0e06 +#define regGRBMH_READ_ERROR_BASE_IDX 0 +#define regGRBMH_GFX_CLKEN_CNTL 0x0e0d +#define regGRBMH_GFX_CLKEN_CNTL_BASE_IDX 0 +#define regGRBMH_FGCG2_MISC 0x0e0e +#define regGRBMH_FGCG2_MISC_BASE_IDX 0 +#define regGRBMH_FGCG1_TARGVF 0x0e0f +#define regGRBMH_FGCG1_TARGVF_BASE_IDX 0 +#define regGRBMH_NOWHERE 0x0e10 +#define regGRBMH_NOWHERE_BASE_IDX 0 +#define regGRBMH_INVALID_PIPE 0x0e12 +#define regGRBMH_INVALID_PIPE_BASE_IDX 0 +#define regGRBMH_SYNC 0x0e13 +#define regGRBMH_SYNC_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_padec +// base address: 0x8800 +#define regGE_RATE_CNTL_1 0x0ff4 +#define regGE_RATE_CNTL_1_BASE_IDX 0 +#define regGE_RATE_CNTL_2 0x0ff5 +#define regGE_RATE_CNTL_2_BASE_IDX 0 +#define regCC_GC_SHADER_ARRAY_CONFIG 0x100f +#define regCC_GC_SHADER_ARRAY_CONFIG_BASE_IDX 0 +#define regGE_SE_CNTL_STATUS 0x1011 +#define regGE_SE_CNTL_STATUS_BASE_IDX 0 +#define regGE_SPI_IF_SAFE_REG 0x1018 +#define regGE_SPI_IF_SAFE_REG_BASE_IDX 0 +#define regGE_PA_IF_SAFE_REG 0x1019 +#define regGE_PA_IF_SAFE_REG_BASE_IDX 0 +#define regPA_SU_DEBUG_CNTL 0x1020 +#define regPA_SU_DEBUG_CNTL_BASE_IDX 0 +#define regPA_CL_CNTL_STATUS 0x1024 +#define regPA_CL_CNTL_STATUS_BASE_IDX 0 +#define regPA_CL_ENHANCE 0x1025 +#define regPA_CL_ENHANCE_BASE_IDX 0 +#define regPA_CL_RESET_DEBUG 0x1026 +#define regPA_CL_RESET_DEBUG_BASE_IDX 0 +#define regPA_SU_CNTL_STATUS 0x1034 +#define regPA_SU_CNTL_STATUS_BASE_IDX 0 +#define regPA_SC_FIFO_DEPTH_CNTL 0x1035 +#define regPA_SC_FIFO_DEPTH_CNTL_BASE_IDX 0 +#define regPA_PH_DEBUG_CNTL 0x1082 +#define regPA_PH_DEBUG_CNTL_BASE_IDX 0 +#define regPA_SC_DEBUG_CNTL 0x1096 +#define regPA_SC_DEBUG_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_sqdec +// base address: 0x8c00 +#define regSQ_CONFIG 0x10a0 +#define regSQ_CONFIG_BASE_IDX 0 +#define regSQC_CONFIG 0x10a1 +#define regSQC_CONFIG_BASE_IDX 0 +#define regSQ_RANDOM_WAVE_PRI 0x10a3 +#define regSQ_RANDOM_WAVE_PRI_BASE_IDX 0 +#define regSQG_STATUS 0x10a4 +#define regSQG_STATUS_BASE_IDX 0 +#define regSQ_FIFO_SIZES 0x10a5 +#define regSQ_FIFO_SIZES_BASE_IDX 0 +#define regSQ_DSM_CNTL 0x10a6 +#define regSQ_DSM_CNTL_BASE_IDX 0 +#define regSQ_DSM_CNTL2 0x10a7 +#define regSQ_DSM_CNTL2_BASE_IDX 0 +#define regSQ_PIT_WEIGHT 0x10a8 +#define regSQ_PIT_WEIGHT_BASE_IDX 0 +#define regSQG_THREAD_TRACE_CONFIG 0x10aa +#define regSQG_THREAD_TRACE_CONFIG_BASE_IDX 0 +#define regSP_CONFIG 0x10ab +#define regSP_CONFIG_BASE_IDX 0 +#define regSQ_ARB_CONFIG 0x10ac +#define regSQ_ARB_CONFIG_BASE_IDX 0 +#define regSQ_DYN_VGPR 0x10ad +#define regSQ_DYN_VGPR_BASE_IDX 0 +#define regSQ_SHADER_CYCLES_LO 0x10ae +#define regSQ_SHADER_CYCLES_LO_BASE_IDX 0 +#define regSQ_SHADER_CYCLES_HI 0x10af +#define regSQ_SHADER_CYCLES_HI_BASE_IDX 0 +#define regSQ_DEBUG_HOST_TRAP_STATUS 0x10b6 +#define regSQ_DEBUG_HOST_TRAP_STATUS_BASE_IDX 0 +#define regSQG_GL1X_CTRL 0x10b8 +#define regSQG_GL1X_CTRL_BASE_IDX 0 +#define regSQG_GL1X_STATUS 0x10b9 +#define regSQG_GL1X_STATUS_BASE_IDX 0 +#define regSQG_CONFIG 0x10ba +#define regSQG_CONFIG_BASE_IDX 0 +#define regSQ_PERF_SNAPSHOT_CTRL 0x10bb +#define regSQ_PERF_SNAPSHOT_CTRL_BASE_IDX 0 +#define regCC_GC_SHADER_RATE_CONFIG_1 0x10bc +#define regCC_GC_SHADER_RATE_CONFIG_1_BASE_IDX 0 +#define regSQ_INTERRUPT_AUTO_MASK 0x10be +#define regSQ_INTERRUPT_AUTO_MASK_BASE_IDX 0 +#define regSQ_INTERRUPT_MSG_CTRL 0x10bf +#define regSQ_INTERRUPT_MSG_CTRL_BASE_IDX 0 +#define regSQ_WATCH0_ADDR_H 0x10d0 +#define regSQ_WATCH0_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH0_ADDR_L 0x10d1 +#define regSQ_WATCH0_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH0_CNTL 0x10d2 +#define regSQ_WATCH0_CNTL_BASE_IDX 0 +#define regSQ_WATCH1_ADDR_H 0x10d3 +#define regSQ_WATCH1_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH1_ADDR_L 0x10d4 +#define regSQ_WATCH1_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH1_CNTL 0x10d5 +#define regSQ_WATCH1_CNTL_BASE_IDX 0 +#define regSQ_WATCH2_ADDR_H 0x10d6 +#define regSQ_WATCH2_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH2_ADDR_L 0x10d7 +#define regSQ_WATCH2_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH2_CNTL 0x10d8 +#define regSQ_WATCH2_CNTL_BASE_IDX 0 +#define regSQ_WATCH3_ADDR_H 0x10d9 +#define regSQ_WATCH3_ADDR_H_BASE_IDX 0 +#define regSQ_WATCH3_ADDR_L 0x10da +#define regSQ_WATCH3_ADDR_L_BASE_IDX 0 +#define regSQ_WATCH3_CNTL 0x10db +#define regSQ_WATCH3_CNTL_BASE_IDX 0 +#define regSQG_UTCL0_STATUS 0x10dc +#define regSQG_UTCL0_STATUS_BASE_IDX 0 +#define regSQG_UTCL0_CNTL1 0x10dd +#define regSQG_UTCL0_CNTL1_BASE_IDX 0 +#define regSQG_UTCL0_CNTL2 0x10de +#define regSQG_UTCL0_CNTL2_BASE_IDX 0 +#define regSQG_UTCL0_RETRY 0x10df +#define regSQG_UTCL0_RETRY_BASE_IDX 0 +#define regSQG_VMID_FED_STATUS 0x10e0 +#define regSQG_VMID_FED_STATUS_BASE_IDX 0 +#define regSQG_VMID_FED_CLEAR 0x10e1 +#define regSQG_VMID_FED_CLEAR_BASE_IDX 0 +#define regSQG_SE_PIT_CONTROL 0x10e2 +#define regSQG_SE_PIT_CONTROL_BASE_IDX 0 +#define regSQG_UTCL0_RETRY_TIMER_THRESHOLD_HI 0x10e3 +#define regSQG_UTCL0_RETRY_TIMER_THRESHOLD_HI_BASE_IDX 0 +#define regSQG_UTCL0_RETRY_TIMER_THRESHOLD_LO 0x10e4 +#define regSQG_UTCL0_RETRY_TIMER_THRESHOLD_LO_BASE_IDX 0 +#define regSQG_WS_INSERTION_COUNT 0x10e5 +#define regSQG_WS_INSERTION_COUNT_BASE_IDX 0 +#define regSQG_WS_SPI_STATUS 0x10e6 +#define regSQG_WS_SPI_STATUS_BASE_IDX 0 +#define regSQ_IND_INDEX 0x1118 +#define regSQ_IND_INDEX_BASE_IDX 0 +#define regSQ_IND_DATA 0x1119 +#define regSQ_IND_DATA_BASE_IDX 0 +#define regSQ_CMD 0x111b +#define regSQ_CMD_BASE_IDX 0 +#define regSQC_WSM_CONTROL 0x1174 +#define regSQC_WSM_CONTROL_BASE_IDX 0 +#define regSQC_PIT_CONTROL0 0x1175 +#define regSQC_PIT_CONTROL0_BASE_IDX 0 +#define regSQC_PIT_CONTROL1 0x1176 +#define regSQC_PIT_CONTROL1_BASE_IDX 0 +#define regSQC_PIT_CONTROL2 0x1177 +#define regSQC_PIT_CONTROL2_BASE_IDX 0 +#define regSQC_UTCL0_RETRY 0x1178 +#define regSQC_UTCL0_RETRY_BASE_IDX 0 +#define regSQC_MISC_CONFIG 0x1179 +#define regSQC_MISC_CONFIG_BASE_IDX 0 +#define regSQ_TIMEOUT_CONFIG 0x117a +#define regSQ_TIMEOUT_CONFIG_BASE_IDX 0 +#define regSQ_TIMEOUT_STATUS_SIMD01 0x117b +#define regSQ_TIMEOUT_STATUS_SIMD01_BASE_IDX 0 +#define regSQ_TIMEOUT_STATUS_SIMD23 0x117c +#define regSQ_TIMEOUT_STATUS_SIMD23_BASE_IDX 0 +#define regSQC_UTCL0_STATUS 0x117d +#define regSQC_UTCL0_STATUS_BASE_IDX 0 +#define regSQC_UTCL0_CNTL1 0x117e +#define regSQC_UTCL0_CNTL1_BASE_IDX 0 +#define regSQC_UTCL0_CNTL2 0x117f +#define regSQC_UTCL0_CNTL2_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_shsdec +// base address: 0x9000 +#define regSX_DEBUG_BUSY 0x11b4 +#define regSX_DEBUG_BUSY_BASE_IDX 0 +#define regSX_DEBUG_BUSY_2 0x11b5 +#define regSX_DEBUG_BUSY_2_BASE_IDX 0 +#define regSX_DEBUG_BUSY_3 0x11b6 +#define regSX_DEBUG_BUSY_3_BASE_IDX 0 +#define regSX_DEBUG_BUSY_4 0x11b7 +#define regSX_DEBUG_BUSY_4_BASE_IDX 0 +#define regSX_DEBUG_1 0x11b8 +#define regSX_DEBUG_1_BASE_IDX 0 +#define regSX_DEBUG_BUSY_5 0x11b9 +#define regSX_DEBUG_BUSY_5_BASE_IDX 0 +#define regSX_DEBUG_BUSY_6 0x11ba +#define regSX_DEBUG_BUSY_6_BASE_IDX 0 +#define regSX_DEBUG_BUSY_7 0x11bb +#define regSX_DEBUG_BUSY_7_BASE_IDX 0 +#define regSX_DEBUG_BUSY_8 0x11bc +#define regSX_DEBUG_BUSY_8_BASE_IDX 0 +#define regSX_DEBUG_BUSY_9 0x11bd +#define regSX_DEBUG_BUSY_9_BASE_IDX 0 +#define regSX_DEBUG_BUSY_10 0x11be +#define regSX_DEBUG_BUSY_10_BASE_IDX 0 +#define regSPI_PS_MAX_WAVE_ID 0x11da +#define regSPI_PS_MAX_WAVE_ID_BASE_IDX 0 +#define regSPI_SCRATCH_ADDR_STATUS 0x11db +#define regSPI_SCRATCH_ADDR_STATUS_BASE_IDX 0 +#define regSPI_GFX_CNTL 0x11dc +#define regSPI_GFX_CNTL_BASE_IDX 0 +#define regSPI_DEBUG_CNTL_2 0x11de +#define regSPI_DEBUG_CNTL_2_BASE_IDX 0 +#define regSPI_DEBUG_CNTL_3 0x11df +#define regSPI_DEBUG_CNTL_3_BASE_IDX 0 +#define regSPI_DEBUG_CNTL 0x11e1 +#define regSPI_DEBUG_CNTL_BASE_IDX 0 +#define regSPI_DEBUG_READ 0x11e2 +#define regSPI_DEBUG_READ_BASE_IDX 0 +#define regSPI_DSM_CNTL 0x11e3 +#define regSPI_DSM_CNTL_BASE_IDX 0 +#define regSPI_DSM_CNTL2 0x11e4 +#define regSPI_DSM_CNTL2_BASE_IDX 0 +#define regSPI_EDC_CNT 0x11e5 +#define regSPI_EDC_CNT_BASE_IDX 0 +#define regSPIRA_DEBUG_READ 0x11e6 +#define regSPIRA_DEBUG_READ_BASE_IDX 0 +#define regSPI_DEBUG_BUSY 0x11f0 +#define regSPI_DEBUG_BUSY_BASE_IDX 0 +#define regSPI_CONFIG_PS_CU_EN 0x11f2 +#define regSPI_CONFIG_PS_CU_EN_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_GFX0 0x11f3 +#define regSPI_CONFIG_CU_MASK_GFX0_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_HP3D0 0x11f4 +#define regSPI_CONFIG_CU_MASK_HP3D0_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_GFX1 0x11f5 +#define regSPI_CONFIG_CU_MASK_GFX1_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_HP3D1 0x11f6 +#define regSPI_CONFIG_CU_MASK_HP3D1_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS0 0x11f7 +#define regSPI_CONFIG_CU_MASK_CS0_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS1 0x11f8 +#define regSPI_CONFIG_CU_MASK_CS1_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS2 0x11f9 +#define regSPI_CONFIG_CU_MASK_CS2_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS3 0x11fa +#define regSPI_CONFIG_CU_MASK_CS3_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS4 0x11fb +#define regSPI_CONFIG_CU_MASK_CS4_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS5 0x11fc +#define regSPI_CONFIG_CU_MASK_CS5_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS6 0x11fd +#define regSPI_CONFIG_CU_MASK_CS6_BASE_IDX 0 +#define regSPI_CONFIG_CU_MASK_CS7 0x11fe +#define regSPI_CONFIG_CU_MASK_CS7_BASE_IDX 0 +#define regSPI_WF_LIFETIME_CNTL 0x124a +#define regSPI_WF_LIFETIME_CNTL_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_0 0x124b +#define regSPI_WF_LIFETIME_LIMIT_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_2 0x124d +#define regSPI_WF_LIFETIME_LIMIT_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_3 0x124e +#define regSPI_WF_LIFETIME_LIMIT_3_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_4 0x124f +#define regSPI_WF_LIFETIME_LIMIT_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_LIMIT_5 0x1250 +#define regSPI_WF_LIFETIME_LIMIT_5_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_0 0x1255 +#define regSPI_WF_LIFETIME_STATUS_0_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_2 0x1257 +#define regSPI_WF_LIFETIME_STATUS_2_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_4 0x1259 +#define regSPI_WF_LIFETIME_STATUS_4_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_6 0x125b +#define regSPI_WF_LIFETIME_STATUS_6_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_7 0x125c +#define regSPI_WF_LIFETIME_STATUS_7_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_9 0x125e +#define regSPI_WF_LIFETIME_STATUS_9_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_11 0x1260 +#define regSPI_WF_LIFETIME_STATUS_11_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_13 0x1262 +#define regSPI_WF_LIFETIME_STATUS_13_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_14 0x1263 +#define regSPI_WF_LIFETIME_STATUS_14_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_15 0x1264 +#define regSPI_WF_LIFETIME_STATUS_15_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_16 0x1265 +#define regSPI_WF_LIFETIME_STATUS_16_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_17 0x1266 +#define regSPI_WF_LIFETIME_STATUS_17_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_18 0x1267 +#define regSPI_WF_LIFETIME_STATUS_18_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_19 0x1268 +#define regSPI_WF_LIFETIME_STATUS_19_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_20 0x1269 +#define regSPI_WF_LIFETIME_STATUS_20_BASE_IDX 0 +#define regSPI_WF_LIFETIME_DEBUG 0x126a +#define regSPI_WF_LIFETIME_DEBUG_BASE_IDX 0 +#define regSPI_WF_LIFETIME_STATUS_21 0x126b +#define regSPI_WF_LIFETIME_STATUS_21_BASE_IDX 0 +#define regSPI_WGP_WORK_PENDING 0x126c +#define regSPI_WGP_WORK_PENDING_BASE_IDX 0 +#define regSPI_CREST_MODE 0x126d +#define regSPI_CREST_MODE_BASE_IDX 0 +#define regSPI_SLAVE_DEBUG_BUSY 0x1273 +#define regSPI_SLAVE_DEBUG_BUSY_BASE_IDX 0 +#define regSPI_LB_CTR_CTRL 0x1274 +#define regSPI_LB_CTR_CTRL_BASE_IDX 0 +#define regSPI_LB_WGP_MASK 0x1275 +#define regSPI_LB_WGP_MASK_BASE_IDX 0 +#define regSPI_LB_DATA_REG 0x1276 +#define regSPI_LB_DATA_REG_BASE_IDX 0 +#define regSPI_PG_ENABLE_STATIC_WGP_MASK 0x1277 +#define regSPI_PG_ENABLE_STATIC_WGP_MASK_BASE_IDX 0 +#define regSPI_GDS_CREDITS 0x1278 +#define regSPI_GDS_CREDITS_BASE_IDX 0 +#define regSPI_SX_EXPORT_BUFFER_SIZES 0x1279 +#define regSPI_SX_EXPORT_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES 0x127a +#define regSPI_SX_SCOREBOARD_BUFFER_SIZES_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_STATUS 0x127b +#define regSPI_CSQ_WF_ACTIVE_STATUS_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_0 0x127c +#define regSPI_CSQ_WF_ACTIVE_COUNT_0_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_1 0x127d +#define regSPI_CSQ_WF_ACTIVE_COUNT_1_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_2 0x127e +#define regSPI_CSQ_WF_ACTIVE_COUNT_2_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_3 0x127f +#define regSPI_CSQ_WF_ACTIVE_COUNT_3_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_4 0x1280 +#define regSPI_CSQ_WF_ACTIVE_COUNT_4_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_5 0x1281 +#define regSPI_CSQ_WF_ACTIVE_COUNT_5_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_6 0x1282 +#define regSPI_CSQ_WF_ACTIVE_COUNT_6_BASE_IDX 0 +#define regSPI_CSQ_WF_ACTIVE_COUNT_7 0x1283 +#define regSPI_CSQ_WF_ACTIVE_COUNT_7_BASE_IDX 0 +#define regSPI_LB_DATA_WAVES 0x1284 +#define regSPI_LB_DATA_WAVES_BASE_IDX 0 +#define regSPI_LB_DATA_PERWGP_WAVE_HSGS 0x1285 +#define regSPI_LB_DATA_PERWGP_WAVE_HSGS_BASE_IDX 0 +#define regSPI_LB_DATA_PERWGP_WAVE_PS 0x1286 +#define regSPI_LB_DATA_PERWGP_WAVE_PS_BASE_IDX 0 +#define regSPI_LB_DATA_PERWGP_WAVE_CS 0x1287 +#define regSPI_LB_DATA_PERWGP_WAVE_CS_BASE_IDX 0 +#define regSPI_WF_ACTIVE_COUNT_GFX 0x1288 +#define regSPI_WF_ACTIVE_COUNT_GFX_BASE_IDX 0 +#define regSPI_WF_ACTIVE_COUNT_HPG 0x1289 +#define regSPI_WF_ACTIVE_COUNT_HPG_BASE_IDX 0 +#define regSPIS_DEBUG_READ 0x128a +#define regSPIS_DEBUG_READ_BASE_IDX 0 +#define regBCI_DEBUG_READ 0x128b +#define regBCI_DEBUG_READ_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_LO 0x128c +#define regSPI_P0_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSBA_HI 0x128d +#define regSPI_P0_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_LO 0x128e +#define regSPI_P0_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_PSMA_HI 0x128f +#define regSPI_P0_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN 0x1290 +#define regSPI_P0_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO 0x1291 +#define regSPI_P1_TRAP_SCREEN_PSBA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI 0x1292 +#define regSPI_P1_TRAP_SCREEN_PSBA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO 0x1293 +#define regSPI_P1_TRAP_SCREEN_PSMA_LO_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI 0x1294 +#define regSPI_P1_TRAP_SCREEN_PSMA_HI_BASE_IDX 0 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN 0x1295 +#define regSPI_P1_TRAP_SCREEN_GPR_MIN_BASE_IDX 0 +#define regSPI_GFX_CRAWLER_CONFIG 0x1296 +#define regSPI_GFX_CRAWLER_CONFIG_BASE_IDX 0 +#define regSPI_CS_CRAWLER_CONFIG 0x1297 +#define regSPI_CS_CRAWLER_CONFIG_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_tpdec +// base address: 0x9400 +#define regTD_CNTL 0x12c5 +#define regTD_CNTL_BASE_IDX 0 +#define regTD_STATUS 0x12c6 +#define regTD_STATUS_BASE_IDX 0 +#define regTD_DEBUG_DATA 0x12c9 +#define regTD_DEBUG_DATA_BASE_IDX 0 +#define regTD_POWER_CNTL 0x12ca +#define regTD_POWER_CNTL_BASE_IDX 0 +#define regTD_CNTL2 0x12cb +#define regTD_CNTL2_BASE_IDX 0 +#define regTD_DSM_CNTL 0x12cf +#define regTD_DSM_CNTL_BASE_IDX 0 +#define regTD_DSM_CNTL2 0x12d0 +#define regTD_DSM_CNTL2_BASE_IDX 0 +#define regTD_SCRATCH 0x12d3 +#define regTD_SCRATCH_BASE_IDX 0 +#define regTA_CNTL 0x12e1 +#define regTA_CNTL_BASE_IDX 0 +#define regTA_CNTL_AUX 0x12e2 +#define regTA_CNTL_AUX_BASE_IDX 0 +#define regTA_CNTL2 0x12e5 +#define regTA_CNTL2_BASE_IDX 0 +#define regTA_STATUS 0x12e8 +#define regTA_STATUS_BASE_IDX 0 +#define regTA_SCRATCH 0x1304 +#define regTA_SCRATCH_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_rbdec +// base address: 0x9800 +#define regDB_DEBUG 0x13ac +#define regDB_DEBUG_BASE_IDX 0 +#define regDB_DEBUG2 0x13ad +#define regDB_DEBUG2_BASE_IDX 0 +#define regDB_DEBUG3 0x13ae +#define regDB_DEBUG3_BASE_IDX 0 +#define regDB_DEBUG4 0x13af +#define regDB_DEBUG4_BASE_IDX 0 +#define regDB_CREDIT_LIMIT 0x13b4 +#define regDB_CREDIT_LIMIT_BASE_IDX 0 +#define regDB_WATERMARKS 0x13b5 +#define regDB_WATERMARKS_BASE_IDX 0 +#define regDB_FREE_CACHELINES 0x13b7 +#define regDB_FREE_CACHELINES_BASE_IDX 0 +#define regDB_FIFO_DEPTH1 0x13b8 +#define regDB_FIFO_DEPTH1_BASE_IDX 0 +#define regDB_FIFO_DEPTH2 0x13b9 +#define regDB_FIFO_DEPTH2_BASE_IDX 0 +#define regDB_RING_CONTROL 0x13bb +#define regDB_RING_CONTROL_BASE_IDX 0 +#define regDB_MEM_ARB_WATERMARKS 0x13bc +#define regDB_MEM_ARB_WATERMARKS_BASE_IDX 0 +#define regDB_FIFO_DEPTH3 0x13bd +#define regDB_FIFO_DEPTH3_BASE_IDX 0 +#define regDB_DEBUG6 0x13be +#define regDB_DEBUG6_BASE_IDX 0 +#define regDB_EXCEPTION_CONTROL 0x13bf +#define regDB_EXCEPTION_CONTROL_BASE_IDX 0 +#define regDB_DEBUG7 0x13d0 +#define regDB_DEBUG7_BASE_IDX 0 +#define regDB_DEBUG5 0x13d1 +#define regDB_DEBUG5_BASE_IDX 0 +#define regDB_MEM_CONFIG 0x13d2 +#define regDB_MEM_CONFIG_BASE_IDX 0 +#define regDB_ARB_CONFIG 0x13d3 +#define regDB_ARB_CONFIG_BASE_IDX 0 +#define regDB_DFD_INDIRECT_SEL 0x13d4 +#define regDB_DFD_INDIRECT_SEL_BASE_IDX 0 +#define regDB_DFD_INDIRECT_DAT 0x13d5 +#define regDB_DFD_INDIRECT_DAT_BASE_IDX 0 +#define regDB_SUMMARIZER_TIMEOUTS 0x13d6 +#define regDB_SUMMARIZER_TIMEOUTS_BASE_IDX 0 +#define regDB_FGCG_SRAMS_CLK_CTRL 0x13d7 +#define regDB_FGCG_SRAMS_CLK_CTRL_BASE_IDX 0 +#define regDB_FGCG_INTERFACES_CLK_CTRL 0x13d8 +#define regDB_FGCG_INTERFACES_CLK_CTRL_BASE_IDX 0 +#define regDB_FIFO_DEPTH4 0x13d9 +#define regDB_FIFO_DEPTH4_BASE_IDX 0 +#define regCC_RB_BACKEND_DISABLE 0x13dd +#define regCC_RB_BACKEND_DISABLE_BASE_IDX 0 +#define regGB_ADDR_CONFIG_1 0x13de +#define regGB_ADDR_CONFIG_1_BASE_IDX 0 +#define regGB_BACKEND_MAP 0x13df +#define regGB_BACKEND_MAP_BASE_IDX 0 +#define regGB_GPU_ID 0x13e0 +#define regGB_GPU_ID_BASE_IDX 0 +#define regGB_ADDR_CONFIG_READ 0x13e2 +#define regGB_ADDR_CONFIG_READ_BASE_IDX 0 +#define regCB_HW_CONTROL_4 0x1422 +#define regCB_HW_CONTROL_4_BASE_IDX 0 +#define regCB_HW_CONTROL_3 0x1423 +#define regCB_HW_CONTROL_3_BASE_IDX 0 +#define regCB_HW_CONTROL 0x1424 +#define regCB_HW_CONTROL_BASE_IDX 0 +#define regCB_HW_CONTROL_1 0x1425 +#define regCB_HW_CONTROL_1_BASE_IDX 0 +#define regCB_HW_CONTROL_2 0x1426 +#define regCB_HW_CONTROL_2_BASE_IDX 0 +#define regCB_HW_MEM_ARBITER_CTL 0x1428 +#define regCB_HW_MEM_ARBITER_CTL_BASE_IDX 0 +#define regCB_FGCG_SRAM_OVERRIDE 0x142a +#define regCB_FGCG_SRAM_OVERRIDE_BASE_IDX 0 +#define regCB_CACHE_EVICT_POINTS 0x142e +#define regCB_CACHE_EVICT_POINTS_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_spipdec2 +// base address: 0x9c80 +#define regSPI_PQEV_CTRL 0x14c0 +#define regSPI_PQEV_CTRL_BASE_IDX 0 +#define regSPI_EXP_THROTTLE_CTRL 0x14c3 +#define regSPI_EXP_THROTTLE_CTRL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_rmi_gfx_se_rmidec +// base address: 0x2e200 +#define regRMI_GENERAL_CNTL 0x1880 +#define regRMI_GENERAL_CNTL_BASE_IDX 1 +#define regRMI_GENERAL_CNTL1 0x1881 +#define regRMI_GENERAL_CNTL1_BASE_IDX 1 +#define regRMI_GENERAL_STATUS 0x1882 +#define regRMI_GENERAL_STATUS_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS0 0x1883 +#define regRMI_SUBBLOCK_STATUS0_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS1 0x1884 +#define regRMI_SUBBLOCK_STATUS1_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS2 0x1885 +#define regRMI_SUBBLOCK_STATUS2_BASE_IDX 1 +#define regRMI_SUBBLOCK_STATUS3 0x1886 +#define regRMI_SUBBLOCK_STATUS3_BASE_IDX 1 +#define regRMI_XBAR_CONFIG 0x1887 +#define regRMI_XBAR_CONFIG_BASE_IDX 1 +#define regRMI_PROBE_POP_LOGIC_CNTL 0x1888 +#define regRMI_PROBE_POP_LOGIC_CNTL_BASE_IDX 1 +#define regRMI_UTC_XNACK_N_MISC_CNTL 0x1889 +#define regRMI_UTC_XNACK_N_MISC_CNTL_BASE_IDX 1 +#define regRMI_DEMUX_CNTL 0x188a +#define regRMI_DEMUX_CNTL_BASE_IDX 1 +#define regRMI_UTCL1_CNTL1 0x188b +#define regRMI_UTCL1_CNTL1_BASE_IDX 1 +#define regRMI_UTCL1_CNTL2 0x188c +#define regRMI_UTCL1_CNTL2_BASE_IDX 1 +#define regRMI_UTC_UNIT_CONFIG 0x188d +#define regRMI_UTC_UNIT_CONFIG_BASE_IDX 1 +#define regRMI_TCIW_FORMATTER0_CNTL 0x188e +#define regRMI_TCIW_FORMATTER0_CNTL_BASE_IDX 1 +#define regRMI_TCIW_FORMATTER1_CNTL 0x188f +#define regRMI_TCIW_FORMATTER1_CNTL_BASE_IDX 1 +#define regRMI_SCOREBOARD_CNTL 0x1890 +#define regRMI_SCOREBOARD_CNTL_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS0 0x1891 +#define regRMI_SCOREBOARD_STATUS0_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS1 0x1892 +#define regRMI_SCOREBOARD_STATUS1_BASE_IDX 1 +#define regRMI_SCOREBOARD_STATUS2 0x1893 +#define regRMI_SCOREBOARD_STATUS2_BASE_IDX 1 +#define regRMI_XBAR_ARBITER_CONFIG 0x1894 +#define regRMI_XBAR_ARBITER_CONFIG_BASE_IDX 1 +#define regRMI_XBAR_ARBITER_CONFIG_1 0x1895 +#define regRMI_XBAR_ARBITER_CONFIG_1_BASE_IDX 1 +#define regRMI_CLOCK_CNTRL 0x1896 +#define regRMI_CLOCK_CNTRL_BASE_IDX 1 +#define regRMI_UTCL1_STATUS 0x1897 +#define regRMI_UTCL1_STATUS_BASE_IDX 1 +#define regRMI_RB_GLX_CID_MAP 0x1898 +#define regRMI_RB_GLX_CID_MAP_BASE_IDX 1 +#define regRMI_XNACK_DEBUG 0x189e +#define regRMI_XNACK_DEBUG_BASE_IDX 1 +#define regRMI_SPARE 0x189f +#define regRMI_SPARE_BASE_IDX 1 +#define regRMI_SPARE_1 0x18a0 +#define regRMI_SPARE_1_BASE_IDX 1 +#define regRMI_SPARE_2 0x18a1 +#define regRMI_SPARE_2_BASE_IDX 1 +#define regCC_RMI_REDUNDANCY 0x18a2 +#define regCC_RMI_REDUNDANCY_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_utcl1dec +// base address: 0x9fb0 +#define regUTCL1_CTRL_1 0x158c +#define regUTCL1_CTRL_1_BASE_IDX 0 +#define regUTCL1_HASH_CTRL 0x158e +#define regUTCL1_HASH_CTRL_BASE_IDX 0 +#define regUTCL1_ALOG 0x158f +#define regUTCL1_ALOG_BASE_IDX 0 +#define regUTCL1_STATUS 0x1594 +#define regUTCL1_STATUS_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_shdec +// base address: 0xb000 +#define regSPI_SHADER_PGM_CHKSUM_PS 0x19a5 +#define regSPI_SHADER_PGM_CHKSUM_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_PS 0x19a6 +#define regSPI_SHADER_PGM_RSRC3_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_PS 0x19a7 +#define regSPI_SHADER_PGM_RSRC4_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_PS 0x19a8 +#define regSPI_SHADER_PGM_LO_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_PS 0x19a9 +#define regSPI_SHADER_PGM_HI_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_PS 0x19aa +#define regSPI_SHADER_PGM_RSRC1_PS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_PS 0x19ab +#define regSPI_SHADER_PGM_RSRC2_PS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_0 0x19ac +#define regSPI_SHADER_USER_DATA_PS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_1 0x19ad +#define regSPI_SHADER_USER_DATA_PS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_2 0x19ae +#define regSPI_SHADER_USER_DATA_PS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_3 0x19af +#define regSPI_SHADER_USER_DATA_PS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_4 0x19b0 +#define regSPI_SHADER_USER_DATA_PS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_5 0x19b1 +#define regSPI_SHADER_USER_DATA_PS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_6 0x19b2 +#define regSPI_SHADER_USER_DATA_PS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_7 0x19b3 +#define regSPI_SHADER_USER_DATA_PS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_8 0x19b4 +#define regSPI_SHADER_USER_DATA_PS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_9 0x19b5 +#define regSPI_SHADER_USER_DATA_PS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_10 0x19b6 +#define regSPI_SHADER_USER_DATA_PS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_11 0x19b7 +#define regSPI_SHADER_USER_DATA_PS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_12 0x19b8 +#define regSPI_SHADER_USER_DATA_PS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_13 0x19b9 +#define regSPI_SHADER_USER_DATA_PS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_14 0x19ba +#define regSPI_SHADER_USER_DATA_PS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_15 0x19bb +#define regSPI_SHADER_USER_DATA_PS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_16 0x19bc +#define regSPI_SHADER_USER_DATA_PS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_17 0x19bd +#define regSPI_SHADER_USER_DATA_PS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_18 0x19be +#define regSPI_SHADER_USER_DATA_PS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_19 0x19bf +#define regSPI_SHADER_USER_DATA_PS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_20 0x19c0 +#define regSPI_SHADER_USER_DATA_PS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_21 0x19c1 +#define regSPI_SHADER_USER_DATA_PS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_22 0x19c2 +#define regSPI_SHADER_USER_DATA_PS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_23 0x19c3 +#define regSPI_SHADER_USER_DATA_PS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_24 0x19c4 +#define regSPI_SHADER_USER_DATA_PS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_25 0x19c5 +#define regSPI_SHADER_USER_DATA_PS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_26 0x19c6 +#define regSPI_SHADER_USER_DATA_PS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_27 0x19c7 +#define regSPI_SHADER_USER_DATA_PS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_28 0x19c8 +#define regSPI_SHADER_USER_DATA_PS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_29 0x19c9 +#define regSPI_SHADER_USER_DATA_PS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_30 0x19ca +#define regSPI_SHADER_USER_DATA_PS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_PS_31 0x19cb +#define regSPI_SHADER_USER_DATA_PS_31_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_PS 0x19d0 +#define regSPI_SHADER_REQ_CTRL_PS_BASE_IDX 0 +#define regSPI_SHADER_GS_OUT_CONFIG_PS 0x19d1 +#define regSPI_SHADER_GS_OUT_CONFIG_PS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_0 0x19d2 +#define regSPI_SHADER_USER_ACCUM_PS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_1 0x19d3 +#define regSPI_SHADER_USER_ACCUM_PS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_2 0x19d4 +#define regSPI_SHADER_USER_ACCUM_PS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_PS_3 0x19d5 +#define regSPI_SHADER_USER_ACCUM_PS_3_BASE_IDX 0 +#define regSPI_SHADER_PGM_CHKSUM_GS 0x1a20 +#define regSPI_SHADER_PGM_CHKSUM_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS 0x1a22 +#define regSPI_SHADER_USER_DATA_ADDR_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS 0x1a23 +#define regSPI_SHADER_USER_DATA_ADDR_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_GS 0x1a24 +#define regSPI_SHADER_PGM_LO_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_GS 0x1a25 +#define regSPI_SHADER_PGM_HI_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_ES 0x1a26 +#define regSPI_SHADER_PGM_HI_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_GS 0x1a27 +#define regSPI_SHADER_PGM_RSRC3_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_GS 0x1a28 +#define regSPI_SHADER_PGM_RSRC4_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_ES 0x1a29 +#define regSPI_SHADER_PGM_LO_ES_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_GS 0x1a2a +#define regSPI_SHADER_PGM_RSRC1_GS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_GS 0x1a2b +#define regSPI_SHADER_PGM_RSRC2_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_0 0x1a2c +#define regSPI_SHADER_USER_DATA_GS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_1 0x1a2d +#define regSPI_SHADER_USER_DATA_GS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_2 0x1a2e +#define regSPI_SHADER_USER_DATA_GS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_3 0x1a2f +#define regSPI_SHADER_USER_DATA_GS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_4 0x1a30 +#define regSPI_SHADER_USER_DATA_GS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_5 0x1a31 +#define regSPI_SHADER_USER_DATA_GS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_6 0x1a32 +#define regSPI_SHADER_USER_DATA_GS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_7 0x1a33 +#define regSPI_SHADER_USER_DATA_GS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_8 0x1a34 +#define regSPI_SHADER_USER_DATA_GS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_9 0x1a35 +#define regSPI_SHADER_USER_DATA_GS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_10 0x1a36 +#define regSPI_SHADER_USER_DATA_GS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_11 0x1a37 +#define regSPI_SHADER_USER_DATA_GS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_12 0x1a38 +#define regSPI_SHADER_USER_DATA_GS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_13 0x1a39 +#define regSPI_SHADER_USER_DATA_GS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_14 0x1a3a +#define regSPI_SHADER_USER_DATA_GS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_15 0x1a3b +#define regSPI_SHADER_USER_DATA_GS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_16 0x1a3c +#define regSPI_SHADER_USER_DATA_GS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_17 0x1a3d +#define regSPI_SHADER_USER_DATA_GS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_18 0x1a3e +#define regSPI_SHADER_USER_DATA_GS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_19 0x1a3f +#define regSPI_SHADER_USER_DATA_GS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_20 0x1a40 +#define regSPI_SHADER_USER_DATA_GS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_21 0x1a41 +#define regSPI_SHADER_USER_DATA_GS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_22 0x1a42 +#define regSPI_SHADER_USER_DATA_GS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_23 0x1a43 +#define regSPI_SHADER_USER_DATA_GS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_24 0x1a44 +#define regSPI_SHADER_USER_DATA_GS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_25 0x1a45 +#define regSPI_SHADER_USER_DATA_GS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_26 0x1a46 +#define regSPI_SHADER_USER_DATA_GS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_27 0x1a47 +#define regSPI_SHADER_USER_DATA_GS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_28 0x1a48 +#define regSPI_SHADER_USER_DATA_GS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_29 0x1a49 +#define regSPI_SHADER_USER_DATA_GS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_30 0x1a4a +#define regSPI_SHADER_USER_DATA_GS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_GS_31 0x1a4b +#define regSPI_SHADER_USER_DATA_GS_31_BASE_IDX 0 +#define regSPI_SHADER_GS_MESHLET_DIM 0x1a4c +#define regSPI_SHADER_GS_MESHLET_DIM_BASE_IDX 0 +#define regSPI_SHADER_GS_MESHLET_EXP_ALLOC 0x1a4d +#define regSPI_SHADER_GS_MESHLET_EXP_ALLOC_BASE_IDX 0 +#define regSPI_SHADER_GS_MESHLET_CTRL 0x1a4e +#define regSPI_SHADER_GS_MESHLET_CTRL_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_ESGS 0x1a50 +#define regSPI_SHADER_REQ_CTRL_ESGS_BASE_IDX 0 +#define regSPI_SHADER_GS_OUT_CONFIG_PS_GS 0x1a51 +#define regSPI_SHADER_GS_OUT_CONFIG_PS_GS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_0 0x1a52 +#define regSPI_SHADER_USER_ACCUM_ESGS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_1 0x1a53 +#define regSPI_SHADER_USER_ACCUM_ESGS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_2 0x1a54 +#define regSPI_SHADER_USER_ACCUM_ESGS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_ESGS_3 0x1a55 +#define regSPI_SHADER_USER_ACCUM_ESGS_3_BASE_IDX 0 +#define regSPI_SHADER_PGM_CHKSUM_HS 0x1aa0 +#define regSPI_SHADER_PGM_CHKSUM_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS 0x1aa2 +#define regSPI_SHADER_USER_DATA_ADDR_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS 0x1aa3 +#define regSPI_SHADER_USER_DATA_ADDR_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_HS 0x1aa4 +#define regSPI_SHADER_PGM_LO_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_HS 0x1aa5 +#define regSPI_SHADER_PGM_HI_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_HI_LS 0x1aa6 +#define regSPI_SHADER_PGM_HI_LS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC3_HS 0x1aa7 +#define regSPI_SHADER_PGM_RSRC3_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC4_HS 0x1aa8 +#define regSPI_SHADER_PGM_RSRC4_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_LO_LS 0x1aa9 +#define regSPI_SHADER_PGM_LO_LS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC1_HS 0x1aaa +#define regSPI_SHADER_PGM_RSRC1_HS_BASE_IDX 0 +#define regSPI_SHADER_PGM_RSRC2_HS 0x1aab +#define regSPI_SHADER_PGM_RSRC2_HS_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_0 0x1aac +#define regSPI_SHADER_USER_DATA_HS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_1 0x1aad +#define regSPI_SHADER_USER_DATA_HS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_2 0x1aae +#define regSPI_SHADER_USER_DATA_HS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_3 0x1aaf +#define regSPI_SHADER_USER_DATA_HS_3_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_4 0x1ab0 +#define regSPI_SHADER_USER_DATA_HS_4_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_5 0x1ab1 +#define regSPI_SHADER_USER_DATA_HS_5_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_6 0x1ab2 +#define regSPI_SHADER_USER_DATA_HS_6_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_7 0x1ab3 +#define regSPI_SHADER_USER_DATA_HS_7_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_8 0x1ab4 +#define regSPI_SHADER_USER_DATA_HS_8_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_9 0x1ab5 +#define regSPI_SHADER_USER_DATA_HS_9_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_10 0x1ab6 +#define regSPI_SHADER_USER_DATA_HS_10_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_11 0x1ab7 +#define regSPI_SHADER_USER_DATA_HS_11_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_12 0x1ab8 +#define regSPI_SHADER_USER_DATA_HS_12_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_13 0x1ab9 +#define regSPI_SHADER_USER_DATA_HS_13_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_14 0x1aba +#define regSPI_SHADER_USER_DATA_HS_14_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_15 0x1abb +#define regSPI_SHADER_USER_DATA_HS_15_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_16 0x1abc +#define regSPI_SHADER_USER_DATA_HS_16_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_17 0x1abd +#define regSPI_SHADER_USER_DATA_HS_17_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_18 0x1abe +#define regSPI_SHADER_USER_DATA_HS_18_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_19 0x1abf +#define regSPI_SHADER_USER_DATA_HS_19_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_20 0x1ac0 +#define regSPI_SHADER_USER_DATA_HS_20_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_21 0x1ac1 +#define regSPI_SHADER_USER_DATA_HS_21_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_22 0x1ac2 +#define regSPI_SHADER_USER_DATA_HS_22_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_23 0x1ac3 +#define regSPI_SHADER_USER_DATA_HS_23_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_24 0x1ac4 +#define regSPI_SHADER_USER_DATA_HS_24_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_25 0x1ac5 +#define regSPI_SHADER_USER_DATA_HS_25_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_26 0x1ac6 +#define regSPI_SHADER_USER_DATA_HS_26_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_27 0x1ac7 +#define regSPI_SHADER_USER_DATA_HS_27_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_28 0x1ac8 +#define regSPI_SHADER_USER_DATA_HS_28_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_29 0x1ac9 +#define regSPI_SHADER_USER_DATA_HS_29_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_30 0x1aca +#define regSPI_SHADER_USER_DATA_HS_30_BASE_IDX 0 +#define regSPI_SHADER_USER_DATA_HS_31 0x1acb +#define regSPI_SHADER_USER_DATA_HS_31_BASE_IDX 0 +#define regSPI_SHADER_REQ_CTRL_LSHS 0x1ad0 +#define regSPI_SHADER_REQ_CTRL_LSHS_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_0 0x1ad2 +#define regSPI_SHADER_USER_ACCUM_LSHS_0_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_1 0x1ad3 +#define regSPI_SHADER_USER_ACCUM_LSHS_1_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_2 0x1ad4 +#define regSPI_SHADER_USER_ACCUM_LSHS_2_BASE_IDX 0 +#define regSPI_SHADER_USER_ACCUM_LSHS_3 0x1ad5 +#define regSPI_SHADER_USER_ACCUM_LSHS_3_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_spipdec +// base address: 0xc700 +#define regSPI_ARB_PRIORITY 0x1f60 +#define regSPI_ARB_PRIORITY_BASE_IDX 0 +#define regSPI_ARB_CYCLES_0 0x1f61 +#define regSPI_ARB_CYCLES_0_BASE_IDX 0 +#define regSPI_ARB_CYCLES_1 0x1f62 +#define regSPI_ARB_CYCLES_1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_GFX 0x1f67 +#define regSPI_WCL_PIPE_PERCENT_GFX_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_HP3D 0x1f68 +#define regSPI_WCL_PIPE_PERCENT_HP3D_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS0 0x1f69 +#define regSPI_WCL_PIPE_PERCENT_CS0_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS1 0x1f6a +#define regSPI_WCL_PIPE_PERCENT_CS1_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS2 0x1f6b +#define regSPI_WCL_PIPE_PERCENT_CS2_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS3 0x1f6c +#define regSPI_WCL_PIPE_PERCENT_CS3_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS4 0x1f6d +#define regSPI_WCL_PIPE_PERCENT_CS4_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS5 0x1f6e +#define regSPI_WCL_PIPE_PERCENT_CS5_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS6 0x1f6f +#define regSPI_WCL_PIPE_PERCENT_CS6_BASE_IDX 0 +#define regSPI_WCL_PIPE_PERCENT_CS7 0x1f70 +#define regSPI_WCL_PIPE_PERCENT_CS7_BASE_IDX 0 +#define regSPI_USER_ACCUM_VMID_CNTL 0x1f71 +#define regSPI_USER_ACCUM_VMID_CNTL_BASE_IDX 0 +#define regSPI_GDBG_PER_VMID_CNTL 0x1f72 +#define regSPI_GDBG_PER_VMID_CNTL_BASE_IDX 0 +#define regSPI_COMPUTE_QUEUE_RESET 0x1f73 +#define regSPI_COMPUTE_QUEUE_RESET_BASE_IDX 0 +#define regSPI_COMPUTE_WF_CTX_SAVE 0x1f74 +#define regSPI_COMPUTE_WF_CTX_SAVE_BASE_IDX 0 +#define regSPI_SAVE_RESTORE_STATUS 0x1f75 +#define regSPI_SAVE_RESTORE_STATUS_BASE_IDX 0 +#define regSPI_CONFIG_DIDT_CNTL 0x1f76 +#define regSPI_CONFIG_DIDT_CNTL_BASE_IDX 0 +#define regSPI_CONFIG_DIDT_TYPEMASK 0x1f77 +#define regSPI_CONFIG_DIDT_TYPEMASK_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_tcpdec +// base address: 0xca80 +#define regTCP_WATCH0_ADDR_H 0x2048 +#define regTCP_WATCH0_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH0_ADDR_L 0x2049 +#define regTCP_WATCH0_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH0_CNTL 0x204a +#define regTCP_WATCH0_CNTL_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_H 0x204b +#define regTCP_WATCH1_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH1_ADDR_L 0x204c +#define regTCP_WATCH1_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH1_CNTL 0x204d +#define regTCP_WATCH1_CNTL_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_H 0x204e +#define regTCP_WATCH2_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH2_ADDR_L 0x204f +#define regTCP_WATCH2_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH2_CNTL 0x2050 +#define regTCP_WATCH2_CNTL_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_H 0x2051 +#define regTCP_WATCH3_ADDR_H_BASE_IDX 0 +#define regTCP_WATCH3_ADDR_L 0x2052 +#define regTCP_WATCH3_ADDR_L_BASE_IDX 0 +#define regTCP_WATCH3_CNTL 0x2053 +#define regTCP_WATCH3_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gfxdec0 +// base address: 0x28000 +#define regDB_RENDER_CONTROL 0x0000 +#define regDB_RENDER_CONTROL_BASE_IDX 1 +#define regDB_DEPTH_VIEW 0x0001 +#define regDB_DEPTH_VIEW_BASE_IDX 1 +#define regDB_DEPTH_VIEW1 0x0002 +#define regDB_DEPTH_VIEW1_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE 0x0003 +#define regDB_RENDER_OVERRIDE_BASE_IDX 1 +#define regDB_RENDER_OVERRIDE2 0x0004 +#define regDB_RENDER_OVERRIDE2_BASE_IDX 1 +#define regDB_DEPTH_SIZE_XY 0x0005 +#define regDB_DEPTH_SIZE_XY_BASE_IDX 1 +#define regDB_Z_INFO 0x0006 +#define regDB_Z_INFO_BASE_IDX 1 +#define regDB_STENCIL_INFO 0x0007 +#define regDB_STENCIL_INFO_BASE_IDX 1 +#define regDB_Z_READ_BASE 0x0008 +#define regDB_Z_READ_BASE_BASE_IDX 1 +#define regDB_Z_READ_BASE_HI 0x0009 +#define regDB_Z_READ_BASE_HI_BASE_IDX 1 +#define regDB_Z_WRITE_BASE 0x000a +#define regDB_Z_WRITE_BASE_BASE_IDX 1 +#define regDB_Z_WRITE_BASE_HI 0x000b +#define regDB_Z_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE 0x000c +#define regDB_STENCIL_READ_BASE_BASE_IDX 1 +#define regDB_STENCIL_READ_BASE_HI 0x000d +#define regDB_STENCIL_READ_BASE_HI_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE 0x000e +#define regDB_STENCIL_WRITE_BASE_BASE_IDX 1 +#define regDB_STENCIL_WRITE_BASE_HI 0x000f +#define regDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 +#define regDB_GL1_INTERFACE_CONTROL 0x0010 +#define regDB_GL1_INTERFACE_CONTROL_BASE_IDX 1 +#define regDB_MEM_TEMPORAL 0x0012 +#define regDB_MEM_TEMPORAL_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MIN 0x0014 +#define regDB_DEPTH_BOUNDS_MIN_BASE_IDX 1 +#define regDB_DEPTH_BOUNDS_MAX 0x0015 +#define regDB_DEPTH_BOUNDS_MAX_BASE_IDX 1 +#define regDB_COUNT_CONTROL 0x0018 +#define regDB_COUNT_CONTROL_BASE_IDX 1 +#define regDB_VIEWPORT_CONTROL 0x0019 +#define regDB_VIEWPORT_CONTROL_BASE_IDX 1 +#define regDB_SPI_VRS_CENTER_LOCATION 0x001a +#define regDB_SPI_VRS_CENTER_LOCATION_BASE_IDX 1 +#define regDB_SHADER_CONTROL 0x001b +#define regDB_SHADER_CONTROL_BASE_IDX 1 +#define regDB_DEPTH_CONTROL 0x001c +#define regDB_DEPTH_CONTROL_BASE_IDX 1 +#define regDB_STENCIL_CONTROL 0x001d +#define regDB_STENCIL_CONTROL_BASE_IDX 1 +#define regDB_EQAA 0x001e +#define regDB_EQAA_BASE_IDX 1 +#define regDB_ALPHA_TO_MASK 0x001f +#define regDB_ALPHA_TO_MASK_BASE_IDX 1 +#define regTA_BC_BASE_ADDR 0x0020 +#define regTA_BC_BASE_ADDR_BASE_IDX 1 +#define regTA_BC_BASE_ADDR_HI 0x0021 +#define regTA_BC_BASE_ADDR_HI_BASE_IDX 1 +#define regDB_STENCIL_REF 0x0022 +#define regDB_STENCIL_REF_BASE_IDX 1 +#define regDB_STENCIL_OPVAL 0x0023 +#define regDB_STENCIL_OPVAL_BASE_IDX 1 +#define regDB_STENCIL_READ_MASK 0x0024 +#define regDB_STENCIL_READ_MASK_BASE_IDX 1 +#define regDB_STENCIL_WRITE_MASK 0x0025 +#define regDB_STENCIL_WRITE_MASK_BASE_IDX 1 +#define regSC_MEM_TEMPORAL 0x003e +#define regSC_MEM_TEMPORAL_BASE_IDX 1 +#define regSC_MEM_SPEC_READ 0x003f +#define regSC_MEM_SPEC_READ_BASE_IDX 1 +#define regPA_SC_VPORT_0_TL 0x0040 +#define regPA_SC_VPORT_0_TL_BASE_IDX 1 +#define regPA_SC_VPORT_0_BR 0x0041 +#define regPA_SC_VPORT_0_BR_BASE_IDX 1 +#define regPA_SC_VPORT_1_TL 0x0042 +#define regPA_SC_VPORT_1_TL_BASE_IDX 1 +#define regPA_SC_VPORT_1_BR 0x0043 +#define regPA_SC_VPORT_1_BR_BASE_IDX 1 +#define regPA_SC_VPORT_2_TL 0x0044 +#define regPA_SC_VPORT_2_TL_BASE_IDX 1 +#define regPA_SC_VPORT_2_BR 0x0045 +#define regPA_SC_VPORT_2_BR_BASE_IDX 1 +#define regPA_SC_VPORT_3_TL 0x0046 +#define regPA_SC_VPORT_3_TL_BASE_IDX 1 +#define regPA_SC_VPORT_3_BR 0x0047 +#define regPA_SC_VPORT_3_BR_BASE_IDX 1 +#define regPA_SC_VPORT_4_TL 0x0048 +#define regPA_SC_VPORT_4_TL_BASE_IDX 1 +#define regPA_SC_VPORT_4_BR 0x0049 +#define regPA_SC_VPORT_4_BR_BASE_IDX 1 +#define regPA_SC_VPORT_5_TL 0x004a +#define regPA_SC_VPORT_5_TL_BASE_IDX 1 +#define regPA_SC_VPORT_5_BR 0x004b +#define regPA_SC_VPORT_5_BR_BASE_IDX 1 +#define regPA_SC_VPORT_6_TL 0x004c +#define regPA_SC_VPORT_6_TL_BASE_IDX 1 +#define regPA_SC_VPORT_6_BR 0x004d +#define regPA_SC_VPORT_6_BR_BASE_IDX 1 +#define regPA_SC_VPORT_7_TL 0x004e +#define regPA_SC_VPORT_7_TL_BASE_IDX 1 +#define regPA_SC_VPORT_7_BR 0x004f +#define regPA_SC_VPORT_7_BR_BASE_IDX 1 +#define regPA_SC_VPORT_8_TL 0x0050 +#define regPA_SC_VPORT_8_TL_BASE_IDX 1 +#define regPA_SC_VPORT_8_BR 0x0051 +#define regPA_SC_VPORT_8_BR_BASE_IDX 1 +#define regPA_SC_VPORT_9_TL 0x0052 +#define regPA_SC_VPORT_9_TL_BASE_IDX 1 +#define regPA_SC_VPORT_9_BR 0x0053 +#define regPA_SC_VPORT_9_BR_BASE_IDX 1 +#define regPA_SC_VPORT_10_TL 0x0054 +#define regPA_SC_VPORT_10_TL_BASE_IDX 1 +#define regPA_SC_VPORT_10_BR 0x0055 +#define regPA_SC_VPORT_10_BR_BASE_IDX 1 +#define regPA_SC_VPORT_11_TL 0x0056 +#define regPA_SC_VPORT_11_TL_BASE_IDX 1 +#define regPA_SC_VPORT_11_BR 0x0057 +#define regPA_SC_VPORT_11_BR_BASE_IDX 1 +#define regPA_SC_VPORT_12_TL 0x0058 +#define regPA_SC_VPORT_12_TL_BASE_IDX 1 +#define regPA_SC_VPORT_12_BR 0x0059 +#define regPA_SC_VPORT_12_BR_BASE_IDX 1 +#define regPA_SC_VPORT_13_TL 0x005a +#define regPA_SC_VPORT_13_TL_BASE_IDX 1 +#define regPA_SC_VPORT_13_BR 0x005b +#define regPA_SC_VPORT_13_BR_BASE_IDX 1 +#define regPA_SC_VPORT_14_TL 0x005c +#define regPA_SC_VPORT_14_TL_BASE_IDX 1 +#define regPA_SC_VPORT_14_BR 0x005d +#define regPA_SC_VPORT_14_BR_BASE_IDX 1 +#define regPA_SC_VPORT_15_TL 0x005e +#define regPA_SC_VPORT_15_TL_BASE_IDX 1 +#define regPA_SC_VPORT_15_BR 0x005f +#define regPA_SC_VPORT_15_BR_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_TL 0x0060 +#define regPA_SC_SCREEN_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_SCREEN_SCISSOR_BR 0x0061 +#define regPA_SC_SCREEN_SCISSOR_BR_BASE_IDX 1 +#define regPA_SC_WINDOW_OFFSET 0x0080 +#define regPA_SC_WINDOW_OFFSET_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_TL 0x0081 +#define regPA_SC_WINDOW_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_WINDOW_SCISSOR_BR 0x0082 +#define regPA_SC_WINDOW_SCISSOR_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_RULE 0x0083 +#define regPA_SC_CLIPRECT_RULE_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_TL 0x0084 +#define regPA_SC_CLIPRECT_0_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_BR 0x0085 +#define regPA_SC_CLIPRECT_0_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_TL 0x0086 +#define regPA_SC_CLIPRECT_1_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_BR 0x0087 +#define regPA_SC_CLIPRECT_1_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_TL 0x0088 +#define regPA_SC_CLIPRECT_2_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_BR 0x0089 +#define regPA_SC_CLIPRECT_2_BR_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_TL 0x008a +#define regPA_SC_CLIPRECT_3_TL_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_BR 0x008b +#define regPA_SC_CLIPRECT_3_BR_BASE_IDX 1 +#define regPA_SC_EDGERULE 0x008c +#define regPA_SC_EDGERULE_BASE_IDX 1 +#define regPA_SU_HARDWARE_SCREEN_OFFSET 0x008d +#define regPA_SU_HARDWARE_SCREEN_OFFSET_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_TL 0x0090 +#define regPA_SC_GENERIC_SCISSOR_TL_BASE_IDX 1 +#define regPA_SC_GENERIC_SCISSOR_BR 0x0091 +#define regPA_SC_GENERIC_SCISSOR_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_TL 0x0094 +#define regPA_SC_VPORT_SCISSOR_0_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_0_BR 0x0095 +#define regPA_SC_VPORT_SCISSOR_0_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_TL 0x0096 +#define regPA_SC_VPORT_SCISSOR_1_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_1_BR 0x0097 +#define regPA_SC_VPORT_SCISSOR_1_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_TL 0x0098 +#define regPA_SC_VPORT_SCISSOR_2_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_2_BR 0x0099 +#define regPA_SC_VPORT_SCISSOR_2_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_TL 0x009a +#define regPA_SC_VPORT_SCISSOR_3_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_3_BR 0x009b +#define regPA_SC_VPORT_SCISSOR_3_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_TL 0x009c +#define regPA_SC_VPORT_SCISSOR_4_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_4_BR 0x009d +#define regPA_SC_VPORT_SCISSOR_4_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_TL 0x009e +#define regPA_SC_VPORT_SCISSOR_5_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_5_BR 0x009f +#define regPA_SC_VPORT_SCISSOR_5_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_TL 0x00a0 +#define regPA_SC_VPORT_SCISSOR_6_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_6_BR 0x00a1 +#define regPA_SC_VPORT_SCISSOR_6_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_TL 0x00a2 +#define regPA_SC_VPORT_SCISSOR_7_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_7_BR 0x00a3 +#define regPA_SC_VPORT_SCISSOR_7_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_TL 0x00a4 +#define regPA_SC_VPORT_SCISSOR_8_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_8_BR 0x00a5 +#define regPA_SC_VPORT_SCISSOR_8_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_TL 0x00a6 +#define regPA_SC_VPORT_SCISSOR_9_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_9_BR 0x00a7 +#define regPA_SC_VPORT_SCISSOR_9_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_TL 0x00a8 +#define regPA_SC_VPORT_SCISSOR_10_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_10_BR 0x00a9 +#define regPA_SC_VPORT_SCISSOR_10_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_TL 0x00aa +#define regPA_SC_VPORT_SCISSOR_11_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_11_BR 0x00ab +#define regPA_SC_VPORT_SCISSOR_11_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_TL 0x00ac +#define regPA_SC_VPORT_SCISSOR_12_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_12_BR 0x00ad +#define regPA_SC_VPORT_SCISSOR_12_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_TL 0x00ae +#define regPA_SC_VPORT_SCISSOR_13_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_13_BR 0x00af +#define regPA_SC_VPORT_SCISSOR_13_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_TL 0x00b0 +#define regPA_SC_VPORT_SCISSOR_14_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_14_BR 0x00b1 +#define regPA_SC_VPORT_SCISSOR_14_BR_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_TL 0x00b2 +#define regPA_SC_VPORT_SCISSOR_15_TL_BASE_IDX 1 +#define regPA_SC_VPORT_SCISSOR_15_BR 0x00b3 +#define regPA_SC_VPORT_SCISSOR_15_BR_BASE_IDX 1 +#define regPA_CL_UCP_0_X 0x00b4 +#define regPA_CL_UCP_0_X_BASE_IDX 1 +#define regPA_CL_UCP_0_Y 0x00b5 +#define regPA_CL_UCP_0_Y_BASE_IDX 1 +#define regPA_CL_UCP_0_Z 0x00b6 +#define regPA_CL_UCP_0_Z_BASE_IDX 1 +#define regPA_CL_UCP_0_W 0x00b7 +#define regPA_CL_UCP_0_W_BASE_IDX 1 +#define regPA_CL_UCP_1_X 0x00b8 +#define regPA_CL_UCP_1_X_BASE_IDX 1 +#define regPA_CL_UCP_1_Y 0x00b9 +#define regPA_CL_UCP_1_Y_BASE_IDX 1 +#define regPA_CL_UCP_1_Z 0x00ba +#define regPA_CL_UCP_1_Z_BASE_IDX 1 +#define regPA_CL_UCP_1_W 0x00bb +#define regPA_CL_UCP_1_W_BASE_IDX 1 +#define regPA_CL_UCP_2_X 0x00bc +#define regPA_CL_UCP_2_X_BASE_IDX 1 +#define regPA_CL_UCP_2_Y 0x00bd +#define regPA_CL_UCP_2_Y_BASE_IDX 1 +#define regPA_CL_UCP_2_Z 0x00be +#define regPA_CL_UCP_2_Z_BASE_IDX 1 +#define regPA_CL_UCP_2_W 0x00bf +#define regPA_CL_UCP_2_W_BASE_IDX 1 +#define regPA_CL_UCP_3_X 0x00c0 +#define regPA_CL_UCP_3_X_BASE_IDX 1 +#define regPA_CL_UCP_3_Y 0x00c1 +#define regPA_CL_UCP_3_Y_BASE_IDX 1 +#define regPA_CL_UCP_3_Z 0x00c2 +#define regPA_CL_UCP_3_Z_BASE_IDX 1 +#define regPA_CL_UCP_3_W 0x00c3 +#define regPA_CL_UCP_3_W_BASE_IDX 1 +#define regPA_CL_UCP_4_X 0x00c4 +#define regPA_CL_UCP_4_X_BASE_IDX 1 +#define regPA_CL_UCP_4_Y 0x00c5 +#define regPA_CL_UCP_4_Y_BASE_IDX 1 +#define regPA_CL_UCP_4_Z 0x00c6 +#define regPA_CL_UCP_4_Z_BASE_IDX 1 +#define regPA_CL_UCP_4_W 0x00c7 +#define regPA_CL_UCP_4_W_BASE_IDX 1 +#define regPA_CL_UCP_5_X 0x00c8 +#define regPA_CL_UCP_5_X_BASE_IDX 1 +#define regPA_CL_UCP_5_Y 0x00c9 +#define regPA_CL_UCP_5_Y_BASE_IDX 1 +#define regPA_CL_UCP_5_Z 0x00ca +#define regPA_CL_UCP_5_Z_BASE_IDX 1 +#define regPA_CL_UCP_5_W 0x00cb +#define regPA_CL_UCP_5_W_BASE_IDX 1 +#define regPA_CL_PROG_NEAR_CLIP_Z 0x00cc +#define regPA_CL_PROG_NEAR_CLIP_Z_BASE_IDX 1 +#define regPA_RATE_CNTL 0x00cd +#define regPA_RATE_CNTL_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG 0x00d4 +#define regPA_SC_RASTER_CONFIG_BASE_IDX 1 +#define regPA_SC_RASTER_CONFIG_1 0x00d5 +#define regPA_SC_RASTER_CONFIG_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_CONTROL 0x00d6 +#define regPA_SC_SCREEN_EXTENT_CONTROL_BASE_IDX 1 +#define regPA_SC_TILE_STEERING_OVERRIDE 0x00d7 +#define regPA_SC_TILE_STEERING_OVERRIDE_BASE_IDX 1 +#define regPA_SC_CLIPRECT_0_EXT 0x00dd +#define regPA_SC_CLIPRECT_0_EXT_BASE_IDX 1 +#define regPA_SC_CLIPRECT_1_EXT 0x00de +#define regPA_SC_CLIPRECT_1_EXT_BASE_IDX 1 +#define regPA_SC_CLIPRECT_2_EXT 0x00df +#define regPA_SC_CLIPRECT_2_EXT_BASE_IDX 1 +#define regPA_SC_CLIPRECT_3_EXT 0x00e0 +#define regPA_SC_CLIPRECT_3_EXT_BASE_IDX 1 +#define regPA_SC_VRS_OVERRIDE_CNTL 0x00f4 +#define regPA_SC_VRS_OVERRIDE_CNTL_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE 0x00f5 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT 0x00f6 +#define regPA_SC_VRS_RATE_FEEDBACK_BASE_EXT_BASE_IDX 1 +#define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY 0x00f7 +#define regPA_SC_VRS_RATE_FEEDBACK_SIZE_XY_BASE_IDX 1 +#define regPA_SC_VRS_INFO 0x00f8 +#define regPA_SC_VRS_INFO_BASE_IDX 1 +#define regPA_SC_VRS_RATE_BASE 0x00fc +#define regPA_SC_VRS_RATE_BASE_BASE_IDX 1 +#define regPA_SC_VRS_RATE_BASE_EXT 0x00fd +#define regPA_SC_VRS_RATE_BASE_EXT_BASE_IDX 1 +#define regPA_SC_VRS_RATE_SIZE_XY 0x00fe +#define regPA_SC_VRS_RATE_SIZE_XY_BASE_IDX 1 +#define regCB_RMI_GL2_CACHE_CONTROL 0x0104 +#define regCB_RMI_GL2_CACHE_CONTROL_BASE_IDX 1 +#define regCB_BLEND_RED 0x0105 +#define regCB_BLEND_RED_BASE_IDX 1 +#define regCB_BLEND_GREEN 0x0106 +#define regCB_BLEND_GREEN_BASE_IDX 1 +#define regCB_BLEND_BLUE 0x0107 +#define regCB_BLEND_BLUE_BASE_IDX 1 +#define regCB_BLEND_ALPHA 0x0108 +#define regCB_BLEND_ALPHA_BASE_IDX 1 +#define regPA_CL_GB_VERT_CLIP_ADJ 0x010b +#define regPA_CL_GB_VERT_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_VERT_DISC_ADJ 0x010c +#define regPA_CL_GB_VERT_DISC_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_CLIP_ADJ 0x010d +#define regPA_CL_GB_HORZ_CLIP_ADJ_BASE_IDX 1 +#define regPA_CL_GB_HORZ_DISC_ADJ 0x010e +#define regPA_CL_GB_HORZ_DISC_ADJ_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE 0x010f +#define regPA_CL_VPORT_XSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET 0x0110 +#define regPA_CL_VPORT_XOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE 0x0111 +#define regPA_CL_VPORT_YSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET 0x0112 +#define regPA_CL_VPORT_YOFFSET_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE 0x0113 +#define regPA_CL_VPORT_ZSCALE_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET 0x0114 +#define regPA_CL_VPORT_ZOFFSET_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_0 0x0115 +#define regPA_SC_VPORT_ZMIN_0_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_0 0x0116 +#define regPA_SC_VPORT_ZMAX_0_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_1 0x0117 +#define regPA_CL_VPORT_XSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_1 0x0118 +#define regPA_CL_VPORT_XOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_1 0x0119 +#define regPA_CL_VPORT_YSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_1 0x011a +#define regPA_CL_VPORT_YOFFSET_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_1 0x011b +#define regPA_CL_VPORT_ZSCALE_1_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_1 0x011c +#define regPA_CL_VPORT_ZOFFSET_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_1 0x011d +#define regPA_SC_VPORT_ZMIN_1_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_1 0x011e +#define regPA_SC_VPORT_ZMAX_1_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_2 0x011f +#define regPA_CL_VPORT_XSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_2 0x0120 +#define regPA_CL_VPORT_XOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_2 0x0121 +#define regPA_CL_VPORT_YSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_2 0x0122 +#define regPA_CL_VPORT_YOFFSET_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_2 0x0123 +#define regPA_CL_VPORT_ZSCALE_2_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_2 0x0124 +#define regPA_CL_VPORT_ZOFFSET_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_2 0x0125 +#define regPA_SC_VPORT_ZMIN_2_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_2 0x0126 +#define regPA_SC_VPORT_ZMAX_2_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_3 0x0127 +#define regPA_CL_VPORT_XSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_3 0x0128 +#define regPA_CL_VPORT_XOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_3 0x0129 +#define regPA_CL_VPORT_YSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_3 0x012a +#define regPA_CL_VPORT_YOFFSET_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_3 0x012b +#define regPA_CL_VPORT_ZSCALE_3_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_3 0x012c +#define regPA_CL_VPORT_ZOFFSET_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_3 0x012d +#define regPA_SC_VPORT_ZMIN_3_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_3 0x012e +#define regPA_SC_VPORT_ZMAX_3_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_4 0x012f +#define regPA_CL_VPORT_XSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_4 0x0130 +#define regPA_CL_VPORT_XOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_4 0x0131 +#define regPA_CL_VPORT_YSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_4 0x0132 +#define regPA_CL_VPORT_YOFFSET_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_4 0x0133 +#define regPA_CL_VPORT_ZSCALE_4_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_4 0x0134 +#define regPA_CL_VPORT_ZOFFSET_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_4 0x0135 +#define regPA_SC_VPORT_ZMIN_4_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_4 0x0136 +#define regPA_SC_VPORT_ZMAX_4_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_5 0x0137 +#define regPA_CL_VPORT_XSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_5 0x0138 +#define regPA_CL_VPORT_XOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_5 0x0139 +#define regPA_CL_VPORT_YSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_5 0x013a +#define regPA_CL_VPORT_YOFFSET_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_5 0x013b +#define regPA_CL_VPORT_ZSCALE_5_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_5 0x013c +#define regPA_CL_VPORT_ZOFFSET_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_5 0x013d +#define regPA_SC_VPORT_ZMIN_5_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_5 0x013e +#define regPA_SC_VPORT_ZMAX_5_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_6 0x013f +#define regPA_CL_VPORT_XSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_6 0x0140 +#define regPA_CL_VPORT_XOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_6 0x0141 +#define regPA_CL_VPORT_YSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_6 0x0142 +#define regPA_CL_VPORT_YOFFSET_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_6 0x0143 +#define regPA_CL_VPORT_ZSCALE_6_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_6 0x0144 +#define regPA_CL_VPORT_ZOFFSET_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_6 0x0145 +#define regPA_SC_VPORT_ZMIN_6_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_6 0x0146 +#define regPA_SC_VPORT_ZMAX_6_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_7 0x0147 +#define regPA_CL_VPORT_XSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_7 0x0148 +#define regPA_CL_VPORT_XOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_7 0x0149 +#define regPA_CL_VPORT_YSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_7 0x014a +#define regPA_CL_VPORT_YOFFSET_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_7 0x014b +#define regPA_CL_VPORT_ZSCALE_7_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_7 0x014c +#define regPA_CL_VPORT_ZOFFSET_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_7 0x014d +#define regPA_SC_VPORT_ZMIN_7_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_7 0x014e +#define regPA_SC_VPORT_ZMAX_7_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_8 0x014f +#define regPA_CL_VPORT_XSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_8 0x0150 +#define regPA_CL_VPORT_XOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_8 0x0151 +#define regPA_CL_VPORT_YSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_8 0x0152 +#define regPA_CL_VPORT_YOFFSET_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_8 0x0153 +#define regPA_CL_VPORT_ZSCALE_8_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_8 0x0154 +#define regPA_CL_VPORT_ZOFFSET_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_8 0x0155 +#define regPA_SC_VPORT_ZMIN_8_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_8 0x0156 +#define regPA_SC_VPORT_ZMAX_8_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_9 0x0157 +#define regPA_CL_VPORT_XSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_9 0x0158 +#define regPA_CL_VPORT_XOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_9 0x0159 +#define regPA_CL_VPORT_YSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_9 0x015a +#define regPA_CL_VPORT_YOFFSET_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_9 0x015b +#define regPA_CL_VPORT_ZSCALE_9_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_9 0x015c +#define regPA_CL_VPORT_ZOFFSET_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_9 0x015d +#define regPA_SC_VPORT_ZMIN_9_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_9 0x015e +#define regPA_SC_VPORT_ZMAX_9_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_10 0x015f +#define regPA_CL_VPORT_XSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_10 0x0160 +#define regPA_CL_VPORT_XOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_10 0x0161 +#define regPA_CL_VPORT_YSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_10 0x0162 +#define regPA_CL_VPORT_YOFFSET_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_10 0x0163 +#define regPA_CL_VPORT_ZSCALE_10_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_10 0x0164 +#define regPA_CL_VPORT_ZOFFSET_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_10 0x0165 +#define regPA_SC_VPORT_ZMIN_10_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_10 0x0166 +#define regPA_SC_VPORT_ZMAX_10_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_11 0x0167 +#define regPA_CL_VPORT_XSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_11 0x0168 +#define regPA_CL_VPORT_XOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_11 0x0169 +#define regPA_CL_VPORT_YSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_11 0x016a +#define regPA_CL_VPORT_YOFFSET_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_11 0x016b +#define regPA_CL_VPORT_ZSCALE_11_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_11 0x016c +#define regPA_CL_VPORT_ZOFFSET_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_11 0x016d +#define regPA_SC_VPORT_ZMIN_11_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_11 0x016e +#define regPA_SC_VPORT_ZMAX_11_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_12 0x016f +#define regPA_CL_VPORT_XSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_12 0x0170 +#define regPA_CL_VPORT_XOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_12 0x0171 +#define regPA_CL_VPORT_YSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_12 0x0172 +#define regPA_CL_VPORT_YOFFSET_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_12 0x0173 +#define regPA_CL_VPORT_ZSCALE_12_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_12 0x0174 +#define regPA_CL_VPORT_ZOFFSET_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_12 0x0175 +#define regPA_SC_VPORT_ZMIN_12_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_12 0x0176 +#define regPA_SC_VPORT_ZMAX_12_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_13 0x0177 +#define regPA_CL_VPORT_XSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_13 0x0178 +#define regPA_CL_VPORT_XOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_13 0x0179 +#define regPA_CL_VPORT_YSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_13 0x017a +#define regPA_CL_VPORT_YOFFSET_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_13 0x017b +#define regPA_CL_VPORT_ZSCALE_13_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_13 0x017c +#define regPA_CL_VPORT_ZOFFSET_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_13 0x017d +#define regPA_SC_VPORT_ZMIN_13_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_13 0x017e +#define regPA_SC_VPORT_ZMAX_13_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_14 0x017f +#define regPA_CL_VPORT_XSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_14 0x0180 +#define regPA_CL_VPORT_XOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_14 0x0181 +#define regPA_CL_VPORT_YSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_14 0x0182 +#define regPA_CL_VPORT_YOFFSET_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_14 0x0183 +#define regPA_CL_VPORT_ZSCALE_14_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_14 0x0184 +#define regPA_CL_VPORT_ZOFFSET_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_14 0x0185 +#define regPA_SC_VPORT_ZMIN_14_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_14 0x0186 +#define regPA_SC_VPORT_ZMAX_14_BASE_IDX 1 +#define regPA_CL_VPORT_XSCALE_15 0x0187 +#define regPA_CL_VPORT_XSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_XOFFSET_15 0x0188 +#define regPA_CL_VPORT_XOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_YSCALE_15 0x0189 +#define regPA_CL_VPORT_YSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_YOFFSET_15 0x018a +#define regPA_CL_VPORT_YOFFSET_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZSCALE_15 0x018b +#define regPA_CL_VPORT_ZSCALE_15_BASE_IDX 1 +#define regPA_CL_VPORT_ZOFFSET_15 0x018c +#define regPA_CL_VPORT_ZOFFSET_15_BASE_IDX 1 +#define regPA_SC_VPORT_ZMIN_15 0x018d +#define regPA_SC_VPORT_ZMIN_15_BASE_IDX 1 +#define regPA_SC_VPORT_ZMAX_15 0x018e +#define regPA_SC_VPORT_ZMAX_15_BASE_IDX 1 +#define regSPI_PS_IN_CONTROL 0x0190 +#define regSPI_PS_IN_CONTROL_BASE_IDX 1 +#define regSPI_INTERP_CONTROL_0 0x0191 +#define regSPI_INTERP_CONTROL_0_BASE_IDX 1 +#define regSPI_SHADER_IDX_FORMAT 0x0192 +#define regSPI_SHADER_IDX_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_POS_FORMAT 0x0193 +#define regSPI_SHADER_POS_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_Z_FORMAT 0x0194 +#define regSPI_SHADER_Z_FORMAT_BASE_IDX 1 +#define regSPI_SHADER_COL_FORMAT 0x0195 +#define regSPI_SHADER_COL_FORMAT_BASE_IDX 1 +#define regSPI_BARYC_CNTL 0x0196 +#define regSPI_BARYC_CNTL_BASE_IDX 1 +#define regSPI_PS_INPUT_ENA 0x0197 +#define regSPI_PS_INPUT_ENA_BASE_IDX 1 +#define regSPI_PS_INPUT_ADDR 0x0198 +#define regSPI_PS_INPUT_ADDR_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_0 0x0199 +#define regSPI_PS_INPUT_CNTL_0_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_1 0x019a +#define regSPI_PS_INPUT_CNTL_1_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_2 0x019b +#define regSPI_PS_INPUT_CNTL_2_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_3 0x019c +#define regSPI_PS_INPUT_CNTL_3_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_4 0x019d +#define regSPI_PS_INPUT_CNTL_4_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_5 0x019e +#define regSPI_PS_INPUT_CNTL_5_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_6 0x019f +#define regSPI_PS_INPUT_CNTL_6_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_7 0x01a0 +#define regSPI_PS_INPUT_CNTL_7_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_8 0x01a1 +#define regSPI_PS_INPUT_CNTL_8_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_9 0x01a2 +#define regSPI_PS_INPUT_CNTL_9_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_10 0x01a3 +#define regSPI_PS_INPUT_CNTL_10_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_11 0x01a4 +#define regSPI_PS_INPUT_CNTL_11_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_12 0x01a5 +#define regSPI_PS_INPUT_CNTL_12_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_13 0x01a6 +#define regSPI_PS_INPUT_CNTL_13_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_14 0x01a7 +#define regSPI_PS_INPUT_CNTL_14_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_15 0x01a8 +#define regSPI_PS_INPUT_CNTL_15_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_16 0x01a9 +#define regSPI_PS_INPUT_CNTL_16_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_17 0x01aa +#define regSPI_PS_INPUT_CNTL_17_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_18 0x01ab +#define regSPI_PS_INPUT_CNTL_18_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_19 0x01ac +#define regSPI_PS_INPUT_CNTL_19_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_20 0x01ad +#define regSPI_PS_INPUT_CNTL_20_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_21 0x01ae +#define regSPI_PS_INPUT_CNTL_21_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_22 0x01af +#define regSPI_PS_INPUT_CNTL_22_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_23 0x01b0 +#define regSPI_PS_INPUT_CNTL_23_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_24 0x01b1 +#define regSPI_PS_INPUT_CNTL_24_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_25 0x01b2 +#define regSPI_PS_INPUT_CNTL_25_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_26 0x01b3 +#define regSPI_PS_INPUT_CNTL_26_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_27 0x01b4 +#define regSPI_PS_INPUT_CNTL_27_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_28 0x01b5 +#define regSPI_PS_INPUT_CNTL_28_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_29 0x01b6 +#define regSPI_PS_INPUT_CNTL_29_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_30 0x01b7 +#define regSPI_PS_INPUT_CNTL_30_BASE_IDX 1 +#define regSPI_PS_INPUT_CNTL_31 0x01b8 +#define regSPI_PS_INPUT_CNTL_31_BASE_IDX 1 +#define regSPI_BARYC_SSAA_CNTL 0x01b9 +#define regSPI_BARYC_SSAA_CNTL_BASE_IDX 1 +#define regSPI_TMPRING_SIZE 0x01ba +#define regSPI_TMPRING_SIZE_BASE_IDX 1 +#define regSPI_GFX_SCRATCH_BASE_LO 0x01bb +#define regSPI_GFX_SCRATCH_BASE_LO_BASE_IDX 1 +#define regSPI_GFX_SCRATCH_BASE_HI 0x01bc +#define regSPI_GFX_SCRATCH_BASE_HI_BASE_IDX 1 +#define regSX_PS_DOWNCONVERT_CONTROL 0x01d4 +#define regSX_PS_DOWNCONVERT_CONTROL_BASE_IDX 1 +#define regSX_PS_DOWNCONVERT 0x01d5 +#define regSX_PS_DOWNCONVERT_BASE_IDX 1 +#define regSX_BLEND_OPT_EPSILON 0x01d6 +#define regSX_BLEND_OPT_EPSILON_BASE_IDX 1 +#define regSX_BLEND_OPT_CONTROL 0x01d7 +#define regSX_BLEND_OPT_CONTROL_BASE_IDX 1 +#define regSX_MRT0_BLEND_OPT 0x01d8 +#define regSX_MRT0_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT1_BLEND_OPT 0x01d9 +#define regSX_MRT1_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT2_BLEND_OPT 0x01da +#define regSX_MRT2_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT3_BLEND_OPT 0x01db +#define regSX_MRT3_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT4_BLEND_OPT 0x01dc +#define regSX_MRT4_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT5_BLEND_OPT 0x01dd +#define regSX_MRT5_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT6_BLEND_OPT 0x01de +#define regSX_MRT6_BLEND_OPT_BASE_IDX 1 +#define regSX_MRT7_BLEND_OPT 0x01df +#define regSX_MRT7_BLEND_OPT_BASE_IDX 1 +#define regCB_BLEND0_CONTROL 0x01e0 +#define regCB_BLEND0_CONTROL_BASE_IDX 1 +#define regCB_BLEND1_CONTROL 0x01e1 +#define regCB_BLEND1_CONTROL_BASE_IDX 1 +#define regCB_BLEND2_CONTROL 0x01e2 +#define regCB_BLEND2_CONTROL_BASE_IDX 1 +#define regCB_BLEND3_CONTROL 0x01e3 +#define regCB_BLEND3_CONTROL_BASE_IDX 1 +#define regCB_BLEND4_CONTROL 0x01e4 +#define regCB_BLEND4_CONTROL_BASE_IDX 1 +#define regCB_BLEND5_CONTROL 0x01e5 +#define regCB_BLEND5_CONTROL_BASE_IDX 1 +#define regCB_BLEND6_CONTROL 0x01e6 +#define regCB_BLEND6_CONTROL_BASE_IDX 1 +#define regCB_BLEND7_CONTROL 0x01e7 +#define regCB_BLEND7_CONTROL_BASE_IDX 1 +#define regPA_CL_POINT_X_RAD 0x01f5 +#define regPA_CL_POINT_X_RAD_BASE_IDX 1 +#define regPA_CL_POINT_Y_RAD 0x01f6 +#define regPA_CL_POINT_Y_RAD_BASE_IDX 1 +#define regPA_CL_POINT_SIZE 0x01f7 +#define regPA_CL_POINT_SIZE_BASE_IDX 1 +#define regPA_CL_POINT_CULL_RAD 0x01f8 +#define regPA_CL_POINT_CULL_RAD_BASE_IDX 1 +#define regGE_MAX_OUTPUT_PER_SUBGROUP 0x01ff +#define regGE_MAX_OUTPUT_PER_SUBGROUP_BASE_IDX 1 +#define regPA_CL_CLIP_CNTL 0x0204 +#define regPA_CL_CLIP_CNTL_BASE_IDX 1 +#define regPA_CL_VTE_CNTL 0x0205 +#define regPA_CL_VTE_CNTL_BASE_IDX 1 +#define regPA_CL_VS_OUT_CNTL 0x0206 +#define regPA_CL_VS_OUT_CNTL_BASE_IDX 1 +#define regPA_SU_SC_MODE_CNTL 0x0207 +#define regPA_SU_SC_MODE_CNTL_BASE_IDX 1 +#define regPA_CL_NANINF_CNTL 0x0208 +#define regPA_CL_NANINF_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_CNTL 0x0209 +#define regPA_SU_LINE_STIPPLE_CNTL_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_SCALE 0x020a +#define regPA_SU_LINE_STIPPLE_SCALE_BASE_IDX 1 +#define regPA_SU_PRIM_FILTER_CNTL 0x020b +#define regPA_SU_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_SU_SMALL_PRIM_FILTER_CNTL 0x020c +#define regPA_SU_SMALL_PRIM_FILTER_CNTL_BASE_IDX 1 +#define regPA_CL_NGG_CNTL 0x020e +#define regPA_CL_NGG_CNTL_BASE_IDX 1 +#define regPA_SU_OVER_RASTERIZATION_CNTL 0x020f +#define regPA_SU_OVER_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_STEREO_CNTL 0x0210 +#define regPA_STEREO_CNTL_BASE_IDX 1 +#define regPA_STATE_STEREO_X 0x0211 +#define regPA_STATE_STEREO_X_BASE_IDX 1 +#define regPA_CL_VRS_CNTL 0x0212 +#define regPA_CL_VRS_CNTL_BASE_IDX 1 +#define regCB_TARGET_MASK 0x0214 +#define regCB_TARGET_MASK_BASE_IDX 1 +#define regCB_SHADER_MASK 0x0215 +#define regCB_SHADER_MASK_BASE_IDX 1 +#define regCB_COLOR_CONTROL 0x0216 +#define regCB_COLOR_CONTROL_BASE_IDX 1 +#define regPA_SU_POINT_SIZE 0x0280 +#define regPA_SU_POINT_SIZE_BASE_IDX 1 +#define regPA_SU_POINT_MINMAX 0x0281 +#define regPA_SU_POINT_MINMAX_BASE_IDX 1 +#define regPA_SU_LINE_CNTL 0x0282 +#define regPA_SU_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE 0x0283 +#define regPA_SC_LINE_STIPPLE_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE_RESET 0x0291 +#define regPA_SC_LINE_STIPPLE_RESET_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_0 0x0292 +#define regPA_SC_MODE_CNTL_0_BASE_IDX 1 +#define regPA_SC_MODE_CNTL_1 0x0293 +#define regPA_SC_MODE_CNTL_1_BASE_IDX 1 +#define regGE_SE_ENHANCE 0x0294 +#define regGE_SE_ENHANCE_BASE_IDX 1 +#define regVGT_REUSE_OFF 0x02a7 +#define regVGT_REUSE_OFF_BASE_IDX 1 +#define regVGT_DRAW_PAYLOAD_CNTL 0x02a8 +#define regVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 +#define regDB_HTILE_SURFACE 0x02af +#define regDB_HTILE_SURFACE_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE0 0x02b0 +#define regDB_SRESULTS_COMPARE_STATE0_BASE_IDX 1 +#define regDB_SRESULTS_COMPARE_STATE1 0x02b1 +#define regDB_SRESULTS_COMPARE_STATE1_BASE_IDX 1 +#define regVGT_GS_MAX_VERT_OUT 0x02ce +#define regVGT_GS_MAX_VERT_OUT_BASE_IDX 1 +#define regVGT_GS_INSTANCE_CNT 0x02cf +#define regVGT_GS_INSTANCE_CNT_BASE_IDX 1 +#define regGE_NGG_SUBGRP_CNTL 0x02d3 +#define regGE_NGG_SUBGRP_CNTL_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL 0x02de +#define regPA_SU_POLY_OFFSET_DB_FMT_CNTL_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_CLAMP 0x02df +#define regPA_SU_POLY_OFFSET_CLAMP_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE 0x02e0 +#define regPA_SU_POLY_OFFSET_FRONT_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET 0x02e1 +#define regPA_SU_POLY_OFFSET_FRONT_OFFSET_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_SCALE 0x02e2 +#define regPA_SU_POLY_OFFSET_BACK_SCALE_BASE_IDX 1 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET 0x02e3 +#define regPA_SU_POLY_OFFSET_BACK_OFFSET_BASE_IDX 1 +#define regPA_SC_HIZ_INFO 0x02e5 +#define regPA_SC_HIZ_INFO_BASE_IDX 1 +#define regPA_SC_HIS_INFO 0x02e6 +#define regPA_SC_HIS_INFO_BASE_IDX 1 +#define regPA_SC_HIZ_BASE 0x02e7 +#define regPA_SC_HIZ_BASE_BASE_IDX 1 +#define regPA_SC_HIZ_BASE_EXT 0x02e8 +#define regPA_SC_HIZ_BASE_EXT_BASE_IDX 1 +#define regPA_SC_HIZ_SIZE_XY 0x02e9 +#define regPA_SC_HIZ_SIZE_XY_BASE_IDX 1 +#define regPA_SC_HIS_BASE 0x02ea +#define regPA_SC_HIS_BASE_BASE_IDX 1 +#define regPA_SC_HIS_BASE_EXT 0x02eb +#define regPA_SC_HIS_BASE_EXT_BASE_IDX 1 +#define regPA_SC_HIS_SIZE_XY 0x02ec +#define regPA_SC_HIS_SIZE_XY_BASE_IDX 1 +#define regPA_SC_BINNER_OUTPUT_TIMEOUT_CNTL 0x02ed +#define regPA_SC_BINNER_OUTPUT_TIMEOUT_CNTL_BASE_IDX 1 +#define regPA_SC_BINNER_DYNAMIC_BATCH_LIMIT 0x02ee +#define regPA_SC_BINNER_DYNAMIC_BATCH_LIMIT_BASE_IDX 1 +#define regPA_SC_HISZ_CONTROL 0x02ef +#define regPA_SC_HISZ_CONTROL_BASE_IDX 1 +#define regPA_SC_HISZ_RENDER_OVERRIDE 0x02f0 +#define regPA_SC_HISZ_RENDER_OVERRIDE_BASE_IDX 1 +#define regPA_SC_LINE_CNTL 0x02f7 +#define regPA_SC_LINE_CNTL_BASE_IDX 1 +#define regPA_SC_AA_CONFIG 0x02f8 +#define regPA_SC_AA_CONFIG_BASE_IDX 1 +#define regPA_SU_VTX_CNTL 0x02f9 +#define regPA_SU_VTX_CNTL_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_0 0x02fc +#define regPA_SC_CENTROID_PRIORITY_0_BASE_IDX 1 +#define regPA_SC_CENTROID_PRIORITY_1 0x02fd +#define regPA_SC_CENTROID_PRIORITY_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x02fe +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0x02ff +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0x0300 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0x0301 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x0302 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0x0303 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0x0304 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0x0305 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x0306 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0x0307 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0x0308 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0x0309 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x030a +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0x030b +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0x030c +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2_BASE_IDX 1 +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0x030d +#define regPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y0_X1Y0 0x030e +#define regPA_SC_AA_MASK_X0Y0_X1Y0_BASE_IDX 1 +#define regPA_SC_AA_MASK_X0Y1_X1Y1 0x030f +#define regPA_SC_AA_MASK_X0Y1_X1Y1_BASE_IDX 1 +#define regPA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER 0x0310 +#define regPA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_0 0x0311 +#define regPA_SC_BINNER_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_1 0x0312 +#define regPA_SC_BINNER_CNTL_1_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_2 0x0313 +#define regPA_SC_BINNER_CNTL_2_BASE_IDX 1 +#define regPA_SC_NGG_MODE_CNTL 0x0314 +#define regPA_SC_NGG_MODE_CNTL_BASE_IDX 1 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL 0x0315 +#define regPA_SC_CONSERVATIVE_RASTERIZATION_CNTL_BASE_IDX 1 +#define regPA_SC_SHADER_CONTROL 0x0316 +#define regPA_SC_SHADER_CONTROL_BASE_IDX 1 +#define regPA_SC_SAMPLE_PROPERTIES 0x0317 +#define regPA_SC_SAMPLE_PROPERTIES_BASE_IDX 1 +#define regCB_COLOR0_BASE 0x0318 +#define regCB_COLOR0_BASE_BASE_IDX 1 +#define regCB_COLOR0_VIEW 0x0319 +#define regCB_COLOR0_VIEW_BASE_IDX 1 +#define regCB_COLOR0_VIEW2 0x031a +#define regCB_COLOR0_VIEW2_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB 0x031b +#define regCB_COLOR0_ATTRIB_BASE_IDX 1 +#define regCB_COLOR0_FDCC_CONTROL 0x031c +#define regCB_COLOR0_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB2 0x031e +#define regCB_COLOR0_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR0_ATTRIB3 0x031f +#define regCB_COLOR0_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR1_BASE 0x0321 +#define regCB_COLOR1_BASE_BASE_IDX 1 +#define regCB_COLOR1_VIEW 0x0322 +#define regCB_COLOR1_VIEW_BASE_IDX 1 +#define regCB_COLOR1_VIEW2 0x0323 +#define regCB_COLOR1_VIEW2_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB 0x0324 +#define regCB_COLOR1_ATTRIB_BASE_IDX 1 +#define regCB_COLOR1_FDCC_CONTROL 0x0325 +#define regCB_COLOR1_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB2 0x0327 +#define regCB_COLOR1_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR1_ATTRIB3 0x0328 +#define regCB_COLOR1_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR2_BASE 0x032a +#define regCB_COLOR2_BASE_BASE_IDX 1 +#define regCB_COLOR2_VIEW 0x032b +#define regCB_COLOR2_VIEW_BASE_IDX 1 +#define regCB_COLOR2_VIEW2 0x032c +#define regCB_COLOR2_VIEW2_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB 0x032d +#define regCB_COLOR2_ATTRIB_BASE_IDX 1 +#define regCB_COLOR2_FDCC_CONTROL 0x032e +#define regCB_COLOR2_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB2 0x0330 +#define regCB_COLOR2_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR2_ATTRIB3 0x0331 +#define regCB_COLOR2_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR3_BASE 0x0333 +#define regCB_COLOR3_BASE_BASE_IDX 1 +#define regCB_COLOR3_VIEW 0x0334 +#define regCB_COLOR3_VIEW_BASE_IDX 1 +#define regCB_COLOR3_VIEW2 0x0335 +#define regCB_COLOR3_VIEW2_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB 0x0336 +#define regCB_COLOR3_ATTRIB_BASE_IDX 1 +#define regCB_COLOR3_FDCC_CONTROL 0x0337 +#define regCB_COLOR3_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB2 0x0339 +#define regCB_COLOR3_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR3_ATTRIB3 0x033a +#define regCB_COLOR3_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR4_BASE 0x033c +#define regCB_COLOR4_BASE_BASE_IDX 1 +#define regCB_COLOR4_VIEW 0x033d +#define regCB_COLOR4_VIEW_BASE_IDX 1 +#define regCB_COLOR4_VIEW2 0x033e +#define regCB_COLOR4_VIEW2_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB 0x033f +#define regCB_COLOR4_ATTRIB_BASE_IDX 1 +#define regCB_COLOR4_FDCC_CONTROL 0x0340 +#define regCB_COLOR4_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB2 0x0342 +#define regCB_COLOR4_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR4_ATTRIB3 0x0343 +#define regCB_COLOR4_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR5_BASE 0x0345 +#define regCB_COLOR5_BASE_BASE_IDX 1 +#define regCB_COLOR5_VIEW 0x0346 +#define regCB_COLOR5_VIEW_BASE_IDX 1 +#define regCB_COLOR5_VIEW2 0x0347 +#define regCB_COLOR5_VIEW2_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB 0x0348 +#define regCB_COLOR5_ATTRIB_BASE_IDX 1 +#define regCB_COLOR5_FDCC_CONTROL 0x0349 +#define regCB_COLOR5_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB2 0x034b +#define regCB_COLOR5_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR5_ATTRIB3 0x034c +#define regCB_COLOR5_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR6_BASE 0x034e +#define regCB_COLOR6_BASE_BASE_IDX 1 +#define regCB_COLOR6_VIEW 0x034f +#define regCB_COLOR6_VIEW_BASE_IDX 1 +#define regCB_COLOR6_VIEW2 0x0350 +#define regCB_COLOR6_VIEW2_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB 0x0351 +#define regCB_COLOR6_ATTRIB_BASE_IDX 1 +#define regCB_COLOR6_FDCC_CONTROL 0x0352 +#define regCB_COLOR6_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB2 0x0354 +#define regCB_COLOR6_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR6_ATTRIB3 0x0355 +#define regCB_COLOR6_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR7_BASE 0x0357 +#define regCB_COLOR7_BASE_BASE_IDX 1 +#define regCB_COLOR7_VIEW 0x0358 +#define regCB_COLOR7_VIEW_BASE_IDX 1 +#define regCB_COLOR7_VIEW2 0x0359 +#define regCB_COLOR7_VIEW2_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB 0x035a +#define regCB_COLOR7_ATTRIB_BASE_IDX 1 +#define regCB_COLOR7_FDCC_CONTROL 0x035b +#define regCB_COLOR7_FDCC_CONTROL_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB2 0x035d +#define regCB_COLOR7_ATTRIB2_BASE_IDX 1 +#define regCB_COLOR7_ATTRIB3 0x035e +#define regCB_COLOR7_ATTRIB3_BASE_IDX 1 +#define regCB_COLOR0_BASE_EXT 0x0390 +#define regCB_COLOR0_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR1_BASE_EXT 0x0391 +#define regCB_COLOR1_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR2_BASE_EXT 0x0392 +#define regCB_COLOR2_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR3_BASE_EXT 0x0393 +#define regCB_COLOR3_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR4_BASE_EXT 0x0394 +#define regCB_COLOR4_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR5_BASE_EXT 0x0395 +#define regCB_COLOR5_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR6_BASE_EXT 0x0396 +#define regCB_COLOR6_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR7_BASE_EXT 0x0397 +#define regCB_COLOR7_BASE_EXT_BASE_IDX 1 +#define regCB_COLOR0_INFO 0x03b0 +#define regCB_COLOR0_INFO_BASE_IDX 1 +#define regCB_COLOR1_INFO 0x03b1 +#define regCB_COLOR1_INFO_BASE_IDX 1 +#define regCB_COLOR2_INFO 0x03b2 +#define regCB_COLOR2_INFO_BASE_IDX 1 +#define regCB_COLOR3_INFO 0x03b3 +#define regCB_COLOR3_INFO_BASE_IDX 1 +#define regCB_COLOR4_INFO 0x03b4 +#define regCB_COLOR4_INFO_BASE_IDX 1 +#define regCB_COLOR5_INFO 0x03b5 +#define regCB_COLOR5_INFO_BASE_IDX 1 +#define regCB_COLOR6_INFO 0x03b6 +#define regCB_COLOR6_INFO_BASE_IDX 1 +#define regCB_COLOR7_INFO 0x03b7 +#define regCB_COLOR7_INFO_BASE_IDX 1 +#define regCB_MEM0_INFO 0x03c0 +#define regCB_MEM0_INFO_BASE_IDX 1 +#define regCB_MEM1_INFO 0x03c1 +#define regCB_MEM1_INFO_BASE_IDX 1 +#define regCB_MEM2_INFO 0x03c2 +#define regCB_MEM2_INFO_BASE_IDX 1 +#define regCB_MEM3_INFO 0x03c3 +#define regCB_MEM3_INFO_BASE_IDX 1 +#define regCB_MEM4_INFO 0x03c4 +#define regCB_MEM4_INFO_BASE_IDX 1 +#define regCB_MEM5_INFO 0x03c5 +#define regCB_MEM5_INFO_BASE_IDX 1 +#define regCB_MEM6_INFO 0x03c6 +#define regCB_MEM6_INFO_BASE_IDX 1 +#define regCB_MEM7_INFO 0x03c7 +#define regCB_MEM7_INFO_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfvf_padec +// base address: 0x2a500 +#define regPA_SC_VRS_SURFACE_CNTL 0x0940 +#define regPA_SC_VRS_SURFACE_CNTL_BASE_IDX 1 +#define regPA_SC_ENHANCE 0x0941 +#define regPA_SC_ENHANCE_BASE_IDX 1 +#define regPA_SC_ENHANCE_1 0x0942 +#define regPA_SC_ENHANCE_1_BASE_IDX 1 +#define regPA_SC_ENHANCE_2 0x0943 +#define regPA_SC_ENHANCE_2_BASE_IDX 1 +#define regPA_SC_ENHANCE_3 0x0944 +#define regPA_SC_ENHANCE_3_BASE_IDX 1 +#define regPA_SC_BINNER_CNTL_OVERRIDE 0x0946 +#define regPA_SC_BINNER_CNTL_OVERRIDE_BASE_IDX 1 +#define regPA_SC_PBB_OVERRIDE_FLAG 0x0947 +#define regPA_SC_PBB_OVERRIDE_FLAG_BASE_IDX 1 +#define regPA_SC_DSM_CNTL 0x0948 +#define regPA_SC_DSM_CNTL_BASE_IDX 1 +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE 0x0949 +#define regPA_SC_TILE_STEERING_CREST_OVERRIDE_BASE_IDX 1 +#define regPA_SC_FIFO_SIZE 0x094a +#define regPA_SC_FIFO_SIZE_BASE_IDX 1 +#define regPA_SC_IF_FIFO_SIZE 0x094b +#define regPA_SC_IF_FIFO_SIZE_BASE_IDX 1 +#define regPA_SC_PACKER_WAVE_ID_CNTL 0x094c +#define regPA_SC_PACKER_WAVE_ID_CNTL_BASE_IDX 1 +#define regPA_SC_ATM_CNTL 0x094d +#define regPA_SC_ATM_CNTL_BASE_IDX 1 +#define regPA_SC_PKR_WAVE_TABLE_CNTL 0x094e +#define regPA_SC_PKR_WAVE_TABLE_CNTL_BASE_IDX 1 +#define regPA_SC_FORCE_EOV_MAX_CNTS 0x094f +#define regPA_SC_FORCE_EOV_MAX_CNTS_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_0 0x0950 +#define regPA_SC_BINNER_EVENT_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_1 0x0951 +#define regPA_SC_BINNER_EVENT_CNTL_1_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_2 0x0952 +#define regPA_SC_BINNER_EVENT_CNTL_2_BASE_IDX 1 +#define regPA_SC_BINNER_EVENT_CNTL_3 0x0953 +#define regPA_SC_BINNER_EVENT_CNTL_3_BASE_IDX 1 +#define regPA_SC_BINNER_TIMEOUT_COUNTER 0x0954 +#define regPA_SC_BINNER_TIMEOUT_COUNTER_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_0 0x0955 +#define regPA_SC_BINNER_PERF_CNTL_0_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_1 0x0956 +#define regPA_SC_BINNER_PERF_CNTL_1_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_2 0x0957 +#define regPA_SC_BINNER_PERF_CNTL_2_BASE_IDX 1 +#define regPA_SC_BINNER_PERF_CNTL_3 0x0958 +#define regPA_SC_BINNER_PERF_CNTL_3_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x095b +#define regPA_SC_P3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x095c +#define regPA_SC_HP3D_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_HV_LOCK 0x095d +#define regPA_SC_TRAP_SCREEN_HV_LOCK_BASE_IDX 1 +#define regPA_PH_INTERFACE_FIFO_SIZE 0x095e +#define regPA_PH_INTERFACE_FIFO_SIZE_BASE_IDX 1 +#define regPA_PH_ENHANCE 0x095f +#define regPA_PH_ENHANCE_BASE_IDX 1 +#define regPA_SC_VRS_SURFACE_CNTL_1 0x0960 +#define regPA_SC_VRS_SURFACE_CNTL_1_BASE_IDX 1 +#define regPA_SC_HIZ_SURFACE_CNTL 0x0961 +#define regPA_SC_HIZ_SURFACE_CNTL_BASE_IDX 1 +#define regPA_SC_HIS_SURFACE_CNTL 0x0962 +#define regPA_SC_HIS_SURFACE_CNTL_BASE_IDX 1 +#define regPA_SC_HIZ_DEBUG 0x0963 +#define regPA_SC_HIZ_DEBUG_BASE_IDX 1 +#define regPA_SC_HIS_DEBUG 0x0964 +#define regPA_SC_HIS_DEBUG_BASE_IDX 1 +#define regSC_MEM_SCOPE 0x0965 +#define regSC_MEM_SCOPE_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfvf_sqdec +// base address: 0x2a780 +#define regSQ_RUNTIME_CONFIG 0x09e0 +#define regSQ_RUNTIME_CONFIG_BASE_IDX 1 +#define regSQ_DEBUG_STS_GLOBAL 0x09e1 +#define regSQ_DEBUG_STS_GLOBAL_BASE_IDX 1 +#define regSQ_DEBUG_STS_GLOBAL2 0x09e2 +#define regSQ_DEBUG_STS_GLOBAL2_BASE_IDX 1 +#define regSH_MEM_BASES 0x09e3 +#define regSH_MEM_BASES_BASE_IDX 1 +#define regSH_MEM_CONFIG 0x09e4 +#define regSH_MEM_CONFIG_BASE_IDX 1 +#define regSQ_DEBUG 0x09e5 +#define regSQ_DEBUG_BASE_IDX 1 +#define regSQ_SHADER_TBA_LO 0x09e6 +#define regSQ_SHADER_TBA_LO_BASE_IDX 1 +#define regSQ_SHADER_TBA_HI 0x09e7 +#define regSQ_SHADER_TBA_HI_BASE_IDX 1 +#define regSQ_SHADER_TMA_LO 0x09e8 +#define regSQ_SHADER_TMA_LO_BASE_IDX 1 +#define regSQ_SHADER_TMA_HI 0x09e9 +#define regSQ_SHADER_TMA_HI_BASE_IDX 1 +#define regSQ_IND_INDEX_USER 0x09ea +#define regSQ_IND_INDEX_USER_BASE_IDX 1 +#define regSQ_CMD_USER 0x09eb +#define regSQ_CMD_USER_BASE_IDX 1 +#define regSQ_IND_DATA_USER 0x09ec +#define regSQ_IND_DATA_USER_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_spidec +// base address: 0x2e500 +#define regSPI_CDBG_SYS_GFX 0x1940 +#define regSPI_CDBG_SYS_GFX_BASE_IDX 1 +#define regSPI_CDBG_SYS_HP3D 0x1941 +#define regSPI_CDBG_SYS_HP3D_BASE_IDX 1 +#define regSPI_CDBG_SYS_CS0 0x1942 +#define regSPI_CDBG_SYS_CS0_BASE_IDX 1 +#define regSPI_GDBG_WAVE_CNTL 0x1943 +#define regSPI_GDBG_WAVE_CNTL_BASE_IDX 1 +#define regSPI_GDBG_TRAP_CONFIG 0x1944 +#define regSPI_GDBG_TRAP_CONFIG_BASE_IDX 1 +#define regSPI_GDBG_WAVE_CNTL3 0x1945 +#define regSPI_GDBG_WAVE_CNTL3_BASE_IDX 1 +#define regSPI_RESET_DEBUG 0x1946 +#define regSPI_RESET_DEBUG_BASE_IDX 1 +#define regGDS_COMPUTE_MAX_WAVE_ID 0x1947 +#define regGDS_COMPUTE_MAX_WAVE_ID_BASE_IDX 1 +#define regSPI_ARB_CNTL_0 0x1949 +#define regSPI_ARB_CNTL_0_BASE_IDX 1 +#define regSPI_FEATURE_CTRL 0x194a +#define regSPI_FEATURE_CTRL_BASE_IDX 1 +#define regSPI_SHADER_RSRC_LIMIT_CTRL 0x194b +#define regSPI_SHADER_RSRC_LIMIT_CTRL_BASE_IDX 1 +#define regPC_CONFIG_CNTL_0 0x194c +#define regPC_CONFIG_CNTL_0_BASE_IDX 1 +#define regPC_CONFIG_CNTL_1 0x194d +#define regPC_CONFIG_CNTL_1_BASE_IDX 1 +#define regSPI_COMPUTE_WF_CTX_SAVE_STATUS 0x194e +#define regSPI_COMPUTE_WF_CTX_SAVE_STATUS_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_utcl1dec +// base address: 0x2e600 +#define regUTCL1_CTRL_0 0x1980 +#define regUTCL1_CTRL_0_BASE_IDX 1 +#define regUTCL1_UTCL0_INVREQ_DISABLE 0x1981 +#define regUTCL1_UTCL0_INVREQ_DISABLE_BASE_IDX 1 +#define regUTCL1_CTRL_2 0x1982 +#define regUTCL1_CTRL_2_BASE_IDX 1 +#define regUTCL1_FIFO_SIZING 0x1983 +#define regUTCL1_FIFO_SIZING_BASE_IDX 1 +#define regGCRD_SA0_TARGETS_DISABLE 0x1984 +#define regGCRD_SA0_TARGETS_DISABLE_BASE_IDX 1 +#define regGCRD_SA1_TARGETS_DISABLE 0x1985 +#define regGCRD_SA1_TARGETS_DISABLE_BASE_IDX 1 +#define regGCRD_CREDIT_SAFE 0x1986 +#define regGCRD_CREDIT_SAFE_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE0 0x1987 +#define regUTCL1_IDENTITY_MODE0_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE1 0x1988 +#define regUTCL1_IDENTITY_MODE1_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE2 0x1989 +#define regUTCL1_IDENTITY_MODE2_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE3 0x198a +#define regUTCL1_IDENTITY_MODE3_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE4 0x198b +#define regUTCL1_IDENTITY_MODE4_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE5 0x198c +#define regUTCL1_IDENTITY_MODE5_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE6 0x198d +#define regUTCL1_IDENTITY_MODE6_BASE_IDX 1 +#define regUTCL1_IDENTITY_MODE7 0x198e +#define regUTCL1_IDENTITY_MODE7_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_tcpdec +// base address: 0x2ef40 +#define regTCP_INVALIDATE 0x1bd0 +#define regTCP_INVALIDATE_BASE_IDX 1 +#define regTCP_STATUS 0x1bd1 +#define regTCP_STATUS_BASE_IDX 1 +#define regTCP_CNTL 0x1bd2 +#define regTCP_CNTL_BASE_IDX 1 +#define regTCP_CNTL2 0x1bd3 +#define regTCP_CNTL2_BASE_IDX 1 +#define regTCP_CREDIT 0x1bd4 +#define regTCP_CREDIT_BASE_IDX 1 +#define regTCP_DEBUG_DATA 0x1bd6 +#define regTCP_DEBUG_DATA_BASE_IDX 1 +#define regTCP_COMPRESSION_CNTL 0x1bd7 +#define regTCP_COMPRESSION_CNTL_BASE_IDX 1 +#define regTCP_ARB 0x1bd8 +#define regTCP_ARB_BASE_IDX 1 +#define regTCP_UTCL0_CNTL1 0x1bd9 +#define regTCP_UTCL0_CNTL1_BASE_IDX 1 +#define regTCP_UTCL0_CNTL2 0x1bda +#define regTCP_UTCL0_CNTL2_BASE_IDX 1 +#define regTCP_UTCL0_STATUS 0x1bdb +#define regTCP_UTCL0_STATUS_BASE_IDX 1 +#define regTCP_RQID_HASH_CNTL 0x1bdc +#define regTCP_RQID_HASH_CNTL_BASE_IDX 1 +#define regTCP_SET_HASH_CFG 0x1bdd +#define regTCP_SET_HASH_CFG_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_64_SET0 0x1bde +#define regTCP_SET_HASH_MASK_64_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_64_SET1 0x1bdf +#define regTCP_SET_HASH_MASK_64_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_64_SET2 0x1be0 +#define regTCP_SET_HASH_MASK_64_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_64_SET3 0x1be1 +#define regTCP_SET_HASH_MASK_64_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_128_SET0 0x1be2 +#define regTCP_SET_HASH_MASK_128_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_128_SET1 0x1be3 +#define regTCP_SET_HASH_MASK_128_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_128_SET2 0x1be4 +#define regTCP_SET_HASH_MASK_128_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_128_SET3 0x1be5 +#define regTCP_SET_HASH_MASK_128_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_128_SET4 0x1be6 +#define regTCP_SET_HASH_MASK_128_SET4_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_192_SET0 0x1be7 +#define regTCP_SET_HASH_MASK_192_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_192_SET1 0x1be8 +#define regTCP_SET_HASH_MASK_192_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_192_SET2 0x1be9 +#define regTCP_SET_HASH_MASK_192_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_192_SET3 0x1bea +#define regTCP_SET_HASH_MASK_192_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET0 0x1beb +#define regTCP_SET_HASH_MASK_256_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET1 0x1bec +#define regTCP_SET_HASH_MASK_256_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET2 0x1bed +#define regTCP_SET_HASH_MASK_256_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET3 0x1bee +#define regTCP_SET_HASH_MASK_256_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET4 0x1bef +#define regTCP_SET_HASH_MASK_256_SET4_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_256_SET5 0x1bf0 +#define regTCP_SET_HASH_MASK_256_SET5_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_320_SET0 0x1bf1 +#define regTCP_SET_HASH_MASK_320_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_320_SET1 0x1bf2 +#define regTCP_SET_HASH_MASK_320_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_320_SET2 0x1bf3 +#define regTCP_SET_HASH_MASK_320_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_320_SET3 0x1bf4 +#define regTCP_SET_HASH_MASK_320_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_384_SET0 0x1bf5 +#define regTCP_SET_HASH_MASK_384_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_384_SET1 0x1bf6 +#define regTCP_SET_HASH_MASK_384_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_384_SET2 0x1bf7 +#define regTCP_SET_HASH_MASK_384_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_384_SET3 0x1bf8 +#define regTCP_SET_HASH_MASK_384_SET3_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_384_SET4 0x1bf9 +#define regTCP_SET_HASH_MASK_384_SET4_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_448_SET0 0x1bfa +#define regTCP_SET_HASH_MASK_448_SET0_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_448_SET1 0x1bfb +#define regTCP_SET_HASH_MASK_448_SET1_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_448_SET2 0x1bfc +#define regTCP_SET_HASH_MASK_448_SET2_BASE_IDX 1 +#define regTCP_SET_HASH_MASK_448_SET3 0x1bfd +#define regTCP_SET_HASH_MASK_448_SET3_BASE_IDX 1 +#define regTCP_CNTL3 0x1bfe +#define regTCP_CNTL3_BASE_IDX 1 +#define regLDS_CONFIG 0x1bff +#define regLDS_CONFIG_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly2_spidec +// base address: 0x2f000 +#define regSPI_RESOURCE_RESERVE_CU_0 0x1c00 +#define regSPI_RESOURCE_RESERVE_CU_0_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_1 0x1c01 +#define regSPI_RESOURCE_RESERVE_CU_1_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_2 0x1c02 +#define regSPI_RESOURCE_RESERVE_CU_2_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_3 0x1c03 +#define regSPI_RESOURCE_RESERVE_CU_3_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_4 0x1c04 +#define regSPI_RESOURCE_RESERVE_CU_4_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_5 0x1c05 +#define regSPI_RESOURCE_RESERVE_CU_5_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_6 0x1c06 +#define regSPI_RESOURCE_RESERVE_CU_6_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_7 0x1c07 +#define regSPI_RESOURCE_RESERVE_CU_7_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_8 0x1c08 +#define regSPI_RESOURCE_RESERVE_CU_8_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_9 0x1c09 +#define regSPI_RESOURCE_RESERVE_CU_9_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_10 0x1c0a +#define regSPI_RESOURCE_RESERVE_CU_10_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_11 0x1c0b +#define regSPI_RESOURCE_RESERVE_CU_11_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_12 0x1c0c +#define regSPI_RESOURCE_RESERVE_CU_12_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_13 0x1c0d +#define regSPI_RESOURCE_RESERVE_CU_13_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_14 0x1c0e +#define regSPI_RESOURCE_RESERVE_CU_14_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_CU_15 0x1c0f +#define regSPI_RESOURCE_RESERVE_CU_15_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_0 0x1c10 +#define regSPI_RESOURCE_RESERVE_EN_CU_0_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_1 0x1c11 +#define regSPI_RESOURCE_RESERVE_EN_CU_1_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_2 0x1c12 +#define regSPI_RESOURCE_RESERVE_EN_CU_2_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_3 0x1c13 +#define regSPI_RESOURCE_RESERVE_EN_CU_3_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_4 0x1c14 +#define regSPI_RESOURCE_RESERVE_EN_CU_4_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_5 0x1c15 +#define regSPI_RESOURCE_RESERVE_EN_CU_5_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_6 0x1c16 +#define regSPI_RESOURCE_RESERVE_EN_CU_6_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_7 0x1c17 +#define regSPI_RESOURCE_RESERVE_EN_CU_7_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_8 0x1c18 +#define regSPI_RESOURCE_RESERVE_EN_CU_8_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_9 0x1c19 +#define regSPI_RESOURCE_RESERVE_EN_CU_9_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_10 0x1c1a +#define regSPI_RESOURCE_RESERVE_EN_CU_10_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_11 0x1c1b +#define regSPI_RESOURCE_RESERVE_EN_CU_11_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_12 0x1c1c +#define regSPI_RESOURCE_RESERVE_EN_CU_12_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_13 0x1c1d +#define regSPI_RESOURCE_RESERVE_EN_CU_13_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_14 0x1c1e +#define regSPI_RESOURCE_RESERVE_EN_CU_14_BASE_IDX 1 +#define regSPI_RESOURCE_RESERVE_EN_CU_15 0x1c1f +#define regSPI_RESOURCE_RESERVE_EN_CU_15_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly2_tcpdec +// base address: 0x2f4c0 +#define regTCP_UTCL0_THRASHING_CTRL 0x1d30 +#define regTCP_UTCL0_THRASHING_CTRL_BASE_IDX 1 +#define regTCP_UTCL0_RETRY_THRESHOLD_DOWN_COUNTER 0x1d31 +#define regTCP_UTCL0_RETRY_THRESHOLD_DOWN_COUNTER_BASE_IDX 1 +#define regTCP_UTCL0_RETRY_THRESHOLD_UP_COUNTER 0x1d32 +#define regTCP_UTCL0_RETRY_THRESHOLD_UP_COUNTER_BASE_IDX 1 +#define regTCP_UTCL0_XNACK_RETRY 0x1d33 +#define regTCP_UTCL0_XNACK_RETRY_BASE_IDX 1 +#define regTCP_UTCL0_RETRY_TIMER_THRESHOLD_LO 0x1d34 +#define regTCP_UTCL0_RETRY_TIMER_THRESHOLD_LO_BASE_IDX 1 +#define regTCP_UTCL0_RETRY_TIMER_THRESHOLD_HI 0x1d35 +#define regTCP_UTCL0_RETRY_TIMER_THRESHOLD_HI_BASE_IDX 1 +#define regTXA_CNTL 0x1d36 +#define regTXA_CNTL_BASE_IDX 1 +#define regTXA_CNTL_AUX 0x1d37 +#define regTXA_CNTL_AUX_BASE_IDX 1 +#define regTXA_CNTL2 0x1d38 +#define regTXA_CNTL2_BASE_IDX 1 +#define regTXA_STATUS 0x1d39 +#define regTXA_STATUS_BASE_IDX 1 +#define regTXA_TDM_ARB_CNTL 0x1d3a +#define regTXA_TDM_ARB_CNTL_BASE_IDX 1 +#define regTCP_CREDIT2 0x1d3b +#define regTCP_CREDIT2_BASE_IDX 1 +#define regVC_CONGESTION_CONTROL 0x1d3c +#define regVC_CONGESTION_CONTROL_BASE_IDX 1 +#define regTXA_TDM_CNTL 0x1d3d +#define regTXA_TDM_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gfxudec +// base address: 0x30000 +#define regVGT_TF_RING_SIZE 0x224e +#define regVGT_TF_RING_SIZE_BASE_IDX 1 +#define regVGT_HS_OFFCHIP_PARAM 0x224f +#define regVGT_HS_OFFCHIP_PARAM_BASE_IDX 1 +#define regGE_POS_RING_BASE 0x2268 +#define regGE_POS_RING_BASE_BASE_IDX 1 +#define regGE_POS_RING_SIZE 0x2269 +#define regGE_POS_RING_SIZE_BASE_IDX 1 +#define regGE_PRIM_RING_BASE 0x226a +#define regGE_PRIM_RING_BASE_BASE_IDX 1 +#define regGE_PRIM_RING_SIZE 0x226b +#define regGE_PRIM_RING_SIZE_BASE_IDX 1 +#define regPA_SU_LINE_STIPPLE_VALUE 0x2280 +#define regPA_SU_LINE_STIPPLE_VALUE_BASE_IDX 1 +#define regPA_SC_LINE_STIPPLE_STATE 0x2281 +#define regPA_SC_LINE_STIPPLE_STATE_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_0 0x2284 +#define regPA_SC_SCREEN_EXTENT_MIN_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_0 0x2285 +#define regPA_SC_SCREEN_EXTENT_MAX_0_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MIN_1 0x2286 +#define regPA_SC_SCREEN_EXTENT_MIN_1_BASE_IDX 1 +#define regPA_SC_SCREEN_EXTENT_MAX_1 0x228b +#define regPA_SC_SCREEN_EXTENT_MAX_1_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN 0x22a0 +#define regPA_SC_P3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_H 0x22a1 +#define regPA_SC_P3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_V 0x22a2 +#define regPA_SC_P3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0x22a3 +#define regPA_SC_P3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT 0x22a4 +#define regPA_SC_P3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN 0x22a8 +#define regPA_SC_HP3D_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_H 0x22a9 +#define regPA_SC_HP3D_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_V 0x22aa +#define regPA_SC_HP3D_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0x22ab +#define regPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT 0x22ac +#define regPA_SC_HP3D_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_HV_EN 0x22b0 +#define regPA_SC_TRAP_SCREEN_HV_EN_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_H 0x22b1 +#define regPA_SC_TRAP_SCREEN_H_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_V 0x22b2 +#define regPA_SC_TRAP_SCREEN_V_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE 0x22b3 +#define regPA_SC_TRAP_SCREEN_OCCURRENCE_BASE_IDX 1 +#define regPA_SC_TRAP_SCREEN_COUNT 0x22b4 +#define regPA_SC_TRAP_SCREEN_COUNT_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_0 0x2340 +#define regSQ_THREAD_TRACE_USERDATA_0_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_1 0x2341 +#define regSQ_THREAD_TRACE_USERDATA_1_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_2 0x2342 +#define regSQ_THREAD_TRACE_USERDATA_2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_3 0x2343 +#define regSQ_THREAD_TRACE_USERDATA_3_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_4 0x2344 +#define regSQ_THREAD_TRACE_USERDATA_4_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_5 0x2345 +#define regSQ_THREAD_TRACE_USERDATA_5_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_6 0x2346 +#define regSQ_THREAD_TRACE_USERDATA_6_BASE_IDX 1 +#define regSQ_THREAD_TRACE_USERDATA_7 0x2347 +#define regSQ_THREAD_TRACE_USERDATA_7_BASE_IDX 1 +#define regSQC_CACHES 0x2348 +#define regSQC_CACHES_BASE_IDX 1 +#define regTA_CS_BC_BASE_ADDR 0x2380 +#define regTA_CS_BC_BASE_ADDR_BASE_IDX 1 +#define regTA_CS_BC_BASE_ADDR_HI 0x2381 +#define regTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_LOW 0x23c0 +#define regDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT0_HI 0x23c1 +#define regDB_OCCLUSION_COUNT0_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_LOW 0x23c2 +#define regDB_OCCLUSION_COUNT1_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT1_HI 0x23c3 +#define regDB_OCCLUSION_COUNT1_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_LOW 0x23c4 +#define regDB_OCCLUSION_COUNT2_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT2_HI 0x23c5 +#define regDB_OCCLUSION_COUNT2_HI_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_LOW 0x23c6 +#define regDB_OCCLUSION_COUNT3_LOW_BASE_IDX 1 +#define regDB_OCCLUSION_COUNT3_HI 0x23c7 +#define regDB_OCCLUSION_COUNT3_HI_BASE_IDX 1 +#define regSPI_CONFIG_CNTL 0x2440 +#define regSPI_CONFIG_CNTL_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_1 0x2441 +#define regSPI_CONFIG_CNTL_1_BASE_IDX 1 +#define regSPI_CONFIG_CNTL_2 0x2442 +#define regSPI_CONFIG_CNTL_2_BASE_IDX 1 +#define regSPI_GS_THROTTLE_CNTL1 0x2444 +#define regSPI_GS_THROTTLE_CNTL1_BASE_IDX 1 +#define regSPI_GS_THROTTLE_CNTL2 0x2445 +#define regSPI_GS_THROTTLE_CNTL2_BASE_IDX 1 +#define regSPI_ATTRIBUTE_RING_BASE 0x2446 +#define regSPI_ATTRIBUTE_RING_BASE_BASE_IDX 1 +#define regSPI_ATTRIBUTE_RING_SIZE 0x2447 +#define regSPI_ATTRIBUTE_RING_SIZE_BASE_IDX 1 +#define regSPI_SQG_EVENT_CTL 0x2448 +#define regSPI_SQG_EVENT_CTL_BASE_IDX 1 +#define regSPI_COMPUTE_WGS_CONTROL 0x2449 +#define regSPI_COMPUTE_WGS_CONTROL_BASE_IDX 1 +#define regSPI_GRP_LAUNCH_GUARANTEE_ENABLE 0x244a +#define regSPI_GRP_LAUNCH_GUARANTEE_ENABLE_BASE_IDX 1 +#define regSPI_GRP_LAUNCH_GUARANTEE_CTRL 0x244b +#define regSPI_GRP_LAUNCH_GUARANTEE_CTRL_BASE_IDX 1 +#define regSPI_GOG_ALLOCATION_CTRL 0x244c +#define regSPI_GOG_ALLOCATION_CTRL_BASE_IDX 1 +#define regSPI_TCP_CNTL 0x244d +#define regSPI_TCP_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_comp_wgsdec +// base address: 0x31a00 +#define regWGS_COMPUTE_DISPATCH_INITIATOR 0x2680 +#define regWGS_COMPUTE_DISPATCH_INITIATOR_BASE_IDX 1 +#define regWGS_COMPUTE_DIM_X 0x2681 +#define regWGS_COMPUTE_DIM_X_BASE_IDX 1 +#define regWGS_COMPUTE_DIM_Y 0x2682 +#define regWGS_COMPUTE_DIM_Y_BASE_IDX 1 +#define regWGS_COMPUTE_DIM_Z 0x2683 +#define regWGS_COMPUTE_DIM_Z_BASE_IDX 1 +#define regWGS_COMPUTE_START_X 0x2684 +#define regWGS_COMPUTE_START_X_BASE_IDX 1 +#define regWGS_COMPUTE_START_Y 0x2685 +#define regWGS_COMPUTE_START_Y_BASE_IDX 1 +#define regWGS_COMPUTE_START_Z 0x2686 +#define regWGS_COMPUTE_START_Z_BASE_IDX 1 +#define regWGS_COMPUTE_NUM_THREAD_X 0x2687 +#define regWGS_COMPUTE_NUM_THREAD_X_BASE_IDX 1 +#define regWGS_COMPUTE_NUM_THREAD_Y 0x2688 +#define regWGS_COMPUTE_NUM_THREAD_Y_BASE_IDX 1 +#define regWGS_COMPUTE_NUM_THREAD_Z 0x2689 +#define regWGS_COMPUTE_NUM_THREAD_Z_BASE_IDX 1 +#define regWGS_COMPUTE_PIPELINESTAT_ENABLE 0x268a +#define regWGS_COMPUTE_PIPELINESTAT_ENABLE_BASE_IDX 1 +#define regWGS_COMPUTE_PERFCOUNT_ENABLE 0x268b +#define regWGS_COMPUTE_PERFCOUNT_ENABLE_BASE_IDX 1 +#define regWGS_COMPUTE_PGM_LO 0x268c +#define regWGS_COMPUTE_PGM_LO_BASE_IDX 1 +#define regWGS_COMPUTE_PGM_HI 0x268d +#define regWGS_COMPUTE_PGM_HI_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_PKT_ADDR_LO 0x268e +#define regWGS_COMPUTE_DISPATCH_PKT_ADDR_LO_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_PKT_ADDR_HI 0x268f +#define regWGS_COMPUTE_DISPATCH_PKT_ADDR_HI_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_SCRATCH_BASE_LO 0x2690 +#define regWGS_COMPUTE_DISPATCH_SCRATCH_BASE_LO_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_SCRATCH_BASE_HI 0x2691 +#define regWGS_COMPUTE_DISPATCH_SCRATCH_BASE_HI_BASE_IDX 1 +#define regWGS_COMPUTE_PGM_RSRC1 0x2692 +#define regWGS_COMPUTE_PGM_RSRC1_BASE_IDX 1 +#define regWGS_COMPUTE_PGM_RSRC2 0x2693 +#define regWGS_COMPUTE_PGM_RSRC2_BASE_IDX 1 +#define regWGS_COMPUTE_VMID 0x2694 +#define regWGS_COMPUTE_VMID_BASE_IDX 1 +#define regWGS_COMPUTE_RESOURCE_LIMITS 0x2695 +#define regWGS_COMPUTE_RESOURCE_LIMITS_BASE_IDX 1 +#define regWGS_COMPUTE_DESTINATION_EN_SE0 0x2696 +#define regWGS_COMPUTE_DESTINATION_EN_SE0_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE0 0x2696 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE0_BASE_IDX 1 +#define regWGS_COMPUTE_DESTINATION_EN_SE1 0x2697 +#define regWGS_COMPUTE_DESTINATION_EN_SE1_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE1 0x2697 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE1_BASE_IDX 1 +#define regWGS_COMPUTE_TMPRING_SIZE 0x2698 +#define regWGS_COMPUTE_TMPRING_SIZE_BASE_IDX 1 +#define regWGS_COMPUTE_DESTINATION_EN_SE2 0x2699 +#define regWGS_COMPUTE_DESTINATION_EN_SE2_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE2 0x2699 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE2_BASE_IDX 1 +#define regWGS_COMPUTE_DESTINATION_EN_SE3 0x269a +#define regWGS_COMPUTE_DESTINATION_EN_SE3_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE3 0x269a +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE3_BASE_IDX 1 +#define regWGS_COMPUTE_RESTART_X 0x269b +#define regWGS_COMPUTE_RESTART_X_BASE_IDX 1 +#define regWGS_COMPUTE_RESTART_Y 0x269c +#define regWGS_COMPUTE_RESTART_Y_BASE_IDX 1 +#define regWGS_COMPUTE_RESTART_Z 0x269d +#define regWGS_COMPUTE_RESTART_Z_BASE_IDX 1 +#define regWGS_COMPUTE_THREAD_TRACE_ENABLE 0x269e +#define regWGS_COMPUTE_THREAD_TRACE_ENABLE_BASE_IDX 1 +#define regWGS_COMPUTE_MISC_RESERVED 0x269f +#define regWGS_COMPUTE_MISC_RESERVED_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_ID 0x26a0 +#define regWGS_COMPUTE_DISPATCH_ID_BASE_IDX 1 +#define regWGS_COMPUTE_THREADGROUP_ID 0x26a1 +#define regWGS_COMPUTE_THREADGROUP_ID_BASE_IDX 1 +#define regWGS_COMPUTE_REQ_CTRL 0x26a2 +#define regWGS_COMPUTE_REQ_CTRL_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE8 0x26a3 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE8_BASE_IDX 1 +#define regWGS_COMPUTE_USER_ACCUM_0 0x26a4 +#define regWGS_COMPUTE_USER_ACCUM_0_BASE_IDX 1 +#define regWGS_COMPUTE_USER_ACCUM_1 0x26a5 +#define regWGS_COMPUTE_USER_ACCUM_1_BASE_IDX 1 +#define regWGS_COMPUTE_USER_ACCUM_2 0x26a6 +#define regWGS_COMPUTE_USER_ACCUM_2_BASE_IDX 1 +#define regWGS_COMPUTE_USER_ACCUM_3 0x26a7 +#define regWGS_COMPUTE_USER_ACCUM_3_BASE_IDX 1 +#define regWGS_COMPUTE_PGM_RSRC3 0x26a8 +#define regWGS_COMPUTE_PGM_RSRC3_BASE_IDX 1 +#define regWGS_COMPUTE_DDID_INDEX 0x26a9 +#define regWGS_COMPUTE_DDID_INDEX_BASE_IDX 1 +#define regWGS_COMPUTE_SHADER_CHKSUM 0x26aa +#define regWGS_COMPUTE_SHADER_CHKSUM_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE4 0x26ab +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE4_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE5 0x26ac +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE5_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE6 0x26ad +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE6_BASE_IDX 1 +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE7 0x26ae +#define regWGS_COMPUTE_STATIC_THREAD_MGMT_SE7_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_INTERLEAVE 0x26af +#define regWGS_COMPUTE_DISPATCH_INTERLEAVE_BASE_IDX 1 +#define regWGS_COMPUTE_RELAUNCH 0x26b0 +#define regWGS_COMPUTE_RELAUNCH_BASE_IDX 1 +#define regWGS_COMPUTE_WAVE_RESTORE_ADDR_LO 0x26b1 +#define regWGS_COMPUTE_WAVE_RESTORE_ADDR_LO_BASE_IDX 1 +#define regWGS_COMPUTE_WAVE_RESTORE_ADDR_HI 0x26b2 +#define regWGS_COMPUTE_WAVE_RESTORE_ADDR_HI_BASE_IDX 1 +#define regWGS_COMPUTE_RELAUNCH2 0x26b3 +#define regWGS_COMPUTE_RELAUNCH2_BASE_IDX 1 +#define regWGS_COMPUTE_PRESCALED_DIM_X 0x26b5 +#define regWGS_COMPUTE_PRESCALED_DIM_X_BASE_IDX 1 +#define regWGS_COMPUTE_PRESCALED_DIM_Y 0x26b6 +#define regWGS_COMPUTE_PRESCALED_DIM_Y_BASE_IDX 1 +#define regWGS_COMPUTE_PRESCALED_DIM_Z 0x26b7 +#define regWGS_COMPUTE_PRESCALED_DIM_Z_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_0 0x26c0 +#define regWGS_COMPUTE_USER_DATA_0_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_1 0x26c1 +#define regWGS_COMPUTE_USER_DATA_1_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_2 0x26c2 +#define regWGS_COMPUTE_USER_DATA_2_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_3 0x26c3 +#define regWGS_COMPUTE_USER_DATA_3_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_4 0x26c4 +#define regWGS_COMPUTE_USER_DATA_4_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_5 0x26c5 +#define regWGS_COMPUTE_USER_DATA_5_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_6 0x26c6 +#define regWGS_COMPUTE_USER_DATA_6_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_7 0x26c7 +#define regWGS_COMPUTE_USER_DATA_7_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_8 0x26c8 +#define regWGS_COMPUTE_USER_DATA_8_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_9 0x26c9 +#define regWGS_COMPUTE_USER_DATA_9_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_10 0x26ca +#define regWGS_COMPUTE_USER_DATA_10_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_11 0x26cb +#define regWGS_COMPUTE_USER_DATA_11_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_12 0x26cc +#define regWGS_COMPUTE_USER_DATA_12_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_13 0x26cd +#define regWGS_COMPUTE_USER_DATA_13_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_14 0x26ce +#define regWGS_COMPUTE_USER_DATA_14_BASE_IDX 1 +#define regWGS_COMPUTE_USER_DATA_15 0x26cf +#define regWGS_COMPUTE_USER_DATA_15_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_TUNNEL 0x26fd +#define regWGS_COMPUTE_DISPATCH_TUNNEL_BASE_IDX 1 +#define regWGS_COMPUTE_DISPATCH_END 0x26fe +#define regWGS_COMPUTE_DISPATCH_END_BASE_IDX 1 +#define regWGS_COMPUTE_NOWHERE 0x26ff +#define regWGS_COMPUTE_NOWHERE_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_wgsdec +// base address: 0x31c00 +#define regWGS_MGCG_SYNC_CNTL 0x2708 +#define regWGS_MGCG_SYNC_CNTL_BASE_IDX 1 +#define regWGS_INT_INFO 0x2709 +#define regWGS_INT_INFO_BASE_IDX 1 +#define regWGS_INT_CNTXID_LO 0x270a +#define regWGS_INT_CNTXID_LO_BASE_IDX 1 +#define regWGS_INT_CNTXID_HI 0x270b +#define regWGS_INT_CNTXID_HI_BASE_IDX 1 +#define regWGS_ERROR 0x270c +#define regWGS_ERROR_BASE_IDX 1 +#define regWGS_ENDIAN_SWAP 0x270d +#define regWGS_ENDIAN_SWAP_BASE_IDX 1 +#define regWGS_GEN_BASE_LO 0x2710 +#define regWGS_GEN_BASE_LO_BASE_IDX 1 +#define regWGS_GEN_BASE_HI 0x2711 +#define regWGS_GEN_BASE_HI_BASE_IDX 1 +#define regCGTT_WGS_CLK_CTRL 0x2712 +#define regCGTT_WGS_CLK_CTRL_BASE_IDX 1 +#define regWGS_ME1_UCODE_ADDR 0x2713 +#define regWGS_ME1_UCODE_ADDR_BASE_IDX 1 +#define regWGS_ME1_UCODE_DATA 0x2714 +#define regWGS_ME1_UCODE_DATA_BASE_IDX 1 +#define regWGS_ME1_UCODE_CHKSUM 0x2717 +#define regWGS_ME1_UCODE_CHKSUM_BASE_IDX 1 +#define regWGS_SUSPEND_CTX_SAVE_BASE_ADDR_LO 0x2719 +#define regWGS_SUSPEND_CTX_SAVE_BASE_ADDR_LO_BASE_IDX 1 +#define regWGS_SUSPEND_CTX_SAVE_BASE_ADDR_HI 0x271a +#define regWGS_SUSPEND_CTX_SAVE_BASE_ADDR_HI_BASE_IDX 1 +#define regWGS_SUSPEND_CTX_SAVE_CONTROL 0x271b +#define regWGS_SUSPEND_CTX_SAVE_CONTROL_BASE_IDX 1 +#define regWGS_SUSPEND_CNTL_STACK_OFFSET 0x271c +#define regWGS_SUSPEND_CNTL_STACK_OFFSET_BASE_IDX 1 +#define regWGS_SUSPEND_CNTL_STACK_SIZE 0x271d +#define regWGS_SUSPEND_CNTL_STACK_SIZE_BASE_IDX 1 +#define regWGS_SUSPEND_WG_STATE_OFFSET 0x271e +#define regWGS_SUSPEND_WG_STATE_OFFSET_BASE_IDX 1 +#define regWGS_SUSPEND_CTX_SAVE_SIZE 0x271f +#define regWGS_SUSPEND_CTX_SAVE_SIZE_BASE_IDX 1 +#define regWGS_OS_PIPES 0x2720 +#define regWGS_OS_PIPES_BASE_IDX 1 +#define regWGS_SUSPEND_RESUME_REQ 0x2721 +#define regWGS_SUSPEND_RESUME_REQ_BASE_IDX 1 +#define regWGS_IQ_WAIT_TIME3 0x2723 +#define regWGS_IQ_WAIT_TIME3_BASE_IDX 1 +#define regWGS_DDID_BASE_ADDR_LO 0x2724 +#define regWGS_DDID_BASE_ADDR_LO_BASE_IDX 1 +#define regWGS_DDID_BASE_ADDR_HI 0x2725 +#define regWGS_DDID_BASE_ADDR_HI_BASE_IDX 1 +#define regWGS_DDID_CNTL 0x2726 +#define regWGS_DDID_CNTL_BASE_IDX 1 +#define regWGS_RS64_PRGRM_CNTR_START 0x2727 +#define regWGS_RS64_PRGRM_CNTR_START_BASE_IDX 1 +#define regWGS_MTVEC_LO 0x2728 +#define regWGS_MTVEC_LO_BASE_IDX 1 +#define regWGS_MTVEC_HI 0x2729 +#define regWGS_MTVEC_HI_BASE_IDX 1 +#define regWGS_RS64_CNTL 0x272b +#define regWGS_RS64_CNTL_BASE_IDX 1 +#define regWGS_MIE_LO 0x272c +#define regWGS_MIE_LO_BASE_IDX 1 +#define regWGS_MIE_HI 0x272d +#define regWGS_MIE_HI_BASE_IDX 1 +#define regWGS_RS64_INTERRUPT 0x272e +#define regWGS_RS64_INTERRUPT_BASE_IDX 1 +#define regWGS_RS64_INSTR_PNTR 0x272f +#define regWGS_RS64_INSTR_PNTR_BASE_IDX 1 +#define regWGS_MIP_LO 0x2730 +#define regWGS_MIP_LO_BASE_IDX 1 +#define regWGS_MIP_HI 0x2731 +#define regWGS_MIP_HI_BASE_IDX 1 +#define regWGS_DC_BASE_CNTL 0x2732 +#define regWGS_DC_BASE_CNTL_BASE_IDX 1 +#define regWGS_DC_OP_CNTL 0x2733 +#define regWGS_DC_OP_CNTL_BASE_IDX 1 +#define regWGS_MTIMECMP_LO 0x2734 +#define regWGS_MTIMECMP_LO_BASE_IDX 1 +#define regWGS_MTIMECMP_HI 0x2735 +#define regWGS_MTIMECMP_HI_BASE_IDX 1 +#define regWGS_GP0_LO 0x2737 +#define regWGS_GP0_LO_BASE_IDX 1 +#define regWGS_GP0_HI 0x2738 +#define regWGS_GP0_HI_BASE_IDX 1 +#define regWGS_GP1_LO 0x2739 +#define regWGS_GP1_LO_BASE_IDX 1 +#define regWGS_GP1_HI 0x273a +#define regWGS_GP1_HI_BASE_IDX 1 +#define regWGS_GP2_LO 0x273b +#define regWGS_GP2_LO_BASE_IDX 1 +#define regWGS_GP2_HI 0x273c +#define regWGS_GP2_HI_BASE_IDX 1 +#define regWGS_GP3_LO 0x273d +#define regWGS_GP3_LO_BASE_IDX 1 +#define regWGS_GP3_HI 0x273e +#define regWGS_GP3_HI_BASE_IDX 1 +#define regWGS_GP4_LO 0x273f +#define regWGS_GP4_LO_BASE_IDX 1 +#define regWGS_GP4_HI 0x2740 +#define regWGS_GP4_HI_BASE_IDX 1 +#define regWGS_GP5_LO 0x2741 +#define regWGS_GP5_LO_BASE_IDX 1 +#define regWGS_GP5_HI 0x2742 +#define regWGS_GP5_HI_BASE_IDX 1 +#define regWGS_GP6_LO 0x2743 +#define regWGS_GP6_LO_BASE_IDX 1 +#define regWGS_GP6_HI 0x2744 +#define regWGS_GP6_HI_BASE_IDX 1 +#define regWGS_GP7_LO 0x2745 +#define regWGS_GP7_LO_BASE_IDX 1 +#define regWGS_GP7_HI 0x2746 +#define regWGS_GP7_HI_BASE_IDX 1 +#define regWGS_GP8_LO 0x2747 +#define regWGS_GP8_LO_BASE_IDX 1 +#define regWGS_GP8_HI 0x2748 +#define regWGS_GP8_HI_BASE_IDX 1 +#define regWGS_GP9_LO 0x2749 +#define regWGS_GP9_LO_BASE_IDX 1 +#define regWGS_GP9_HI 0x274a +#define regWGS_GP9_HI_BASE_IDX 1 +#define regWGS_DM_INDEX_ADDR 0x274b +#define regWGS_DM_INDEX_ADDR_BASE_IDX 1 +#define regWGS_DM_INDEX_DATA 0x274c +#define regWGS_DM_INDEX_DATA_BASE_IDX 1 +#define regWGS_LOCAL_BASE0_LO 0x274e +#define regWGS_LOCAL_BASE0_LO_BASE_IDX 1 +#define regWGS_LOCAL_BASE0_HI 0x274f +#define regWGS_LOCAL_BASE0_HI_BASE_IDX 1 +#define regWGS_LOCAL_MASK0_LO 0x2750 +#define regWGS_LOCAL_MASK0_LO_BASE_IDX 1 +#define regWGS_LOCAL_MASK0_HI 0x2751 +#define regWGS_LOCAL_MASK0_HI_BASE_IDX 1 +#define regWGS_LOCAL_APERTURE 0x2752 +#define regWGS_LOCAL_APERTURE_BASE_IDX 1 +#define regWGS_LOCAL_INSTR_BASE_LO 0x2753 +#define regWGS_LOCAL_INSTR_BASE_LO_BASE_IDX 1 +#define regWGS_LOCAL_INSTR_BASE_HI 0x2754 +#define regWGS_LOCAL_INSTR_BASE_HI_BASE_IDX 1 +#define regWGS_LOCAL_INSTR_MASK_LO 0x2755 +#define regWGS_LOCAL_INSTR_MASK_LO_BASE_IDX 1 +#define regWGS_LOCAL_INSTR_MASK_HI 0x2756 +#define regWGS_LOCAL_INSTR_MASK_HI_BASE_IDX 1 +#define regWGS_LOCAL_INSTR_APERTURE 0x2757 +#define regWGS_LOCAL_INSTR_APERTURE_BASE_IDX 1 +#define regWGS_LOCAL_SCRATCH_APERTURE 0x2758 +#define regWGS_LOCAL_SCRATCH_APERTURE_BASE_IDX 1 +#define regWGS_LOCAL_SCRATCH_BASE_LO 0x2759 +#define regWGS_LOCAL_SCRATCH_BASE_LO_BASE_IDX 1 +#define regWGS_LOCAL_SCRATCH_BASE_HI 0x275a +#define regWGS_LOCAL_SCRATCH_BASE_HI_BASE_IDX 1 +#define regWGS_RS64_PERFCOUNT_CNTL 0x275b +#define regWGS_RS64_PERFCOUNT_CNTL_BASE_IDX 1 +#define regWGS_RS64_PENDING_INTERRUPT 0x275c +#define regWGS_RS64_PENDING_INTERRUPT_BASE_IDX 1 +#define regWGS_RS64_EXCEPTION_STATUS 0x275e +#define regWGS_RS64_EXCEPTION_STATUS_BASE_IDX 1 +#define regWGS_RS64_PRGRM_CNTR_START_HI 0x275f +#define regWGS_RS64_PRGRM_CNTR_START_HI_BASE_IDX 1 +#define regWGS_DC_BASE_LO 0x2799 +#define regWGS_DC_BASE_LO_BASE_IDX 1 +#define regWGS_MDBASE_LO 0x2799 +#define regWGS_MDBASE_LO_BASE_IDX 1 +#define regWGS_DC_BASE_HI 0x279a +#define regWGS_DC_BASE_HI_BASE_IDX 1 +#define regWGS_MDBASE_HI 0x279a +#define regWGS_MDBASE_HI_BASE_IDX 1 +#define regWGS_MIBOUND_LO 0x279b +#define regWGS_MIBOUND_LO_BASE_IDX 1 +#define regWGS_MIBOUND_HI 0x279c +#define regWGS_MIBOUND_HI_BASE_IDX 1 +#define regWGS_MDBOUND_LO 0x279d +#define regWGS_MDBOUND_LO_BASE_IDX 1 +#define regWGS_MDBOUND_HI 0x279e +#define regWGS_MDBOUND_HI_BASE_IDX 1 +#define regWGS_IC_OP_CNTL 0x279f +#define regWGS_IC_OP_CNTL_BASE_IDX 1 +#define regWGS_INT_STATUS 0x27a3 +#define regWGS_INT_STATUS_BASE_IDX 1 +#define regWGS_IH_FREE_COUNT 0x27a4 +#define regWGS_IH_FREE_COUNT_BASE_IDX 1 +#define regWGS_ME1_PIPE_PRIORITY_CNTS 0x27a6 +#define regWGS_ME1_PIPE_PRIORITY_CNTS_BASE_IDX 1 +#define regWGS_ME1_PIPE0_PRIORITY 0x27a7 +#define regWGS_ME1_PIPE0_PRIORITY_BASE_IDX 1 +#define regWGS_ME1_PIPE1_PRIORITY 0x27a8 +#define regWGS_ME1_PIPE1_PRIORITY_BASE_IDX 1 +#define regWGS_ME1_PIPE2_PRIORITY 0x27a9 +#define regWGS_ME1_PIPE2_PRIORITY_BASE_IDX 1 +#define regWGS_ME1_PIPE3_PRIORITY 0x27aa +#define regWGS_ME1_PIPE3_PRIORITY_BASE_IDX 1 +#define regWGS_IQ_WAIT_TIME1 0x27b4 +#define regWGS_IQ_WAIT_TIME1_BASE_IDX 1 +#define regWGS_IQ_WAIT_TIME2 0x27b5 +#define regWGS_IQ_WAIT_TIME2_BASE_IDX 1 +#define regWGS_IC_BASE_LO 0x27b7 +#define regWGS_IC_BASE_LO_BASE_IDX 1 +#define regWGS_IC_BASE_HI 0x27b8 +#define regWGS_IC_BASE_HI_BASE_IDX 1 +#define regWGS_IC_BASE_CNTL 0x27b9 +#define regWGS_IC_BASE_CNTL_BASE_IDX 1 +#define regWGS_UCODE_VERS 0x27bb +#define regWGS_UCODE_VERS_BASE_IDX 1 +#define regWGS_BUSY_HYSTERESIS 0x27bd +#define regWGS_BUSY_HYSTERESIS_BASE_IDX 1 +#define regWGS_STATUS 0x27d0 +#define regWGS_STATUS_BASE_IDX 1 +#define regWGS_BUSY_STAT 0x27d1 +#define regWGS_BUSY_STAT_BASE_IDX 1 +#define regWGS_STALLED_STAT1 0x27d2 +#define regWGS_STALLED_STAT1_BASE_IDX 1 +#define regWGS_BUSY_STAT2 0x27d3 +#define regWGS_BUSY_STAT2_BASE_IDX 1 +#define regWGS_ME1_HEADER_DUMP 0x27d4 +#define regWGS_ME1_HEADER_DUMP_BASE_IDX 1 +#define regWGS_SCRATCH_INDEX 0x27d6 +#define regWGS_SCRATCH_INDEX_BASE_IDX 1 +#define regWGS_SCRATCH_DATA 0x27d7 +#define regWGS_SCRATCH_DATA_BASE_IDX 1 +#define regWGS_LATENCY_STATS_SELECT 0x27d8 +#define regWGS_LATENCY_STATS_SELECT_BASE_IDX 1 +#define regWGS_LATENCY_STATS_DATA 0x27d9 +#define regWGS_LATENCY_STATS_DATA_BASE_IDX 1 +#define regWGS_TC_PERF_COUNTER_WINDOW_SELECT 0x27da +#define regWGS_TC_PERF_COUNTER_WINDOW_SELECT_BASE_IDX 1 +#define regWGS_DATA1 0x27db +#define regWGS_DATA1_BASE_IDX 1 +#define regWGS_DATA2 0x27dc +#define regWGS_DATA2_BASE_IDX 1 +#define regWGS_DATA3 0x27dd +#define regWGS_DATA3_BASE_IDX 1 +#define regWGS_DATA4 0x27de +#define regWGS_DATA4_BASE_IDX 1 +#define regWGS_DATA5 0x27df +#define regWGS_DATA5_BASE_IDX 1 +#define regWGS_DATA6 0x27e0 +#define regWGS_DATA6_BASE_IDX 1 +#define regWGS_DATA7 0x27e1 +#define regWGS_DATA7_BASE_IDX 1 +#define regWGS_DATA8 0x27e2 +#define regWGS_DATA8_BASE_IDX 1 +#define regWGS_DATA9 0x27e3 +#define regWGS_DATA9_BASE_IDX 1 +#define regWGS_DATA10 0x27e4 +#define regWGS_DATA10_BASE_IDX 1 +#define regWGS_DATA11 0x27e5 +#define regWGS_DATA11_BASE_IDX 1 +#define regWGS_DATA12 0x27e6 +#define regWGS_DATA12_BASE_IDX 1 +#define regWGS_DATA13 0x27e7 +#define regWGS_DATA13_BASE_IDX 1 +#define regWGS_DATA14 0x27e8 +#define regWGS_DATA14_BASE_IDX 1 +#define regWGS_DATA15 0x27e9 +#define regWGS_DATA15_BASE_IDX 1 +#define regWGS_DATA16 0x27ea +#define regWGS_DATA16_BASE_IDX 1 +#define regWGS_METADATA_BASE_ADDR_LO 0x27eb +#define regWGS_METADATA_BASE_ADDR_LO_BASE_IDX 1 +#define regWGS_METADATA_BASE_ADDR_HI 0x27ec +#define regWGS_METADATA_BASE_ADDR_HI_BASE_IDX 1 +#define regWGS_METADATA_CNTL 0x27ed +#define regWGS_METADATA_CNTL_BASE_IDX 1 +#define regWGS_IQ_TIMER 0x27ee +#define regWGS_IQ_TIMER_BASE_IDX 1 +#define regWGS_HALT_HYST_COUNT 0x27ef +#define regWGS_HALT_HYST_COUNT_BASE_IDX 1 +#define regWGS_IQ_TIMER_MESSAGE 0x27f0 +#define regWGS_IQ_TIMER_MESSAGE_BASE_IDX 1 +#define regWGS_RS64_THREAD_CNTL 0x27f6 +#define regWGS_RS64_THREAD_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gl1dec +// base address: 0x33400 +#define regGL1_ARB_CTRL 0x2d00 +#define regGL1_ARB_CTRL_BASE_IDX 1 +#define regGL1_DRAM_BURST_MASK 0x2d02 +#define regGL1_DRAM_BURST_MASK_BASE_IDX 1 +#define regGL1_ARB_STATUS 0x2d03 +#define regGL1_ARB_STATUS_BASE_IDX 1 +#define regGL1_DRAM_BURST_CTRL 0x2d04 +#define regGL1_DRAM_BURST_CTRL_BASE_IDX 1 +#define regGL1I_GL1R_REP_FGCG_OVERRIDE 0x2d05 +#define regGL1I_GL1R_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regGL1A_GL1C_CREDITS 0x2d08 +#define regGL1A_GL1C_CREDITS_BASE_IDX 1 +#define regGL1A_CLIENT_FREE_DELAY 0x2d09 +#define regGL1A_CLIENT_FREE_DELAY_BASE_IDX 1 +#define regGL1X_ARB_CTRL 0x2d20 +#define regGL1X_ARB_CTRL_BASE_IDX 1 +#define regGL1X_DRAM_BURST_MASK 0x2d22 +#define regGL1X_DRAM_BURST_MASK_BASE_IDX 1 +#define regGL1X_ARB_STATUS 0x2d23 +#define regGL1X_ARB_STATUS_BASE_IDX 1 +#define regGL1X_DRAM_BURST_CTRL 0x2d24 +#define regGL1X_DRAM_BURST_CTRL_BASE_IDX 1 +#define regGL1XI_GL1XR_REP_FGCG_OVERRIDE 0x2d25 +#define regGL1XI_GL1XR_REP_FGCG_OVERRIDE_BASE_IDX 1 +#define regGL1XA_GL1XC_CREDITS 0x2d28 +#define regGL1XA_GL1XC_CREDITS_BASE_IDX 1 +#define regGL1XA_CLIENT_FREE_DELAY 0x2d29 +#define regGL1XA_CLIENT_FREE_DELAY_BASE_IDX 1 +#define regGL1XA_COMPRESSION_MODE 0x2d2a +#define regGL1XA_COMPRESSION_MODE_BASE_IDX 1 +#define regGL1XA_COMPRESSOR_OVERRIDE 0x2d2b +#define regGL1XA_COMPRESSOR_OVERRIDE_BASE_IDX 1 +#define regGL1C_CTRL 0x2d40 +#define regGL1C_CTRL_BASE_IDX 1 +#define regGL1C_STATUS 0x2d41 +#define regGL1C_STATUS_BASE_IDX 1 +#define regGL1C_CTRL2 0x2d46 +#define regGL1C_CTRL2_BASE_IDX 1 +#define regGL1XC_CTRL 0x2d47 +#define regGL1XC_CTRL_BASE_IDX 1 +#define regGL1XC_STATUS 0x2d48 +#define regGL1XC_STATUS_BASE_IDX 1 +#define regGL1XC_UTCL0_CNTL1 0x2d49 +#define regGL1XC_UTCL0_CNTL1_BASE_IDX 1 +#define regGL1XC_UTCL0_CNTL2 0x2d4a +#define regGL1XC_UTCL0_CNTL2_BASE_IDX 1 +#define regGL1XC_UTCL0_STATUS 0x2d4b +#define regGL1XC_UTCL0_STATUS_BASE_IDX 1 +#define regGL1XC_UTCL0_RETRY 0x2d4c +#define regGL1XC_UTCL0_RETRY_BASE_IDX 1 +#define regGL1XC_CTRL2 0x2d4d +#define regGL1XC_CTRL2_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_secacdec +// base address: 0x2f1c0 +#define regSE_CAC_CTRL_1 0x1c70 +#define regSE_CAC_CTRL_1_BASE_IDX 1 +#define regSE_CAC_CTRL_2 0x1c71 +#define regSE_CAC_CTRL_2_BASE_IDX 1 +#define regSE_CAC_SOFT_CTRL 0x1c72 +#define regSE_CAC_SOFT_CTRL_BASE_IDX 1 +#define regSE_CAC_OVR_VAL_LOWER 0x1c74 +#define regSE_CAC_OVR_VAL_LOWER_BASE_IDX 1 +#define regSE_CAC_OVR_VAL_UPPER 0x1c75 +#define regSE_CAC_OVR_VAL_UPPER_BASE_IDX 1 +#define regSE_CAC_WINDOW_AGGR_VALUE_LO 0x1c76 +#define regSE_CAC_WINDOW_AGGR_VALUE_LO_BASE_IDX 1 +#define regSE_CAC_WINDOW_AGGR_VALUE_HI 0x1c77 +#define regSE_CAC_WINDOW_AGGR_VALUE_HI_BASE_IDX 1 +#define regSE_CAC_WINDOW_GFXCLK_CYCLE 0x1c78 +#define regSE_CAC_WINDOW_GFXCLK_CYCLE_BASE_IDX 1 +#define regDIDT_EDC_CTRL 0x1c7c +#define regDIDT_EDC_CTRL_BASE_IDX 1 +#define regDIDT_EDC_THROTTLE_CTRL 0x1c7d +#define regDIDT_EDC_THROTTLE_CTRL_BASE_IDX 1 +#define regDIDT_EDC_THRESHOLD 0x1c7e +#define regDIDT_EDC_THRESHOLD_BASE_IDX 1 +#define regDIDT_EDC_STRETCH_THRESHOLD 0x1c7f +#define regDIDT_EDC_STRETCH_THRESHOLD_BASE_IDX 1 +#define regDIDT_EDC_CLK_COUNTER_THRESHOLD 0x1c80 +#define regDIDT_EDC_CLK_COUNTER_THRESHOLD_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_1_2 0x1c81 +#define regDIDT_EDC_STALL_PATTERN_1_2_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_3_4 0x1c82 +#define regDIDT_EDC_STALL_PATTERN_3_4_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_5_6 0x1c83 +#define regDIDT_EDC_STALL_PATTERN_5_6_BASE_IDX 1 +#define regDIDT_EDC_STALL_PATTERN_7 0x1c84 +#define regDIDT_EDC_STALL_PATTERN_7_BASE_IDX 1 +#define regDIDT_EDC_STATUS 0x1c85 +#define regDIDT_EDC_STATUS_BASE_IDX 1 +#define regDIDT_EDC_OVERFLOW 0x1c86 +#define regDIDT_EDC_OVERFLOW_BASE_IDX 1 +#define regDIDT_EDC_ROLLING_POWER_DELTA 0x1c87 +#define regDIDT_EDC_ROLLING_POWER_DELTA_BASE_IDX 1 +#define regDIDT_EDC_AVG_POWER_DELTA_HI 0x1c88 +#define regDIDT_EDC_AVG_POWER_DELTA_HI_BASE_IDX 1 +#define regDIDT_EDC_AVG_POWER_DELTA_LO 0x1c89 +#define regDIDT_EDC_AVG_POWER_DELTA_LO_BASE_IDX 1 +#define regDIDT_EDC_STALL_PERF_COUNTER 0x1c8a +#define regDIDT_EDC_STALL_PERF_COUNTER_BASE_IDX 1 +#define regDIDT_THRESHOLD 0x1c8c +#define regDIDT_THRESHOLD_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS1_0 0x1c93 +#define regSE_CAC_WEIGHT_LDS1_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS1_1 0x1c94 +#define regSE_CAC_WEIGHT_LDS1_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS1_2 0x1c95 +#define regSE_CAC_WEIGHT_LDS1_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS1_3 0x1c96 +#define regSE_CAC_WEIGHT_LDS1_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_0 0x1c9d +#define regSE_CAC_WEIGHT_TCP_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_1 0x1c9e +#define regSE_CAC_WEIGHT_TCP_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_2 0x1c9f +#define regSE_CAC_WEIGHT_TCP_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_3 0x1ca0 +#define regSE_CAC_WEIGHT_TCP_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_0 0x1ca1 +#define regSE_CAC_WEIGHT_SQ_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_1 0x1ca2 +#define regSE_CAC_WEIGHT_SQ_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQ_2 0x1ca3 +#define regSE_CAC_WEIGHT_SQ_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SP_0 0x1ca4 +#define regSE_CAC_WEIGHT_SP_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SP_1 0x1ca5 +#define regSE_CAC_WEIGHT_SP_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SP_2 0x1ca6 +#define regSE_CAC_WEIGHT_SP_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS0_0 0x1ca7 +#define regSE_CAC_WEIGHT_LDS0_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS0_1 0x1ca8 +#define regSE_CAC_WEIGHT_LDS0_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS0_2 0x1ca9 +#define regSE_CAC_WEIGHT_LDS0_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_LDS0_3 0x1caa +#define regSE_CAC_WEIGHT_LDS0_3_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQC_0 0x1cac +#define regSE_CAC_WEIGHT_SQC_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SQC_1 0x1cad +#define regSE_CAC_WEIGHT_SQC_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_CU_0 0x1cae +#define regSE_CAC_WEIGHT_CU_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_UTCL1_0 0x1cc3 +#define regSE_CAC_WEIGHT_UTCL1_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_GL1C_0 0x1cc4 +#define regSE_CAC_WEIGHT_GL1C_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_GL1C_1 0x1cc5 +#define regSE_CAC_WEIGHT_GL1C_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_0 0x1cc6 +#define regSE_CAC_WEIGHT_SPI_0_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_1 0x1cc7 +#define regSE_CAC_WEIGHT_SPI_1_BASE_IDX 1 +#define regSE_CAC_WEIGHT_SPI_2 0x1cc8 +#define regSE_CAC_WEIGHT_SPI_2_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_4 0x1cdc +#define regSE_CAC_WEIGHT_TCP_4_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_5 0x1cdd +#define regSE_CAC_WEIGHT_TCP_5_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_6 0x1cde +#define regSE_CAC_WEIGHT_TCP_6_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_7 0x1cdf +#define regSE_CAC_WEIGHT_TCP_7_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_8 0x1ce0 +#define regSE_CAC_WEIGHT_TCP_8_BASE_IDX 1 +#define regSE_CAC_WEIGHT_TCP_9 0x1ce1 +#define regSE_CAC_WEIGHT_TCP_9_BASE_IDX 1 +#define regSE_CAC_IND_INDEX 0x1d2e +#define regSE_CAC_IND_INDEX_BASE_IDX 1 +#define regSE_CAC_IND_DATA 0x1d2f +#define regSE_CAC_IND_DATA_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_perfddec +// base address: 0x34000 +#define regGE2_SE_PERFCOUNTER0_LO 0x30b4 +#define regGE2_SE_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_HI 0x30b5 +#define regGE2_SE_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_LO 0x30b6 +#define regGE2_SE_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_HI 0x30b7 +#define regGE2_SE_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_LO 0x30b8 +#define regGE2_SE_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_HI 0x30b9 +#define regGE2_SE_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_LO 0x30ba +#define regGE2_SE_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_HI 0x30bb +#define regGE2_SE_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER0_LO 0x30f8 +#define regGRBMH_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER0_HI 0x30f9 +#define regGRBMH_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER1_LO 0x30fa +#define regGRBMH_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER1_HI 0x30fb +#define regGRBMH_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_LO 0x3100 +#define regPA_SU_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_HI 0x3101 +#define regPA_SU_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_LO 0x3102 +#define regPA_SU_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_HI 0x3103 +#define regPA_SU_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_LO 0x3104 +#define regPA_SU_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_HI 0x3105 +#define regPA_SU_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_LO 0x3106 +#define regPA_SU_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_HI 0x3107 +#define regPA_SU_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_LO 0x3140 +#define regPA_SC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_HI 0x3141 +#define regPA_SC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_LO 0x3142 +#define regPA_SC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_HI 0x3143 +#define regPA_SC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_LO 0x3144 +#define regPA_SC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_HI 0x3145 +#define regPA_SC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_LO 0x3146 +#define regPA_SC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_HI 0x3147 +#define regPA_SC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_LO 0x3148 +#define regPA_SC_PERFCOUNTER4_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_HI 0x3149 +#define regPA_SC_PERFCOUNTER4_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_LO 0x314a +#define regPA_SC_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_HI 0x314b +#define regPA_SC_PERFCOUNTER5_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_LO 0x314c +#define regPA_SC_PERFCOUNTER6_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_HI 0x314d +#define regPA_SC_PERFCOUNTER6_HI_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_LO 0x314e +#define regPA_SC_PERFCOUNTER7_LO_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_HI 0x314f +#define regPA_SC_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_HI 0x3180 +#define regSPI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_LO 0x3181 +#define regSPI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_HI 0x3182 +#define regSPI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_LO 0x3183 +#define regSPI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_HI 0x3184 +#define regSPI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_LO 0x3185 +#define regSPI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_HI 0x3186 +#define regSPI_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_LO 0x3187 +#define regSPI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_HI 0x3188 +#define regSPI_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_LO 0x3189 +#define regSPI_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_HI 0x318a +#define regSPI_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_LO 0x318b +#define regSPI_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER0_HI 0x318c +#define regPC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER0_LO 0x318d +#define regPC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER1_HI 0x318e +#define regPC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER1_LO 0x318f +#define regPC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER2_HI 0x3190 +#define regPC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER2_LO 0x3191 +#define regPC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPC_PERFCOUNTER3_HI 0x3192 +#define regPC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPC_PERFCOUNTER3_LO 0x3193 +#define regPC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_LO 0x31c0 +#define regSQ_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_LO 0x31c2 +#define regSQ_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_LO 0x31c4 +#define regSQ_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_LO 0x31c6 +#define regSQ_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_LO 0x31c8 +#define regSQ_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_LO 0x31ca +#define regSQ_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_LO 0x31cc +#define regSQ_PERFCOUNTER6_LO_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_LO 0x31ce +#define regSQ_PERFCOUNTER7_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_LO 0x31e4 +#define regSQG_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_HI 0x31e5 +#define regSQG_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_LO 0x31e6 +#define regSQG_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_HI 0x31e7 +#define regSQG_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_LO 0x31e8 +#define regSQG_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_HI 0x31e9 +#define regSQG_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_LO 0x31ea +#define regSQG_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_HI 0x31eb +#define regSQG_PERFCOUNTER3_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_LO 0x31ec +#define regSQG_PERFCOUNTER4_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_HI 0x31ed +#define regSQG_PERFCOUNTER4_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_LO 0x31ee +#define regSQG_PERFCOUNTER5_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_HI 0x31ef +#define regSQG_PERFCOUNTER5_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_LO 0x31f0 +#define regSQG_PERFCOUNTER6_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_HI 0x31f1 +#define regSQG_PERFCOUNTER6_HI_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_LO 0x31f2 +#define regSQG_PERFCOUNTER7_LO_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_HI 0x31f3 +#define regSQG_PERFCOUNTER7_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER0_LO 0x3240 +#define regSX_PERFCOUNTER0_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER0_HI 0x3241 +#define regSX_PERFCOUNTER0_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER1_LO 0x3242 +#define regSX_PERFCOUNTER1_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER1_HI 0x3243 +#define regSX_PERFCOUNTER1_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER2_LO 0x3244 +#define regSX_PERFCOUNTER2_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER2_HI 0x3245 +#define regSX_PERFCOUNTER2_HI_BASE_IDX 1 +#define regSX_PERFCOUNTER3_LO 0x3246 +#define regSX_PERFCOUNTER3_LO_BASE_IDX 1 +#define regSX_PERFCOUNTER3_HI 0x3247 +#define regSX_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER0_LO 0x32c0 +#define regTA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER0_HI 0x32c1 +#define regTA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTA_PERFCOUNTER1_LO 0x32c2 +#define regTA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTA_PERFCOUNTER1_HI 0x32c3 +#define regTA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER0_LO 0x3300 +#define regTD_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER0_HI 0x3301 +#define regTD_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTD_PERFCOUNTER1_LO 0x3302 +#define regTD_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTD_PERFCOUNTER1_HI 0x3303 +#define regTD_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_LO 0x3340 +#define regTCP_PERFCOUNTER0_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_HI 0x3341 +#define regTCP_PERFCOUNTER0_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_LO 0x3342 +#define regTCP_PERFCOUNTER1_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_HI 0x3343 +#define regTCP_PERFCOUNTER1_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_LO 0x3344 +#define regTCP_PERFCOUNTER2_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_HI 0x3345 +#define regTCP_PERFCOUNTER2_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_LO 0x3346 +#define regTCP_PERFCOUNTER3_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_HI 0x3347 +#define regTCP_PERFCOUNTER3_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER4_LO 0x3348 +#define regTCP_PERFCOUNTER4_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER4_HI 0x3349 +#define regTCP_PERFCOUNTER4_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER5_LO 0x334a +#define regTCP_PERFCOUNTER5_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER5_HI 0x334b +#define regTCP_PERFCOUNTER5_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER6_LO 0x334c +#define regTCP_PERFCOUNTER6_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER6_HI 0x334d +#define regTCP_PERFCOUNTER6_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER7_LO 0x334e +#define regTCP_PERFCOUNTER7_LO_BASE_IDX 1 +#define regTCP_PERFCOUNTER7_HI 0x334f +#define regTCP_PERFCOUNTER7_HI_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER 0x3350 +#define regTCP_PERFCOUNTER_FILTER_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER2 0x3351 +#define regTCP_PERFCOUNTER_FILTER2_BASE_IDX 1 +#define regTCP_PERFCOUNTER_FILTER_EN 0x3352 +#define regTCP_PERFCOUNTER_FILTER_EN_BASE_IDX 1 +#define regTCP_PERFCOUNTER_SET_DEFINE 0x3353 +#define regTCP_PERFCOUNTER_SET_DEFINE_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_LO 0x33a0 +#define regGL1C_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_HI 0x33a1 +#define regGL1C_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_LO 0x33a2 +#define regGL1C_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_HI 0x33a3 +#define regGL1C_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_LO 0x33a4 +#define regGL1C_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_HI 0x33a5 +#define regGL1C_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_LO 0x33a6 +#define regGL1C_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_HI 0x33a7 +#define regGL1C_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER0_LO 0x33a8 +#define regGL1XC_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER0_HI 0x33a9 +#define regGL1XC_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER1_LO 0x33aa +#define regGL1XC_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER1_HI 0x33ab +#define regGL1XC_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER2_LO 0x33ac +#define regGL1XC_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER2_HI 0x33ad +#define regGL1XC_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER3_LO 0x33ae +#define regGL1XC_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER3_HI 0x33af +#define regGL1XC_PERFCOUNTER3_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER0_LO 0x3406 +#define regCB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER0_HI 0x3407 +#define regCB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER1_LO 0x3408 +#define regCB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER1_HI 0x3409 +#define regCB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER2_LO 0x340a +#define regCB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER2_HI 0x340b +#define regCB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regCB_PERFCOUNTER3_LO 0x340c +#define regCB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regCB_PERFCOUNTER3_HI 0x340d +#define regCB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER0_LO 0x3440 +#define regDB_PERFCOUNTER0_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER0_HI 0x3441 +#define regDB_PERFCOUNTER0_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER1_LO 0x3442 +#define regDB_PERFCOUNTER1_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER1_HI 0x3443 +#define regDB_PERFCOUNTER1_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER2_LO 0x3444 +#define regDB_PERFCOUNTER2_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER2_HI 0x3445 +#define regDB_PERFCOUNTER2_HI_BASE_IDX 1 +#define regDB_PERFCOUNTER3_LO 0x3446 +#define regDB_PERFCOUNTER3_LO_BASE_IDX 1 +#define regDB_PERFCOUNTER3_HI 0x3447 +#define regDB_PERFCOUNTER3_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_LO 0x34c0 +#define regRMI_PERFCOUNTER0_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_HI 0x34c1 +#define regRMI_PERFCOUNTER0_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_LO 0x34c2 +#define regRMI_PERFCOUNTER1_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_HI 0x34c3 +#define regRMI_PERFCOUNTER1_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_LO 0x34c4 +#define regRMI_PERFCOUNTER2_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_HI 0x34c5 +#define regRMI_PERFCOUNTER2_HI_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_LO 0x34c6 +#define regRMI_PERFCOUNTER3_LO_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_HI 0x34c7 +#define regRMI_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_LO 0x3580 +#define regPA_PH_PERFCOUNTER0_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_HI 0x3581 +#define regPA_PH_PERFCOUNTER0_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_LO 0x3582 +#define regPA_PH_PERFCOUNTER1_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_HI 0x3583 +#define regPA_PH_PERFCOUNTER1_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_LO 0x3584 +#define regPA_PH_PERFCOUNTER2_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_HI 0x3585 +#define regPA_PH_PERFCOUNTER2_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_LO 0x3586 +#define regPA_PH_PERFCOUNTER3_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_HI 0x3587 +#define regPA_PH_PERFCOUNTER3_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_LO 0x3588 +#define regPA_PH_PERFCOUNTER4_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_HI 0x3589 +#define regPA_PH_PERFCOUNTER4_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_LO 0x358a +#define regPA_PH_PERFCOUNTER5_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_HI 0x358b +#define regPA_PH_PERFCOUNTER5_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_LO 0x358c +#define regPA_PH_PERFCOUNTER6_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_HI 0x358d +#define regPA_PH_PERFCOUNTER6_HI_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_LO 0x358e +#define regPA_PH_PERFCOUNTER7_LO_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_HI 0x358f +#define regPA_PH_PERFCOUNTER7_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_LO 0x35a0 +#define regUTCL1_PERFCOUNTER0_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_HI 0x35a1 +#define regUTCL1_PERFCOUNTER0_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_LO 0x35a2 +#define regUTCL1_PERFCOUNTER1_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_HI 0x35a3 +#define regUTCL1_PERFCOUNTER1_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_LO 0x35a4 +#define regUTCL1_PERFCOUNTER2_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_HI 0x35a5 +#define regUTCL1_PERFCOUNTER2_HI_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_LO 0x35a6 +#define regUTCL1_PERFCOUNTER3_LO_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_HI 0x35a7 +#define regUTCL1_PERFCOUNTER3_HI_BASE_IDX 1 +#define regWGS_PERFCOUNTER1_LO 0x35b0 +#define regWGS_PERFCOUNTER1_LO_BASE_IDX 1 +#define regWGS_PERFCOUNTER1_HI 0x35b1 +#define regWGS_PERFCOUNTER1_HI_BASE_IDX 1 +#define regWGS_PERFCOUNTER0_LO 0x35b2 +#define regWGS_PERFCOUNTER0_LO_BASE_IDX 1 +#define regWGS_PERFCOUNTER0_HI 0x35b3 +#define regWGS_PERFCOUNTER0_HI_BASE_IDX 1 +#define regWGS_PERFMON_CNTL 0x35b4 +#define regWGS_PERFMON_CNTL_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_LO 0x35c0 +#define regGL1A_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_HI 0x35c1 +#define regGL1A_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_LO 0x35c2 +#define regGL1A_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_HI 0x35c3 +#define regGL1A_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_LO 0x35c4 +#define regGL1A_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_HI 0x35c5 +#define regGL1A_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_LO 0x35c6 +#define regGL1A_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_HI 0x35c7 +#define regGL1A_PERFCOUNTER3_HI_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER0_LO 0x35c8 +#define regGL1XA_PERFCOUNTER0_LO_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER0_HI 0x35c9 +#define regGL1XA_PERFCOUNTER0_HI_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER1_LO 0x35ca +#define regGL1XA_PERFCOUNTER1_LO_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER1_HI 0x35cb +#define regGL1XA_PERFCOUNTER1_HI_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER2_LO 0x35cc +#define regGL1XA_PERFCOUNTER2_LO_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER2_HI 0x35cd +#define regGL1XA_PERFCOUNTER2_HI_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER3_LO 0x35ce +#define regGL1XA_PERFCOUNTER3_LO_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER3_HI 0x35cf +#define regGL1XA_PERFCOUNTER3_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_perfsdec +// base address: 0x36000 +#define regGE2_SE_PERFCOUNTER0_SELECT 0x38b4 +#define regGE2_SE_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER0_SELECT1 0x38b5 +#define regGE2_SE_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_SELECT 0x38b6 +#define regGE2_SE_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER1_SELECT1 0x38b7 +#define regGE2_SE_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_SELECT 0x38b8 +#define regGE2_SE_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER2_SELECT1 0x38b9 +#define regGE2_SE_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_SELECT 0x38ba +#define regGE2_SE_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGE2_SE_PERFCOUNTER3_SELECT1 0x38bb +#define regGE2_SE_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER0_SELECT 0x38f8 +#define regGRBMH_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGRBMH_PERFCOUNTER1_SELECT 0x38f9 +#define regGRBMH_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT 0x3900 +#define regPA_SU_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER0_SELECT1 0x3901 +#define regPA_SU_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT 0x3902 +#define regPA_SU_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER1_SELECT1 0x3903 +#define regPA_SU_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_SELECT 0x3904 +#define regPA_SU_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER2_SELECT1 0x3905 +#define regPA_SU_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_SELECT 0x3906 +#define regPA_SU_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SU_PERFCOUNTER3_SELECT1 0x3907 +#define regPA_SU_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT 0x3940 +#define regPA_SC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER0_SELECT1 0x3941 +#define regPA_SC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER1_SELECT 0x3942 +#define regPA_SC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER2_SELECT 0x3943 +#define regPA_SC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER3_SELECT 0x3944 +#define regPA_SC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER4_SELECT 0x3945 +#define regPA_SC_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER5_SELECT 0x3946 +#define regPA_SC_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER6_SELECT 0x3947 +#define regPA_SC_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regPA_SC_PERFCOUNTER7_SELECT 0x3948 +#define regPA_SC_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT 0x3980 +#define regSPI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT 0x3981 +#define regSPI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT 0x3982 +#define regSPI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT 0x3983 +#define regSPI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_SELECT 0x3984 +#define regSPI_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_SELECT 0x3985 +#define regSPI_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSPI_PERFCOUNTER0_SELECT1 0x3986 +#define regSPI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER1_SELECT1 0x3987 +#define regSPI_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER2_SELECT1 0x3988 +#define regSPI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER3_SELECT1 0x3989 +#define regSPI_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER4_SELECT1 0x398a +#define regSPI_PERFCOUNTER4_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER5_SELECT1 0x398b +#define regSPI_PERFCOUNTER5_SELECT1_BASE_IDX 1 +#define regSPI_PERFCOUNTER_BINS 0x398c +#define regSPI_PERFCOUNTER_BINS_BASE_IDX 1 +#define regPC_PERFCOUNTER0_SELECT 0x3990 +#define regPC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER1_SELECT 0x3991 +#define regPC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER2_SELECT 0x3992 +#define regPC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER3_SELECT 0x3993 +#define regPC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPC_PERFCOUNTER0_SELECT1 0x3994 +#define regPC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER1_SELECT1 0x3995 +#define regPC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER2_SELECT1 0x3996 +#define regPC_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPC_PERFCOUNTER3_SELECT1 0x3997 +#define regPC_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regSQ_PERFCOUNTER0_SELECT 0x39c0 +#define regSQ_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER1_SELECT 0x39c1 +#define regSQ_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER2_SELECT 0x39c2 +#define regSQ_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER3_SELECT 0x39c3 +#define regSQ_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER4_SELECT 0x39c4 +#define regSQ_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER5_SELECT 0x39c5 +#define regSQ_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER6_SELECT 0x39c6 +#define regSQ_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER7_SELECT 0x39c7 +#define regSQ_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER8_SELECT 0x39c8 +#define regSQ_PERFCOUNTER8_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER9_SELECT 0x39c9 +#define regSQ_PERFCOUNTER9_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER10_SELECT 0x39ca +#define regSQ_PERFCOUNTER10_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER11_SELECT 0x39cb +#define regSQ_PERFCOUNTER11_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER12_SELECT 0x39cc +#define regSQ_PERFCOUNTER12_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER13_SELECT 0x39cd +#define regSQ_PERFCOUNTER13_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER14_SELECT 0x39ce +#define regSQ_PERFCOUNTER14_SELECT_BASE_IDX 1 +#define regSQ_PERFCOUNTER15_SELECT 0x39cf +#define regSQ_PERFCOUNTER15_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER0_SELECT 0x39d0 +#define regSQG_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER1_SELECT 0x39d1 +#define regSQG_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER2_SELECT 0x39d2 +#define regSQG_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER3_SELECT 0x39d3 +#define regSQG_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER4_SELECT 0x39d4 +#define regSQG_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER5_SELECT 0x39d5 +#define regSQG_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER6_SELECT 0x39d6 +#define regSQG_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER7_SELECT 0x39d7 +#define regSQG_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regSQG_PERFCOUNTER_CTRL 0x39d8 +#define regSQG_PERFCOUNTER_CTRL_BASE_IDX 1 +#define regSQG_PERFCOUNTER_CTRL2 0x39da +#define regSQG_PERFCOUNTER_CTRL2_BASE_IDX 1 +#define regSQG_PERF_SAMPLE_FINISH 0x39db +#define regSQG_PERF_SAMPLE_FINISH_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL 0x39e0 +#define regSQ_PERFCOUNTER_CTRL_BASE_IDX 1 +#define regSQ_PERFCOUNTER_CTRL2 0x39e2 +#define regSQ_PERFCOUNTER_CTRL2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF0_SIZE 0x39e6 +#define regSQ_THREAD_TRACE_BUF0_SIZE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF0_BASE_LO 0x39e7 +#define regSQ_THREAD_TRACE_BUF0_BASE_LO_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF0_BASE_HI 0x39e8 +#define regSQ_THREAD_TRACE_BUF0_BASE_HI_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF1_SIZE 0x39e9 +#define regSQ_THREAD_TRACE_BUF1_SIZE_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF1_BASE_LO 0x39ea +#define regSQ_THREAD_TRACE_BUF1_BASE_LO_BASE_IDX 1 +#define regSQ_THREAD_TRACE_BUF1_BASE_HI 0x39eb +#define regSQ_THREAD_TRACE_BUF1_BASE_HI_BASE_IDX 1 +#define regSQ_THREAD_TRACE_CTRL 0x39ec +#define regSQ_THREAD_TRACE_CTRL_BASE_IDX 1 +#define regSQ_THREAD_TRACE_MASK 0x39ed +#define regSQ_THREAD_TRACE_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_TOKEN_MASK 0x39ee +#define regSQ_THREAD_TRACE_TOKEN_MASK_BASE_IDX 1 +#define regSQ_THREAD_TRACE_WPTR 0x39ef +#define regSQ_THREAD_TRACE_WPTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HALT 0x39f0 +#define regSQ_THREAD_TRACE_HALT_BASE_IDX 1 +#define regSQ_THREAD_TRACE_POWEROFF_RESTORE_1 0x39f1 +#define regSQ_THREAD_TRACE_POWEROFF_RESTORE_1_BASE_IDX 1 +#define regSQ_THREAD_TRACE_STATUS 0x39f4 +#define regSQ_THREAD_TRACE_STATUS_BASE_IDX 1 +#define regSQ_THREAD_TRACE_STATUS2 0x39f5 +#define regSQ_THREAD_TRACE_STATUS2_BASE_IDX 1 +#define regSQ_THREAD_TRACE_GFX_DRAW_CNTR 0x39f6 +#define regSQ_THREAD_TRACE_GFX_DRAW_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_GFX_MARKER_CNTR 0x39f7 +#define regSQ_THREAD_TRACE_GFX_MARKER_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR 0x39f8 +#define regSQ_THREAD_TRACE_HP3D_DRAW_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR 0x39f9 +#define regSQ_THREAD_TRACE_HP3D_MARKER_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_DROPPED_CNTR 0x39fa +#define regSQ_THREAD_TRACE_DROPPED_CNTR_BASE_IDX 1 +#define regSQ_THREAD_TRACE_FINISH_DONE_DEBUG 0x39fb +#define regSQ_THREAD_TRACE_FINISH_DONE_DEBUG_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT 0x3a40 +#define regSX_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT 0x3a41 +#define regSX_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER2_SELECT 0x3a42 +#define regSX_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER3_SELECT 0x3a43 +#define regSX_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regSX_PERFCOUNTER0_SELECT1 0x3a44 +#define regSX_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regSX_PERFCOUNTER1_SELECT1 0x3a45 +#define regSX_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regSX_PERFCOUNTER2_SELECT1 0x3a46 +#define regSX_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regSX_PERFCOUNTER3_SELECT1 0x3a47 +#define regSX_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT 0x3ac0 +#define regTA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTA_PERFCOUNTER0_SELECT1 0x3ac1 +#define regTA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTA_PERFCOUNTER1_SELECT 0x3ac2 +#define regTA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT 0x3b00 +#define regTD_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTD_PERFCOUNTER0_SELECT1 0x3b01 +#define regTD_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTD_PERFCOUNTER1_SELECT 0x3b02 +#define regTD_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT 0x3b40 +#define regTCP_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER0_SELECT1 0x3b41 +#define regTCP_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT 0x3b42 +#define regTCP_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER1_SELECT1 0x3b43 +#define regTCP_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_SELECT 0x3b44 +#define regTCP_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER2_SELECT1 0x3b45 +#define regTCP_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_SELECT 0x3b46 +#define regTCP_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER3_SELECT1 0x3b47 +#define regTCP_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regTCP_PERFCOUNTER4_SELECT 0x3b4a +#define regTCP_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER5_SELECT 0x3b4b +#define regTCP_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER6_SELECT 0x3b4c +#define regTCP_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regTCP_PERFCOUNTER7_SELECT 0x3b4d +#define regTCP_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_SELECT 0x3ba0 +#define regGL1C_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER0_SELECT1 0x3ba1 +#define regGL1C_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_SELECT 0x3ba2 +#define regGL1C_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER1_SELECT1 0x3ba3 +#define regGL1C_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_SELECT 0x3ba4 +#define regGL1C_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER2_SELECT1 0x3ba5 +#define regGL1C_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_SELECT 0x3ba6 +#define regGL1C_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1C_PERFCOUNTER3_SELECT1 0x3ba7 +#define regGL1C_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER0_SELECT 0x3ba8 +#define regGL1XC_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER0_SELECT1 0x3ba9 +#define regGL1XC_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER1_SELECT 0x3baa +#define regGL1XC_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER1_SELECT1 0x3bab +#define regGL1XC_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER2_SELECT 0x3bac +#define regGL1XC_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER2_SELECT1 0x3bad +#define regGL1XC_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER3_SELECT 0x3bae +#define regGL1XC_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1XC_PERFCOUNTER3_SELECT1 0x3baf +#define regGL1XC_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regCB_PERFCOUNTER_FILTER 0x3c00 +#define regCB_PERFCOUNTER_FILTER_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT 0x3c01 +#define regCB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER0_SELECT1 0x3c02 +#define regCB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regCB_PERFCOUNTER1_SELECT 0x3c03 +#define regCB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER2_SELECT 0x3c04 +#define regCB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regCB_PERFCOUNTER3_SELECT 0x3c05 +#define regCB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT 0x3c40 +#define regDB_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER0_SELECT1 0x3c41 +#define regDB_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT 0x3c42 +#define regDB_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER1_SELECT1 0x3c43 +#define regDB_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER2_SELECT 0x3c44 +#define regDB_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER2_SELECT1 0x3c45 +#define regDB_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regDB_PERFCOUNTER3_SELECT 0x3c46 +#define regDB_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regDB_PERFCOUNTER3_SELECT1 0x3c47 +#define regDB_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT 0x3d00 +#define regRMI_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER0_SELECT1 0x3d01 +#define regRMI_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER1_SELECT 0x3d02 +#define regRMI_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT 0x3d03 +#define regRMI_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regRMI_PERFCOUNTER2_SELECT1 0x3d04 +#define regRMI_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regRMI_PERFCOUNTER3_SELECT 0x3d05 +#define regRMI_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regRMI_PERF_COUNTER_CNTL 0x3d06 +#define regRMI_PERF_COUNTER_CNTL_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_SELECT 0x3d80 +#define regPA_PH_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER0_SELECT1 0x3d81 +#define regPA_PH_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_SELECT 0x3d82 +#define regPA_PH_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_SELECT 0x3d83 +#define regPA_PH_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_SELECT 0x3d84 +#define regPA_PH_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER4_SELECT 0x3d85 +#define regPA_PH_PERFCOUNTER4_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER5_SELECT 0x3d86 +#define regPA_PH_PERFCOUNTER5_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER6_SELECT 0x3d87 +#define regPA_PH_PERFCOUNTER6_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER7_SELECT 0x3d88 +#define regPA_PH_PERFCOUNTER7_SELECT_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER1_SELECT1 0x3d90 +#define regPA_PH_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER2_SELECT1 0x3d91 +#define regPA_PH_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regPA_PH_PERFCOUNTER3_SELECT1 0x3d92 +#define regPA_PH_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_SELECT 0x3da0 +#define regUTCL1_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER0_SELECT1 0x3da1 +#define regUTCL1_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_SELECT 0x3da2 +#define regUTCL1_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER1_SELECT1 0x3da3 +#define regUTCL1_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER2_SELECT 0x3da4 +#define regUTCL1_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regUTCL1_PERFCOUNTER3_SELECT 0x3da5 +#define regUTCL1_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regWGS_PERFCOUNTER1_SELECT 0x3db0 +#define regWGS_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regWGS_PERFCOUNTER0_SELECT1 0x3db1 +#define regWGS_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regWGS_PERFCOUNTER0_SELECT 0x3db3 +#define regWGS_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_SELECT 0x3dc0 +#define regGL1A_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER0_SELECT1 0x3dc1 +#define regGL1A_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_SELECT 0x3dc2 +#define regGL1A_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER1_SELECT1 0x3dc3 +#define regGL1A_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_SELECT 0x3dc4 +#define regGL1A_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER2_SELECT1 0x3dc5 +#define regGL1A_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_SELECT 0x3dc6 +#define regGL1A_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1A_PERFCOUNTER3_SELECT1 0x3dc7 +#define regGL1A_PERFCOUNTER3_SELECT1_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER0_SELECT 0x3dc8 +#define regGL1XA_PERFCOUNTER0_SELECT_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER0_SELECT1 0x3dc9 +#define regGL1XA_PERFCOUNTER0_SELECT1_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER1_SELECT 0x3dca +#define regGL1XA_PERFCOUNTER1_SELECT_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER1_SELECT1 0x3dcb +#define regGL1XA_PERFCOUNTER1_SELECT1_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER2_SELECT 0x3dcc +#define regGL1XA_PERFCOUNTER2_SELECT_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER2_SELECT1 0x3dcd +#define regGL1XA_PERFCOUNTER2_SELECT1_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER3_SELECT 0x3dce +#define regGL1XA_PERFCOUNTER3_SELECT_BASE_IDX 1 +#define regGL1XA_PERFCOUNTER3_SELECT1 0x3dcf +#define regGL1XA_PERFCOUNTER3_SELECT1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pwrdec +// base address: 0x3c000 +#define regGFX_ICG_SPI_RA0_CLK_CTRL 0x507a +#define regGFX_ICG_SPI_RA0_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_SPI_RA1_CLK_CTRL 0x507b +#define regGFX_ICG_SPI_RA1_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_SPI_CS_CTRL 0x507c +#define regGFX_ICG_SPI_CS_CTRL_BASE_IDX 1 +#define regGFX_ICG_SPI_PS_CTRL 0x507d +#define regGFX_ICG_SPI_PS_CTRL_BASE_IDX 1 +#define regGFX_ICG_SPIS_CTRL 0x507e +#define regGFX_ICG_SPIS_CTRL_BASE_IDX 1 +#define regCGTX_SPI_DEBUG_CLK_CTRL 0x507f +#define regCGTX_SPI_DEBUG_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_SPI_CTRL 0x5080 +#define regGFX_ICG_SPI_CTRL_BASE_IDX 1 +#define regGFX_ICG_PC_CLK_CTRL 0x5081 +#define regGFX_ICG_PC_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_BCI_CTRL 0x5082 +#define regGFX_ICG_BCI_CTRL_BASE_IDX 1 +#define regCGTT_VGT_CLK_CTRL 0x5084 +#define regCGTT_VGT_CLK_CTRL_BASE_IDX 1 +#define regCGTT_GS_NGG_CLK_CTRL 0x5087 +#define regCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 +#define regCGTT_PA_CLK_CTRL 0x5088 +#define regCGTT_PA_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SQ_CLK_CTRL 0x508c +#define regCGTT_SQ_CLK_CTRL_BASE_IDX 1 +#define regCGTT_SQG_CLK_CTRL 0x508d +#define regCGTT_SQG_CLK_CTRL_BASE_IDX 1 +#define regSQ_ALU_CLK_CTRL 0x508e +#define regSQ_ALU_CLK_CTRL_BASE_IDX 1 +#define regSQ_TEX_CLK_CTRL 0x508f +#define regSQ_TEX_CLK_CTRL_BASE_IDX 1 +#define regSQ_LDS_CLK_CTRL 0x5090 +#define regSQ_LDS_CLK_CTRL_BASE_IDX 1 +#define regSQ_CLK_CTRL 0x5091 +#define regSQ_CLK_CTRL_BASE_IDX 1 +#define regICG_SQ_CLK_CTRL 0x5092 +#define regICG_SQ_CLK_CTRL_BASE_IDX 1 +#define regICG_SP_CLK_CTRL 0x5093 +#define regICG_SP_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_SX_CLK_CTRL0 0x5094 +#define regGFX_ICG_SX_CLK_CTRL0_BASE_IDX 1 +#define regGFX_ICG_SX_CLK_CTRL1 0x5095 +#define regGFX_ICG_SX_CLK_CTRL1_BASE_IDX 1 +#define regGFX_ICG_SX_CLK_CTRL2 0x5096 +#define regGFX_ICG_SX_CLK_CTRL2_BASE_IDX 1 +#define regGFX_ICG_SX_CLK_CTRL3 0x5097 +#define regGFX_ICG_SX_CLK_CTRL3_BASE_IDX 1 +#define regGFX_ICG_SX_CLK_CTRL4 0x5098 +#define regGFX_ICG_SX_CLK_CTRL4_BASE_IDX 1 +#define regGFX_ICG_TA_CTRL 0x509e +#define regGFX_ICG_TA_CTRL_BASE_IDX 1 +#define regGFX_ICG_TD_CTRL 0x509f +#define regGFX_ICG_TD_CTRL_BASE_IDX 1 +#define regDB_CGTT_CLK_CTRL_0 0x50a4 +#define regDB_CGTT_CLK_CTRL_0_BASE_IDX 1 +#define regGFX_ICG_CB_CTRL 0x50a9 +#define regGFX_ICG_CB_CTRL_BASE_IDX 1 +#define regGFX_ICG_RMI_CTRL 0x50c0 +#define regGFX_ICG_RMI_CTRL_BASE_IDX 1 +#define regGFX_ICG_SE_CAC_CLK_CTRL 0x50d0 +#define regGFX_ICG_SE_CAC_CLK_CTRL_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL0 0x50f8 +#define regCGTT_PH_CLK_CTRL0_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL1 0x50f9 +#define regCGTT_PH_CLK_CTRL1_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL2 0x50fa +#define regCGTT_PH_CLK_CTRL2_BASE_IDX 1 +#define regCGTT_PH_CLK_CTRL3 0x50fb +#define regCGTT_PH_CLK_CTRL3_BASE_IDX 1 +#define regGFX_ICG_TCP_CTRL 0x5101 +#define regGFX_ICG_TCP_CTRL_BASE_IDX 1 +#define regGFX_ICG_TCP_CTRL2 0x5102 +#define regGFX_ICG_TCP_CTRL2_BASE_IDX 1 +#define regICG_LDS_CLK_CTRL 0x5114 +#define regICG_LDS_CLK_CTRL_BASE_IDX 1 +#define regGFX_ICG_UTCL1_CTRL 0x511c +#define regGFX_ICG_UTCL1_CTRL_BASE_IDX 1 +#define regGFX_ICG_GRBMH_CTRL 0x5120 +#define regGFX_ICG_GRBMH_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_sc_pwrdec +// base address: 0x3c344 +#define regCGTT_SC_CLK_CTRL0 0x50d1 +#define regCGTT_SC_CLK_CTRL0_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL1 0x50d2 +#define regCGTT_SC_CLK_CTRL1_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL2 0x50d3 +#define regCGTT_SC_CLK_CTRL2_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL3 0x50d4 +#define regCGTT_SC_CLK_CTRL3_BASE_IDX 1 +#define regCGTT_SC_CLK_CTRL4 0x50d5 +#define regCGTT_SC_CLK_CTRL4_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gl1_pwrdec +// base address: 0x3c364 +#define regICG_GL1C_CLK_CTRL 0x50d9 +#define regICG_GL1C_CLK_CTRL_BASE_IDX 1 +#define regGL1I_GL1R_MGCG_OVERRIDE 0x50da +#define regGL1I_GL1R_MGCG_OVERRIDE_BASE_IDX 1 +#define regGL1XI_GL1XR_MGCG_OVERRIDE 0x50db +#define regGL1XI_GL1XR_MGCG_OVERRIDE_BASE_IDX 1 +#define regICG_GL1XC_CLK_CTRL 0x50dc +#define regICG_GL1XC_CLK_CTRL_BASE_IDX 1 +#define regICG_GL1A_CTRL 0x50dd +#define regICG_GL1A_CTRL_BASE_IDX 1 +#define regICG_GL1XA_CTRL 0x50de +#define regICG_GL1XA_CTRL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_hypdec +// base address: 0x3e000 +#define regGL1_PIPE_STEER_LSB 0x5b84 +#define regGL1_PIPE_STEER_LSB_BASE_IDX 1 +#define regGL1_PIPE_STEER_MSB 0x5b85 +#define regGL1_PIPE_STEER_MSB_BASE_IDX 1 +#define regGL1_HASH_CFG 0x5b86 +#define regGL1_HASH_CFG_BASE_IDX 1 +#define regGC_USER_SHADER_ARRAY_CONFIG 0x5b90 +#define regGC_USER_SHADER_ARRAY_CONFIG_BASE_IDX 1 +#define regGC_USER_RB_BACKEND_DISABLE 0x5b94 +#define regGC_USER_RB_BACKEND_DISABLE_BASE_IDX 1 +#define regGC_USER_RMI_REDUNDANCY 0x5b95 +#define regGC_USER_RMI_REDUNDANCY_BASE_IDX 1 +#define regGC_USER_SHADER_RATE_CONFIG_1 0x5b97 +#define regGC_USER_SHADER_RATE_CONFIG_1_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_grbmh_hypdec +// base address: 0x3ee80 +#define regGRBMH_WGP_SA0_REMAP_CNTL 0x5ba0 +#define regGRBMH_WGP_SA0_REMAP_CNTL_BASE_IDX 1 +#define regGRBMH_WGP_SA1_REMAP_CNTL 0x5ba1 +#define regGRBMH_WGP_SA1_REMAP_CNTL_BASE_IDX 1 +#define regGRBMH_RB_SA0_REMAP_CNTL 0x5ba2 +#define regGRBMH_RB_SA0_REMAP_CNTL_BASE_IDX 1 +#define regGRBMH_RB_SA1_REMAP_CNTL 0x5ba3 +#define regGRBMH_RB_SA1_REMAP_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedpfdec +// base address: 0xa000 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x15a0 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x15a1 +#define regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 0 +#define regGCUTCL2_ICG_CTRL 0x15a2 +#define regGCUTCL2_ICG_CTRL_BASE_IDX 0 +#define regGCMC_SHARED_ACTIVE_FCN_ID 0x15a3 +#define regGCMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 0 +#define regGCUTCL2_CGTT_BUSY_CTRL 0x15a4 +#define regGCUTCL2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regGCUTCL2_GROUP_RET_FAULT_STATUS 0x15a5 +#define regGCUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pfdec +// base address: 0xa090 +#define regGCVM_L2_CNTL 0x15c4 +#define regGCVM_L2_CNTL_BASE_IDX 0 +#define regGCVM_L2_CNTL2 0x15c5 +#define regGCVM_L2_CNTL2_BASE_IDX 0 +#define regGCVM_L2_CNTL3 0x15c6 +#define regGCVM_L2_CNTL3_BASE_IDX 0 +#define regGCVM_L2_STATUS 0x15c7 +#define regGCVM_L2_STATUS_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_CNTL 0x15c8 +#define regGCVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x15c9 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x15ca +#define regGCVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_CNTL 0x15cb +#define regGCVM_INVALIDATE_CNTL_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_CNTL_LO32 0x15cc +#define regGCVM_L2_PROTECTION_FAULT_CNTL_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_CNTL_HI32 0x15cd +#define regGCVM_L2_PROTECTION_FAULT_CNTL_HI32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_CNTL2 0x15ce +#define regGCVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3 0x15cf +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4 0x15d0 +#define regGCVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_STATUS_LO32 0x15d1 +#define regGCVM_L2_PROTECTION_FAULT_STATUS_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_STATUS_HI32 0x15d2 +#define regGCVM_L2_PROTECTION_FAULT_STATUS_HI32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32 0x15d3 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32 0x15d4 +#define regGCVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x15d5 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x15d6 +#define regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0 +#define regGCVM_DEBUG 0x15d7 +#define regGCVM_DEBUG_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x15d8 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x15d9 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x15da +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x15db +#define regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x15dc +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 0 +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x15dd +#define regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 0 +#define regGCVM_L2_CNTL4 0x15de +#define regGCVM_L2_CNTL4_BASE_IDX 0 +#define regGCVM_L2_MM_GROUP_RT_CLASSES 0x15df +#define regGCVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID 0x15e0 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID2 0x15e1 +#define regGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0 +#define regGCVM_L2_CACHE_PARITY_CNTL 0x15e2 +#define regGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0 +#define regGCVM_L2_ICG_CTRL 0x15e3 +#define regGCVM_L2_ICG_CTRL_BASE_IDX 0 +#define regGCVM_L2_CNTL5 0x15e4 +#define regGCVM_L2_CNTL5_BASE_IDX 0 +#define regGCVM_L2_GCR_CNTL 0x15e5 +#define regGCVM_L2_GCR_CNTL_BASE_IDX 0 +#define regGCVML2_WALKER_MACRO_THROTTLE_TIME 0x15e6 +#define regGCVML2_WALKER_MACRO_THROTTLE_TIME_BASE_IDX 0 +#define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT 0x15e7 +#define regGCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 +#define regGCVML2_WALKER_MICRO_THROTTLE_TIME 0x15e8 +#define regGCVML2_WALKER_MICRO_THROTTLE_TIME_BASE_IDX 0 +#define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT 0x15e9 +#define regGCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT_BASE_IDX 0 +#define regGCVM_L2_CGTT_BUSY_CTRL 0x15ea +#define regGCVM_L2_CGTT_BUSY_CTRL_BASE_IDX 0 +#define regGCVM_L2_PTE_CACHE_DUMP_CNTL 0x15eb +#define regGCVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 0 +#define regGCVM_L2_PTE_CACHE_DUMP_READ 0x15ec +#define regGCVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 0 +#define regGCVML2_MAIN_DEBUG 0x15ed +#define regGCVML2_MAIN_DEBUG_BASE_IDX 0 +#define regGCVML2_WALKER_DEBUG 0x15ee +#define regGCVML2_WALKER_DEBUG_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32 0x15ef +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32 0x15f0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR 0x15f1 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32 0x15f2 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32 0x15f3 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32_BASE_IDX 0 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR 0x15f4 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR_BASE_IDX 0 +#define regGCVM_L2_BANK_SELECT_MASKS 0x15f5 +#define regGCVM_L2_BANK_SELECT_MASKS_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x15f6 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x15f7 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 0 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x15f8 +#define regGCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 0 +#define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x15f9 +#define regGCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 0 +#define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x15fa +#define regGCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 0 +#define regGCVM_L2_UTCL2_FED_VMID_STS 0x15fb +#define regGCVM_L2_UTCL2_FED_VMID_STS_BASE_IDX 0 +#define regGCVM_L2_UTCL2_FED_ACK_REG 0x15fc +#define regGCVM_L2_UTCL2_FED_ACK_REG_BASE_IDX 0 +#define regGCVML2_IH_FAULT_INTERRUPT_CNTL 0x15fd +#define regGCVML2_IH_FAULT_INTERRUPT_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpfdec +// base address: 0xa1d0 +#define regGC_L2TLB_TLB0_STATUS 0x1615 +#define regGC_L2TLB_TLB0_STATUS_BASE_IDX 0 +#define regGC_L2TLB_TLB0_RETRY_CNTL 0x1616 +#define regGC_L2TLB_TLB0_RETRY_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedvcdec +// base address: 0xa210 +#define regGCMC_VM_FB_LOCATION_BASE_LO32 0x1624 +#define regGCMC_VM_FB_LOCATION_BASE_LO32_BASE_IDX 0 +#define regGCMC_VM_FB_LOCATION_BASE_HI32 0x1625 +#define regGCMC_VM_FB_LOCATION_BASE_HI32_BASE_IDX 0 +#define regGCMC_VM_FB_LOCATION_TOP_LO32 0x1626 +#define regGCMC_VM_FB_LOCATION_TOP_LO32_BASE_IDX 0 +#define regGCMC_VM_FB_LOCATION_TOP_HI32 0x1627 +#define regGCMC_VM_FB_LOCATION_TOP_HI32_BASE_IDX 0 +#define regGCMC_VM_AGP_TOP_LO32 0x1628 +#define regGCMC_VM_AGP_TOP_LO32_BASE_IDX 0 +#define regGCMC_VM_AGP_TOP_HI32 0x1629 +#define regGCMC_VM_AGP_TOP_HI32_BASE_IDX 0 +#define regGCMC_VM_AGP_BOT_LO32 0x162a +#define regGCMC_VM_AGP_BOT_LO32_BASE_IDX 0 +#define regGCMC_VM_AGP_BOT_HI32 0x162b +#define regGCMC_VM_AGP_BOT_HI32_BASE_IDX 0 +#define regGCMC_VM_AGP_BASE_LO32 0x162c +#define regGCMC_VM_AGP_BASE_LO32_BASE_IDX 0 +#define regGCMC_VM_AGP_BASE_HI32 0x162d +#define regGCMC_VM_AGP_BASE_HI32_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32 0x162e +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32 0x162f +#define regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32 0x1630 +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32_BASE_IDX 0 +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32 0x1631 +#define regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32_BASE_IDX 0 +#define regGCMC_VM_MX_L1_TLB_CNTL 0x1632 +#define regGCMC_VM_MX_L1_TLB_CNTL_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2vcdec +// base address: 0xa250 +#define regGCVM_CONTEXT0_CNTL 0x1634 +#define regGCVM_CONTEXT0_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT1_CNTL 0x1635 +#define regGCVM_CONTEXT1_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT2_CNTL 0x1636 +#define regGCVM_CONTEXT2_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT3_CNTL 0x1637 +#define regGCVM_CONTEXT3_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT4_CNTL 0x1638 +#define regGCVM_CONTEXT4_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT5_CNTL 0x1639 +#define regGCVM_CONTEXT5_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT6_CNTL 0x163a +#define regGCVM_CONTEXT6_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT7_CNTL 0x163b +#define regGCVM_CONTEXT7_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT8_CNTL 0x163c +#define regGCVM_CONTEXT8_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT9_CNTL 0x163d +#define regGCVM_CONTEXT9_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT10_CNTL 0x163e +#define regGCVM_CONTEXT10_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT11_CNTL 0x163f +#define regGCVM_CONTEXT11_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT12_CNTL 0x1640 +#define regGCVM_CONTEXT12_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT13_CNTL 0x1641 +#define regGCVM_CONTEXT13_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT14_CNTL 0x1642 +#define regGCVM_CONTEXT14_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXT15_CNTL 0x1643 +#define regGCVM_CONTEXT15_CNTL_BASE_IDX 0 +#define regGCVM_CONTEXTS_DISABLE 0x1644 +#define regGCVM_CONTEXTS_DISABLE_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_SEM 0x1645 +#define regGCVM_INVALIDATE_ENG0_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_SEM 0x1646 +#define regGCVM_INVALIDATE_ENG1_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_SEM 0x1647 +#define regGCVM_INVALIDATE_ENG2_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_SEM 0x1648 +#define regGCVM_INVALIDATE_ENG3_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_SEM 0x1649 +#define regGCVM_INVALIDATE_ENG4_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_SEM 0x164a +#define regGCVM_INVALIDATE_ENG5_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_SEM 0x164b +#define regGCVM_INVALIDATE_ENG6_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_SEM 0x164c +#define regGCVM_INVALIDATE_ENG7_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_SEM 0x164d +#define regGCVM_INVALIDATE_ENG8_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_SEM 0x164e +#define regGCVM_INVALIDATE_ENG9_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_SEM 0x164f +#define regGCVM_INVALIDATE_ENG10_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_SEM 0x1650 +#define regGCVM_INVALIDATE_ENG11_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_SEM 0x1651 +#define regGCVM_INVALIDATE_ENG12_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_SEM 0x1652 +#define regGCVM_INVALIDATE_ENG13_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_SEM 0x1653 +#define regGCVM_INVALIDATE_ENG14_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_SEM 0x1654 +#define regGCVM_INVALIDATE_ENG15_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_SEM 0x1655 +#define regGCVM_INVALIDATE_ENG16_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_SEM 0x1656 +#define regGCVM_INVALIDATE_ENG17_SEM_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_REQ 0x1657 +#define regGCVM_INVALIDATE_ENG0_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_REQ 0x1658 +#define regGCVM_INVALIDATE_ENG1_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_REQ 0x1659 +#define regGCVM_INVALIDATE_ENG2_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_REQ 0x165a +#define regGCVM_INVALIDATE_ENG3_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_REQ 0x165b +#define regGCVM_INVALIDATE_ENG4_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_REQ 0x165c +#define regGCVM_INVALIDATE_ENG5_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_REQ 0x165d +#define regGCVM_INVALIDATE_ENG6_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_REQ 0x165e +#define regGCVM_INVALIDATE_ENG7_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_REQ 0x165f +#define regGCVM_INVALIDATE_ENG8_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_REQ 0x1660 +#define regGCVM_INVALIDATE_ENG9_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_REQ 0x1661 +#define regGCVM_INVALIDATE_ENG10_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_REQ 0x1662 +#define regGCVM_INVALIDATE_ENG11_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_REQ 0x1663 +#define regGCVM_INVALIDATE_ENG12_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_REQ 0x1664 +#define regGCVM_INVALIDATE_ENG13_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_REQ 0x1665 +#define regGCVM_INVALIDATE_ENG14_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_REQ 0x1666 +#define regGCVM_INVALIDATE_ENG15_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_REQ 0x1667 +#define regGCVM_INVALIDATE_ENG16_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_REQ 0x1668 +#define regGCVM_INVALIDATE_ENG17_REQ_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ACK 0x1669 +#define regGCVM_INVALIDATE_ENG0_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ACK 0x166a +#define regGCVM_INVALIDATE_ENG1_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ACK 0x166b +#define regGCVM_INVALIDATE_ENG2_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ACK 0x166c +#define regGCVM_INVALIDATE_ENG3_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ACK 0x166d +#define regGCVM_INVALIDATE_ENG4_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ACK 0x166e +#define regGCVM_INVALIDATE_ENG5_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ACK 0x166f +#define regGCVM_INVALIDATE_ENG6_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ACK 0x1670 +#define regGCVM_INVALIDATE_ENG7_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ACK 0x1671 +#define regGCVM_INVALIDATE_ENG8_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ACK 0x1672 +#define regGCVM_INVALIDATE_ENG9_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ACK 0x1673 +#define regGCVM_INVALIDATE_ENG10_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ACK 0x1674 +#define regGCVM_INVALIDATE_ENG11_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ACK 0x1675 +#define regGCVM_INVALIDATE_ENG12_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ACK 0x1676 +#define regGCVM_INVALIDATE_ENG13_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ACK 0x1677 +#define regGCVM_INVALIDATE_ENG14_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ACK 0x1678 +#define regGCVM_INVALIDATE_ENG15_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ACK 0x1679 +#define regGCVM_INVALIDATE_ENG16_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ACK 0x167a +#define regGCVM_INVALIDATE_ENG17_ACK_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x167b +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x167c +#define regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x167d +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x167e +#define regGCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x167f +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x1680 +#define regGCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x1681 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x1682 +#define regGCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x1683 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x1684 +#define regGCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x1685 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x1686 +#define regGCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x1687 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x1688 +#define regGCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x1689 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x168a +#define regGCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x168b +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x168c +#define regGCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x168d +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x168e +#define regGCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x168f +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x1690 +#define regGCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x1691 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x1692 +#define regGCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x1693 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x1694 +#define regGCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x1695 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x1696 +#define regGCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x1697 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x1698 +#define regGCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x1699 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x169a +#define regGCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x169b +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x169c +#define regGCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x169d +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 0 +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x169e +#define regGCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x169f +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x16a0 +#define regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x16a1 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x16a2 +#define regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x16a3 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x16a4 +#define regGCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x16a5 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x16a6 +#define regGCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x16a7 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x16a8 +#define regGCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x16a9 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x16aa +#define regGCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x16ab +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x16ac +#define regGCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x16ad +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x16ae +#define regGCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x16af +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x16b0 +#define regGCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x16b1 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x16b2 +#define regGCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x16b3 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x16b4 +#define regGCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x16b5 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x16b6 +#define regGCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x16b7 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x16b8 +#define regGCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x16b9 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x16ba +#define regGCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x16bb +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x16bc +#define regGCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x16bd +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x16be +#define regGCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x16bf +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x16c0 +#define regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x16c1 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x16c2 +#define regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x16c3 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x16c4 +#define regGCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x16c5 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x16c6 +#define regGCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x16c7 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x16c8 +#define regGCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x16c9 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x16ca +#define regGCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x16cb +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x16cc +#define regGCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x16cd +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x16ce +#define regGCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x16cf +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x16d0 +#define regGCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x16d1 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x16d2 +#define regGCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x16d3 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x16d4 +#define regGCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x16d5 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x16d6 +#define regGCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x16d7 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x16d8 +#define regGCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x16d9 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x16da +#define regGCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x16db +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x16dc +#define regGCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x16dd +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x16de +#define regGCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x16df +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x16e0 +#define regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x16e1 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x16e2 +#define regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x16e3 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x16e4 +#define regGCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x16e5 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x16e6 +#define regGCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x16e7 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x16e8 +#define regGCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x16e9 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x16ea +#define regGCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x16eb +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x16ec +#define regGCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x16ed +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x16ee +#define regGCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x16ef +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x16f0 +#define regGCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x16f1 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x16f2 +#define regGCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x16f3 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x16f4 +#define regGCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x16f5 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x16f6 +#define regGCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x16f7 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x16f8 +#define regGCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x16f9 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x16fa +#define regGCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x16fb +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x16fc +#define regGCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x16fd +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x16fe +#define regGCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 +#define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x16ff +#define regGCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1700 +#define regGCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1701 +#define regGCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1702 +#define regGCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1703 +#define regGCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1704 +#define regGCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1705 +#define regGCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1706 +#define regGCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1707 +#define regGCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1708 +#define regGCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x1709 +#define regGCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170a +#define regGCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170b +#define regGCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170c +#define regGCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170d +#define regGCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170e +#define regGCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 +#define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x170f +#define regGCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedvfdec +// base address: 0xa5d0 +#define regGCMC_VM_PCIE_ATOMIC_SUPPORTED 0x1714 +#define regGCMC_VM_PCIE_ATOMIC_SUPPORTED_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbvfdec +// base address: 0xa5e0 +#define regGC_L2TLB_TLB0_EN_RETRY_ON_ATOMIC 0x1718 +#define regGC_L2TLB_TLB0_EN_RETRY_ON_ATOMIC_BASE_IDX 0 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2prdec +// base address: 0x35380 +#define regGCMC_VM_L2_PERFCOUNTER_LO 0x34e0 +#define regGCMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER_HI 0x34e1 +#define regGCMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_LO 0x34e2 +#define regGCUTCL2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_HI 0x34e3 +#define regGCUTCL2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2prdec +// base address: 0x353c0 +#define regGC_ATC_L2_PERFCOUNTER_LO 0x34f0 +#define regGC_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER_HI 0x34f1 +#define regGC_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbprdec +// base address: 0x353f0 +#define regGC_L2TLB_PERFCOUNTER_LO 0x34fc +#define regGC_L2TLB_PERFCOUNTER_LO_BASE_IDX 1 +#define regGC_L2TLB_PERFCOUNTER_HI 0x34fd +#define regGC_L2TLB_PERFCOUNTER_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pldec +// base address: 0x37b00 +#define regGCMC_VM_L2_PERFCOUNTER0_CFG 0x3ec0 +#define regGCMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER1_CFG 0x3ec1 +#define regGCMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER2_CFG 0x3ec2 +#define regGCMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER3_CFG 0x3ec3 +#define regGCMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER4_CFG 0x3ec4 +#define regGCMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER5_CFG 0x3ec5 +#define regGCMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER6_CFG 0x3ec6 +#define regGCMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER7_CFG 0x3ec7 +#define regGCMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER8_CFG 0x3ec8 +#define regGCMC_VM_L2_PERFCOUNTER8_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER9_CFG 0x3ec9 +#define regGCMC_VM_L2_PERFCOUNTER9_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER10_CFG 0x3eca +#define regGCMC_VM_L2_PERFCOUNTER10_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER11_CFG 0x3ecb +#define regGCMC_VM_L2_PERFCOUNTER11_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER12_CFG 0x3ecc +#define regGCMC_VM_L2_PERFCOUNTER12_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER13_CFG 0x3ecd +#define regGCMC_VM_L2_PERFCOUNTER13_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER14_CFG 0x3ece +#define regGCMC_VM_L2_PERFCOUNTER14_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER15_CFG 0x3ecf +#define regGCMC_VM_L2_PERFCOUNTER15_CFG_BASE_IDX 1 +#define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3ed0 +#define regGCMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER0_CFG 0x3ed1 +#define regGCUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER1_CFG 0x3ed2 +#define regGCUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER2_CFG 0x3ed3 +#define regGCUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER3_CFG 0x3ed4 +#define regGCUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_RSLT_CNTL 0x3ed5 +#define regGCUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 +#define regGCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT 0x3ed6 +#define regGCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2pldec +// base address: 0x37b60 +#define regGC_ATC_L2_PERFCOUNTER0_CFG 0x3ed8 +#define regGC_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER1_CFG 0x3ed9 +#define regGC_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER2_CFG 0x3eda +#define regGC_ATC_L2_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER3_CFG 0x3edb +#define regGC_ATC_L2_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER4_CFG 0x3edc +#define regGC_ATC_L2_PERFCOUNTER4_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER5_CFG 0x3edd +#define regGC_ATC_L2_PERFCOUNTER5_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER6_CFG 0x3ede +#define regGC_ATC_L2_PERFCOUNTER6_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER7_CFG 0x3edf +#define regGC_ATC_L2_PERFCOUNTER7_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER8_CFG 0x3ee0 +#define regGC_ATC_L2_PERFCOUNTER8_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER9_CFG 0x3ee1 +#define regGC_ATC_L2_PERFCOUNTER9_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER10_CFG 0x3ee2 +#define regGC_ATC_L2_PERFCOUNTER10_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER11_CFG 0x3ee3 +#define regGC_ATC_L2_PERFCOUNTER11_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER12_CFG 0x3ee4 +#define regGC_ATC_L2_PERFCOUNTER12_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER13_CFG 0x3ee5 +#define regGC_ATC_L2_PERFCOUNTER13_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER14_CFG 0x3ee6 +#define regGC_ATC_L2_PERFCOUNTER14_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER15_CFG 0x3ee7 +#define regGC_ATC_L2_PERFCOUNTER15_CFG_BASE_IDX 1 +#define regGC_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x3ee8 +#define regGC_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpldec +// base address: 0x37c50 +#define regGC_L2TLB_PERFCOUNTER0_CFG 0x3f14 +#define regGC_L2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 +#define regGC_L2TLB_PERFCOUNTER1_CFG 0x3f15 +#define regGC_L2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 +#define regGC_L2TLB_PERFCOUNTER2_CFG 0x3f16 +#define regGC_L2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 +#define regGC_L2TLB_PERFCOUNTER3_CFG 0x3f17 +#define regGC_L2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 +#define regGC_L2TLB_PERFCOUNTER_RSLT_CNTL 0x3f18 +#define regGC_L2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedhvdec +// base address: 0x3e800 +#define regGCVM_PCIE_ATS_CNTL 0x5a00 +#define regGCVM_PCIE_ATS_CNTL_BASE_IDX 1 +#define regGCMC_VM_NB_MMIOBASE 0x5a01 +#define regGCMC_VM_NB_MMIOBASE_BASE_IDX 1 +#define regGCMC_VM_NB_MMIOLIMIT 0x5a02 +#define regGCMC_VM_NB_MMIOLIMIT_BASE_IDX 1 +#define regGCMC_VM_NB_PCI_CTRL 0x5a03 +#define regGCMC_VM_NB_PCI_CTRL_BASE_IDX 1 +#define regGCMC_VM_NB_PCI_ARB 0x5a04 +#define regGCMC_VM_NB_PCI_ARB_BASE_IDX 1 +#define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1 0x5a05 +#define regGCMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 +#define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2 0x5a06 +#define regGCMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 +#define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2 0x5a07 +#define regGCMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 +#define regGCMC_VM_STEERING 0x5a08 +#define regGCMC_VM_STEERING_BASE_IDX 1 +#define regGCMC_SHARED_VIRT_RESET_REQ 0x5a09 +#define regGCMC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 +#define regGCMC_VM_XGMI_LFB_CNTL 0x5a0a +#define regGCMC_VM_XGMI_LFB_CNTL_BASE_IDX 1 +#define regGCMC_VM_XGMI_LFB_SIZE 0x5a0b +#define regGCMC_VM_XGMI_LFB_SIZE_BASE_IDX 1 +#define regGCMC_VM_HOST_MAPPING 0x5a0c +#define regGCMC_VM_HOST_MAPPING_BASE_IDX 1 +#define regGCMC_VM_XGMI_GPUIOV_ENABLE 0x5a0d +#define regGCMC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1 +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x5a0e +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x5a0f +#define regGCMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x5a10 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 1 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x5a11 +#define regGCMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 1 +#define regGCMC_VM_LPDDR_ADDRESS_START 0x5a12 +#define regGCMC_VM_LPDDR_ADDRESS_START_BASE_IDX 1 +#define regGCMC_VM_LPDDR_ADDRESS_END 0x5a13 +#define regGCMC_VM_LPDDR_ADDRESS_END_BASE_IDX 1 +#define regGCMC_VM_APT_CNTL 0x5a14 +#define regGCMC_VM_APT_CNTL_BASE_IDX 1 +#define regGCUTCL2_HARVEST_BYPASS_GROUPS 0x5a15 +#define regGCUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 1 +#define regGCUTCL2_ROUTER_DEBUG 0x5a16 +#define regGCUTCL2_ROUTER_DEBUG_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2dec +// base address: 0x3e9f0 +#define regGC_ATC_L2_CNTL 0x5a7c +#define regGC_ATC_L2_CNTL_BASE_IDX 1 +#define regGC_ATC_L2_CNTL2 0x5a7d +#define regGC_ATC_L2_CNTL2_BASE_IDX 1 +#define regGC_ATC_L2_CACHE_DATA0 0x5a80 +#define regGC_ATC_L2_CACHE_DATA0_BASE_IDX 1 +#define regGC_ATC_L2_CACHE_DATA1 0x5a81 +#define regGC_ATC_L2_CACHE_DATA1_BASE_IDX 1 +#define regGC_ATC_L2_CACHE_DATA2 0x5a82 +#define regGC_ATC_L2_CACHE_DATA2_BASE_IDX 1 +#define regGC_ATC_L2_CACHE_DATA3 0x5a83 +#define regGC_ATC_L2_CACHE_DATA3_BASE_IDX 1 +#define regGC_ATC_L2_CACHE_DATA4 0x5a84 +#define regGC_ATC_L2_CACHE_DATA4_BASE_IDX 1 +#define regGC_ATC_L2_CNTL3 0x5a85 +#define regGC_ATC_L2_CNTL3_BASE_IDX 1 +#define regGC_ATC_L2_STATUS 0x5a86 +#define regGC_ATC_L2_STATUS_BASE_IDX 1 +#define regGC_ATC_L2_MISC_CG 0x5a87 +#define regGC_ATC_L2_MISC_CG_BASE_IDX 1 +#define regGC_ATC_L2_ICG_CTRL 0x5a88 +#define regGC_ATC_L2_ICG_CTRL_BASE_IDX 1 +#define regGC_ATC_L2_SDPPORT_CTRL 0x5a8b +#define regGC_ATC_L2_SDPPORT_CTRL_BASE_IDX 1 +#define regGC_ATC_L2_MISC_DEBUG 0x5a8c +#define regGC_ATC_L2_MISC_DEBUG_BASE_IDX 1 +#define regGC_ATC_L2_BANK_SELECT_MASKS 0x5a8d +#define regGC_ATC_L2_BANK_SELECT_MASKS_BASE_IDX 1 +#define regGC_ATC_L2_FAULT_CNTL 0x5a8e +#define regGC_ATC_L2_FAULT_CNTL_BASE_IDX 1 +#define regGC_ATC_L2_FAULT_STATUS 0x5a8f +#define regGC_ATC_L2_FAULT_STATUS_BASE_IDX 1 +#define regGC_ATC_L2_FAULT_ADDR_LO 0x5a90 +#define regGC_ATC_L2_FAULT_ADDR_LO_BASE_IDX 1 +#define regGC_ATC_L2_FAULT_ADDR_HI 0x5a91 +#define regGC_ATC_L2_FAULT_ADDR_HI_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbhvdec +// base address: 0x3eb20 +#define regGC_L2TLB_TMZ_CNTL 0x5ac9 +#define regGC_L2TLB_TMZ_CNTL_BASE_IDX 1 +#define regGC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 0x5aca +#define regGC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1 +#define regGC_L2TLB_GCC_MTYPE_ENCODING_CNTL 0x5acb +#define regGC_L2TLB_GCC_MTYPE_ENCODING_CNTL_BASE_IDX 1 +#define regGC_L2TLB_FB_COMP_EN_CNTL 0x5acc +#define regGC_L2TLB_FB_COMP_EN_CNTL_BASE_IDX 1 +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_0 0x5acd +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_0_BASE_IDX 1 +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_1 0x5ace +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_1_BASE_IDX 1 +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_2 0x5acf +#define regGC_L2TLB_RETRY_TIMEOUT_STATUS_2_BASE_IDX 1 +#define regGC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS 0x5ad0 +#define regGC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pspdec +// base address: 0x3f900 +#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID 0x5e40 +#define regGCUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 +#define regGCVML2_SEC_MASTER 0x5e41 +#define regGCVML2_SEC_MASTER_BASE_IDX 1 +#define regGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE 0x5e42 +#define regGCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX 1 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x5e43 +#define regGCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1 +#define regGCVM_IOMMU_CONTROL_REGISTER 0x5e44 +#define regGCVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 +#define regGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x5e45 +#define regGCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 +#define regGCUTC_TRANSLATION_FAULT_CNTL0 0x5e46 +#define regGCUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1 +#define regGCUTC_TRANSLATION_FAULT_CNTL1 0x5e47 +#define regGCUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1 +#define regGCUTCL2_COMP_EN_OVERRIDES 0x5e49 +#define regGCUTCL2_COMP_EN_OVERRIDES_BASE_IDX 1 +#define regGCUTCL2_ROUTER_CNTL 0x5e4a +#define regGCUTCL2_ROUTER_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedpspdec +// base address: 0x3f950 +#define regGCMC_VM_FB_SIZE_OFFSET_VF0 0x5e54 +#define regGCMC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF1 0x5e55 +#define regGCMC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF2 0x5e56 +#define regGCMC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF3 0x5e57 +#define regGCMC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF4 0x5e58 +#define regGCMC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF5 0x5e59 +#define regGCMC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF6 0x5e5a +#define regGCMC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1 +#define regGCMC_VM_FB_SIZE_OFFSET_VF7 0x5e5b +#define regGCMC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1 +#define regGCMC_VM_FB_OFFSET 0x5e5c +#define regGCMC_VM_FB_OFFSET_BASE_IDX 1 +#define regGCMC_VM_LOCAL_FB_ADDRESS_START 0x5e5d +#define regGCMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 1 +#define regGCMC_VM_LOCAL_FB_ADDRESS_END 0x5e5e +#define regGCMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 1 +#define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x5e5f +#define regGCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 1 +#define regGCUTCL2_MISC_CNTL 0x5e64 +#define regGCUTCL2_MISC_CNTL_BASE_IDX 1 + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpspdec +// base address: 0x3fa00 +#define regGC_L2TLB_TLB0_CAM_ECC_CNTL 0x5e80 +#define regGC_L2TLB_TLB0_CAM_ECC_CNTL_BASE_IDX 1 + + +// addressBlock: gfx_se_sqind +// base address: 0x0 +#define ixSQ_DEBUG_STS_LOCAL 0x0008 +#define ixSQ_DEBUG_CTRL_LOCAL 0x0009 +#define ixSQ_WAVE_ACTIVE 0x000a +#define ixSQ_WAVE_VALID_AND_IDLE 0x000b +#define ixSQ_WAVE_MODE 0x0101 +#define ixSQ_WAVE_STATUS 0x0102 +#define ixSQ_WAVE_STATE_PRIV 0x0104 +#define ixSQ_WAVE_GPR_ALLOC 0x0105 +#define ixSQ_WAVE_LDS_ALLOC 0x0106 +#define ixSQ_WAVE_IB_STS 0x0107 +#define ixSQ_PERF_SNAPSHOT_DATA 0x010a +#define ixSQ_PERF_SNAPSHOT_PC_LO 0x010b +#define ixSQ_PERF_SNAPSHOT_PC_HI 0x010c +#define ixSQ_WAVE_IB_DBG1 0x010d +#define ixSQ_WAVE_FLUSH_IB 0x010e +#define ixSQ_PERF_SNAPSHOT_DATA1 0x010f +#define ixSQ_PERF_SNAPSHOT_DATA2 0x0110 +#define ixSQ_WAVE_EXCP_FLAG_PRIV 0x0111 +#define ixSQ_WAVE_EXCP_FLAG_USER 0x0112 +#define ixSQ_WAVE_TRAP_CTRL 0x0113 +#define ixSQ_WAVE_SCRATCH_BASE_LO 0x0114 +#define ixSQ_WAVE_SCRATCH_BASE_HI 0x0115 +#define ixSQ_WAVE_HW_ID1 0x0117 +#define ixSQ_WAVE_HW_ID2 0x0118 +#define ixSQ_WAVE_SCHED_MODE 0x011a +#define ixSQ_WAVE_IB_STS2 0x011c +#define ixSQ_WAVE_DVGPR_ALLOC_LO 0x011f +#define ixSQ_WAVE_DVGPR_ALLOC_HI 0x0120 +#define ixSQ_WAVE_XNACK_STATE_PRIV 0x0121 +#define ixSQ_WAVE_XNACK_MASK 0x0122 +#define ixSQ_WAVE_PC_LO 0x0140 +#define ixSQ_WAVE_PC_HI 0x0141 +#define ixSQ_WAVE_TTMP0 0x026c +#define ixSQ_WAVE_TTMP1 0x026d +#define ixSQ_WAVE_TTMP2 0x026e +#define ixSQ_WAVE_TTMP3 0x026f +#define ixSQ_WAVE_TTMP4 0x0270 +#define ixSQ_WAVE_TTMP5 0x0271 +#define ixSQ_WAVE_TTMP6 0x0272 +#define ixSQ_WAVE_TTMP7 0x0273 +#define ixSQ_WAVE_TTMP8 0x0274 +#define ixSQ_WAVE_TTMP9 0x0275 +#define ixSQ_WAVE_TTMP10 0x0276 +#define ixSQ_WAVE_TTMP11 0x0277 +#define ixSQ_WAVE_TTMP12 0x0278 +#define ixSQ_WAVE_TTMP13 0x0279 +#define ixSQ_WAVE_TTMP14 0x027a +#define ixSQ_WAVE_TTMP15 0x027b +#define ixSQ_WAVE_M0 0x027d +#define ixSQ_WAVE_EXEC_LO 0x027e +#define ixSQ_WAVE_EXEC_HI 0x027f + + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h new file mode 100644 index 000000000000..4db680044a83 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h @@ -0,0 +1,44620 @@ +/* + * Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _gc_12_1_0_SH_MASK_HEADER +#define _gc_12_1_0_SH_MASK_HEADER + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmadec +//SDMA0_SDMA_DEC_START +#define SDMA0_SDMA_DEC_START__START__SHIFT 0x0 +#define SDMA0_SDMA_DEC_START__START_MASK 0xFFFFFFFFL +//SDMA0_SDMA_MCU_MISC_CNTL +#define SDMA0_SDMA_MCU_MISC_CNTL__MCU_WAKEUP__SHIFT 0x0 +#define SDMA0_SDMA_MCU_MISC_CNTL__MCU_WAKEUP_MASK 0x00000001L +//SDMA0_SDMA_UCODE_REV +#define SDMA0_SDMA_UCODE_REV__P4_CL__SHIFT 0x0 +#define SDMA0_SDMA_UCODE_REV__DEBUG_VER__SHIFT 0x18 +#define SDMA0_SDMA_UCODE_REV__VARIANT_ID__SHIFT 0x1c +#define SDMA0_SDMA_UCODE_REV__P4_CL_MASK 0x00FFFFFFL +#define SDMA0_SDMA_UCODE_REV__DEBUG_VER_MASK 0x0F000000L +#define SDMA0_SDMA_UCODE_REV__VARIANT_ID_MASK 0xF0000000L +//SDMA0_SDMA_GLOBAL_TIMESTAMP_LO +#define SDMA0_SDMA_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_GLOBAL_TIMESTAMP_HI +#define SDMA0_SDMA_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_POWER_CNTL +#define SDMA0_SDMA_POWER_CNTL__LS_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_POWER_CNTL__LS_ENABLE_MASK 0x00000100L +//SDMA0_SDMA_CNTL +#define SDMA0_SDMA_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_CNTL__RESERVED__SHIFT 0x2 +#define SDMA0_SDMA_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA0_SDMA_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA0_SDMA_CNTL__PIO_DONE_ACK_ENABLE__SHIFT 0x6 +#define SDMA0_SDMA_CNTL__CP_MES_SYNC_ENABLE__SHIFT 0x7 +#define SDMA0_SDMA_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_CNTL__PAGE_NULL_INT_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA0_SDMA_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA0_SDMA_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA0_SDMA_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f +#define SDMA0_SDMA_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_CNTL__RESERVED_MASK 0x00000004L +#define SDMA0_SDMA_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA0_SDMA_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA0_SDMA_CNTL__PIO_DONE_ACK_ENABLE_MASK 0x00000040L +#define SDMA0_SDMA_CNTL__CP_MES_SYNC_ENABLE_MASK 0x00000080L +#define SDMA0_SDMA_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_CNTL__CP_MES_INT_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_CNTL__PAGE_NULL_INT_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_CNTL__PAGE_FAULT_INT_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA0_SDMA_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA0_SDMA_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +#define SDMA0_SDMA_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L +//SDMA0_SDMA_CHICKEN_BITS +#define SDMA0_SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x5 +#define SDMA0_SDMA_CHICKEN_BITS__RD_BURST__SHIFT 0x6 +#define SDMA0_SDMA_CHICKEN_BITS__WR_BURST__SHIFT 0x8 +#define SDMA0_SDMA_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa +#define SDMA0_SDMA_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT 0xe +#define SDMA0_SDMA_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT 0xf +#define SDMA0_SDMA_CHICKEN_BITS__OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT 0x13 +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT 0x14 +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT 0x15 +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT 0x16 +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT 0x17 +#define SDMA0_SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x18 +#define SDMA0_SDMA_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT 0x19 +#define SDMA0_SDMA_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL__SHIFT 0x1a +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_REG_ADDR_CHECK__SHIFT 0x1b +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CANE_FGCG__SHIFT 0x1c +#define SDMA0_SDMA_CHICKEN_BITS__RESERVED__SHIFT 0x1d +#define SDMA0_SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00000020L +#define SDMA0_SDMA_CHICKEN_BITS__RD_BURST_MASK 0x000000C0L +#define SDMA0_SDMA_CHICKEN_BITS__WR_BURST_MASK 0x00000300L +#define SDMA0_SDMA_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK 0x00003C00L +#define SDMA0_SDMA_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK 0x00004000L +#define SDMA0_SDMA_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK 0x00008000L +#define SDMA0_SDMA_CHICKEN_BITS__OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK 0x00080000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK 0x00100000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK 0x00200000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK 0x00400000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK 0x00800000L +#define SDMA0_SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x01000000L +#define SDMA0_SDMA_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK 0x02000000L +#define SDMA0_SDMA_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL_MASK 0x04000000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_REG_ADDR_CHECK_MASK 0x08000000L +#define SDMA0_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CANE_FGCG_MASK 0x10000000L +#define SDMA0_SDMA_CHICKEN_BITS__RESERVED_MASK 0xE0000000L +//SDMA0_SDMA_CACHE_CNTL +#define SDMA0_SDMA_CACHE_CNTL__RD_TEMPORAL_HINT__SHIFT 0x0 +#define SDMA0_SDMA_CACHE_CNTL__WR_TEMPORAL_HINT__SHIFT 0x3 +#define SDMA0_SDMA_CACHE_CNTL__RD_SCOPE__SHIFT 0xc +#define SDMA0_SDMA_CACHE_CNTL__WR_SCOPE__SHIFT 0xe +#define SDMA0_SDMA_CACHE_CNTL__RD_TEMPORAL_HINT_MASK 0x00000007L +#define SDMA0_SDMA_CACHE_CNTL__WR_TEMPORAL_HINT_MASK 0x00000038L +#define SDMA0_SDMA_CACHE_CNTL__RD_SCOPE_MASK 0x00003000L +#define SDMA0_SDMA_CACHE_CNTL__WR_SCOPE_MASK 0x0000C000L +//SDMA0_SDMA_RB_RPTR_FETCH +#define SDMA0_SDMA_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA0_SDMA_RB_RPTR_FETCH_HI +#define SDMA0_SDMA_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_IB_OFFSET_FETCH +#define SDMA0_SDMA_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_PROGRAM +#define SDMA0_SDMA_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA0_SDMA_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA0_SDMA_STATUS_REG +#define SDMA0_SDMA_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA0_SDMA_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA0_SDMA_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA0_SDMA_STATUS_REG__RESERVED_3__SHIFT 0x3 +#define SDMA0_SDMA_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA0_SDMA_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA0_SDMA_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA0_SDMA_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA0_SDMA_STATUS_REG__CORE_IDLE__SHIFT 0x8 +#define SDMA0_SDMA_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA0_SDMA_STATUS_REG__FETCH_IDLE__SHIFT 0xa +#define SDMA0_SDMA_STATUS_REG__CGCG_FENCE__SHIFT 0xb +#define SDMA0_SDMA_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA0_SDMA_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA0_SDMA_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA0_SDMA_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA0_SDMA_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA0_SDMA_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA0_SDMA_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA0_SDMA_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA0_SDMA_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA0_SDMA_STATUS_REG__RESERVED_24_21__SHIFT 0x15 +#define SDMA0_SDMA_STATUS_REG__EXEC_ENG_IDLE__SHIFT 0x19 +#define SDMA0_SDMA_STATUS_REG__PROC_CNTL_IDLE__SHIFT 0x1a +#define SDMA0_SDMA_STATUS_REG__UCODE_INIT_DONE__SHIFT 0x1b +#define SDMA0_SDMA_STATUS_REG__RESERVED_29_28__SHIFT 0x1c +#define SDMA0_SDMA_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA0_SDMA_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA0_SDMA_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA0_SDMA_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA0_SDMA_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA0_SDMA_STATUS_REG__RESERVED_3_MASK 0x00000008L +#define SDMA0_SDMA_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA0_SDMA_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA0_SDMA_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA0_SDMA_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA0_SDMA_STATUS_REG__CORE_IDLE_MASK 0x00000100L +#define SDMA0_SDMA_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA0_SDMA_STATUS_REG__FETCH_IDLE_MASK 0x00000400L +#define SDMA0_SDMA_STATUS_REG__CGCG_FENCE_MASK 0x00000800L +#define SDMA0_SDMA_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA0_SDMA_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA0_SDMA_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA0_SDMA_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA0_SDMA_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA0_SDMA_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA0_SDMA_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA0_SDMA_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA0_SDMA_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA0_SDMA_STATUS_REG__RESERVED_24_21_MASK 0x01E00000L +#define SDMA0_SDMA_STATUS_REG__EXEC_ENG_IDLE_MASK 0x02000000L +#define SDMA0_SDMA_STATUS_REG__PROC_CNTL_IDLE_MASK 0x04000000L +#define SDMA0_SDMA_STATUS_REG__UCODE_INIT_DONE_MASK 0x08000000L +#define SDMA0_SDMA_STATUS_REG__RESERVED_29_28_MASK 0x30000000L +#define SDMA0_SDMA_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA0_SDMA_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA0_SDMA_STATUS1_REG +#define SDMA0_SDMA_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA0_SDMA_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA0_SDMA_STATUS1_REG__CE_SPLIT_RD_IDLE__SHIFT 0x2 +#define SDMA0_SDMA_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA0_SDMA_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA0_SDMA_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA0_SDMA_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA0_SDMA_STATUS1_REG__CE_WR_TRACK_IDLE__SHIFT 0x7 +#define SDMA0_SDMA_STATUS1_REG__CE_SPLIT_WR_IDLE__SHIFT 0x8 +#define SDMA0_SDMA_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA0_SDMA_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA0_SDMA_STATUS1_REG__CE_INFO_FULL__SHIFT 0xb +#define SDMA0_SDMA_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xc +#define SDMA0_SDMA_STATUS1_REG__EX_START__SHIFT 0xd +#define SDMA0_SDMA_STATUS1_REG__CE_RD_STALL__SHIFT 0xf +#define SDMA0_SDMA_STATUS1_REG__CE_WR_STALL__SHIFT 0x10 +#define SDMA0_SDMA_STATUS1_REG__SEC_INTR_STATUS__SHIFT 0x11 +#define SDMA0_SDMA_STATUS1_REG__WPTR_POLL_IDLE__SHIFT 0x12 +#define SDMA0_SDMA_STATUS1_REG__SDMA_IDLE__SHIFT 0x13 +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_IDLE__SHIFT 0x14 +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_FAULT__SHIFT 0x15 +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_RETRY_TIMEOUT__SHIFT 0x16 +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_NULL__SHIFT 0x17 +#define SDMA0_SDMA_STATUS1_REG__MCU_FW_STACK_OVERFLOW__SHIFT 0x18 +#define SDMA0_SDMA_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA0_SDMA_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA0_SDMA_STATUS1_REG__CE_SPLIT_RD_IDLE_MASK 0x00000004L +#define SDMA0_SDMA_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA0_SDMA_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA0_SDMA_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA0_SDMA_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA0_SDMA_STATUS1_REG__CE_WR_TRACK_IDLE_MASK 0x00000080L +#define SDMA0_SDMA_STATUS1_REG__CE_SPLIT_WR_IDLE_MASK 0x00000100L +#define SDMA0_SDMA_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA0_SDMA_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA0_SDMA_STATUS1_REG__CE_INFO_FULL_MASK 0x00000800L +#define SDMA0_SDMA_STATUS1_REG__CE_INFO1_FULL_MASK 0x00001000L +#define SDMA0_SDMA_STATUS1_REG__EX_START_MASK 0x00002000L +#define SDMA0_SDMA_STATUS1_REG__CE_RD_STALL_MASK 0x00008000L +#define SDMA0_SDMA_STATUS1_REG__CE_WR_STALL_MASK 0x00010000L +#define SDMA0_SDMA_STATUS1_REG__SEC_INTR_STATUS_MASK 0x00020000L +#define SDMA0_SDMA_STATUS1_REG__WPTR_POLL_IDLE_MASK 0x00040000L +#define SDMA0_SDMA_STATUS1_REG__SDMA_IDLE_MASK 0x00080000L +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_IDLE_MASK 0x00100000L +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_FAULT_MASK 0x00200000L +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_RETRY_TIMEOUT_MASK 0x00400000L +#define SDMA0_SDMA_STATUS1_REG__IC_FETCH_PAGE_NULL_MASK 0x00800000L +#define SDMA0_SDMA_STATUS1_REG__MCU_FW_STACK_OVERFLOW_MASK 0x03000000L +//SDMA0_SDMA_CNTL1 +#define SDMA0_SDMA_CNTL1__WPTR_POLL_FREQUENCY__SHIFT 0x2 +#define SDMA0_SDMA_CNTL1__WPTR_POLL_FREQUENCY_MASK 0x0000FFFCL +//SDMA0_SDMA_HBM_PAGE_CONFIG +#define SDMA0_SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA0_SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA0_SDMA_FREEZE +#define SDMA0_SDMA_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA0_SDMA_FREEZE__MCU_FREEZE__SHIFT 0x6 +#define SDMA0_SDMA_FREEZE__IMU_FSM_STATE__SHIFT 0x8 +#define SDMA0_SDMA_FREEZE__EXTERNAL_FROZEN__SHIFT 0xc +#define SDMA0_SDMA_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA0_SDMA_FREEZE__MCU_FREEZE_MASK 0x00000040L +#define SDMA0_SDMA_FREEZE__IMU_FSM_STATE_MASK 0x00000300L +#define SDMA0_SDMA_FREEZE__EXTERNAL_FROZEN_MASK 0x00001000L +//SDMA0_SDMA_PROCESS_QUANTUM0 +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L +#define SDMA0_SDMA_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L +//SDMA0_SDMA_PROCESS_QUANTUM1 +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L +#define SDMA0_SDMA_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L +//SDMA0_SDMA_WATCHDOG_CNTL +#define SDMA0_SDMA_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 +#define SDMA0_SDMA_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 +#define SDMA0_SDMA_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL +#define SDMA0_SDMA_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE_STATUS0 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L +#define SDMA0_SDMA_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L +//SDMA0_SDMA_QUEUE_STATUS1 +#define SDMA0_SDMA_QUEUE_STATUS1__QUEUE8_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE_STATUS1__QUEUE9_STATUS__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE_STATUS1__QUEUE8_STATUS_MASK 0x0000000FL +#define SDMA0_SDMA_QUEUE_STATUS1__QUEUE9_STATUS_MASK 0x000000F0L +//SDMA0_SDMA_ID +#define SDMA0_SDMA_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA0_SDMA_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA0_SDMA_VERSION +#define SDMA0_SDMA_VERSION__MINVER__SHIFT 0x0 +#define SDMA0_SDMA_VERSION__MAJVER__SHIFT 0x8 +#define SDMA0_SDMA_VERSION__REV__SHIFT 0x10 +#define SDMA0_SDMA_VERSION__MINVER_MASK 0x0000007FL +#define SDMA0_SDMA_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA0_SDMA_VERSION__REV_MASK 0x003F0000L +//SDMA0_SDMA_STATUS2_REG +#define SDMA0_SDMA_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA0_SDMA_STATUS2_REG__TH0MCU_INSTR_PTR__SHIFT 0x2 +#define SDMA0_SDMA_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA0_SDMA_STATUS2_REG__ID_MASK 0x00000003L +#define SDMA0_SDMA_STATUS2_REG__TH0MCU_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA0_SDMA_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA0_SDMA_ATOMIC_CNTL +#define SDMA0_SDMA_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA0_SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA0_SDMA_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA0_SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA0_SDMA_ATOMIC_PERMS_CNTL +#define SDMA0_SDMA_ATOMIC_PERMS_CNTL__EN_RETRY_ON_ATOMIC__SHIFT 0x0 +#define SDMA0_SDMA_ATOMIC_PERMS_CNTL__PCIE_ATOMIC_SUPPORTED__SHIFT 0x1 +#define SDMA0_SDMA_ATOMIC_PERMS_CNTL__EN_RETRY_ON_ATOMIC_MASK 0x00000001L +#define SDMA0_SDMA_ATOMIC_PERMS_CNTL__PCIE_ATOMIC_SUPPORTED_MASK 0x00000002L +//SDMA0_SDMA_ATOMIC_PREOP_LO +#define SDMA0_SDMA_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_ATOMIC_PREOP_HI +#define SDMA0_SDMA_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_DCC_CNTL +#define SDMA0_SDMA_DCC_CNTL__DCC_FORCE_BYPASS__SHIFT 0x0 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0__SHIFT 0x1 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0__SHIFT 0x2 +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0__SHIFT 0x3 +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0__SHIFT 0x4 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1__SHIFT 0x5 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1__SHIFT 0x6 +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1__SHIFT 0x7 +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1__SHIFT 0x8 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2__SHIFT 0x9 +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2__SHIFT 0xa +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2__SHIFT 0xb +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2__SHIFT 0xc +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3__SHIFT 0xd +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3__SHIFT 0xe +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3__SHIFT 0xf +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3__SHIFT 0x10 +#define SDMA0_SDMA_DCC_CNTL__DCC_FORCE_BYPASS_MASK 0x00000001L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0_MASK 0x00000002L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0_MASK 0x00000004L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0_MASK 0x00000008L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0_MASK 0x00000010L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1_MASK 0x00000020L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1_MASK 0x00000040L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1_MASK 0x00000080L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1_MASK 0x00000100L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2_MASK 0x00000200L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2_MASK 0x00000400L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2_MASK 0x00000800L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2_MASK 0x00001000L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3_MASK 0x00002000L +#define SDMA0_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3_MASK 0x00004000L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3_MASK 0x00008000L +#define SDMA0_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3_MASK 0x00010000L +//SDMA0_SDMA_UTCL1_WARMUPL2_CNTL +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__WARMUP_EN__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__INTERVAL_VA__SHIFT 0x1 +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__GRANU__SHIFT 0x8 +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__STEP_PER_INTERVAL__SHIFT 0x10 +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__WARMUP_EN_MASK 0x00000001L +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__INTERVAL_VA_MASK 0x0000007EL +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__GRANU_MASK 0x00007F00L +#define SDMA0_SDMA_UTCL1_WARMUPL2_CNTL__STEP_PER_INTERVAL_MASK 0x00070000L +//SDMA0_SDMA_UTCL1_CNTL +#define SDMA0_SDMA_UTCL1_CNTL__REDO_DELAY__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT 0x5 +#define SDMA0_SDMA_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 +#define SDMA0_SDMA_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xb +#define SDMA0_SDMA_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xc +#define SDMA0_SDMA_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT 0xd +#define SDMA0_SDMA_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT 0xe +#define SDMA0_SDMA_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xf +#define SDMA0_SDMA_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x13 +#define SDMA0_SDMA_UTCL1_CNTL__REQL2_5CYC_CREDIT__SHIFT 0x19 +#define SDMA0_SDMA_UTCL1_CNTL__REDO_DELAY_MASK 0x0000001FL +#define SDMA0_SDMA_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK 0x000001E0L +#define SDMA0_SDMA_UTCL1_CNTL__RESP_MODE_MASK 0x00000600L +#define SDMA0_SDMA_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00000800L +#define SDMA0_SDMA_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00001000L +#define SDMA0_SDMA_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK 0x00002000L +#define SDMA0_SDMA_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK 0x00004000L +#define SDMA0_SDMA_UTCL1_CNTL__INVACK_DELAY_MASK 0x00078000L +#define SDMA0_SDMA_UTCL1_CNTL__REQL2_CREDIT_MASK 0x01F80000L +#define SDMA0_SDMA_UTCL1_CNTL__REQL2_5CYC_CREDIT_MASK 0x7E000000L +//SDMA0_SDMA_UTCL1_WATERMK +#define SDMA0_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT 0x4 +#define SDMA0_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT 0x6 +#define SDMA0_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa +#define SDMA0_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT 0xc +#define SDMA0_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT 0x10 +#define SDMA0_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT 0x12 +#define SDMA0_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT 0x16 +#define SDMA0_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK 0x0000000FL +#define SDMA0_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK 0x00000030L +#define SDMA0_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK 0x000003C0L +#define SDMA0_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK 0x00000C00L +#define SDMA0_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK 0x0000F000L +#define SDMA0_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK 0x00030000L +#define SDMA0_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK 0x003C0000L +#define SDMA0_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK 0x00C00000L +//SDMA0_SDMA_UTCL1_TIMEOUT +#define SDMA0_SDMA_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_TIMEOUT__XNACK_LIMIT_MASK 0xFFFFFFFFL +//SDMA0_SDMA_UTCL1_PAGE +#define SDMA0_SDMA_UTCL1_PAGE__INVALID_ADDR__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA0_SDMA_UTCL1_PAGE__USE_MTYPE__SHIFT 0x7 +#define SDMA0_SDMA_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa +#define SDMA0_SDMA_UTCL1_PAGE__USE_IO__SHIFT 0xb +#define SDMA0_SDMA_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc +#define SDMA0_SDMA_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe +#define SDMA0_SDMA_UTCL1_PAGE__USE_BC__SHIFT 0x16 +#define SDMA0_SDMA_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 +#define SDMA0_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_VALUE__SHIFT 0x18 +#define SDMA0_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_EN__SHIFT 0x19 +#define SDMA0_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_VALUE__SHIFT 0x1b +#define SDMA0_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_EN__SHIFT 0x1e +#define SDMA0_SDMA_UTCL1_PAGE__INVALID_ADDR_MASK 0x00000001L +#define SDMA0_SDMA_UTCL1_PAGE__REQ_TYPE_MASK 0x0000003EL +#define SDMA0_SDMA_UTCL1_PAGE__USE_MTYPE_MASK 0x00000380L +#define SDMA0_SDMA_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L +#define SDMA0_SDMA_UTCL1_PAGE__USE_IO_MASK 0x00000800L +#define SDMA0_SDMA_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L +#define SDMA0_SDMA_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L +#define SDMA0_SDMA_UTCL1_PAGE__USE_BC_MASK 0x00400000L +#define SDMA0_SDMA_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L +#define SDMA0_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_VALUE_MASK 0x01000000L +#define SDMA0_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_EN_MASK 0x02000000L +#define SDMA0_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_VALUE_MASK 0x18000000L +#define SDMA0_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_EN_MASK 0x40000000L +//SDMA0_SDMA_EXTERNAL_FROZEN +#define SDMA0_SDMA_EXTERNAL_FROZEN__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_EXTERNAL_FROZEN__THRESHOLD_MASK 0x0000FFFFL +//SDMA0_SDMA_FREEZE_TRIGGER +#define SDMA0_SDMA_FREEZE_TRIGGER__CORE_FREEZE__SHIFT 0x0 +#define SDMA0_SDMA_FREEZE_TRIGGER__CORE_FREEZE_MASK 0x00000001L +//SDMA0_SDMA_UTCL1_CACHE_CNTL +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_EN__SHIFT 0x14 +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_VALUE__SHIFT 0x15 +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_IC__SHIFT 0x19 +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_GU__SHIFT 0x1a +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__STRICT_PERMISSION__SHIFT 0x1d +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_EN_MASK 0x00100000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_VALUE_MASK 0x00600000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_IC_MASK 0x02000000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_GU_MASK 0x04000000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define SDMA0_SDMA_UTCL1_CACHE_CNTL__STRICT_PERMISSION_MASK 0x20000000L +//SDMA0_SDMA_UTCL1_RD_STATUS +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_DATA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_EMPTY__SHIFT 0x2 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_FULL__SHIFT 0x7 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_FULL__SHIFT 0x8 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_FULL__SHIFT 0x9 +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT 0xb +#define SDMA0_SDMA_UTCL1_RD_STATUS__L2_INTF_RD_IDLE__SHIFT 0x10 +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT 0x11 +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT 0x12 +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL1_WARMUP_IDLE__SHIFT 0x1a +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_IDLE__SHIFT 0x1b +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_WARMUP_IDLE__SHIFT 0x1c +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE1_IDLE__SHIFT 0x1d +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE0_IDLE__SHIFT 0x1e +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_IDLE__SHIFT 0x1f +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_DATA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_EMPTY_MASK 0x00000004L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_FULL_MASK 0x00000080L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_FULL_MASK 0x00000100L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_FULL_MASK 0x00000200L +#define SDMA0_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK 0x00000800L +#define SDMA0_SDMA_UTCL1_RD_STATUS__L2_INTF_RD_IDLE_MASK 0x00010000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK 0x00020000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK 0x00040000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL1_WARMUP_IDLE_MASK 0x04000000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_IDLE_MASK 0x08000000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_WARMUP_IDLE_MASK 0x10000000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE1_IDLE_MASK 0x20000000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE0_IDLE_MASK 0x40000000L +#define SDMA0_SDMA_UTCL1_RD_STATUS__UTCL2_IDLE_MASK 0x80000000L +//SDMA0_SDMA_UTCL1_WR_STATUS +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_EMPTY__SHIFT 0x1 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_EMPTY__SHIFT 0x2 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_EMPTY__SHIFT 0x3 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT 0x5 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_FULL__SHIFT 0x6 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_FULL__SHIFT 0x7 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_FULL__SHIFT 0x8 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_FULL__SHIFT 0x9 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT 0xb +#define SDMA0_SDMA_UTCL1_WR_STATUS__L2_INTF_WR_IDLE__SHIFT 0x10 +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT 0x11 +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT 0x12 +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_EMPTY_MASK 0x00000002L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_EMPTY_MASK 0x00000004L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_EMPTY_MASK 0x00000008L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK 0x00000020L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_FULL_MASK 0x00000040L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_FULL_MASK 0x00000080L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_FULL_MASK 0x00000100L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_FULL_MASK 0x00000200L +#define SDMA0_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK 0x00000800L +#define SDMA0_SDMA_UTCL1_WR_STATUS__L2_INTF_WR_IDLE_MASK 0x00010000L +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK 0x00020000L +#define SDMA0_SDMA_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK 0x00040000L +//SDMA0_SDMA_UTCL1_INV0 +#define SDMA0_SDMA_UTCL1_INV0__INV_PROC_BUSY__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID__SHIFT 0x7 +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_MODE__SHIFT 0xb +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_HIGH__SHIFT 0xd +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_TAG__SHIFT 0xe +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT 0x12 +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT 0x16 +#define SDMA0_SDMA_UTCL1_INV0__INV_TYPE__SHIFT 0x1a +#define SDMA0_SDMA_UTCL1_INV0__INV_PROC_BUSY_MASK 0x00000001L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK 0x0000007EL +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID_MASK 0x00000780L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_MODE_MASK 0x00001800L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_HIGH_MASK 0x00002000L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_TAG_MASK 0x0003C000L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID_HIGH_MASK 0x003C0000L +#define SDMA0_SDMA_UTCL1_INV0__GPUVM_VMID_LOW_MASK 0x03C00000L +#define SDMA0_SDMA_UTCL1_INV0__INV_TYPE_MASK 0x0C000000L +//SDMA0_SDMA_UTCL1_INV1 +#define SDMA0_SDMA_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_UTCL1_INV2 +#define SDMA0_SDMA_UTCL1_INV2__CPF_VMID__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT 0x10 +#define SDMA0_SDMA_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT 0x11 +#define SDMA0_SDMA_UTCL1_INV2__CPF_VMID_MASK 0x0000FFFFL +#define SDMA0_SDMA_UTCL1_INV2__CPF_FLUSH_TYPE_MASK 0x00010000L +#define SDMA0_SDMA_UTCL1_INV2__CPF_FRAG_SIZE_MASK 0x007E0000L +//SDMA0_SDMA_UTCL1_RD_XNACK0 +#define SDMA0_SDMA_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_UTCL1_RD_XNACK1 +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT 0xd +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x11 +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0x14 +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0x17 +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT 0x1a +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT 0x1b +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x1c +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x00001FFFL +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK 0x0001E000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK 0x000E0000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK 0x00700000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x03800000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK 0x04000000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK 0x08000000L +#define SDMA0_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x10000000L +//SDMA0_SDMA_UTCL1_WR_XNACK0 +#define SDMA0_SDMA_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_UTCL1_WR_XNACK1 +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT 0xd +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x11 +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT 0x14 +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0x17 +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT 0x1a +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT 0x1b +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x1c +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x00001FFFL +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK 0x0001E000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK 0x000E0000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK 0x00700000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x03800000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK 0x04000000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK 0x08000000L +#define SDMA0_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x10000000L +//SDMA0_SDMA_CHICKEN_BITS_2 +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_SEND_POSTCODE_EN__SHIFT 0x4 +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_DEBUG_MODE__SHIFT 0x5 +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_7_6__SHIFT 0x6 +#define SDMA0_SDMA_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT 0x8 +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_14_12__SHIFT 0xc +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_15__SHIFT 0xf +#define SDMA0_SDMA_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 +#define SDMA0_SDMA_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MARGIN__SHIFT 0x14 +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT 0x17 +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT 0x19 +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_30__SHIFT 0x1e +#define SDMA0_SDMA_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT 0x1f +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_CMD_PROC_DELAY_MASK 0x0000000FL +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_SEND_POSTCODE_EN_MASK 0x00000010L +#define SDMA0_SDMA_CHICKEN_BITS_2__MCU_DEBUG_MODE_MASK 0x00000020L +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_7_6_MASK 0x000000C0L +#define SDMA0_SDMA_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK 0x00000F00L +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_14_12_MASK 0x00007000L +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_15_MASK 0x00008000L +#define SDMA0_SDMA_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L +#define SDMA0_SDMA_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MARGIN_MASK 0x00700000L +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK 0x01800000L +#define SDMA0_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK 0x3E000000L +#define SDMA0_SDMA_CHICKEN_BITS_2__RESERVED_30_MASK 0x40000000L +#define SDMA0_SDMA_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK 0x80000000L +//SDMA0_SDMA_STATUS3_REG +#define SDMA0_SDMA_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA0_SDMA_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA0_SDMA_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 +#define SDMA0_SDMA_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 +#define SDMA0_SDMA_STATUS3_REG__GCR_IDLE__SHIFT 0x17 +#define SDMA0_SDMA_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 +#define SDMA0_SDMA_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 +#define SDMA0_SDMA_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a +#define SDMA0_SDMA_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT 0x1e +#define SDMA0_SDMA_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA0_SDMA_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA0_SDMA_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L +#define SDMA0_SDMA_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L +#define SDMA0_SDMA_STATUS3_REG__GCR_IDLE_MASK 0x00800000L +#define SDMA0_SDMA_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L +#define SDMA0_SDMA_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L +#define SDMA0_SDMA_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L +#define SDMA0_SDMA_STATUS3_REG__TMZ_MTYPE_STATUS_MASK 0xC0000000L +//SDMA0_SDMA_GLOBAL_QUANTUM +#define SDMA0_SDMA_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 +#define SDMA0_SDMA_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL +#define SDMA0_SDMA_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_ERROR_LOG +#define SDMA0_SDMA_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA0_SDMA_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA0_SDMA_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA0_SDMA_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA0_SDMA_PUB_DUMMY_REG0 +#define SDMA0_SDMA_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PUB_DUMMY_REG1 +#define SDMA0_SDMA_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PUB_DUMMY_REG2 +#define SDMA0_SDMA_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PUB_DUMMY_REG3 +#define SDMA0_SDMA_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_MCU_COUNTER +#define SDMA0_SDMA_MCU_COUNTER__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_MCU_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_CRD_CNTL +#define SDMA0_SDMA_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 +#define SDMA0_SDMA_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 +#define SDMA0_SDMA_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L +#define SDMA0_SDMA_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L +//SDMA0_SDMA_RLC_CGCG_CTRL +#define SDMA0_SDMA_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT 0x1 +#define SDMA0_SDMA_RLC_CGCG_CTRL__MCU_CGCG_ALLOW__SHIFT 0x4 +#define SDMA0_SDMA_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT 0x10 +#define SDMA0_SDMA_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK 0x00000002L +#define SDMA0_SDMA_RLC_CGCG_CTRL__MCU_CGCG_ALLOW_MASK 0x00000010L +#define SDMA0_SDMA_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK 0xFFFF0000L +//SDMA0_SDMA_GPU_IOV_VIOLATION_LOG +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x07C00000L +//SDMA0_SDMA_AQL_STATUS +#define SDMA0_SDMA_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 +#define SDMA0_SDMA_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 +#define SDMA0_SDMA_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L +#define SDMA0_SDMA_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L +//SDMA0_SDMA_TLBI_GCR_CNTL +#define SDMA0_SDMA_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 +#define SDMA0_SDMA_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 +#define SDMA0_SDMA_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 +#define SDMA0_SDMA_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 +#define SDMA0_SDMA_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL +#define SDMA0_SDMA_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L +#define SDMA0_SDMA_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L +#define SDMA0_SDMA_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L +//SDMA0_SDMA_INT_STATUS +#define SDMA0_SDMA_INT_STATUS__DATA__SHIFT 0x0 +#define SDMA0_SDMA_INT_STATUS__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_GPU_IOV_VIOLATION_LOG2 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA0_SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL +//SDMA0_SDMA_INVALID_ADDR_LO +#define SDMA0_SDMA_INVALID_ADDR_LO__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_INVALID_ADDR_LO__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_INVALID_ADDR_HI +#define SDMA0_SDMA_INVALID_ADDR_HI__VALUE__SHIFT 0x0 +#define SDMA0_SDMA_INVALID_ADDR_HI__VALUE_MASK 0xFFFFFFFFL +//SDMA0_SDMA_INVALID_ADDR_SOURCE +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__ID__SHIFT 0x0 +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VMID__SHIFT 0x6 +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VFID__SHIFT 0xa +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VF__SHIFT 0xf +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__ID_MASK 0x0000003FL +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VMID_MASK 0x000003C0L +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VFID_MASK 0x00007C00L +#define SDMA0_SDMA_INVALID_ADDR_SOURCE__VF_MASK 0x00008000L +//SDMA0_SDMA_CLOCK_GATING_STATUS +#define SDMA0_SDMA_CLOCK_GATING_STATUS__PTR_MGCG_CLK_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__PIO_MGCG_CLK_STATUS__SHIFT 0x9 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MCU_MGCG_CLK_STATUS__SHIFT 0xa +#define SDMA0_SDMA_CLOCK_GATING_STATUS__COPY_ENG_MGCG_CLK_STATUS__SHIFT 0xb +#define SDMA0_SDMA_CLOCK_GATING_STATUS__SERVE_ENG_MGCG_CLK_STATUS__SHIFT 0xc +#define SDMA0_SDMA_CLOCK_GATING_STATUS__CMD_FETCH_MGCG_CLK_STATUS__SHIFT 0xd +#define SDMA0_SDMA_CLOCK_GATING_STATUS__GU_MEMREQ_MGCG_CLK_STATUS__SHIFT 0xe +#define SDMA0_SDMA_CLOCK_GATING_STATUS__INV_MGCG_CLK_STATUS__SHIFT 0xf +#define SDMA0_SDMA_CLOCK_GATING_STATUS__GU_CACHE_MGCG_CLK_STATUS__SHIFT 0x10 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__IC_CACHE_MGCG_CLK_STATUS__SHIFT 0x11 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_MGCG_CLK_STATUS__SHIFT 0x12 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESE_MGCG_CLK_STATUS__SHIFT 0x13 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__FE_ENG_MGCG_CLK_STATUS__SHIFT 0x14 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESEFE_MGCG_CLK_STATUS__SHIFT 0x15 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_FE_WARMUP_MGCG_CLK_STATUS__SHIFT 0x16 +#define SDMA0_SDMA_CLOCK_GATING_STATUS__PTR_MGCG_CLK_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__PIO_MGCG_CLK_STATUS_MASK 0x00000200L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MCU_MGCG_CLK_STATUS_MASK 0x00000400L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__COPY_ENG_MGCG_CLK_STATUS_MASK 0x00000800L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__SERVE_ENG_MGCG_CLK_STATUS_MASK 0x00001000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__CMD_FETCH_MGCG_CLK_STATUS_MASK 0x00002000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__GU_MEMREQ_MGCG_CLK_STATUS_MASK 0x00004000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__INV_MGCG_CLK_STATUS_MASK 0x00008000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__GU_CACHE_MGCG_CLK_STATUS_MASK 0x00010000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__IC_CACHE_MGCG_CLK_STATUS_MASK 0x00020000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_MGCG_CLK_STATUS_MASK 0x00040000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESE_MGCG_CLK_STATUS_MASK 0x00080000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__FE_ENG_MGCG_CLK_STATUS_MASK 0x00100000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESEFE_MGCG_CLK_STATUS_MASK 0x00200000L +#define SDMA0_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_FE_WARMUP_MGCG_CLK_STATUS_MASK 0x00400000L +//SDMA0_SDMA_STATUS4_REG +#define SDMA0_SDMA_STATUS4_REG__IDLE__SHIFT 0x0 +#define SDMA0_SDMA_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 +#define SDMA0_SDMA_STATUS4_REG__RESERVED__SHIFT 0x3 +#define SDMA0_SDMA_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 +#define SDMA0_SDMA_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 +#define SDMA0_SDMA_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 +#define SDMA0_SDMA_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 +#define SDMA0_SDMA_STATUS4_REG__CMDFETCH_OUTSTANDING__SHIFT 0xa +#define SDMA0_SDMA_STATUS4_REG__RESERVED_11__SHIFT 0xb +#define SDMA0_SDMA_STATUS4_REG__RESERVED_13_12__SHIFT 0xc +#define SDMA0_SDMA_STATUS4_REG__RESERVED_15_14__SHIFT 0xe +#define SDMA0_SDMA_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 +#define SDMA0_SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 +#define SDMA0_SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT 0x16 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT 0x17 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT 0x18 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT 0x19 +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT 0x1a +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT 0x1b +#define SDMA0_SDMA_STATUS4_REG__IDLE_MASK 0x00000001L +#define SDMA0_SDMA_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L +#define SDMA0_SDMA_STATUS4_REG__RESERVED_MASK 0x00000008L +#define SDMA0_SDMA_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L +#define SDMA0_SDMA_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L +#define SDMA0_SDMA_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L +#define SDMA0_SDMA_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L +#define SDMA0_SDMA_STATUS4_REG__CMDFETCH_OUTSTANDING_MASK 0x00000400L +#define SDMA0_SDMA_STATUS4_REG__RESERVED_11_MASK 0x00000800L +#define SDMA0_SDMA_STATUS4_REG__RESERVED_13_12_MASK 0x00003000L +#define SDMA0_SDMA_STATUS4_REG__RESERVED_15_14_MASK 0x0000C000L +#define SDMA0_SDMA_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L +#define SDMA0_SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L +#define SDMA0_SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK 0x00400000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK 0x00800000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK 0x01000000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK 0x02000000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK 0x04000000L +#define SDMA0_SDMA_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK 0x08000000L +//SDMA0_SDMA_SCRATCH_RAM_DATA +#define SDMA0_SDMA_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define SDMA0_SDMA_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_SCRATCH_RAM_ADDR +#define SDMA0_SDMA_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//SDMA0_SDMA_TIMESTAMP_CNTL +#define SDMA0_SDMA_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 +#define SDMA0_SDMA_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L +//SDMA0_SDMA_STATUS5_REG +#define SDMA0_SDMA_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 +#define SDMA0_SDMA_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 +#define SDMA0_SDMA_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 +#define SDMA0_SDMA_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 +#define SDMA0_SDMA_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 +#define SDMA0_SDMA_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 +#define SDMA0_SDMA_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 +#define SDMA0_SDMA_STATUS5_REG__QUEUE8_RB_ENABLE_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_STATUS5_REG__QUEUE9_RB_ENABLE_STATUS__SHIFT 0x9 +#define SDMA0_SDMA_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x10 +#define SDMA0_SDMA_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x11 +#define SDMA0_SDMA_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x12 +#define SDMA0_SDMA_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x13 +#define SDMA0_SDMA_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x14 +#define SDMA0_SDMA_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x15 +#define SDMA0_SDMA_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x16 +#define SDMA0_SDMA_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x17 +#define SDMA0_SDMA_STATUS5_REG__QUEUE8_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x18 +#define SDMA0_SDMA_STATUS5_REG__QUEUE9_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x19 +#define SDMA0_SDMA_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L +#define SDMA0_SDMA_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L +#define SDMA0_SDMA_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L +#define SDMA0_SDMA_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L +#define SDMA0_SDMA_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L +#define SDMA0_SDMA_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L +#define SDMA0_SDMA_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L +#define SDMA0_SDMA_STATUS5_REG__QUEUE8_RB_ENABLE_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_STATUS5_REG__QUEUE9_RB_ENABLE_STATUS_MASK 0x00000200L +#define SDMA0_SDMA_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00010000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00020000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00040000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00080000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00100000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00200000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00400000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00800000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE8_WPTR_POLL_PAGE_EXCEPTION_MASK 0x01000000L +#define SDMA0_SDMA_STATUS5_REG__QUEUE9_WPTR_POLL_PAGE_EXCEPTION_MASK 0x02000000L +//SDMA0_SDMA_QUEUE_RESET_REQ +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE8_RESET__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE9_RESET__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE8_RESET_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE_RESET_REQ__QUEUE9_RESET_MASK 0x00000200L +//SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE0_DEQUEUE_REQ__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE1_DEQUEUE_REQ__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE2_DEQUEUE_REQ__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE3_DEQUEUE_REQ__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE4_DEQUEUE_REQ__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE5_DEQUEUE_REQ__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE6_DEQUEUE_REQ__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE7_DEQUEUE_REQ__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE8_DEQUEUE_REQ__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE9_DEQUEUE_REQ__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE0_DEQUEUE_REQ_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE1_DEQUEUE_REQ_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE2_DEQUEUE_REQ_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE3_DEQUEUE_REQ_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE4_DEQUEUE_REQ_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE5_DEQUEUE_REQ_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE6_DEQUEUE_REQ_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE7_DEQUEUE_REQ_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE8_DEQUEUE_REQ_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE9_DEQUEUE_REQ_MASK 0x00000200L +//SDMA0_SDMA_STATUS6_REG +#define SDMA0_SDMA_STATUS6_REG__ID__SHIFT 0x0 +#define SDMA0_SDMA_STATUS6_REG__TH1MCU_INSTR_PTR__SHIFT 0x2 +#define SDMA0_SDMA_STATUS6_REG__TH1_EXCEPTION__SHIFT 0x10 +#define SDMA0_SDMA_STATUS6_REG__ID_MASK 0x00000003L +#define SDMA0_SDMA_STATUS6_REG__TH1MCU_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA0_SDMA_STATUS6_REG__TH1_EXCEPTION_MASK 0xFFFF0000L +//SDMA0_SDMA_STATUS7_REG +#define SDMA0_SDMA_STATUS7_REG__BLT_REQ_DROP__SHIFT 0x0 +#define SDMA0_SDMA_STATUS7_REG__BLT_REQ_DROP_MASK 0x00000001L +//SDMA0_SDMA_STATUS8_REG +#define SDMA0_SDMA_STATUS8_REG__LD_CTXSW_COND__SHIFT 0x0 +#define SDMA0_SDMA_STATUS8_REG__LD_CTXSW_COND_MASK 0xFFFFFFFFL +//SDMA0_SDMA_CE_CTRL +#define SDMA0_SDMA_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define SDMA0_SDMA_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define SDMA0_SDMA_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define SDMA0_SDMA_CE_CTRL__RESERVED__SHIFT 0x9 +#define SDMA0_SDMA_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define SDMA0_SDMA_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define SDMA0_SDMA_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define SDMA0_SDMA_CE_CTRL__RESERVED_MASK 0xFFFFFE00L +//SDMA0_SDMA_RAS_STATUS +#define SDMA0_SDMA_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 +#define SDMA0_SDMA_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 +#define SDMA0_SDMA_RAS_STATUS__MCU_DATA_ECC__SHIFT 0x2 +#define SDMA0_SDMA_RAS_STATUS__WPTR_POLL_ECC__SHIFT 0x3 +#define SDMA0_SDMA_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 +#define SDMA0_SDMA_RAS_STATUS__INSTR_FETCH_ECC__SHIFT 0x5 +#define SDMA0_SDMA_RAS_STATUS__ATOMIC_ECC__SHIFT 0x6 +#define SDMA0_SDMA_RAS_STATUS__FRONTEND_ECC__SHIFT 0x7 +#define SDMA0_SDMA_RAS_STATUS__SRAM_ECC__SHIFT 0x10 +#define SDMA0_SDMA_RAS_STATUS__BUS_PARITY__SHIFT 0x12 +#define SDMA0_SDMA_RAS_STATUS__VMID__SHIFT 0x14 +#define SDMA0_SDMA_RAS_STATUS__VFID__SHIFT 0x18 +#define SDMA0_SDMA_RAS_STATUS__VF__SHIFT 0x1d +#define SDMA0_SDMA_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L +#define SDMA0_SDMA_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L +#define SDMA0_SDMA_RAS_STATUS__MCU_DATA_ECC_MASK 0x00000004L +#define SDMA0_SDMA_RAS_STATUS__WPTR_POLL_ECC_MASK 0x00000008L +#define SDMA0_SDMA_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L +#define SDMA0_SDMA_RAS_STATUS__INSTR_FETCH_ECC_MASK 0x00000020L +#define SDMA0_SDMA_RAS_STATUS__ATOMIC_ECC_MASK 0x00000040L +#define SDMA0_SDMA_RAS_STATUS__FRONTEND_ECC_MASK 0x00000080L +#define SDMA0_SDMA_RAS_STATUS__SRAM_ECC_MASK 0x00010000L +#define SDMA0_SDMA_RAS_STATUS__BUS_PARITY_MASK 0x00040000L +#define SDMA0_SDMA_RAS_STATUS__VMID_MASK 0x00F00000L +#define SDMA0_SDMA_RAS_STATUS__VFID_MASK 0x1F000000L +#define SDMA0_SDMA_RAS_STATUS__VF_MASK 0x20000000L +//SDMA0_SDMA_POISON_INFO +#define SDMA0_SDMA_POISON_INFO__VMID__SHIFT 0x0 +#define SDMA0_SDMA_POISON_INFO__VFID__SHIFT 0x4 +#define SDMA0_SDMA_POISON_INFO__VF__SHIFT 0x9 +#define SDMA0_SDMA_POISON_INFO__VMID_MASK 0x0000000FL +#define SDMA0_SDMA_POISON_INFO__VFID_MASK 0x000001F0L +#define SDMA0_SDMA_POISON_INFO__VF_MASK 0x00000200L +//SDMA0_SDMA_MEMHUB_CNTL +#define SDMA0_SDMA_MEMHUB_CNTL__SPECULATIVE_DATA_READ__SHIFT 0x0 +#define SDMA0_SDMA_MEMHUB_CNTL__SPECULATIVE_DATA_READ_MASK 0x00000003L +//SDMA0_SDMA_QUEUE0_RB_CNTL +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE0_RB_BASE +#define SDMA0_SDMA_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_BASE_HI +#define SDMA0_SDMA_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE0_RB_RPTR +#define SDMA0_SDMA_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_WPTR +#define SDMA0_SDMA_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_IB_CNTL +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE0_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE0_IB_RPTR +#define SDMA0_SDMA_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE0_IB_OFFSET +#define SDMA0_SDMA_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE0_IB_BASE_LO +#define SDMA0_SDMA_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_IB_BASE_HI +#define SDMA0_SDMA_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_IB_SIZE +#define SDMA0_SDMA_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE0_DOORBELL +#define SDMA0_SDMA_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE0_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE0_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE0_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE0_PREEMPT +#define SDMA0_SDMA_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE0_DUMMY_REG +#define SDMA0_SDMA_QUEUE0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE0_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE0_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE0_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE0_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_MQD_CONTROL +#define SDMA0_SDMA_QUEUE0_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE0_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE0_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE0_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE0_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE0_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE0_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_CNTL +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE1_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE1_RB_BASE +#define SDMA0_SDMA_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_BASE_HI +#define SDMA0_SDMA_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE1_RB_RPTR +#define SDMA0_SDMA_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_WPTR +#define SDMA0_SDMA_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_IB_CNTL +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE1_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE1_IB_RPTR +#define SDMA0_SDMA_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE1_IB_OFFSET +#define SDMA0_SDMA_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE1_IB_BASE_LO +#define SDMA0_SDMA_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_IB_BASE_HI +#define SDMA0_SDMA_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_IB_SIZE +#define SDMA0_SDMA_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE1_DOORBELL +#define SDMA0_SDMA_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE1_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE1_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE1_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE1_PREEMPT +#define SDMA0_SDMA_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE1_DUMMY_REG +#define SDMA0_SDMA_QUEUE1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE1_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE1_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE1_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE1_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE1_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_MQD_CONTROL +#define SDMA0_SDMA_QUEUE1_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE1_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE1_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE1_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE1_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE1_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE1_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_CNTL +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE2_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE2_RB_BASE +#define SDMA0_SDMA_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_BASE_HI +#define SDMA0_SDMA_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE2_RB_RPTR +#define SDMA0_SDMA_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_WPTR +#define SDMA0_SDMA_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_IB_CNTL +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE2_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE2_IB_RPTR +#define SDMA0_SDMA_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE2_IB_OFFSET +#define SDMA0_SDMA_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE2_IB_BASE_LO +#define SDMA0_SDMA_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_IB_BASE_HI +#define SDMA0_SDMA_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_IB_SIZE +#define SDMA0_SDMA_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE2_DOORBELL +#define SDMA0_SDMA_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE2_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE2_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE2_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE2_PREEMPT +#define SDMA0_SDMA_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE2_DUMMY_REG +#define SDMA0_SDMA_QUEUE2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE2_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE2_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE2_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE2_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE2_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_MQD_CONTROL +#define SDMA0_SDMA_QUEUE2_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE2_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE2_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE2_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE2_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE2_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE2_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_CNTL +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE3_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE3_RB_BASE +#define SDMA0_SDMA_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_BASE_HI +#define SDMA0_SDMA_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE3_RB_RPTR +#define SDMA0_SDMA_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_WPTR +#define SDMA0_SDMA_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_IB_CNTL +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE3_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE3_IB_RPTR +#define SDMA0_SDMA_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE3_IB_OFFSET +#define SDMA0_SDMA_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE3_IB_BASE_LO +#define SDMA0_SDMA_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_IB_BASE_HI +#define SDMA0_SDMA_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_IB_SIZE +#define SDMA0_SDMA_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE3_DOORBELL +#define SDMA0_SDMA_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE3_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE3_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE3_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE3_PREEMPT +#define SDMA0_SDMA_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE3_DUMMY_REG +#define SDMA0_SDMA_QUEUE3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE3_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE3_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE3_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE3_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE3_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_MQD_CONTROL +#define SDMA0_SDMA_QUEUE3_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE3_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE3_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE3_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE3_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE3_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE3_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_CNTL +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE4_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE4_RB_BASE +#define SDMA0_SDMA_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_BASE_HI +#define SDMA0_SDMA_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE4_RB_RPTR +#define SDMA0_SDMA_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_WPTR +#define SDMA0_SDMA_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_IB_CNTL +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE4_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE4_IB_RPTR +#define SDMA0_SDMA_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE4_IB_OFFSET +#define SDMA0_SDMA_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE4_IB_BASE_LO +#define SDMA0_SDMA_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_IB_BASE_HI +#define SDMA0_SDMA_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_IB_SIZE +#define SDMA0_SDMA_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE4_DOORBELL +#define SDMA0_SDMA_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE4_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE4_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE4_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE4_PREEMPT +#define SDMA0_SDMA_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE4_DUMMY_REG +#define SDMA0_SDMA_QUEUE4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE4_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE4_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE4_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE4_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE4_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_MQD_CONTROL +#define SDMA0_SDMA_QUEUE4_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE4_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE4_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE4_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE4_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE4_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE4_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_CNTL +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE5_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE5_RB_BASE +#define SDMA0_SDMA_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_BASE_HI +#define SDMA0_SDMA_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE5_RB_RPTR +#define SDMA0_SDMA_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_WPTR +#define SDMA0_SDMA_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_IB_CNTL +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE5_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE5_IB_RPTR +#define SDMA0_SDMA_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE5_IB_OFFSET +#define SDMA0_SDMA_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE5_IB_BASE_LO +#define SDMA0_SDMA_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_IB_BASE_HI +#define SDMA0_SDMA_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_IB_SIZE +#define SDMA0_SDMA_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE5_DOORBELL +#define SDMA0_SDMA_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE5_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE5_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE5_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE5_PREEMPT +#define SDMA0_SDMA_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE5_DUMMY_REG +#define SDMA0_SDMA_QUEUE5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE5_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE5_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE5_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE5_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE5_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_MQD_CONTROL +#define SDMA0_SDMA_QUEUE5_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE5_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE5_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE5_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE5_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE5_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE5_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_CNTL +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE6_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE6_RB_BASE +#define SDMA0_SDMA_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_BASE_HI +#define SDMA0_SDMA_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE6_RB_RPTR +#define SDMA0_SDMA_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_WPTR +#define SDMA0_SDMA_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_IB_CNTL +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE6_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE6_IB_RPTR +#define SDMA0_SDMA_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE6_IB_OFFSET +#define SDMA0_SDMA_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE6_IB_BASE_LO +#define SDMA0_SDMA_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_IB_BASE_HI +#define SDMA0_SDMA_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_IB_SIZE +#define SDMA0_SDMA_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE6_DOORBELL +#define SDMA0_SDMA_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE6_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE6_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE6_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE6_PREEMPT +#define SDMA0_SDMA_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE6_DUMMY_REG +#define SDMA0_SDMA_QUEUE6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE6_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE6_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE6_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE6_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE6_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_MQD_CONTROL +#define SDMA0_SDMA_QUEUE6_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE6_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE6_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE6_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE6_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE6_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE6_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_CNTL +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE7_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE7_RB_BASE +#define SDMA0_SDMA_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_BASE_HI +#define SDMA0_SDMA_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE7_RB_RPTR +#define SDMA0_SDMA_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_WPTR +#define SDMA0_SDMA_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_IB_CNTL +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE7_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE7_IB_RPTR +#define SDMA0_SDMA_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE7_IB_OFFSET +#define SDMA0_SDMA_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE7_IB_BASE_LO +#define SDMA0_SDMA_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_IB_BASE_HI +#define SDMA0_SDMA_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_IB_SIZE +#define SDMA0_SDMA_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE7_DOORBELL +#define SDMA0_SDMA_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE7_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE7_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE7_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE7_PREEMPT +#define SDMA0_SDMA_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE7_DUMMY_REG +#define SDMA0_SDMA_QUEUE7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE7_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE7_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE7_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE7_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE7_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_MQD_CONTROL +#define SDMA0_SDMA_QUEUE7_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE7_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE7_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE7_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE7_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE7_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE7_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_CNTL +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE8_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE8_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE8_RB_BASE +#define SDMA0_SDMA_QUEUE8_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_BASE_HI +#define SDMA0_SDMA_QUEUE8_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE8_RB_RPTR +#define SDMA0_SDMA_QUEUE8_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE8_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_WPTR +#define SDMA0_SDMA_QUEUE8_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE8_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_IB_CNTL +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE8_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE8_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE8_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE8_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE8_IB_RPTR +#define SDMA0_SDMA_QUEUE8_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE8_IB_OFFSET +#define SDMA0_SDMA_QUEUE8_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE8_IB_BASE_LO +#define SDMA0_SDMA_QUEUE8_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_IB_BASE_HI +#define SDMA0_SDMA_QUEUE8_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_IB_SIZE +#define SDMA0_SDMA_QUEUE8_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE8_DOORBELL +#define SDMA0_SDMA_QUEUE8_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE8_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE8_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE8_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE8_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE8_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE8_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE8_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE8_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE8_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE8_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE8_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE8_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE8_PREEMPT +#define SDMA0_SDMA_QUEUE8_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE8_DUMMY_REG +#define SDMA0_SDMA_QUEUE8_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE8_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE8_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE8_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE8_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE8_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE8_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE8_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE8_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_MQD_CONTROL +#define SDMA0_SDMA_QUEUE8_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE8_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE8_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE8_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE8_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE8_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE8_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_CNTL +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE9_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA0_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA0_SDMA_QUEUE9_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA0_SDMA_QUEUE9_RB_BASE +#define SDMA0_SDMA_QUEUE9_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_BASE_HI +#define SDMA0_SDMA_QUEUE9_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA0_SDMA_QUEUE9_RB_RPTR +#define SDMA0_SDMA_QUEUE9_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_RPTR_HI +#define SDMA0_SDMA_QUEUE9_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_WPTR +#define SDMA0_SDMA_QUEUE9_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_WPTR_HI +#define SDMA0_SDMA_QUEUE9_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_LO +#define SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_HI +#define SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_IB_CNTL +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE9_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE9_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE9_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA0_SDMA_QUEUE9_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA0_SDMA_QUEUE9_IB_RPTR +#define SDMA0_SDMA_QUEUE9_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE9_IB_OFFSET +#define SDMA0_SDMA_QUEUE9_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA0_SDMA_QUEUE9_IB_BASE_LO +#define SDMA0_SDMA_QUEUE9_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_IB_BASE_HI +#define SDMA0_SDMA_QUEUE9_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_IB_SIZE +#define SDMA0_SDMA_QUEUE9_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA0_SDMA_QUEUE9_DOORBELL +#define SDMA0_SDMA_QUEUE9_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_QUEUE9_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA0_SDMA_QUEUE9_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_QUEUE9_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA0_SDMA_QUEUE9_DOORBELL_LOG +#define SDMA0_SDMA_QUEUE9_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_DOORBELL_OFFSET +#define SDMA0_SDMA_QUEUE9_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA0_SDMA_QUEUE9_CSA_ADDR_LO +#define SDMA0_SDMA_QUEUE9_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_CSA_ADDR_HI +#define SDMA0_SDMA_QUEUE9_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA0_SDMA_QUEUE9_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA0_SDMA_QUEUE9_IB_SUB_REMAIN +#define SDMA0_SDMA_QUEUE9_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA0_SDMA_QUEUE9_PREEMPT +#define SDMA0_SDMA_QUEUE9_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA0_SDMA_QUEUE9_DUMMY_REG +#define SDMA0_SDMA_QUEUE9_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO +#define SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI +#define SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_RB_AQL_CNTL +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA0_SDMA_QUEUE9_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA0_SDMA_QUEUE9_MINOR_PTR_UPDATE +#define SDMA0_SDMA_QUEUE9_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA0_SDMA_QUEUE9_MIDCMD_CNTL +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA0_SDMA_QUEUE9_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA1 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA2 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA3 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA4 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA5 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA6 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA7 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA8 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA9 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MIDCMD_DATA10 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_UTILIZATION_LO +#define SDMA0_SDMA_QUEUE9_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_UTILIZATION_HI +#define SDMA0_SDMA_QUEUE9_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_WAIT_UNSATISFIED_THD +#define SDMA0_SDMA_QUEUE9_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_LO +#define SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_HI +#define SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_MQD_CONTROL +#define SDMA0_SDMA_QUEUE9_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA0_SDMA_QUEUE9_CONTEXT_STATUS +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA0_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA0_SDMA_QUEUE9_DUMMY_REG1 +#define SDMA0_SDMA_QUEUE9_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA0_SDMA_QUEUE9_DUMMY_REG2 +#define SDMA0_SDMA_QUEUE9_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA0_SDMA_QUEUE9_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmahypdec +//SDMA0_SDMA_VM_CTX_LO +#define SDMA0_SDMA_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA0_SDMA_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA0_SDMA_VM_CTX_HI +#define SDMA0_SDMA_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA0_SDMA_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA0_SDMA_ACTIVE_FCN_ID +#define SDMA0_SDMA_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA0_SDMA_ACTIVE_FCN_ID__VF__SHIFT 0x7 +#define SDMA0_SDMA_ACTIVE_FCN_ID__RESERVED__SHIFT 0x8 +#define SDMA0_SDMA_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL +#define SDMA0_SDMA_ACTIVE_FCN_ID__VF_MASK 0x00000080L +#define SDMA0_SDMA_ACTIVE_FCN_ID__RESERVED_MASK 0xFFFFFF00L +//SDMA0_SDMA_VM_CTX_CNTL +#define SDMA0_SDMA_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA0_SDMA_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA0_SDMA_VM_CTX_CNTL__MEM_PHY__SHIFT 0x8 +#define SDMA0_SDMA_VM_CTX_CNTL__MEM_MTYPE__SHIFT 0xa +#define SDMA0_SDMA_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE__SHIFT 0x10 +#define SDMA0_SDMA_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA0_SDMA_VM_CTX_CNTL__VMID_MASK 0x000000F0L +#define SDMA0_SDMA_VM_CTX_CNTL__MEM_PHY_MASK 0x00000300L +#define SDMA0_SDMA_VM_CTX_CNTL__MEM_MTYPE_MASK 0x00000C00L +#define SDMA0_SDMA_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE_MASK 0x00010000L +//SDMA0_SDMA_VIRT_RESET_REQ +#define SDMA0_SDMA_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA0_SDMA_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA0_SDMA_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL +#define SDMA0_SDMA_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA0_SDMA_CONTEXT_REG_TYPE0 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_CNTL__SHIFT 0x0 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE__SHIFT 0x1 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_HI__SHIFT 0x2 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR__SHIFT 0x3 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_HI__SHIFT 0x4 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR__SHIFT 0x5 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_HI__SHIFT 0x6 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_LO__SHIFT 0x7 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_CNTL__SHIFT 0x9 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_RPTR__SHIFT 0xa +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_OFFSET__SHIFT 0xb +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_LO__SHIFT 0xc +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_HI__SHIFT 0xd +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SIZE__SHIFT 0xe +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL__SHIFT 0xf +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_LOG__SHIFT 0x10 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_OFFSET__SHIFT 0x11 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_LO__SHIFT 0x12 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_HI__SHIFT 0x13 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_SCHEDULE_CNTL__SHIFT 0x14 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SUB_REMAIN__SHIFT 0x15 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_PREEMPT__SHIFT 0x16 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DUMMY_REG__SHIFT 0x17 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__SHIFT 0x18 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__SHIFT 0x19 +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_AQL_CNTL__SHIFT 0x1a +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MINOR_PTR_UPDATE__SHIFT 0x1b +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SHIFT 0x1e +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MIDCMD_CNTL__SHIFT 0x1f +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_CNTL_MASK 0x00000001L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_MASK 0x00000002L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_HI_MASK 0x00000004L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_MASK 0x00000008L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_HI_MASK 0x00000010L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_MASK 0x00000020L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_HI_MASK 0x00000040L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_LO_MASK 0x00000080L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_CNTL_MASK 0x00000200L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_RPTR_MASK 0x00000400L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_OFFSET_MASK 0x00000800L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_LO_MASK 0x00001000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_HI_MASK 0x00002000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SIZE_MASK 0x00004000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_MASK 0x00008000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_LOG_MASK 0x00010000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_OFFSET_MASK 0x00020000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_LO_MASK 0x00040000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_HI_MASK 0x00080000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_SCHEDULE_CNTL_MASK 0x00100000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SUB_REMAIN_MASK 0x00200000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_PREEMPT_MASK 0x00400000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DUMMY_REG_MASK 0x00800000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO_MASK 0x01000000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI_MASK 0x02000000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_AQL_CNTL_MASK 0x04000000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MINOR_PTR_UPDATE_MASK 0x08000000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CONTEXT_SWITCH_STATUS_MASK 0x40000000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MIDCMD_CNTL_MASK 0x80000000L +//SDMA0_SDMA_CONTEXT_REG_TYPE1 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA9__SHIFT 0x9 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA10__SHIFT 0xa +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_LO__SHIFT 0xb +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_HI__SHIFT 0xc +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_WAIT_UNSATISFIED_THD__SHIFT 0xd +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_LO__SHIFT 0xe +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_HI__SHIFT 0xf +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_CONTROL__SHIFT 0x10 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG1__SHIFT 0x12 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG2__SHIFT 0x13 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x14 +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA9_MASK 0x00000200L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA10_MASK 0x00000400L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_LO_MASK 0x00000800L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_HI_MASK 0x00001000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_WAIT_UNSATISFIED_THD_MASK 0x00002000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_LO_MASK 0x00004000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_HI_MASK 0x00008000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_CONTROL_MASK 0x00010000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG1_MASK 0x00040000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG2_MASK 0x00080000L +#define SDMA0_SDMA_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFF00000L +//SDMA0_SDMA_CONTEXT_REG_TYPE2 +#define SDMA0_SDMA_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x0 +#define SDMA0_SDMA_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PUB_REG_TYPE0 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_DEC_START__SHIFT 0x0 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_MCU_MISC_CNTL__SHIFT 0x1 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_UCODE_REV__SHIFT 0x3 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_LO__SHIFT 0x5 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_HI__SHIFT 0x6 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_POWER_CNTL__SHIFT 0xc +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CNTL__SHIFT 0xd +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CHICKEN_BITS__SHIFT 0xe +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CACHE_CNTL__SHIFT 0xf +#define SDMA0_SDMA_PUB_REG_TYPE0__RESERVED__SHIFT 0x15 +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_DEC_START_MASK 0x00000001L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_MCU_MISC_CNTL_MASK 0x00000002L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_UCODE_REV_MASK 0x00000008L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_LO_MASK 0x00000020L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_HI_MASK 0x00000040L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_POWER_CNTL_MASK 0x00001000L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CNTL_MASK 0x00002000L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CHICKEN_BITS_MASK 0x00004000L +#define SDMA0_SDMA_PUB_REG_TYPE0__SDMA_CACHE_CNTL_MASK 0x00008000L +#define SDMA0_SDMA_PUB_REG_TYPE0__RESERVED_MASK 0xFFE00000L +//SDMA0_SDMA_PUB_REG_TYPE1 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH__SHIFT 0x0 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI__SHIFT 0x1 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH__SHIFT 0x2 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROGRAM__SHIFT 0x3 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG__SHIFT 0x4 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG__SHIFT 0x5 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_CNTL1__SHIFT 0x6 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG__SHIFT 0x7 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_FREEZE__SHIFT 0x8 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM0__SHIFT 0x9 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM1__SHIFT 0xa +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_WATCHDOG_CNTL__SHIFT 0xb +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS0__SHIFT 0xc +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS1__SHIFT 0xd +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ID__SHIFT 0xe +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_VERSION__SHIFT 0xf +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG__SHIFT 0x10 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL__SHIFT 0x11 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PERMS_CNTL__SHIFT 0x12 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO__SHIFT 0x13 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI__SHIFT 0x14 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_DCC_CNTL__SHIFT 0x15 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WARMUPL2_CNTL__SHIFT 0x16 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL__SHIFT 0x17 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK__SHIFT 0x18 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_TIMEOUT__SHIFT 0x19 +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_PAGE__SHIFT 0x1a +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_EXTERNAL_FROZEN__SHIFT 0x1b +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_TRIGGER__SHIFT 0x1c +#define SDMA0_SDMA_PUB_REG_TYPE1__RESERVED__SHIFT 0x1d +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_MASK 0x00000001L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI_MASK 0x00000002L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH_MASK 0x00000004L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROGRAM_MASK 0x00000008L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG_MASK 0x00000010L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG_MASK 0x00000020L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_CNTL1_MASK 0x00000040L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG_MASK 0x00000080L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_MASK 0x00000100L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM0_MASK 0x00000200L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM1_MASK 0x00000400L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_WATCHDOG_CNTL_MASK 0x00000800L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS0_MASK 0x00001000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS1_MASK 0x00002000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ID_MASK 0x00004000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_VERSION_MASK 0x00008000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG_MASK 0x00010000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL_MASK 0x00020000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PERMS_CNTL_MASK 0x00040000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO_MASK 0x00080000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI_MASK 0x00100000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_DCC_CNTL_MASK 0x00200000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WARMUPL2_CNTL_MASK 0x00400000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL_MASK 0x00800000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK_MASK 0x01000000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_TIMEOUT_MASK 0x02000000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_PAGE_MASK 0x04000000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_EXTERNAL_FROZEN_MASK 0x08000000L +#define SDMA0_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_TRIGGER_MASK 0x10000000L +#define SDMA0_SDMA_PUB_REG_TYPE1__RESERVED_MASK 0xE0000000L +//SDMA0_SDMA_PUB_REG_TYPE2 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_CACHE_CNTL__SHIFT 0x0 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_STATUS__SHIFT 0x1 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_STATUS__SHIFT 0x2 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0__SHIFT 0x3 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1__SHIFT 0x4 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2__SHIFT 0x5 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0__SHIFT 0x6 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1__SHIFT 0x7 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0__SHIFT 0x8 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1__SHIFT 0x9 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2__SHIFT 0xa +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG__SHIFT 0xb +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_GLOBAL_QUANTUM__SHIFT 0xc +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG__SHIFT 0xd +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0__SHIFT 0xe +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1__SHIFT 0xf +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2__SHIFT 0x10 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3__SHIFT 0x11 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_MCU_COUNTER__SHIFT 0x12 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL__SHIFT 0x13 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_RLC_CGCG_CTRL__SHIFT 0x14 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG__SHIFT 0x15 +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_AQL_STATUS__SHIFT 0x17 +#define SDMA0_SDMA_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_CACHE_CNTL_MASK 0x00000001L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_STATUS_MASK 0x00000002L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_STATUS_MASK 0x00000004L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0_MASK 0x00000008L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1_MASK 0x00000010L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2_MASK 0x00000020L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0_MASK 0x00000040L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1_MASK 0x00000080L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0_MASK 0x00000100L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1_MASK 0x00000200L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2_MASK 0x00000400L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG_MASK 0x00000800L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_GLOBAL_QUANTUM_MASK 0x00001000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG_MASK 0x00002000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0_MASK 0x00004000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1_MASK 0x00008000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2_MASK 0x00010000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3_MASK 0x00020000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_MCU_COUNTER_MASK 0x00040000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL_MASK 0x00080000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_RLC_CGCG_CTRL_MASK 0x00100000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG_MASK 0x00200000L +#define SDMA0_SDMA_PUB_REG_TYPE2__SDMA_AQL_STATUS_MASK 0x00800000L +#define SDMA0_SDMA_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA0_SDMA_PUB_REG_TYPE3 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_TLBI_GCR_CNTL__SHIFT 0x0 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INT_STATUS__SHIFT 0x1 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_LO__SHIFT 0x3 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_HI__SHIFT 0x4 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_SRC__SHIFT 0x5 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_CLOCK_GATING_STATUS__SHIFT 0x6 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG__SHIFT 0x7 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA__SHIFT 0x8 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR__SHIFT 0x9 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_TIMESTAMP_CNTL__SHIFT 0xa +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS5_REG__SHIFT 0xb +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_RESET_REQ__SHIFT 0xc +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_DEQUEUE_REQUEST__SHIFT 0xd +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS6_REG__SHIFT 0xe +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL__SHIFT 0xf +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS__SHIFT 0x10 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_POISON_INFO__SHIFT 0x11 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_MEMHUB_CNTL__SHIFT 0x12 +#define SDMA0_SDMA_PUB_REG_TYPE3__RESERVED__SHIFT 0x13 +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_TLBI_GCR_CNTL_MASK 0x00000001L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INT_STATUS_MASK 0x00000002L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_LO_MASK 0x00000008L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_HI_MASK 0x00000010L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_SRC_MASK 0x00000020L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_CLOCK_GATING_STATUS_MASK 0x00000040L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG_MASK 0x00000080L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA_MASK 0x00000100L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR_MASK 0x00000200L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_TIMESTAMP_CNTL_MASK 0x00000400L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS5_REG_MASK 0x00000800L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_RESET_REQ_MASK 0x00001000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_DEQUEUE_REQUEST_MASK 0x00002000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_STATUS6_REG_MASK 0x00004000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL_MASK 0x00008000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS_MASK 0x00010000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_POISON_INFO_MASK 0x00020000L +#define SDMA0_SDMA_PUB_REG_TYPE3__SDMA_MEMHUB_CNTL_MASK 0x00040000L +#define SDMA0_SDMA_PUB_REG_TYPE3__RESERVED_MASK 0xFFF80000L +//SDMA0_SDMA_VM_CNTL +#define SDMA0_SDMA_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA0_SDMA_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA0_SDMA_MCU_CNTL +#define SDMA0_SDMA_MCU_CNTL__HALT__SHIFT 0x0 +#define SDMA0_SDMA_MCU_CNTL__RESET__SHIFT 0x1 +#define SDMA0_SDMA_MCU_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define SDMA0_SDMA_MCU_CNTL__HALT_MASK 0x00000001L +#define SDMA0_SDMA_MCU_CNTL__RESET_MASK 0x00000002L +#define SDMA0_SDMA_MCU_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL +//SDMA0_SDMA_IC_BASE_LO +#define SDMA0_SDMA_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define SDMA0_SDMA_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//SDMA0_SDMA_IC_BASE_HI +#define SDMA0_SDMA_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define SDMA0_SDMA_IC_BASE_HI__IC_BASE_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_IC_BASE_CNTL +#define SDMA0_SDMA_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define SDMA0_SDMA_IC_BASE_CNTL__MTYPE__SHIFT 0x4 +#define SDMA0_SDMA_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define SDMA0_SDMA_IC_BASE_CNTL__TEMPORAL_HINT__SHIFT 0x18 +#define SDMA0_SDMA_IC_BASE_CNTL__SCOPE__SHIFT 0x1c +#define SDMA0_SDMA_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define SDMA0_SDMA_IC_BASE_CNTL__MTYPE_MASK 0x00000030L +#define SDMA0_SDMA_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define SDMA0_SDMA_IC_BASE_CNTL__TEMPORAL_HINT_MASK 0x07000000L +#define SDMA0_SDMA_IC_BASE_CNTL__SCOPE_MASK 0x30000000L +//SDMA0_SDMA_IC_OP_CNTL +#define SDMA0_SDMA_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define SDMA0_SDMA_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define SDMA0_SDMA_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define SDMA0_SDMA_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define SDMA0_SDMA_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define SDMA0_SDMA_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//SDMA0_SDMA_IC_CNTL +#define SDMA0_SDMA_IC_CNTL__CID_SEL__SHIFT 0x0 +#define SDMA0_SDMA_IC_CNTL__GPA__SHIFT 0x2 +#define SDMA0_SDMA_IC_CNTL__UCODE_VF_OVERRIDE__SHIFT 0x4 +#define SDMA0_SDMA_IC_CNTL__AUTO_PRIME_ICACHE__SHIFT 0x5 +#define SDMA0_SDMA_IC_CNTL__CID_SEL_MASK 0x00000001L +#define SDMA0_SDMA_IC_CNTL__GPA_MASK 0x0000000CL +#define SDMA0_SDMA_IC_CNTL__UCODE_VF_OVERRIDE_MASK 0x00000010L +#define SDMA0_SDMA_IC_CNTL__AUTO_PRIME_ICACHE_MASK 0x00000020L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapspdec +//SDMA0_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET +#define SDMA0_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET__DATA__SHIFT 0x0 +#define SDMA0_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfsdec +//SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SDMA0_SDMA_PERFCNT_MISC_CNTL +#define SDMA0_SDMA_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +//SDMA0_SDMA_PERFCOUNTER0_SELECT +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER0_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER1_SELECT +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER1_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER2_SELECT +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER2_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER3_SELECT +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER3_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER4_SELECT +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER4_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER5_SELECT +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA0_SDMA_PERFCOUNTER5_SELECT1 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA0_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE2_MASK 0xF0000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfddec +//SDMA0_SDMA_PERFCNT_PERFCOUNTER_LO +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCNT_PERFCOUNTER_HI +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define SDMA0_SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//SDMA0_SDMA_PERFCOUNTER0_LO +#define SDMA0_SDMA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER0_HI +#define SDMA0_SDMA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER1_LO +#define SDMA0_SDMA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER1_HI +#define SDMA0_SDMA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER2_LO +#define SDMA0_SDMA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER2_HI +#define SDMA0_SDMA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER3_LO +#define SDMA0_SDMA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER3_HI +#define SDMA0_SDMA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER4_LO +#define SDMA0_SDMA_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER4_HI +#define SDMA0_SDMA_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER5_LO +#define SDMA0_SDMA_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA0_SDMA_PERFCOUNTER5_HI +#define SDMA0_SDMA_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA0_SDMA_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapwrdec +//SDMA0_GFX_ICG_SDMA_CTRL +#define SDMA0_GFX_ICG_SDMA_CTRL__REG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x1 +#define SDMA0_GFX_ICG_SDMA_CTRL__PTR_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x2 +#define SDMA0_GFX_ICG_SDMA_CTRL__PIO_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x3 +#define SDMA0_GFX_ICG_SDMA_CTRL__MCU_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x4 +#define SDMA0_GFX_ICG_SDMA_CTRL__COPY_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x5 +#define SDMA0_GFX_ICG_SDMA_CTRL__SERVE_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x6 +#define SDMA0_GFX_ICG_SDMA_CTRL__CMD_FETCH_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x7 +#define SDMA0_GFX_ICG_SDMA_CTRL__GU_MEMREQ_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x8 +#define SDMA0_GFX_ICG_SDMA_CTRL__INV_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x9 +#define SDMA0_GFX_ICG_SDMA_CTRL__GU_CACHE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xa +#define SDMA0_GFX_ICG_SDMA_CTRL__IC_CACHE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xb +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xc +#define SDMA0_GFX_ICG_SDMA_CTRL__PERF_CNTR_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xd +#define SDMA0_GFX_ICG_SDMA_CTRL__CORE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xe +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xf +#define SDMA0_GFX_ICG_SDMA_CTRL__FE_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x10 +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESEFE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x11 +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_FE_WARMUP_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x12 +#define SDMA0_GFX_ICG_SDMA_CTRL__MGCG_CLK_HYST__SHIFT 0x18 +#define SDMA0_GFX_ICG_SDMA_CTRL__REG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000002L +#define SDMA0_GFX_ICG_SDMA_CTRL__PTR_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000004L +#define SDMA0_GFX_ICG_SDMA_CTRL__PIO_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000008L +#define SDMA0_GFX_ICG_SDMA_CTRL__MCU_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000010L +#define SDMA0_GFX_ICG_SDMA_CTRL__COPY_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000020L +#define SDMA0_GFX_ICG_SDMA_CTRL__SERVE_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000040L +#define SDMA0_GFX_ICG_SDMA_CTRL__CMD_FETCH_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000080L +#define SDMA0_GFX_ICG_SDMA_CTRL__GU_MEMREQ_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000100L +#define SDMA0_GFX_ICG_SDMA_CTRL__INV_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000200L +#define SDMA0_GFX_ICG_SDMA_CTRL__GU_CACHE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000400L +#define SDMA0_GFX_ICG_SDMA_CTRL__IC_CACHE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000800L +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00001000L +#define SDMA0_GFX_ICG_SDMA_CTRL__PERF_CNTR_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00002000L +#define SDMA0_GFX_ICG_SDMA_CTRL__CORE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00004000L +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00008000L +#define SDMA0_GFX_ICG_SDMA_CTRL__FE_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00010000L +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESEFE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00020000L +#define SDMA0_GFX_ICG_SDMA_CTRL__MEM_CHNL_FE_WARMUP_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00040000L +#define SDMA0_GFX_ICG_SDMA_CTRL__MGCG_CLK_HYST_MASK 0xFF000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmadec:1 +//SDMA1_SDMA_DEC_START +#define SDMA1_SDMA_DEC_START__START__SHIFT 0x0 +#define SDMA1_SDMA_DEC_START__START_MASK 0xFFFFFFFFL +//SDMA1_SDMA_MCU_MISC_CNTL +#define SDMA1_SDMA_MCU_MISC_CNTL__MCU_WAKEUP__SHIFT 0x0 +#define SDMA1_SDMA_MCU_MISC_CNTL__MCU_WAKEUP_MASK 0x00000001L +//SDMA1_SDMA_UCODE_REV +#define SDMA1_SDMA_UCODE_REV__P4_CL__SHIFT 0x0 +#define SDMA1_SDMA_UCODE_REV__DEBUG_VER__SHIFT 0x18 +#define SDMA1_SDMA_UCODE_REV__VARIANT_ID__SHIFT 0x1c +#define SDMA1_SDMA_UCODE_REV__P4_CL_MASK 0x00FFFFFFL +#define SDMA1_SDMA_UCODE_REV__DEBUG_VER_MASK 0x0F000000L +#define SDMA1_SDMA_UCODE_REV__VARIANT_ID_MASK 0xF0000000L +//SDMA1_SDMA_GLOBAL_TIMESTAMP_LO +#define SDMA1_SDMA_GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_GLOBAL_TIMESTAMP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_GLOBAL_TIMESTAMP_HI +#define SDMA1_SDMA_GLOBAL_TIMESTAMP_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_GLOBAL_TIMESTAMP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_POWER_CNTL +#define SDMA1_SDMA_POWER_CNTL__LS_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_POWER_CNTL__LS_ENABLE_MASK 0x00000100L +//SDMA1_SDMA_CNTL +#define SDMA1_SDMA_CNTL__TRAP_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_CNTL__RESERVED__SHIFT 0x2 +#define SDMA1_SDMA_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 +#define SDMA1_SDMA_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 +#define SDMA1_SDMA_CNTL__PIO_DONE_ACK_ENABLE__SHIFT 0x6 +#define SDMA1_SDMA_CNTL__CP_MES_SYNC_ENABLE__SHIFT 0x7 +#define SDMA1_SDMA_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_CNTL__MIDCMD_EXPIRE_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_CNTL__CP_MES_INT_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_CNTL__PAGE_NULL_INT_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_CNTL__PAGE_FAULT_INT_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_CNTL__CH_PERFCNT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 +#define SDMA1_SDMA_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d +#define SDMA1_SDMA_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e +#define SDMA1_SDMA_CNTL__RB_PREEMPT_INT_ENABLE__SHIFT 0x1f +#define SDMA1_SDMA_CNTL__TRAP_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_CNTL__RESERVED_MASK 0x00000004L +#define SDMA1_SDMA_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L +#define SDMA1_SDMA_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L +#define SDMA1_SDMA_CNTL__PIO_DONE_ACK_ENABLE_MASK 0x00000040L +#define SDMA1_SDMA_CNTL__CP_MES_SYNC_ENABLE_MASK 0x00000080L +#define SDMA1_SDMA_CNTL__TMZ_MIDCMD_PREEMPT_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_CNTL__MIDCMD_EXPIRE_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_CNTL__CP_MES_INT_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_CNTL__PAGE_RETRY_TIMEOUT_INT_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_CNTL__PAGE_NULL_INT_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_CNTL__PAGE_FAULT_INT_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_CNTL__CH_PERFCNT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L +#define SDMA1_SDMA_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L +#define SDMA1_SDMA_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L +#define SDMA1_SDMA_CNTL__RB_PREEMPT_INT_ENABLE_MASK 0x80000000L +//SDMA1_SDMA_CHICKEN_BITS +#define SDMA1_SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x5 +#define SDMA1_SDMA_CHICKEN_BITS__RD_BURST__SHIFT 0x6 +#define SDMA1_SDMA_CHICKEN_BITS__WR_BURST__SHIFT 0x8 +#define SDMA1_SDMA_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE__SHIFT 0xa +#define SDMA1_SDMA_CHICKEN_BITS__WR_COMBINE_256B_ENABLE__SHIFT 0xe +#define SDMA1_SDMA_CHICKEN_BITS__RD_COMBINE_256B_ENABLE__SHIFT 0xf +#define SDMA1_SDMA_CHICKEN_BITS__OVERLAP_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_CHICKEN_BITS__T2L_256B_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG__SHIFT 0x13 +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG__SHIFT 0x14 +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG__SHIFT 0x15 +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG__SHIFT 0x16 +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG__SHIFT 0x17 +#define SDMA1_SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x18 +#define SDMA1_SDMA_CHICKEN_BITS__SW_FREEZE_ENABLE__SHIFT 0x19 +#define SDMA1_SDMA_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL__SHIFT 0x1a +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_REG_ADDR_CHECK__SHIFT 0x1b +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CANE_FGCG__SHIFT 0x1c +#define SDMA1_SDMA_CHICKEN_BITS__RESERVED__SHIFT 0x1d +#define SDMA1_SDMA_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00000020L +#define SDMA1_SDMA_CHICKEN_BITS__RD_BURST_MASK 0x000000C0L +#define SDMA1_SDMA_CHICKEN_BITS__WR_BURST_MASK 0x00000300L +#define SDMA1_SDMA_CHICKEN_BITS__COMBINE_256B_WAIT_CYCLE_MASK 0x00003C00L +#define SDMA1_SDMA_CHICKEN_BITS__WR_COMBINE_256B_ENABLE_MASK 0x00004000L +#define SDMA1_SDMA_CHICKEN_BITS__RD_COMBINE_256B_ENABLE_MASK 0x00008000L +#define SDMA1_SDMA_CHICKEN_BITS__OVERLAP_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_CHICKEN_BITS__T2L_256B_ENABLE_MASK 0x00040000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GCR_FGCG_MASK 0x00080000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_GRBM_FGCG_MASK 0x00100000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CH_FGCG_MASK 0x00200000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL2_INVREQ_FGCG_MASK 0x00400000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_UTCL1_FGCG_MASK 0x00800000L +#define SDMA1_SDMA_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x01000000L +#define SDMA1_SDMA_CHICKEN_BITS__SW_FREEZE_ENABLE_MASK 0x02000000L +#define SDMA1_SDMA_CHICKEN_BITS__DRAM_ECC_COPY_MODE_CNTL_MASK 0x04000000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_REG_ADDR_CHECK_MASK 0x08000000L +#define SDMA1_SDMA_CHICKEN_BITS__SOFT_OVERRIDE_CANE_FGCG_MASK 0x10000000L +#define SDMA1_SDMA_CHICKEN_BITS__RESERVED_MASK 0xE0000000L +//SDMA1_SDMA_CACHE_CNTL +#define SDMA1_SDMA_CACHE_CNTL__RD_TEMPORAL_HINT__SHIFT 0x0 +#define SDMA1_SDMA_CACHE_CNTL__WR_TEMPORAL_HINT__SHIFT 0x3 +#define SDMA1_SDMA_CACHE_CNTL__RD_SCOPE__SHIFT 0xc +#define SDMA1_SDMA_CACHE_CNTL__WR_SCOPE__SHIFT 0xe +#define SDMA1_SDMA_CACHE_CNTL__RD_TEMPORAL_HINT_MASK 0x00000007L +#define SDMA1_SDMA_CACHE_CNTL__WR_TEMPORAL_HINT_MASK 0x00000038L +#define SDMA1_SDMA_CACHE_CNTL__RD_SCOPE_MASK 0x00003000L +#define SDMA1_SDMA_CACHE_CNTL__WR_SCOPE_MASK 0x0000C000L +//SDMA1_SDMA_RB_RPTR_FETCH +#define SDMA1_SDMA_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL +//SDMA1_SDMA_RB_RPTR_FETCH_HI +#define SDMA1_SDMA_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_IB_OFFSET_FETCH +#define SDMA1_SDMA_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_PROGRAM +#define SDMA1_SDMA_PROGRAM__STREAM__SHIFT 0x0 +#define SDMA1_SDMA_PROGRAM__STREAM_MASK 0xFFFFFFFFL +//SDMA1_SDMA_STATUS_REG +#define SDMA1_SDMA_STATUS_REG__IDLE__SHIFT 0x0 +#define SDMA1_SDMA_STATUS_REG__REG_IDLE__SHIFT 0x1 +#define SDMA1_SDMA_STATUS_REG__RB_EMPTY__SHIFT 0x2 +#define SDMA1_SDMA_STATUS_REG__RESERVED_3__SHIFT 0x3 +#define SDMA1_SDMA_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 +#define SDMA1_SDMA_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 +#define SDMA1_SDMA_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 +#define SDMA1_SDMA_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 +#define SDMA1_SDMA_STATUS_REG__CORE_IDLE__SHIFT 0x8 +#define SDMA1_SDMA_STATUS_REG__INSIDE_IB__SHIFT 0x9 +#define SDMA1_SDMA_STATUS_REG__FETCH_IDLE__SHIFT 0xa +#define SDMA1_SDMA_STATUS_REG__CGCG_FENCE__SHIFT 0xb +#define SDMA1_SDMA_STATUS_REG__PACKET_READY__SHIFT 0xc +#define SDMA1_SDMA_STATUS_REG__MC_WR_IDLE__SHIFT 0xd +#define SDMA1_SDMA_STATUS_REG__SRBM_IDLE__SHIFT 0xe +#define SDMA1_SDMA_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf +#define SDMA1_SDMA_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 +#define SDMA1_SDMA_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 +#define SDMA1_SDMA_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 +#define SDMA1_SDMA_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 +#define SDMA1_SDMA_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 +#define SDMA1_SDMA_STATUS_REG__RESERVED_24_21__SHIFT 0x15 +#define SDMA1_SDMA_STATUS_REG__EXEC_ENG_IDLE__SHIFT 0x19 +#define SDMA1_SDMA_STATUS_REG__PROC_CNTL_IDLE__SHIFT 0x1a +#define SDMA1_SDMA_STATUS_REG__UCODE_INIT_DONE__SHIFT 0x1b +#define SDMA1_SDMA_STATUS_REG__RESERVED_29_28__SHIFT 0x1c +#define SDMA1_SDMA_STATUS_REG__INT_IDLE__SHIFT 0x1e +#define SDMA1_SDMA_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f +#define SDMA1_SDMA_STATUS_REG__IDLE_MASK 0x00000001L +#define SDMA1_SDMA_STATUS_REG__REG_IDLE_MASK 0x00000002L +#define SDMA1_SDMA_STATUS_REG__RB_EMPTY_MASK 0x00000004L +#define SDMA1_SDMA_STATUS_REG__RESERVED_3_MASK 0x00000008L +#define SDMA1_SDMA_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L +#define SDMA1_SDMA_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L +#define SDMA1_SDMA_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L +#define SDMA1_SDMA_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L +#define SDMA1_SDMA_STATUS_REG__CORE_IDLE_MASK 0x00000100L +#define SDMA1_SDMA_STATUS_REG__INSIDE_IB_MASK 0x00000200L +#define SDMA1_SDMA_STATUS_REG__FETCH_IDLE_MASK 0x00000400L +#define SDMA1_SDMA_STATUS_REG__CGCG_FENCE_MASK 0x00000800L +#define SDMA1_SDMA_STATUS_REG__PACKET_READY_MASK 0x00001000L +#define SDMA1_SDMA_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L +#define SDMA1_SDMA_STATUS_REG__SRBM_IDLE_MASK 0x00004000L +#define SDMA1_SDMA_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L +#define SDMA1_SDMA_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L +#define SDMA1_SDMA_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L +#define SDMA1_SDMA_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L +#define SDMA1_SDMA_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L +#define SDMA1_SDMA_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L +#define SDMA1_SDMA_STATUS_REG__RESERVED_24_21_MASK 0x01E00000L +#define SDMA1_SDMA_STATUS_REG__EXEC_ENG_IDLE_MASK 0x02000000L +#define SDMA1_SDMA_STATUS_REG__PROC_CNTL_IDLE_MASK 0x04000000L +#define SDMA1_SDMA_STATUS_REG__UCODE_INIT_DONE_MASK 0x08000000L +#define SDMA1_SDMA_STATUS_REG__RESERVED_29_28_MASK 0x30000000L +#define SDMA1_SDMA_STATUS_REG__INT_IDLE_MASK 0x40000000L +#define SDMA1_SDMA_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L +//SDMA1_SDMA_STATUS1_REG +#define SDMA1_SDMA_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 +#define SDMA1_SDMA_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 +#define SDMA1_SDMA_STATUS1_REG__CE_SPLIT_RD_IDLE__SHIFT 0x2 +#define SDMA1_SDMA_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 +#define SDMA1_SDMA_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 +#define SDMA1_SDMA_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 +#define SDMA1_SDMA_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 +#define SDMA1_SDMA_STATUS1_REG__CE_WR_TRACK_IDLE__SHIFT 0x7 +#define SDMA1_SDMA_STATUS1_REG__CE_SPLIT_WR_IDLE__SHIFT 0x8 +#define SDMA1_SDMA_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 +#define SDMA1_SDMA_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa +#define SDMA1_SDMA_STATUS1_REG__CE_INFO_FULL__SHIFT 0xb +#define SDMA1_SDMA_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xc +#define SDMA1_SDMA_STATUS1_REG__EX_START__SHIFT 0xd +#define SDMA1_SDMA_STATUS1_REG__CE_RD_STALL__SHIFT 0xf +#define SDMA1_SDMA_STATUS1_REG__CE_WR_STALL__SHIFT 0x10 +#define SDMA1_SDMA_STATUS1_REG__SEC_INTR_STATUS__SHIFT 0x11 +#define SDMA1_SDMA_STATUS1_REG__WPTR_POLL_IDLE__SHIFT 0x12 +#define SDMA1_SDMA_STATUS1_REG__SDMA_IDLE__SHIFT 0x13 +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_IDLE__SHIFT 0x14 +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_FAULT__SHIFT 0x15 +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_RETRY_TIMEOUT__SHIFT 0x16 +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_NULL__SHIFT 0x17 +#define SDMA1_SDMA_STATUS1_REG__MCU_FW_STACK_OVERFLOW__SHIFT 0x18 +#define SDMA1_SDMA_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L +#define SDMA1_SDMA_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L +#define SDMA1_SDMA_STATUS1_REG__CE_SPLIT_RD_IDLE_MASK 0x00000004L +#define SDMA1_SDMA_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L +#define SDMA1_SDMA_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L +#define SDMA1_SDMA_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L +#define SDMA1_SDMA_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L +#define SDMA1_SDMA_STATUS1_REG__CE_WR_TRACK_IDLE_MASK 0x00000080L +#define SDMA1_SDMA_STATUS1_REG__CE_SPLIT_WR_IDLE_MASK 0x00000100L +#define SDMA1_SDMA_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L +#define SDMA1_SDMA_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L +#define SDMA1_SDMA_STATUS1_REG__CE_INFO_FULL_MASK 0x00000800L +#define SDMA1_SDMA_STATUS1_REG__CE_INFO1_FULL_MASK 0x00001000L +#define SDMA1_SDMA_STATUS1_REG__EX_START_MASK 0x00002000L +#define SDMA1_SDMA_STATUS1_REG__CE_RD_STALL_MASK 0x00008000L +#define SDMA1_SDMA_STATUS1_REG__CE_WR_STALL_MASK 0x00010000L +#define SDMA1_SDMA_STATUS1_REG__SEC_INTR_STATUS_MASK 0x00020000L +#define SDMA1_SDMA_STATUS1_REG__WPTR_POLL_IDLE_MASK 0x00040000L +#define SDMA1_SDMA_STATUS1_REG__SDMA_IDLE_MASK 0x00080000L +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_IDLE_MASK 0x00100000L +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_FAULT_MASK 0x00200000L +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_RETRY_TIMEOUT_MASK 0x00400000L +#define SDMA1_SDMA_STATUS1_REG__IC_FETCH_PAGE_NULL_MASK 0x00800000L +#define SDMA1_SDMA_STATUS1_REG__MCU_FW_STACK_OVERFLOW_MASK 0x03000000L +//SDMA1_SDMA_CNTL1 +#define SDMA1_SDMA_CNTL1__WPTR_POLL_FREQUENCY__SHIFT 0x2 +#define SDMA1_SDMA_CNTL1__WPTR_POLL_FREQUENCY_MASK 0x0000FFFCL +//SDMA1_SDMA_HBM_PAGE_CONFIG +#define SDMA1_SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 +#define SDMA1_SDMA_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L +//SDMA1_SDMA_FREEZE +#define SDMA1_SDMA_FREEZE__FROZEN__SHIFT 0x5 +#define SDMA1_SDMA_FREEZE__MCU_FREEZE__SHIFT 0x6 +#define SDMA1_SDMA_FREEZE__IMU_FSM_STATE__SHIFT 0x8 +#define SDMA1_SDMA_FREEZE__EXTERNAL_FROZEN__SHIFT 0xc +#define SDMA1_SDMA_FREEZE__FROZEN_MASK 0x00000020L +#define SDMA1_SDMA_FREEZE__MCU_FREEZE_MASK 0x00000040L +#define SDMA1_SDMA_FREEZE__IMU_FSM_STATE_MASK 0x00000300L +#define SDMA1_SDMA_FREEZE__EXTERNAL_FROZEN_MASK 0x00001000L +//SDMA1_SDMA_PROCESS_QUANTUM0 +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS0_QUANTUM__SHIFT 0x0 +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS1_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS2_QUANTUM__SHIFT 0x10 +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS3_QUANTUM__SHIFT 0x18 +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS0_QUANTUM_MASK 0x000000FFL +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS1_QUANTUM_MASK 0x0000FF00L +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS2_QUANTUM_MASK 0x00FF0000L +#define SDMA1_SDMA_PROCESS_QUANTUM0__PROCESS3_QUANTUM_MASK 0xFF000000L +//SDMA1_SDMA_PROCESS_QUANTUM1 +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS4_QUANTUM__SHIFT 0x0 +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS5_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS6_QUANTUM__SHIFT 0x10 +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS7_QUANTUM__SHIFT 0x18 +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS4_QUANTUM_MASK 0x000000FFL +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS5_QUANTUM_MASK 0x0000FF00L +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS6_QUANTUM_MASK 0x00FF0000L +#define SDMA1_SDMA_PROCESS_QUANTUM1__PROCESS7_QUANTUM_MASK 0xFF000000L +//SDMA1_SDMA_WATCHDOG_CNTL +#define SDMA1_SDMA_WATCHDOG_CNTL__QUEUE_HANG_COUNT__SHIFT 0x0 +#define SDMA1_SDMA_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT__SHIFT 0x8 +#define SDMA1_SDMA_WATCHDOG_CNTL__QUEUE_HANG_COUNT_MASK 0x000000FFL +#define SDMA1_SDMA_WATCHDOG_CNTL__CMD_TIMEOUT_COUNT_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE_STATUS0 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE0_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE1_STATUS__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE2_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE3_STATUS__SHIFT 0xc +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE4_STATUS__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE5_STATUS__SHIFT 0x14 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE6_STATUS__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE7_STATUS__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE0_STATUS_MASK 0x0000000FL +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE1_STATUS_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE2_STATUS_MASK 0x00000F00L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE3_STATUS_MASK 0x0000F000L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE4_STATUS_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE5_STATUS_MASK 0x00F00000L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE6_STATUS_MASK 0x0F000000L +#define SDMA1_SDMA_QUEUE_STATUS0__QUEUE7_STATUS_MASK 0xF0000000L +//SDMA1_SDMA_QUEUE_STATUS1 +#define SDMA1_SDMA_QUEUE_STATUS1__QUEUE8_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE_STATUS1__QUEUE9_STATUS__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE_STATUS1__QUEUE8_STATUS_MASK 0x0000000FL +#define SDMA1_SDMA_QUEUE_STATUS1__QUEUE9_STATUS_MASK 0x000000F0L +//SDMA1_SDMA_ID +#define SDMA1_SDMA_ID__DEVICE_ID__SHIFT 0x0 +#define SDMA1_SDMA_ID__DEVICE_ID_MASK 0x000000FFL +//SDMA1_SDMA_VERSION +#define SDMA1_SDMA_VERSION__MINVER__SHIFT 0x0 +#define SDMA1_SDMA_VERSION__MAJVER__SHIFT 0x8 +#define SDMA1_SDMA_VERSION__REV__SHIFT 0x10 +#define SDMA1_SDMA_VERSION__MINVER_MASK 0x0000007FL +#define SDMA1_SDMA_VERSION__MAJVER_MASK 0x00007F00L +#define SDMA1_SDMA_VERSION__REV_MASK 0x003F0000L +//SDMA1_SDMA_STATUS2_REG +#define SDMA1_SDMA_STATUS2_REG__ID__SHIFT 0x0 +#define SDMA1_SDMA_STATUS2_REG__TH0MCU_INSTR_PTR__SHIFT 0x2 +#define SDMA1_SDMA_STATUS2_REG__CMD_OP__SHIFT 0x10 +#define SDMA1_SDMA_STATUS2_REG__ID_MASK 0x00000003L +#define SDMA1_SDMA_STATUS2_REG__TH0MCU_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA1_SDMA_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L +//SDMA1_SDMA_ATOMIC_CNTL +#define SDMA1_SDMA_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 +#define SDMA1_SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f +#define SDMA1_SDMA_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL +#define SDMA1_SDMA_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L +//SDMA1_SDMA_ATOMIC_PERMS_CNTL +#define SDMA1_SDMA_ATOMIC_PERMS_CNTL__EN_RETRY_ON_ATOMIC__SHIFT 0x0 +#define SDMA1_SDMA_ATOMIC_PERMS_CNTL__PCIE_ATOMIC_SUPPORTED__SHIFT 0x1 +#define SDMA1_SDMA_ATOMIC_PERMS_CNTL__EN_RETRY_ON_ATOMIC_MASK 0x00000001L +#define SDMA1_SDMA_ATOMIC_PERMS_CNTL__PCIE_ATOMIC_SUPPORTED_MASK 0x00000002L +//SDMA1_SDMA_ATOMIC_PREOP_LO +#define SDMA1_SDMA_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_ATOMIC_PREOP_HI +#define SDMA1_SDMA_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_DCC_CNTL +#define SDMA1_SDMA_DCC_CNTL__DCC_FORCE_BYPASS__SHIFT 0x0 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0__SHIFT 0x1 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0__SHIFT 0x2 +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0__SHIFT 0x3 +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0__SHIFT 0x4 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1__SHIFT 0x5 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1__SHIFT 0x6 +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1__SHIFT 0x7 +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1__SHIFT 0x8 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2__SHIFT 0x9 +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2__SHIFT 0xa +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2__SHIFT 0xb +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2__SHIFT 0xc +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3__SHIFT 0xd +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3__SHIFT 0xe +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3__SHIFT 0xf +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3__SHIFT 0x10 +#define SDMA1_SDMA_DCC_CNTL__DCC_FORCE_BYPASS_MASK 0x00000001L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_0_MASK 0x00000002L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_0_MASK 0x00000004L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_0_MASK 0x00000008L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_0_MASK 0x00000010L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_1_MASK 0x00000020L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_1_MASK 0x00000040L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_1_MASK 0x00000080L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_1_MASK 0x00000100L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_2_MASK 0x00000200L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_2_MASK 0x00000400L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_2_MASK 0x00000800L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_2_MASK 0x00001000L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_OVERRIDE_3_MASK 0x00002000L +#define SDMA1_SDMA_DCC_CNTL__DCC_RD_NOPTE_COMP_EN_3_MASK 0x00004000L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_OVERRIDE_3_MASK 0x00008000L +#define SDMA1_SDMA_DCC_CNTL__DCC_WR_NOPTE_COMP_EN_3_MASK 0x00010000L +//SDMA1_SDMA_UTCL1_WARMUPL2_CNTL +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__WARMUP_EN__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__INTERVAL_VA__SHIFT 0x1 +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__GRANU__SHIFT 0x8 +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__STEP_PER_INTERVAL__SHIFT 0x10 +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__WARMUP_EN_MASK 0x00000001L +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__INTERVAL_VA_MASK 0x0000007EL +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__GRANU_MASK 0x00007F00L +#define SDMA1_SDMA_UTCL1_WARMUPL2_CNTL__STEP_PER_INTERVAL_MASK 0x00070000L +//SDMA1_SDMA_UTCL1_CNTL +#define SDMA1_SDMA_UTCL1_CNTL__REDO_DELAY__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_CNTL__PAGE_WAIT_DELAY__SHIFT 0x5 +#define SDMA1_SDMA_UTCL1_CNTL__RESP_MODE__SHIFT 0x9 +#define SDMA1_SDMA_UTCL1_CNTL__FORCE_INVALIDATION__SHIFT 0xb +#define SDMA1_SDMA_UTCL1_CNTL__FORCE_INVREQ_HEAVY__SHIFT 0xc +#define SDMA1_SDMA_UTCL1_CNTL__WR_EXE_PERMS_CTRL__SHIFT 0xd +#define SDMA1_SDMA_UTCL1_CNTL__RD_EXE_PERMS_CTRL__SHIFT 0xe +#define SDMA1_SDMA_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xf +#define SDMA1_SDMA_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x13 +#define SDMA1_SDMA_UTCL1_CNTL__REQL2_5CYC_CREDIT__SHIFT 0x19 +#define SDMA1_SDMA_UTCL1_CNTL__REDO_DELAY_MASK 0x0000001FL +#define SDMA1_SDMA_UTCL1_CNTL__PAGE_WAIT_DELAY_MASK 0x000001E0L +#define SDMA1_SDMA_UTCL1_CNTL__RESP_MODE_MASK 0x00000600L +#define SDMA1_SDMA_UTCL1_CNTL__FORCE_INVALIDATION_MASK 0x00000800L +#define SDMA1_SDMA_UTCL1_CNTL__FORCE_INVREQ_HEAVY_MASK 0x00001000L +#define SDMA1_SDMA_UTCL1_CNTL__WR_EXE_PERMS_CTRL_MASK 0x00002000L +#define SDMA1_SDMA_UTCL1_CNTL__RD_EXE_PERMS_CTRL_MASK 0x00004000L +#define SDMA1_SDMA_UTCL1_CNTL__INVACK_DELAY_MASK 0x00078000L +#define SDMA1_SDMA_UTCL1_CNTL__REQL2_CREDIT_MASK 0x01F80000L +#define SDMA1_SDMA_UTCL1_CNTL__REQL2_5CYC_CREDIT_MASK 0x7E000000L +//SDMA1_SDMA_UTCL1_WATERMK +#define SDMA1_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP__SHIFT 0x4 +#define SDMA1_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK__SHIFT 0x6 +#define SDMA1_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP__SHIFT 0xa +#define SDMA1_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK__SHIFT 0xc +#define SDMA1_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP__SHIFT 0x10 +#define SDMA1_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK__SHIFT 0x12 +#define SDMA1_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP__SHIFT 0x16 +#define SDMA1_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_WATERMK_MASK 0x0000000FL +#define SDMA1_SDMA_UTCL1_WATERMK__WR_REQ_FIFO_DEPTH_STEP_MASK 0x00000030L +#define SDMA1_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_WATERMK_MASK 0x000003C0L +#define SDMA1_SDMA_UTCL1_WATERMK__RD_REQ_FIFO_DEPTH_STEP_MASK 0x00000C00L +#define SDMA1_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_WATERMK_MASK 0x0000F000L +#define SDMA1_SDMA_UTCL1_WATERMK__WR_PAGE_FIFO_DEPTH_STEP_MASK 0x00030000L +#define SDMA1_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_WATERMK_MASK 0x003C0000L +#define SDMA1_SDMA_UTCL1_WATERMK__RD_PAGE_FIFO_DEPTH_STEP_MASK 0x00C00000L +//SDMA1_SDMA_UTCL1_TIMEOUT +#define SDMA1_SDMA_UTCL1_TIMEOUT__XNACK_LIMIT__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_TIMEOUT__XNACK_LIMIT_MASK 0xFFFFFFFFL +//SDMA1_SDMA_UTCL1_PAGE +#define SDMA1_SDMA_UTCL1_PAGE__INVALID_ADDR__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 +#define SDMA1_SDMA_UTCL1_PAGE__USE_MTYPE__SHIFT 0x7 +#define SDMA1_SDMA_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0xa +#define SDMA1_SDMA_UTCL1_PAGE__USE_IO__SHIFT 0xb +#define SDMA1_SDMA_UTCL1_PAGE__RD_L2_POLICY__SHIFT 0xc +#define SDMA1_SDMA_UTCL1_PAGE__WR_L2_POLICY__SHIFT 0xe +#define SDMA1_SDMA_UTCL1_PAGE__USE_BC__SHIFT 0x16 +#define SDMA1_SDMA_UTCL1_PAGE__ADDR_IS_PA__SHIFT 0x17 +#define SDMA1_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_VALUE__SHIFT 0x18 +#define SDMA1_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_EN__SHIFT 0x19 +#define SDMA1_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_VALUE__SHIFT 0x1b +#define SDMA1_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_EN__SHIFT 0x1e +#define SDMA1_SDMA_UTCL1_PAGE__INVALID_ADDR_MASK 0x00000001L +#define SDMA1_SDMA_UTCL1_PAGE__REQ_TYPE_MASK 0x0000003EL +#define SDMA1_SDMA_UTCL1_PAGE__USE_MTYPE_MASK 0x00000380L +#define SDMA1_SDMA_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000400L +#define SDMA1_SDMA_UTCL1_PAGE__USE_IO_MASK 0x00000800L +#define SDMA1_SDMA_UTCL1_PAGE__RD_L2_POLICY_MASK 0x00003000L +#define SDMA1_SDMA_UTCL1_PAGE__WR_L2_POLICY_MASK 0x0000C000L +#define SDMA1_SDMA_UTCL1_PAGE__USE_BC_MASK 0x00400000L +#define SDMA1_SDMA_UTCL1_PAGE__ADDR_IS_PA_MASK 0x00800000L +#define SDMA1_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_VALUE_MASK 0x01000000L +#define SDMA1_SDMA_UTCL1_PAGE__FORCE_BE_CMD_SNOOP_EN_MASK 0x02000000L +#define SDMA1_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_VALUE_MASK 0x18000000L +#define SDMA1_SDMA_UTCL1_PAGE__MTYPE_NO_PTE_OVERRIDE_EN_MASK 0x40000000L +//SDMA1_SDMA_EXTERNAL_FROZEN +#define SDMA1_SDMA_EXTERNAL_FROZEN__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_EXTERNAL_FROZEN__THRESHOLD_MASK 0x0000FFFFL +//SDMA1_SDMA_FREEZE_TRIGGER +#define SDMA1_SDMA_FREEZE_TRIGGER__CORE_FREEZE__SHIFT 0x0 +#define SDMA1_SDMA_FREEZE_TRIGGER__CORE_FREEZE_MASK 0x00000001L +//SDMA1_SDMA_UTCL1_CACHE_CNTL +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_EN__SHIFT 0x14 +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_VALUE__SHIFT 0x15 +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_IC__SHIFT 0x19 +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_GU__SHIFT 0x1a +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__STRICT_PERMISSION__SHIFT 0x1d +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_EN_MASK 0x00100000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__MTYPE_NO_PTE_OVERRIDE_VALUE_MASK 0x00600000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_IC_MASK 0x02000000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__INVALIDATE_GU_MASK 0x04000000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define SDMA1_SDMA_UTCL1_CACHE_CNTL__STRICT_PERMISSION_MASK 0x20000000L +//SDMA1_SDMA_UTCL1_RD_STATUS +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_DATA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_EMPTY__SHIFT 0x2 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_FULL__SHIFT 0x7 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_FULL__SHIFT 0x8 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_FULL__SHIFT 0x9 +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_FULL__SHIFT 0xb +#define SDMA1_SDMA_UTCL1_RD_STATUS__L2_INTF_RD_IDLE__SHIFT 0x10 +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_REQRET_IDLE__SHIFT 0x11 +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_REQ_IDLE__SHIFT 0x12 +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL1_WARMUP_IDLE__SHIFT 0x1a +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_IDLE__SHIFT 0x1b +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_WARMUP_IDLE__SHIFT 0x1c +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE1_IDLE__SHIFT 0x1d +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE0_IDLE__SHIFT 0x1e +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_IDLE__SHIFT 0x1f +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_DATA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_EMPTY_MASK 0x00000004L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_VA_REQ_SEND_FIFO_FULL_MASK 0x00000080L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REG_ENTRY_FULL_MASK 0x00000100L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_PAGE_FIFO_FULL_MASK 0x00000200L +#define SDMA1_SDMA_UTCL1_RD_STATUS__CE_RD_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_VA_FIFO_FULL_MASK 0x00000800L +#define SDMA1_SDMA_UTCL1_RD_STATUS__L2_INTF_RD_IDLE_MASK 0x00010000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_REQRET_IDLE_MASK 0x00020000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__RD_REQ_IDLE_MASK 0x00040000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL1_WARMUP_IDLE_MASK 0x04000000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_IDLE_MASK 0x08000000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_1CYC_WARMUP_IDLE_MASK 0x10000000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE1_IDLE_MASK 0x20000000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_5CYC_CACHE0_IDLE_MASK 0x40000000L +#define SDMA1_SDMA_UTCL1_RD_STATUS__UTCL2_IDLE_MASK 0x80000000L +//SDMA1_SDMA_UTCL1_WR_STATUS +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_EMPTY__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_EMPTY__SHIFT 0x1 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_EMPTY__SHIFT 0x2 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_EMPTY__SHIFT 0x3 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_EMPTY__SHIFT 0x4 +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY__SHIFT 0x5 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_FULL__SHIFT 0x6 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_FULL__SHIFT 0x7 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_FULL__SHIFT 0x8 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_FULL__SHIFT 0x9 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_FULL__SHIFT 0xa +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_FULL__SHIFT 0xb +#define SDMA1_SDMA_UTCL1_WR_STATUS__L2_INTF_WR_IDLE__SHIFT 0x10 +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_REQRET_IDLE__SHIFT 0x11 +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_REQ_IDLE__SHIFT 0x12 +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_EMPTY_MASK 0x00000001L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_EMPTY_MASK 0x00000002L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_EMPTY_MASK 0x00000004L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_EMPTY_MASK 0x00000008L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_EMPTY_MASK 0x00000010L +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_EMPTY_MASK 0x00000020L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_DATA_FIFO_FULL_MASK 0x00000040L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_VA_REQ_SEND_FIFO_FULL_MASK 0x00000080L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REG_ENTRY_FULL_MASK 0x00000100L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_PAGE_FIFO_FULL_MASK 0x00000200L +#define SDMA1_SDMA_UTCL1_WR_STATUS__CE_WR_REQ_FIFO_FULL_MASK 0x00000400L +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_VA_FIFO_FULL_MASK 0x00000800L +#define SDMA1_SDMA_UTCL1_WR_STATUS__L2_INTF_WR_IDLE_MASK 0x00010000L +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_REQRET_IDLE_MASK 0x00020000L +#define SDMA1_SDMA_UTCL1_WR_STATUS__WR_REQ_IDLE_MASK 0x00040000L +//SDMA1_SDMA_UTCL1_INV0 +#define SDMA1_SDMA_UTCL1_INV0__INV_PROC_BUSY__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_FRAG_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID__SHIFT 0x7 +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_MODE__SHIFT 0xb +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_HIGH__SHIFT 0xd +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_TAG__SHIFT 0xe +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID_HIGH__SHIFT 0x12 +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID_LOW__SHIFT 0x16 +#define SDMA1_SDMA_UTCL1_INV0__INV_TYPE__SHIFT 0x1a +#define SDMA1_SDMA_UTCL1_INV0__INV_PROC_BUSY_MASK 0x00000001L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_FRAG_SIZE_MASK 0x0000007EL +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID_MASK 0x00000780L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_MODE_MASK 0x00001800L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_HIGH_MASK 0x00002000L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_TAG_MASK 0x0003C000L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID_HIGH_MASK 0x003C0000L +#define SDMA1_SDMA_UTCL1_INV0__GPUVM_VMID_LOW_MASK 0x03C00000L +#define SDMA1_SDMA_UTCL1_INV0__INV_TYPE_MASK 0x0C000000L +//SDMA1_SDMA_UTCL1_INV1 +#define SDMA1_SDMA_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_UTCL1_INV2 +#define SDMA1_SDMA_UTCL1_INV2__CPF_VMID__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_INV2__CPF_FLUSH_TYPE__SHIFT 0x10 +#define SDMA1_SDMA_UTCL1_INV2__CPF_FRAG_SIZE__SHIFT 0x11 +#define SDMA1_SDMA_UTCL1_INV2__CPF_VMID_MASK 0x0000FFFFL +#define SDMA1_SDMA_UTCL1_INV2__CPF_FLUSH_TYPE_MASK 0x00010000L +#define SDMA1_SDMA_UTCL1_INV2__CPF_FRAG_SIZE_MASK 0x007E0000L +//SDMA1_SDMA_UTCL1_RD_XNACK0 +#define SDMA1_SDMA_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_RD_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_UTCL1_RD_XNACK1 +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VMID__SHIFT 0xd +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x11 +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR__SHIFT 0x14 +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0x17 +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG__SHIFT 0x1a +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_FLAG__SHIFT 0x1b +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x1c +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x00001FFFL +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VMID_MASK 0x0001E000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_VECTOR_MASK 0x000E0000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_VECTOR_MASK 0x00700000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x03800000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_FAULT_FLAG_MASK 0x04000000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_NULL_FLAG_MASK 0x08000000L +#define SDMA1_SDMA_UTCL1_RD_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x10000000L +//SDMA1_SDMA_UTCL1_WR_XNACK0 +#define SDMA1_SDMA_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_WR_XNACK0__XNACK_FAULT_ADDR_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_UTCL1_WR_XNACK1 +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VMID__SHIFT 0xd +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR__SHIFT 0x11 +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR__SHIFT 0x14 +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR__SHIFT 0x17 +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG__SHIFT 0x1a +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_FLAG__SHIFT 0x1b +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG__SHIFT 0x1c +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_ADDR_HI_MASK 0x00001FFFL +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VMID_MASK 0x0001E000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_VECTOR_MASK 0x000E0000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_VECTOR_MASK 0x00700000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_VECTOR_MASK 0x03800000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_FAULT_FLAG_MASK 0x04000000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_NULL_FLAG_MASK 0x08000000L +#define SDMA1_SDMA_UTCL1_WR_XNACK1__XNACK_TIMEOUT_FLAG_MASK 0x10000000L +//SDMA1_SDMA_CHICKEN_BITS_2 +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_CMD_PROC_DELAY__SHIFT 0x0 +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_SEND_POSTCODE_EN__SHIFT 0x4 +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_DEBUG_MODE__SHIFT 0x5 +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_7_6__SHIFT 0x6 +#define SDMA1_SDMA_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING__SHIFT 0x8 +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_14_12__SHIFT 0xc +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_15__SHIFT 0xf +#define SDMA1_SDMA_CHICKEN_BITS_2__RB_FIFO_WATERMARK__SHIFT 0x10 +#define SDMA1_SDMA_CHICKEN_BITS_2__IB_FIFO_WATERMARK__SHIFT 0x12 +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MARGIN__SHIFT 0x14 +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_RD_WATERMARK__SHIFT 0x17 +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK__SHIFT 0x19 +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_30__SHIFT 0x1e +#define SDMA1_SDMA_CHICKEN_BITS_2__PIO_VFID_SOURCE__SHIFT 0x1f +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_CMD_PROC_DELAY_MASK 0x0000000FL +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_SEND_POSTCODE_EN_MASK 0x00000010L +#define SDMA1_SDMA_CHICKEN_BITS_2__MCU_DEBUG_MODE_MASK 0x00000020L +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_7_6_MASK 0x000000C0L +#define SDMA1_SDMA_CHICKEN_BITS_2__WPTR_POLL_OUTSTANDING_MASK 0x00000F00L +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_14_12_MASK 0x00007000L +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_15_MASK 0x00008000L +#define SDMA1_SDMA_CHICKEN_BITS_2__RB_FIFO_WATERMARK_MASK 0x00030000L +#define SDMA1_SDMA_CHICKEN_BITS_2__IB_FIFO_WATERMARK_MASK 0x000C0000L +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MARGIN_MASK 0x00700000L +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_RD_WATERMARK_MASK 0x01800000L +#define SDMA1_SDMA_CHICKEN_BITS_2__CH_WR_WATERMARK_MASK 0x3E000000L +#define SDMA1_SDMA_CHICKEN_BITS_2__RESERVED_30_MASK 0x40000000L +#define SDMA1_SDMA_CHICKEN_BITS_2__PIO_VFID_SOURCE_MASK 0x80000000L +//SDMA1_SDMA_STATUS3_REG +#define SDMA1_SDMA_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 +#define SDMA1_SDMA_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 +#define SDMA1_SDMA_STATUS3_REG__AQL_PREV_CMD_IDLE__SHIFT 0x15 +#define SDMA1_SDMA_STATUS3_REG__TLBI_IDLE__SHIFT 0x16 +#define SDMA1_SDMA_STATUS3_REG__GCR_IDLE__SHIFT 0x17 +#define SDMA1_SDMA_STATUS3_REG__INVREQ_IDLE__SHIFT 0x18 +#define SDMA1_SDMA_STATUS3_REG__QUEUE_ID_MATCH__SHIFT 0x19 +#define SDMA1_SDMA_STATUS3_REG__INT_QUEUE_ID__SHIFT 0x1a +#define SDMA1_SDMA_STATUS3_REG__TMZ_MTYPE_STATUS__SHIFT 0x1e +#define SDMA1_SDMA_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L +#define SDMA1_SDMA_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L +#define SDMA1_SDMA_STATUS3_REG__AQL_PREV_CMD_IDLE_MASK 0x00200000L +#define SDMA1_SDMA_STATUS3_REG__TLBI_IDLE_MASK 0x00400000L +#define SDMA1_SDMA_STATUS3_REG__GCR_IDLE_MASK 0x00800000L +#define SDMA1_SDMA_STATUS3_REG__INVREQ_IDLE_MASK 0x01000000L +#define SDMA1_SDMA_STATUS3_REG__QUEUE_ID_MATCH_MASK 0x02000000L +#define SDMA1_SDMA_STATUS3_REG__INT_QUEUE_ID_MASK 0x3C000000L +#define SDMA1_SDMA_STATUS3_REG__TMZ_MTYPE_STATUS_MASK 0xC0000000L +//SDMA1_SDMA_GLOBAL_QUANTUM +#define SDMA1_SDMA_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM__SHIFT 0x0 +#define SDMA1_SDMA_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_GLOBAL_QUANTUM__GLOBAL_FOCUS_QUANTUM_MASK 0x000000FFL +#define SDMA1_SDMA_GLOBAL_QUANTUM__GLOBAL_NORMAL_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_ERROR_LOG +#define SDMA1_SDMA_ERROR_LOG__OVERRIDE__SHIFT 0x0 +#define SDMA1_SDMA_ERROR_LOG__STATUS__SHIFT 0x10 +#define SDMA1_SDMA_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL +#define SDMA1_SDMA_ERROR_LOG__STATUS_MASK 0xFFFF0000L +//SDMA1_SDMA_PUB_DUMMY_REG0 +#define SDMA1_SDMA_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PUB_DUMMY_REG1 +#define SDMA1_SDMA_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PUB_DUMMY_REG2 +#define SDMA1_SDMA_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PUB_DUMMY_REG3 +#define SDMA1_SDMA_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_MCU_COUNTER +#define SDMA1_SDMA_MCU_COUNTER__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_MCU_COUNTER__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_CRD_CNTL +#define SDMA1_SDMA_CRD_CNTL__CH_WRREQ_CREDIT__SHIFT 0x13 +#define SDMA1_SDMA_CRD_CNTL__CH_RDREQ_CREDIT__SHIFT 0x19 +#define SDMA1_SDMA_CRD_CNTL__CH_WRREQ_CREDIT_MASK 0x01F80000L +#define SDMA1_SDMA_CRD_CNTL__CH_RDREQ_CREDIT_MASK 0x7E000000L +//SDMA1_SDMA_RLC_CGCG_CTRL +#define SDMA1_SDMA_RLC_CGCG_CTRL__CGCG_INT_ENABLE__SHIFT 0x1 +#define SDMA1_SDMA_RLC_CGCG_CTRL__MCU_CGCG_ALLOW__SHIFT 0x4 +#define SDMA1_SDMA_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS__SHIFT 0x10 +#define SDMA1_SDMA_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK 0x00000002L +#define SDMA1_SDMA_RLC_CGCG_CTRL__MCU_CGCG_ALLOW_MASK 0x00000010L +#define SDMA1_SDMA_RLC_CGCG_CTRL__CGCG_IDLE_HYSTERESIS_MASK 0xFFFF0000L +//SDMA1_SDMA_GPU_IOV_VIOLATION_LOG +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x14 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x15 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x16 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x000FFFFCL +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00100000L +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00200000L +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x07C00000L +//SDMA1_SDMA_AQL_STATUS +#define SDMA1_SDMA_AQL_STATUS__COMPLETE_SIGNAL_EMPTY__SHIFT 0x0 +#define SDMA1_SDMA_AQL_STATUS__INVALID_CMD_EMPTY__SHIFT 0x1 +#define SDMA1_SDMA_AQL_STATUS__COMPLETE_SIGNAL_EMPTY_MASK 0x00000001L +#define SDMA1_SDMA_AQL_STATUS__INVALID_CMD_EMPTY_MASK 0x00000002L +//SDMA1_SDMA_TLBI_GCR_CNTL +#define SDMA1_SDMA_TLBI_GCR_CNTL__TLBI_CMD_DW__SHIFT 0x0 +#define SDMA1_SDMA_TLBI_GCR_CNTL__GCR_CMD_DW__SHIFT 0x4 +#define SDMA1_SDMA_TLBI_GCR_CNTL__TLBI_CREDIT__SHIFT 0x10 +#define SDMA1_SDMA_TLBI_GCR_CNTL__GCR_CREDIT__SHIFT 0x18 +#define SDMA1_SDMA_TLBI_GCR_CNTL__TLBI_CMD_DW_MASK 0x0000000FL +#define SDMA1_SDMA_TLBI_GCR_CNTL__GCR_CMD_DW_MASK 0x000000F0L +#define SDMA1_SDMA_TLBI_GCR_CNTL__TLBI_CREDIT_MASK 0x00FF0000L +#define SDMA1_SDMA_TLBI_GCR_CNTL__GCR_CREDIT_MASK 0xFF000000L +//SDMA1_SDMA_INT_STATUS +#define SDMA1_SDMA_INT_STATUS__DATA__SHIFT 0x0 +#define SDMA1_SDMA_INT_STATUS__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_GPU_IOV_VIOLATION_LOG2 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID__SHIFT 0x0 +#define SDMA1_SDMA_GPU_IOV_VIOLATION_LOG2__INITIATOR_ID_MASK 0x000003FFL +//SDMA1_SDMA_INVALID_ADDR_LO +#define SDMA1_SDMA_INVALID_ADDR_LO__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_INVALID_ADDR_LO__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_INVALID_ADDR_HI +#define SDMA1_SDMA_INVALID_ADDR_HI__VALUE__SHIFT 0x0 +#define SDMA1_SDMA_INVALID_ADDR_HI__VALUE_MASK 0xFFFFFFFFL +//SDMA1_SDMA_INVALID_ADDR_SOURCE +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__ID__SHIFT 0x0 +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VMID__SHIFT 0x6 +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VFID__SHIFT 0xa +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VF__SHIFT 0xf +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__ID_MASK 0x0000003FL +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VMID_MASK 0x000003C0L +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VFID_MASK 0x00007C00L +#define SDMA1_SDMA_INVALID_ADDR_SOURCE__VF_MASK 0x00008000L +//SDMA1_SDMA_CLOCK_GATING_STATUS +#define SDMA1_SDMA_CLOCK_GATING_STATUS__PTR_MGCG_CLK_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__PIO_MGCG_CLK_STATUS__SHIFT 0x9 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MCU_MGCG_CLK_STATUS__SHIFT 0xa +#define SDMA1_SDMA_CLOCK_GATING_STATUS__COPY_ENG_MGCG_CLK_STATUS__SHIFT 0xb +#define SDMA1_SDMA_CLOCK_GATING_STATUS__SERVE_ENG_MGCG_CLK_STATUS__SHIFT 0xc +#define SDMA1_SDMA_CLOCK_GATING_STATUS__CMD_FETCH_MGCG_CLK_STATUS__SHIFT 0xd +#define SDMA1_SDMA_CLOCK_GATING_STATUS__GU_MEMREQ_MGCG_CLK_STATUS__SHIFT 0xe +#define SDMA1_SDMA_CLOCK_GATING_STATUS__INV_MGCG_CLK_STATUS__SHIFT 0xf +#define SDMA1_SDMA_CLOCK_GATING_STATUS__GU_CACHE_MGCG_CLK_STATUS__SHIFT 0x10 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__IC_CACHE_MGCG_CLK_STATUS__SHIFT 0x11 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_MGCG_CLK_STATUS__SHIFT 0x12 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESE_MGCG_CLK_STATUS__SHIFT 0x13 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__FE_ENG_MGCG_CLK_STATUS__SHIFT 0x14 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESEFE_MGCG_CLK_STATUS__SHIFT 0x15 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_FE_WARMUP_MGCG_CLK_STATUS__SHIFT 0x16 +#define SDMA1_SDMA_CLOCK_GATING_STATUS__PTR_MGCG_CLK_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__PIO_MGCG_CLK_STATUS_MASK 0x00000200L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MCU_MGCG_CLK_STATUS_MASK 0x00000400L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__COPY_ENG_MGCG_CLK_STATUS_MASK 0x00000800L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__SERVE_ENG_MGCG_CLK_STATUS_MASK 0x00001000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__CMD_FETCH_MGCG_CLK_STATUS_MASK 0x00002000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__GU_MEMREQ_MGCG_CLK_STATUS_MASK 0x00004000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__INV_MGCG_CLK_STATUS_MASK 0x00008000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__GU_CACHE_MGCG_CLK_STATUS_MASK 0x00010000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__IC_CACHE_MGCG_CLK_STATUS_MASK 0x00020000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_MGCG_CLK_STATUS_MASK 0x00040000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESE_MGCG_CLK_STATUS_MASK 0x00080000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__FE_ENG_MGCG_CLK_STATUS_MASK 0x00100000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_CESEFE_MGCG_CLK_STATUS_MASK 0x00200000L +#define SDMA1_SDMA_CLOCK_GATING_STATUS__MEM_CHNL_FE_WARMUP_MGCG_CLK_STATUS_MASK 0x00400000L +//SDMA1_SDMA_STATUS4_REG +#define SDMA1_SDMA_STATUS4_REG__IDLE__SHIFT 0x0 +#define SDMA1_SDMA_STATUS4_REG__IH_OUTSTANDING__SHIFT 0x2 +#define SDMA1_SDMA_STATUS4_REG__RESERVED__SHIFT 0x3 +#define SDMA1_SDMA_STATUS4_REG__CH_RD_OUTSTANDING__SHIFT 0x4 +#define SDMA1_SDMA_STATUS4_REG__CH_WR_OUTSTANDING__SHIFT 0x5 +#define SDMA1_SDMA_STATUS4_REG__GCR_OUTSTANDING__SHIFT 0x6 +#define SDMA1_SDMA_STATUS4_REG__TLBI_OUTSTANDING__SHIFT 0x7 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING__SHIFT 0x8 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING__SHIFT 0x9 +#define SDMA1_SDMA_STATUS4_REG__CMDFETCH_OUTSTANDING__SHIFT 0xa +#define SDMA1_SDMA_STATUS4_REG__RESERVED_11__SHIFT 0xb +#define SDMA1_SDMA_STATUS4_REG__RESERVED_13_12__SHIFT 0xc +#define SDMA1_SDMA_STATUS4_REG__RESERVED_15_14__SHIFT 0xe +#define SDMA1_SDMA_STATUS4_REG__ACTIVE_QUEUE_ID__SHIFT 0x10 +#define SDMA1_SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD__SHIFT 0x14 +#define SDMA1_SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD__SHIFT 0x15 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_FAULT__SHIFT 0x16 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_NULL__SHIFT 0x17 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT__SHIFT 0x18 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_FAULT__SHIFT 0x19 +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_NULL__SHIFT 0x1a +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT__SHIFT 0x1b +#define SDMA1_SDMA_STATUS4_REG__IDLE_MASK 0x00000001L +#define SDMA1_SDMA_STATUS4_REG__IH_OUTSTANDING_MASK 0x00000004L +#define SDMA1_SDMA_STATUS4_REG__RESERVED_MASK 0x00000008L +#define SDMA1_SDMA_STATUS4_REG__CH_RD_OUTSTANDING_MASK 0x00000010L +#define SDMA1_SDMA_STATUS4_REG__CH_WR_OUTSTANDING_MASK 0x00000020L +#define SDMA1_SDMA_STATUS4_REG__GCR_OUTSTANDING_MASK 0x00000040L +#define SDMA1_SDMA_STATUS4_REG__TLBI_OUTSTANDING_MASK 0x00000080L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_OUTSTANDING_MASK 0x00000100L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_OUTSTANDING_MASK 0x00000200L +#define SDMA1_SDMA_STATUS4_REG__CMDFETCH_OUTSTANDING_MASK 0x00000400L +#define SDMA1_SDMA_STATUS4_REG__RESERVED_11_MASK 0x00000800L +#define SDMA1_SDMA_STATUS4_REG__RESERVED_13_12_MASK 0x00003000L +#define SDMA1_SDMA_STATUS4_REG__RESERVED_15_14_MASK 0x0000C000L +#define SDMA1_SDMA_STATUS4_REG__ACTIVE_QUEUE_ID_MASK 0x000F0000L +#define SDMA1_SDMA_STATUS4_REG__SRIOV_WATING_RLCV_CMD_MASK 0x00100000L +#define SDMA1_SDMA_STATUS4_REG__SRIOV_SDMA_EXECUTING_CMD_MASK 0x00200000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_FAULT_MASK 0x00400000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_NULL_MASK 0x00800000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_RD_XNACK_TIMEOUT_MASK 0x01000000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_FAULT_MASK 0x02000000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_NULL_MASK 0x04000000L +#define SDMA1_SDMA_STATUS4_REG__UTCL2_WR_XNACK_TIMEOUT_MASK 0x08000000L +//SDMA1_SDMA_SCRATCH_RAM_DATA +#define SDMA1_SDMA_SCRATCH_RAM_DATA__DATA__SHIFT 0x0 +#define SDMA1_SDMA_SCRATCH_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_SCRATCH_RAM_ADDR +#define SDMA1_SDMA_SCRATCH_RAM_ADDR__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_SCRATCH_RAM_ADDR__ADDR_MASK 0x0000007FL +//SDMA1_SDMA_TIMESTAMP_CNTL +#define SDMA1_SDMA_TIMESTAMP_CNTL__CAPTURE__SHIFT 0x0 +#define SDMA1_SDMA_TIMESTAMP_CNTL__CAPTURE_MASK 0x00000001L +//SDMA1_SDMA_STATUS5_REG +#define SDMA1_SDMA_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS__SHIFT 0x1 +#define SDMA1_SDMA_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS__SHIFT 0x2 +#define SDMA1_SDMA_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS__SHIFT 0x3 +#define SDMA1_SDMA_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS__SHIFT 0x4 +#define SDMA1_SDMA_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS__SHIFT 0x5 +#define SDMA1_SDMA_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS__SHIFT 0x6 +#define SDMA1_SDMA_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS__SHIFT 0x7 +#define SDMA1_SDMA_STATUS5_REG__QUEUE8_RB_ENABLE_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_STATUS5_REG__QUEUE9_RB_ENABLE_STATUS__SHIFT 0x9 +#define SDMA1_SDMA_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x10 +#define SDMA1_SDMA_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x11 +#define SDMA1_SDMA_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x12 +#define SDMA1_SDMA_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x13 +#define SDMA1_SDMA_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x14 +#define SDMA1_SDMA_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x15 +#define SDMA1_SDMA_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x16 +#define SDMA1_SDMA_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x17 +#define SDMA1_SDMA_STATUS5_REG__QUEUE8_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x18 +#define SDMA1_SDMA_STATUS5_REG__QUEUE9_WPTR_POLL_PAGE_EXCEPTION__SHIFT 0x19 +#define SDMA1_SDMA_STATUS5_REG__QUEUE0_RB_ENABLE_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_STATUS5_REG__QUEUE1_RB_ENABLE_STATUS_MASK 0x00000002L +#define SDMA1_SDMA_STATUS5_REG__QUEUE2_RB_ENABLE_STATUS_MASK 0x00000004L +#define SDMA1_SDMA_STATUS5_REG__QUEUE3_RB_ENABLE_STATUS_MASK 0x00000008L +#define SDMA1_SDMA_STATUS5_REG__QUEUE4_RB_ENABLE_STATUS_MASK 0x00000010L +#define SDMA1_SDMA_STATUS5_REG__QUEUE5_RB_ENABLE_STATUS_MASK 0x00000020L +#define SDMA1_SDMA_STATUS5_REG__QUEUE6_RB_ENABLE_STATUS_MASK 0x00000040L +#define SDMA1_SDMA_STATUS5_REG__QUEUE7_RB_ENABLE_STATUS_MASK 0x00000080L +#define SDMA1_SDMA_STATUS5_REG__QUEUE8_RB_ENABLE_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_STATUS5_REG__QUEUE9_RB_ENABLE_STATUS_MASK 0x00000200L +#define SDMA1_SDMA_STATUS5_REG__QUEUE0_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00010000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE1_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00020000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE2_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00040000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE3_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00080000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE4_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00100000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE5_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00200000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE6_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00400000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE7_WPTR_POLL_PAGE_EXCEPTION_MASK 0x00800000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE8_WPTR_POLL_PAGE_EXCEPTION_MASK 0x01000000L +#define SDMA1_SDMA_STATUS5_REG__QUEUE9_WPTR_POLL_PAGE_EXCEPTION_MASK 0x02000000L +//SDMA1_SDMA_QUEUE_RESET_REQ +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE0_RESET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE1_RESET__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE2_RESET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE3_RESET__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE4_RESET__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE5_RESET__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE6_RESET__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE7_RESET__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE8_RESET__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE9_RESET__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE0_RESET_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE1_RESET_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE2_RESET_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE3_RESET_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE4_RESET_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE5_RESET_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE6_RESET_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE7_RESET_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE8_RESET_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE_RESET_REQ__QUEUE9_RESET_MASK 0x00000200L +//SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE0_DEQUEUE_REQ__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE1_DEQUEUE_REQ__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE2_DEQUEUE_REQ__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE3_DEQUEUE_REQ__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE4_DEQUEUE_REQ__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE5_DEQUEUE_REQ__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE6_DEQUEUE_REQ__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE7_DEQUEUE_REQ__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE8_DEQUEUE_REQ__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE9_DEQUEUE_REQ__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE0_DEQUEUE_REQ_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE1_DEQUEUE_REQ_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE2_DEQUEUE_REQ_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE3_DEQUEUE_REQ_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE4_DEQUEUE_REQ_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE5_DEQUEUE_REQ_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE6_DEQUEUE_REQ_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE7_DEQUEUE_REQ_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE8_DEQUEUE_REQ_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE_DEQUEUE_REQUEST__QUEUE9_DEQUEUE_REQ_MASK 0x00000200L +//SDMA1_SDMA_STATUS6_REG +#define SDMA1_SDMA_STATUS6_REG__ID__SHIFT 0x0 +#define SDMA1_SDMA_STATUS6_REG__TH1MCU_INSTR_PTR__SHIFT 0x2 +#define SDMA1_SDMA_STATUS6_REG__TH1_EXCEPTION__SHIFT 0x10 +#define SDMA1_SDMA_STATUS6_REG__ID_MASK 0x00000003L +#define SDMA1_SDMA_STATUS6_REG__TH1MCU_INSTR_PTR_MASK 0x0000FFFCL +#define SDMA1_SDMA_STATUS6_REG__TH1_EXCEPTION_MASK 0xFFFF0000L +//SDMA1_SDMA_STATUS7_REG +#define SDMA1_SDMA_STATUS7_REG__BLT_REQ_DROP__SHIFT 0x0 +#define SDMA1_SDMA_STATUS7_REG__BLT_REQ_DROP_MASK 0x00000001L +//SDMA1_SDMA_STATUS8_REG +#define SDMA1_SDMA_STATUS8_REG__LD_CTXSW_COND__SHIFT 0x0 +#define SDMA1_SDMA_STATUS8_REG__LD_CTXSW_COND_MASK 0xFFFFFFFFL +//SDMA1_SDMA_CE_CTRL +#define SDMA1_SDMA_CE_CTRL__RD_LUT_WATERMARK__SHIFT 0x0 +#define SDMA1_SDMA_CE_CTRL__RD_LUT_DEPTH__SHIFT 0x3 +#define SDMA1_SDMA_CE_CTRL__WR_AFIFO_WATERMARK__SHIFT 0x5 +#define SDMA1_SDMA_CE_CTRL__RESERVED__SHIFT 0x9 +#define SDMA1_SDMA_CE_CTRL__RD_LUT_WATERMARK_MASK 0x00000007L +#define SDMA1_SDMA_CE_CTRL__RD_LUT_DEPTH_MASK 0x00000018L +#define SDMA1_SDMA_CE_CTRL__WR_AFIFO_WATERMARK_MASK 0x000000E0L +#define SDMA1_SDMA_CE_CTRL__RESERVED_MASK 0xFFFFFE00L +//SDMA1_SDMA_RAS_STATUS +#define SDMA1_SDMA_RAS_STATUS__RB_FETCH_ECC__SHIFT 0x0 +#define SDMA1_SDMA_RAS_STATUS__IB_FETCH_ECC__SHIFT 0x1 +#define SDMA1_SDMA_RAS_STATUS__MCU_DATA_ECC__SHIFT 0x2 +#define SDMA1_SDMA_RAS_STATUS__WPTR_POLL_ECC__SHIFT 0x3 +#define SDMA1_SDMA_RAS_STATUS__COPY_DATA_ECC__SHIFT 0x4 +#define SDMA1_SDMA_RAS_STATUS__INSTR_FETCH_ECC__SHIFT 0x5 +#define SDMA1_SDMA_RAS_STATUS__ATOMIC_ECC__SHIFT 0x6 +#define SDMA1_SDMA_RAS_STATUS__FRONTEND_ECC__SHIFT 0x7 +#define SDMA1_SDMA_RAS_STATUS__SRAM_ECC__SHIFT 0x10 +#define SDMA1_SDMA_RAS_STATUS__BUS_PARITY__SHIFT 0x12 +#define SDMA1_SDMA_RAS_STATUS__VMID__SHIFT 0x14 +#define SDMA1_SDMA_RAS_STATUS__VFID__SHIFT 0x18 +#define SDMA1_SDMA_RAS_STATUS__VF__SHIFT 0x1d +#define SDMA1_SDMA_RAS_STATUS__RB_FETCH_ECC_MASK 0x00000001L +#define SDMA1_SDMA_RAS_STATUS__IB_FETCH_ECC_MASK 0x00000002L +#define SDMA1_SDMA_RAS_STATUS__MCU_DATA_ECC_MASK 0x00000004L +#define SDMA1_SDMA_RAS_STATUS__WPTR_POLL_ECC_MASK 0x00000008L +#define SDMA1_SDMA_RAS_STATUS__COPY_DATA_ECC_MASK 0x00000010L +#define SDMA1_SDMA_RAS_STATUS__INSTR_FETCH_ECC_MASK 0x00000020L +#define SDMA1_SDMA_RAS_STATUS__ATOMIC_ECC_MASK 0x00000040L +#define SDMA1_SDMA_RAS_STATUS__FRONTEND_ECC_MASK 0x00000080L +#define SDMA1_SDMA_RAS_STATUS__SRAM_ECC_MASK 0x00010000L +#define SDMA1_SDMA_RAS_STATUS__BUS_PARITY_MASK 0x00040000L +#define SDMA1_SDMA_RAS_STATUS__VMID_MASK 0x00F00000L +#define SDMA1_SDMA_RAS_STATUS__VFID_MASK 0x1F000000L +#define SDMA1_SDMA_RAS_STATUS__VF_MASK 0x20000000L +//SDMA1_SDMA_POISON_INFO +#define SDMA1_SDMA_POISON_INFO__VMID__SHIFT 0x0 +#define SDMA1_SDMA_POISON_INFO__VFID__SHIFT 0x4 +#define SDMA1_SDMA_POISON_INFO__VF__SHIFT 0x9 +#define SDMA1_SDMA_POISON_INFO__VMID_MASK 0x0000000FL +#define SDMA1_SDMA_POISON_INFO__VFID_MASK 0x000001F0L +#define SDMA1_SDMA_POISON_INFO__VF_MASK 0x00000200L +//SDMA1_SDMA_MEMHUB_CNTL +#define SDMA1_SDMA_MEMHUB_CNTL__SPECULATIVE_DATA_READ__SHIFT 0x0 +#define SDMA1_SDMA_MEMHUB_CNTL__SPECULATIVE_DATA_READ_MASK 0x00000003L +//SDMA1_SDMA_QUEUE0_RB_CNTL +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE0_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE0_RB_BASE +#define SDMA1_SDMA_QUEUE0_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_BASE_HI +#define SDMA1_SDMA_QUEUE0_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE0_RB_RPTR +#define SDMA1_SDMA_QUEUE0_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE0_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_WPTR +#define SDMA1_SDMA_QUEUE0_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE0_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_IB_CNTL +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE0_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE0_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE0_IB_RPTR +#define SDMA1_SDMA_QUEUE0_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE0_IB_OFFSET +#define SDMA1_SDMA_QUEUE0_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE0_IB_BASE_LO +#define SDMA1_SDMA_QUEUE0_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_IB_BASE_HI +#define SDMA1_SDMA_QUEUE0_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_IB_SIZE +#define SDMA1_SDMA_QUEUE0_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE0_DOORBELL +#define SDMA1_SDMA_QUEUE0_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE0_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE0_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE0_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE0_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE0_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE0_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE0_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE0_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE0_PREEMPT +#define SDMA1_SDMA_QUEUE0_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE0_DUMMY_REG +#define SDMA1_SDMA_QUEUE0_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE0_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE0_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE0_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE0_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE0_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE0_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_MQD_CONTROL +#define SDMA1_SDMA_QUEUE0_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE0_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE0_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE0_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE0_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE0_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE0_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE0_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_CNTL +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE1_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE1_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE1_RB_BASE +#define SDMA1_SDMA_QUEUE1_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_BASE_HI +#define SDMA1_SDMA_QUEUE1_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE1_RB_RPTR +#define SDMA1_SDMA_QUEUE1_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE1_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_WPTR +#define SDMA1_SDMA_QUEUE1_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE1_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_IB_CNTL +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE1_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE1_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE1_IB_RPTR +#define SDMA1_SDMA_QUEUE1_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE1_IB_OFFSET +#define SDMA1_SDMA_QUEUE1_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE1_IB_BASE_LO +#define SDMA1_SDMA_QUEUE1_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_IB_BASE_HI +#define SDMA1_SDMA_QUEUE1_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_IB_SIZE +#define SDMA1_SDMA_QUEUE1_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE1_DOORBELL +#define SDMA1_SDMA_QUEUE1_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE1_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE1_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE1_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE1_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE1_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE1_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE1_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE1_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE1_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE1_PREEMPT +#define SDMA1_SDMA_QUEUE1_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE1_DUMMY_REG +#define SDMA1_SDMA_QUEUE1_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE1_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE1_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE1_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE1_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE1_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE1_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE1_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_MQD_CONTROL +#define SDMA1_SDMA_QUEUE1_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE1_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE1_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE1_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE1_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE1_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE1_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE1_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_CNTL +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE2_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE2_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE2_RB_BASE +#define SDMA1_SDMA_QUEUE2_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_BASE_HI +#define SDMA1_SDMA_QUEUE2_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE2_RB_RPTR +#define SDMA1_SDMA_QUEUE2_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE2_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_WPTR +#define SDMA1_SDMA_QUEUE2_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE2_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_IB_CNTL +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE2_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE2_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE2_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE2_IB_RPTR +#define SDMA1_SDMA_QUEUE2_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE2_IB_OFFSET +#define SDMA1_SDMA_QUEUE2_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE2_IB_BASE_LO +#define SDMA1_SDMA_QUEUE2_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_IB_BASE_HI +#define SDMA1_SDMA_QUEUE2_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_IB_SIZE +#define SDMA1_SDMA_QUEUE2_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE2_DOORBELL +#define SDMA1_SDMA_QUEUE2_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE2_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE2_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE2_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE2_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE2_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE2_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE2_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE2_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE2_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE2_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE2_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE2_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE2_PREEMPT +#define SDMA1_SDMA_QUEUE2_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE2_DUMMY_REG +#define SDMA1_SDMA_QUEUE2_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE2_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE2_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE2_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE2_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE2_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE2_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE2_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE2_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE2_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_MQD_CONTROL +#define SDMA1_SDMA_QUEUE2_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE2_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE2_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE2_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE2_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE2_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE2_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE2_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_CNTL +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE3_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE3_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE3_RB_BASE +#define SDMA1_SDMA_QUEUE3_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_BASE_HI +#define SDMA1_SDMA_QUEUE3_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE3_RB_RPTR +#define SDMA1_SDMA_QUEUE3_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE3_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_WPTR +#define SDMA1_SDMA_QUEUE3_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE3_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_IB_CNTL +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE3_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE3_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE3_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE3_IB_RPTR +#define SDMA1_SDMA_QUEUE3_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE3_IB_OFFSET +#define SDMA1_SDMA_QUEUE3_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE3_IB_BASE_LO +#define SDMA1_SDMA_QUEUE3_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_IB_BASE_HI +#define SDMA1_SDMA_QUEUE3_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_IB_SIZE +#define SDMA1_SDMA_QUEUE3_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE3_DOORBELL +#define SDMA1_SDMA_QUEUE3_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE3_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE3_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE3_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE3_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE3_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE3_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE3_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE3_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE3_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE3_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE3_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE3_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE3_PREEMPT +#define SDMA1_SDMA_QUEUE3_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE3_DUMMY_REG +#define SDMA1_SDMA_QUEUE3_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE3_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE3_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE3_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE3_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE3_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE3_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE3_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE3_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE3_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_MQD_CONTROL +#define SDMA1_SDMA_QUEUE3_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE3_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE3_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE3_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE3_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE3_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE3_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE3_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_CNTL +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE4_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE4_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE4_RB_BASE +#define SDMA1_SDMA_QUEUE4_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_BASE_HI +#define SDMA1_SDMA_QUEUE4_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE4_RB_RPTR +#define SDMA1_SDMA_QUEUE4_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE4_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_WPTR +#define SDMA1_SDMA_QUEUE4_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE4_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_IB_CNTL +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE4_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE4_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE4_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE4_IB_RPTR +#define SDMA1_SDMA_QUEUE4_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE4_IB_OFFSET +#define SDMA1_SDMA_QUEUE4_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE4_IB_BASE_LO +#define SDMA1_SDMA_QUEUE4_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_IB_BASE_HI +#define SDMA1_SDMA_QUEUE4_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_IB_SIZE +#define SDMA1_SDMA_QUEUE4_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE4_DOORBELL +#define SDMA1_SDMA_QUEUE4_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE4_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE4_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE4_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE4_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE4_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE4_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE4_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE4_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE4_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE4_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE4_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE4_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE4_PREEMPT +#define SDMA1_SDMA_QUEUE4_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE4_DUMMY_REG +#define SDMA1_SDMA_QUEUE4_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE4_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE4_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE4_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE4_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE4_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE4_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE4_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE4_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE4_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_MQD_CONTROL +#define SDMA1_SDMA_QUEUE4_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE4_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE4_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE4_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE4_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE4_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE4_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE4_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_CNTL +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE5_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE5_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE5_RB_BASE +#define SDMA1_SDMA_QUEUE5_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_BASE_HI +#define SDMA1_SDMA_QUEUE5_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE5_RB_RPTR +#define SDMA1_SDMA_QUEUE5_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE5_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_WPTR +#define SDMA1_SDMA_QUEUE5_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE5_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_IB_CNTL +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE5_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE5_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE5_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE5_IB_RPTR +#define SDMA1_SDMA_QUEUE5_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE5_IB_OFFSET +#define SDMA1_SDMA_QUEUE5_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE5_IB_BASE_LO +#define SDMA1_SDMA_QUEUE5_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_IB_BASE_HI +#define SDMA1_SDMA_QUEUE5_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_IB_SIZE +#define SDMA1_SDMA_QUEUE5_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE5_DOORBELL +#define SDMA1_SDMA_QUEUE5_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE5_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE5_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE5_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE5_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE5_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE5_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE5_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE5_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE5_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE5_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE5_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE5_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE5_PREEMPT +#define SDMA1_SDMA_QUEUE5_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE5_DUMMY_REG +#define SDMA1_SDMA_QUEUE5_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE5_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE5_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE5_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE5_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE5_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE5_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE5_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE5_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE5_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_MQD_CONTROL +#define SDMA1_SDMA_QUEUE5_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE5_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE5_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE5_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE5_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE5_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE5_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE5_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_CNTL +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE6_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE6_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE6_RB_BASE +#define SDMA1_SDMA_QUEUE6_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_BASE_HI +#define SDMA1_SDMA_QUEUE6_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE6_RB_RPTR +#define SDMA1_SDMA_QUEUE6_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE6_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_WPTR +#define SDMA1_SDMA_QUEUE6_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE6_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_IB_CNTL +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE6_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE6_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE6_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE6_IB_RPTR +#define SDMA1_SDMA_QUEUE6_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE6_IB_OFFSET +#define SDMA1_SDMA_QUEUE6_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE6_IB_BASE_LO +#define SDMA1_SDMA_QUEUE6_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_IB_BASE_HI +#define SDMA1_SDMA_QUEUE6_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_IB_SIZE +#define SDMA1_SDMA_QUEUE6_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE6_DOORBELL +#define SDMA1_SDMA_QUEUE6_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE6_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE6_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE6_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE6_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE6_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE6_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE6_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE6_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE6_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE6_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE6_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE6_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE6_PREEMPT +#define SDMA1_SDMA_QUEUE6_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE6_DUMMY_REG +#define SDMA1_SDMA_QUEUE6_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE6_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE6_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE6_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE6_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE6_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE6_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE6_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE6_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE6_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_MQD_CONTROL +#define SDMA1_SDMA_QUEUE6_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE6_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE6_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE6_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE6_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE6_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE6_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE6_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_CNTL +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE7_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE7_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE7_RB_BASE +#define SDMA1_SDMA_QUEUE7_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_BASE_HI +#define SDMA1_SDMA_QUEUE7_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE7_RB_RPTR +#define SDMA1_SDMA_QUEUE7_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE7_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_WPTR +#define SDMA1_SDMA_QUEUE7_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE7_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_IB_CNTL +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE7_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE7_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE7_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE7_IB_RPTR +#define SDMA1_SDMA_QUEUE7_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE7_IB_OFFSET +#define SDMA1_SDMA_QUEUE7_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE7_IB_BASE_LO +#define SDMA1_SDMA_QUEUE7_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_IB_BASE_HI +#define SDMA1_SDMA_QUEUE7_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_IB_SIZE +#define SDMA1_SDMA_QUEUE7_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE7_DOORBELL +#define SDMA1_SDMA_QUEUE7_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE7_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE7_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE7_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE7_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE7_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE7_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE7_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE7_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE7_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE7_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE7_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE7_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE7_PREEMPT +#define SDMA1_SDMA_QUEUE7_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE7_DUMMY_REG +#define SDMA1_SDMA_QUEUE7_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE7_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE7_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE7_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE7_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE7_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE7_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE7_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE7_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE7_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_MQD_CONTROL +#define SDMA1_SDMA_QUEUE7_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE7_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE7_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE7_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE7_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE7_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE7_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE7_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_CNTL +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE8_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE8_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE8_RB_BASE +#define SDMA1_SDMA_QUEUE8_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_BASE_HI +#define SDMA1_SDMA_QUEUE8_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE8_RB_RPTR +#define SDMA1_SDMA_QUEUE8_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE8_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_WPTR +#define SDMA1_SDMA_QUEUE8_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE8_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_IB_CNTL +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE8_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE8_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE8_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE8_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE8_IB_RPTR +#define SDMA1_SDMA_QUEUE8_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE8_IB_OFFSET +#define SDMA1_SDMA_QUEUE8_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE8_IB_BASE_LO +#define SDMA1_SDMA_QUEUE8_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_IB_BASE_HI +#define SDMA1_SDMA_QUEUE8_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_IB_SIZE +#define SDMA1_SDMA_QUEUE8_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE8_DOORBELL +#define SDMA1_SDMA_QUEUE8_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE8_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE8_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE8_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE8_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE8_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE8_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE8_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE8_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE8_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE8_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE8_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE8_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE8_PREEMPT +#define SDMA1_SDMA_QUEUE8_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE8_DUMMY_REG +#define SDMA1_SDMA_QUEUE8_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE8_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE8_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE8_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE8_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE8_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE8_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE8_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE8_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE8_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_MQD_CONTROL +#define SDMA1_SDMA_QUEUE8_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE8_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE8_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE8_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE8_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE8_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE8_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE8_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_CNTL +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_ENABLE__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_SWAP_ENABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE9_RB_CNTL__MCU_WPTR_POLL_ENABLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_PRIV__SHIFT 0x17 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_VMID__SHIFT 0x18 +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_SIZE_MASK 0x0000003EL +#define SDMA1_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_ENABLE_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__WPTR_POLL_SWAP_ENABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__MCU_WPTR_POLL_ENABLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_PRIV_MASK 0x00800000L +#define SDMA1_SDMA_QUEUE9_RB_CNTL__RB_VMID_MASK 0x0F000000L +//SDMA1_SDMA_QUEUE9_RB_BASE +#define SDMA1_SDMA_QUEUE9_RB_BASE__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_BASE__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_BASE_HI +#define SDMA1_SDMA_QUEUE9_RB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL +//SDMA1_SDMA_QUEUE9_RB_RPTR +#define SDMA1_SDMA_QUEUE9_RB_RPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_RPTR_HI +#define SDMA1_SDMA_QUEUE9_RB_RPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_WPTR +#define SDMA1_SDMA_QUEUE9_RB_WPTR__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_WPTR_HI +#define SDMA1_SDMA_QUEUE9_RB_WPTR_HI__OFFSET__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_LO +#define SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_HI +#define SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_IB_CNTL +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE9_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_IB_CNTL__CMD_VMID__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_PRIV__SHIFT 0x1f +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE9_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE9_IB_CNTL__CMD_VMID_MASK 0x000F0000L +#define SDMA1_SDMA_QUEUE9_IB_CNTL__IB_PRIV_MASK 0x80000000L +//SDMA1_SDMA_QUEUE9_IB_RPTR +#define SDMA1_SDMA_QUEUE9_IB_RPTR__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_IB_RPTR__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE9_IB_OFFSET +#define SDMA1_SDMA_QUEUE9_IB_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_IB_OFFSET__OFFSET_MASK 0x003FFFFCL +//SDMA1_SDMA_QUEUE9_IB_BASE_LO +#define SDMA1_SDMA_QUEUE9_IB_BASE_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_IB_BASE_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_IB_BASE_HI +#define SDMA1_SDMA_QUEUE9_IB_BASE_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_IB_SIZE +#define SDMA1_SDMA_QUEUE9_IB_SIZE__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_IB_SIZE__SIZE_MASK 0x000FFFFFL +//SDMA1_SDMA_QUEUE9_DOORBELL +#define SDMA1_SDMA_QUEUE9_DOORBELL__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_QUEUE9_DOORBELL__CAPTURED__SHIFT 0x1e +#define SDMA1_SDMA_QUEUE9_DOORBELL__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_QUEUE9_DOORBELL__CAPTURED_MASK 0x40000000L +//SDMA1_SDMA_QUEUE9_DOORBELL_LOG +#define SDMA1_SDMA_QUEUE9_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_DOORBELL_LOG__DATA__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_DOORBELL_OFFSET +#define SDMA1_SDMA_QUEUE9_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL +//SDMA1_SDMA_QUEUE9_CSA_ADDR_LO +#define SDMA1_SDMA_QUEUE9_CSA_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_CSA_ADDR_HI +#define SDMA1_SDMA_QUEUE9_CSA_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__GLOBAL_ID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__PROCESS_ID__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__LOCAL_ID__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__GLOBAL_ID_MASK 0x00000003L +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__PROCESS_ID_MASK 0x0000001CL +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__LOCAL_ID_MASK 0x000000C0L +#define SDMA1_SDMA_QUEUE9_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK 0x0000FF00L +//SDMA1_SDMA_QUEUE9_IB_SUB_REMAIN +#define SDMA1_SDMA_QUEUE9_IB_SUB_REMAIN__SIZE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL +//SDMA1_SDMA_QUEUE9_PREEMPT +#define SDMA1_SDMA_QUEUE9_PREEMPT__IB_PREEMPT__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_PREEMPT__IB_PREEMPT_MASK 0x00000001L +//SDMA1_SDMA_QUEUE9_DUMMY_REG +#define SDMA1_SDMA_QUEUE9_DUMMY_REG__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO +#define SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI +#define SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_RB_AQL_CNTL +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE__SHIFT 0x11 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__OVERLAP_ENABLE__SHIFT 0x12 +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00010000L +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__MIDCMD_PREEMPT_DATA_RESTORE_MASK 0x00020000L +#define SDMA1_SDMA_QUEUE9_RB_AQL_CNTL__OVERLAP_ENABLE_MASK 0x00040000L +//SDMA1_SDMA_QUEUE9_MINOR_PTR_UPDATE +#define SDMA1_SDMA_QUEUE9_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L +//SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION__SHIFT 0x5 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION__SHIFT 0x6 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__RB_PREEMPT_STATUS_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__VM_HOLE_EXCEPTION_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__PAGE_EXCEPTION_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__CMD_TIMEOUT_EXCEPTION_MASK 0x00000010L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__QUEUE_HANG_EXCEPTION_MASK 0x00000020L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DOORBELL_ERROR_EXCEPTION_MASK 0x00000040L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__SRAM_ECC_EXCEPTION_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__DRAM_ECC_EXCEPTION_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE9_CONTEXT_SWITCH_STATUS__WPTR_LT_RPTR_EXCEPTION_MASK 0x00000200L +//SDMA1_SDMA_QUEUE9_MIDCMD_CNTL +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L +#define SDMA1_SDMA_QUEUE9_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA0__DATA0__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA1 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA1__DATA1__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA2 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA2__DATA2__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA3 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA3__DATA3__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA4 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA4__DATA4__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA5 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA5__DATA5__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA6 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA6__DATA6__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA7 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA7__DATA7__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA8 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA8__DATA8__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA9 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA9__DATA9__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA9__DATA9_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MIDCMD_DATA10 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA10__DATA10__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MIDCMD_DATA10__DATA10_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_UTILIZATION_LO +#define SDMA1_SDMA_QUEUE9_UTILIZATION_LO__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_UTILIZATION_LO__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_UTILIZATION_HI +#define SDMA1_SDMA_QUEUE9_UTILIZATION_HI__DATA__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_UTILIZATION_HI__DATA_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_WAIT_UNSATISFIED_THD +#define SDMA1_SDMA_QUEUE9_WAIT_UNSATISFIED_THD__THRESHOLD__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_WAIT_UNSATISFIED_THD__THRESHOLD_MASK 0x0000001FL +//SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_LO +#define SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFFCL +//SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_HI +#define SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_MQD_CONTROL +#define SDMA1_SDMA_QUEUE9_MQD_CONTROL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_MQD_CONTROL__VMID_MASK 0x0000000FL +//SDMA1_SDMA_QUEUE9_CONTEXT_STATUS +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__SELECTED__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__USE_IB__SHIFT 0x1 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__IDLE__SHIFT 0x2 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__VF_STATUS__SHIFT 0x8 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__PRIV_VIOLATION__SHIFT 0x9 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__RPTR_WB_IDLE__SHIFT 0xb +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_PENDING__SHIFT 0xc +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x10 +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__SELECTED_MASK 0x00000001L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__USE_IB_MASK 0x00000002L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__IDLE_MASK 0x00000004L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__VF_STATUS_MASK 0x00000100L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__PRIV_VIOLATION_MASK 0x00000200L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__RPTR_WB_IDLE_MASK 0x00000800L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_PENDING_MASK 0x00001000L +#define SDMA1_SDMA_QUEUE9_CONTEXT_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x00FF0000L +//SDMA1_SDMA_QUEUE9_DUMMY_REG1 +#define SDMA1_SDMA_QUEUE9_DUMMY_REG1__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_DUMMY_REG1__DUMMY_MASK 0xFFFFFFFFL +//SDMA1_SDMA_QUEUE9_DUMMY_REG2 +#define SDMA1_SDMA_QUEUE9_DUMMY_REG2__DUMMY__SHIFT 0x0 +#define SDMA1_SDMA_QUEUE9_DUMMY_REG2__DUMMY_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmahypdec:1 +//SDMA1_SDMA_VM_CTX_LO +#define SDMA1_SDMA_VM_CTX_LO__ADDR__SHIFT 0x2 +#define SDMA1_SDMA_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL +//SDMA1_SDMA_VM_CTX_HI +#define SDMA1_SDMA_VM_CTX_HI__ADDR__SHIFT 0x0 +#define SDMA1_SDMA_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL +//SDMA1_SDMA_ACTIVE_FCN_ID +#define SDMA1_SDMA_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define SDMA1_SDMA_ACTIVE_FCN_ID__VF__SHIFT 0x7 +#define SDMA1_SDMA_ACTIVE_FCN_ID__RESERVED__SHIFT 0x8 +#define SDMA1_SDMA_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL +#define SDMA1_SDMA_ACTIVE_FCN_ID__VF_MASK 0x00000080L +#define SDMA1_SDMA_ACTIVE_FCN_ID__RESERVED_MASK 0xFFFFFF00L +//SDMA1_SDMA_VM_CTX_CNTL +#define SDMA1_SDMA_VM_CTX_CNTL__PRIV__SHIFT 0x0 +#define SDMA1_SDMA_VM_CTX_CNTL__VMID__SHIFT 0x4 +#define SDMA1_SDMA_VM_CTX_CNTL__MEM_PHY__SHIFT 0x8 +#define SDMA1_SDMA_VM_CTX_CNTL__MEM_MTYPE__SHIFT 0xa +#define SDMA1_SDMA_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE__SHIFT 0x10 +#define SDMA1_SDMA_VM_CTX_CNTL__PRIV_MASK 0x00000001L +#define SDMA1_SDMA_VM_CTX_CNTL__VMID_MASK 0x000000F0L +#define SDMA1_SDMA_VM_CTX_CNTL__MEM_PHY_MASK 0x00000300L +#define SDMA1_SDMA_VM_CTX_CNTL__MEM_MTYPE_MASK 0x00000C00L +#define SDMA1_SDMA_VM_CTX_CNTL__BUSY_STATUS_REPORT_ENABLE_MASK 0x00010000L +//SDMA1_SDMA_VIRT_RESET_REQ +#define SDMA1_SDMA_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define SDMA1_SDMA_VIRT_RESET_REQ__PF__SHIFT 0x1f +#define SDMA1_SDMA_VIRT_RESET_REQ__VF_MASK 0x7FFFFFFFL +#define SDMA1_SDMA_VIRT_RESET_REQ__PF_MASK 0x80000000L +//SDMA1_SDMA_CONTEXT_REG_TYPE0 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_CNTL__SHIFT 0x0 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE__SHIFT 0x1 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_HI__SHIFT 0x2 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR__SHIFT 0x3 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_HI__SHIFT 0x4 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR__SHIFT 0x5 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_HI__SHIFT 0x6 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_LO__SHIFT 0x7 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_HI__SHIFT 0x8 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_CNTL__SHIFT 0x9 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_RPTR__SHIFT 0xa +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_OFFSET__SHIFT 0xb +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_LO__SHIFT 0xc +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_HI__SHIFT 0xd +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SIZE__SHIFT 0xe +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL__SHIFT 0xf +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_LOG__SHIFT 0x10 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_OFFSET__SHIFT 0x11 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_LO__SHIFT 0x12 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_HI__SHIFT 0x13 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_SCHEDULE_CNTL__SHIFT 0x14 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SUB_REMAIN__SHIFT 0x15 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_PREEMPT__SHIFT 0x16 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DUMMY_REG__SHIFT 0x17 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO__SHIFT 0x18 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI__SHIFT 0x19 +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_AQL_CNTL__SHIFT 0x1a +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MINOR_PTR_UPDATE__SHIFT 0x1b +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CONTEXT_SWITCH_STATUS__SHIFT 0x1e +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MIDCMD_CNTL__SHIFT 0x1f +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_CNTL_MASK 0x00000001L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_MASK 0x00000002L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_BASE_HI_MASK 0x00000004L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_MASK 0x00000008L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_HI_MASK 0x00000010L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_MASK 0x00000020L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_HI_MASK 0x00000040L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_LO_MASK 0x00000080L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_RPTR_ADDR_HI_MASK 0x00000100L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_CNTL_MASK 0x00000200L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_RPTR_MASK 0x00000400L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_OFFSET_MASK 0x00000800L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_LO_MASK 0x00001000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_BASE_HI_MASK 0x00002000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SIZE_MASK 0x00004000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_MASK 0x00008000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_LOG_MASK 0x00010000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DOORBELL_OFFSET_MASK 0x00020000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_LO_MASK 0x00040000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CSA_ADDR_HI_MASK 0x00080000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_SCHEDULE_CNTL_MASK 0x00100000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_IB_SUB_REMAIN_MASK 0x00200000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_PREEMPT_MASK 0x00400000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_DUMMY_REG_MASK 0x00800000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_LO_MASK 0x01000000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_WPTR_POLL_ADDR_HI_MASK 0x02000000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_RB_AQL_CNTL_MASK 0x04000000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MINOR_PTR_UPDATE_MASK 0x08000000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_CONTEXT_SWITCH_STATUS_MASK 0x40000000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE0__SDMA_QUEUE0_MIDCMD_CNTL_MASK 0x80000000L +//SDMA1_SDMA_CONTEXT_REG_TYPE1 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA0__SHIFT 0x0 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA1__SHIFT 0x1 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA2__SHIFT 0x2 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA3__SHIFT 0x3 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA4__SHIFT 0x4 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA5__SHIFT 0x5 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA6__SHIFT 0x6 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA7__SHIFT 0x7 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA8__SHIFT 0x8 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA9__SHIFT 0x9 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA10__SHIFT 0xa +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_LO__SHIFT 0xb +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_HI__SHIFT 0xc +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_WAIT_UNSATISFIED_THD__SHIFT 0xd +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_LO__SHIFT 0xe +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_HI__SHIFT 0xf +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_CONTROL__SHIFT 0x10 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_CONTEXT_STATUS__SHIFT 0x11 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG1__SHIFT 0x12 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG2__SHIFT 0x13 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x14 +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA0_MASK 0x00000001L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA1_MASK 0x00000002L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA2_MASK 0x00000004L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA3_MASK 0x00000008L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA4_MASK 0x00000010L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA5_MASK 0x00000020L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA6_MASK 0x00000040L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA7_MASK 0x00000080L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA8_MASK 0x00000100L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA9_MASK 0x00000200L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MIDCMD_DATA10_MASK 0x00000400L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_LO_MASK 0x00000800L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_UTILIZATION_HI_MASK 0x00001000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_WAIT_UNSATISFIED_THD_MASK 0x00002000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_LO_MASK 0x00004000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_BASE_ADDR_HI_MASK 0x00008000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_MQD_CONTROL_MASK 0x00010000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_CONTEXT_STATUS_MASK 0x00020000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG1_MASK 0x00040000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__SDMA_QUEUE0_DUMMY_REG2_MASK 0x00080000L +#define SDMA1_SDMA_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFF00000L +//SDMA1_SDMA_CONTEXT_REG_TYPE2 +#define SDMA1_SDMA_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x0 +#define SDMA1_SDMA_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PUB_REG_TYPE0 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_DEC_START__SHIFT 0x0 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_MCU_MISC_CNTL__SHIFT 0x1 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_UCODE_REV__SHIFT 0x3 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_LO__SHIFT 0x5 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_HI__SHIFT 0x6 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_POWER_CNTL__SHIFT 0xc +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CNTL__SHIFT 0xd +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CHICKEN_BITS__SHIFT 0xe +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CACHE_CNTL__SHIFT 0xf +#define SDMA1_SDMA_PUB_REG_TYPE0__RESERVED__SHIFT 0x15 +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_DEC_START_MASK 0x00000001L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_MCU_MISC_CNTL_MASK 0x00000002L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_UCODE_REV_MASK 0x00000008L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_LO_MASK 0x00000020L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_GLOBAL_TIMESTAMP_HI_MASK 0x00000040L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_POWER_CNTL_MASK 0x00001000L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CNTL_MASK 0x00002000L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CHICKEN_BITS_MASK 0x00004000L +#define SDMA1_SDMA_PUB_REG_TYPE0__SDMA_CACHE_CNTL_MASK 0x00008000L +#define SDMA1_SDMA_PUB_REG_TYPE0__RESERVED_MASK 0xFFE00000L +//SDMA1_SDMA_PUB_REG_TYPE1 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH__SHIFT 0x0 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI__SHIFT 0x1 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH__SHIFT 0x2 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROGRAM__SHIFT 0x3 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG__SHIFT 0x4 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG__SHIFT 0x5 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_CNTL1__SHIFT 0x6 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG__SHIFT 0x7 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_FREEZE__SHIFT 0x8 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM0__SHIFT 0x9 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM1__SHIFT 0xa +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_WATCHDOG_CNTL__SHIFT 0xb +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS0__SHIFT 0xc +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS1__SHIFT 0xd +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ID__SHIFT 0xe +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_VERSION__SHIFT 0xf +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG__SHIFT 0x10 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL__SHIFT 0x11 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PERMS_CNTL__SHIFT 0x12 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO__SHIFT 0x13 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI__SHIFT 0x14 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_DCC_CNTL__SHIFT 0x15 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WARMUPL2_CNTL__SHIFT 0x16 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL__SHIFT 0x17 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK__SHIFT 0x18 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_TIMEOUT__SHIFT 0x19 +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_PAGE__SHIFT 0x1a +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_EXTERNAL_FROZEN__SHIFT 0x1b +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_TRIGGER__SHIFT 0x1c +#define SDMA1_SDMA_PUB_REG_TYPE1__RESERVED__SHIFT 0x1d +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_MASK 0x00000001L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_RB_RPTR_FETCH_HI_MASK 0x00000002L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_IB_OFFSET_FETCH_MASK 0x00000004L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROGRAM_MASK 0x00000008L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS_REG_MASK 0x00000010L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS1_REG_MASK 0x00000020L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_CNTL1_MASK 0x00000040L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_HBM_PAGE_CONFIG_MASK 0x00000080L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_MASK 0x00000100L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM0_MASK 0x00000200L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_PROCESS_QUANTUM1_MASK 0x00000400L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_WATCHDOG_CNTL_MASK 0x00000800L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS0_MASK 0x00001000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_QUEUE_STATUS1_MASK 0x00002000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ID_MASK 0x00004000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_VERSION_MASK 0x00008000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_STATUS2_REG_MASK 0x00010000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_CNTL_MASK 0x00020000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PERMS_CNTL_MASK 0x00040000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_LO_MASK 0x00080000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_ATOMIC_PREOP_HI_MASK 0x00100000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_DCC_CNTL_MASK 0x00200000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WARMUPL2_CNTL_MASK 0x00400000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_CNTL_MASK 0x00800000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_WATERMK_MASK 0x01000000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_TIMEOUT_MASK 0x02000000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_UTCL1_PAGE_MASK 0x04000000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_EXTERNAL_FROZEN_MASK 0x08000000L +#define SDMA1_SDMA_PUB_REG_TYPE1__SDMA_FREEZE_TRIGGER_MASK 0x10000000L +#define SDMA1_SDMA_PUB_REG_TYPE1__RESERVED_MASK 0xE0000000L +//SDMA1_SDMA_PUB_REG_TYPE2 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_CACHE_CNTL__SHIFT 0x0 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_STATUS__SHIFT 0x1 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_STATUS__SHIFT 0x2 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0__SHIFT 0x3 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1__SHIFT 0x4 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2__SHIFT 0x5 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0__SHIFT 0x6 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1__SHIFT 0x7 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0__SHIFT 0x8 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1__SHIFT 0x9 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2__SHIFT 0xa +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG__SHIFT 0xb +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_GLOBAL_QUANTUM__SHIFT 0xc +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG__SHIFT 0xd +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0__SHIFT 0xe +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1__SHIFT 0xf +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2__SHIFT 0x10 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3__SHIFT 0x11 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_MCU_COUNTER__SHIFT 0x12 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL__SHIFT 0x13 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_RLC_CGCG_CTRL__SHIFT 0x14 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG__SHIFT 0x15 +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_AQL_STATUS__SHIFT 0x17 +#define SDMA1_SDMA_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_CACHE_CNTL_MASK 0x00000001L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_STATUS_MASK 0x00000002L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_STATUS_MASK 0x00000004L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV0_MASK 0x00000008L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV1_MASK 0x00000010L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_INV2_MASK 0x00000020L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK0_MASK 0x00000040L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_RD_XNACK1_MASK 0x00000080L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK0_MASK 0x00000100L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_UTCL1_WR_XNACK1_MASK 0x00000200L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_CHICKEN_BITS_2_MASK 0x00000400L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_STATUS3_REG_MASK 0x00000800L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_GLOBAL_QUANTUM_MASK 0x00001000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_ERROR_LOG_MASK 0x00002000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG0_MASK 0x00004000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG1_MASK 0x00008000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG2_MASK 0x00010000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_PUB_DUMMY_REG3_MASK 0x00020000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_MCU_COUNTER_MASK 0x00040000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_CRD_CNTL_MASK 0x00080000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_RLC_CGCG_CTRL_MASK 0x00100000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_GPU_IOV_VIOLATION_LOG_MASK 0x00200000L +#define SDMA1_SDMA_PUB_REG_TYPE2__SDMA_AQL_STATUS_MASK 0x00800000L +#define SDMA1_SDMA_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L +//SDMA1_SDMA_PUB_REG_TYPE3 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_TLBI_GCR_CNTL__SHIFT 0x0 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INT_STATUS__SHIFT 0x1 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2__SHIFT 0x2 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_LO__SHIFT 0x3 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_HI__SHIFT 0x4 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_SRC__SHIFT 0x5 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_CLOCK_GATING_STATUS__SHIFT 0x6 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG__SHIFT 0x7 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA__SHIFT 0x8 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR__SHIFT 0x9 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_TIMESTAMP_CNTL__SHIFT 0xa +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS5_REG__SHIFT 0xb +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_RESET_REQ__SHIFT 0xc +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_DEQUEUE_REQUEST__SHIFT 0xd +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS6_REG__SHIFT 0xe +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL__SHIFT 0xf +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS__SHIFT 0x10 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_POISON_INFO__SHIFT 0x11 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_MEMHUB_CNTL__SHIFT 0x12 +#define SDMA1_SDMA_PUB_REG_TYPE3__RESERVED__SHIFT 0x13 +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_TLBI_GCR_CNTL_MASK 0x00000001L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INT_STATUS_MASK 0x00000002L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_GPU_IOV_VIOLATION_LOG2_MASK 0x00000004L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_LO_MASK 0x00000008L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_HI_MASK 0x00000010L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_INVALID_ADDR_SRC_MASK 0x00000020L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_CLOCK_GATING_STATUS_MASK 0x00000040L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS4_REG_MASK 0x00000080L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_DATA_MASK 0x00000100L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_SCRATCH_RAM_ADDR_MASK 0x00000200L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_TIMESTAMP_CNTL_MASK 0x00000400L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS5_REG_MASK 0x00000800L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_RESET_REQ_MASK 0x00001000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_QUEUE_DEQUEUE_REQUEST_MASK 0x00002000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_STATUS6_REG_MASK 0x00004000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_CE_CTRL_MASK 0x00008000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_RAS_STATUS_MASK 0x00010000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_POISON_INFO_MASK 0x00020000L +#define SDMA1_SDMA_PUB_REG_TYPE3__SDMA_MEMHUB_CNTL_MASK 0x00040000L +#define SDMA1_SDMA_PUB_REG_TYPE3__RESERVED_MASK 0xFFF80000L +//SDMA1_SDMA_VM_CNTL +#define SDMA1_SDMA_VM_CNTL__CMD__SHIFT 0x0 +#define SDMA1_SDMA_VM_CNTL__CMD_MASK 0x0000000FL +//SDMA1_SDMA_MCU_CNTL +#define SDMA1_SDMA_MCU_CNTL__HALT__SHIFT 0x0 +#define SDMA1_SDMA_MCU_CNTL__RESET__SHIFT 0x1 +#define SDMA1_SDMA_MCU_CNTL__DBG_SELECT_BITS__SHIFT 0x2 +#define SDMA1_SDMA_MCU_CNTL__HALT_MASK 0x00000001L +#define SDMA1_SDMA_MCU_CNTL__RESET_MASK 0x00000002L +#define SDMA1_SDMA_MCU_CNTL__DBG_SELECT_BITS_MASK 0x000000FCL +//SDMA1_SDMA_IC_BASE_LO +#define SDMA1_SDMA_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define SDMA1_SDMA_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//SDMA1_SDMA_IC_BASE_HI +#define SDMA1_SDMA_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define SDMA1_SDMA_IC_BASE_HI__IC_BASE_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_IC_BASE_CNTL +#define SDMA1_SDMA_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define SDMA1_SDMA_IC_BASE_CNTL__MTYPE__SHIFT 0x4 +#define SDMA1_SDMA_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define SDMA1_SDMA_IC_BASE_CNTL__TEMPORAL_HINT__SHIFT 0x18 +#define SDMA1_SDMA_IC_BASE_CNTL__SCOPE__SHIFT 0x1c +#define SDMA1_SDMA_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define SDMA1_SDMA_IC_BASE_CNTL__MTYPE_MASK 0x00000030L +#define SDMA1_SDMA_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define SDMA1_SDMA_IC_BASE_CNTL__TEMPORAL_HINT_MASK 0x07000000L +#define SDMA1_SDMA_IC_BASE_CNTL__SCOPE_MASK 0x30000000L +//SDMA1_SDMA_IC_OP_CNTL +#define SDMA1_SDMA_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define SDMA1_SDMA_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define SDMA1_SDMA_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define SDMA1_SDMA_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define SDMA1_SDMA_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define SDMA1_SDMA_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//SDMA1_SDMA_IC_CNTL +#define SDMA1_SDMA_IC_CNTL__CID_SEL__SHIFT 0x0 +#define SDMA1_SDMA_IC_CNTL__GPA__SHIFT 0x2 +#define SDMA1_SDMA_IC_CNTL__UCODE_VF_OVERRIDE__SHIFT 0x4 +#define SDMA1_SDMA_IC_CNTL__AUTO_PRIME_ICACHE__SHIFT 0x5 +#define SDMA1_SDMA_IC_CNTL__CID_SEL_MASK 0x00000001L +#define SDMA1_SDMA_IC_CNTL__GPA_MASK 0x0000000CL +#define SDMA1_SDMA_IC_CNTL__UCODE_VF_OVERRIDE_MASK 0x00000010L +#define SDMA1_SDMA_IC_CNTL__AUTO_PRIME_ICACHE_MASK 0x00000020L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapspdec:1 +//SDMA1_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET +#define SDMA1_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET__DATA__SHIFT 0x0 +#define SDMA1_SDMA_MCU_DM_FROM_RST_ADDR_OFFSET__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfsdec:1 +//SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//SDMA1_SDMA_PERFCNT_MISC_CNTL +#define SDMA1_SDMA_PERFCNT_MISC_CNTL__CMD_OP__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_MISC_CNTL__CMD_OP_MASK 0x0000FFFFL +//SDMA1_SDMA_PERFCOUNTER0_SELECT +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER0_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER1_SELECT +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER1_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER1_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER1_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER2_SELECT +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER2_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER2_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER2_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER3_SELECT +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER3_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER3_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER3_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER4_SELECT +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER4_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER4_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER4_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER5_SELECT +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__PERF_SEL1__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE1__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE0__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER5_SELECT__CNTR_MODE0_MASK 0xF0000000L +//SDMA1_SDMA_PERFCOUNTER5_SELECT1 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL3__SHIFT 0xa +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define SDMA1_SDMA_PERFCOUNTER5_SELECT1__CNTR_MODE2_MASK 0xF0000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmaperfddec:1 +//SDMA1_SDMA_PERFCNT_PERFCOUNTER_LO +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCNT_PERFCOUNTER_HI +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define SDMA1_SDMA_PERFCNT_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//SDMA1_SDMA_PERFCOUNTER0_LO +#define SDMA1_SDMA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER0_HI +#define SDMA1_SDMA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER1_LO +#define SDMA1_SDMA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER1_HI +#define SDMA1_SDMA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER2_LO +#define SDMA1_SDMA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER2_HI +#define SDMA1_SDMA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER3_LO +#define SDMA1_SDMA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER3_HI +#define SDMA1_SDMA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER4_LO +#define SDMA1_SDMA_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER4_HI +#define SDMA1_SDMA_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER5_LO +#define SDMA1_SDMA_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SDMA1_SDMA_PERFCOUNTER5_HI +#define SDMA1_SDMA_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SDMA1_SDMA_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_sdma_sdmapwrdec:1 +//SDMA1_GFX_ICG_SDMA_CTRL +#define SDMA1_GFX_ICG_SDMA_CTRL__REG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x1 +#define SDMA1_GFX_ICG_SDMA_CTRL__PTR_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x2 +#define SDMA1_GFX_ICG_SDMA_CTRL__PIO_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x3 +#define SDMA1_GFX_ICG_SDMA_CTRL__MCU_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x4 +#define SDMA1_GFX_ICG_SDMA_CTRL__COPY_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x5 +#define SDMA1_GFX_ICG_SDMA_CTRL__SERVE_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x6 +#define SDMA1_GFX_ICG_SDMA_CTRL__CMD_FETCH_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x7 +#define SDMA1_GFX_ICG_SDMA_CTRL__GU_MEMREQ_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x8 +#define SDMA1_GFX_ICG_SDMA_CTRL__INV_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x9 +#define SDMA1_GFX_ICG_SDMA_CTRL__GU_CACHE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xa +#define SDMA1_GFX_ICG_SDMA_CTRL__IC_CACHE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xb +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xc +#define SDMA1_GFX_ICG_SDMA_CTRL__PERF_CNTR_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xd +#define SDMA1_GFX_ICG_SDMA_CTRL__CORE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xe +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0xf +#define SDMA1_GFX_ICG_SDMA_CTRL__FE_ENG_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x10 +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESEFE_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x11 +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_FE_WARMUP_MGCG_CLK_SOFT_OVERRIDE__SHIFT 0x12 +#define SDMA1_GFX_ICG_SDMA_CTRL__MGCG_CLK_HYST__SHIFT 0x18 +#define SDMA1_GFX_ICG_SDMA_CTRL__REG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000002L +#define SDMA1_GFX_ICG_SDMA_CTRL__PTR_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000004L +#define SDMA1_GFX_ICG_SDMA_CTRL__PIO_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000008L +#define SDMA1_GFX_ICG_SDMA_CTRL__MCU_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000010L +#define SDMA1_GFX_ICG_SDMA_CTRL__COPY_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000020L +#define SDMA1_GFX_ICG_SDMA_CTRL__SERVE_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000040L +#define SDMA1_GFX_ICG_SDMA_CTRL__CMD_FETCH_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000080L +#define SDMA1_GFX_ICG_SDMA_CTRL__GU_MEMREQ_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000100L +#define SDMA1_GFX_ICG_SDMA_CTRL__INV_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000200L +#define SDMA1_GFX_ICG_SDMA_CTRL__GU_CACHE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000400L +#define SDMA1_GFX_ICG_SDMA_CTRL__IC_CACHE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00000800L +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00001000L +#define SDMA1_GFX_ICG_SDMA_CTRL__PERF_CNTR_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00002000L +#define SDMA1_GFX_ICG_SDMA_CTRL__CORE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00004000L +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00008000L +#define SDMA1_GFX_ICG_SDMA_CTRL__FE_ENG_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00010000L +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_CESEFE_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00020000L +#define SDMA1_GFX_ICG_SDMA_CTRL__MEM_CHNL_FE_WARMUP_MGCG_CLK_SOFT_OVERRIDE_MASK 0x00040000L +#define SDMA1_GFX_ICG_SDMA_CTRL__MGCG_CLK_HYST_MASK 0xFF000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_grbmdec +//GRBM_CNTL +#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define GRBM_CNTL__SED_READ_TIMEOUT__SHIFT 0x10 +#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f +#define GRBM_CNTL__READ_TIMEOUT_MASK 0x0000FFFFL +#define GRBM_CNTL__SED_READ_TIMEOUT_MASK 0x0FFF0000L +#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L +//GRBM_SKEW_CNTL +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 +#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL +#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L +//GRBM_STATUS2 +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe +#define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf +#define GRBM_STATUS2__CANE_BUSY__SHIFT 0x10 +#define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 +#define GRBM_STATUS2__SDMA_SCH_RQ_PENDING__SHIFT 0x13 +#define GRBM_STATUS2__CANE_LINK_BUSY__SHIFT 0x14 +#define GRBM_STATUS2__SDMA_BUSY__SHIFT 0x15 +#define GRBM_STATUS2__SDMA0_RQ_PENDING__SHIFT 0x16 +#define GRBM_STATUS2__SDMA1_RQ_PENDING__SHIFT 0x17 +#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x1a +#define GRBM_STATUS2__TCP_BUSY__SHIFT 0x1b +#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c +#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d +#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L +#define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L +#define GRBM_STATUS2__CANE_BUSY_MASK 0x00010000L +#define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L +#define GRBM_STATUS2__SDMA_SCH_RQ_PENDING_MASK 0x00080000L +#define GRBM_STATUS2__CANE_LINK_BUSY_MASK 0x00100000L +#define GRBM_STATUS2__SDMA_BUSY_MASK 0x00200000L +#define GRBM_STATUS2__SDMA0_RQ_PENDING_MASK 0x00400000L +#define GRBM_STATUS2__SDMA1_RQ_PENDING_MASK 0x00800000L +#define GRBM_STATUS2__RLC_BUSY_MASK 0x04000000L +#define GRBM_STATUS2__TCP_BUSY_MASK 0x08000000L +#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L +#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L +#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L +//GRBM_PWR_CNTL +#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 +#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 +#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 +#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 +#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe +#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf +#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L +#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL +#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L +#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L +#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L +#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L +//GRBM_STATUS +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS__SDMA_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc +#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd +#define GRBM_STATUS__TA_BUSY__SHIFT 0xe +#define GRBM_STATUS__GE_BUSY_NO_DMA__SHIFT 0x10 +#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 +#define GRBM_STATUS__GE_BUSY__SHIFT 0x15 +#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 +#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 +#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 +#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 +#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a +#define GRBM_STATUS__ANY_ACTIVE__SHIFT 0x1b +#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c +#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d +#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e +#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL +#define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L +#define GRBM_STATUS__SDMA_RQ_PENDING_MASK 0x00000040L +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L +#define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L +#define GRBM_STATUS__TA_BUSY_MASK 0x00004000L +#define GRBM_STATUS__GE_BUSY_NO_DMA_MASK 0x00010000L +#define GRBM_STATUS__SX_BUSY_MASK 0x00100000L +#define GRBM_STATUS__GE_BUSY_MASK 0x00200000L +#define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L +#define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L +#define GRBM_STATUS__SC_BUSY_MASK 0x01000000L +#define GRBM_STATUS__PA_BUSY_MASK 0x02000000L +#define GRBM_STATUS__DB_BUSY_MASK 0x04000000L +#define GRBM_STATUS__ANY_ACTIVE_MASK 0x08000000L +#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L +#define GRBM_STATUS__CP_BUSY_MASK 0x20000000L +#define GRBM_STATUS__CB_BUSY_MASK 0x40000000L +#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L +//GRBM_STATUS_SE0 +#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE0__UTCL1_BUSY__SHIFT 0x3 +#define GRBM_STATUS_SE0__TCP_BUSY__SHIFT 0x4 +#define GRBM_STATUS_SE0__GL1CC_BUSY__SHIFT 0x5 +#define GRBM_STATUS_SE0__GL1XCC_BUSY__SHIFT 0x6 +#define GRBM_STATUS_SE0__WGS_BUSY__SHIFT 0x14 +#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE0__UTCL1_BUSY_MASK 0x00000008L +#define GRBM_STATUS_SE0__TCP_BUSY_MASK 0x00000010L +#define GRBM_STATUS_SE0__GL1CC_BUSY_MASK 0x00000020L +#define GRBM_STATUS_SE0__GL1XCC_BUSY_MASK 0x00000040L +#define GRBM_STATUS_SE0__WGS_BUSY_MASK 0x00100000L +#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS_SE1 +#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE1__UTCL1_BUSY__SHIFT 0x3 +#define GRBM_STATUS_SE1__TCP_BUSY__SHIFT 0x4 +#define GRBM_STATUS_SE1__GL1CC_BUSY__SHIFT 0x5 +#define GRBM_STATUS_SE1__GL1XCC_BUSY__SHIFT 0x6 +#define GRBM_STATUS_SE1__WGS_BUSY__SHIFT 0x14 +#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L +#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L +#define GRBM_STATUS_SE1__UTCL1_BUSY_MASK 0x00000008L +#define GRBM_STATUS_SE1__TCP_BUSY_MASK 0x00000010L +#define GRBM_STATUS_SE1__GL1CC_BUSY_MASK 0x00000020L +#define GRBM_STATUS_SE1__GL1XCC_BUSY_MASK 0x00000040L +#define GRBM_STATUS_SE1__WGS_BUSY_MASK 0x00100000L +#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L +#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L +#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L +#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L +#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L +#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L +#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L +#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L +//GRBM_STATUS3 +#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING__SHIFT 0x5 +#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING__SHIFT 0x7 +#define GRBM_STATUS3__MESPIPE0_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS3__MESPIPE1_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS3__CH_BUSY__SHIFT 0xe +#define GRBM_STATUS3__GLARB_BUSY__SHIFT 0xf +#define GRBM_STATUS3__GL1CC_BUSY__SHIFT 0x10 +#define GRBM_STATUS3__WGS_BUSY__SHIFT 0x11 +#define GRBM_STATUS3__GL1XCC_BUSY__SHIFT 0x1b +#define GRBM_STATUS3__UTCL1_BUSY__SHIFT 0x1e +#define GRBM_STATUS3__PMM_BUSY__SHIFT 0x1f +#define GRBM_STATUS3__GRBM_RLC_INTR_CREDIT_PENDING_MASK 0x00000020L +#define GRBM_STATUS3__GRBM_CPF_INTR_CREDIT_PENDING_MASK 0x00000080L +#define GRBM_STATUS3__MESPIPE0_RQ_PENDING_MASK 0x00000100L +#define GRBM_STATUS3__MESPIPE1_RQ_PENDING_MASK 0x00000200L +#define GRBM_STATUS3__CH_BUSY_MASK 0x00004000L +#define GRBM_STATUS3__GLARB_BUSY_MASK 0x00008000L +#define GRBM_STATUS3__GL1CC_BUSY_MASK 0x00010000L +#define GRBM_STATUS3__WGS_BUSY_MASK 0x00020000L +#define GRBM_STATUS3__GL1XCC_BUSY_MASK 0x08000000L +#define GRBM_STATUS3__UTCL1_BUSY_MASK 0x40000000L +#define GRBM_STATUS3__PMM_BUSY_MASK 0x80000000L +//GRBM_SOFT_RESET +#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 +#define GRBM_SOFT_RESET__SOFT_RESET_UTCL2__SHIFT 0xf +#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 +#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 +#define GRBM_SOFT_RESET__SOFT_RESET_CANE__SHIFT 0x15 +#define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT 0x17 +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1__SHIFT 0x18 +#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L +#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L +#define GRBM_SOFT_RESET__SOFT_RESET_UTCL2_MASK 0x00008000L +#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L +#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L +#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L +#define GRBM_SOFT_RESET__SOFT_RESET_CANE_MASK 0x00200000L +#define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK 0x00800000L +#define GRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK 0x01000000L +//GRBM_FAO_CNT +#define GRBM_FAO_CNT__GRBM_FAO_CNT__SHIFT 0x0 +#define GRBM_FAO_CNT__GRBM_FAO_CNT_MASK 0x0000FFFFL +//GRBM_GFX_CLKEN_CNTL +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L +//GRBM_WAIT_IDLE_CLOCKS +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL +//GRBM_READ_ERROR +#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 +#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 +#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x000FFFFCL +#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L +#define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L +#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L +//GRBM_READ_ERROR2 +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0__SHIFT 0x9 +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1__SHIFT 0xa +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2__SHIFT 0xb +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3__SHIFT 0xc +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0__SHIFT 0xd +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1__SHIFT 0xe +#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE0_MASK 0x00000200L +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE1_MASK 0x00000400L +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE2_MASK 0x00000800L +#define GRBM_READ_ERROR2__READ_REQUESTER_MESPIPE3_MASK 0x00001000L +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA0_MASK 0x00002000L +#define GRBM_READ_ERROR2__READ_REQUESTER_SDMA1_MASK 0x00004000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L +//GRBM_INT_CNTL +#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 +#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L +//GRBM_TRAP_OP +#define GRBM_TRAP_OP__RW__SHIFT 0x0 +#define GRBM_TRAP_OP__RW_MASK 0x00000001L +//GRBM_TRAP_ADDR +#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_ADDR_MSK +#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL +//GRBM_TRAP_WD +#define GRBM_TRAP_WD__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL +//GRBM_TRAP_WD_MSK +#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL +//GRBM_DSM_BYPASS +#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 +#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 +#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L +#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L +//GRBM_WRITE_ERROR +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1 +#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 +#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x7 +#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc +#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd +#define GRBM_WRITE_ERROR__TMZ__SHIFT 0x11 +#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 +#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 +#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L +#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000003CL +#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x00000F80L +#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L +#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L +#define GRBM_WRITE_ERROR__TMZ_MASK 0x00020000L +#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L +#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L +#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L +//GRBM_IOV_ERROR_FIFO +#define GRBM_IOV_ERROR_FIFO__IOV_ADDR__SHIFT 0x0 +#define GRBM_IOV_ERROR_FIFO__IOV_VFID__SHIFT 0x12 +#define GRBM_IOV_ERROR_FIFO__IOV_SSRCID__SHIFT 0x18 +#define GRBM_IOV_ERROR_FIFO__IOV_OP__SHIFT 0x1c +#define GRBM_IOV_ERROR_FIFO__IOV_VF__SHIFT 0x1d +#define GRBM_IOV_ERROR_FIFO__FIFO_OVERFLOW__SHIFT 0x1e +#define GRBM_IOV_ERROR_FIFO__READ_VALID__SHIFT 0x1f +#define GRBM_IOV_ERROR_FIFO__IOV_ADDR_MASK 0x0003FFFFL +#define GRBM_IOV_ERROR_FIFO__IOV_VFID_MASK 0x00FC0000L +#define GRBM_IOV_ERROR_FIFO__IOV_SSRCID_MASK 0x0F000000L +#define GRBM_IOV_ERROR_FIFO__IOV_OP_MASK 0x10000000L +#define GRBM_IOV_ERROR_FIFO__IOV_VF_MASK 0x20000000L +#define GRBM_IOV_ERROR_FIFO__FIFO_OVERFLOW_MASK 0x40000000L +#define GRBM_IOV_ERROR_FIFO__READ_VALID_MASK 0x80000000L +//GRBM_CHIP_REVISION +#define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 +#define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL +//GRBM_RSMU_CFG +#define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0 +#define GRBM_RSMU_CFG__QOS__SHIFT 0xc +#define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10 +#define GRBM_RSMU_CFG__DEBUG_MASK__SHIFT 0x11 +#define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL +#define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L +#define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L +#define GRBM_RSMU_CFG__DEBUG_MASK_MASK 0x00020000L +//GRBM_IH_CREDIT +#define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +#define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 +#define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +#define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L +//GRBM_PWR_CNTL2 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 +#define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L +#define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L +//GRBM_UTCL2_INVAL_RANGE_START +#define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL +//GRBM_UTCL2_INVAL_RANGE_END +#define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 +#define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL +//GRBM_RSMU_READ_ERROR +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15 +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L +#define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L +//GRBM_INVALID_PIPE +#define GRBM_INVALID_PIPE__ADDR__SHIFT 0x2 +#define GRBM_INVALID_PIPE__PIPEID__SHIFT 0x14 +#define GRBM_INVALID_PIPE__MEID__SHIFT 0x16 +#define GRBM_INVALID_PIPE__QUEUEID__SHIFT 0x18 +#define GRBM_INVALID_PIPE__SSRCID__SHIFT 0x1b +#define GRBM_INVALID_PIPE__INVALID_PIPE__SHIFT 0x1f +#define GRBM_INVALID_PIPE__ADDR_MASK 0x000FFFFCL +#define GRBM_INVALID_PIPE__PIPEID_MASK 0x00300000L +#define GRBM_INVALID_PIPE__MEID_MASK 0x00C00000L +#define GRBM_INVALID_PIPE__QUEUEID_MASK 0x07000000L +#define GRBM_INVALID_PIPE__SSRCID_MASK 0x78000000L +#define GRBM_INVALID_PIPE__INVALID_PIPE_MASK 0x80000000L +//GRBM_FENCE_RANGE0 +#define GRBM_FENCE_RANGE0__START__SHIFT 0x0 +#define GRBM_FENCE_RANGE0__END__SHIFT 0x10 +#define GRBM_FENCE_RANGE0__START_MASK 0x0000FFFFL +#define GRBM_FENCE_RANGE0__END_MASK 0xFFFF0000L +//GRBM_FENCE_RANGE1 +#define GRBM_FENCE_RANGE1__START__SHIFT 0x0 +#define GRBM_FENCE_RANGE1__END__SHIFT 0x10 +#define GRBM_FENCE_RANGE1__START_MASK 0x0000FFFFL +#define GRBM_FENCE_RANGE1__END_MASK 0xFFFF0000L +//GRBM_CHICKEN_BITS0 +#define GRBM_CHICKEN_BITS0__GRBM_SDMA0_reg_fgcg_chick_bit__SHIFT 0x0 +#define GRBM_CHICKEN_BITS0__GRBM_SDMA1_reg_fgcg_chick_bit__SHIFT 0x1 +#define GRBM_CHICKEN_BITS0__GRBM_CPG_reg_fgcg_chick_bit__SHIFT 0x2 +#define GRBM_CHICKEN_BITS0__GRBM_CPF_reg_fgcg_chick_bit__SHIFT 0x3 +#define GRBM_CHICKEN_BITS0__GRBM_UTCL2_reg_fgcg_chick_bit__SHIFT 0x5 +#define GRBM_CHICKEN_BITS0__GRBM_TARG0_mcd_reg_clken_chick_bit__SHIFT 0x6 +#define GRBM_CHICKEN_BITS0__GRBM_TARG1_targvf_reg_clken_chick_bit__SHIFT 0x7 +#define GRBM_CHICKEN_BITS0__GRBM_TARG2_targvf_reg_clken_chick_bit__SHIFT 0x8 +#define GRBM_CHICKEN_BITS0__GRBM_TARG3_targvf_reg_clken_chick_bit__SHIFT 0x9 +#define GRBM_CHICKEN_BITS0__GRBM_TARG4_targvf_reg_clken_chick_bit__SHIFT 0xa +#define GRBM_CHICKEN_BITS0__GRBM_TARG5_reg_clken_chick_bit__SHIFT 0xb +#define GRBM_CHICKEN_BITS0__GRBM_TARG6_reg_clken_chick_bit__SHIFT 0xc +#define GRBM_CHICKEN_BITS0__GRBM_TARG7_reg_clken_chick_bit__SHIFT 0xd +#define GRBM_CHICKEN_BITS0__GRBM_TARG8_reg_clken_chick_bit__SHIFT 0xe +#define GRBM_CHICKEN_BITS0__GRBM_TARG9_reg_clken_chick_bit__SHIFT 0xf +#define GRBM_CHICKEN_BITS0__GRBM_TARG10_reg_clken_chick_bit__SHIFT 0x10 +#define GRBM_CHICKEN_BITS0__GRBM_TARG11_reg_clken_chick_bit__SHIFT 0x11 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE0_reg_clken_chick_bit__SHIFT 0x12 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE1_reg_clken_chick_bit__SHIFT 0x13 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE2_reg_clken_chick_bit__SHIFT 0x14 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE3_reg_clken_chick_bit__SHIFT 0x15 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE4_reg_clken_chick_bit__SHIFT 0x16 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE5_reg_clken_chick_bit__SHIFT 0x17 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE6_reg_clken_chick_bit__SHIFT 0x18 +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE7_reg_clken_chick_bit__SHIFT 0x19 +#define GRBM_CHICKEN_BITS0__GRBM_CPC_reg_clken_chick_bit__SHIFT 0x1c +#define GRBM_CHICKEN_BITS0__GRBM_RLC_reg_clken_chick_bit__SHIFT 0x1f +#define GRBM_CHICKEN_BITS0__GRBM_SDMA0_reg_fgcg_chick_bit_MASK 0x00000001L +#define GRBM_CHICKEN_BITS0__GRBM_SDMA1_reg_fgcg_chick_bit_MASK 0x00000002L +#define GRBM_CHICKEN_BITS0__GRBM_CPG_reg_fgcg_chick_bit_MASK 0x00000004L +#define GRBM_CHICKEN_BITS0__GRBM_CPF_reg_fgcg_chick_bit_MASK 0x00000008L +#define GRBM_CHICKEN_BITS0__GRBM_UTCL2_reg_fgcg_chick_bit_MASK 0x00000020L +#define GRBM_CHICKEN_BITS0__GRBM_TARG0_mcd_reg_clken_chick_bit_MASK 0x00000040L +#define GRBM_CHICKEN_BITS0__GRBM_TARG1_targvf_reg_clken_chick_bit_MASK 0x00000080L +#define GRBM_CHICKEN_BITS0__GRBM_TARG2_targvf_reg_clken_chick_bit_MASK 0x00000100L +#define GRBM_CHICKEN_BITS0__GRBM_TARG3_targvf_reg_clken_chick_bit_MASK 0x00000200L +#define GRBM_CHICKEN_BITS0__GRBM_TARG4_targvf_reg_clken_chick_bit_MASK 0x00000400L +#define GRBM_CHICKEN_BITS0__GRBM_TARG5_reg_clken_chick_bit_MASK 0x00000800L +#define GRBM_CHICKEN_BITS0__GRBM_TARG6_reg_clken_chick_bit_MASK 0x00001000L +#define GRBM_CHICKEN_BITS0__GRBM_TARG7_reg_clken_chick_bit_MASK 0x00002000L +#define GRBM_CHICKEN_BITS0__GRBM_TARG8_reg_clken_chick_bit_MASK 0x00004000L +#define GRBM_CHICKEN_BITS0__GRBM_TARG9_reg_clken_chick_bit_MASK 0x00008000L +#define GRBM_CHICKEN_BITS0__GRBM_TARG10_reg_clken_chick_bit_MASK 0x00010000L +#define GRBM_CHICKEN_BITS0__GRBM_TARG11_reg_clken_chick_bit_MASK 0x00020000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE0_reg_clken_chick_bit_MASK 0x00040000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE1_reg_clken_chick_bit_MASK 0x00080000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE2_reg_clken_chick_bit_MASK 0x00100000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE3_reg_clken_chick_bit_MASK 0x00200000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE4_reg_clken_chick_bit_MASK 0x00400000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE5_reg_clken_chick_bit_MASK 0x00800000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE6_reg_clken_chick_bit_MASK 0x01000000L +#define GRBM_CHICKEN_BITS0__GRBM_GRBMHSE7_reg_clken_chick_bit_MASK 0x02000000L +#define GRBM_CHICKEN_BITS0__GRBM_CPC_reg_clken_chick_bit_MASK 0x10000000L +#define GRBM_CHICKEN_BITS0__GRBM_RLC_reg_clken_chick_bit_MASK 0x80000000L +//GRBM_CHICKEN_BITS1 +#define GRBM_CHICKEN_BITS1__GRBM_UTCL2MCA_reg_clken_chick_bit__SHIFT 0xd +#define GRBM_CHICKEN_BITS1__GRBM_MCA0_reg_clken_chick_bit__SHIFT 0xe +#define GRBM_CHICKEN_BITS1__GRBM_MCA1_reg_clken_chick_bit__SHIFT 0xf +#define GRBM_CHICKEN_BITS1__GRBM_MCA2_reg_clken_chick_bit__SHIFT 0x10 +#define GRBM_CHICKEN_BITS1__GRBM_MCA3_reg_clken_chick_bit__SHIFT 0x11 +#define GRBM_CHICKEN_BITS1__GRBM_MCA4_reg_clken_chick_bit__SHIFT 0x12 +#define GRBM_CHICKEN_BITS1__GRBM_MCA5_reg_clken_chick_bit__SHIFT 0x13 +#define GRBM_CHICKEN_BITS1__GRBM_MCA6_reg_clken_chick_bit__SHIFT 0x14 +#define GRBM_CHICKEN_BITS1__GRBM_MCA7_reg_clken_chick_bit__SHIFT 0x15 +#define GRBM_CHICKEN_BITS1__GRBM_MCA8_reg_clken_chick_bit__SHIFT 0x16 +#define GRBM_CHICKEN_BITS1__GRBM_MCA9_reg_clken_chick_bit__SHIFT 0x17 +#define GRBM_CHICKEN_BITS1__GRBM_MCA10_reg_clken_chick_bit__SHIFT 0x18 +#define GRBM_CHICKEN_BITS1__GRBM_UTCL2MCA_reg_clken_chick_bit_MASK 0x00002000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA0_reg_clken_chick_bit_MASK 0x00004000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA1_reg_clken_chick_bit_MASK 0x00008000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA2_reg_clken_chick_bit_MASK 0x00010000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA3_reg_clken_chick_bit_MASK 0x00020000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA4_reg_clken_chick_bit_MASK 0x00040000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA5_reg_clken_chick_bit_MASK 0x00080000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA6_reg_clken_chick_bit_MASK 0x00100000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA7_reg_clken_chick_bit_MASK 0x00200000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA8_reg_clken_chick_bit_MASK 0x00400000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA9_reg_clken_chick_bit_MASK 0x00800000L +#define GRBM_CHICKEN_BITS1__GRBM_MCA10_reg_clken_chick_bit_MASK 0x01000000L +//CC_GC_FULL_SA_UNIT_DISABLE +#define CC_GC_FULL_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 +#define CC_GC_FULL_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x03FFFF00L +//GRBM_SCRATCH_REG0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG1 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG2 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG3 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG4 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG5 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG6 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//GRBM_SCRATCH_REG7 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL +//VIOLATION_DATA_ASYNC_VF_PROG +#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID__SHIFT 0x0 +#define VIOLATION_DATA_ASYNC_VF_PROG__VFID__SHIFT 0x4 +#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR__SHIFT 0x1f +#define VIOLATION_DATA_ASYNC_VF_PROG__SSRCID_MASK 0x0000000FL +#define VIOLATION_DATA_ASYNC_VF_PROG__VFID_MASK 0x000003F0L +#define VIOLATION_DATA_ASYNC_VF_PROG__VIOLATION_ERROR_MASK 0x80000000L +//GRBM_INTF_CNTL +#define GRBM_INTF_CNTL__GRBM_BRIDGE_DISABLE__SHIFT 0x0 +#define GRBM_INTF_CNTL__GRBM_BRIDGE_DISABLE_MASK 0x00000001L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cpdec +//CP_CPC_DEBUG_CNTL +#define CP_CPC_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 +#define CP_CPC_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL +//CP_CPC_DEBUG_DATA +#define CP_CPC_DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 +#define CP_CPC_DEBUG_DATA__DEBUG_DATA_MASK 0xFFFFFFFFL +//CP_CPF_DEBUG_CNTL +#define CP_CPF_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 +#define CP_CPF_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL +//CP_CPF_DEBUG_DATA +#define CP_CPF_DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 +#define CP_CPF_DEBUG_DATA__DEBUG_DATA_MASK 0xFFFFFFFFL +//CP_CPC_STATUS +#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 +#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 +#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 +#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 +#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 +#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 +#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 +#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 +#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb +#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc +#define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe +#define CP_CPC_STATUS__GCRIU_BUSY__SHIFT 0xf +#define CP_CPC_STATUS__MES_BUSY__SHIFT 0x10 +#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT 0x11 +#define CP_CPC_STATUS__RCIU3_BUSY__SHIFT 0x12 +#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT 0x13 +#define CP_CPC_STATUS__MES_DATA_CACHE_BUSY__SHIFT 0x14 +#define CP_CPC_STATUS__MEC_DATA_CACHE_BUSY__SHIFT 0x15 +#define CP_CPC_STATUS__CANEIU_BUSY__SHIFT 0x16 +#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1d +#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1e +#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f +#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L +#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L +#define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L +#define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L +#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L +#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L +#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L +#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L +#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L +#define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L +#define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L +#define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L +#define CP_CPC_STATUS__GCRIU_BUSY_MASK 0x00008000L +#define CP_CPC_STATUS__MES_BUSY_MASK 0x00010000L +#define CP_CPC_STATUS__MES_SCRATCH_RAM_BUSY_MASK 0x00020000L +#define CP_CPC_STATUS__RCIU3_BUSY_MASK 0x00040000L +#define CP_CPC_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK 0x00080000L +#define CP_CPC_STATUS__MES_DATA_CACHE_BUSY_MASK 0x00100000L +#define CP_CPC_STATUS__MEC_DATA_CACHE_BUSY_MASK 0x00200000L +#define CP_CPC_STATUS__CANEIU_BUSY_MASK 0x00400000L +#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x20000000L +#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x40000000L +#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L +//CP_CPC_BUSY_STAT +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L +//CP_CPC_STALLED_STAT1 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 +#define CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x7 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 +#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT 0x19 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L +#define CP_CPC_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000080L +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L +#define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L +#define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L +#define CP_CPC_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK 0x02000000L +//CP_CPF_STATUS +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 +#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 +#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 +#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb +#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd +#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe +#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf +#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 +#define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 +#define CP_CPF_STATUS__RCIU_BUSY__SHIFT 0x12 +#define CP_CPF_STATUS__RCIU_GFX_BUSY__SHIFT 0x13 +#define CP_CPF_STATUS__RCIU_CMP_BUSY__SHIFT 0x14 +#define CP_CPF_STATUS__ROQ_DATA_BUSY__SHIFT 0x15 +#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY__SHIFT 0x16 +#define CP_CPF_STATUS__GCRIU_BUSY__SHIFT 0x17 +#define CP_CPF_STATUS__MES_HQD_BUSY__SHIFT 0x18 +#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a +#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c +#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e +#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x00000001L +#define CP_CPF_STATUS__CSF_BUSY_MASK 0x00000002L +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x00000010L +#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x00000020L +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x00000040L +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x00000080L +#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x00000100L +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x00000200L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x00002000L +#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x00004000L +#define CP_CPF_STATUS__HQD_BUSY_MASK 0x00008000L +#define CP_CPF_STATUS__PRT_BUSY_MASK 0x00010000L +#define CP_CPF_STATUS__UTCL2IU_BUSY_MASK 0x00020000L +#define CP_CPF_STATUS__RCIU_BUSY_MASK 0x00040000L +#define CP_CPF_STATUS__RCIU_GFX_BUSY_MASK 0x00080000L +#define CP_CPF_STATUS__RCIU_CMP_BUSY_MASK 0x00100000L +#define CP_CPF_STATUS__ROQ_DATA_BUSY_MASK 0x00200000L +#define CP_CPF_STATUS__ROQ_CE_DATA_BUSY_MASK 0x00400000L +#define CP_CPF_STATUS__GCRIU_BUSY_MASK 0x00800000L +#define CP_CPF_STATUS__MES_HQD_BUSY_MASK 0x01000000L +#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x04000000L +#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x08000000L +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000L +#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000L +#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000L +//CP_CPF_BUSY_STAT +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY__SHIFT 0x9 +#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY__SHIFT 0xa +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x00000002L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x00000004L +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x00000008L +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x00000010L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x00000020L +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x00000040L +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x00000080L +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x00000100L +#define CP_CPF_BUSY_STAT__CSF_DATA_BUSY_MASK 0x00000200L +#define CP_CPF_BUSY_STAT__CSF_CE_DATA_BUSY_MASK 0x00000400L +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x00000800L +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x00001000L +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x00002000L +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x00020000L +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x00040000L +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x00080000L +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x00100000L +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x00200000L +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x00800000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x02000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x04000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x08000000L +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000L +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000L +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000L +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000L +//CP_CPF_STALLED_STAT1 +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x7 +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x8 +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS__SHIFT 0x9 +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS__SHIFT 0xa +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE__SHIFT 0xb +#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA__SHIFT 0xc +#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE__SHIFT 0xd +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x00000001L +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x00000002L +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x00000004L +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x00000008L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x00000020L +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000040L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00000080L +#define CP_CPF_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00000100L +#define CP_CPF_STALLED_STAT1__GFX_UTCL1_WAITING_ON_TRANS_MASK 0x00000200L +#define CP_CPF_STALLED_STAT1__CMP_UTCL1_WAITING_ON_TRANS_MASK 0x00000400L +#define CP_CPF_STALLED_STAT1__RCIU_WAITING_ON_FREE_MASK 0x00000800L +#define CP_CPF_STALLED_STAT1__DATA_FETCHING_DATA_MASK 0x00001000L +#define CP_CPF_STALLED_STAT1__GCRIU_WAIT_ON_FREE_MASK 0x00002000L +//CP_CPC_BUSY_STAT2 +#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT2__MES_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT2__MES_PIPE0_DC_BUSY__SHIFT 0xe +#define CP_CPC_BUSY_STAT2__MES_PIPE1_DC_BUSY__SHIFT 0xf +#define CP_CPC_BUSY_STAT2__MES_PIPE2_DC_BUSY__SHIFT 0x10 +#define CP_CPC_BUSY_STAT2__MES_PIPE3_DC_BUSY__SHIFT 0x11 +#define CP_CPC_BUSY_STAT2__MEC1_PIPE0_DC_BUSY__SHIFT 0x12 +#define CP_CPC_BUSY_STAT2__MEC1_PIPE1_DC_BUSY__SHIFT 0x13 +#define CP_CPC_BUSY_STAT2__MEC1_PIPE2_DC_BUSY__SHIFT 0x14 +#define CP_CPC_BUSY_STAT2__MEC1_PIPE3_DC_BUSY__SHIFT 0x15 +#define CP_CPC_BUSY_STAT2__MES_LOAD_BUSY_MASK 0x00000001L +#define CP_CPC_BUSY_STAT2__MES_MUTEX_BUSY_MASK 0x00000004L +#define CP_CPC_BUSY_STAT2__MES_MESSAGE_BUSY_MASK 0x00000008L +#define CP_CPC_BUSY_STAT2__MES_TC_BUSY_MASK 0x00000080L +#define CP_CPC_BUSY_STAT2__MES_DMA_BUSY_MASK 0x00000100L +#define CP_CPC_BUSY_STAT2__MES_PIPE0_BUSY_MASK 0x00000400L +#define CP_CPC_BUSY_STAT2__MES_PIPE1_BUSY_MASK 0x00000800L +#define CP_CPC_BUSY_STAT2__MES_PIPE2_BUSY_MASK 0x00001000L +#define CP_CPC_BUSY_STAT2__MES_PIPE3_BUSY_MASK 0x00002000L +#define CP_CPC_BUSY_STAT2__MES_PIPE0_DC_BUSY_MASK 0x00004000L +#define CP_CPC_BUSY_STAT2__MES_PIPE1_DC_BUSY_MASK 0x00008000L +#define CP_CPC_BUSY_STAT2__MES_PIPE2_DC_BUSY_MASK 0x00010000L +#define CP_CPC_BUSY_STAT2__MES_PIPE3_DC_BUSY_MASK 0x00020000L +#define CP_CPC_BUSY_STAT2__MEC1_PIPE0_DC_BUSY_MASK 0x00040000L +#define CP_CPC_BUSY_STAT2__MEC1_PIPE1_DC_BUSY_MASK 0x00080000L +#define CP_CPC_BUSY_STAT2__MEC1_PIPE2_DC_BUSY_MASK 0x00100000L +#define CP_CPC_BUSY_STAT2__MEC1_PIPE3_DC_BUSY_MASK 0x00200000L +//CP_CPC_GRBM_FREE_COUNT +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +//CP_CPC_PRIV_VIOLATION_ADDR +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS__SHIFT 0x0 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP__SHIFT 0x1 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x2 +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS_MASK 0x00000001L +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP_MASK 0x00000002L +#define CP_CPC_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0xFFFFFFFCL +//CP_CPC_PRIV_VIOLATION_ADDR_HI +#define CP_CPC_PRIV_VIOLATION_ADDR_HI__PRIV_VIOLATION_ADDR__SHIFT 0x0 +#define CP_CPC_PRIV_VIOLATION_ADDR_HI__PRIV_VIOLATION_ADDR_MASK 0x000000FFL +//CP_MEC_ME1_HEADER_DUMP +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_CPC_SCRATCH_INDEX +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//CP_CPC_SCRATCH_DATA +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_CPF_GRBM_FREE_COUNT +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_CPF_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x00000007L +//CP_CPF_BUSY_STAT2 +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT2__MES_UNMAPPED_DOORBELL_BUSY__SHIFT 0x1f +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPG_BUSY_MASK 0x00000001L +#define CP_CPF_BUSY_STAT2__CP_SDMA_CPC_BUSY_MASK 0x00000002L +#define CP_CPF_BUSY_STAT2__MES_HQD_DISPATCH_BUSY_MASK 0x00001000L +#define CP_CPF_BUSY_STAT2__MES_HQD_DMA_OFFLOAD_BUSY_MASK 0x00004000L +#define CP_CPF_BUSY_STAT2__MES_HQD_MESSAGE_BUSY_MASK 0x00020000L +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_FETCHER_BUSY_MASK 0x00040000L +#define CP_CPF_BUSY_STAT2__MES_HQD_CONSUMED_RPTR_BUSY_MASK 0x00400000L +#define CP_CPF_BUSY_STAT2__MES_HQD_FETCHER_ARB_BUSY_MASK 0x00800000L +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_ALIGN_BUSY_MASK 0x01000000L +#define CP_CPF_BUSY_STAT2__MES_HQD_ROQ_PQ_BUSY_MASK 0x08000000L +#define CP_CPF_BUSY_STAT2__MES_HQD_PQ_BUSY_MASK 0x40000000L +#define CP_CPF_BUSY_STAT2__MES_UNMAPPED_DOORBELL_BUSY_MASK 0x80000000L +//CP_CPC_HALT_HYST_COUNT +#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 +#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL +//CP_STALLED_STAT3 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE__SHIFT 0x12 +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x13 +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS__SHIFT 0x14 +#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE__SHIFT 0x15 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x00000004L +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x00000008L +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x00000010L +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x00000020L +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x00000040L +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x00000080L +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x00000400L +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x00001000L +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x00002000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x00004000L +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x00008000L +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x00010000L +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00020000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_FREE_MASK 0x00040000L +#define CP_STALLED_STAT3__UTCL2IU_WAITING_ON_TAGS_MASK 0x00080000L +#define CP_STALLED_STAT3__UTCL1_WAITING_ON_TRANS_MASK 0x00100000L +#define CP_STALLED_STAT3__GCRIU_WAITING_ON_FREE_MASK 0x00200000L +//CP_STALLED_STAT1 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0__SHIFT 0x4 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1__SHIFT 0x5 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R0_MASK 0x00000010L +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_R1_MASK 0x00000020L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x00000400L +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x00000800L +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x00001000L +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00002000L +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x00004000L +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x00008000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x00800000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x01000000L +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x02000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x04000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x08000000L +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000L +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000L +//CP_STALLED_STAT2 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 +#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE__SHIFT 0x15 +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM__SHIFT 0x16 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x00000001L +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x00000002L +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x00000004L +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x00000010L +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x00000020L +#define CP_STALLED_STAT2__PFP_TO_MEQ_DDID_NOT_RDY_TO_RCV_MASK 0x00000040L +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x00000100L +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x00000200L +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x00000400L +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x00000800L +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x00001000L +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x00002000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x00004000L +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x00008000L +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00010000L +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x00020000L +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x00040000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x00080000L +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x00100000L +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_PULSE_MASK 0x00200000L +#define CP_STALLED_STAT2__QU_STALLED_ON_EOP_DONE_WR_CONFIRM_MASK 0x00400000L +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x00800000L +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x01000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x02000000L +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x04000000L +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x08000000L +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000L +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000L +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000L +//CP_BUSY_STAT +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_BUSY_STAT__PFP_DATA_CACHE_BUSY__SHIFT 0x1 +#define CP_BUSY_STAT__ME_DATA_CACHE_BUSY__SHIFT 0x2 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 +#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 +#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 +#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf +#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 +#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 +#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 +#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 +#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 +#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 +#define CP_BUSY_STAT__PFP_PIPE0_DC_BUSY__SHIFT 0x17 +#define CP_BUSY_STAT__ME_PIPE0_DC_BUSY__SHIFT 0x18 +#define CP_BUSY_STAT__PFP_PIPE1_DC_BUSY__SHIFT 0x19 +#define CP_BUSY_STAT__ME_PIPE1_DC_BUSY__SHIFT 0x1a +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x00000001L +#define CP_BUSY_STAT__PFP_DATA_CACHE_BUSY_MASK 0x00000002L +#define CP_BUSY_STAT__ME_DATA_CACHE_BUSY_MASK 0x00000004L +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x00000040L +#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x00000080L +#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x00000100L +#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x00000200L +#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x00000400L +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x00008000L +#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x00020000L +#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x00040000L +#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x00080000L +#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x00100000L +#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x00200000L +#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x00400000L +#define CP_BUSY_STAT__PFP_PIPE0_DC_BUSY_MASK 0x00800000L +#define CP_BUSY_STAT__ME_PIPE0_DC_BUSY_MASK 0x01000000L +#define CP_BUSY_STAT__PFP_PIPE1_DC_BUSY_MASK 0x02000000L +#define CP_BUSY_STAT__ME_PIPE1_DC_BUSY_MASK 0x04000000L +//CP_STAT +#define CP_STAT__ROQ_DB_BUSY__SHIFT 0x5 +#define CP_STAT__ROQ_CE_DB_BUSY__SHIFT 0x6 +#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 +#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa +#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb +#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc +#define CP_STAT__DC_BUSY__SHIFT 0xd +#define CP_STAT__UTCL2IU_BUSY__SHIFT 0xe +#define CP_STAT__PFP_BUSY__SHIFT 0xf +#define CP_STAT__MEQ_BUSY__SHIFT 0x10 +#define CP_STAT__ME_BUSY__SHIFT 0x11 +#define CP_STAT__QUERY_BUSY__SHIFT 0x12 +#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 +#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 +#define CP_STAT__DMA_BUSY__SHIFT 0x16 +#define CP_STAT__RCIU_BUSY__SHIFT 0x17 +#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 +#define CP_STAT__GCRIU_BUSY__SHIFT 0x19 +#define CP_STAT__CE_BUSY__SHIFT 0x1a +#define CP_STAT__TCIU_BUSY__SHIFT 0x1b +#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e +#define CP_STAT__CP_BUSY__SHIFT 0x1f +#define CP_STAT__ROQ_DB_BUSY_MASK 0x00000020L +#define CP_STAT__ROQ_CE_DB_BUSY_MASK 0x00000040L +#define CP_STAT__ROQ_RING_BUSY_MASK 0x00000200L +#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x00000400L +#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x00000800L +#define CP_STAT__ROQ_STATE_BUSY_MASK 0x00001000L +#define CP_STAT__DC_BUSY_MASK 0x00002000L +#define CP_STAT__UTCL2IU_BUSY_MASK 0x00004000L +#define CP_STAT__PFP_BUSY_MASK 0x00008000L +#define CP_STAT__MEQ_BUSY_MASK 0x00010000L +#define CP_STAT__ME_BUSY_MASK 0x00020000L +#define CP_STAT__QUERY_BUSY_MASK 0x00040000L +#define CP_STAT__INTERRUPT_BUSY_MASK 0x00100000L +#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x00200000L +#define CP_STAT__DMA_BUSY_MASK 0x00400000L +#define CP_STAT__RCIU_BUSY_MASK 0x00800000L +#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x01000000L +#define CP_STAT__GCRIU_BUSY_MASK 0x02000000L +#define CP_STAT__CE_BUSY_MASK 0x04000000L +#define CP_STAT__TCIU_BUSY_MASK 0x08000000L +#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000L +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000L +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000L +#define CP_STAT__CP_BUSY_MASK 0x80000000L +//CP_ME_HEADER_DUMP +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_PFP_HEADER_DUMP +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_GRBM_FREE_COUNT +#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x0000003FL +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x003F0000L +//CP_PFP_INSTR_PNTR +#define CP_PFP_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_PFP_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_ME_INSTR_PNTR +#define CP_ME_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_ME_INSTR_PNTR__INSTR_PNTR_MASK 0x0000FFFFL +//CP_CSF_STAT +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x0001FF00L +//CP_CNTX_STAT +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0x000000FFL +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x00000700L +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0x0FF00000L +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000L +//CP_ME_PREEMPTION +#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 +#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x00000001L +//CP_RB0_RPTR +#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB0_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_RPTR +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_RB_WPTR_DELAY +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0x0FFFFFFFL +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xF0000000L +//CP_RB_WPTR_POLL_CNTL +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0x0000FFFFL +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L +//CP_ROQ1_THRESHOLDS +#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0xa +#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x14 +#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0x000003FFL +#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0x000FFC00L +#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0x3FF00000L +//CP_ROQ2_THRESHOLDS +#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x0 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0xa +#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0x000003FFL +#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0x000FFC00L +//CP_STQ_THRESHOLDS +#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 +#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 +#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 +#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0x000000FFL +#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0x0000FF00L +#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0x00FF0000L +//CP_MEQ_THRESHOLDS +#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 +#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 +#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0x000000FFL +#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0x0000FF00L +//CP_ROQ_AVAIL +#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 +#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x00000FFFL +#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x0FFF0000L +//CP_STQ_AVAIL +#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 +#define CP_STQ_AVAIL__STQ_CNT_MASK 0x000003FFL +//CP_ROQ2_AVAIL +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 +#define CP_ROQ2_AVAIL__ROQ_CNT_DB__SHIFT 0x10 +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x00000FFFL +#define CP_ROQ2_AVAIL__ROQ_CNT_DB_MASK 0x0FFF0000L +//CP_MEQ_AVAIL +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x000003FFL +//CP_CMD_INDEX +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x000007FFL +#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x00003000L +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x00070000L +//CP_CMD_DATA +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 +#define CP_CMD_DATA__CMD_DATA_MASK 0xFFFFFFFFL +//CP_ROQ_RB_STAT +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x00000FFFL +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x0FFF0000L +//CP_ROQ_IB1_STAT +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x00000FFFL +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x0FFF0000L +//CP_ROQ_IB2_STAT +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x00000FFFL +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x0FFF0000L +//CP_STQ_STAT +#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 +#define CP_STQ_STAT__STQ_RPTR_MASK 0x000003FFL +//CP_STQ_WR_STAT +#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 +#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x000003FFL +//CP_MEQ_STAT +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x000003FFL +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x03FF0000L +//CP_ROQ3_THRESHOLDS +#define CP_ROQ3_THRESHOLDS__R0_DB_START__SHIFT 0x0 +#define CP_ROQ3_THRESHOLDS__R1_DB_START__SHIFT 0xa +#define CP_ROQ3_THRESHOLDS__R0_DB_START_MASK 0x000003FFL +#define CP_ROQ3_THRESHOLDS__R1_DB_START_MASK 0x000FFC00L +//CP_ROQ_DB_STAT +#define CP_ROQ_DB_STAT__ROQ_RPTR_DB__SHIFT 0x0 +#define CP_ROQ_DB_STAT__ROQ_WPTR_DB__SHIFT 0x10 +#define CP_ROQ_DB_STAT__ROQ_RPTR_DB_MASK 0x00000FFFL +#define CP_ROQ_DB_STAT__ROQ_WPTR_DB_MASK 0x0FFF0000L +//CP_INT_STAT_DEBUG +#define CP_INT_STAT_DEBUG__RESUME_INT_ASSERTED__SHIFT 0x8 +#define CP_INT_STAT_DEBUG__SUSPEND_INT_ASSERTED__SHIFT 0x9 +#define CP_INT_STAT_DEBUG__DMA_WATCH_INT_ASSERTED__SHIFT 0xa +#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_INT_STAT_DEBUG__FUE_INT_STATUS_DEBUG__SHIFT 0xf +#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12 +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 +#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_INT_STAT_DEBUG__RESUME_INT_ASSERTED_MASK 0x00000100L +#define CP_INT_STAT_DEBUG__SUSPEND_INT_ASSERTED_MASK 0x00000200L +#define CP_INT_STAT_DEBUG__DMA_WATCH_INT_ASSERTED_MASK 0x00000400L +#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x00000800L +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L +#define CP_INT_STAT_DEBUG__FUE_INT_STATUS_DEBUG_MASK 0x00008000L +#define CP_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L +#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x00040000L +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x00080000L +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x00100000L +#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x00200000L +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x00400000L +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L +//CP_DEBUG_CNTL +#define CP_DEBUG_CNTL__DEBUG_INDX__SHIFT 0x0 +#define CP_DEBUG_CNTL__DEBUG_INDX_MASK 0x0000007FL +//CP_DEBUG_DATA +#define CP_DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 +#define CP_DEBUG_DATA__DEBUG_DATA_MASK 0xFFFFFFFFL +//CP_PRIV_VIOLATION_ADDR +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS__SHIFT 0x0 +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP__SHIFT 0x1 +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR__SHIFT 0x2 +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_STATUS_MASK 0x00000001L +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_OP_MASK 0x00000002L +#define CP_PRIV_VIOLATION_ADDR__PRIV_VIOLATION_ADDR_MASK 0xFFFFFFFCL +//CP_PRIV_VIOLATION_ADDR_HI +#define CP_PRIV_VIOLATION_ADDR_HI__PRIV_VIOLATION_ADDR_HI__SHIFT 0x0 +#define CP_PRIV_VIOLATION_ADDR_HI__PRIV_VIOLATION_ADDR_HI_MASK 0x000000FFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_padec +//VGT_DMA_DATA_FIFO_DEPTH +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x000003FFL +//VGT_DMA_REQ_FIFO_DEPTH +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x0000003FL +//VGT_DRAW_INIT_FIFO_DEPTH +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x0000003FL +//VGT_MC_LAT_CNTL +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x0000000FL +//IA_UTCL1_STATUS_2 +#define IA_UTCL1_STATUS_2__FAULT_DETECTED__SHIFT 0x0 +#define IA_UTCL1_STATUS_2__RETRY_DETECTED__SHIFT 0x1 +#define IA_UTCL1_STATUS_2__PRT_DETECTED__SHIFT 0x2 +#define IA_UTCL1_STATUS_2__FAULT_VMID__SHIFT 0x4 +#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID__SHIFT 0x8 +#define IA_UTCL1_STATUS_2__FAULT_INSTANCEID__SHIFT 0xe +#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID__SHIFT 0x10 +#define IA_UTCL1_STATUS_2__RETRY_INSTANCEID__SHIFT 0x16 +#define IA_UTCL1_STATUS_2__PRT_UTCL1ID__SHIFT 0x18 +#define IA_UTCL1_STATUS_2__PRT_INSTANCEID__SHIFT 0x1e +#define IA_UTCL1_STATUS_2__FAULT_DETECTED_MASK 0x00000001L +#define IA_UTCL1_STATUS_2__RETRY_DETECTED_MASK 0x00000002L +#define IA_UTCL1_STATUS_2__PRT_DETECTED_MASK 0x00000004L +#define IA_UTCL1_STATUS_2__FAULT_VMID_MASK 0x000000F0L +#define IA_UTCL1_STATUS_2__FAULT_UTCL1ID_MASK 0x00003F00L +#define IA_UTCL1_STATUS_2__FAULT_INSTANCEID_MASK 0x0000C000L +#define IA_UTCL1_STATUS_2__RETRY_UTCL1ID_MASK 0x003F0000L +#define IA_UTCL1_STATUS_2__RETRY_INSTANCEID_MASK 0x00C00000L +#define IA_UTCL1_STATUS_2__PRT_UTCL1ID_MASK 0x3F000000L +#define IA_UTCL1_STATUS_2__PRT_INSTANCEID_MASK 0xC0000000L +//GE_WD_CNTL_STATUS +#define GE_WD_CNTL_STATUS__DIST_BUSY__SHIFT 0x0 +#define GE_WD_CNTL_STATUS__DIST_BE_BUSY__SHIFT 0x1 +#define GE_WD_CNTL_STATUS__GE_UTCL1_BUSY__SHIFT 0x2 +#define GE_WD_CNTL_STATUS__WD_TE11_BUSY__SHIFT 0x3 +#define GE_WD_CNTL_STATUS__PC_MANAGER_BUSY__SHIFT 0x4 +#define GE_WD_CNTL_STATUS__WLC_BUSY__SHIFT 0x5 +#define GE_WD_CNTL_STATUS__DIST_BUSY_MASK 0x00000001L +#define GE_WD_CNTL_STATUS__DIST_BE_BUSY_MASK 0x00000002L +#define GE_WD_CNTL_STATUS__GE_UTCL1_BUSY_MASK 0x00000004L +#define GE_WD_CNTL_STATUS__WD_TE11_BUSY_MASK 0x00000008L +#define GE_WD_CNTL_STATUS__PC_MANAGER_BUSY_MASK 0x00000010L +#define GE_WD_CNTL_STATUS__WLC_BUSY_MASK 0x00000020L +//WD_UTCL1_CNTL +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define WD_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define WD_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define WD_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define WD_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define WD_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define WD_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d +#define WD_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define WD_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define WD_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define WD_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define WD_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define WD_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define WD_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define WD_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L +//WD_UTCL1_STATUS +#define WD_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define WD_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define WD_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define WD_UTCL1_STATUS__FAULT_VMID__SHIFT 0x4 +#define WD_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define WD_UTCL1_STATUS__FAULT_INSTANCEID__SHIFT 0xe +#define WD_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define WD_UTCL1_STATUS__RETRY_INSTANCEID__SHIFT 0x16 +#define WD_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define WD_UTCL1_STATUS__PRT_INSTANCEID__SHIFT 0x1e +#define WD_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define WD_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define WD_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define WD_UTCL1_STATUS__FAULT_VMID_MASK 0x000000F0L +#define WD_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define WD_UTCL1_STATUS__FAULT_INSTANCEID_MASK 0x0000C000L +#define WD_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define WD_UTCL1_STATUS__RETRY_INSTANCEID_MASK 0x00C00000L +#define WD_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +#define WD_UTCL1_STATUS__PRT_INSTANCEID_MASK 0xC0000000L +//IA_UTCL1_CNTL +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define IA_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define IA_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define IA_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define IA_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define IA_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define IA_UTCL1_CNTL__MTYPE_OVERRIDE__SHIFT 0x1d +#define IA_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define IA_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define IA_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define IA_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define IA_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define IA_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define IA_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define IA_UTCL1_CNTL__MTYPE_OVERRIDE_MASK 0x20000000L +//IA_UTCL1_STATUS +#define IA_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define IA_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define IA_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define IA_UTCL1_STATUS__FAULT_VMID__SHIFT 0x4 +#define IA_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define IA_UTCL1_STATUS__FAULT_INSTANCEID__SHIFT 0xe +#define IA_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define IA_UTCL1_STATUS__RETRY_INSTANCEID__SHIFT 0x16 +#define IA_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define IA_UTCL1_STATUS__PRT_INSTANCEID__SHIFT 0x1e +#define IA_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define IA_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define IA_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define IA_UTCL1_STATUS__FAULT_VMID_MASK 0x000000F0L +#define IA_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define IA_UTCL1_STATUS__FAULT_INSTANCEID_MASK 0x0000C000L +#define IA_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define IA_UTCL1_STATUS__RETRY_INSTANCEID_MASK 0x00C00000L +#define IA_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +#define IA_UTCL1_STATUS__PRT_INSTANCEID_MASK 0xC0000000L +//CC_GC_SA_UNIT_DISABLE +#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 +#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x00FFFF00L +//GE_FED_STATUS +#define GE_FED_STATUS__DMA_C0_FED_ERROR__SHIFT 0x0 +#define GE_FED_STATUS__DMA_C1_FED_ERROR__SHIFT 0x1 +#define GE_FED_STATUS__TF_REQ_FED_ERROR__SHIFT 0x2 +#define GE_FED_STATUS__DMA_C0_FED_ERROR_MASK 0x00000001L +#define GE_FED_STATUS__DMA_C1_FED_ERROR_MASK 0x00000002L +#define GE_FED_STATUS__TF_REQ_FED_ERROR_MASK 0x00000004L +//GE_PRIV_CONTROL +#define GE_PRIV_CONTROL__RESERVED__SHIFT 0x0 +#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE__SHIFT 0x1 +#define GE_PRIV_CONTROL__FGCG_OVERRIDE__SHIFT 0xf +#define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE__SHIFT 0x10 +#define GE_PRIV_CONTROL__MIN_ATTR_GRPS__SHIFT 0x12 +#define GE_PRIV_CONTROL__RESERVED_MASK 0x00000001L +#define GE_PRIV_CONTROL__CLAMP_PRIMGRP_SIZE_MASK 0x000003FEL +#define GE_PRIV_CONTROL__FGCG_OVERRIDE_MASK 0x00008000L +#define GE_PRIV_CONTROL__CLAMP_HS_OFFCHIP_PER_SE_OVERRIDE_MASK 0x00010000L +#define GE_PRIV_CONTROL__MIN_ATTR_GRPS_MASK 0x003C0000L +//GE_STATUS +#define GE_STATUS__PERFCOUNTER_STATUS__SHIFT 0x0 +#define GE_STATUS__THREAD_TRACE_STATUS__SHIFT 0x1 +#define GE_STATUS__PERFCOUNTER_STATUS_MASK 0x00000001L +#define GE_STATUS__THREAD_TRACE_STATUS_MASK 0x00000002L +//VGT_GS_MAX_WAVE_ID +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_GS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//GFX_PIPE_CONTROL +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN__SHIFT 0x11 +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x00001FFFL +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x00010000L +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_STALL_EN_MASK 0x00020000L +//VGT_RESET_DEBUG +#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 +#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 +#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 +#define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE0__SHIFT 0x3 +#define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE1__SHIFT 0x4 +#define VGT_RESET_DEBUG__ENABLE_VMID_RESET_UTCL1__SHIFT 0x5 +#define VGT_RESET_DEBUG__DISABLE_PREFETCH__SHIFT 0x6 +#define VGT_RESET_DEBUG__DISABLE_SWITCH_MODE_STALL_FIX__SHIFT 0x7 +#define VGT_RESET_DEBUG__DISABLE_SENDING_MULTIPLE_SE_IN_PD__SHIFT 0x8 +#define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_ON_OFF__SHIFT 0x9 +#define VGT_RESET_DEBUG__DISABLE_PATCH_OPTIMIZATION__SHIFT 0xa +#define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_OFF_ON__SHIFT 0xb +#define VGT_RESET_DEBUG__DISABLE_MERGE_GRP_PERF_FIX__SHIFT 0xc +#define VGT_RESET_DEBUG__DISABLE_MESH_SHADER_ATTR_PACKING__SHIFT 0xd +#define VGT_RESET_DEBUG__ENABLE_SMALL_INST_PACK_ADJ_GS_OFF__SHIFT 0xe +#define VGT_RESET_DEBUG__DISABLE_PATCH_DIST_LAST_DONUT_SE_SWITCH_LOGIC__SHIFT 0xf +#define VGT_RESET_DEBUG__DISABLE_GE1_FED_OPT__SHIFT 0x10 +#define VGT_RESET_DEBUG__DISABLE_GE2_DIST_FED_OPT__SHIFT 0x11 +#define VGT_RESET_DEBUG__SPARE__SHIFT 0x12 +#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x00000001L +#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x00000002L +#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x00000004L +#define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE0_MASK 0x00000008L +#define VGT_RESET_DEBUG__DISABLE_TE11_DIST_PIPE1_MASK 0x00000010L +#define VGT_RESET_DEBUG__ENABLE_VMID_RESET_UTCL1_MASK 0x00000020L +#define VGT_RESET_DEBUG__DISABLE_PREFETCH_MASK 0x00000040L +#define VGT_RESET_DEBUG__DISABLE_SWITCH_MODE_STALL_FIX_MASK 0x00000080L +#define VGT_RESET_DEBUG__DISABLE_SENDING_MULTIPLE_SE_IN_PD_MASK 0x00000100L +#define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_ON_OFF_MASK 0x00000200L +#define VGT_RESET_DEBUG__DISABLE_PATCH_OPTIMIZATION_MASK 0x00000400L +#define VGT_RESET_DEBUG__ENABLE_DIST_STALL_TESS_OFF_ON_MASK 0x00000800L +#define VGT_RESET_DEBUG__DISABLE_MERGE_GRP_PERF_FIX_MASK 0x00001000L +#define VGT_RESET_DEBUG__DISABLE_MESH_SHADER_ATTR_PACKING_MASK 0x00002000L +#define VGT_RESET_DEBUG__ENABLE_SMALL_INST_PACK_ADJ_GS_OFF_MASK 0x00004000L +#define VGT_RESET_DEBUG__DISABLE_PATCH_DIST_LAST_DONUT_SE_SWITCH_LOGIC_MASK 0x00008000L +#define VGT_RESET_DEBUG__DISABLE_GE1_FED_OPT_MASK 0x00010000L +#define VGT_RESET_DEBUG__DISABLE_GE2_DIST_FED_OPT_MASK 0x00020000L +#define VGT_RESET_DEBUG__SPARE_MASK 0xFFFC0000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_shdec +//COMPUTE_DISPATCH_INITIATOR +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L0_INV__SHIFT 0xa +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L0_INV__SHIFT 0xb +#define COMPUTE_DISPATCH_INITIATOR__PING_PONG_EN__SHIFT 0xc +#define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT 0xd +#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe +#define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT 0xf +#define COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN__SHIFT 0x10 +#define COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN__SHIFT 0x11 +#define COMPUTE_DISPATCH_INITIATOR__INTERLEAVE_2D_EN__SHIFT 0x12 +#define COMPUTE_DISPATCH_INITIATOR__WGS_DISPATCH__SHIFT 0x13 +#define COMPUTE_DISPATCH_INITIATOR__CLUSTER_EN__SHIFT 0x14 +#define COMPUTE_DISPATCH_INITIATOR__TTRACE_QUEUE_ID__SHIFT 0x1d +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x000000C0L +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L0_INV_MASK 0x00000400L +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L0_INV_MASK 0x00000800L +#define COMPUTE_DISPATCH_INITIATOR__PING_PONG_EN_MASK 0x00001000L +#define COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK 0x00002000L +#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L +#define COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK 0x00008000L +#define COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN_MASK 0x00010000L +#define COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN_MASK 0x00020000L +#define COMPUTE_DISPATCH_INITIATOR__INTERLEAVE_2D_EN_MASK 0x00040000L +#define COMPUTE_DISPATCH_INITIATOR__WGS_DISPATCH_MASK 0x00080000L +#define COMPUTE_DISPATCH_INITIATOR__CLUSTER_EN_MASK 0x00100000L +#define COMPUTE_DISPATCH_INITIATOR__TTRACE_QUEUE_ID_MASK 0xE0000000L +//COMPUTE_DIM_X +#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Y +#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DIM_Z +#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_START_X +#define COMPUTE_START_X__START__SHIFT 0x0 +#define COMPUTE_START_X__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Y +#define COMPUTE_START_Y__START__SHIFT 0x0 +#define COMPUTE_START_Y__START_MASK 0xFFFFFFFFL +//COMPUTE_START_Z +#define COMPUTE_START_Z__START__SHIFT 0x0 +#define COMPUTE_START_Z__START_MASK 0xFFFFFFFFL +//COMPUTE_NUM_THREAD_X +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__INTERLEAVE_BITS_X__SHIFT 0xd +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x00001FFFL +#define COMPUTE_NUM_THREAD_X__INTERLEAVE_BITS_X_MASK 0x0000E000L +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Y +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Y__INTERLEAVE_BITS_Y__SHIFT 0xd +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x00001FFFL +#define COMPUTE_NUM_THREAD_Y__INTERLEAVE_BITS_Y_MASK 0x0000E000L +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_NUM_THREAD_Z +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//COMPUTE_PIPELINESTAT_ENABLE +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L +//COMPUTE_PERFCOUNT_ENABLE +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L +//COMPUTE_PGM_LO +#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 +#define COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_PGM_HI +#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__DATA_MASK 0x0001FFFFL +//COMPUTE_DISPATCH_PKT_ADDR_LO +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_PKT_ADDR_HI +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL +//COMPUTE_DISPATCH_SCRATCH_BASE_LO +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_SCRATCH_BASE_HI +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x0001FFFFL +//COMPUTE_PGM_RSRC1 +#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 +#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa +#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc +#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 +#define COMPUTE_PGM_RSRC1__WG_RR_EN__SHIFT 0x15 +#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 +#define COMPUTE_PGM_RSRC1__DISABLE_PERF__SHIFT 0x17 +#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 +#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 +#define COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a +#define COMPUTE_PGM_RSRC1__FLAT_SCRATCH_IS_NV__SHIFT 0x1b +#define COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT 0x1d +#define COMPUTE_PGM_RSRC1__MEM_ORDERED__SHIFT 0x1e +#define COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT 0x1f +#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL +#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L +#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L +#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L +#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L +#define COMPUTE_PGM_RSRC1__WG_RR_EN_MASK 0x00200000L +#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L +#define COMPUTE_PGM_RSRC1__DISABLE_PERF_MASK 0x00800000L +#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L +#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L +#define COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L +#define COMPUTE_PGM_RSRC1__FLAT_SCRATCH_IS_NV_MASK 0x08000000L +#define COMPUTE_PGM_RSRC1__WGP_MODE_MASK 0x20000000L +#define COMPUTE_PGM_RSRC1__MEM_ORDERED_MASK 0x40000000L +#define COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK 0x80000000L +//COMPUTE_PGM_RSRC2 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 +#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 +#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd +#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf +#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 +#define COMPUTE_PGM_RSRC2__WGP_TAKEOVER__SHIFT 0x1f +#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L +#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000007EL +#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L +#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L +#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L +#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L +#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L +#define COMPUTE_PGM_RSRC2__WGP_TAKEOVER_MASK 0x80000000L +//COMPUTE_VMID +#define COMPUTE_VMID__DATA__SHIFT 0x0 +#define COMPUTE_VMID__DATA_MASK 0x0000000FL +//COMPUTE_RESOURCE_LIMITS +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 +#define COMPUTE_RESOURCE_LIMITS__CLUSTER_PER_SE__SHIFT 0x1b +#define COMPUTE_RESOURCE_LIMITS__SIMD_WALK_PATTERN__SHIFT 0x1f +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L +#define COMPUTE_RESOURCE_LIMITS__CLUSTER_PER_SE_MASK 0x78000000L +#define COMPUTE_RESOURCE_LIMITS__SIMD_WALK_PATTERN_MASK 0x80000000L +//COMPUTE_TMPRING_SIZE +#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x3FFFF000L +//COMPUTE_RESTART_X +#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Y +#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_RESTART_Z +#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL +//COMPUTE_THREAD_TRACE_ENABLE +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L +//COMPUTE_MISC_RESERVED +#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 +#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x0000000FL +#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L +//COMPUTE_DISPATCH_ID +#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 +#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL +//COMPUTE_THREADGROUP_ID +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL +//COMPUTE_REQ_CTRL +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT 0x0 +#define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT 0x14 +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK 0x00000001L +#define COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +#define COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK 0x07F00000L +//COMPUTE_USER_ACCUM_0 +#define COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_USER_ACCUM_1 +#define COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_USER_ACCUM_2 +#define COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_USER_ACCUM_3 +#define COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT 0x0 +#define COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK 0x0000007FL +//COMPUTE_PGM_RSRC3 +#define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT 0x0 +#define COMPUTE_PGM_RSRC3__INST_PREF_SIZE__SHIFT 0x4 +#define COMPUTE_PGM_RSRC3__GLG_EN__SHIFT 0xd +#define COMPUTE_PGM_RSRC3__NAMED_BAR_CNT__SHIFT 0xe +#define COMPUTE_PGM_RSRC3__DYNAMIC_VGPR__SHIFT 0x11 +#define COMPUTE_PGM_RSRC3__TCP_SPLIT__SHIFT 0x12 +#define COMPUTE_PGM_RSRC3__DIDT_THROTTLE__SHIFT 0x15 +#define COMPUTE_PGM_RSRC3__IMAGE_OP__SHIFT 0x1f +#define COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK 0x0000000FL +#define COMPUTE_PGM_RSRC3__INST_PREF_SIZE_MASK 0x00000FF0L +#define COMPUTE_PGM_RSRC3__GLG_EN_MASK 0x00002000L +#define COMPUTE_PGM_RSRC3__NAMED_BAR_CNT_MASK 0x0001C000L +#define COMPUTE_PGM_RSRC3__DYNAMIC_VGPR_MASK 0x00020000L +#define COMPUTE_PGM_RSRC3__TCP_SPLIT_MASK 0x001C0000L +#define COMPUTE_PGM_RSRC3__DIDT_THROTTLE_MASK 0x00200000L +#define COMPUTE_PGM_RSRC3__IMAGE_OP_MASK 0x80000000L +//COMPUTE_DDID_INDEX +#define COMPUTE_DDID_INDEX__INDEX__SHIFT 0x0 +#define COMPUTE_DDID_INDEX__INDEX_MASK 0x000007FFL +//COMPUTE_SHADER_CHKSUM +#define COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 +#define COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL +//COMPUTE_DISPATCH_INTERLEAVE +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_1D__SHIFT 0x0 +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_X_SIZE__SHIFT 0x10 +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_Y_SIZE__SHIFT 0x15 +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_Z_SIZE__SHIFT 0x1a +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_1D_MASK 0x000003FFL +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_X_SIZE_MASK 0x001F0000L +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_Y_SIZE_MASK 0x03E00000L +#define COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_Z_SIZE_MASK 0x7C000000L +//COMPUTE_CURRENT_LOGICAL_XCC_ID +#define COMPUTE_CURRENT_LOGICAL_XCC_ID__CURRENT_LOGICAL_XCC_ID__SHIFT 0x0 +#define COMPUTE_CURRENT_LOGICAL_XCC_ID__CURRENT_LOGICAL_XCC_ID_MASK 0x0000000FL +//COMPUTE_RESTART_CG_TG_ID +#define COMPUTE_RESTART_CG_TG_ID__RESTART_CG_TG_ID__SHIFT 0x0 +#define COMPUTE_RESTART_CG_TG_ID__RESTART_CG_TG_ID_MASK 0x000FFFFFL +//COMPUTE_TG_CHUNK_SIZE +#define COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE__SHIFT 0x0 +#define COMPUTE_TG_CHUNK_SIZE__TG_CHUNK_SIZE_MASK 0x0000FFFFL +//COMPUTE_RESTORE_TG_CHUNK_SIZE +#define COMPUTE_RESTORE_TG_CHUNK_SIZE__RESTORE_TG_CHUNK_SIZE__SHIFT 0x0 +#define COMPUTE_RESTORE_TG_CHUNK_SIZE__RESTORE_TG_CHUNK_SIZE_MASK 0x0000FFFFL +//COMPUTE_SPARE_1 +#define COMPUTE_SPARE_1__SIZE__SHIFT 0x0 +#define COMPUTE_SPARE_1__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_SPARE_2 +#define COMPUTE_SPARE_2__SIZE__SHIFT 0x0 +#define COMPUTE_SPARE_2__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_PRESCALED_DIM_X +#define COMPUTE_PRESCALED_DIM_X__SIZE__SHIFT 0x0 +#define COMPUTE_PRESCALED_DIM_X__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_PRESCALED_DIM_Y +#define COMPUTE_PRESCALED_DIM_Y__SIZE__SHIFT 0x0 +#define COMPUTE_PRESCALED_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_PRESCALED_DIM_Z +#define COMPUTE_PRESCALED_DIM_Z__SIZE__SHIFT 0x0 +#define COMPUTE_PRESCALED_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//COMPUTE_DESTINATION_EN_SE0 +#define COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_DESTINATION_EN_SE1 +#define COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE1 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_DESTINATION_EN_SE2 +#define COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE2 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_DESTINATION_EN_SE3 +#define COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT 0x0 +#define COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK 0xFFFFFFFFL +//COMPUTE_STATIC_THREAD_MGMT_SE3 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE4 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE5 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE6 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE7 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_STATIC_THREAD_MGMT_SE8 +#define COMPUTE_STATIC_THREAD_MGMT_SE8__SA0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE8__SA1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE8__SA0_CU_EN_MASK 0x0000FFFFL +#define COMPUTE_STATIC_THREAD_MGMT_SE8__SA1_CU_EN_MASK 0xFFFF0000L +//COMPUTE_USER_DATA_0 +#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_1 +#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_2 +#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_3 +#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_4 +#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_5 +#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_6 +#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_7 +#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_8 +#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_9 +#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_10 +#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_11 +#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_12 +#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_13 +#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_14 +#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_15 +#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_16 +#define COMPUTE_USER_DATA_16__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_16__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_17 +#define COMPUTE_USER_DATA_17__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_17__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_18 +#define COMPUTE_USER_DATA_18__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_18__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_19 +#define COMPUTE_USER_DATA_19__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_19__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_20 +#define COMPUTE_USER_DATA_20__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_20__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_21 +#define COMPUTE_USER_DATA_21__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_21__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_22 +#define COMPUTE_USER_DATA_22__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_22__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_23 +#define COMPUTE_USER_DATA_23__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_23__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_24 +#define COMPUTE_USER_DATA_24__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_24__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_25 +#define COMPUTE_USER_DATA_25__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_25__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_26 +#define COMPUTE_USER_DATA_26__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_26__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_27 +#define COMPUTE_USER_DATA_27__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_27__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_28 +#define COMPUTE_USER_DATA_28__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_28__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_29 +#define COMPUTE_USER_DATA_29__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_29__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_30 +#define COMPUTE_USER_DATA_30__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_30__DATA_MASK 0xFFFFFFFFL +//COMPUTE_USER_DATA_31 +#define COMPUTE_USER_DATA_31__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_31__DATA_MASK 0xFFFFFFFFL +//COMPUTE_RELAUNCH +#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 +#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL +#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L +//COMPUTE_RELAUNCH_STATE_PAYLOAD +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__VGPRS__SHIFT 0x0 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__WGP_TAKEOVER__SHIFT 0x6 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__LDS_SPLIT__SHIFT 0x7 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__LDS_SIZE__SHIFT 0xa +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__TG_PER_CU__SHIFT 0x13 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__SCRATCH_EN__SHIFT 0x17 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__W32_EN__SHIFT 0x18 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__WGP_CENTRIC__SHIFT 0x19 +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__NAMED_BAR_CNT__SHIFT 0x1a +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__DYNAMIC_VGPR__SHIFT 0x1d +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__VGPRS_MASK 0x0000003FL +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__WGP_TAKEOVER_MASK 0x00000040L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__LDS_SPLIT_MASK 0x00000380L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__LDS_SIZE_MASK 0x0007FC00L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__TG_PER_CU_MASK 0x00780000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__SCRATCH_EN_MASK 0x00800000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__W32_EN_MASK 0x01000000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__WGP_CENTRIC_MASK 0x02000000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__NAMED_BAR_CNT_MASK 0x1C000000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__DYNAMIC_VGPR_MASK 0x20000000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH_STATE_PAYLOAD__IS_STATE_MASK 0x80000000L +//COMPUTE_WAVE_RESTORE_ADDR_LO +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//COMPUTE_WAVE_RESTORE_ADDR_HI +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0x01FFFFFFL +//COMPUTE_RELAUNCH2 +#define COMPUTE_RELAUNCH2__PAYLOAD__SHIFT 0x0 +#define COMPUTE_RELAUNCH2__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH2__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH2__PAYLOAD_MASK 0x3FFFFFFFL +#define COMPUTE_RELAUNCH2__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH2__IS_STATE_MASK 0x80000000L +//COMPUTE_RELAUNCH2_STATE_PAYLOAD +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM0__SHIFT 0x0 +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM1__SHIFT 0x7 +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM2__SHIFT 0xe +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM3__SHIFT 0x15 +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__BULKY__SHIFT 0x1c +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__IS_STATE__SHIFT 0x1f +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM0_MASK 0x0000007FL +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM1_MASK 0x00003F80L +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM2_MASK 0x001FC000L +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__USER_ACCUM3_MASK 0x0FE00000L +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__BULKY_MASK 0x10000000L +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__IS_EVENT_MASK 0x40000000L +#define COMPUTE_RELAUNCH2_STATE_PAYLOAD__IS_STATE_MASK 0x80000000L +//COMPUTE_DISPATCH_TUNNEL +#define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT 0x0 +#define COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK 0x00001FFFL +//COMPUTE_DISPATCH_END +#define COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 +#define COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL +//COMPUTE_NOWHERE +#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 +#define COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL +//SH_RESERVED_REG0 +#define SH_RESERVED_REG0__DATA__SHIFT 0x0 +#define SH_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//SH_RESERVED_REG1 +#define SH_RESERVED_REG1__DATA__SHIFT 0x0 +#define SH_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL +//COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE__SHIFT 0x0 +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE_RESV__SHIFT 0x7 +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE_EN__SHIFT 0x1f +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE_MASK 0x0000007FL +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE_RESV_MASK 0x7FFFFF80L +#define COMPUTE_PREALLOC_CR_DB_BUFFER_SIZE__CR_DB_OVERRIDE_EN_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_gccacdec +//GC_CAC_CTRL_1 +#define GC_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 +#define GC_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x8 +#define GC_CAC_CTRL_1__CAC_WINDOW_MASK 0x000000FFL +#define GC_CAC_CTRL_1__TDP_WINDOW_MASK 0xFFFFFF00L +//GC_CAC_CTRL_2 +#define GC_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 +#define GC_CAC_CTRL_2__GC_LCAC_ENABLE__SHIFT 0x1 +#define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x2 +#define GC_CAC_CTRL_2__TOGGLE_EN__SHIFT 0x3 +#define GC_CAC_CTRL_2__INTR_EN__SHIFT 0x4 +#define GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL__SHIFT 0x5 +#define GC_CAC_CTRL_2__SE_AGGR_ACC_EN__SHIFT 0x6 +#define GC_CAC_CTRL_2__GC_AGGR_ACC_EN__SHIFT 0xf +#define GC_CAC_CTRL_2__GC_LCAC_OVR_EN__SHIFT 0x10 +#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE__SHIFT 0x11 +#define GC_CAC_CTRL_2__CAC_INTR_MAX_HYSTERESIS__SHIFT 0x12 +#define GC_CAC_CTRL_2__CAC_TDP_AGGR_MODE__SHIFT 0x18 +#define GC_CAC_CTRL_2__LOCAL_REP_FGCG_OVERRIDE__SHIFT 0x19 +#define GC_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L +#define GC_CAC_CTRL_2__GC_LCAC_ENABLE_MASK 0x00000002L +#define GC_CAC_CTRL_2__GC_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000004L +#define GC_CAC_CTRL_2__TOGGLE_EN_MASK 0x00000008L +#define GC_CAC_CTRL_2__INTR_EN_MASK 0x00000010L +#define GC_CAC_CTRL_2__CAC_COUNTER_SNAP_SEL_MASK 0x00000020L +#define GC_CAC_CTRL_2__SE_AGGR_ACC_EN_MASK 0x00007FC0L +#define GC_CAC_CTRL_2__GC_AGGR_ACC_EN_MASK 0x00008000L +#define GC_CAC_CTRL_2__GC_LCAC_OVR_EN_MASK 0x00010000L +#define GC_CAC_CTRL_2__CAC_SOFT_CTRL_ENABLE_MASK 0x00020000L +#define GC_CAC_CTRL_2__CAC_INTR_MAX_HYSTERESIS_MASK 0x00FC0000L +#define GC_CAC_CTRL_2__CAC_TDP_AGGR_MODE_MASK 0x01000000L +#define GC_CAC_CTRL_2__LOCAL_REP_FGCG_OVERRIDE_MASK 0x02000000L +//GC_CAC_AGGR_LOWER +#define GC_CAC_AGGR_LOWER__GC_AGGR_31_0__SHIFT 0x0 +#define GC_CAC_AGGR_LOWER__GC_AGGR_31_0_MASK 0xFFFFFFFFL +//GC_CAC_AGGR_UPPER +#define GC_CAC_AGGR_UPPER__GC_AGGR_63_32__SHIFT 0x0 +#define GC_CAC_AGGR_UPPER__GC_AGGR_63_32_MASK 0xFFFFFFFFL +//SE0_CAC_AGGR_LOWER +#define SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0__SHIFT 0x0 +#define SE0_CAC_AGGR_LOWER__SE0_AGGR_31_0_MASK 0xFFFFFFFFL +//SE0_CAC_AGGR_UPPER +#define SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32__SHIFT 0x0 +#define SE0_CAC_AGGR_UPPER__SE0_AGGR_63_32_MASK 0xFFFFFFFFL +//SE1_CAC_AGGR_LOWER +#define SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0__SHIFT 0x0 +#define SE1_CAC_AGGR_LOWER__SE1_AGGR_31_0_MASK 0xFFFFFFFFL +//SE1_CAC_AGGR_UPPER +#define SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32__SHIFT 0x0 +#define SE1_CAC_AGGR_UPPER__SE1_AGGR_63_32_MASK 0xFFFFFFFFL +//GC_CAC_AGGR_GFXCLK_CYCLE +#define GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define GC_CAC_AGGR_GFXCLK_CYCLE__GC_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//SE0_CAC_AGGR_GFXCLK_CYCLE +#define SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define SE0_CAC_AGGR_GFXCLK_CYCLE__SE0_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//SE1_CAC_AGGR_GFXCLK_CYCLE +#define SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE__SHIFT 0x0 +#define SE1_CAC_AGGR_GFXCLK_CYCLE__SE1_AGGR_GFXCLK_CYCLE_MASK 0xFFFFFFFFL +//GC_CAC_OVR_VAL_LOWER +#define GC_CAC_OVR_VAL_LOWER__GC_LCAC_OVR_VAL_LOWER__SHIFT 0x0 +#define GC_CAC_OVR_VAL_LOWER__GC_LCAC_OVR_VAL_LOWER_MASK 0xFFFFFFFFL +//GC_CAC_OVR_VAL_UPPER +#define GC_CAC_OVR_VAL_UPPER__GC_LCAC_OVR_VAL_UPPER__SHIFT 0x0 +#define GC_CAC_OVR_VAL_UPPER__GC_LCAC_OVR_VAL_UPPER_MASK 0xFFFFFFFFL +//GC_EDC_CTRL +#define GC_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define GC_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0xa +#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0xb +#define GC_EDC_CTRL__EDC_LEVEL_SEL__SHIFT 0xf +#define GC_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT 0x10 +#define GC_EDC_CTRL__EDC_AVGDIV__SHIFT 0x11 +#define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL__SHIFT 0x15 +#define GC_EDC_CTRL__THROTTLE_SRC0_MASK__SHIFT 0x18 +#define GC_EDC_CTRL__THROTTLE_SRC1_MASK__SHIFT 0x19 +#define GC_EDC_CTRL__THROTTLE_SRC2_MASK__SHIFT 0x1a +#define GC_EDC_CTRL__THROTTLE_SRC3_MASK__SHIFT 0x1b +#define GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS__SHIFT 0x1c +#define GC_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define GC_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define GC_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000003F0L +#define GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00000400L +#define GC_EDC_CTRL__EDC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00007800L +#define GC_EDC_CTRL__EDC_LEVEL_SEL_MASK 0x00008000L +#define GC_EDC_CTRL__EDC_ALGORITHM_MODE_MASK 0x00010000L +#define GC_EDC_CTRL__EDC_AVGDIV_MASK 0x001E0000L +#define GC_EDC_CTRL__PSM_THROTTLE_SRC_SEL_MASK 0x00E00000L +#define GC_EDC_CTRL__THROTTLE_SRC0_MASK_MASK 0x01000000L +#define GC_EDC_CTRL__THROTTLE_SRC1_MASK_MASK 0x02000000L +#define GC_EDC_CTRL__THROTTLE_SRC2_MASK_MASK 0x04000000L +#define GC_EDC_CTRL__THROTTLE_SRC3_MASK_MASK 0x08000000L +#define GC_EDC_CTRL__EDC_CREDIT_SHIFT_BIT_NUMS_MASK 0xF0000000L +//GC_EDC_STRETCH_CTRL +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN__SHIFT 0x0 +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY__SHIFT 0x1 +#define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY__SHIFT 0xa +#define GC_EDC_STRETCH_CTRL__ROLLING_POWER_MODE__SHIFT 0x13 +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_EN_MASK 0x00000001L +#define GC_EDC_STRETCH_CTRL__EDC_STRETCH_DELAY_MASK 0x000003FEL +#define GC_EDC_STRETCH_CTRL__EDC_UNSTRETCH_DELAY_MASK 0x0007FC00L +#define GC_EDC_STRETCH_CTRL__ROLLING_POWER_MODE_MASK 0x00080000L +//GC_EDC_THRESHOLD_LO +#define GC_EDC_THRESHOLD_LO__EDC_THRESHOLD_LO__SHIFT 0x0 +#define GC_EDC_THRESHOLD_LO__EDC_THRESHOLD_LO_MASK 0xFFFFFFFFL +//GC_EDC_THRESHOLD_HI +#define GC_EDC_THRESHOLD_HI__EDC_THRESHOLD_HI__SHIFT 0x0 +#define GC_EDC_THRESHOLD_HI__EDC_THRESHOLD_HI_MASK 0xFFFFFFFFL +//GC_EDC_STRETCH_THRESHOLD_LO +#define GC_EDC_STRETCH_THRESHOLD_LO__EDC_STRETCH_THRESHOLD_LO__SHIFT 0x0 +#define GC_EDC_STRETCH_THRESHOLD_LO__EDC_STRETCH_THRESHOLD_LO_MASK 0xFFFFFFFFL +//GC_EDC_STRETCH_THRESHOLD_HI +#define GC_EDC_STRETCH_THRESHOLD_HI__EDC_STRETCH_THRESHOLD_HI__SHIFT 0x0 +#define GC_EDC_STRETCH_THRESHOLD_HI__EDC_STRETCH_THRESHOLD_HI_MASK 0xFFFFFFFFL +//EDC_HYSTERESIS_CNTL +#define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS__SHIFT 0x0 +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER__SHIFT 0x8 +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN__SHIFT 0x10 +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE__SHIFT 0x11 +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE__SHIFT 0x14 +#define EDC_HYSTERESIS_CNTL__MAX_HYSTERESIS_MASK 0x000000FFL +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_TIMER_MASK 0x0000FF00L +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_EN_MASK 0x00010000L +#define EDC_HYSTERESIS_CNTL__PATTERN_EXTEND_MODE_MASK 0x000E0000L +#define EDC_HYSTERESIS_CNTL__EDC_AGGR_MODE_MASK 0x00100000L +//GC_THROTTLE_CTRL +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST__SHIFT 0x0 +#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN__SHIFT 0x1 +#define GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT 0x2 +#define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL__SHIFT 0x3 +#define GC_THROTTLE_CTRL__PCC_STALL_EN__SHIFT 0x4 +#define GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT 0x5 +#define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE__SHIFT 0x6 +#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE__SHIFT 0x7 +#define GC_THROTTLE_CTRL__PCC_OVERRIDE__SHIFT 0x8 +#define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE__SHIFT 0x9 +#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN__SHIFT 0xa +#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN__SHIFT 0xb +#define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN__SHIFT 0xc +#define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT 0xd +#define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN__SHIFT 0x17 +#define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX__SHIFT 0x18 +#define GC_THROTTLE_CTRL__LUT_HW_UPDATE__SHIFT 0x1d +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE__SHIFT 0x1e +#define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL__SHIFT 0x1f +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_SW_RST_MASK 0x00000001L +#define GC_THROTTLE_CTRL__GC_EDC_STALL_EN_MASK 0x00000002L +#define GC_THROTTLE_CTRL__PWRBRK_STALL_EN_MASK 0x00000004L +#define GC_THROTTLE_CTRL__PWRBRK_POLARITY_CNTL_MASK 0x00000008L +#define GC_THROTTLE_CTRL__PCC_STALL_EN_MASK 0x00000010L +#define GC_THROTTLE_CTRL__PATTERN_MODE_MASK 0x00000020L +#define GC_THROTTLE_CTRL__GC_EDC_ONLY_MODE_MASK 0x00000040L +#define GC_THROTTLE_CTRL__GC_EDC_OVERRIDE_MASK 0x00000080L +#define GC_THROTTLE_CTRL__PCC_OVERRIDE_MASK 0x00000100L +#define GC_THROTTLE_CTRL__PWRBRK_OVERRIDE_MASK 0x00000200L +#define GC_THROTTLE_CTRL__GC_EDC_PERF_COUNTER_EN_MASK 0x00000400L +#define GC_THROTTLE_CTRL__PCC_PERF_COUNTER_EN_MASK 0x00000800L +#define GC_THROTTLE_CTRL__PWRBRK_PERF_COUNTER_EN_MASK 0x00001000L +#define GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL_MASK 0x007FE000L +#define GC_THROTTLE_CTRL__FIXED_PATTERN_PERF_COUNTER_EN_MASK 0x00800000L +#define GC_THROTTLE_CTRL__FIXED_PATTERN_LOG_INDEX_MASK 0x1F000000L +#define GC_THROTTLE_CTRL__LUT_HW_UPDATE_MASK 0x20000000L +#define GC_THROTTLE_CTRL__THROTTLE_CTRL_CLK_EN_OVERRIDE_MASK 0x40000000L +#define GC_THROTTLE_CTRL__PCC_POLARITY_CNTL_MASK 0x80000000L +//GC_THROTTLE_CTRL1 +#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN__SHIFT 0x0 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP__SHIFT 0x1 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP__SHIFT 0x5 +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa +#define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN__SHIFT 0xd +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP__SHIFT 0xe +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP__SHIFT 0x12 +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0x17 +#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT__SHIFT 0x1a +#define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN__SHIFT 0x1e +#define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN__SHIFT 0x1f +#define GC_THROTTLE_CTRL1__PCC_FP_PROGRAM_STEP_EN_MASK 0x00000001L +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MIN_STEP_MASK 0x0000001EL +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_MAX_STEP_MASK 0x000003E0L +#define GC_THROTTLE_CTRL1__PCC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L +#define GC_THROTTLE_CTRL1__PWRBRK_FP_PROGRAM_STEP_EN_MASK 0x00002000L +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MIN_STEP_MASK 0x0003C000L +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_MAX_STEP_MASK 0x007C0000L +#define GC_THROTTLE_CTRL1__PWRBRK_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x03800000L +#define GC_THROTTLE_CTRL1__FIXED_PATTERN_SELECT_MASK 0x0C000000L +#define GC_THROTTLE_CTRL1__GC_EDC_STRETCH_PERF_COUNTER_EN_MASK 0x40000000L +#define GC_THROTTLE_CTRL1__GC_EDC_UNSTRETCH_PERF_COUNTER_EN_MASK 0x80000000L +//GC_THROTTLE_CTRL2 +#define GC_THROTTLE_CTRL2__EDC_FP_PROGRAM_STEP_EN__SHIFT 0x0 +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_MIN_STEP__SHIFT 0x1 +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_MAX_STEP__SHIFT 0x5 +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_UPWARDS_STEP_SIZE__SHIFT 0xa +#define GC_THROTTLE_CTRL2__PATTERN_COUNTER_NO_RESTART__SHIFT 0xd +#define GC_THROTTLE_CTRL2__EDC_THROTTLE_LEVEL_COUNTER_EN__SHIFT 0xe +#define GC_THROTTLE_CTRL2__EDC_POWER_DELTA_ALGO2_EN__SHIFT 0xf +#define GC_THROTTLE_CTRL2__EDC_FP_PROGRAM_STEP_EN_MASK 0x00000001L +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_MIN_STEP_MASK 0x0000001EL +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_MAX_STEP_MASK 0x000003E0L +#define GC_THROTTLE_CTRL2__EDC_PROGRAM_UPWARDS_STEP_SIZE_MASK 0x00001C00L +#define GC_THROTTLE_CTRL2__PATTERN_COUNTER_NO_RESTART_MASK 0x00002000L +#define GC_THROTTLE_CTRL2__EDC_THROTTLE_LEVEL_COUNTER_EN_MASK 0x00004000L +#define GC_THROTTLE_CTRL2__EDC_POWER_DELTA_ALGO2_EN_MASK 0x00008000L +//EDC_STALL_PATTERN_CTRL +#define EDC_STALL_PATTERN_CTRL__EDC_STEP_INTERVAL__SHIFT 0x0 +#define EDC_STALL_PATTERN_CTRL__EDC_BEGIN_STEP__SHIFT 0xa +#define EDC_STALL_PATTERN_CTRL__EDC_END_STEP__SHIFT 0xf +#define EDC_STALL_PATTERN_CTRL__EDC_DITHER_MODE__SHIFT 0x14 +#define EDC_STALL_PATTERN_CTRL__EDC_STEP_INTERVAL_MASK 0x000003FFL +#define EDC_STALL_PATTERN_CTRL__EDC_BEGIN_STEP_MASK 0x00007C00L +#define EDC_STALL_PATTERN_CTRL__EDC_END_STEP_MASK 0x000F8000L +#define EDC_STALL_PATTERN_CTRL__EDC_DITHER_MODE_MASK 0x00100000L +//PCC_STALL_PATTERN_CTRL +#define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL__SHIFT 0x0 +#define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP__SHIFT 0xa +#define PCC_STALL_PATTERN_CTRL__PCC_END_STEP__SHIFT 0xf +#define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR__SHIFT 0x18 +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR__SHIFT 0x19 +#define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE__SHIFT 0x1a +#define PCC_STALL_PATTERN_CTRL__PCC_STEP_INTERVAL_MASK 0x000003FFL +#define PCC_STALL_PATTERN_CTRL__PCC_BEGIN_STEP_MASK 0x00007C00L +#define PCC_STALL_PATTERN_CTRL__PCC_END_STEP_MASK 0x000F8000L +#define PCC_STALL_PATTERN_CTRL__PCC_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_INCR_MASK 0x01000000L +#define PCC_STALL_PATTERN_CTRL__PCC_INST_THROT_DECR_MASK 0x02000000L +#define PCC_STALL_PATTERN_CTRL__PCC_DITHER_MODE_MASK 0x04000000L +//PWRBRK_STALL_PATTERN_CTRL +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT 0xa +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT 0xf +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT 0x14 +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL_MASK 0x000003FFL +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP_MASK 0x00007C00L +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP_MASK 0x000F8000L +#define PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS_MASK 0x00F00000L +//EDC_STALL_PATTERN_1_2 +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +//EDC_STALL_PATTERN_3_4 +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +//EDC_STALL_PATTERN_5_6 +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +//EDC_STALL_PATTERN_7 +#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_0__SHIFT 0x10 +#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +#define EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_0_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_1_2 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1__SHIFT 0x0 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2__SHIFT 0x10 +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_1_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_1_2__PCC_STALL_PATTERN_2_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_3_4 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3__SHIFT 0x0 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4__SHIFT 0x10 +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_3_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_3_4__PCC_STALL_PATTERN_4_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_5_6 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5__SHIFT 0x0 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6__SHIFT 0x10 +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_5_MASK 0x00007FFFL +#define PCC_STALL_PATTERN_5_6__PCC_STALL_PATTERN_6_MASK 0x7FFF0000L +//PCC_STALL_PATTERN_7 +#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7__SHIFT 0x0 +#define PCC_STALL_PATTERN_7__PCC_STALL_PATTERN_7_MASK 0x00007FFFL +//PWRBRK_STALL_PATTERN_1_2 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_1_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_1_2__PWRBRK_STALL_PATTERN_2_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_3_4 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_3_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_3_4__PWRBRK_STALL_PATTERN_4_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_5_6 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6__SHIFT 0x10 +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_5_MASK 0x00007FFFL +#define PWRBRK_STALL_PATTERN_5_6__PWRBRK_STALL_PATTERN_6_MASK 0x7FFF0000L +//PWRBRK_STALL_PATTERN_7 +#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7__SHIFT 0x0 +#define PWRBRK_STALL_PATTERN_7__PWRBRK_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_STALL_PATTERN_CTRL +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN__SHIFT 0x0 +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST__SHIFT 0x1 +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT 0x3 +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN__SHIFT 0x7 +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE__SHIFT 0x8 +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_STRETCH_EN__SHIFT 0xb +#define DIDT_STALL_PATTERN_CTRL__DIDT_MAX_HYSTERESIS__SHIFT 0xc +#define DIDT_STALL_PATTERN_CTRL__DIDT_PERF_COUNTER_EN__SHIFT 0x14 +#define DIDT_STALL_PATTERN_CTRL__PSM_DIDT_THROTTLE_SRC_SEL__SHIFT 0x15 +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC0_MASK__SHIFT 0x18 +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC1_MASK__SHIFT 0x19 +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC2_MASK__SHIFT 0x1a +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC3_MASK__SHIFT 0x1b +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CTRL_EN_MASK 0x00000001L +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_SW_RST_MASK 0x00000002L +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_STALL_PATTERN_CTRL__DIDT_STALL_PATTERN_BIT_NUMS_MASK 0x00000078L +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_EN_MASK 0x00000080L +#define DIDT_STALL_PATTERN_CTRL__DIDT_PATTERN_EXTEND_MODE_MASK 0x00000700L +#define DIDT_STALL_PATTERN_CTRL__DIDT_DROOP_STRETCH_EN_MASK 0x00000800L +#define DIDT_STALL_PATTERN_CTRL__DIDT_MAX_HYSTERESIS_MASK 0x000FF000L +#define DIDT_STALL_PATTERN_CTRL__DIDT_PERF_COUNTER_EN_MASK 0x00100000L +#define DIDT_STALL_PATTERN_CTRL__PSM_DIDT_THROTTLE_SRC_SEL_MASK 0x00E00000L +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC0_MASK_MASK 0x01000000L +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC1_MASK_MASK 0x02000000L +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC2_MASK_MASK 0x04000000L +#define DIDT_STALL_PATTERN_CTRL__DIDT_THROTTLE_SRC3_MASK_MASK 0x08000000L +//DIDT_STALL_PATTERN_1_2 +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_STALL_PATTERN_3_4 +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_STALL_PATTERN_5_6 +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_STALL_PATTERN_7 +#define DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK 0x00007FFFL +//PCC_PWRBRK_HYSTERESIS_CTRL +#define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS__SHIFT 0x0 +#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS__SHIFT 0x8 +#define PCC_PWRBRK_HYSTERESIS_CTRL__PCC_MAX_HYSTERESIS_MASK 0x000000FFL +#define PCC_PWRBRK_HYSTERESIS_CTRL__PWRBRK_MAX_HYSTERESIS_MASK 0x0000FF00L +//EDC_STRETCH_PERF_COUNTER +#define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER__SHIFT 0x0 +#define EDC_STRETCH_PERF_COUNTER__STRETCH_PERF_COUNTER_MASK 0xFFFFFFFFL +//EDC_UNSTRETCH_PERF_COUNTER +#define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER__SHIFT 0x0 +#define EDC_UNSTRETCH_PERF_COUNTER__UNSTRETCH_PERF_COUNTER_MASK 0xFFFFFFFFL +//EDC_STRETCH_NUM_PERF_COUNTER +#define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER__SHIFT 0x0 +#define EDC_STRETCH_NUM_PERF_COUNTER__STRETCH_NUM_PERF_COUNTER_MASK 0xFFFFFFFFL +//GC_EDC_STATUS +#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x0 +#define GC_EDC_STATUS__GPIO_IN_0__SHIFT 0x3 +#define GC_EDC_STATUS__GPIO_IN_1__SHIFT 0x4 +#define GC_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x00000007L +#define GC_EDC_STATUS__GPIO_IN_0_MASK 0x00000008L +#define GC_EDC_STATUS__GPIO_IN_1_MASK 0x00000010L +//GC_EDC_OVERFLOW +#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define GC_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define GC_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//GC_EDC_ROLLING_POWER_DELTA_LO +#define GC_EDC_ROLLING_POWER_DELTA_LO__EDC_ROLLING_POWER_DELTA_LO__SHIFT 0x0 +#define GC_EDC_ROLLING_POWER_DELTA_LO__EDC_ROLLING_POWER_DELTA_LO_MASK 0xFFFFFFFFL +//GC_EDC_ROLLING_POWER_DELTA_HI +#define GC_EDC_ROLLING_POWER_DELTA_HI__EDC_ROLLING_POWER_DELTA_HI__SHIFT 0x0 +#define GC_EDC_ROLLING_POWER_DELTA_HI__EDC_ROLLING_POWER_DELTA_HI_MASK 0xFFFFFFFFL +//GC_EDC_AVG_POWER_DELTA_LO +#define GC_EDC_AVG_POWER_DELTA_LO__EDC_AVG_POWER_DELTA_LO__SHIFT 0x0 +#define GC_EDC_AVG_POWER_DELTA_LO__EDC_AVG_POWER_DELTA_LO_MASK 0xFFFFFFFFL +//GC_EDC_AVG_POWER_DELTA_HI +#define GC_EDC_AVG_POWER_DELTA_HI__EDC_AVG_POWER_DELTA_HI__SHIFT 0x0 +#define GC_EDC_AVG_POWER_DELTA_HI__EDC_AVG_POWER_DELTA_HI_MASK 0xFFFFFFFFL +//GC_THROTTLE_STATUS +#define GC_THROTTLE_STATUS__FSM_STATE__SHIFT 0x0 +#define GC_THROTTLE_STATUS__PATTERN_INDEX__SHIFT 0x4 +#define GC_THROTTLE_STATUS__FSM_STATE_MASK 0x0000000FL +#define GC_THROTTLE_STATUS__PATTERN_INDEX_MASK 0x000001F0L +//EDC_PERF_COUNTER +#define EDC_PERF_COUNTER__EDC_PERF_COUNTER__SHIFT 0x0 +#define EDC_PERF_COUNTER__EDC_PERF_COUNTER_MASK 0xFFFFFFFFL +//PCC_PERF_COUNTER +#define PCC_PERF_COUNTER__PCC_PERF_COUNTER__SHIFT 0x0 +#define PCC_PERF_COUNTER__PCC_PERF_COUNTER_MASK 0xFFFFFFFFL +//PWRBRK_PERF_COUNTER +#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER__SHIFT 0x0 +#define PWRBRK_PERF_COUNTER__PWRBRK_PERF_COUNTER_MASK 0xFFFFFFFFL +//EDC_HYSTERESIS_STAT +#define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT__SHIFT 0x0 +#define EDC_HYSTERESIS_STAT__EDC_STATUS__SHIFT 0x8 +#define EDC_HYSTERESIS_STAT__EDC_THRESHOLD_STAT__SHIFT 0x9 +#define EDC_HYSTERESIS_STAT__HYSTERESIS_CNT_MASK 0x000000FFL +#define EDC_HYSTERESIS_STAT__EDC_STATUS_MASK 0x00000100L +#define EDC_HYSTERESIS_STAT__EDC_THRESHOLD_STAT_MASK 0x00000200L +//DIDT_HYSTERESIS_STAT +#define DIDT_HYSTERESIS_STAT__DIDT_HYSTERESIS_CNT__SHIFT 0x0 +#define DIDT_HYSTERESIS_STAT__DIDT_DROOP_STATUS__SHIFT 0x8 +#define DIDT_HYSTERESIS_STAT__DIDT_HYSTERESIS_CNT_MASK 0x000000FFL +#define DIDT_HYSTERESIS_STAT__DIDT_DROOP_STATUS_MASK 0x00000100L +//DIDT_PERF_COUNTER +#define DIDT_PERF_COUNTER__DIDT_PERF_COUNTER__SHIFT 0x0 +#define DIDT_PERF_COUNTER__DIDT_PERF_COUNTER_MASK 0xFFFFFFFFL +//GC_EDC_CLK_MONITOR_CTRL +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN__SHIFT 0x0 +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL__SHIFT 0x1 +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD__SHIFT 0x5 +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_EN_MASK 0x00000001L +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_INTERVAL_MASK 0x0000001EL +#define GC_EDC_CLK_MONITOR_CTRL__EDC_CLK_MONITOR_THRESHOLD_MASK 0x0001FFE0L +//GC_CAC_SOFT_CTRL +#define GC_CAC_SOFT_CTRL__CAC_SOFT_SNAP__SHIFT 0x0 +#define GC_CAC_SOFT_CTRL__CAC_SOFT_SNAP_MASK 0x00000001L +//GC_CAC_WEIGHT_CP_0 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CP_0__WEIGHT_CP_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CP_1 +#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CP_1__WEIGHT_CP_SIG2_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_PMM_0 +#define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_PMM_0__WEIGHT_PMM_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_SDMA_0 +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_0__WEIGHT_SDMA_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_1 +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG2_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_1__WEIGHT_SDMA_SIG3_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_2 +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG4_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_2__WEIGHT_SDMA_SIG5_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_3 +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG6_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_3__WEIGHT_SDMA_SIG7_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_4 +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG8_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_4__WEIGHT_SDMA_SIG9_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_5 +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG10_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_5__WEIGHT_SDMA_SIG11_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CHC_0 +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_CHC_0__WEIGHT_CHC_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_CHC_1 +#define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_CHC_1__WEIGHT_CHC_SIG2_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_RLC_0 +#define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_RLC_0__WEIGHT_RLC_SIG0_MASK 0x0000FFFFL +//GC_CAC_WEIGHT_GRBM_0 +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GRBM_0__WEIGHT_GRBM_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_6 +#define GC_CAC_WEIGHT_SDMA_6__WEIGHT_SDMA_SIG12__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_6__WEIGHT_SDMA_SIG13__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_6__WEIGHT_SDMA_SIG12_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_6__WEIGHT_SDMA_SIG13_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_SDMA_7 +#define GC_CAC_WEIGHT_SDMA_7__WEIGHT_SDMA_SIG14__SHIFT 0x0 +#define GC_CAC_WEIGHT_SDMA_7__WEIGHT_SDMA_SIG15__SHIFT 0x10 +#define GC_CAC_WEIGHT_SDMA_7__WEIGHT_SDMA_SIG14_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_SDMA_7__WEIGHT_SDMA_SIG15_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GLARB_0 +#define GC_CAC_WEIGHT_GLARB_0__WEIGHT_GLARB_SIG0__SHIFT 0x0 +#define GC_CAC_WEIGHT_GLARB_0__WEIGHT_GLARB_SIG1__SHIFT 0x10 +#define GC_CAC_WEIGHT_GLARB_0__WEIGHT_GLARB_SIG0_MASK 0x0000FFFFL +#define GC_CAC_WEIGHT_GLARB_0__WEIGHT_GLARB_SIG1_MASK 0xFFFF0000L +//GC_CAC_WEIGHT_GLARB_1 +#define GC_CAC_WEIGHT_GLARB_1__WEIGHT_GLARB_SIG2__SHIFT 0x0 +#define GC_CAC_WEIGHT_GLARB_1__WEIGHT_GLARB_SIG2_MASK 0x0000FFFFL +//XCD_TOTAL_CAC_AGGR_LOWER +#define XCD_TOTAL_CAC_AGGR_LOWER__XCD_TOTAL_AGGR_31_0__SHIFT 0x0 +#define XCD_TOTAL_CAC_AGGR_LOWER__XCD_TOTAL_AGGR_31_0_MASK 0xFFFFFFFFL +//XCD_TOTAL_CAC_AGGR_UPPER +#define XCD_TOTAL_CAC_AGGR_UPPER__XCD_TOTAL_AGGR_63_32__SHIFT 0x0 +#define XCD_TOTAL_CAC_AGGR_UPPER__XCD_TOTAL_AGGR_63_32_MASK 0xFFFFFFFFL +//GC_EDC_WEIGHTED_DATA_MULTIPLIER +#define GC_EDC_WEIGHTED_DATA_MULTIPLIER__CAC_SCALE__SHIFT 0x0 +#define GC_EDC_WEIGHTED_DATA_MULTIPLIER__CAC_SCALING_EN__SHIFT 0x10 +#define GC_EDC_WEIGHTED_DATA_MULTIPLIER__CAC_SCALE_MASK 0x0000FFFFL +#define GC_EDC_WEIGHTED_DATA_MULTIPLIER__CAC_SCALING_EN_MASK 0x00010000L +//GC_CAC_IND_INDEX +#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR__SHIFT 0x0 +#define GC_CAC_IND_INDEX__GC_CAC_IND_ADDR_MASK 0xFFFFFFFFL +//GC_CAC_IND_DATA +#define GC_CAC_IND_DATA__GC_CAC_IND_DATA__SHIFT 0x0 +#define GC_CAC_IND_DATA__GC_CAC_IND_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gc_ea_cpwd_gceadec +//GC_EA_CPWD_VC_MAP +#define GC_EA_CPWD_VC_MAP__DRAM_VC__SHIFT 0x0 +#define GC_EA_CPWD_VC_MAP__IO_RD_VC__SHIFT 0x3 +#define GC_EA_CPWD_VC_MAP__IO_WR_VC__SHIFT 0x6 +#define GC_EA_CPWD_VC_MAP__GMI_VC__SHIFT 0x9 +#define GC_EA_CPWD_VC_MAP__NPA_VC__SHIFT 0xc +#define GC_EA_CPWD_VC_MAP__NPAS_VC__SHIFT 0xf +#define GC_EA_CPWD_VC_MAP__LPDDR_VC__SHIFT 0x12 +#define GC_EA_CPWD_VC_MAP__RSP_ACK_TRCKR_CHECK_EN_ON_RSP_CREDIT__SHIFT 0x15 +#define GC_EA_CPWD_VC_MAP__PRB_RSP_SEND_WO_PRB_RTN_DAT_AVAIL__SHIFT 0x16 +#define GC_EA_CPWD_VC_MAP__REG_ATOMIC_RPC_CMD_SELECT__SHIFT 0x17 +#define GC_EA_CPWD_VC_MAP__RSP_ACK_TRACKER_FIFO_SPACE__SHIFT 0x18 +#define GC_EA_CPWD_VC_MAP__DRAM_VC_MASK 0x00000007L +#define GC_EA_CPWD_VC_MAP__IO_RD_VC_MASK 0x00000038L +#define GC_EA_CPWD_VC_MAP__IO_WR_VC_MASK 0x000001C0L +#define GC_EA_CPWD_VC_MAP__GMI_VC_MASK 0x00000E00L +#define GC_EA_CPWD_VC_MAP__NPA_VC_MASK 0x00007000L +#define GC_EA_CPWD_VC_MAP__NPAS_VC_MASK 0x00038000L +#define GC_EA_CPWD_VC_MAP__LPDDR_VC_MASK 0x001C0000L +#define GC_EA_CPWD_VC_MAP__RSP_ACK_TRCKR_CHECK_EN_ON_RSP_CREDIT_MASK 0x00200000L +#define GC_EA_CPWD_VC_MAP__PRB_RSP_SEND_WO_PRB_RTN_DAT_AVAIL_MASK 0x00400000L +#define GC_EA_CPWD_VC_MAP__REG_ATOMIC_RPC_CMD_SELECT_MASK 0x00800000L +#define GC_EA_CPWD_VC_MAP__RSP_ACK_TRACKER_FIFO_SPACE_MASK 0xFF000000L +//GC_EA_CPWD_SDP_ARB_FINAL +#define GC_EA_CPWD_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 +#define GC_EA_CPWD_SDP_ARB_FINAL__LPDDR_BURST_LIMIT__SHIFT 0x5 +#define GC_EA_CPWD_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa +#define GC_EA_CPWD_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf +#define GC_EA_CPWD_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x11 +#define GC_EA_CPWD_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x12 +#define GC_EA_CPWD_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x13 +#define GC_EA_CPWD_SDP_ARB_FINAL__HDM_BURST_LIMIT__SHIFT 0x18 +#define GC_EA_CPWD_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL +#define GC_EA_CPWD_SDP_ARB_FINAL__LPDDR_BURST_LIMIT_MASK 0x000003E0L +#define GC_EA_CPWD_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L +#define GC_EA_CPWD_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L +#define GC_EA_CPWD_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x00020000L +#define GC_EA_CPWD_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x00040000L +#define GC_EA_CPWD_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x00F80000L +#define GC_EA_CPWD_SDP_ARB_FINAL__HDM_BURST_LIMIT_MASK 0x1F000000L +//GC_EA_CPWD_SDP_PRIORITY +#define GC_EA_CPWD_SDP_PRIORITY__DRAM_PRIORITY__SHIFT 0x0 +#define GC_EA_CPWD_SDP_PRIORITY__IO_RD_PRIORITY__SHIFT 0x4 +#define GC_EA_CPWD_SDP_PRIORITY__IO_WR_PRIORITY__SHIFT 0x8 +#define GC_EA_CPWD_SDP_PRIORITY__MAM_WR_PRIORITY__SHIFT 0xc +#define GC_EA_CPWD_SDP_PRIORITY__GMI_PRIORITY__SHIFT 0x10 +#define GC_EA_CPWD_SDP_PRIORITY__HDM_PRIORITY__SHIFT 0x14 +#define GC_EA_CPWD_SDP_PRIORITY__LPDDR_PRIORITY__SHIFT 0x18 +#define GC_EA_CPWD_SDP_PRIORITY__DRAM_PRIORITY_MASK 0x0000000FL +#define GC_EA_CPWD_SDP_PRIORITY__IO_RD_PRIORITY_MASK 0x000000F0L +#define GC_EA_CPWD_SDP_PRIORITY__IO_WR_PRIORITY_MASK 0x00000F00L +#define GC_EA_CPWD_SDP_PRIORITY__MAM_WR_PRIORITY_MASK 0x0000F000L +#define GC_EA_CPWD_SDP_PRIORITY__GMI_PRIORITY_MASK 0x000F0000L +#define GC_EA_CPWD_SDP_PRIORITY__HDM_PRIORITY_MASK 0x00F00000L +#define GC_EA_CPWD_SDP_PRIORITY__LPDDR_PRIORITY_MASK 0x0F000000L +//GC_EA_CPWD_SDP_CREDITS +#define GC_EA_CPWD_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 +#define GC_EA_CPWD_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x9 +#define GC_EA_CPWD_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 +#define GC_EA_CPWD_SDP_CREDITS__PRB_REQ_CREDITS__SHIFT 0x17 +#define GC_EA_CPWD_SDP_CREDITS__TAG_LIMIT_MASK 0x000001FFL +#define GC_EA_CPWD_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x0000FE00L +#define GC_EA_CPWD_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L +#define GC_EA_CPWD_SDP_CREDITS__PRB_REQ_CREDITS_MASK 0x3F800000L +//GC_EA_CPWD_SDP_TAG_RESERVE0 +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC1__SHIFT 0x9 +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC2__SHIFT 0x12 +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC0_MASK 0x000001FFL +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC1_MASK 0x0003FE00L +#define GC_EA_CPWD_SDP_TAG_RESERVE0__VC2_MASK 0x07FC0000L +//GC_EA_CPWD_SDP_TAG_RESERVE1 +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC3__SHIFT 0x0 +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC4__SHIFT 0x9 +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC5__SHIFT 0x12 +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC3_MASK 0x000001FFL +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC4_MASK 0x0003FE00L +#define GC_EA_CPWD_SDP_TAG_RESERVE1__VC5_MASK 0x07FC0000L +//GC_EA_CPWD_SDP_TAG_RESERVE2 +#define GC_EA_CPWD_SDP_TAG_RESERVE2__VC6__SHIFT 0x0 +#define GC_EA_CPWD_SDP_TAG_RESERVE2__VC7__SHIFT 0x9 +#define GC_EA_CPWD_SDP_TAG_RESERVE2__VC6_MASK 0x000001FFL +#define GC_EA_CPWD_SDP_TAG_RESERVE2__VC7_MASK 0x0003FE00L +//GC_EA_CPWD_SDP_VCC_RESERVE0 +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define GC_EA_CPWD_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//GC_EA_CPWD_SDP_VCC_RESERVE1 +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define GC_EA_CPWD_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define GC_EA_CPWD_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define GC_EA_CPWD_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//GC_EA_CPWD_SDP_VCD_RESERVE0 +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L +#define GC_EA_CPWD_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L +//GC_EA_CPWD_SDP_VCD_RESERVE1 +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc +#define GC_EA_CPWD_SDP_VCD_RESERVE1__PRB_CREDITS__SHIFT 0x12 +#define GC_EA_CPWD_SDP_VCD_RESERVE1__POOL_CREDITS__SHIFT 0x18 +#define GC_EA_CPWD_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L +#define GC_EA_CPWD_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L +#define GC_EA_CPWD_SDP_VCD_RESERVE1__PRB_CREDITS_MASK 0x00FC0000L +#define GC_EA_CPWD_SDP_VCD_RESERVE1__POOL_CREDITS_MASK 0x3F000000L +#define GC_EA_CPWD_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L +//GC_EA_CPWD_SDP_REQ_CNTL +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 +#define GC_EA_CPWD_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x3 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x4 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x6 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0x8 +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0xa +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0xb +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_HDM__SHIFT 0xc +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_LPDDR__SHIFT 0xd +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L +#define GC_EA_CPWD_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000008L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x00000030L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x000000C0L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000300L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000400L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000800L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_HDM_MASK 0x00001000L +#define GC_EA_CPWD_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_LPDDR_MASK 0x00002000L +//GC_EA_CPWD_MISC +#define GC_EA_CPWD_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x0 +#define GC_EA_CPWD_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x2 +#define GC_EA_CPWD_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x4 +#define GC_EA_CPWD_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x6 +#define GC_EA_CPWD_MISC__LINKMGR_CREDITRESET_CGCG_IGNORE__SHIFT 0xb +#define GC_EA_CPWD_MISC__RSP_ACK_TRACKER_FIFO_SPACE_RSP_PATH__SHIFT 0xc +#define GC_EA_CPWD_MISC__RSP_ACK_PRB_LINK_BUSY__SHIFT 0x14 +#define GC_EA_CPWD_MISC__RSP_ACK_TAG_RELEASE__SHIFT 0x15 +#define GC_EA_CPWD_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000003L +#define GC_EA_CPWD_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x0000000CL +#define GC_EA_CPWD_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00000030L +#define GC_EA_CPWD_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x000007C0L +#define GC_EA_CPWD_MISC__LINKMGR_CREDITRESET_CGCG_IGNORE_MASK 0x00000800L +#define GC_EA_CPWD_MISC__RSP_ACK_TRACKER_FIFO_SPACE_RSP_PATH_MASK 0x000FF000L +#define GC_EA_CPWD_MISC__RSP_ACK_PRB_LINK_BUSY_MASK 0x00100000L +#define GC_EA_CPWD_MISC__RSP_ACK_TAG_RELEASE_MASK 0x00200000L +//GC_EA_CPWD_ERR_STATUS +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 +#define GC_EA_CPWD_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_COMP_KEY_PARITY_ERROR__SHIFT 0xb +#define GC_EA_CPWD_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xc +#define GC_EA_CPWD_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xd +#define GC_EA_CPWD_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe +#define GC_EA_CPWD_ERR_STATUS__FUE_FLAG__SHIFT 0xf +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL +#define GC_EA_CPWD_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define GC_EA_CPWD_ERR_STATUS__SDP_RDRSP_COMP_KEY_PARITY_ERROR_MASK 0x00000800L +#define GC_EA_CPWD_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00001000L +#define GC_EA_CPWD_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00002000L +#define GC_EA_CPWD_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L +#define GC_EA_CPWD_ERR_STATUS__FUE_FLAG_MASK 0x00008000L +//GC_EA_CPWD_MISC2 +#define GC_EA_CPWD_MISC2__BLOCK_REQUESTS__SHIFT 0x0 +#define GC_EA_CPWD_MISC2__REQUESTS_BLOCKED__SHIFT 0x1 +#define GC_EA_CPWD_MISC2__FGCLKEN_OVERRIDE__SHIFT 0x2 +#define GC_EA_CPWD_MISC2__LINKMGR_CRBUSY_MASK__SHIFT 0x3 +#define GC_EA_CPWD_MISC2__RDRET_FED_MASK__SHIFT 0x4 +#define GC_EA_CPWD_MISC2__BLOCK_REQUESTS_MASK 0x00000001L +#define GC_EA_CPWD_MISC2__REQUESTS_BLOCKED_MASK 0x00000002L +#define GC_EA_CPWD_MISC2__FGCLKEN_OVERRIDE_MASK 0x00000004L +#define GC_EA_CPWD_MISC2__LINKMGR_CRBUSY_MASK_MASK 0x00000008L +#define GC_EA_CPWD_MISC2__RDRET_FED_MASK_MASK 0x00000010L +//GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L +//GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC0_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC1_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC2_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC3_CREDITS_RECEIVED__SHIFT 0x15 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC4_CREDITS_RECEIVED__SHIFT 0x1c +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC0_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC1_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC2_CREDITS_RECEIVED_MASK 0x001FC000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS0_WRITE__VC4_CREDITS_RECEIVED_MASK 0xF0000000L +//GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L +//GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC4_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC5_CREDITS_RECEIVED__SHIFT 0x3 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC6_CREDITS_RECEIVED__SHIFT 0xa +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC7_CREDITS_RECEIVED__SHIFT 0x11 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__POOL_CREDITS_RECEIVED__SHIFT 0x18 +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC4_CREDITS_RECEIVED_MASK 0x00000007L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC5_CREDITS_RECEIVED_MASK 0x000003F8L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L +#define GC_EA_CPWD_SDP_BACKDOOR_CMDCREDITS1_WRITE__POOL_CREDITS_RECEIVED_MASK 0x7F000000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED__SHIFT 0x15 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED__SHIFT 0x1c +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC0_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC1_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC2_CREDITS_RECEIVED_MASK 0x001FC000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0__VC4_CREDITS_RECEIVED_MASK 0xF0000000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC0_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC1_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC2_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC3_CREDITS_RECEIVED__SHIFT 0x15 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC4_CREDITS_RECEIVED__SHIFT 0x1c +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC0_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC1_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC2_CREDITS_RECEIVED_MASK 0x001FC000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC3_CREDITS_RECEIVED_MASK 0x0FE00000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS0_WRITE__VC4_CREDITS_RECEIVED_MASK 0xF0000000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED__SHIFT 0x3 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED__SHIFT 0xa +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED__SHIFT 0x11 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED__SHIFT 0x18 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC4_CREDITS_RECEIVED_MASK 0x00000007L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC5_CREDITS_RECEIVED_MASK 0x000003F8L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1__POOL_CREDITS_RECEIVED_MASK 0x7F000000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC4_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC5_CREDITS_RECEIVED__SHIFT 0x3 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC6_CREDITS_RECEIVED__SHIFT 0xa +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC7_CREDITS_RECEIVED__SHIFT 0x11 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__POOL_CREDITS_RECEIVED__SHIFT 0x18 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC4_CREDITS_RECEIVED_MASK 0x00000007L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC5_CREDITS_RECEIVED_MASK 0x000003F8L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC6_CREDITS_RECEIVED_MASK 0x0001FC00L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__VC7_CREDITS_RECEIVED_MASK 0x00FE0000L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS1_WRITE__POOL_CREDITS_RECEIVED_MASK 0x7F000000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__PRBR_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__PRBRSP_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__RSP_ACK_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__PRBR_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__PRBRSP_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2__RSP_ACK_CREDITS_RECEIVED_MASK 0x001FC000L +//GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__PRBR_CREDITS_RECEIVED__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__PRBRSP_CREDITS_RECEIVED__SHIFT 0x7 +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__RSP_ACK_CREDITS_RECEIVED__SHIFT 0xe +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__PRBR_CREDITS_RECEIVED_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__PRBRSP_CREDITS_RECEIVED_MASK 0x00003F80L +#define GC_EA_CPWD_SDP_BACKDOOR_DATACREDITS2_WRITE__RSP_ACK_CREDITS_RECEIVED_MASK 0x001FC000L +//GC_EA_CPWD_SDP_BACKDOOR_MISCCTL +#define GC_EA_CPWD_SDP_BACKDOOR_MISCCTL__SDP_ORIGCLKCTL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_MISCCTL__SDP_ORIGCLKCTL_MASK 0x00000001L +//GC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE +#define GC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE__SDP_ORIGCLKCTL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_BACKDOOR_MISCCTL_WRITE__SDP_ORIGCLKCTL_MASK 0x00000001L +//GC_EA_CPWD_INVALID_OPCODE +#define GC_EA_CPWD_INVALID_OPCODE__INVALID_COMMAND__SHIFT 0x0 +#define GC_EA_CPWD_INVALID_OPCODE__BAD_OPCODE__SHIFT 0x1 +#define GC_EA_CPWD_INVALID_OPCODE__BAD_OPCODE_VFID__SHIFT 0xc +#define GC_EA_CPWD_INVALID_OPCODE__INVALID_COMMAND_MASK 0x00000001L +#define GC_EA_CPWD_INVALID_OPCODE__BAD_OPCODE_MASK 0x000001FEL +#define GC_EA_CPWD_INVALID_OPCODE__BAD_OPCODE_VFID_MASK 0x0001F000L +//GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__EGRESS_POISON_ERR_INJ_CNT__SHIFT 0x0 +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__EGRESS_POISON_ERR_INJ_EN__SHIFT 0x7 +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__INGRESS_POISON_ERR_INJ_CNT__SHIFT 0x8 +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__INGRESS_POISON_ERR_INJ_EN__SHIFT 0xf +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__EGRESS_POISON_ERR_INJ_CNT_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__EGRESS_POISON_ERR_INJ_EN_MASK 0x00000080L +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__INGRESS_POISON_ERR_INJ_CNT_MASK 0x00007F00L +#define GC_EA_CPWD_SDP_POISON_ERR_INJ_CTRL__INGRESS_POISON_ERR_INJ_EN_MASK 0x00008000L +//GC_EA_CPWD_SDP_POISON_ERR_LOG +#define GC_EA_CPWD_SDP_POISON_ERR_LOG__EGRESS_POISON_ERR_CNT_LOG__SHIFT 0x0 +#define GC_EA_CPWD_SDP_POISON_ERR_LOG__INGRESS_POISON_ERR_CNT_LOG__SHIFT 0x8 +#define GC_EA_CPWD_SDP_POISON_ERR_LOG__EGRESS_POISON_ERR_CNT_LOG_MASK 0x000000FFL +#define GC_EA_CPWD_SDP_POISON_ERR_LOG__INGRESS_POISON_ERR_CNT_LOG_MASK 0x0000FF00L +//GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__EGRESS_ORIGDATA_PARITY_ERR_INJ_CNT__SHIFT 0x0 +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__EGRESS_ORIGDATA_PARITY_ERR_INJ_EN__SHIFT 0x7 +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__INGRESS_RDRSPDATA_PARITY_ERR_INJ_CNT__SHIFT 0x8 +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__INGRESS_RDRSPDATA_PARITY_ERR_INJ_EN__SHIFT 0xf +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__EGRESS_ORIGDATA_PARITY_ERR_INJ_CNT_MASK 0x0000007FL +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__EGRESS_ORIGDATA_PARITY_ERR_INJ_EN_MASK 0x00000080L +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__INGRESS_RDRSPDATA_PARITY_ERR_INJ_CNT_MASK 0x00007F00L +#define GC_EA_CPWD_SDP_PARITY_ERR_INJ_CTRL__INGRESS_RDRSPDATA_PARITY_ERR_INJ_EN_MASK 0x00008000L +//GC_EA_CPWD_SDP_PARITY_ERR_LOG +#define GC_EA_CPWD_SDP_PARITY_ERR_LOG__EGRESS_ORIGDATA_PARITY_ERR_CNT_LOG__SHIFT 0x0 +#define GC_EA_CPWD_SDP_PARITY_ERR_LOG__INGRESS_RDRSPDATA_PARITY_ERR_CNT_LOG__SHIFT 0x8 +#define GC_EA_CPWD_SDP_PARITY_ERR_LOG__EGRESS_ORIGDATA_PARITY_ERR_CNT_LOG_MASK 0x000000FFL +#define GC_EA_CPWD_SDP_PARITY_ERR_LOG__INGRESS_RDRSPDATA_PARITY_ERR_CNT_LOG_MASK 0x0000FF00L +//GC_EA_CPWD_SDP_ENABLE +#define GC_EA_CPWD_SDP_ENABLE__ENABLE__SHIFT 0x0 +#define GC_EA_CPWD_SDP_ENABLE__EARLY_CREDIT_REQUEST__SHIFT 0x1 +#define GC_EA_CPWD_SDP_ENABLE__ENABLE_MASK 0x00000001L +#define GC_EA_CPWD_SDP_ENABLE__EARLY_CREDIT_REQUEST_MASK 0x00000002L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gcrdec +//GCR_PIO_CNTL +#define GCR_PIO_CNTL__GCR_DATA_INDEX__SHIFT 0x0 +#define GCR_PIO_CNTL__GCR_REG_DONE__SHIFT 0x3 +#define GCR_PIO_CNTL__GCR_REG_RESET__SHIFT 0x4 +#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG__SHIFT 0x10 +#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE__SHIFT 0x1e +#define GCR_PIO_CNTL__GCR_READY__SHIFT 0x1f +#define GCR_PIO_CNTL__GCR_DATA_INDEX_MASK 0x00000007L +#define GCR_PIO_CNTL__GCR_REG_DONE_MASK 0x00000008L +#define GCR_PIO_CNTL__GCR_REG_RESET_MASK 0x00000010L +#define GCR_PIO_CNTL__GCR_PIO_RSP_TAG_MASK 0x00FF0000L +#define GCR_PIO_CNTL__GCR_PIO_RSP_DONE_MASK 0x40000000L +#define GCR_PIO_CNTL__GCR_READY_MASK 0x80000000L +//GCR_PIO_DATA +#define GCR_PIO_DATA__GCR_DATA__SHIFT 0x0 +#define GCR_PIO_DATA__GCR_DATA_MASK 0xFFFFFFFFL +//GCR_NHTOE_CNTL +#define GCR_NHTOE_CNTL__GCR_DATA_INDEX__SHIFT 0x0 +#define GCR_NHTOE_CNTL__GCR_REG_DONE__SHIFT 0x3 +#define GCR_NHTOE_CNTL__GCR_REG_RESET__SHIFT 0x4 +#define GCR_NHTOE_CNTL__GCR_NHTOE_RSP_TAG__SHIFT 0x10 +#define GCR_NHTOE_CNTL__GCR_NHTOE_RSP_DONE__SHIFT 0x1e +#define GCR_NHTOE_CNTL__GCR_READY__SHIFT 0x1f +#define GCR_NHTOE_CNTL__GCR_DATA_INDEX_MASK 0x00000007L +#define GCR_NHTOE_CNTL__GCR_REG_DONE_MASK 0x00000008L +#define GCR_NHTOE_CNTL__GCR_REG_RESET_MASK 0x00000010L +#define GCR_NHTOE_CNTL__GCR_NHTOE_RSP_TAG_MASK 0x00FF0000L +#define GCR_NHTOE_CNTL__GCR_NHTOE_RSP_DONE_MASK 0x40000000L +#define GCR_NHTOE_CNTL__GCR_READY_MASK 0x80000000L +//GCR_NHTOE_DATA +#define GCR_NHTOE_DATA__GCR_DATA__SHIFT 0x0 +#define GCR_NHTOE_DATA__GCR_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cppdec +//CPC_INT_ADDR1 +#define CPC_INT_ADDR1__ADDR__SHIFT 0x0 +#define CPC_INT_ADDR1__ADDR_MASK 0x000001FFL +//CP_CU_MASK_ADDR_LO +#define CP_CU_MASK_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_CU_MASK_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_CU_MASK_ADDR_HI +#define CP_CU_MASK_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_CU_MASK_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//CP_CU_MASK_CNTL +#define CP_CU_MASK_CNTL__POLICY__SHIFT 0x0 +#define CP_CU_MASK_CNTL__SCOPE__SHIFT 0x2 +#define CP_CU_MASK_CNTL__POLICY_MASK 0x00000003L +#define CP_CU_MASK_CNTL__SCOPE_MASK 0x0000000CL +//CP_EOPQ_WAIT_TIME +#define CP_EOPQ_WAIT_TIME__WAIT_TIME__SHIFT 0x0 +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT__SHIFT 0xa +#define CP_EOPQ_WAIT_TIME__WAIT_TIME_MASK 0x000003FFL +#define CP_EOPQ_WAIT_TIME__SCALE_COUNT_MASK 0x0003FC00L +//CP_CPC_MGCG_SYNC_CNTL +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L +//CPC_INT_INFO +#define CPC_INT_INFO__ADDR_HI__SHIFT 0x0 +#define CPC_INT_INFO__TYPE__SHIFT 0x10 +#define CPC_INT_INFO__VMID__SHIFT 0x14 +#define CPC_INT_INFO__QUEUE_ID__SHIFT 0x1c +#define CPC_INT_INFO__ADDR_HI_MASK 0x0000FFFFL +#define CPC_INT_INFO__TYPE_MASK 0x00010000L +#define CPC_INT_INFO__VMID_MASK 0x00F00000L +#define CPC_INT_INFO__QUEUE_ID_MASK 0x70000000L +//CP_VIRT_STATUS +#define CP_VIRT_STATUS__VF__SHIFT 0x0 +#define CP_VIRT_STATUS__PF__SHIFT 0x1f +#define CP_VIRT_STATUS__VF_MASK 0x00FFFFFFL +#define CP_VIRT_STATUS__PF_MASK 0x80000000L +//CPC_INT_ADDR +#define CPC_INT_ADDR__ADDR__SHIFT 0x0 +#define CPC_INT_ADDR__ADDR_MASK 0xFFFFFFFFL +//CPC_INT_PASID +#define CPC_INT_PASID__PASID__SHIFT 0x0 +#define CPC_INT_PASID__BYPASS_PASID__SHIFT 0x10 +#define CPC_INT_PASID__PASID_MASK 0x0000FFFFL +#define CPC_INT_PASID__BYPASS_PASID_MASK 0x00010000L +//CP_GFX_ERROR +#define CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR__SHIFT 0x0 +#define CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR__SHIFT 0x1 +#define CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR__SHIFT 0x2 +#define CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR__SHIFT 0x3 +#define CP_GFX_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR__SHIFT 0x6 +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR__SHIFT 0x9 +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR__SHIFT 0xa +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR__SHIFT 0xb +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR__SHIFT 0xc +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR__SHIFT 0xd +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR__SHIFT 0xe +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR__SHIFT 0xf +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0x12 +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x13 +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR__SHIFT 0x14 +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR__SHIFT 0x15 +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR__SHIFT 0x17 +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR__SHIFT 0x18 +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR__SHIFT 0x19 +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR__SHIFT 0x1a +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR__SHIFT 0x1b +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR__SHIFT 0x1e +#define CP_GFX_ERROR__RESERVED__SHIFT 0x1f +#define CP_GFX_ERROR__ME_INSTR_CACHE_UTCL1_ERROR_MASK 0x00000001L +#define CP_GFX_ERROR__PFP_INSTR_CACHE_UTCL1_ERROR_MASK 0x00000002L +#define CP_GFX_ERROR__DDID_DRAW_UTCL1_ERROR_MASK 0x00000004L +#define CP_GFX_ERROR__DDID_DISPATCH_UTCL1_ERROR_MASK 0x00000008L +#define CP_GFX_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_GFX_ERROR__DATA_FETCHER_UTCL1_ERROR_MASK 0x00000040L +#define CP_GFX_ERROR__QU_EOP_UTCL1_ERROR_MASK 0x00000200L +#define CP_GFX_ERROR__QU_PIPE_UTCL1_ERROR_MASK 0x00000400L +#define CP_GFX_ERROR__QU_READ_UTCL1_ERROR_MASK 0x00000800L +#define CP_GFX_ERROR__SYNC_MEMRD_UTCL1_ERROR_MASK 0x00001000L +#define CP_GFX_ERROR__SYNC_MEMWR_UTCL1_ERROR_MASK 0x00002000L +#define CP_GFX_ERROR__SHADOW_UTCL1_ERROR_MASK 0x00004000L +#define CP_GFX_ERROR__APPEND_UTCL1_ERROR_MASK 0x00008000L +#define CP_GFX_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00040000L +#define CP_GFX_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00080000L +#define CP_GFX_ERROR__PFP_TC_UTCL1_ERROR_MASK 0x00100000L +#define CP_GFX_ERROR__ME_TC_UTCL1_ERROR_MASK 0x00200000L +#define CP_GFX_ERROR__PRT_LOD_UTCL1_ERROR_MASK 0x00800000L +#define CP_GFX_ERROR__RDPTR_RPT_UTCL1_ERROR_MASK 0x01000000L +#define CP_GFX_ERROR__RB_FETCHER_UTCL1_ERROR_MASK 0x02000000L +#define CP_GFX_ERROR__I1_FETCHER_UTCL1_ERROR_MASK 0x04000000L +#define CP_GFX_ERROR__I2_FETCHER_UTCL1_ERROR_MASK 0x08000000L +#define CP_GFX_ERROR__ST_FETCHER_UTCL1_ERROR_MASK 0x40000000L +#define CP_GFX_ERROR__RESERVED_MASK 0x80000000L +//CPG_UTCL1_CNTL +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPG_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPG_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPG_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPG_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPG_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPG_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPG_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPG_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPG_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPG_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPG_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPG_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPC_UTCL1_CNTL +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPC_UTCL1_CNTL__EN_RETRY_ON_ATOMIC__SHIFT 0x15 +#define CPC_UTCL1_CNTL__PCIE_ATOMIC_SUPPORTED__SHIFT 0x16 +#define CPC_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPC_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPC_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPC_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPC_UTCL1_CNTL__EN_RETRY_ON_ATOMIC_MASK 0x00200000L +#define CPC_UTCL1_CNTL__PCIE_ATOMIC_SUPPORTED_MASK 0x00400000L +#define CPC_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPC_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPC_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPC_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPC_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPC_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +//CPF_UTCL1_CNTL +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CPF_UTCL1_CNTL__VMID_RESET_MODE__SHIFT 0x17 +#define CPF_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define CPF_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define CPF_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x1d +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x1e +#define CPF_UTCL1_CNTL__FORCE_NO_EXE__SHIFT 0x1f +#define CPF_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define CPF_UTCL1_CNTL__VMID_RESET_MODE_MASK 0x00800000L +#define CPF_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define CPF_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define CPF_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define CPF_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define CPF_UTCL1_CNTL__IGNORE_PTE_PERMISSION_MASK 0x20000000L +#define CPF_UTCL1_CNTL__MTYPE_NO_PTE_MODE_MASK 0x40000000L +#define CPF_UTCL1_CNTL__FORCE_NO_EXE_MASK 0x80000000L +//CP_AQL_SMM_STATUS +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM__SHIFT 0x0 +#define CP_AQL_SMM_STATUS__AQL_QUEUE_SMM_MASK 0xFFFFFFFFL +//CP_RB0_BASE +#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB_BASE +#define CP_RB_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_RB0_CNTL +#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB0_CNTL__TMZ_STATE__SHIFT 0x6 +#define CP_RB0_CNTL__TMZ_MATCH__SHIFT 0x7 +#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB0_CNTL__RB_NON_PRIV__SHIFT 0xf +#define CP_RB0_CNTL__SCOPE__SHIFT 0x12 +#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB0_CNTL__RB_EXE__SHIFT 0x1c +#define CP_RB0_CNTL__KMD_QUEUE__SHIFT 0x1d +#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB0_CNTL__TMZ_STATE_MASK 0x00000040L +#define CP_RB0_CNTL__TMZ_MATCH_MASK 0x00000080L +#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB0_CNTL__RB_NON_PRIV_MASK 0x00008000L +#define CP_RB0_CNTL__SCOPE_MASK 0x000C0000L +#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB0_CNTL__RB_EXE_MASK 0x10000000L +#define CP_RB0_CNTL__KMD_QUEUE_MASK 0x20000000L +#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_CNTL +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB_CNTL__TMZ_STATE__SHIFT 0x6 +#define CP_RB_CNTL__TMZ_MATCH__SHIFT 0x7 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB_CNTL__RB_NON_PRIV__SHIFT 0xf +#define CP_RB_CNTL__SCOPE__SHIFT 0x12 +#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB_CNTL__RB_EXE__SHIFT 0x1c +#define CP_RB_CNTL__KMD_QUEUE__SHIFT 0x1d +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_RB_CNTL__TMZ_STATE_MASK 0x00000040L +#define CP_RB_CNTL__TMZ_MATCH_MASK 0x00000080L +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_RB_CNTL__RB_NON_PRIV_MASK 0x00008000L +#define CP_RB_CNTL__SCOPE_MASK 0x000C0000L +#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_RB_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_RB_CNTL__RB_EXE_MASK 0x10000000L +#define CP_RB_CNTL__KMD_QUEUE_MASK 0x20000000L +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_RB_RPTR_WR +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0x000FFFFFL +//CP_RB0_RPTR_ADDR +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB_RPTR_ADDR +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_RB0_RPTR_ADDR_HI +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_RPTR_ADDR_HI +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB0_BUFSZ_MASK +#define CP_RB0_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB0_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_RB_BUFSZ_MASK +#define CP_RB_BUFSZ_MASK__DATA__SHIFT 0x0 +#define CP_RB_BUFSZ_MASK__DATA_MASK 0x000FFFFFL +//CP_ME3_INT_STAT_DEBUG +#define CP_ME3_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME3_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME3_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME3_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME3_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L +#define CP_ME3_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L +#define CP_ME3_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L +#define CP_ME3_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L +//GC_PRIV_MODE +#define GC_PRIV_MODE__MC_PRIV_MODE__SHIFT 0x0 +#define GC_PRIV_MODE__MC_PRIV_MODE_MASK 0x00000001L +//CP_INT_CNTL +#define CP_INT_CNTL__RESUME_INT_ENABLE__SHIFT 0x8 +#define CP_INT_CNTL__SUSPEND_INT_ENABLE__SHIFT 0x9 +#define CP_INT_CNTL__DMA_WATCH_INT_ENABLE__SHIFT 0xa +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL__RESUME_INT_ENABLE_MASK 0x00000100L +#define CP_INT_CNTL__SUSPEND_INT_ENABLE_MASK 0x00000200L +#define CP_INT_CNTL__DMA_WATCH_INT_ENABLE_MASK 0x00000400L +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_INT_STATUS +#define CP_INT_STATUS__RESUME_INT_STAT__SHIFT 0x8 +#define CP_INT_STATUS__SUSPEND_INT_STAT__SHIFT 0x9 +#define CP_INT_STATUS__DMA_WATCH_INT_STAT__SHIFT 0xa +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS__RESUME_INT_STAT_MASK 0x00000100L +#define CP_INT_STATUS__SUSPEND_INT_STAT_MASK 0x00000200L +#define CP_INT_STATUS__DMA_WATCH_INT_STAT_MASK 0x00000400L +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_DEVICE_ID +#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define CP_DEVICE_ID__DEVICE_ID_MASK 0x000000FFL +//CP_ME0_PIPE_PRIORITY_CNTS +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_RING_PRIORITY_CNTS +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME0_PIPE0_PRIORITY +#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_RING0_PRIORITY +#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_FATAL_ERROR +#define CP_FATAL_ERROR__CPF_FATAL_ERROR__SHIFT 0x0 +#define CP_FATAL_ERROR__CPG_FATAL_ERROR__SHIFT 0x1 +#define CP_FATAL_ERROR__GFX_HALT_PROC__SHIFT 0x2 +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR__SHIFT 0x3 +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN__SHIFT 0x4 +#define CP_FATAL_ERROR__CPF_FATAL_ERROR_MASK 0x00000001L +#define CP_FATAL_ERROR__CPG_FATAL_ERROR_MASK 0x00000002L +#define CP_FATAL_ERROR__GFX_HALT_PROC_MASK 0x00000004L +#define CP_FATAL_ERROR__DIS_CPG_FATAL_ERROR_MASK 0x00000008L +#define CP_FATAL_ERROR__CPG_TAG_FATAL_ERROR_EN_MASK 0x00000010L +//CP_RB_VMID +#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 +#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 +#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 +#define CP_RB_VMID__RB0_VMID_MASK 0x0000000FL +#define CP_RB_VMID__RB1_VMID_MASK 0x00000F00L +#define CP_RB_VMID__RB2_VMID_MASK 0x000F0000L +//CP_ME0_PIPE0_VMID +#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE0_VMID__VMID_MASK 0x0000000FL +//CP_RB0_WPTR +#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB0_WPTR_HI +#define CP_RB0_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB0_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_RB_WPTR_HI +#define CP_RB_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_PROCESS_QUANTUM +#define CP_PROCESS_QUANTUM__QUANTUM_DURATION__SHIFT 0x0 +#define CP_PROCESS_QUANTUM__TIMER_EXPIRED__SHIFT 0x1c +#define CP_PROCESS_QUANTUM__QUANTUM_SCALE__SHIFT 0x1d +#define CP_PROCESS_QUANTUM__QUANTUM_EN__SHIFT 0x1f +#define CP_PROCESS_QUANTUM__QUANTUM_DURATION_MASK 0x0FFFFFFFL +#define CP_PROCESS_QUANTUM__TIMER_EXPIRED_MASK 0x10000000L +#define CP_PROCESS_QUANTUM__QUANTUM_SCALE_MASK 0x60000000L +#define CP_PROCESS_QUANTUM__QUANTUM_EN_MASK 0x80000000L +//CP_RB_DOORBELL_RANGE_LOWER +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x00000FFCL +//CP_RB_DOORBELL_RANGE_UPPER +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL +//CP_MEC_DOORBELL_RANGE_LOWER +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x00000FFCL +//CP_MEC_DOORBELL_RANGE_UPPER +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x00000FFCL +//CPG_UTCL1_ERROR +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPG_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CPC_UTCL1_ERROR +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT__SHIFT 0x0 +#define CPC_UTCL1_ERROR__ERROR_DETECTED_HALT_MASK 0x00000001L +//CPF_FED_STATUS +#define CPF_FED_STATUS__FED_ERROR__SHIFT 0x0 +#define CPF_FED_STATUS__FED_ERROR_ID__SHIFT 0x1 +#define CPF_FED_STATUS__FED_RING_ID__SHIFT 0x18 +#define CPF_FED_STATUS__FED_VF_ID__SHIFT 0x1a +#define CPF_FED_STATUS__FED_VF_PF__SHIFT 0x1f +#define CPF_FED_STATUS__FED_ERROR_MASK 0x00000001L +#define CPF_FED_STATUS__FED_ERROR_ID_MASK 0x0000003EL +#define CPF_FED_STATUS__FED_RING_ID_MASK 0x03000000L +#define CPF_FED_STATUS__FED_VF_ID_MASK 0x7C000000L +#define CPF_FED_STATUS__FED_VF_PF_MASK 0x80000000L +//CPC_FED_STATUS +#define CPC_FED_STATUS__FED_ERROR__SHIFT 0x0 +#define CPC_FED_STATUS__FED_ERROR_ID__SHIFT 0x1 +#define CPC_FED_STATUS__FED_RING_ID__SHIFT 0x18 +#define CPC_FED_STATUS__FED_VF_ID__SHIFT 0x1a +#define CPC_FED_STATUS__FED_VF_PF__SHIFT 0x1f +#define CPC_FED_STATUS__FED_ERROR_MASK 0x00000001L +#define CPC_FED_STATUS__FED_ERROR_ID_MASK 0x0000003EL +#define CPC_FED_STATUS__FED_RING_ID_MASK 0x03000000L +#define CPC_FED_STATUS__FED_VF_ID_MASK 0x7C000000L +#define CPC_FED_STATUS__FED_VF_PF_MASK 0x80000000L +//CPG_FED_STATUS +#define CPG_FED_STATUS__FED_ERROR__SHIFT 0x0 +#define CPG_FED_STATUS__FED_ERROR_ID__SHIFT 0x1 +#define CPG_FED_STATUS__FED_RING_ID__SHIFT 0x18 +#define CPG_FED_STATUS__FED_VF_ID__SHIFT 0x1a +#define CPG_FED_STATUS__FED_VF_PF__SHIFT 0x1f +#define CPG_FED_STATUS__FED_ERROR_MASK 0x00000001L +#define CPG_FED_STATUS__FED_ERROR_ID_MASK 0x0000003EL +#define CPG_FED_STATUS__FED_RING_ID_MASK 0x03000000L +#define CPG_FED_STATUS__FED_VF_ID_MASK 0x7C000000L +#define CPG_FED_STATUS__FED_VF_PF_MASK 0x80000000L +//CP_IB1_BUFFER_COUNT +#define CP_IB1_BUFFER_COUNT__COUNT__SHIFT 0x0 +#define CP_IB1_BUFFER_COUNT__COUNT_MASK 0x000FFFFFL +//CP_IB2_BUFFER_COUNT +#define CP_IB2_BUFFER_COUNT__COUNT__SHIFT 0x0 +#define CP_IB2_BUFFER_COUNT__COUNT_MASK 0x000FFFFFL +//CP_INT_CNTL_RING0 +#define CP_INT_CNTL_RING0__RESUME_INT_ENABLE__SHIFT 0x8 +#define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE__SHIFT 0x9 +#define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE__SHIFT 0xa +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING0__RESUME_INT_ENABLE_MASK 0x00000100L +#define CP_INT_CNTL_RING0__SUSPEND_INT_ENABLE_MASK 0x00000200L +#define CP_INT_CNTL_RING0__DMA_WATCH_INT_ENABLE_MASK 0x00000400L +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x00000800L +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_INT_CNTL_RING0__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x00040000L +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x00080000L +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x00100000L +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x00200000L +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x00400000L +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_DEBUG_2 +#define CP_DEBUG_2__CPG_CHIU_HDM_OVERRIDE__SHIFT 0x9 +#define CP_DEBUG_2__CPG_CHIU_TEE_OVERRIDE__SHIFT 0xa +#define CP_DEBUG_2__HEADER_TRAP_DIS__SHIFT 0xb +#define CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE__SHIFT 0xe +#define CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE__SHIFT 0xf +#define CP_DEBUG_2__NOP_DISCARD_DISABLE__SHIFT 0x10 +#define CP_DEBUG_2__DC_INTERLEAVE_DISABLE__SHIFT 0x11 +#define CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE__SHIFT 0x1b +#define CP_DEBUG_2__DC_FORCE_CLK_EN__SHIFT 0x1c +#define CP_DEBUG_2__DC_DISABLE_BROADCAST__SHIFT 0x1d +#define CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE__SHIFT 0x1e +#define CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE__SHIFT 0x1f +#define CP_DEBUG_2__CPG_CHIU_HDM_OVERRIDE_MASK 0x00000200L +#define CP_DEBUG_2__CPG_CHIU_TEE_OVERRIDE_MASK 0x00000400L +#define CP_DEBUG_2__HEADER_TRAP_DIS_MASK 0x00000800L +#define CP_DEBUG_2__RB_PACKET_INJECTOR_DISABLE_MASK 0x00004000L +#define CP_DEBUG_2__CNTX_DONE_COPY_STATE_DISABLE_MASK 0x00008000L +#define CP_DEBUG_2__NOP_DISCARD_DISABLE_MASK 0x00010000L +#define CP_DEBUG_2__DC_INTERLEAVE_DISABLE_MASK 0x00020000L +#define CP_DEBUG_2__BC_LOOKUP_CB_DB_FLUSH_DISABLE_MASK 0x08000000L +#define CP_DEBUG_2__DC_FORCE_CLK_EN_MASK 0x10000000L +#define CP_DEBUG_2__DC_DISABLE_BROADCAST_MASK 0x20000000L +#define CP_DEBUG_2__NOT_EOP_HW_DETECT_DISABLE_MASK 0x40000000L +#define CP_DEBUG_2__PFP_DDID_HW_DETECT_DISABLE_MASK 0x80000000L +//CP_INT_STATUS_RING0 +#define CP_INT_STATUS_RING0__RESUME_INT_STAT__SHIFT 0x8 +#define CP_INT_STATUS_RING0__SUSPEND_INT_STAT__SHIFT 0x9 +#define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT__SHIFT 0xa +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING0__GPF_INT_STAT__SHIFT 0x10 +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING0__RESUME_INT_STAT_MASK 0x00000100L +#define CP_INT_STATUS_RING0__SUSPEND_INT_STAT_MASK 0x00000200L +#define CP_INT_STATUS_RING0__DMA_WATCH_INT_STAT_MASK 0x00000400L +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x00000800L +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x00004000L +#define CP_INT_STATUS_RING0__GPF_INT_STAT_MASK 0x00010000L +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x00020000L +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x00040000L +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x00080000L +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x00100000L +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x00200000L +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x00400000L +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x00800000L +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x01000000L +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x04000000L +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x08000000L +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000L +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000L +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000L +//CP_ME_F32_INTERRUPT +#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT__SHIFT 0x1 +#define CP_ME_F32_INTERRUPT__ME_F32_INT_2__SHIFT 0x2 +#define CP_ME_F32_INTERRUPT__ME_F32_INT_3__SHIFT 0x3 +#define CP_ME_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_ME_F32_INTERRUPT__TIME_STAMP_INT_MASK 0x00000002L +#define CP_ME_F32_INTERRUPT__ME_F32_INT_2_MASK 0x00000004L +#define CP_ME_F32_INTERRUPT__ME_F32_INT_3_MASK 0x00000008L +//CP_PFP_F32_INTERRUPT +#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT__SHIFT 0x0 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3__SHIFT 0x3 +#define CP_PFP_F32_INTERRUPT__ECC_ERROR_INT_MASK 0x00000001L +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_PFP_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_PFP_F32_INTERRUPT__PFP_F32_INT_3_MASK 0x00000008L +//CP_MEC1_F32_INTERRUPT +#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF__SHIFT 0xa +#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA__SHIFT 0xb +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC__SHIFT 0xc +#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT__SHIFT 0xd +#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT__SHIFT 0xe +#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT__SHIFT 0xf +#define CP_MEC1_F32_INTERRUPT__EDC_ROQ_FED_INT_MASK 0x00000001L +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x00000002L +#define CP_MEC1_F32_INTERRUPT__RESERVED_BIT_ERR_INT_MASK 0x00000004L +#define CP_MEC1_F32_INTERRUPT__EDC_TC_FED_INT_MASK 0x00000008L +#define CP_MEC1_F32_INTERRUPT__EDC_GDS_FED_INT_MASK 0x00000010L +#define CP_MEC1_F32_INTERRUPT__EDC_SCRATCH_FED_INT_MASK 0x00000020L +#define CP_MEC1_F32_INTERRUPT__WAVE_RESTORE_INT_MASK 0x00000040L +#define CP_MEC1_F32_INTERRUPT__SUA_VIOLATION_INT_MASK 0x00000080L +#define CP_MEC1_F32_INTERRUPT__EDC_DMA_FED_INT_MASK 0x00000100L +#define CP_MEC1_F32_INTERRUPT__IQ_TIMER_INT_MASK 0x00000200L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPF_MASK 0x00000400L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_DMA_MASK 0x00000800L +#define CP_MEC1_F32_INTERRUPT__GPF_INT_CPC_MASK 0x00001000L +#define CP_MEC1_F32_INTERRUPT__EDC_SR_MEM_FED_INT_MASK 0x00002000L +#define CP_MEC1_F32_INTERRUPT__QUEUE_MESSAGE_INT_MASK 0x00004000L +#define CP_MEC1_F32_INTERRUPT__FATAL_EDC_ERROR_INT_MASK 0x00008000L +//CP_PWR_CNTL +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0__SHIFT 0x14 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1__SHIFT 0x15 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2__SHIFT 0x16 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3__SHIFT 0x17 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x00000001L +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x00000002L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x00000100L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x00000200L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x00000400L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x00000800L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x00010000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x00020000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x00040000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x00080000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE0_MASK 0x00100000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE1_MASK 0x00200000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE2_MASK 0x00400000L +#define CP_PWR_CNTL__CMP_CLK_HALT_ME3_PIPE3_MASK 0x00800000L +//CP_ECC_FIRSTOCCURRENCE +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 +#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x00000003L +#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0x000000F0L +#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x00000300L +#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0x00000C00L +#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0x000F0000L +//CP_ECC_FIRSTOCCURRENCE_RING0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xFFFFFFFFL +//GB_EDC_MODE +#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf +#define GB_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 +#define GB_EDC_MODE__GATE_FUE__SHIFT 0x11 +#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 +#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d +#define GB_EDC_MODE__BYPASS__SHIFT 0x1f +#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L +#define GB_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L +#define GB_EDC_MODE__GATE_FUE_MASK 0x00020000L +#define GB_EDC_MODE__DED_MODE_MASK 0x00300000L +#define GB_EDC_MODE__PROP_FED_MASK 0x20000000L +#define GB_EDC_MODE__BYPASS_MASK 0x80000000L +//CP_DEBUG +#define CP_DEBUG__PERFMON_RING_SEL__SHIFT 0x0 +#define CP_DEBUG__DEBUG_BUS_SELECT_BITS__SHIFT 0x2 +#define CP_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT 0x8 +#define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 +#define CP_DEBUG__PACKET_FILTER_DISABLE__SHIFT 0xa +#define CP_DEBUG__NOT_EOP_PREEMPT_DISABLE__SHIFT 0xb +#define CP_DEBUG__CPG_CHIU_RO_DISABLE__SHIFT 0xc +#define CP_DEBUG__CPG_GCR_CNTL_BYPASS__SHIFT 0xd +#define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE__SHIFT 0xe +#define CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE__SHIFT 0xf +#define CP_DEBUG__SURFSYNC_CNTX_RDADDR__SHIFT 0x10 +#define CP_DEBUG__CPG_DATA_POISONING_INT_DISABLE__SHIFT 0x13 +#define CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT 0x14 +#define CP_DEBUG__INTERRUPT_DISABLE__SHIFT 0x16 +#define CP_DEBUG__PREDICATE_DISABLE__SHIFT 0x17 +#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 +#define CP_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 +#define CP_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x1a +#define CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE__SHIFT 0x1b +#define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x1c +#define CP_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x1d +#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE__SHIFT 0x1e +#define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE__SHIFT 0x1f +#define CP_DEBUG__PERFMON_RING_SEL_MASK 0x00000003L +#define CP_DEBUG__DEBUG_BUS_SELECT_BITS_MASK 0x000000FCL +#define CP_DEBUG__DEBUG_BUS_FLOP_EN_MASK 0x00000100L +#define CP_DEBUG__CPG_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L +#define CP_DEBUG__PACKET_FILTER_DISABLE_MASK 0x00000400L +#define CP_DEBUG__NOT_EOP_PREEMPT_DISABLE_MASK 0x00000800L +#define CP_DEBUG__CPG_CHIU_RO_DISABLE_MASK 0x00001000L +#define CP_DEBUG__CPG_GCR_CNTL_BYPASS_MASK 0x00002000L +#define CP_DEBUG__CPG_RAM_CLK_GATING_DISABLE_MASK 0x00004000L +#define CP_DEBUG__CPG_UTCL1_ERROR_HALT_DISABLE_MASK 0x00008000L +#define CP_DEBUG__SURFSYNC_CNTX_RDADDR_MASK 0x00070000L +#define CP_DEBUG__CPG_DATA_POISONING_INT_DISABLE_MASK 0x00080000L +#define CP_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK 0x00100000L +#define CP_DEBUG__INTERRUPT_DISABLE_MASK 0x00400000L +#define CP_DEBUG__PREDICATE_DISABLE_MASK 0x00800000L +#define CP_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L +#define CP_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L +#define CP_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L +#define CP_DEBUG__CPG_CHIU_MTYPE_OVERRIDE_MASK 0x08000000L +#define CP_DEBUG__CPG_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L +#define CP_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L +#define CP_DEBUG__CS_PIPELINE_RESET_DISABLE_MASK 0x40000000L +#define CP_DEBUG__IB_PACKET_INJECTOR_DISABLE_MASK 0x80000000L +//CP_CPF_DEBUG +#define CP_CPF_DEBUG__PRIVATE_REG_ACC_DISABLE__SHIFT 0x6 +#define CP_CPF_DEBUG__CPF_CHIU_TEE_OVERRIDE__SHIFT 0x7 +#define CP_CPF_DEBUG__CPF_CHIU_HDM_OVERRIDE__SHIFT 0xd +#define CP_CPF_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT 0xe +#define CP_CPF_DEBUG__MES_DOORBELL_HIT_BUSY_OVERRIDE__SHIFT 0xf +#define CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE__SHIFT 0x10 +#define CP_CPF_DEBUG__CPF_GCR_CNTL_BYPASS__SHIFT 0x11 +#define CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE__SHIFT 0x12 +#define CP_CPF_DEBUG__CPF_DATA_POISONING_INT_DISABLE__SHIFT 0x13 +#define CP_CPF_DEBUG__CLOCK_ACTIVE_DELAY_OVERRIDE__SHIFT 0x16 +#define CP_CPF_DEBUG__CLOCK_ACTIVE_OVERRIDE__SHIFT 0x17 +#define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 +#define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 +#define CP_CPF_DEBUG__CE_FETCHER_DISABLE__SHIFT 0x1b +#define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS__SHIFT 0x1d +#define CP_CPF_DEBUG__CPF_CHIU_MTYPE_OVERRIDE__SHIFT 0x1e +#define CP_CPF_DEBUG__DBGU_TRIGGER__SHIFT 0x1f +#define CP_CPF_DEBUG__PRIVATE_REG_ACC_DISABLE_MASK 0x00000040L +#define CP_CPF_DEBUG__CPF_CHIU_TEE_OVERRIDE_MASK 0x00000080L +#define CP_CPF_DEBUG__CPF_CHIU_HDM_OVERRIDE_MASK 0x00002000L +#define CP_CPF_DEBUG__DEBUG_BUS_FLOP_EN_MASK 0x00004000L +#define CP_CPF_DEBUG__MES_DOORBELL_HIT_BUSY_OVERRIDE_MASK 0x00008000L +#define CP_CPF_DEBUG__CPF_REPEATER_FGCG_OVERRIDE_MASK 0x00010000L +#define CP_CPF_DEBUG__CPF_GCR_CNTL_BYPASS_MASK 0x00020000L +#define CP_CPF_DEBUG__CPF_RAM_CLK_GATING_DISABLE_MASK 0x00040000L +#define CP_CPF_DEBUG__CPF_DATA_POISONING_INT_DISABLE_MASK 0x00080000L +#define CP_CPF_DEBUG__CLOCK_ACTIVE_DELAY_OVERRIDE_MASK 0x00400000L +#define CP_CPF_DEBUG__CLOCK_ACTIVE_OVERRIDE_MASK 0x00800000L +#define CP_CPF_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L +#define CP_CPF_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L +#define CP_CPF_DEBUG__CE_FETCHER_DISABLE_MASK 0x08000000L +#define CP_CPF_DEBUG__CPF_PRIORITY_YIELD_ACTIVE_DIS_MASK 0x20000000L +#define CP_CPF_DEBUG__CPF_CHIU_MTYPE_OVERRIDE_MASK 0x40000000L +#define CP_CPF_DEBUG__DBGU_TRIGGER_MASK 0x80000000L +//CP_CPC_DEBUG +#define CP_CPC_DEBUG__PIPE_SELECT__SHIFT 0x0 +#define CP_CPC_DEBUG__ME_SELECT__SHIFT 0x2 +#define CP_CPC_DEBUG__CPC_CHIU_TEE_OVERRIDE__SHIFT 0x3 +#define CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE__SHIFT 0x4 +#define CP_CPC_DEBUG__CPC_CHIU_HDM_OVERRIDE__SHIFT 0x5 +#define CP_CPC_DEBUG__DISP_MODE1_FAST_SKIP_DISABLE__SHIFT 0x6 +#define CP_CPC_DEBUG__DISABLE_PER_QUEUE_ADC_STATE_STORE__SHIFT 0xb +#define CP_CPC_DEBUG__ENABLE_CONF_CS_DIST__SHIFT 0xd +#define CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN__SHIFT 0xe +#define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE__SHIFT 0xf +#define CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS__SHIFT 0x11 +#define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE__SHIFT 0x12 +#define CP_CPC_DEBUG__CPC_DATA_POISONING_INT_DISABLE__SHIFT 0x13 +#define CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE__SHIFT 0x14 +#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE__SHIFT 0x15 +#define CP_CPC_DEBUG__INTERRUPT_DISABLE__SHIFT 0x16 +#define CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE__SHIFT 0x17 +#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE__SHIFT 0x18 +#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE__SHIFT 0x19 +#define CP_CPC_DEBUG__EVENT_FILT_DISABLE__SHIFT 0x1a +#define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE__SHIFT 0x1c +#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE__SHIFT 0x1d +#define CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE__SHIFT 0x1e +#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE__SHIFT 0x1f +#define CP_CPC_DEBUG__PIPE_SELECT_MASK 0x00000003L +#define CP_CPC_DEBUG__ME_SELECT_MASK 0x00000004L +#define CP_CPC_DEBUG__CPC_CHIU_TEE_OVERRIDE_MASK 0x00000008L +#define CP_CPC_DEBUG__ADC_INTERLEAVE_DISABLE_MASK 0x00000010L +#define CP_CPC_DEBUG__CPC_CHIU_HDM_OVERRIDE_MASK 0x00000020L +#define CP_CPC_DEBUG__DISP_MODE1_FAST_SKIP_DISABLE_MASK 0x00000040L +#define CP_CPC_DEBUG__DISABLE_PER_QUEUE_ADC_STATE_STORE_MASK 0x00000800L +#define CP_CPC_DEBUG__ENABLE_CONF_CS_DIST_MASK 0x00002000L +#define CP_CPC_DEBUG__DEBUG_BUS_FLOP_EN_MASK 0x00004000L +#define CP_CPC_DEBUG__CPC_REPEATER_FGCG_OVERRIDE_MASK 0x00008000L +#define CP_CPC_DEBUG__CPC_GCR_CNTL_BYPASS_MASK 0x00020000L +#define CP_CPC_DEBUG__CPC_RAM_CLK_GATING_DISABLE_MASK 0x00040000L +#define CP_CPC_DEBUG__CPC_DATA_POISONING_INT_DISABLE_MASK 0x00080000L +#define CP_CPC_DEBUG__PRIV_VIOLATION_WRITE_DISABLE_MASK 0x00100000L +#define CP_CPC_DEBUG__UCODE_ECC_ERROR_DISABLE_MASK 0x00200000L +#define CP_CPC_DEBUG__INTERRUPT_DISABLE_MASK 0x00400000L +#define CP_CPC_DEBUG__CPC_CHIU_RO_DISABLE_MASK 0x00800000L +#define CP_CPC_DEBUG__UNDERFLOW_BUSY_DISABLE_MASK 0x01000000L +#define CP_CPC_DEBUG__OVERFLOW_BUSY_DISABLE_MASK 0x02000000L +#define CP_CPC_DEBUG__EVENT_FILT_DISABLE_MASK 0x04000000L +#define CP_CPC_DEBUG__CPC_TC_ONE_CYCLE_WRITE_DISABLE_MASK 0x10000000L +#define CP_CPC_DEBUG__CS_STATE_FILT_DISABLE_MASK 0x20000000L +#define CP_CPC_DEBUG__CPC_CHIU_MTYPE_OVERRIDE_MASK 0x40000000L +#define CP_CPC_DEBUG__ME2_UCODE_RAM_ENABLE_MASK 0x80000000L +//CP_PQ_WPTR_POLL_CNTL +#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT__SHIFT 0x1d +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e +#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f +#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0x000000FFL +#define CP_PQ_WPTR_POLL_CNTL__DISABLE_PEND_REQ_ONE_SHOT_MASK 0x20000000L +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000L +#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000L +//CP_PQ_WPTR_POLL_CNTL1 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xFFFFFFFFL +//CP_ME1_PIPE0_INT_CNTL +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE1_INT_CNTL +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE2_INT_CNTL +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE3_INT_CNTL +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CP_ME1_PIPE0_INT_STATUS +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE0_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE1_INT_STATUS +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE1_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE2_INT_STATUS +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE2_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_PIPE3_INT_STATUS +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_PIPE3_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_ME1_INT_STAT_DEBUG +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED__SHIFT 0x10 +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x00001000L +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x00002000L +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x00004000L +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CP_ME1_INT_STAT_DEBUG__GPF_INT_ASSERTED_MASK 0x00010000L +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x00020000L +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x00800000L +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x01000000L +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x04000000L +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x08000000L +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000L +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000L +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000L +//CP_GFX_QUEUE_INDEX +#define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS__SHIFT 0x0 +#define CP_GFX_QUEUE_INDEX__PIPE_ID__SHIFT 0x4 +#define CP_GFX_QUEUE_INDEX__QUEUE_ID__SHIFT 0x8 +#define CP_GFX_QUEUE_INDEX__QUEUE_ACCESS_MASK 0x00000001L +#define CP_GFX_QUEUE_INDEX__PIPE_ID_MASK 0x00000030L +#define CP_GFX_QUEUE_INDEX__QUEUE_ID_MASK 0x00000700L +//CC_GC_EDC_CONFIG +#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x00000002L +//CP_ME1_PIPE_PRIORITY_CNTS +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_ME1_PIPE0_PRIORITY +#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE1_PRIORITY +#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE2_PRIORITY +#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_ME1_PIPE3_PRIORITY +#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_PFP_PRGRM_CNTR_START +#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_ME_PRGRM_CNTR_START +#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_MEC1_PRGRM_CNTR_START +#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0x000FFFFFL +//CP_PFP_INTR_ROUTINE_START +#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL +//CP_ME_INTR_ROUTINE_START +#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL +//CP_MEC1_INTR_ROUTINE_START +#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0x000FFFFFL +//CP_CONTEXT_CNTL +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX__SHIFT 0x10 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_GE_CNTX_MASK 0x0000000FL +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x000000F0L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_GE_CNTX_MASK 0x000F0000L +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x00F00000L +//CP_MAX_CONTEXT +#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 +#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x00000007L +//CP_IQ_WAIT_TIME1 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 +#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L +#define CP_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L +//CP_IQ_WAIT_TIME2 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 +#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL +#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L +#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L +//CP_RB0_BASE_HI +#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_VMID_RESET +#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 +#define CP_VMID_RESET__PIPE0_QUEUES__SHIFT 0x10 +#define CP_VMID_RESET__PIPE1_QUEUES__SHIFT 0x18 +#define CP_VMID_RESET__RESET_REQUEST_MASK 0x0000FFFFL +#define CP_VMID_RESET__PIPE0_QUEUES_MASK 0x00FF0000L +#define CP_VMID_RESET__PIPE1_QUEUES_MASK 0xFF000000L +//CPC_INT_CNTL +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CPC_INT_CNTL__GPF_INT_ENABLE__SHIFT 0x10 +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x00001000L +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x00002000L +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x00004000L +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x00008000L +#define CPC_INT_CNTL__GPF_INT_ENABLE_MASK 0x00010000L +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x00020000L +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x00800000L +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x01000000L +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x04000000L +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x08000000L +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000L +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000L +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000L +//CPC_INT_STATUS +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CPC_INT_STATUS__GPF_INT_STATUS__SHIFT 0x10 +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x00001000L +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x00002000L +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x00004000L +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x00008000L +#define CPC_INT_STATUS__GPF_INT_STATUS_MASK 0x00010000L +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x00020000L +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x00800000L +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x01000000L +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x04000000L +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x08000000L +#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000L +#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000L +#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000L +//CP_VMID_PREEMPT +#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 +#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 +#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0x0000FFFFL +#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0x000F0000L +//CPC_INT_CNTX_ID +#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_PQ_STATUS +#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_PQ_STATUS__DOORBELL_UPDATED_EN__SHIFT 0x2 +#define CP_PQ_STATUS__DOORBELL_UPDATED_MODE__SHIFT 0x3 +#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +#define CP_PQ_STATUS__DOORBELL_UPDATED_EN_MASK 0x00000004L +#define CP_PQ_STATUS__DOORBELL_UPDATED_MODE_MASK 0x00000008L +//CP_PFP_PRGRM_CNTR_START_HI +#define CP_PFP_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_MAX_DRAW_COUNT +#define CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT__SHIFT 0x0 +#define CP_MAX_DRAW_COUNT__MAX_DRAW_COUNT_MASK 0xFFFFFFFFL +//CP_VMID_STATUS +#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 +#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 +#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0x0000FFFFL +#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xFFFF0000L +//CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L +//CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CPC_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +//CPC_SUSPEND_CTX_SAVE_CONTROL +#define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define CPC_SUSPEND_CTX_SAVE_CONTROL__SCOPE__SHIFT 0x5 +#define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CPC_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L +#define CPC_SUSPEND_CTX_SAVE_CONTROL__SCOPE_MASK 0x00000060L +#define CPC_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L +//CPC_SUSPEND_CNTL_STACK_OFFSET +#define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CPC_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//CPC_SUSPEND_CNTL_STACK_SIZE +#define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define CPC_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L +//CPC_SUSPEND_WG_STATE_OFFSET +#define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CPC_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL +//CPC_SUSPEND_CTX_SAVE_SIZE +#define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define CPC_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK 0x03FFF000L +//CPC_OS_PIPES +#define CPC_OS_PIPES__OS_PIPES__SHIFT 0x0 +#define CPC_OS_PIPES__OS_PIPES_MASK 0x000000FFL +//CP_SUSPEND_RESUME_REQ +#define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT 0x0 +#define CP_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT 0x1 +#define CP_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK 0x00000001L +#define CP_SUSPEND_RESUME_REQ__RESUME_REQ_MASK 0x00000002L +//CP_SUSPEND_CNTL +#define CP_SUSPEND_CNTL__SUSPEND_MODE__SHIFT 0x0 +#define CP_SUSPEND_CNTL__SUSPEND_ENABLE__SHIFT 0x1 +#define CP_SUSPEND_CNTL__RESUME_LOCK__SHIFT 0x2 +#define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE__SHIFT 0x3 +#define CP_SUSPEND_CNTL__SUSPEND_MODE_MASK 0x00000001L +#define CP_SUSPEND_CNTL__SUSPEND_ENABLE_MASK 0x00000002L +#define CP_SUSPEND_CNTL__RESUME_LOCK_MASK 0x00000004L +#define CP_SUSPEND_CNTL__ACE_SUSPEND_ACTIVE_MASK 0x00000008L +//CP_IQ_WAIT_TIME3 +#define CP_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT 0x0 +#define CP_IQ_WAIT_TIME3__SUSPEND_QUE_MASK 0x000000FFL +//CPC_DDID_BASE_ADDR_LO +#define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 +#define CPC_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L +//CP_DDID_BASE_ADDR_LO +#define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 +#define CP_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L +//CPC_DDID_BASE_ADDR_HI +#define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CPC_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x01FFFFFFL +//CP_DDID_BASE_ADDR_HI +#define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x01FFFFFFL +//CPC_DDID_CNTL +#define CPC_DDID_CNTL__THRESHOLD__SHIFT 0x0 +#define CPC_DDID_CNTL__SIZE__SHIFT 0x10 +#define CPC_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 +#define CPC_DDID_CNTL__SCOPE__SHIFT 0x18 +#define CPC_DDID_CNTL__POLICY__SHIFT 0x1c +#define CPC_DDID_CNTL__MODE__SHIFT 0x1e +#define CPC_DDID_CNTL__ENABLE__SHIFT 0x1f +#define CPC_DDID_CNTL__THRESHOLD_MASK 0x000000FFL +#define CPC_DDID_CNTL__SIZE_MASK 0x00010000L +#define CPC_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L +#define CPC_DDID_CNTL__SCOPE_MASK 0x03000000L +#define CPC_DDID_CNTL__POLICY_MASK 0x30000000L +#define CPC_DDID_CNTL__MODE_MASK 0x40000000L +#define CPC_DDID_CNTL__ENABLE_MASK 0x80000000L +//CP_DDID_CNTL +#define CP_DDID_CNTL__THRESHOLD__SHIFT 0x0 +#define CP_DDID_CNTL__SIZE__SHIFT 0x10 +#define CP_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 +#define CP_DDID_CNTL__VMID__SHIFT 0x14 +#define CP_DDID_CNTL__VMID_SEL__SHIFT 0x18 +#define CP_DDID_CNTL__SCOPE__SHIFT 0x1a +#define CP_DDID_CNTL__POLICY__SHIFT 0x1c +#define CP_DDID_CNTL__MODE__SHIFT 0x1e +#define CP_DDID_CNTL__ENABLE__SHIFT 0x1f +#define CP_DDID_CNTL__THRESHOLD_MASK 0x000000FFL +#define CP_DDID_CNTL__SIZE_MASK 0x00010000L +#define CP_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L +#define CP_DDID_CNTL__VMID_MASK 0x00F00000L +#define CP_DDID_CNTL__VMID_SEL_MASK 0x01000000L +#define CP_DDID_CNTL__SCOPE_MASK 0x0C000000L +#define CP_DDID_CNTL__POLICY_MASK 0x30000000L +#define CP_DDID_CNTL__MODE_MASK 0x40000000L +#define CP_DDID_CNTL__ENABLE_MASK 0x80000000L +//CP_GFX_DDID_INFLIGHT_COUNT +#define CP_GFX_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL +//CP_GFX_DDID_WPTR +#define CP_GFX_DDID_WPTR__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_WPTR__COUNT_MASK 0x0000FFFFL +//CP_GFX_DDID_RPTR +#define CP_GFX_DDID_RPTR__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_RPTR__COUNT_MASK 0x0000FFFFL +//CP_GFX_DDID_DELTA_RPT_COUNT +#define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 +#define CP_GFX_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL +//CP_GFX_HPD_STATUS0 +#define CP_GFX_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 +#define CP_GFX_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 +#define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 +#define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE__SHIFT 0x10 +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 +#define CP_GFX_HPD_STATUS0__SUSPEND_REQ__SHIFT 0x1c +#define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID__SHIFT 0x1d +#define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID__SHIFT 0x1e +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f +#define CP_GFX_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL +#define CP_GFX_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L +#define CP_GFX_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L +#define CP_GFX_HPD_STATUS0__FORCE_MAPPED_QUEUE_MASK 0x00070000L +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L +#define CP_GFX_HPD_STATUS0__SUSPEND_REQ_MASK 0x10000000L +#define CP_GFX_HPD_STATUS0__ENABLE_OVERIDE_QUEUEID_MASK 0x20000000L +#define CP_GFX_HPD_STATUS0__OVERIDE_QUEUEID_MASK 0x40000000L +#define CP_GFX_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L +//CP_GFX_HPD_CONTROL0 +#define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE__SHIFT 0x0 +#define CP_GFX_HPD_CONTROL0__PIPE_HOLDING__SHIFT 0x4 +#define CP_GFX_HPD_CONTROL0__SUSPEND_ENABLE_MASK 0x00000001L +#define CP_GFX_HPD_CONTROL0__PIPE_HOLDING_MASK 0x00000010L +//CP_GFX_HPD_OSPRE_FENCE_ADDR_LO +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_GFX_HPD_OSPRE_FENCE_ADDR_HI +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_GFX_HPD_OSPRE_FENCE_ADDR_HI__RSVD_MASK 0xFFFF0000L +//CP_GFX_HPD_OSPRE_FENCE_DATA_LO +#define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_GFX_HPD_OSPRE_FENCE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL +//CP_GFX_HPD_OSPRE_FENCE_DATA_HI +#define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_GFX_HPD_OSPRE_FENCE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL +//CP_GFX_INDEX_MUTEX +#define CP_GFX_INDEX_MUTEX__REQUEST__SHIFT 0x0 +#define CP_GFX_INDEX_MUTEX__CLIENTID__SHIFT 0x1 +#define CP_GFX_INDEX_MUTEX__REQUEST_MASK 0x00000001L +#define CP_GFX_INDEX_MUTEX__CLIENTID_MASK 0x0000000EL +//CP_ME_PRGRM_CNTR_START_HI +#define CP_ME_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_PFP_INTR_ROUTINE_START_HI +#define CP_PFP_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START_HI__IR_START_MASK 0x3FFFFFFFL +//CP_ME_INTR_ROUTINE_START_HI +#define CP_ME_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START_HI__IR_START_MASK 0x3FFFFFFFL +//CP_GFX_MQD_BASE_ADDR +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_GFX_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_GFX_MQD_BASE_ADDR_HI +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID__SHIFT 0x1c +#define CP_GFX_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +#define CP_GFX_MQD_BASE_ADDR_HI__APP_VMID_MASK 0xF0000000L +//CP_GFX_HQD_ACTIVE +#define CP_GFX_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_GFX_HQD_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_GFX_HQD_VMID +#define CP_GFX_HQD_VMID__VMID__SHIFT 0x0 +#define CP_GFX_HQD_VMID__VMID_MASK 0x0000000FL +//CP_GFX_HQD_QUEUE_PRIORITY +#define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_GFX_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL +//CP_GFX_HQD_QUANTUM +#define CP_GFX_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x3 +#define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f +#define CP_GFX_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L +#define CP_GFX_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000018L +#define CP_GFX_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x0000FF00L +#define CP_GFX_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L +//CP_GFX_HQD_BASE +#define CP_GFX_HQD_BASE__RB_BASE__SHIFT 0x0 +#define CP_GFX_HQD_BASE__RB_BASE_MASK 0xFFFFFFFFL +//CP_GFX_HQD_BASE_HI +#define CP_GFX_HQD_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_GFX_HQD_BASE_HI__RB_BASE_HI_MASK 0x000000FFL +//CP_GFX_HQD_RPTR +#define CP_GFX_HQD_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_GFX_HQD_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_GFX_HQD_RPTR_ADDR +#define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_GFX_HQD_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFCL +//CP_GFX_HQD_RPTR_ADDR_HI +#define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_GFX_HQD_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_WPTR_POLL_ADDR_LO +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xFFFFFFFCL +//CP_RB_WPTR_POLL_ADDR_HI +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0x0000FFFFL +//CP_RB_DOORBELL_CONTROL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_GFX_HQD_OFFSET +#define CP_GFX_HQD_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET__SHIFT 0x1f +#define CP_GFX_HQD_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +#define CP_GFX_HQD_OFFSET__DISABLE_RB_OFFSET_MASK 0x80000000L +//CP_GFX_HQD_CNTL +#define CP_GFX_HQD_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_GFX_HQD_CNTL__TMZ_STATE__SHIFT 0x6 +#define CP_GFX_HQD_CNTL__TMZ_MATCH__SHIFT 0x7 +#define CP_GFX_HQD_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_GFX_HQD_CNTL__RB_NON_PRIV__SHIFT 0xf +#define CP_GFX_HQD_CNTL__BUF_SWAP__SHIFT 0x10 +#define CP_GFX_HQD_CNTL__SCOPE__SHIFT 0x12 +#define CP_GFX_HQD_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_GFX_HQD_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_HQD_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_GFX_HQD_CNTL__RB_EXE__SHIFT 0x1c +#define CP_GFX_HQD_CNTL__KMD_QUEUE__SHIFT 0x1d +#define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_GFX_HQD_CNTL__RB_BUFSZ_MASK 0x0000003FL +#define CP_GFX_HQD_CNTL__TMZ_STATE_MASK 0x00000040L +#define CP_GFX_HQD_CNTL__TMZ_MATCH_MASK 0x00000080L +#define CP_GFX_HQD_CNTL__RB_BLKSZ_MASK 0x00003F00L +#define CP_GFX_HQD_CNTL__RB_NON_PRIV_MASK 0x00008000L +#define CP_GFX_HQD_CNTL__BUF_SWAP_MASK 0x00030000L +#define CP_GFX_HQD_CNTL__SCOPE_MASK 0x000C0000L +#define CP_GFX_HQD_CNTL__MIN_AVAILSZ_MASK 0x00300000L +#define CP_GFX_HQD_CNTL__MIN_IB_AVAILSZ_MASK 0x00C00000L +#define CP_GFX_HQD_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_GFX_HQD_CNTL__RB_NO_UPDATE_MASK 0x08000000L +#define CP_GFX_HQD_CNTL__RB_EXE_MASK 0x10000000L +#define CP_GFX_HQD_CNTL__KMD_QUEUE_MASK 0x20000000L +#define CP_GFX_HQD_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000L +//CP_GFX_HQD_CSMD_RPTR +#define CP_GFX_HQD_CSMD_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_GFX_HQD_CSMD_RPTR__RB_RPTR_MASK 0x000FFFFFL +//CP_GFX_HQD_WPTR +#define CP_GFX_HQD_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_GFX_HQD_WPTR__RB_WPTR_MASK 0xFFFFFFFFL +//CP_GFX_HQD_WPTR_HI +#define CP_GFX_HQD_WPTR_HI__RB_WPTR__SHIFT 0x0 +#define CP_GFX_HQD_WPTR_HI__RB_WPTR_MASK 0xFFFFFFFFL +//CP_GFX_HQD_DEQUEUE_REQUEST +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_GFX_HQD_DEQUEUE_REQUEST__REQ_TYPE__SHIFT 0x1 +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x00000001L +#define CP_GFX_HQD_DEQUEUE_REQUEST__REQ_TYPE_MASK 0x0000000EL +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L +#define CP_GFX_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L +#define CP_GFX_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L +//CP_GFX_HQD_MAPPED +#define CP_GFX_HQD_MAPPED__MAPPED__SHIFT 0x0 +#define CP_GFX_HQD_MAPPED__MAPPED_MASK 0x00000001L +//CP_GFX_HQD_QUE_MGR_CONTROL +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT__SHIFT 0x0 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE__SHIFT 0x4 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT__SHIFT 0x5 +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN__SHIFT 0x6 +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN__SHIFT 0x7 +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE__SHIFT 0x8 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE__SHIFT 0xb +#define CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE__SHIFT 0xd +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR__SHIFT 0xf +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE__SHIFT 0x10 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE__SHIFT 0x11 +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT__SHIFT 0x12 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG__SHIFT 0x17 +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_IDLE_QUEUE_DISCONNECT_MASK 0x00000001L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_CONNECT_HANDSHAKE_MASK 0x00000010L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_FETCHER_DISCONNECT_MASK 0x00000020L +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_ACTIVE_EN_MASK 0x00000040L +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_ALLOW_DB_UPDATE_EN_MASK 0x00000080L +#define CP_GFX_HQD_QUE_MGR_CONTROL__FORCE_QUEUE_MASK 0x00000700L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_OFFSET_UPDATE_MASK 0x00000800L +#define CP_GFX_HQD_QUE_MGR_CONTROL__PRIORITY_PREEMPT_DISABLE_MASK 0x00002000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_QUEUE_MGR_MASK 0x00008000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_IDLE_MESSAGE_MASK 0x00010000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_SWITCH_MESSAGE_IDLE_MASK 0x00020000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__ENABLE_SWITCH_MSG_PREEMPT_MASK 0x00040000L +#define CP_GFX_HQD_QUE_MGR_CONTROL__DISABLE_MAPPED_QUEUE_IDLE_MSG_MASK 0x00800000L +//CP_GFX_HQD_IQ_TIMER +#define CP_GFX_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_GFX_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b +#define CP_GFX_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c +#define CP_GFX_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_GFX_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL +#define CP_GFX_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L +#define CP_GFX_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L +#define CP_GFX_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L +#define CP_GFX_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L +#define CP_GFX_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L +#define CP_GFX_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L +#define CP_GFX_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L +#define CP_GFX_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L +//CP_GFX_HQD_HQ_STATUS0 +#define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 +#define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS__SHIFT 0x4 +#define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK__SHIFT 0x6 +#define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e +#define CP_GFX_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x00000001L +#define CP_GFX_HQD_HQ_STATUS0__OS_PREEMPT_STATUS_MASK 0x00000030L +#define CP_GFX_HQD_HQ_STATUS0__PREEMPT_ACK_MASK 0x00000040L +#define CP_GFX_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L +//CP_GFX_HQD_HQ_CONTROL0 +#define CP_GFX_HQD_HQ_CONTROL0__COMMAND__SHIFT 0x0 +#define CP_GFX_HQD_HQ_CONTROL0__SPARES__SHIFT 0x4 +#define CP_GFX_HQD_HQ_CONTROL0__COMMAND_MASK 0x0000000FL +#define CP_GFX_HQD_HQ_CONTROL0__SPARES_MASK 0x000000F0L +//CP_GFX_MQD_CONTROL +#define CP_GFX_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_GFX_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd +#define CP_GFX_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_GFX_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_MQD_CONTROL__SCOPE__SHIFT 0x1a +#define CP_GFX_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_GFX_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L +#define CP_GFX_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L +#define CP_GFX_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_GFX_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L +#define CP_GFX_MQD_CONTROL__SCOPE_MASK 0x0C000000L +//CP_HQD_GFX_CONTROL +#define CP_HQD_GFX_CONTROL__MESSAGE__SHIFT 0x0 +#define CP_HQD_GFX_CONTROL__MISC__SHIFT 0x4 +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN__SHIFT 0xf +#define CP_HQD_GFX_CONTROL__MESSAGE_MASK 0x0000000FL +#define CP_HQD_GFX_CONTROL__MISC_MASK 0x00007FF0L +#define CP_HQD_GFX_CONTROL__DB_UPDATED_MSG_EN_MASK 0x00008000L +//CP_HQD_GFX_STATUS +#define CP_HQD_GFX_STATUS__STATUS__SHIFT 0x0 +#define CP_HQD_GFX_STATUS__STATUS_MASK 0x0000FFFFL +//CP_DMA_WATCH0_ADDR_LO +#define CP_DMA_WATCH0_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH0_ADDR_LO__ADDR_LO__SHIFT 0x8 +#define CP_DMA_WATCH0_ADDR_LO__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH0_ADDR_LO__ADDR_LO_MASK 0xFFFFFF00L +//CP_DMA_WATCH0_ADDR_HI +#define CP_DMA_WATCH0_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH0_ADDR_HI__RSVD__SHIFT 0x19 +#define CP_DMA_WATCH0_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_WATCH0_ADDR_HI__RSVD_MASK 0xFE000000L +//CP_DMA_WATCH0_MASK +#define CP_DMA_WATCH0_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH0_MASK__MASK__SHIFT 0x8 +#define CP_DMA_WATCH0_MASK__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH0_MASK__MASK_MASK 0xFFFFFF00L +//CP_DMA_WATCH0_CNTL +#define CP_DMA_WATCH0_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH0_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH0_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH0_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH0_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH0_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH0_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH0_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH0_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH0_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH0_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH0_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH1_ADDR_LO +#define CP_DMA_WATCH1_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH1_ADDR_LO__ADDR_LO__SHIFT 0x8 +#define CP_DMA_WATCH1_ADDR_LO__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH1_ADDR_LO__ADDR_LO_MASK 0xFFFFFF00L +//CP_DMA_WATCH1_ADDR_HI +#define CP_DMA_WATCH1_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH1_ADDR_HI__RSVD__SHIFT 0x19 +#define CP_DMA_WATCH1_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_WATCH1_ADDR_HI__RSVD_MASK 0xFE000000L +//CP_DMA_WATCH1_MASK +#define CP_DMA_WATCH1_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH1_MASK__MASK__SHIFT 0x8 +#define CP_DMA_WATCH1_MASK__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH1_MASK__MASK_MASK 0xFFFFFF00L +//CP_DMA_WATCH1_CNTL +#define CP_DMA_WATCH1_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH1_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH1_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH1_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH1_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH1_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH1_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH1_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH1_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH1_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH1_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH1_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH2_ADDR_LO +#define CP_DMA_WATCH2_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH2_ADDR_LO__ADDR_LO__SHIFT 0x8 +#define CP_DMA_WATCH2_ADDR_LO__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH2_ADDR_LO__ADDR_LO_MASK 0xFFFFFF00L +//CP_DMA_WATCH2_ADDR_HI +#define CP_DMA_WATCH2_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH2_ADDR_HI__RSVD__SHIFT 0x19 +#define CP_DMA_WATCH2_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_WATCH2_ADDR_HI__RSVD_MASK 0xFE000000L +//CP_DMA_WATCH2_MASK +#define CP_DMA_WATCH2_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH2_MASK__MASK__SHIFT 0x8 +#define CP_DMA_WATCH2_MASK__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH2_MASK__MASK_MASK 0xFFFFFF00L +//CP_DMA_WATCH2_CNTL +#define CP_DMA_WATCH2_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH2_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH2_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH2_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH2_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH2_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH2_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH2_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH2_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH2_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH2_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH2_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH3_ADDR_LO +#define CP_DMA_WATCH3_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH3_ADDR_LO__ADDR_LO__SHIFT 0x8 +#define CP_DMA_WATCH3_ADDR_LO__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH3_ADDR_LO__ADDR_LO_MASK 0xFFFFFF00L +//CP_DMA_WATCH3_ADDR_HI +#define CP_DMA_WATCH3_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH3_ADDR_HI__RSVD__SHIFT 0x19 +#define CP_DMA_WATCH3_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_WATCH3_ADDR_HI__RSVD_MASK 0xFE000000L +//CP_DMA_WATCH3_MASK +#define CP_DMA_WATCH3_MASK__RSVD__SHIFT 0x0 +#define CP_DMA_WATCH3_MASK__MASK__SHIFT 0x8 +#define CP_DMA_WATCH3_MASK__RSVD_MASK 0x000000FFL +#define CP_DMA_WATCH3_MASK__MASK_MASK 0xFFFFFF00L +//CP_DMA_WATCH3_CNTL +#define CP_DMA_WATCH3_CNTL__VMID__SHIFT 0x0 +#define CP_DMA_WATCH3_CNTL__RSVD1__SHIFT 0x4 +#define CP_DMA_WATCH3_CNTL__WATCH_READS__SHIFT 0x8 +#define CP_DMA_WATCH3_CNTL__WATCH_WRITES__SHIFT 0x9 +#define CP_DMA_WATCH3_CNTL__ANY_VMID__SHIFT 0xa +#define CP_DMA_WATCH3_CNTL__RSVD2__SHIFT 0xb +#define CP_DMA_WATCH3_CNTL__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH3_CNTL__RSVD1_MASK 0x000000F0L +#define CP_DMA_WATCH3_CNTL__WATCH_READS_MASK 0x00000100L +#define CP_DMA_WATCH3_CNTL__WATCH_WRITES_MASK 0x00000200L +#define CP_DMA_WATCH3_CNTL__ANY_VMID_MASK 0x00000400L +#define CP_DMA_WATCH3_CNTL__RSVD2_MASK 0xFFFFF800L +//CP_DMA_WATCH_STAT_ADDR_LO +#define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_DMA_WATCH_STAT_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_DMA_WATCH_STAT_ADDR_HI +#define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_WATCH_STAT_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +//CP_DMA_WATCH_STAT +#define CP_DMA_WATCH_STAT__VMID__SHIFT 0x0 +#define CP_DMA_WATCH_STAT__QUEUE_ID__SHIFT 0x4 +#define CP_DMA_WATCH_STAT__CLIENT_ID__SHIFT 0x8 +#define CP_DMA_WATCH_STAT__PIPE__SHIFT 0xc +#define CP_DMA_WATCH_STAT__WATCH_ID__SHIFT 0x10 +#define CP_DMA_WATCH_STAT__RD_WR__SHIFT 0x14 +#define CP_DMA_WATCH_STAT__TRAP_FLAG__SHIFT 0x1f +#define CP_DMA_WATCH_STAT__VMID_MASK 0x0000000FL +#define CP_DMA_WATCH_STAT__QUEUE_ID_MASK 0x00000070L +#define CP_DMA_WATCH_STAT__CLIENT_ID_MASK 0x00000700L +#define CP_DMA_WATCH_STAT__PIPE_MASK 0x00003000L +#define CP_DMA_WATCH_STAT__WATCH_ID_MASK 0x00030000L +#define CP_DMA_WATCH_STAT__RD_WR_MASK 0x00100000L +#define CP_DMA_WATCH_STAT__TRAP_FLAG_MASK 0x80000000L +//CP_PFP_JT_STAT +#define CP_PFP_JT_STAT__JT_LOADED__SHIFT 0x0 +#define CP_PFP_JT_STAT__WR_MASK__SHIFT 0x10 +#define CP_PFP_JT_STAT__JT_LOADED_MASK 0x00000003L +#define CP_PFP_JT_STAT__WR_MASK_MASK 0x00030000L +//CP_MEC_JT_STAT +#define CP_MEC_JT_STAT__JT_LOADED__SHIFT 0x0 +#define CP_MEC_JT_STAT__WR_MASK__SHIFT 0x10 +#define CP_MEC_JT_STAT__JT_LOADED_MASK 0x000000FFL +#define CP_MEC_JT_STAT__WR_MASK_MASK 0x00FF0000L +//CP_CPC_BUSY_HYSTERESIS +#define CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE__SHIFT 0x0 +#define CP_CPC_BUSY_HYSTERESIS__CPC_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_HYSTERESIS__CAC_ACTIVE_MASK 0x000000FFL +#define CP_CPC_BUSY_HYSTERESIS__CPC_BUSY_MASK 0x0000FF00L +//CP_CPF_BUSY_HYSTERESIS1 +#define CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT 0x0 +#define CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY__SHIFT 0x10 +#define CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK 0x000000FFL +#define CP_CPF_BUSY_HYSTERESIS1__CPF_BUSY_MASK 0x0000FF00L +#define CP_CPF_BUSY_HYSTERESIS1__CORE_BUSY_MASK 0x00FF0000L +#define CP_CPF_BUSY_HYSTERESIS1__GFX_BUSY_MASK 0xFF000000L +//CP_CPF_BUSY_HYSTERESIS2 +#define CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_HYSTERESIS2__CMP_BUSY_MASK 0x000000FFL +//CP_CPG_BUSY_HYSTERESIS1 +#define CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE__SHIFT 0x0 +#define CP_CPG_BUSY_HYSTERESIS1__CP_BUSY__SHIFT 0x8 +#define CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY__SHIFT 0x10 +#define CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY__SHIFT 0x18 +#define CP_CPG_BUSY_HYSTERESIS1__CAC_ACTIVE_MASK 0x000000FFL +#define CP_CPG_BUSY_HYSTERESIS1__CP_BUSY_MASK 0x0000FF00L +#define CP_CPG_BUSY_HYSTERESIS1__DMA_BUSY_MASK 0x00FF0000L +#define CP_CPG_BUSY_HYSTERESIS1__GFX_BUSY_MASK 0xFF000000L +//CP_CPG_BUSY_HYSTERESIS2 +#define CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY__SHIFT 0x0 +#define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0__SHIFT 0x8 +#define CP_CPG_BUSY_HYSTERESIS2__CMP_BUSY_MASK 0x000000FFL +#define CP_CPG_BUSY_HYSTERESIS2__SPI_CLOCK_0_MASK 0x0000FF00L +//CPF_FED_ERROR_ADDR_LO +#define CPF_FED_ERROR_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CPF_FED_ERROR_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L +//CPF_FED_ERROR_ADDR_HI +#define CPF_FED_ERROR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CPF_FED_ERROR_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +//CPC_FED_ERROR_ADDR_LO +#define CPC_FED_ERROR_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CPC_FED_ERROR_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L +//CPC_FED_ERROR_ADDR_HI +#define CPC_FED_ERROR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CPC_FED_ERROR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CPG_FED_ERROR_ADDR_LO +#define CPG_FED_ERROR_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CPG_FED_ERROR_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L +//CPG_FED_ERROR_ADDR_HI +#define CPG_FED_ERROR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CPG_FED_ERROR_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +//CP_RB_DOORBELL_CLEAR +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE__SHIFT 0x0 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR__SHIFT 0x8 +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR__SHIFT 0x9 +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR__SHIFT 0xa +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR__SHIFT 0xb +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR__SHIFT 0xc +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR__SHIFT 0xd +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUEUE_MASK 0x00000007L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_EN_CLEAR_MASK 0x00000100L +#define CP_RB_DOORBELL_CLEAR__MAPPED_QUE_DOORBELL_HIT_CLEAR_MASK 0x00000200L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_EN_CLEAR_MASK 0x00000400L +#define CP_RB_DOORBELL_CLEAR__MASTER_DOORBELL_HIT_CLEAR_MASK 0x00000800L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_EN_CLEAR_MASK 0x00001000L +#define CP_RB_DOORBELL_CLEAR__QUEUES_DOORBELL_HIT_CLEAR_MASK 0x00002000L +//CP_RB0_ACTIVE +#define CP_RB0_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB0_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_RB_ACTIVE +#define CP_RB_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_RB_ACTIVE__ACTIVE_MASK 0x00000001L +//CP_RB_STATUS +#define CP_RB_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_RB_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_RB_STATUS__DOORBELL_UPDATED_MASK 0x00000001L +#define CP_RB_STATUS__DOORBELL_ENABLE_MASK 0x00000002L +//CPG_RCIU_CAM_INDEX +#define CPG_RCIU_CAM_INDEX__INDEX__SHIFT 0x0 +#define CPG_RCIU_CAM_INDEX__INDEX_MASK 0x0000001FL +//CPG_RCIU_CAM_DATA +#define CPG_RCIU_CAM_DATA__DATA__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_RCIU_CAM_DATA_PHASE0 +#define CPG_RCIU_CAM_DATA_PHASE0__ADDR__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN__SHIFT 0x18 +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN__SHIFT 0x19 +#define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR__SHIFT 0x1f +#define CPG_RCIU_CAM_DATA_PHASE0__ADDR_MASK 0x0003FFFFL +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE0_EN_MASK 0x01000000L +#define CPG_RCIU_CAM_DATA_PHASE0__PIPE1_EN_MASK 0x02000000L +#define CPG_RCIU_CAM_DATA_PHASE0__SKIP_WR_MASK 0x80000000L +//CPG_RCIU_CAM_DATA_PHASE1 +#define CPG_RCIU_CAM_DATA_PHASE1__MASK__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA_PHASE1__MASK_MASK 0xFFFFFFFFL +//CPG_RCIU_CAM_DATA_PHASE2 +#define CPG_RCIU_CAM_DATA_PHASE2__VALUE__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA_PHASE2__VALUE_MASK 0xFFFFFFFFL +//CPG_RCIU_CAM_DATA_PHASE3 +#define CPG_RCIU_CAM_DATA_PHASE3__ADDR_HI__SHIFT 0x0 +#define CPG_RCIU_CAM_DATA_PHASE3__ADDR_HI_MASK 0x000FFFFFL +//CP_GPU_TIMESTAMP_OFFSET_LO +#define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO__SHIFT 0x0 +#define CP_GPU_TIMESTAMP_OFFSET_LO__OFFSET_LO_MASK 0xFFFFFFFFL +//CP_GPU_TIMESTAMP_OFFSET_HI +#define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI__SHIFT 0x0 +#define CP_GPU_TIMESTAMP_OFFSET_HI__OFFSET_HI_MASK 0xFFFFFFFFL +//CP_SDMA_DMA_DONE +#define CP_SDMA_DMA_DONE__SDMA_ID__SHIFT 0x0 +#define CP_SDMA_DMA_DONE__SDMA_ID_MASK 0x0000000FL +//CP_PFP_SDMA_CS +#define CP_PFP_SDMA_CS__REQUEST_GRANT__SHIFT 0x0 +#define CP_PFP_SDMA_CS__SDMA_ID__SHIFT 0x4 +#define CP_PFP_SDMA_CS__REQUEST_POSITION__SHIFT 0x8 +#define CP_PFP_SDMA_CS__SDMA_COUNT__SHIFT 0xc +#define CP_PFP_SDMA_CS__REQUEST_GRANT_MASK 0x00000001L +#define CP_PFP_SDMA_CS__SDMA_ID_MASK 0x000000F0L +#define CP_PFP_SDMA_CS__REQUEST_POSITION_MASK 0x00000F00L +#define CP_PFP_SDMA_CS__SDMA_COUNT_MASK 0x00003000L +//CP_ME_SDMA_CS +#define CP_ME_SDMA_CS__REQUEST_GRANT__SHIFT 0x0 +#define CP_ME_SDMA_CS__SDMA_ID__SHIFT 0x4 +#define CP_ME_SDMA_CS__REQUEST_POSITION__SHIFT 0x8 +#define CP_ME_SDMA_CS__SDMA_COUNT__SHIFT 0xc +#define CP_ME_SDMA_CS__REQUEST_GRANT_MASK 0x00000001L +#define CP_ME_SDMA_CS__SDMA_ID_MASK 0x000000F0L +#define CP_ME_SDMA_CS__REQUEST_POSITION_MASK 0x00000F00L +#define CP_ME_SDMA_CS__SDMA_COUNT_MASK 0x00003000L +//CPF_GCR_CNTL +#define CPF_GCR_CNTL__GCR_GL_CMD__SHIFT 0x0 +#define CPF_GCR_CNTL__GCR_GL_CMD_MASK 0x0007FFFFL +//CPG_UTCL1_STATUS +#define CPG_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPG_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPG_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPG_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPG_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPG_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPG_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPG_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPG_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPG_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPC_UTCL1_STATUS +#define CPC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CPF_UTCL1_STATUS +#define CPF_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define CPF_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define CPF_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define CPF_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define CPF_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define CPF_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define CPF_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define CPF_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define CPF_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define CPF_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +//CP_SD_CNTL +#define CP_SD_CNTL__CPF_EN__SHIFT 0x0 +#define CP_SD_CNTL__CPG_EN__SHIFT 0x1 +#define CP_SD_CNTL__CPC_EN__SHIFT 0x2 +#define CP_SD_CNTL__RLC_EN__SHIFT 0x3 +#define CP_SD_CNTL__GE_EN__SHIFT 0x5 +#define CP_SD_CNTL__UTCL1_EN__SHIFT 0x6 +#define CP_SD_CNTL__EA_EN__SHIFT 0x9 +#define CP_SD_CNTL__SDMA_EN__SHIFT 0xa +#define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE__SHIFT 0x1f +#define CP_SD_CNTL__CPF_EN_MASK 0x00000001L +#define CP_SD_CNTL__CPG_EN_MASK 0x00000002L +#define CP_SD_CNTL__CPC_EN_MASK 0x00000004L +#define CP_SD_CNTL__RLC_EN_MASK 0x00000008L +#define CP_SD_CNTL__GE_EN_MASK 0x00000020L +#define CP_SD_CNTL__UTCL1_EN_MASK 0x00000040L +#define CP_SD_CNTL__EA_EN_MASK 0x00000200L +#define CP_SD_CNTL__SDMA_EN_MASK 0x00000400L +#define CP_SD_CNTL__SD_VMIDVEC_OVERRIDE_MASK 0x80000000L +//CP_SOFT_RESET_CNTL +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET__SHIFT 0x0 +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET__SHIFT 0x1 +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET__SHIFT 0x2 +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET__SHIFT 0x3 +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET__SHIFT 0x4 +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET__SHIFT 0x5 +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET__SHIFT 0x6 +#define CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET__SHIFT 0x7 +#define CP_SOFT_RESET_CNTL__CMP_ONLY_SOFT_RESET_MASK 0x00000001L +#define CP_SOFT_RESET_CNTL__GFX_ONLY_SOFT_RESET_MASK 0x00000002L +#define CP_SOFT_RESET_CNTL__CMP_HQD_REG_RESET_MASK 0x00000004L +#define CP_SOFT_RESET_CNTL__CMP_INTR_REG_RESET_MASK 0x00000008L +#define CP_SOFT_RESET_CNTL__CMP_HQD_QUEUE_DOORBELL_RESET_MASK 0x00000010L +#define CP_SOFT_RESET_CNTL__GFX_RB_DOORBELL_RESET_MASK 0x00000020L +#define CP_SOFT_RESET_CNTL__GFX_INTR_REG_RESET_MASK 0x00000040L +#define CP_SOFT_RESET_CNTL__GFX_HQD_REG_RESET_MASK 0x00000080L +//CP_CPC_GFX_CNTL +#define CP_CPC_GFX_CNTL__QUEUEID__SHIFT 0x0 +#define CP_CPC_GFX_CNTL__PIPEID__SHIFT 0x3 +#define CP_CPC_GFX_CNTL__MEID__SHIFT 0x5 +#define CP_CPC_GFX_CNTL__VALID__SHIFT 0x7 +#define CP_CPC_GFX_CNTL__QUEUEID_MASK 0x00000007L +#define CP_CPC_GFX_CNTL__PIPEID_MASK 0x00000018L +#define CP_CPC_GFX_CNTL__MEID_MASK 0x00000060L +#define CP_CPC_GFX_CNTL__VALID_MASK 0x00000080L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cpphqddec +//CP_HPD_UTCL1_CNTL +#define CP_HPD_UTCL1_CNTL__SELECT__SHIFT 0x0 +#define CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT__SHIFT 0xa +#define CP_HPD_UTCL1_CNTL__SELECT_MASK 0x0000000FL +#define CP_HPD_UTCL1_CNTL__DISABLE_ERROR_REPORT_MASK 0x00000400L +//CP_HPD_UTCL1_ERROR +#define CP_HPD_UTCL1_ERROR__ADDR_HI__SHIFT 0x0 +#define CP_HPD_UTCL1_ERROR__TYPE__SHIFT 0x1b +#define CP_HPD_UTCL1_ERROR__VMID__SHIFT 0x1c +#define CP_HPD_UTCL1_ERROR__ADDR_HI_MASK 0x01FFFFFFL +#define CP_HPD_UTCL1_ERROR__TYPE_MASK 0x08000000L +#define CP_HPD_UTCL1_ERROR__VMID_MASK 0xF0000000L +//CP_HPD_UTCL1_ERROR_ADDR +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR__SHIFT 0xc +#define CP_HPD_UTCL1_ERROR_ADDR__ADDR_MASK 0xFFFFF000L +//CP_MQD_BASE_ADDR +#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFCL +//CP_MQD_BASE_ADDR_HI +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x01FFFFFFL +//CP_HQD_ACTIVE +#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 +#define CP_HQD_ACTIVE__ACTIVE_MASK 0x00000001L +#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x00000002L +//CP_HQD_VMID +#define CP_HQD_VMID__VMID__SHIFT 0x0 +#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 +#define CP_HQD_VMID__VQID__SHIFT 0x10 +#define CP_HQD_VMID__VMID_MASK 0x0000000FL +#define CP_HQD_VMID__IB_VMID_MASK 0x00000F00L +#define CP_HQD_VMID__VQID_MASK 0x03FF0000L +//CP_HQD_PERSISTENT_STATE +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 +#define CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE__SHIFT 0x1 +#define CP_HQD_PERSISTENT_STATE__WGS_QUEUE__SHIFT 0x4 +#define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS__SHIFT 0x7 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 +#define CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT__SHIFT 0x12 +#define CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS__SHIFT 0x13 +#define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN__SHIFT 0x14 +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN__SHIFT 0x15 +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN__SHIFT 0x16 +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN__SHIFT 0x17 +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN__SHIFT 0x18 +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN__SHIFT 0x19 +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN__SHIFT 0x1a +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN__SHIFT 0x1b +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x00000001L +#define CP_HQD_PERSISTENT_STATE__TMZ_CONNECT_OVERRIDE_MASK 0x00000002L +#define CP_HQD_PERSISTENT_STATE__WGS_QUEUE_MASK 0x00000010L +#define CP_HQD_PERSISTENT_STATE__SUSPEND_STATUS_MASK 0x00000080L +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x0003FF00L +#define CP_HQD_PERSISTENT_STATE__TMZ_SWITCH_EXEMPT_MASK 0x00040000L +#define CP_HQD_PERSISTENT_STATE__TMZ_MATCH_DIS_MASK 0x00080000L +#define CP_HQD_PERSISTENT_STATE__WPP_CLAMP_EN_MASK 0x00100000L +#define CP_HQD_PERSISTENT_STATE__WPP_SWITCH_QOS_EN_MASK 0x00200000L +#define CP_HQD_PERSISTENT_STATE__IQ_SWITCH_QOS_EN_MASK 0x00400000L +#define CP_HQD_PERSISTENT_STATE__IB_SWITCH_QOS_EN_MASK 0x00800000L +#define CP_HQD_PERSISTENT_STATE__EOP_SWITCH_QOS_EN_MASK 0x01000000L +#define CP_HQD_PERSISTENT_STATE__PQ_SWITCH_QOS_EN_MASK 0x02000000L +#define CP_HQD_PERSISTENT_STATE__TC_OFFLOAD_QOS_EN_MASK 0x04000000L +#define CP_HQD_PERSISTENT_STATE__CACHE_FULL_PACKET_EN_MASK 0x08000000L +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000L +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000L +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000L +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000L +//CP_HQD_PIPE_PRIORITY +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x00000003L +//CP_HQD_QUEUE_PRIORITY +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0x0000000FL +//CP_HQD_QUANTUM +#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 +#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f +#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x00000001L +#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x00000010L +#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x00003F00L +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000L +//CP_HQD_PQ_BASE +#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 +#define CP_HQD_PQ_BASE__ADDR_MASK 0xFFFFFFFFL +//CP_HQD_PQ_BASE_HI +#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0x0001FFFFL +//CP_HQD_PQ_RPTR +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_RPTR_REPORT_ADDR +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_PQ_RPTR_REPORT_ADDR_HI +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0x01FFFFFFL +//CP_HQD_PQ_WPTR_POLL_ADDR +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x3 +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xFFFFFFF8L +//CP_HQD_PQ_WPTR_POLL_ADDR_HI +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0x01FFFFFFL +//CP_HQD_PQ_DOORBELL_CONTROL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x00000001L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x00000002L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000L +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000L +//CP_HQD_PQ_CONTROL +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__WPTR_CARRY__SHIFT 0x6 +#define CP_HQD_PQ_CONTROL__RPTR_CARRY__SHIFT 0x7 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN__SHIFT 0xe +#define CP_HQD_PQ_CONTROL__PQ_EMPTY__SHIFT 0xf +#define CP_HQD_PQ_CONTROL__SCOPE__SHIFT 0x10 +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x12 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_PQ_CONTROL__TMZ__SHIFT 0x16 +#define CP_HQD_PQ_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c +#define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH__SHIFT 0x1d +#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e +#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x0000003FL +#define CP_HQD_PQ_CONTROL__WPTR_CARRY_MASK 0x00000040L +#define CP_HQD_PQ_CONTROL__RPTR_CARRY_MASK 0x00000080L +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x00003F00L +#define CP_HQD_PQ_CONTROL__QUEUE_FULL_EN_MASK 0x00004000L +#define CP_HQD_PQ_CONTROL__PQ_EMPTY_MASK 0x00008000L +#define CP_HQD_PQ_CONTROL__SCOPE_MASK 0x00030000L +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x000C0000L +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_PQ_CONTROL__TMZ_MASK 0x00400000L +#define CP_HQD_PQ_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x03000000L +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x08000000L +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000L +#define CP_HQD_PQ_CONTROL__TUNNEL_DISPATCH_MASK 0x20000000L +#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000L +#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000L +//CP_HQD_IB_BASE_ADDR +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xFFFFFFFCL +//CP_HQD_IB_BASE_ADDR_HI +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0x01FFFFFFL +//CP_HQD_IB_RPTR +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0x000FFFFFL +//CP_HQD_IB_CONTROL +#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IB_CONTROL__IB_SCOPE__SHIFT 0x1a +#define CP_HQD_IB_CONTROL__IB_PRIV_STATE__SHIFT 0x1e +#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f +#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0x000FFFFFL +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x00300000L +#define CP_HQD_IB_CONTROL__IB_EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x03000000L +#define CP_HQD_IB_CONTROL__IB_SCOPE_MASK 0x0C000000L +#define CP_HQD_IB_CONTROL__IB_PRIV_STATE_MASK 0x40000000L +#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000L +//CP_HQD_IQ_TIMER +#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define CP_HQD_IQ_TIMER__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b +#define CP_HQD_IQ_TIMER__REARM_TIMER__SHIFT 0x1c +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d +#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e +#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL +#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L +#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x003F0000L +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L +#define CP_HQD_IQ_TIMER__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L +#define CP_HQD_IQ_TIMER__REARM_TIMER_MASK 0x10000000L +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000L +#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000L +#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000L +//CP_HQD_IQ_RPTR +#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x0000003FL +//CP_HQD_DEQUEUE_REQUEST +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x0000000FL +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x00000010L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x00000100L +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x00000200L +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x00000400L +//CP_HQD_DMA_OFFLOAD +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L +#define CP_HQD_DMA_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L +#define CP_HQD_DMA_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L +//CP_HQD_OFFLOAD +#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD__SHIFT 0x2 +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN__SHIFT 0x3 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x00000001L +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x00000002L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_MASK 0x00000004L +#define CP_HQD_OFFLOAD__AQL_OFFLOAD_EN_MASK 0x00000008L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x00000010L +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x00000020L +//CP_HQD_MSG_TYPE +#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 +#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 +#define CP_HQD_MSG_TYPE__ACTION_MASK 0x00000007L +#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x00000070L +//CP_HQD_ATOMIC0_PREOP_LO +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC0_PREOP_HI +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_LO +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xFFFFFFFFL +//CP_HQD_ATOMIC1_PREOP_HI +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER0 +#define CP_HQD_HQ_SCHEDULER0__CWSR__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER0__SAVE_STATUS__SHIFT 0x1 +#define CP_HQD_HQ_SCHEDULER0__RSRV__SHIFT 0x2 +#define CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE__SHIFT 0x3 +#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE__SHIFT 0x6 +#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID__SHIFT 0x9 +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE__SHIFT 0xa +#define CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS__SHIFT 0xd +#define CP_HQD_HQ_SCHEDULER0__C_QUEUE_DEBUG_EN__SHIFT 0xe +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED__SHIFT 0xf +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED__SHIFT 0x14 +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE__SHIFT 0x15 +#define CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT__SHIFT 0x18 +#define CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE__SHIFT 0x1e +#define CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN__SHIFT 0x1f +#define CP_HQD_HQ_SCHEDULER0__CWSR_MASK 0x00000001L +#define CP_HQD_HQ_SCHEDULER0__SAVE_STATUS_MASK 0x00000002L +#define CP_HQD_HQ_SCHEDULER0__RSRV_MASK 0x00000004L +#define CP_HQD_HQ_SCHEDULER0__STATIC_QUEUE_MASK 0x00000038L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_RUN_ONCE_MASK 0x00000040L +#define CP_HQD_HQ_SCHEDULER0__SCRATCH_RAM_INIT_MASK 0x00000080L +#define CP_HQD_HQ_SCHEDULER0__TCL2_DIRTY_MASK 0x00000100L +#define CP_HQD_HQ_SCHEDULER0__C_INHERIT_VMID_MASK 0x00000200L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SCHEDULER_TYPE_MASK 0x00001C00L +#define CP_HQD_HQ_SCHEDULER0__C_QUEUE_USE_GWS_MASK 0x00002000L +#define CP_HQD_HQ_SCHEDULER0__C_QUEUE_DEBUG_EN_MASK 0x00004000L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_SLOT_CONNECTED_MASK 0x00008000L +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_ENABLED_MASK 0x00100000L +#define CP_HQD_HQ_SCHEDULER0__MES_INTERRUPT_PIPE_MASK 0x00600000L +#define CP_HQD_HQ_SCHEDULER0__CONCURRENT_PROCESS_COUNT_MASK 0x0F000000L +#define CP_HQD_HQ_SCHEDULER0__QUEUE_IDLE_MASK 0x40000000L +#define CP_HQD_HQ_SCHEDULER0__DB_UPDATED_MSG_EN_MASK 0x80000000L +//CP_HQD_HQ_STATUS0 +#define CP_HQD_HQ_STATUS0__CWSR__SHIFT 0x0 +#define CP_HQD_HQ_STATUS0__SAVE_STATUS__SHIFT 0x1 +#define CP_HQD_HQ_STATUS0__RSRV__SHIFT 0x2 +#define CP_HQD_HQ_STATUS0__STATIC_QUEUE__SHIFT 0x3 +#define CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE__SHIFT 0x6 +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_STATUS0__C_INHERIT_VMID__SHIFT 0x9 +#define CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE__SHIFT 0xa +#define CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS__SHIFT 0xd +#define CP_HQD_HQ_STATUS0__C_QUEUE_DEBUG_EN__SHIFT 0xe +#define CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED__SHIFT 0xf +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED__SHIFT 0x14 +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE__SHIFT 0x15 +#define CP_HQD_HQ_STATUS0__DFWX_QUEUE_SUPPORTED__SHIFT 0x17 +#define CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT__SHIFT 0x18 +#define CP_HQD_HQ_STATUS0__PLATFORM_ATOMICS_SUPPORTED__SHIFT 0x1d +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE__SHIFT 0x1e +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN__SHIFT 0x1f +#define CP_HQD_HQ_STATUS0__CWSR_MASK 0x00000001L +#define CP_HQD_HQ_STATUS0__SAVE_STATUS_MASK 0x00000002L +#define CP_HQD_HQ_STATUS0__RSRV_MASK 0x00000004L +#define CP_HQD_HQ_STATUS0__STATIC_QUEUE_MASK 0x00000038L +#define CP_HQD_HQ_STATUS0__QUEUE_RUN_ONCE_MASK 0x00000040L +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x00000080L +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x00000100L +#define CP_HQD_HQ_STATUS0__C_INHERIT_VMID_MASK 0x00000200L +#define CP_HQD_HQ_STATUS0__QUEUE_SCHEDULER_TYPE_MASK 0x00001C00L +#define CP_HQD_HQ_STATUS0__C_QUEUE_USE_GWS_MASK 0x00002000L +#define CP_HQD_HQ_STATUS0__C_QUEUE_DEBUG_EN_MASK 0x00004000L +#define CP_HQD_HQ_STATUS0__QUEUE_SLOT_CONNECTED_MASK 0x00008000L +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_ENABLED_MASK 0x00100000L +#define CP_HQD_HQ_STATUS0__MES_INTERRUPT_PIPE_MASK 0x00600000L +#define CP_HQD_HQ_STATUS0__DFWX_QUEUE_SUPPORTED_MASK 0x00800000L +#define CP_HQD_HQ_STATUS0__CONCURRENT_PROCESS_COUNT_MASK 0x0F000000L +#define CP_HQD_HQ_STATUS0__PLATFORM_ATOMICS_SUPPORTED_MASK 0x20000000L +#define CP_HQD_HQ_STATUS0__QUEUE_IDLE_MASK 0x40000000L +#define CP_HQD_HQ_STATUS0__DB_UPDATED_MSG_EN_MASK 0x80000000L +//CP_HQD_HQ_CONTROL0 +#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_HQ_SCHEDULER1 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xFFFFFFFFL +//CP_MQD_CONTROL +#define CP_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_MQD_CONTROL__PRIV_STATE__SHIFT 0x8 +#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc +#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd +#define CP_MQD_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_MQD_CONTROL__SCOPE__SHIFT 0x1a +#define CP_MQD_CONTROL__VMID_MASK 0x0000000FL +#define CP_MQD_CONTROL__PRIV_STATE_MASK 0x00000100L +#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x00001000L +#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x00002000L +#define CP_MQD_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x03000000L +#define CP_MQD_CONTROL__SCOPE_MASK 0x0C000000L +//CP_HQD_HQ_STATUS1 +#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 +#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xFFFFFFFFL +//CP_HQD_HQ_CONTROL1 +#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xFFFFFFFFL +//CP_HQD_EOP_BASE_ADDR_HI +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0001FFFFL +//CP_HQD_EOP_CONTROL +#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe +#define CP_HQD_EOP_CONTROL__SCOPE__SHIFT 0x13 +#define CP_HQD_EOP_CONTROL__HALT_FETCHER__SHIFT 0x15 +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN__SHIFT 0x16 +#define CP_HQD_EOP_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x0000003FL +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x00000100L +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x00001000L +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x00002000L +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x00004000L +#define CP_HQD_EOP_CONTROL__SCOPE_MASK 0x00180000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_MASK 0x00200000L +#define CP_HQD_EOP_CONTROL__HALT_FETCHER_EN_MASK 0x00400000L +#define CP_HQD_EOP_CONTROL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x03000000L +//CP_HQD_EOP_RPTR +#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 +#define CP_HQD_EOP_RPTR__RESET_FETCHER__SHIFT 0x1c +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND__SHIFT 0x1d +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e +#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f +#define CP_HQD_EOP_RPTR__RPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_RPTR__RESET_FETCHER_MASK 0x10000000L +#define CP_HQD_EOP_RPTR__DEQUEUE_PEND_MASK 0x20000000L +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000L +#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000L +//CP_HQD_EOP_WPTR +#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR__EOP_EMPTY__SHIFT 0xf +#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 +#define CP_HQD_EOP_WPTR__WPTR_MASK 0x00001FFFL +#define CP_HQD_EOP_WPTR__EOP_EMPTY_MASK 0x00008000L +#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1FFF0000L +//CP_HQD_EOP_EVENTS +#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 +#define CP_HQD_EOP_EVENTS__RESTORE_EOP__SHIFT 0xf +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 +#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0x00000FFFL +#define CP_HQD_EOP_EVENTS__RESTORE_EOP_MASK 0x00008000L +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x00010000L +//CP_HQD_CTX_SAVE_BASE_ADDR_LO +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L +//CP_HQD_CTX_SAVE_BASE_ADDR_HI +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +//CP_HQD_CTX_SAVE_CONTROL +#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define CP_HQD_CTX_SAVE_CONTROL__SCOPE__SHIFT 0x8 +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L +#define CP_HQD_CTX_SAVE_CONTROL__SCOPE_MASK 0x00000300L +#define CP_HQD_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L +//CP_HQD_CNTL_STACK_OFFSET +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//CP_HQD_CNTL_STACK_SIZE +#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L +//CP_HQD_WG_STATE_OFFSET +#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL +//CP_HQD_CTX_SAVE_SIZE +#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x03FFF000L +//CP_HQD_GDS_RESOURCE_STATE +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x00000001L +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x00000002L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x000003F0L +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x0003F000L +//CP_HQD_ERROR +#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 +#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_HQD_ERROR__AQL_ERROR__SHIFT 0x5 +#define CP_HQD_ERROR__PQ_UTCL1_ERROR__SHIFT 0x8 +#define CP_HQD_ERROR__IB_UTCL1_ERROR__SHIFT 0x9 +#define CP_HQD_ERROR__EOP_UTCL1_ERROR__SHIFT 0xa +#define CP_HQD_ERROR__IQ_UTCL1_ERROR__SHIFT 0xb +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR__SHIFT 0xc +#define CP_HQD_ERROR__WPP_UTCL1_ERROR__SHIFT 0xd +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR__SHIFT 0xf +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR__SHIFT 0x10 +#define CP_HQD_ERROR__SR_UTCL1_ERROR__SHIFT 0x11 +#define CP_HQD_ERROR__QU_UTCL1_ERROR__SHIFT 0x12 +#define CP_HQD_ERROR__TC_UTCL1_ERROR__SHIFT 0x13 +#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0x0000000FL +#define CP_HQD_ERROR__SUA_ERROR_MASK 0x00000010L +#define CP_HQD_ERROR__AQL_ERROR_MASK 0x00000020L +#define CP_HQD_ERROR__PQ_UTCL1_ERROR_MASK 0x00000100L +#define CP_HQD_ERROR__IB_UTCL1_ERROR_MASK 0x00000200L +#define CP_HQD_ERROR__EOP_UTCL1_ERROR_MASK 0x00000400L +#define CP_HQD_ERROR__IQ_UTCL1_ERROR_MASK 0x00000800L +#define CP_HQD_ERROR__RRPT_UTCL1_ERROR_MASK 0x00001000L +#define CP_HQD_ERROR__WPP_UTCL1_ERROR_MASK 0x00002000L +#define CP_HQD_ERROR__DMA_SRC_UTCL1_ERROR_MASK 0x00008000L +#define CP_HQD_ERROR__DMA_DST_UTCL1_ERROR_MASK 0x00010000L +#define CP_HQD_ERROR__SR_UTCL1_ERROR_MASK 0x00020000L +#define CP_HQD_ERROR__QU_UTCL1_ERROR_MASK 0x00040000L +#define CP_HQD_ERROR__TC_UTCL1_ERROR_MASK 0x00080000L +//CP_HQD_EOP_WPTR_MEM +#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x00001FFFL +//CP_HQD_AQL_CONTROL +#define CP_HQD_AQL_CONTROL__CONTROL0__SHIFT 0x0 +#define CP_HQD_AQL_CONTROL__CONTROL0_EN__SHIFT 0xf +#define CP_HQD_AQL_CONTROL__CONTROL1__SHIFT 0x10 +#define CP_HQD_AQL_CONTROL__CONTROL1_EN__SHIFT 0x1f +#define CP_HQD_AQL_CONTROL__CONTROL0_MASK 0x00007FFFL +#define CP_HQD_AQL_CONTROL__CONTROL0_EN_MASK 0x00008000L +#define CP_HQD_AQL_CONTROL__CONTROL1_MASK 0x7FFF0000L +#define CP_HQD_AQL_CONTROL__CONTROL1_EN_MASK 0x80000000L +//CP_HQD_PQ_WPTR_LO +#define CP_HQD_PQ_WPTR_LO__OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_LO__OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_PQ_WPTR_HI +#define CP_HQD_PQ_WPTR_HI__DATA__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_HI__DATA_MASK 0xFFFFFFFFL +//CP_HQD_SUSPEND_CNTL_STACK_OFFSET +#define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//CP_HQD_SUSPEND_CNTL_STACK_DW_CNT +#define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT__SHIFT 0x0 +#define CP_HQD_SUSPEND_CNTL_STACK_DW_CNT__CNT_MASK 0x00003FFFL +//CP_HQD_SUSPEND_WG_STATE_OFFSET +#define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL +//CP_HQD_DDID_RPTR +#define CP_HQD_DDID_RPTR__RPTR__SHIFT 0x0 +#define CP_HQD_DDID_RPTR__RPTR_MASK 0x000007FFL +//CP_HQD_DDID_WPTR +#define CP_HQD_DDID_WPTR__WPTR__SHIFT 0x0 +#define CP_HQD_DDID_WPTR__WPTR_MASK 0x000007FFL +//CP_HQD_DDID_INFLIGHT_COUNT +#define CP_HQD_DDID_INFLIGHT_COUNT__COUNT__SHIFT 0x0 +#define CP_HQD_DDID_INFLIGHT_COUNT__COUNT_MASK 0x0000FFFFL +//CP_HQD_DDID_DELTA_RPT_COUNT +#define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT__SHIFT 0x0 +#define CP_HQD_DDID_DELTA_RPT_COUNT__COUNT_MASK 0x000000FFL +//CP_HQD_DEQUEUE_STATUS +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT__SHIFT 0x0 +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN__SHIFT 0x9 +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN__SHIFT 0xa +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_MASK 0x0000000FL +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_MASK 0x00000010L +#define CP_HQD_DEQUEUE_STATUS__SUSPEND_REQ_PEND_EN_MASK 0x00000200L +#define CP_HQD_DEQUEUE_STATUS__DEQUEUE_STAT_EN_MASK 0x00000400L +//CP_HQD_AQL_CONTROL_1 +#define CP_HQD_AQL_CONTROL_1__RESERVED__SHIFT 0x0 +#define CP_HQD_AQL_CONTROL_1__RESERVED_MASK 0xFFFFFFFFL +//CP_HQD_AQL_DISPATCH_ID +#define CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_AQL_DISPATCH_ID__CONSUMED_OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_AQL_DISPATCH_ID_HI +#define CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_AQL_DISPATCH_ID_HI__CONSUMED_OFFSET_MASK 0xFFFFFFFFL +//CP_HQD_KD_BASE +#define CP_HQD_KD_BASE__ADDR__SHIFT 0x0 +#define CP_HQD_KD_BASE__ADDR_MASK 0xFFFFFFFFL +//CP_HQD_KD_BASE_HI +#define CP_HQD_KD_BASE_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_KD_BASE_HI__ADDR_HI_MASK 0x0001FFFFL +//CP_HQD_KD_CNTL +#define CP_HQD_KD_CNTL__KD_SIZE__SHIFT 0x0 +#define CP_HQD_KD_CNTL__KD_FETCHER_ENABLE__SHIFT 0x10 +#define CP_HQD_KD_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_HQD_KD_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_KD_CNTL__SCOPE__SHIFT 0x1a +#define CP_HQD_KD_CNTL__PRIV_STATE__SHIFT 0x1e +#define CP_HQD_KD_CNTL__KD_SIZE_MASK 0x00000003L +#define CP_HQD_KD_CNTL__KD_FETCHER_ENABLE_MASK 0x00010000L +#define CP_HQD_KD_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_HQD_KD_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_HQD_KD_CNTL__SCOPE_MASK 0x0C000000L +#define CP_HQD_KD_CNTL__PRIV_STATE_MASK 0x40000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gfxdec0 +//COHER_DEST_BASE_HI_0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_1 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_2 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_HI_3 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0x000000FFL +//COHER_DEST_BASE_2 +#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_3 +#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_0 +#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xFFFFFFFFL +//COHER_DEST_BASE_1 +#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xFFFFFFFFL +//CP_PERFMON_CNTX_CNTL +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L +//CP_PIPEID +#define CP_PIPEID__PIPE_ID__SHIFT 0x0 +#define CP_PIPEID__PIPE_ID_MASK 0x00000003L +//CP_RINGID +#define CP_RINGID__RINGID__SHIFT 0x0 +#define CP_RINGID__RINGID_MASK 0x00000003L +//CP_VMID +#define CP_VMID__VMID__SHIFT 0x0 +#define CP_VMID__VMID_MASK 0x0000000FL +//CONTEXT_RESERVED_REG0 +#define CONTEXT_RESERVED_REG0__DATA__SHIFT 0x0 +#define CONTEXT_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//CONTEXT_RESERVED_REG1 +#define CONTEXT_RESERVED_REG1__DATA__SHIFT 0x0 +#define CONTEXT_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL +//VGT_MULTI_PRIM_IB_RESET_INDX +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL +//GFX_COPY_STATE +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x00000007L +//VGT_DMA_BASE_HI +#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0x0000FFFFL +//VGT_DMA_BASE +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xFFFFFFFFL +//VGT_DRAW_INITIATOR +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 +#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 +#define VGT_DRAW_INITIATOR__REG_RT_INDEX__SHIFT 0x1d +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x00000003L +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x00000020L +#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x00000040L +#define VGT_DRAW_INITIATOR__REG_RT_INDEX_MASK 0xE0000000L +//VGT_EVENT_ADDRESS_REG +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0x0FFFFFFFL +//VGT_HOS_MAX_TESS_LEVEL +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xFFFFFFFFL +//VGT_HOS_MIN_TESS_LEVEL +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xFFFFFFFFL +//GE_IA_ENHANCE +#define GE_IA_ENHANCE__MISC__SHIFT 0x0 +#define GE_IA_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_DMA_SIZE +#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 +#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_DMA_MAX_SIZE +#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 +#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xFFFFFFFFL +//VGT_DMA_INDEX_TYPE +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 +#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 +#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb +#define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT 0xe +#define VGT_DMA_INDEX_TYPE__TEMPORAL__SHIFT 0xf +#define VGT_DMA_INDEX_TYPE__SPEC_DATA_READ__SHIFT 0x11 +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x000000C0L +#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x00000200L +#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x00003800L +#define VGT_DMA_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK 0x00004000L +#define VGT_DMA_INDEX_TYPE__TEMPORAL_MASK 0x00018000L +#define VGT_DMA_INDEX_TYPE__SPEC_DATA_READ_MASK 0x00060000L +//GE_WD_ENHANCE +#define GE_WD_ENHANCE__MISC__SHIFT 0x0 +#define GE_WD_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_DMA_NUM_INSTANCES +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_EVENT_INITIATOR +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0xa +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x0000003FL +#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x07FFFC00L +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x08000000L +//VGT_SHADER_STAGES_EN +#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 +#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH__SHIFT 0x13 +#define VGT_SHADER_STAGES_EN__HS_W32_EN__SHIFT 0x15 +#define VGT_SHADER_STAGES_EN__GS_W32_EN__SHIFT 0x16 +#define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN__SHIFT 0x18 +#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG__SHIFT 0x1a +#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x00000004L +#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x00000020L +#define VGT_SHADER_STAGES_EN__GS_FAST_LAUNCH_MASK 0x00080000L +#define VGT_SHADER_STAGES_EN__HS_W32_EN_MASK 0x00200000L +#define VGT_SHADER_STAGES_EN__GS_W32_EN_MASK 0x00400000L +#define VGT_SHADER_STAGES_EN__NGG_WAVE_ID_EN_MASK 0x01000000L +#define VGT_SHADER_STAGES_EN__PRIMGEN_PASSTHRU_NO_MSG_MASK 0x04000000L +//VGT_TF_PARAM +#define VGT_TF_PARAM__TYPE__SHIFT 0x0 +#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 +#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 +#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe +#define VGT_TF_PARAM__TEMPORAL__SHIFT 0xf +#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 +#define VGT_TF_PARAM__DETECT_ONE__SHIFT 0x13 +#define VGT_TF_PARAM__DETECT_ZERO__SHIFT 0x14 +#define VGT_TF_PARAM__MTYPE__SHIFT 0x17 +#define VGT_TF_PARAM__SPEC_DATA_READ__SHIFT 0x1c +#define VGT_TF_PARAM__TYPE_MASK 0x00000003L +#define VGT_TF_PARAM__PARTITIONING_MASK 0x0000001CL +#define VGT_TF_PARAM__TOPOLOGY_MASK 0x000000E0L +#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x00004000L +#define VGT_TF_PARAM__TEMPORAL_MASK 0x00018000L +#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x00060000L +#define VGT_TF_PARAM__DETECT_ONE_MASK 0x00080000L +#define VGT_TF_PARAM__DETECT_ZERO_MASK 0x00100000L +#define VGT_TF_PARAM__MTYPE_MASK 0x03800000L +#define VGT_TF_PARAM__SPEC_DATA_READ_MASK 0x30000000L +//VGT_STRMOUT_DRAW_OPAQUE_OFFSET +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xFFFFFFFFL +//VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x000001FFL +//VGT_TESS_DISTRIBUTION +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT__SHIFT 0x1d +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0x000000FFL +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0x0000FF00L +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0x00FF0000L +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0x1F000000L +#define VGT_TESS_DISTRIBUTION__TRAP_SPLIT_MASK 0xE0000000L +//VGT_LS_HS_CONFIG +#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe +#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0x000000FFL +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0x000FC000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvf_cpdec +//CONFIG_RESERVED_REG0 +#define CONFIG_RESERVED_REG0__DATA__SHIFT 0x0 +#define CONFIG_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//CONFIG_RESERVED_REG1 +#define CONFIG_RESERVED_REG1__DATA__SHIFT 0x0 +#define CONFIG_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL +//CP_MEC_CNTL +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x1b +#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e +#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x00010000L +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x00020000L +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x00040000L +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x00080000L +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x08000000L +#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000L +#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000L +//CP_ME_CNTL +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 +#define CP_ME_CNTL__PFP_PIPE0_DISABLE__SHIFT 0xc +#define CP_ME_CNTL__PFP_PIPE1_DISABLE__SHIFT 0xd +#define CP_ME_CNTL__ME_PIPE0_DISABLE__SHIFT 0xe +#define CP_ME_CNTL__ME_PIPE1_DISABLE__SHIFT 0xf +#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 +#define CP_ME_CNTL__CE_PIPE1_RESET__SHIFT 0x11 +#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 +#define CP_ME_CNTL__PFP_PIPE1_RESET__SHIFT 0x13 +#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 +#define CP_ME_CNTL__ME_PIPE1_RESET__SHIFT 0x15 +#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 +#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 +#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a +#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b +#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c +#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x00000040L +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x00000100L +#define CP_ME_CNTL__PFP_PIPE0_DISABLE_MASK 0x00001000L +#define CP_ME_CNTL__PFP_PIPE1_DISABLE_MASK 0x00002000L +#define CP_ME_CNTL__ME_PIPE0_DISABLE_MASK 0x00004000L +#define CP_ME_CNTL__ME_PIPE1_DISABLE_MASK 0x00008000L +#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x00010000L +#define CP_ME_CNTL__CE_PIPE1_RESET_MASK 0x00020000L +#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x00040000L +#define CP_ME_CNTL__PFP_PIPE1_RESET_MASK 0x00080000L +#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x00100000L +#define CP_ME_CNTL__ME_PIPE1_RESET_MASK 0x00200000L +#define CP_ME_CNTL__CE_HALT_MASK 0x01000000L +#define CP_ME_CNTL__CE_STEP_MASK 0x02000000L +#define CP_ME_CNTL__PFP_HALT_MASK 0x04000000L +#define CP_ME_CNTL__PFP_STEP_MASK 0x08000000L +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000L +#define CP_ME_CNTL__ME_STEP_MASK 0x20000000L +//CP_UNMAPPED_QUEUE0 +#define CP_UNMAPPED_QUEUE0__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE0__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE1 +#define CP_UNMAPPED_QUEUE1__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE1__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE2 +#define CP_UNMAPPED_QUEUE2__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE2__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE3 +#define CP_UNMAPPED_QUEUE3__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE3__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE4 +#define CP_UNMAPPED_QUEUE4__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE4__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE5 +#define CP_UNMAPPED_QUEUE5__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE5__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE6 +#define CP_UNMAPPED_QUEUE6__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE6__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE7 +#define CP_UNMAPPED_QUEUE7__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE7__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE8 +#define CP_UNMAPPED_QUEUE8__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE8__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE9 +#define CP_UNMAPPED_QUEUE9__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE9__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE10 +#define CP_UNMAPPED_QUEUE10__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE10__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE11 +#define CP_UNMAPPED_QUEUE11__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE11__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE12 +#define CP_UNMAPPED_QUEUE12__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE12__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE13 +#define CP_UNMAPPED_QUEUE13__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE13__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE14 +#define CP_UNMAPPED_QUEUE14__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE14__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE15 +#define CP_UNMAPPED_QUEUE15__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE15__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE16 +#define CP_UNMAPPED_QUEUE16__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE16__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE17 +#define CP_UNMAPPED_QUEUE17__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE17__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE18 +#define CP_UNMAPPED_QUEUE18__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE18__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE19 +#define CP_UNMAPPED_QUEUE19__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE19__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE20 +#define CP_UNMAPPED_QUEUE20__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE20__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE21 +#define CP_UNMAPPED_QUEUE21__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE21__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE22 +#define CP_UNMAPPED_QUEUE22__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE22__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE23 +#define CP_UNMAPPED_QUEUE23__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE23__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE24 +#define CP_UNMAPPED_QUEUE24__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE24__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE25 +#define CP_UNMAPPED_QUEUE25__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE25__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE26 +#define CP_UNMAPPED_QUEUE26__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE26__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE27 +#define CP_UNMAPPED_QUEUE27__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE27__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE28 +#define CP_UNMAPPED_QUEUE28__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE28__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE29 +#define CP_UNMAPPED_QUEUE29__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE29__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE30 +#define CP_UNMAPPED_QUEUE30__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE30__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE31 +#define CP_UNMAPPED_QUEUE31__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE31__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE32 +#define CP_UNMAPPED_QUEUE32__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE32__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE33 +#define CP_UNMAPPED_QUEUE33__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE33__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE34 +#define CP_UNMAPPED_QUEUE34__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE34__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE35 +#define CP_UNMAPPED_QUEUE35__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE35__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE36 +#define CP_UNMAPPED_QUEUE36__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE36__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE37 +#define CP_UNMAPPED_QUEUE37__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE37__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE38 +#define CP_UNMAPPED_QUEUE38__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE38__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE39 +#define CP_UNMAPPED_QUEUE39__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE39__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE40 +#define CP_UNMAPPED_QUEUE40__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE40__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE41 +#define CP_UNMAPPED_QUEUE41__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE41__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE42 +#define CP_UNMAPPED_QUEUE42__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE42__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE43 +#define CP_UNMAPPED_QUEUE43__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE43__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE44 +#define CP_UNMAPPED_QUEUE44__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE44__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE45 +#define CP_UNMAPPED_QUEUE45__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE45__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE46 +#define CP_UNMAPPED_QUEUE46__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE46__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE47 +#define CP_UNMAPPED_QUEUE47__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE47__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE48 +#define CP_UNMAPPED_QUEUE48__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE48__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE49 +#define CP_UNMAPPED_QUEUE49__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE49__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE50 +#define CP_UNMAPPED_QUEUE50__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE50__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE51 +#define CP_UNMAPPED_QUEUE51__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE51__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE52 +#define CP_UNMAPPED_QUEUE52__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE52__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE53 +#define CP_UNMAPPED_QUEUE53__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE53__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE54 +#define CP_UNMAPPED_QUEUE54__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE54__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE55 +#define CP_UNMAPPED_QUEUE55__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE55__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE56 +#define CP_UNMAPPED_QUEUE56__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE56__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE57 +#define CP_UNMAPPED_QUEUE57__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE57__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE58 +#define CP_UNMAPPED_QUEUE58__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE58__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE59 +#define CP_UNMAPPED_QUEUE59__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE59__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE60 +#define CP_UNMAPPED_QUEUE60__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE60__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE61 +#define CP_UNMAPPED_QUEUE61__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE61__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE62 +#define CP_UNMAPPED_QUEUE62__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE62__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE63 +#define CP_UNMAPPED_QUEUE63__HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE63__HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_DOORBELL +#define CP_UNMAPPED_DOORBELL__ENABLE__SHIFT 0x0 +#define CP_UNMAPPED_DOORBELL__DBELL_MSG_BLOCK__SHIFT 0x1 +#define CP_UNMAPPED_DOORBELL__CLEAR_ALL__SHIFT 0x2 +#define CP_UNMAPPED_DOORBELL__QUEUE_LSB__SHIFT 0x4 +#define CP_UNMAPPED_DOORBELL__PROC_LSB__SHIFT 0x8 +#define CP_UNMAPPED_DOORBELL__ENABLE_MASK 0x00000001L +#define CP_UNMAPPED_DOORBELL__DBELL_MSG_BLOCK_MASK 0x00000002L +#define CP_UNMAPPED_DOORBELL__CLEAR_ALL_MASK 0x00000004L +#define CP_UNMAPPED_DOORBELL__QUEUE_LSB_MASK 0x000000F0L +#define CP_UNMAPPED_DOORBELL__PROC_LSB_MASK 0x00001F00L +//CP_UNMAPPED_QUEUE_BANK0 +#define CP_UNMAPPED_QUEUE_BANK0__BANK_HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE_BANK0__BANK_HIT_MASK 0xFFFFFFFFL +//CP_UNMAPPED_QUEUE_BANK1 +#define CP_UNMAPPED_QUEUE_BANK1__BANK_HIT__SHIFT 0x0 +#define CP_UNMAPPED_QUEUE_BANK1__BANK_HIT_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvf_grbmdec +//GRBM_GFX_CNTL +#define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL__CTXID__SHIFT 0xb +#define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L +#define GRBM_GFX_CNTL__CTXID_MASK 0x00003800L +//GRBM_NOWHERE +#define GRBM_NOWHERE__DATA__SHIFT 0x0 +#define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_cpdec +//CP_FETCHER_SOURCE +#define CP_FETCHER_SOURCE__ME_SRC__SHIFT 0x0 +#define CP_FETCHER_SOURCE__ME_SRC_MASK 0x00000001L +//CP_DFY_CNTL +#define CP_DFY_CNTL__SCOPE__SHIFT 0x6 +#define CP_DFY_CNTL__POLICY__SHIFT 0x8 +#define CP_DFY_CNTL__MTYPE__SHIFT 0xc +#define CP_DFY_CNTL__SPEC_DATA_READ__SHIFT 0xf +#define CP_DFY_CNTL__REPEATER_FGCG_DISABLE__SHIFT 0x19 +#define CP_DFY_CNTL__TPI_SDP_SEL__SHIFT 0x1a +#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c +#define CP_DFY_CNTL__MODE__SHIFT 0x1d +#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f +#define CP_DFY_CNTL__SCOPE_MASK 0x000000C0L +#define CP_DFY_CNTL__POLICY_MASK 0x00000300L +#define CP_DFY_CNTL__MTYPE_MASK 0x00003000L +#define CP_DFY_CNTL__SPEC_DATA_READ_MASK 0x00018000L +#define CP_DFY_CNTL__REPEATER_FGCG_DISABLE_MASK 0x02000000L +#define CP_DFY_CNTL__TPI_SDP_SEL_MASK 0x04000000L +#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000L +#define CP_DFY_CNTL__MODE_MASK 0x60000000L +#define CP_DFY_CNTL__ENABLE_MASK 0x80000000L +//CP_DFY_STAT +#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 +#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 +#define CP_DFY_STAT__BUSY__SHIFT 0x1f +#define CP_DFY_STAT__BURST_COUNT_MASK 0x0000FFFFL +#define CP_DFY_STAT__TAGS_PENDING_MASK 0x07FF0000L +#define CP_DFY_STAT__BUSY_MASK 0x80000000L +//CP_DFY_ADDR_HI +#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//CP_DFY_ADDR_LO +#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xFFFFFFE0L +//CP_DFY_DATA_0 +#define CP_DFY_DATA_0__DATA__SHIFT 0x0 +#define CP_DFY_DATA_0__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_1 +#define CP_DFY_DATA_1__DATA__SHIFT 0x0 +#define CP_DFY_DATA_1__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_2 +#define CP_DFY_DATA_2__DATA__SHIFT 0x0 +#define CP_DFY_DATA_2__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_3 +#define CP_DFY_DATA_3__DATA__SHIFT 0x0 +#define CP_DFY_DATA_3__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_4 +#define CP_DFY_DATA_4__DATA__SHIFT 0x0 +#define CP_DFY_DATA_4__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_5 +#define CP_DFY_DATA_5__DATA__SHIFT 0x0 +#define CP_DFY_DATA_5__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_6 +#define CP_DFY_DATA_6__DATA__SHIFT 0x0 +#define CP_DFY_DATA_6__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_7 +#define CP_DFY_DATA_7__DATA__SHIFT 0x0 +#define CP_DFY_DATA_7__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_8 +#define CP_DFY_DATA_8__DATA__SHIFT 0x0 +#define CP_DFY_DATA_8__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_9 +#define CP_DFY_DATA_9__DATA__SHIFT 0x0 +#define CP_DFY_DATA_9__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_10 +#define CP_DFY_DATA_10__DATA__SHIFT 0x0 +#define CP_DFY_DATA_10__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_11 +#define CP_DFY_DATA_11__DATA__SHIFT 0x0 +#define CP_DFY_DATA_11__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_12 +#define CP_DFY_DATA_12__DATA__SHIFT 0x0 +#define CP_DFY_DATA_12__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_13 +#define CP_DFY_DATA_13__DATA__SHIFT 0x0 +#define CP_DFY_DATA_13__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_14 +#define CP_DFY_DATA_14__DATA__SHIFT 0x0 +#define CP_DFY_DATA_14__DATA_MASK 0xFFFFFFFFL +//CP_DFY_DATA_15 +#define CP_DFY_DATA_15__DATA__SHIFT 0x0 +#define CP_DFY_DATA_15__DATA_MASK 0xFFFFFFFFL +//CP_DFY_CMD +#define CP_DFY_CMD__SIZE__SHIFT 0x10 +#define CP_DFY_CMD__SIZE_MASK 0xFFFF0000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_cpphqddec +//CP_HPD_MES_ROQ_OFFSETS +#define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_MES_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L +#define CP_HPD_MES_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L +#define CP_HPD_MES_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L +//CP_HPD_ROQ_OFFSETS +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_ROQ_OFFSETS__KD_OFFSET__SHIFT 0x18 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x00000007L +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x00003F00L +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x007F0000L +#define CP_HPD_ROQ_OFFSETS__KD_OFFSET_MASK 0xFF000000L +//CP_HPD_STATUS0 +#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 +#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 +#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 +#define CP_HPD_STATUS0__FETCHING_MQD__SHIFT 0x10 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB__SHIFT 0x11 +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ__SHIFT 0x12 +#define CP_HPD_STATUS0__ENABLE_MSG_NO_DISC__SHIFT 0x13 +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE__SHIFT 0x14 +#define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS__SHIFT 0x1b +#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK__SHIFT 0x1c +#define CP_HPD_STATUS0__FREEZE_QUEUE_STATE__SHIFT 0x1e +#define CP_HPD_STATUS0__FORCE_QUEUE__SHIFT 0x1f +#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x0000001FL +#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0x000000E0L +#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0x0000FF00L +#define CP_HPD_STATUS0__FETCHING_MQD_MASK 0x00010000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_PQIB_MASK 0x00020000L +#define CP_HPD_STATUS0__PEND_TXFER_SIZE_IQ_MASK 0x00040000L +#define CP_HPD_STATUS0__ENABLE_MSG_NO_DISC_MASK 0x00080000L +#define CP_HPD_STATUS0__FORCE_QUEUE_STATE_MASK 0x01F00000L +#define CP_HPD_STATUS0__MASTER_QUEUE_IDLE_DIS_MASK 0x08000000L +#define CP_HPD_STATUS0__ENABLE_OFFLOAD_CHECK_MASK 0x30000000L +#define CP_HPD_STATUS0__FREEZE_QUEUE_STATE_MASK 0x40000000L +#define CP_HPD_STATUS0__FORCE_QUEUE_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfonly_gcrdec +//GCR_GENERAL_CNTL +#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP__SHIFT 0x0 +#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ__SHIFT 0x1 +#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ__SHIFT 0x2 +#define GCR_GENERAL_CNTL__FORCE_INV_ALL__SHIFT 0x3 +#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL__SHIFT 0x4 +#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE__SHIFT 0x6 +#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE__SHIFT 0x7 +#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE__SHIFT 0x8 +#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ__SHIFT 0x9 +#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM__SHIFT 0xa +#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS__SHIFT 0xd +#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS__SHIFT 0xe +#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ__SHIFT 0xf +#define GCR_GENERAL_CNTL__DISABLE_FGCG__SHIFT 0x10 +#define GCR_GENERAL_CNTL__UTCL2_REQ_LIMIT__SHIFT 0x11 +#define GCR_GENERAL_CNTL__CLIENT_ID__SHIFT 0x14 +#define GCR_GENERAL_CNTL__FORCE_4K_L2_RESP_MASK 0x00000001L +#define GCR_GENERAL_CNTL__REDUCE_HALF_MAIN_WQ_MASK 0x00000002L +#define GCR_GENERAL_CNTL__REDUCE_HALF_PHY_WQ_MASK 0x00000004L +#define GCR_GENERAL_CNTL__FORCE_INV_ALL_MASK 0x00000008L +#define GCR_GENERAL_CNTL__HI_PRIORITY_CNTL_MASK 0x00000030L +#define GCR_GENERAL_CNTL__HI_PRIORITY_DISABLE_MASK 0x00000040L +#define GCR_GENERAL_CNTL__BIG_PAGE_FILTER_DISABLE_MASK 0x00000080L +#define GCR_GENERAL_CNTL__PERF_CNTR_ENABLE_MASK 0x00000100L +#define GCR_GENERAL_CNTL__FORCE_SINGLE_WQ_MASK 0x00000200L +#define GCR_GENERAL_CNTL__UTCL2_REQ_PERM_MASK 0x00001C00L +#define GCR_GENERAL_CNTL__TARGET_MGCG_CLKEN_DIS_MASK 0x00002000L +#define GCR_GENERAL_CNTL__MIXED_RANGE_MODE_DIS_MASK 0x00004000L +#define GCR_GENERAL_CNTL__ENABLE_16K_UTCL2_REQ_MASK 0x00008000L +#define GCR_GENERAL_CNTL__DISABLE_FGCG_MASK 0x00010000L +#define GCR_GENERAL_CNTL__UTCL2_REQ_LIMIT_MASK 0x000E0000L +#define GCR_GENERAL_CNTL__CLIENT_ID_MASK 0x1FF00000L +//GCR_TARGET_DISABLE +#define GCR_TARGET_DISABLE__DISABLE_SE0_PHY__SHIFT 0x0 +#define GCR_TARGET_DISABLE__DISABLE_SE0_VIRT__SHIFT 0x1 +#define GCR_TARGET_DISABLE__DISABLE_SE1_PHY__SHIFT 0x2 +#define GCR_TARGET_DISABLE__DISABLE_SE1_VIRT__SHIFT 0x3 +#define GCR_TARGET_DISABLE__DISABLE_SE2_PHY__SHIFT 0x4 +#define GCR_TARGET_DISABLE__DISABLE_SE2_VIRT__SHIFT 0x5 +#define GCR_TARGET_DISABLE__DISABLE_SE3_PHY__SHIFT 0x6 +#define GCR_TARGET_DISABLE__DISABLE_SE3_VIRT__SHIFT 0x7 +#define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY__SHIFT 0x8 +#define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY__SHIFT 0x9 +#define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY__SHIFT 0xa +#define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY__SHIFT 0xb +#define GCR_TARGET_DISABLE__SE0_INACTIVE_STATUS__SHIFT 0x10 +#define GCR_TARGET_DISABLE__SE1_INACTIVE_STATUS__SHIFT 0x11 +#define GCR_TARGET_DISABLE__SE2_INACTIVE_STATUS__SHIFT 0x12 +#define GCR_TARGET_DISABLE__SE3_INACTIVE_STATUS__SHIFT 0x13 +#define GCR_TARGET_DISABLE__GL2A0_DISABLE_STATUS__SHIFT 0x18 +#define GCR_TARGET_DISABLE__GL2A1_DISABLE_STATUS__SHIFT 0x19 +#define GCR_TARGET_DISABLE__GL2A2_DISABLE_STATUS__SHIFT 0x1a +#define GCR_TARGET_DISABLE__GL2A3_DISABLE_STATUS__SHIFT 0x1b +#define GCR_TARGET_DISABLE__DISABLE_SE0_PHY_MASK 0x00000001L +#define GCR_TARGET_DISABLE__DISABLE_SE0_VIRT_MASK 0x00000002L +#define GCR_TARGET_DISABLE__DISABLE_SE1_PHY_MASK 0x00000004L +#define GCR_TARGET_DISABLE__DISABLE_SE1_VIRT_MASK 0x00000008L +#define GCR_TARGET_DISABLE__DISABLE_SE2_PHY_MASK 0x00000010L +#define GCR_TARGET_DISABLE__DISABLE_SE2_VIRT_MASK 0x00000020L +#define GCR_TARGET_DISABLE__DISABLE_SE3_PHY_MASK 0x00000040L +#define GCR_TARGET_DISABLE__DISABLE_SE3_VIRT_MASK 0x00000080L +#define GCR_TARGET_DISABLE__DISABLE_GL2A0_PHY_MASK 0x00000100L +#define GCR_TARGET_DISABLE__DISABLE_GL2A1_PHY_MASK 0x00000200L +#define GCR_TARGET_DISABLE__DISABLE_GL2A2_PHY_MASK 0x00000400L +#define GCR_TARGET_DISABLE__DISABLE_GL2A3_PHY_MASK 0x00000800L +#define GCR_TARGET_DISABLE__SE0_INACTIVE_STATUS_MASK 0x00010000L +#define GCR_TARGET_DISABLE__SE1_INACTIVE_STATUS_MASK 0x00020000L +#define GCR_TARGET_DISABLE__SE2_INACTIVE_STATUS_MASK 0x00040000L +#define GCR_TARGET_DISABLE__SE3_INACTIVE_STATUS_MASK 0x00080000L +#define GCR_TARGET_DISABLE__GL2A0_DISABLE_STATUS_MASK 0x01000000L +#define GCR_TARGET_DISABLE__GL2A1_DISABLE_STATUS_MASK 0x02000000L +#define GCR_TARGET_DISABLE__GL2A2_DISABLE_STATUS_MASK 0x04000000L +#define GCR_TARGET_DISABLE__GL2A3_DISABLE_STATUS_MASK 0x08000000L +//GCR_CMD_STATUS +#define GCR_CMD_STATUS__GCR_CONTROL__SHIFT 0x0 +#define GCR_CMD_STATUS__GCR_SRC__SHIFT 0x13 +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN__SHIFT 0x17 +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID__SHIFT 0x18 +#define GCR_CMD_STATUS__UTCL2_NACK_STATUS__SHIFT 0x1c +#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR__SHIFT 0x1e +#define GCR_CMD_STATUS__UTCL2_NACK_ERROR__SHIFT 0x1f +#define GCR_CMD_STATUS__GCR_CONTROL_MASK 0x0007FFFFL +#define GCR_CMD_STATUS__GCR_SRC_MASK 0x00780000L +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_MASK 0x00800000L +#define GCR_CMD_STATUS__GCR_TLB_SHOOTDOWN_VMID_MASK 0x0F000000L +#define GCR_CMD_STATUS__UTCL2_NACK_STATUS_MASK 0x30000000L +#define GCR_CMD_STATUS__GCR_SEQ_OP_ERROR_MASK 0x40000000L +#define GCR_CMD_STATUS__UTCL2_NACK_ERROR_MASK 0x80000000L +//GCR_SPARE +#define GCR_SPARE__SPARE_BIT_1__SHIFT 0x1 +#define GCR_SPARE__SPARE_BIT_2__SHIFT 0x2 +#define GCR_SPARE__SPARE_BIT_3__SHIFT 0x3 +#define GCR_SPARE__SPARE_BIT_4__SHIFT 0x4 +#define GCR_SPARE__SPARE_BIT_5__SHIFT 0x5 +#define GCR_SPARE__SPARE_BIT_6__SHIFT 0x6 +#define GCR_SPARE__SPARE_BIT_7__SHIFT 0x7 +#define GCR_SPARE__UTCL2_REQ_CREDIT__SHIFT 0x8 +#define GCR_SPARE__GCRD_GL2A_REQ_CREDIT__SHIFT 0x10 +#define GCR_SPARE__GCRD_SE_REQ_CREDIT__SHIFT 0x14 +#define GCR_SPARE__SPARE_BIT_31_24__SHIFT 0x18 +#define GCR_SPARE__SPARE_BIT_1_MASK 0x00000002L +#define GCR_SPARE__SPARE_BIT_2_MASK 0x00000004L +#define GCR_SPARE__SPARE_BIT_3_MASK 0x00000008L +#define GCR_SPARE__SPARE_BIT_4_MASK 0x00000010L +#define GCR_SPARE__SPARE_BIT_5_MASK 0x00000020L +#define GCR_SPARE__SPARE_BIT_6_MASK 0x00000040L +#define GCR_SPARE__SPARE_BIT_7_MASK 0x00000080L +#define GCR_SPARE__UTCL2_REQ_CREDIT_MASK 0x0000FF00L +#define GCR_SPARE__GCRD_GL2A_REQ_CREDIT_MASK 0x000F0000L +#define GCR_SPARE__GCRD_SE_REQ_CREDIT_MASK 0x00F00000L +#define GCR_SPARE__SPARE_BIT_31_24_MASK 0xFF000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_gfxudec +//CP_EOP_DONE_ADDR_LO +#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_EOP_DONE_ADDR_HI +#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_EOP_DONE_DATA_LO +#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xFFFFFFFFL +//CP_EOP_DONE_DATA_HI +#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_LO +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xFFFFFFFFL +//CP_EOP_LAST_FENCE_HI +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_ADDR_LO +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xFFFFFFFCL +//CP_PIPE_STATS_ADDR_HI +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0x0000FFFFL +//CP_VGT_IAVERT_COUNT_LO +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAVERT_COUNT_HI +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_LO +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_IAPRIM_COUNT_HI +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_LO +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSPRIM_COUNT_HI +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_LO +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_VSINVOC_COUNT_HI +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_LO +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_GSINVOC_COUNT_HI +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_LO +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_HSINVOC_COUNT_HI +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_LO +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_DSINVOC_COUNT_HI +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_LO +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CINVOC_COUNT_HI +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_LO +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_CPRIM_COUNT_HI +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_LO +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT0_HI +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_LO +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xFFFFFFFFL +//CP_SC_PSINVOC_COUNT1_HI +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_LO +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_CSINVOC_COUNT_HI +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_VGT_ASINVOC_COUNT_LO +#define CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_ASINVOC_COUNT_LO__ASINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_VGT_ASINVOC_COUNT_HI +#define CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_ASINVOC_COUNT_HI__ASINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_PIPE_STATS_CONTROL +#define CP_PIPE_STATS_CONTROL__SCOPE__SHIFT 0x17 +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY__SHIFT 0x19 +#define CP_PIPE_STATS_CONTROL__SCOPE_MASK 0x01800000L +#define CP_PIPE_STATS_CONTROL__CACHE_POLICY_MASK 0x06000000L +//SCRATCH_REG0 +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL +//SCRATCH_REG1 +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL +//SCRATCH_REG2 +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL +//SCRATCH_REG3 +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL +//SCRATCH_REG4 +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL +//SCRATCH_REG5 +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL +//SCRATCH_REG6 +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL +//SCRATCH_REG7 +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL +//SCRATCH_REG_ATOMIC +#define SCRATCH_REG_ATOMIC__IMMED__SHIFT 0x0 +#define SCRATCH_REG_ATOMIC__ID__SHIFT 0x18 +#define SCRATCH_REG_ATOMIC__reserved27__SHIFT 0x1b +#define SCRATCH_REG_ATOMIC__OP__SHIFT 0x1c +#define SCRATCH_REG_ATOMIC__reserved31__SHIFT 0x1f +#define SCRATCH_REG_ATOMIC__IMMED_MASK 0x00FFFFFFL +#define SCRATCH_REG_ATOMIC__ID_MASK 0x07000000L +#define SCRATCH_REG_ATOMIC__reserved27_MASK 0x08000000L +#define SCRATCH_REG_ATOMIC__OP_MASK 0x70000000L +#define SCRATCH_REG_ATOMIC__reserved31_MASK 0x80000000L +//SCRATCH_REG_CMPSWAP_ATOMIC +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE__SHIFT 0x0 +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE__SHIFT 0xc +#define SCRATCH_REG_CMPSWAP_ATOMIC__ID__SHIFT 0x18 +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27__SHIFT 0x1b +#define SCRATCH_REG_CMPSWAP_ATOMIC__OP__SHIFT 0x1c +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31__SHIFT 0x1f +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_COMPARE_MASK 0x00000FFFL +#define SCRATCH_REG_CMPSWAP_ATOMIC__IMMED_REPLACE_MASK 0x00FFF000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__ID_MASK 0x07000000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved27_MASK 0x08000000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__OP_MASK 0x70000000L +#define SCRATCH_REG_CMPSWAP_ATOMIC__reserved31_MASK 0x80000000L +//CP_APPEND_DDID_CNT +#define CP_APPEND_DDID_CNT__DATA__SHIFT 0x0 +#define CP_APPEND_DDID_CNT__DATA_MASK 0x000000FFL +//CP_APPEND_DATA_HI +#define CP_APPEND_DATA_HI__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_HI__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_HI +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_HI +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_HI__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_LO +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_PFP_ATOMIC_PREOP_HI +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_APPEND_ADDR_LO +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xFFFFFFFCL +//CP_APPEND_ADDR_HI +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 +#define CP_APPEND_ADDR_HI__FENCE_SIZE__SHIFT 0x12 +#define CP_APPEND_ADDR_HI__PWS_ENABLE__SHIFT 0x13 +#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 +#define CP_APPEND_ADDR_HI__SCOPE__SHIFT 0x1b +#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0x0000FFFFL +#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x00030000L +#define CP_APPEND_ADDR_HI__FENCE_SIZE_MASK 0x00040000L +#define CP_APPEND_ADDR_HI__PWS_ENABLE_MASK 0x00080000L +#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x06000000L +#define CP_APPEND_ADDR_HI__SCOPE_MASK 0x18000000L +#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xE0000000L +//CP_APPEND_DATA +#define CP_APPEND_DATA__DATA__SHIFT 0x0 +#define CP_APPEND_DATA__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_DATA_LO +#define CP_APPEND_DATA_LO__DATA__SHIFT 0x0 +#define CP_APPEND_DATA_LO__DATA_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_CS_FENCE_LO +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_APPEND_LAST_PS_FENCE_LO +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE_LO__LAST_FENCE_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_LO +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_LO +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xFFFFFFFFL +//CP_ATOMIC_PREOP_HI +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_ATOMIC_PREOP_HI +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_WADDR_LO +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_WADDR_HI +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 +#define CP_ME_MC_WADDR_HI__WRITE_CONFIRM__SHIFT 0x11 +#define CP_ME_MC_WADDR_HI__WRITE64__SHIFT 0x12 +#define CP_ME_MC_WADDR_HI__SCOPE__SHIFT 0x14 +#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_WADDR_HI__VMID__SHIFT 0x18 +#define CP_ME_MC_WADDR_HI__RINGID__SHIFT 0x1c +#define CP_ME_MC_WADDR_HI__PRIVILEGE__SHIFT 0x1f +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_WADDR_HI__WRITE_CONFIRM_MASK 0x00020000L +#define CP_ME_MC_WADDR_HI__WRITE64_MASK 0x00040000L +#define CP_ME_MC_WADDR_HI__SCOPE_MASK 0x00300000L +#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x00C00000L +#define CP_ME_MC_WADDR_HI__VMID_MASK 0x0F000000L +#define CP_ME_MC_WADDR_HI__RINGID_MASK 0x30000000L +#define CP_ME_MC_WADDR_HI__PRIVILEGE_MASK 0x80000000L +//CP_ME_MC_WDATA_LO +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xFFFFFFFFL +//CP_ME_MC_WDATA_HI +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xFFFFFFFFL +//CP_ME_MC_RADDR_LO +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xFFFFFFFCL +//CP_ME_MC_RADDR_HI +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 +#define CP_ME_MC_RADDR_HI__SIZE__SHIFT 0x10 +#define CP_ME_MC_RADDR_HI__SCOPE__SHIFT 0x14 +#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_RADDR_HI__VMID__SHIFT 0x18 +#define CP_ME_MC_RADDR_HI__PRIVILEGE__SHIFT 0x1f +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0x0000FFFFL +#define CP_ME_MC_RADDR_HI__SIZE_MASK 0x000F0000L +#define CP_ME_MC_RADDR_HI__SCOPE_MASK 0x00300000L +#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x00C00000L +#define CP_ME_MC_RADDR_HI__VMID_MASK 0x0F000000L +#define CP_ME_MC_RADDR_HI__PRIVILEGE_MASK 0x80000000L +//CP_WAIT_REG_MEM_TIMEOUT +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xFFFFFFFFL +//CP_DMA_PFP_CONTROL +#define CP_DMA_PFP_CONTROL__VMID__SHIFT 0x0 +#define CP_DMA_PFP_CONTROL__TMZ__SHIFT 0x4 +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_PFP_CONTROL__SRC_SCOPE__SHIFT 0xf +#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_PFP_CONTROL__DST_SCOPE__SHIFT 0x1b +#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_PFP_CONTROL__VMID_MASK 0x0000000FL +#define CP_DMA_PFP_CONTROL__TMZ_MASK 0x00000010L +#define CP_DMA_PFP_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L +#define CP_DMA_PFP_CONTROL__SRC_SCOPE_MASK 0x00018000L +#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L +#define CP_DMA_PFP_CONTROL__DST_SCOPE_MASK 0x18000000L +#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_DMA_ME_CONTROL +#define CP_DMA_ME_CONTROL__VMID__SHIFT 0x0 +#define CP_DMA_ME_CONTROL__TMZ__SHIFT 0x4 +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR__SHIFT 0xa +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_ME_CONTROL__SRC_SCOPE__SHIFT 0xf +#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_ME_CONTROL__DST_SCOPE__SHIFT 0x1b +#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_ME_CONTROL__VMID_MASK 0x0000000FL +#define CP_DMA_ME_CONTROL__TMZ_MASK 0x00000010L +#define CP_DMA_ME_CONTROL__MEMLOG_CLEAR_MASK 0x00000400L +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x00006000L +#define CP_DMA_ME_CONTROL__SRC_SCOPE_MASK 0x00018000L +#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x00300000L +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x06000000L +#define CP_DMA_ME_CONTROL__DST_SCOPE_MASK 0x18000000L +#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000L +//CP_DMA_ME_SRC_ADDR +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_SRC_ADDR_HI +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR_HI__SRC_TRANS_ERROR_TYPE__SHIFT 0x1b +#define CP_DMA_ME_SRC_ADDR_HI__SRC_TRANS_ERROR_VMID__SHIFT 0x1c +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_ME_SRC_ADDR_HI__SRC_TRANS_ERROR_TYPE_MASK 0x08000000L +#define CP_DMA_ME_SRC_ADDR_HI__SRC_TRANS_ERROR_VMID_MASK 0xF0000000L +//CP_DMA_ME_DST_ADDR +#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_ME_DST_ADDR_HI +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR_HI__DST_TRANS_ERROR_TYPE__SHIFT 0x1b +#define CP_DMA_ME_DST_ADDR_HI__DST_TRANS_ERROR_VMID__SHIFT 0x1c +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_ME_DST_ADDR_HI__DST_TRANS_ERROR_TYPE_MASK 0x08000000L +#define CP_DMA_ME_DST_ADDR_HI__DST_TRANS_ERROR_VMID_MASK 0xF0000000L +//CP_DMA_ME_COMMAND +#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_ME_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_ME_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_PFP_SRC_ADDR +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_SRC_ADDR_HI +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_DST_ADDR +#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xFFFFFFFFL +//CP_DMA_PFP_DST_ADDR_HI +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0x0000FFFFL +//CP_DMA_PFP_COMMAND +#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x1f +#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x03FFFFFFL +#define CP_DMA_PFP_COMMAND__SAS_MASK 0x04000000L +#define CP_DMA_PFP_COMMAND__DAS_MASK 0x08000000L +#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000L +#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000L +#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000L +#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x80000000L +//CP_DMA_CNTL +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL__SHIFT 0x0 +#define CP_DMA_CNTL__WATCH_CONTROL__SHIFT 0x1 +#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 +#define CP_DMA_CNTL__SPECULATIVE_DATA_READ__SHIFT 0x6 +#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c +#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d +#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e +#define CP_DMA_CNTL__UTCL1_FAULT_CONTROL_MASK 0x00000001L +#define CP_DMA_CNTL__WATCH_CONTROL_MASK 0x00000002L +#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x00000030L +#define CP_DMA_CNTL__SPECULATIVE_DATA_READ_MASK 0x000000C0L +#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0x01FF0000L +#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000L +#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000L +#define CP_DMA_CNTL__PIO_COUNT_MASK 0xC0000000L +//CP_DMA_READ_TAGS +#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c +#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x03FFFFFFL +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000L +//CP_PFP_IB_CONTROL +#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 +#define CP_PFP_IB_CONTROL__IB_EN_MASK 0x000000FFL +//CP_PFP_LOAD_CONTROL +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN__SHIFT 0xf +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 +#define CP_PFP_LOAD_CONTROL__LOAD_ORDINAL__SHIFT 0x1f +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x00000001L +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x00000002L +#define CP_PFP_LOAD_CONTROL__UCONFIG_REG_EN_MASK 0x00008000L +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x00010000L +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x01000000L +#define CP_PFP_LOAD_CONTROL__LOAD_ORDINAL_MASK 0x80000000L +//CP_SCRATCH_INDEX +#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//CP_SCRATCH_DATA +#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_RB_OFFSET +#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_RB_OFFSET__RB_OFFSET_MASK 0x000FFFFFL +//CP_IB1_OFFSET +#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0x000FFFFFL +//CP_IB2_OFFSET +#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0x000FFFFFL +//CP_IB1_PREAMBLE_BEGIN +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0x000FFFFFL +//CP_IB1_PREAMBLE_END +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_BEGIN +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0x000FFFFFL +//CP_IB2_PREAMBLE_END +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0x000FFFFFL +//CP_DMA_ME_CMD_ADDR_LO +#define CP_DMA_ME_CMD_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_DMA_ME_CMD_ADDR_LO__RSVD_MASK 0x00000003L +#define CP_DMA_ME_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_DMA_ME_CMD_ADDR_HI +#define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_CMD_ADDR_HI__RSVD__SHIFT 0x19 +#define CP_DMA_ME_CMD_ADDR_HI__ADDR_HI_MASK 0x01FFFFFFL +#define CP_DMA_ME_CMD_ADDR_HI__RSVD_MASK 0xFE000000L +//CP_DMA_PFP_CMD_ADDR_LO +#define CP_DMA_PFP_CMD_ADDR_LO__RSVD__SHIFT 0x0 +#define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_DMA_PFP_CMD_ADDR_LO__RSVD_MASK 0x00000003L +#define CP_DMA_PFP_CMD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFCL +//CP_DMA_PFP_CMD_ADDR_HI +#define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_CMD_ADDR_HI__RSVD__SHIFT 0x10 +#define CP_DMA_PFP_CMD_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +#define CP_DMA_PFP_CMD_ADDR_HI__RSVD_MASK 0xFFFF0000L +//UCONFIG_RESERVED_REG0 +#define UCONFIG_RESERVED_REG0__DATA__SHIFT 0x0 +#define UCONFIG_RESERVED_REG0__DATA_MASK 0xFFFFFFFFL +//UCONFIG_RESERVED_REG1 +#define UCONFIG_RESERVED_REG1__DATA__SHIFT 0x0 +#define UCONFIG_RESERVED_REG1__DATA_MASK 0xFFFFFFFFL +//CP_PA_MSPRIM_COUNT_LO +#define CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_MSPRIM_COUNT_LO__MSPRIM_COUNT_LO_MASK 0xFFFFFFFFL +//CP_PA_MSPRIM_COUNT_HI +#define CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_PA_MSPRIM_COUNT_HI__MSPRIM_COUNT_HI_MASK 0xFFFFFFFFL +//CP_GE_MSINVOC_COUNT_LO +#define CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_GE_MSINVOC_COUNT_LO__MSINVOC_COUNT_LO_MASK 0xFFFFFFFFL +//CP_GE_MSINVOC_COUNT_HI +#define CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_GE_MSINVOC_COUNT_HI__MSINVOC_COUNT_HI_MASK 0xFFFFFFFFL +//CP_IB1_CMD_BUFSZ +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ__SHIFT 0x0 +#define CP_IB1_CMD_BUFSZ__IB1_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB2_CMD_BUFSZ +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ__SHIFT 0x0 +#define CP_IB2_CMD_BUFSZ__IB2_CMD_REQSZ_MASK 0x000FFFFFL +//CP_ST_CMD_BUFSZ +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ__SHIFT 0x0 +#define CP_ST_CMD_BUFSZ__ST_CMD_REQSZ_MASK 0x000FFFFFL +//CP_IB1_BASE_LO +#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xFFFFFFFCL +//CP_IB1_BASE_HI +#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0x0000FFFFL +//CP_IB1_BUFSZ +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0x000FFFFFL +//CP_IB2_BASE_LO +#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xFFFFFFFCL +//CP_IB2_BASE_HI +#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0x0000FFFFL +//CP_IB2_BUFSZ +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0x000FFFFFL +//CP_ST_BASE_LO +#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 +#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xFFFFFFFCL +//CP_ST_BASE_HI +#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 +#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0x0000FFFFL +//CP_ST_BUFSZ +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0x000FFFFFL +//CP_EOP_DONE_EVENT_CNTL +#define CP_EOP_DONE_EVENT_CNTL__SCOPE__SHIFT 0x7 +#define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL__SHIFT 0xc +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY__SHIFT 0x19 +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE__SHIFT 0x1c +#define CP_EOP_DONE_EVENT_CNTL__GLK_INV__SHIFT 0x1e +#define CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE__SHIFT 0x1f +#define CP_EOP_DONE_EVENT_CNTL__SCOPE_MASK 0x00000180L +#define CP_EOP_DONE_EVENT_CNTL__GCR_CNTL_MASK 0x01FFF000L +#define CP_EOP_DONE_EVENT_CNTL__CACHE_POLICY_MASK 0x06000000L +#define CP_EOP_DONE_EVENT_CNTL__EXECUTE_MASK 0x10000000L +#define CP_EOP_DONE_EVENT_CNTL__GLK_INV_MASK 0x40000000L +#define CP_EOP_DONE_EVENT_CNTL__PWS_ENABLE_MASK 0x80000000L +//CP_EOP_DONE_DATA_CNTL +#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 +#define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID__SHIFT 0x14 +#define CP_EOP_DONE_DATA_CNTL__ACTION_ID__SHIFT 0x16 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d +#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x00030000L +#define CP_EOP_DONE_DATA_CNTL__ACTION_PIPE_ID_MASK 0x00300000L +#define CP_EOP_DONE_DATA_CNTL__ACTION_ID_MASK 0x00C00000L +#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x07000000L +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xE0000000L +//CP_EOP_DONE_CNTX_ID +#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xFFFFFFFFL +//CP_DB_BASE_LO +#define CP_DB_BASE_LO__DB_BASE_LO__SHIFT 0x2 +#define CP_DB_BASE_LO__DB_BASE_LO_MASK 0xFFFFFFFCL +//CP_DB_BASE_HI +#define CP_DB_BASE_HI__DB_BASE_HI__SHIFT 0x0 +#define CP_DB_BASE_HI__DB_BASE_HI_MASK 0x0000FFFFL +//CP_DB_BUFSZ +#define CP_DB_BUFSZ__DB_BUFSZ__SHIFT 0x0 +#define CP_DB_BUFSZ__DB_BUFSZ_MASK 0x000FFFFFL +//CP_DB_CMD_BUFSZ +#define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ__SHIFT 0x0 +#define CP_DB_CMD_BUFSZ__DB_CMD_REQSZ_MASK 0x000FFFFFL +//CP_PFP_COMPLETION_STATUS +#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x00000003L +//CP_PRED_NOT_VISIBLE +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x00000001L +//CP_PFP_METADATA_BASE_ADDR +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_PFP_METADATA_BASE_ADDR_HI +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DRAW_INDX_INDR_ADDR +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DRAW_INDX_INDR_ADDR_HI +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_DISPATCH_INDR_ADDR +#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_DISPATCH_INDR_ADDR_HI +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_BASE_ADDR +#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xFFFFFFFFL +//CP_INDEX_BASE_ADDR_HI +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//CP_INDEX_TYPE +#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +//CP_SAMPLE_STATUS +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x00000001L +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x00000002L +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x00000004L +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x00000008L +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x00000010L +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x00000020L +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x00000040L +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x00000080L +//CP_ME_COHER_CNTL +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 +#define CP_ME_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x00000001L +#define CP_ME_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x00000002L +#define CP_ME_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x00000040L +#define CP_ME_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x00000080L +#define CP_ME_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x00000100L +#define CP_ME_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x00000200L +#define CP_ME_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x00000400L +#define CP_ME_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x00000800L +#define CP_ME_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x00001000L +#define CP_ME_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x00002000L +#define CP_ME_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x00004000L +#define CP_ME_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x00080000L +#define CP_ME_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x00200000L +//CP_ME_COHER_SIZE +#define CP_ME_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE__COHER_SIZE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_SIZE_HI +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_BASE +#define CP_ME_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE__COHER_BASE_256B_MASK 0xFFFFFFFFL +//CP_ME_COHER_BASE_HI +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_ME_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0x000000FFL +//CP_ME_COHER_STATUS +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 +#define CP_ME_COHER_STATUS__STATUS__SHIFT 0x1f +#define CP_ME_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0x000000FFL +#define CP_ME_COHER_STATUS__STATUS_MASK 0x80000000L +//RLC_GPM_PERF_COUNT_0 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_0__SA_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_0__WGP_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_0__SA_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_0__WGP_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xFFE00000L +//RLC_GPM_PERF_COUNT_1 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_1__SA_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_1__WGP_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0x0000000FL +#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0x000000F0L +#define RLC_GPM_PERF_COUNT_1__SA_INDEX_MASK 0x00000F00L +#define RLC_GPM_PERF_COUNT_1__WGP_INDEX_MASK 0x0000F000L +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x00030000L +#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0x000C0000L +#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x00100000L +#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xFFE00000L +//GRBM_GFX_INDEX +#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX__SA_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0x0000007FL +#define GRBM_GFX_INDEX__SA_INDEX_MASK 0x00000300L +#define GRBM_GFX_INDEX__SE_INDEX_MASK 0x000F0000L +#define GRBM_GFX_INDEX__SA_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000L +//GRBM_NOWHERE_2 +#define GRBM_NOWHERE_2__DATA__SHIFT 0x0 +#define GRBM_NOWHERE_2__DATA_MASK 0xFFFFFFFFL +//VGT_PRIMITIVE_TYPE +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_PRIMITIVE_TYPE__NUM_INPUT_CP__SHIFT 0x6 +#define VGT_PRIMITIVE_TYPE__PRIMS_PER_SUBGROUP__SHIFT 0xc +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x0000003FL +#define VGT_PRIMITIVE_TYPE__NUM_INPUT_CP_MASK 0x00000FC0L +#define VGT_PRIMITIVE_TYPE__PRIMS_PER_SUBGROUP_MASK 0x001FF000L +//VGT_INDEX_TYPE +#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING__SHIFT 0xe +#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x00000003L +#define VGT_INDEX_TYPE__DISABLE_INSTANCE_PACKING_MASK 0x00004000L +//GE_MIN_VTX_INDX +#define GE_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 +#define GE_MIN_VTX_INDX__MIN_INDX_MASK 0xFFFFFFFFL +//GE_INDX_OFFSET +#define GE_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 +#define GE_INDX_OFFSET__INDX_OFFSET_MASK 0xFFFFFFFFL +//GE_MULTI_PRIM_IB_RESET_EN +#define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 +#define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS__SHIFT 0x1 +#define GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX__SHIFT 0x2 +#define GE_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x00000001L +#define GE_MULTI_PRIM_IB_RESET_EN__MATCH_ALL_BITS_MASK 0x00000002L +#define GE_MULTI_PRIM_IB_RESET_EN__DISABLE_FOR_AUTO_INDEX_MASK 0x00000004L +//VGT_NUM_INDICES +#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 +#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xFFFFFFFFL +//VGT_NUM_INSTANCES +#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xFFFFFFFFL +//VGT_TF_MEMORY_BASE +#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE__BASE_MASK 0xFFFFFFFFL +//GE_GS_THROTTLE +#define GE_GS_THROTTLE__T0__SHIFT 0x0 +#define GE_GS_THROTTLE__T1__SHIFT 0x3 +#define GE_GS_THROTTLE__T2__SHIFT 0x6 +#define GE_GS_THROTTLE__STALL_CYCLES__SHIFT 0x9 +#define GE_GS_THROTTLE__FACTOR1__SHIFT 0x10 +#define GE_GS_THROTTLE__FACTOR2__SHIFT 0x13 +#define GE_GS_THROTTLE__ENABLE_THROTTLE__SHIFT 0x16 +#define GE_GS_THROTTLE__NUM_INIT_GRPS__SHIFT 0x17 +#define GE_GS_THROTTLE__T0_MASK 0x00000007L +#define GE_GS_THROTTLE__T1_MASK 0x00000038L +#define GE_GS_THROTTLE__T2_MASK 0x000001C0L +#define GE_GS_THROTTLE__STALL_CYCLES_MASK 0x0000FE00L +#define GE_GS_THROTTLE__FACTOR1_MASK 0x00070000L +#define GE_GS_THROTTLE__FACTOR2_MASK 0x00380000L +#define GE_GS_THROTTLE__ENABLE_THROTTLE_MASK 0x00400000L +#define GE_GS_THROTTLE__NUM_INIT_GRPS_MASK 0x7F800000L +//GE_MAX_VTX_INDX +#define GE_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 +#define GE_MAX_VTX_INDX__MAX_INDX_MASK 0xFFFFFFFFL +//VGT_INSTANCE_BASE_ID +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 +#define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL +//GE_CNTL +#define GE_CNTL__PRIMS_PER_SUBGRP__SHIFT 0x0 +#define GE_CNTL__VERTS_PER_SUBGRP__SHIFT 0x9 +#define GE_CNTL__BREAK_SUBGRP_AT_EOI__SHIFT 0x12 +#define GE_CNTL__PACKET_TO_ONE_PA__SHIFT 0x13 +#define GE_CNTL__BREAK_PRIMGRP_AT_EOI__SHIFT 0x14 +#define GE_CNTL__PRIM_GRP_SIZE__SHIFT 0x15 +#define GE_CNTL__GCR_DISABLE__SHIFT 0x1e +#define GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP__SHIFT 0x1f +#define GE_CNTL__PRIMS_PER_SUBGRP_MASK 0x000001FFL +#define GE_CNTL__VERTS_PER_SUBGRP_MASK 0x0003FE00L +#define GE_CNTL__BREAK_SUBGRP_AT_EOI_MASK 0x00040000L +#define GE_CNTL__PACKET_TO_ONE_PA_MASK 0x00080000L +#define GE_CNTL__BREAK_PRIMGRP_AT_EOI_MASK 0x00100000L +#define GE_CNTL__PRIM_GRP_SIZE_MASK 0x3FE00000L +#define GE_CNTL__GCR_DISABLE_MASK 0x40000000L +#define GE_CNTL__DIS_PG_SIZE_ADJUST_FOR_STRIP_MASK 0x80000000L +//GE_USER_VGPR1 +#define GE_USER_VGPR1__DATA__SHIFT 0x0 +#define GE_USER_VGPR1__DATA_MASK 0xFFFFFFFFL +//GE_USER_VGPR2 +#define GE_USER_VGPR2__DATA__SHIFT 0x0 +#define GE_USER_VGPR2__DATA_MASK 0xFFFFFFFFL +//GE_USER_VGPR3 +#define GE_USER_VGPR3__DATA__SHIFT 0x0 +#define GE_USER_VGPR3__DATA_MASK 0xFFFFFFFFL +//GE_STEREO_CNTL +#define GE_STEREO_CNTL__RT_SLICE__SHIFT 0x0 +#define GE_STEREO_CNTL__VIEWPORT__SHIFT 0x3 +#define GE_STEREO_CNTL__UNUSED__SHIFT 0x7 +#define GE_STEREO_CNTL__EN_STEREO__SHIFT 0x8 +#define GE_STEREO_CNTL__RT_SLICE_MASK 0x00000007L +#define GE_STEREO_CNTL__VIEWPORT_MASK 0x00000078L +#define GE_STEREO_CNTL__UNUSED_MASK 0x00000080L +#define GE_STEREO_CNTL__EN_STEREO_MASK 0x00000100L +//GE_USER_VGPR_EN +#define GE_USER_VGPR_EN__EN_USER_VGPR1__SHIFT 0x0 +#define GE_USER_VGPR_EN__EN_USER_VGPR2__SHIFT 0x1 +#define GE_USER_VGPR_EN__EN_USER_VGPR3__SHIFT 0x2 +#define GE_USER_VGPR_EN__EN_USER_VGPR1_MASK 0x00000001L +#define GE_USER_VGPR_EN__EN_USER_VGPR2_MASK 0x00000002L +#define GE_USER_VGPR_EN__EN_USER_VGPR3_MASK 0x00000004L +//VGT_PRIMITIVEID_EN +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE__SHIFT 0x2 +#define VGT_PRIMITIVEID_EN__NGG_DISABLE_PROVOK_REUSE_MASK 0x00000004L +//GE_VRS_RATE +#define GE_VRS_RATE__RATE_X__SHIFT 0x0 +#define GE_VRS_RATE__RATE_Y__SHIFT 0x4 +#define GE_VRS_RATE__RATE_X_MASK 0x00000003L +#define GE_VRS_RATE__RATE_Y_MASK 0x00000030L +//GE_GS_FAST_LAUNCH_WG_DIM +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X__SHIFT 0x0 +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y__SHIFT 0x10 +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_X_MASK 0x0000FFFFL +#define GE_GS_FAST_LAUNCH_WG_DIM__GS_FL_DIM_Y_MASK 0xFFFF0000L +//GE_GS_FAST_LAUNCH_WG_DIM_1 +#define GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z__SHIFT 0x0 +#define GE_GS_FAST_LAUNCH_WG_DIM_1__GS_FL_DIM_Z_MASK 0x0000FFFFL +//VGT_GS_OUT_PRIM_TYPE +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x0000003FL +//VGT_TF_MEMORY_BASE_HI +#define VGT_TF_MEMORY_BASE_HI__BASE_HI__SHIFT 0x0 +#define VGT_TF_MEMORY_BASE_HI__BASE_HI_MASK 0x000000FFL +//GE_GS_ORDERED_ID_BASE +#define GE_GS_ORDERED_ID_BASE__BASE__SHIFT 0x0 +#define GE_GS_ORDERED_ID_BASE__BASE_MASK 0x00000FFFL +//VGT_PRIMITIVEID_RESET +#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 +#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cprs64dec +//CP_MES_PRGRM_CNTR_START +#define CP_MES_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MES_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_MES_INTR_ROUTINE_START +#define CP_MES_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MES_INTR_ROUTINE_START__IR_START_MASK 0xFFFFFFFFL +//CP_MES_MTVEC_LO +#define CP_MES_MTVEC_LO__ADDR_LO__SHIFT 0x0 +#define CP_MES_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MES_INTR_ROUTINE_START_HI +#define CP_MES_INTR_ROUTINE_START_HI__IR_START__SHIFT 0x0 +#define CP_MES_INTR_ROUTINE_START_HI__IR_START_MASK 0xFFFFFFFFL +//CP_MES_MTVEC_HI +#define CP_MES_MTVEC_HI__ADDR_LO__SHIFT 0x0 +#define CP_MES_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MES_CNTL +#define CP_MES_CNTL__MES_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MES_CNTL__MES_PIPE0_RESET__SHIFT 0x10 +#define CP_MES_CNTL__MES_PIPE1_RESET__SHIFT 0x11 +#define CP_MES_CNTL__MES_PIPE2_RESET__SHIFT 0x12 +#define CP_MES_CNTL__MES_PIPE3_RESET__SHIFT 0x13 +#define CP_MES_CNTL__MES_PIPE0_ACTIVE__SHIFT 0x1a +#define CP_MES_CNTL__MES_PIPE1_ACTIVE__SHIFT 0x1b +#define CP_MES_CNTL__MES_PIPE2_ACTIVE__SHIFT 0x1c +#define CP_MES_CNTL__MES_PIPE3_ACTIVE__SHIFT 0x1d +#define CP_MES_CNTL__MES_HALT__SHIFT 0x1e +#define CP_MES_CNTL__MES_STEP__SHIFT 0x1f +#define CP_MES_CNTL__MES_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_MES_CNTL__MES_PIPE0_RESET_MASK 0x00010000L +#define CP_MES_CNTL__MES_PIPE1_RESET_MASK 0x00020000L +#define CP_MES_CNTL__MES_PIPE2_RESET_MASK 0x00040000L +#define CP_MES_CNTL__MES_PIPE3_RESET_MASK 0x00080000L +#define CP_MES_CNTL__MES_PIPE0_ACTIVE_MASK 0x04000000L +#define CP_MES_CNTL__MES_PIPE1_ACTIVE_MASK 0x08000000L +#define CP_MES_CNTL__MES_PIPE2_ACTIVE_MASK 0x10000000L +#define CP_MES_CNTL__MES_PIPE3_ACTIVE_MASK 0x20000000L +#define CP_MES_CNTL__MES_HALT_MASK 0x40000000L +#define CP_MES_CNTL__MES_STEP_MASK 0x80000000L +//CP_MES_PIPE_PRIORITY_CNTS +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define CP_MES_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//CP_MES_PIPE0_PRIORITY +#define CP_MES_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_PIPE1_PRIORITY +#define CP_MES_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_PIPE2_PRIORITY +#define CP_MES_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_PIPE3_PRIORITY +#define CP_MES_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_MES_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//CP_MES_HEADER_DUMP +#define CP_MES_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MES_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//CP_MES_MIE_LO +#define CP_MES_MIE_LO__MES_INT__SHIFT 0x0 +#define CP_MES_MIE_LO__MES_INT_MASK 0xFFFFFFFFL +//CP_MES_MIE_HI +#define CP_MES_MIE_HI__MES_INT__SHIFT 0x0 +#define CP_MES_MIE_HI__MES_INT_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT +#define CP_MES_INTERRUPT__MES_INT__SHIFT 0x0 +#define CP_MES_INTERRUPT__MES_INT_MASK 0xFFFFFFFFL +//CP_MES_SCRATCH_INDEX +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +#define CP_MES_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//CP_MES_SCRATCH_DATA +#define CP_MES_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_MES_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//CP_MES_INSTR_PNTR +#define CP_MES_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MES_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL +//CP_MES_MSCRATCH_HI +#define CP_MES_MSCRATCH_HI__DATA__SHIFT 0x0 +#define CP_MES_MSCRATCH_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_MSCRATCH_LO +#define CP_MES_MSCRATCH_LO__DATA__SHIFT 0x0 +#define CP_MES_MSCRATCH_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_MSTATUS_LO +#define CP_MES_MSTATUS_LO__STATUS_LO__SHIFT 0x0 +#define CP_MES_MSTATUS_LO__STATUS_LO_MASK 0xFFFFFFFFL +//CP_MES_MSTATUS_HI +#define CP_MES_MSTATUS_HI__STATUS_HI__SHIFT 0x0 +#define CP_MES_MSTATUS_HI__STATUS_HI_MASK 0xFFFFFFFFL +//CP_MES_MEPC_LO +#define CP_MES_MEPC_LO__MEPC_LO__SHIFT 0x0 +#define CP_MES_MEPC_LO__MEPC_LO_MASK 0xFFFFFFFFL +//CP_MES_MEPC_HI +#define CP_MES_MEPC_HI__MEPC_HI__SHIFT 0x0 +#define CP_MES_MEPC_HI__MEPC_HI_MASK 0xFFFFFFFFL +//CP_MES_MCAUSE_LO +#define CP_MES_MCAUSE_LO__CAUSE_LO__SHIFT 0x0 +#define CP_MES_MCAUSE_LO__CAUSE_LO_MASK 0xFFFFFFFFL +//CP_MES_MCAUSE_HI +#define CP_MES_MCAUSE_HI__CAUSE_HI__SHIFT 0x0 +#define CP_MES_MCAUSE_HI__CAUSE_HI_MASK 0xFFFFFFFFL +//CP_MES_MBADADDR_LO +#define CP_MES_MBADADDR_LO__ADDR_LO__SHIFT 0x0 +#define CP_MES_MBADADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MES_MBADADDR_HI +#define CP_MES_MBADADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_MES_MBADADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//CP_MES_MIP_LO +#define CP_MES_MIP_LO__MIP_LO__SHIFT 0x0 +#define CP_MES_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL +//CP_MES_MIP_HI +#define CP_MES_MIP_HI__MIP_HI__SHIFT 0x0 +#define CP_MES_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL +//CP_MES_IC_OP_CNTL +#define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_MES_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_MES_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_MES_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_MES_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_MES_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_MES_MCYCLE_LO +#define CP_MES_MCYCLE_LO__CYCLE_LO__SHIFT 0x0 +#define CP_MES_MCYCLE_LO__CYCLE_LO_MASK 0xFFFFFFFFL +//CP_MES_MCYCLE_HI +#define CP_MES_MCYCLE_HI__CYCLE_HI__SHIFT 0x0 +#define CP_MES_MCYCLE_HI__CYCLE_HI_MASK 0xFFFFFFFFL +//CP_MES_MTIME_LO +#define CP_MES_MTIME_LO__TIME_LO__SHIFT 0x0 +#define CP_MES_MTIME_LO__TIME_LO_MASK 0xFFFFFFFFL +//CP_MES_MTIME_HI +#define CP_MES_MTIME_HI__TIME_HI__SHIFT 0x0 +#define CP_MES_MTIME_HI__TIME_HI_MASK 0xFFFFFFFFL +//CP_MES_MINSTRET_LO +#define CP_MES_MINSTRET_LO__INSTRET_LO__SHIFT 0x0 +#define CP_MES_MINSTRET_LO__INSTRET_LO_MASK 0xFFFFFFFFL +//CP_MES_MINSTRET_HI +#define CP_MES_MINSTRET_HI__INSTRET_HI__SHIFT 0x0 +#define CP_MES_MINSTRET_HI__INSTRET_HI_MASK 0xFFFFFFFFL +//CP_MES_MISA_LO +#define CP_MES_MISA_LO__MISA_LO__SHIFT 0x0 +#define CP_MES_MISA_LO__MISA_LO_MASK 0xFFFFFFFFL +//CP_MES_MISA_HI +#define CP_MES_MISA_HI__MISA_HI__SHIFT 0x0 +#define CP_MES_MISA_HI__MISA_HI_MASK 0xFFFFFFFFL +//CP_MES_MVENDORID_LO +#define CP_MES_MVENDORID_LO__MVENDORID_LO__SHIFT 0x0 +#define CP_MES_MVENDORID_LO__MVENDORID_LO_MASK 0xFFFFFFFFL +//CP_MES_MVENDORID_HI +#define CP_MES_MVENDORID_HI__MVENDORID_HI__SHIFT 0x0 +#define CP_MES_MVENDORID_HI__MVENDORID_HI_MASK 0xFFFFFFFFL +//CP_MES_MARCHID_LO +#define CP_MES_MARCHID_LO__MARCHID_LO__SHIFT 0x0 +#define CP_MES_MARCHID_LO__MARCHID_LO_MASK 0xFFFFFFFFL +//CP_MES_MARCHID_HI +#define CP_MES_MARCHID_HI__MARCHID_HI__SHIFT 0x0 +#define CP_MES_MARCHID_HI__MARCHID_HI_MASK 0xFFFFFFFFL +//CP_MES_MIMPID_LO +#define CP_MES_MIMPID_LO__MIMPID_LO__SHIFT 0x0 +#define CP_MES_MIMPID_LO__MIMPID_LO_MASK 0xFFFFFFFFL +//CP_MES_MIMPID_HI +#define CP_MES_MIMPID_HI__MIMPID_HI__SHIFT 0x0 +#define CP_MES_MIMPID_HI__MIMPID_HI_MASK 0xFFFFFFFFL +//CP_MES_MHARTID_LO +#define CP_MES_MHARTID_LO__MHARTID_LO__SHIFT 0x0 +#define CP_MES_MHARTID_LO__MHARTID_LO_MASK 0xFFFFFFFFL +//CP_MES_MHARTID_HI +#define CP_MES_MHARTID_HI__MHARTID_HI__SHIFT 0x0 +#define CP_MES_MHARTID_HI__MHARTID_HI_MASK 0xFFFFFFFFL +//CP_MES_DC_BASE_CNTL +#define CP_MES_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_MES_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_MES_DC_BASE_CNTL__SCOPE__SHIFT 0x1a +#define CP_MES_DC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_MES_DC_BASE_CNTL__SCOPE_MASK 0x0C000000L +//CP_MES_DC_OP_CNTL +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define CP_MES_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define CP_MES_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define CP_MES_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +//CP_MES_MTIMECMP_LO +#define CP_MES_MTIMECMP_LO__TIME_LO__SHIFT 0x0 +#define CP_MES_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL +//CP_MES_MTIMECMP_HI +#define CP_MES_MTIMECMP_HI__TIME_HI__SHIFT 0x0 +#define CP_MES_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL +//CP_MES_PROCESS_QUANTUM_PIPE0 +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION__SHIFT 0x0 +#define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED__SHIFT 0x1c +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE__SHIFT 0x1d +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN__SHIFT 0x1f +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_DURATION_MASK 0x0FFFFFFFL +#define CP_MES_PROCESS_QUANTUM_PIPE0__TIMER_EXPIRED_MASK 0x10000000L +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_SCALE_MASK 0x60000000L +#define CP_MES_PROCESS_QUANTUM_PIPE0__QUANTUM_EN_MASK 0x80000000L +//CP_MES_PROCESS_QUANTUM_PIPE1 +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION__SHIFT 0x0 +#define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED__SHIFT 0x1c +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE__SHIFT 0x1d +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN__SHIFT 0x1f +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_DURATION_MASK 0x0FFFFFFFL +#define CP_MES_PROCESS_QUANTUM_PIPE1__TIMER_EXPIRED_MASK 0x10000000L +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_SCALE_MASK 0x60000000L +#define CP_MES_PROCESS_QUANTUM_PIPE1__QUANTUM_EN_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL1 +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL1__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL2 +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL2__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL3 +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL3__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL4 +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL4__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL5 +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL5__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_DOORBELL_CONTROL6 +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN__SHIFT 0x1e +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT__SHIFT 0x1f +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_OFFSET_MASK 0x0FFFFFFCL +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_EN_MASK 0x40000000L +#define CP_MES_DOORBELL_CONTROL6__DOORBELL_HIT_MASK 0x80000000L +//CP_MES_GP0_LO +#define CP_MES_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MES_GP0_LO__DATA__SHIFT 0x1 +#define CP_MES_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MES_GP0_LO__DATA_MASK 0xFFFFFFFEL +//CP_MES_GP0_HI +#define CP_MES_GP0_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MES_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MES_GP1_LO +#define CP_MES_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MES_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MES_GP1_HI +#define CP_MES_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MES_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MES_GP2_LO +#define CP_MES_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MES_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MES_GP2_HI +#define CP_MES_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MES_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MES_GP3_LO +#define CP_MES_GP3_LO__DATA__SHIFT 0x0 +#define CP_MES_GP3_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP3_HI +#define CP_MES_GP3_HI__DATA__SHIFT 0x0 +#define CP_MES_GP3_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP4_LO +#define CP_MES_GP4_LO__DATA__SHIFT 0x0 +#define CP_MES_GP4_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP4_HI +#define CP_MES_GP4_HI__DATA__SHIFT 0x0 +#define CP_MES_GP4_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP5_LO +#define CP_MES_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MES_GP5_LO__DATA__SHIFT 0x1 +#define CP_MES_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MES_GP5_LO__DATA_MASK 0xFFFFFFFEL +//CP_MES_GP5_HI +#define CP_MES_GP5_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MES_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MES_GP6_LO +#define CP_MES_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MES_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MES_GP6_HI +#define CP_MES_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MES_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MES_GP7_LO +#define CP_MES_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MES_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MES_GP7_HI +#define CP_MES_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MES_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MES_GP8_LO +#define CP_MES_GP8_LO__DATA__SHIFT 0x0 +#define CP_MES_GP8_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP8_HI +#define CP_MES_GP8_HI__DATA__SHIFT 0x0 +#define CP_MES_GP8_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP9_LO +#define CP_MES_GP9_LO__DATA__SHIFT 0x0 +#define CP_MES_GP9_LO__DATA_MASK 0xFFFFFFFFL +//CP_MES_GP9_HI +#define CP_MES_GP9_HI__DATA__SHIFT 0x0 +#define CP_MES_GP9_HI__DATA_MASK 0xFFFFFFFFL +//CP_MES_LOCAL_BASE0_LO +#define CP_MES_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define CP_MES_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_BASE0_HI +#define CP_MES_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define CP_MES_LOCAL_BASE0_HI__BASE0_HI_MASK 0x01FFFFFFL +//CP_MES_LOCAL_MASK0_LO +#define CP_MES_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define CP_MES_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_MASK0_HI +#define CP_MES_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define CP_MES_LOCAL_MASK0_HI__MASK0_HI_MASK 0x01FFFFFFL +//CP_MES_LOCAL_APERTURE +#define CP_MES_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MES_LOCAL_APERTURE__SCOPE__SHIFT 0x6 +#define CP_MES_LOCAL_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_MES_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +#define CP_MES_LOCAL_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_MES_LOCAL_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_MES_LOCAL_INSTR_BASE_LO +#define CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MES_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_INSTR_BASE_HI +#define CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MES_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MES_LOCAL_INSTR_MASK_LO +#define CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define CP_MES_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_INSTR_MASK_HI +#define CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define CP_MES_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x01FFFFFFL +//CP_MES_LOCAL_INSTR_APERTURE +#define CP_MES_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MES_LOCAL_INSTR_APERTURE__SCOPE__SHIFT 0x6 +#define CP_MES_LOCAL_INSTR_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_MES_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +#define CP_MES_LOCAL_INSTR_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_MES_LOCAL_INSTR_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_MES_LOCAL_SCRATCH_APERTURE +#define CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MES_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//CP_MES_LOCAL_SCRATCH_BASE_LO +#define CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MES_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MES_LOCAL_SCRATCH_BASE_HI +#define CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MES_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MES_PERFCOUNT_CNTL +#define CP_MES_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 +#define CP_MES_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL +//CP_MES_PENDING_INTERRUPT +#define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_MES_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_MES_RS64_EXCEPTION_STATUS +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION__SHIFT 0x0 +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR__SHIFT 0x1 +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION__SHIFT 0x2 +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT__SHIFT 0x3 +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR__SHIFT 0x4 +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION_MASK 0x00000001L +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR_MASK 0x00000002L +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION_MASK 0x00000004L +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT_MASK 0x00000008L +#define CP_MES_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR_MASK 0x07FFFFF0L +//CP_MES_PRGRM_CNTR_START_HI +#define CP_MES_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_MES_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_MES_INTERRUPT_DATA_16 +#define CP_MES_INTERRUPT_DATA_16__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_17 +#define CP_MES_INTERRUPT_DATA_17__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_18 +#define CP_MES_INTERRUPT_DATA_18__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_19 +#define CP_MES_INTERRUPT_DATA_19__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_20 +#define CP_MES_INTERRUPT_DATA_20__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_21 +#define CP_MES_INTERRUPT_DATA_21__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_22 +#define CP_MES_INTERRUPT_DATA_22__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_23 +#define CP_MES_INTERRUPT_DATA_23__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_24 +#define CP_MES_INTERRUPT_DATA_24__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_25 +#define CP_MES_INTERRUPT_DATA_25__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_26 +#define CP_MES_INTERRUPT_DATA_26__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_27 +#define CP_MES_INTERRUPT_DATA_27__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_28 +#define CP_MES_INTERRUPT_DATA_28__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_29 +#define CP_MES_INTERRUPT_DATA_29__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_30 +#define CP_MES_INTERRUPT_DATA_30__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL +//CP_MES_INTERRUPT_DATA_31 +#define CP_MES_INTERRUPT_DATA_31__DATA__SHIFT 0x0 +#define CP_MES_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL +//CP_MES_METADATA_CNTL +#define CP_MES_METADATA_CNTL__SCOPE__SHIFT 0x6 +#define CP_MES_METADATA_CNTL__TEMPORAL__SHIFT 0x8 +#define CP_MES_METADATA_CNTL__SCOPE_MASK 0x000000C0L +#define CP_MES_METADATA_CNTL__TEMPORAL_MASK 0x00000700L +//CP_MEC_RS64_PRGRM_CNTR_START +#define CP_MEC_RS64_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC_RS64_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//CP_MEC_MTVEC_LO +#define CP_MEC_MTVEC_LO__ADDR_LO__SHIFT 0x0 +#define CP_MEC_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MEC_MTVEC_HI +#define CP_MEC_MTVEC_HI__ADDR_LO__SHIFT 0x0 +#define CP_MEC_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL +//CP_MEC_RS64_CNTL +#define CP_MEC_RS64_CNTL__SPARE__SHIFT 0x0 +#define CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MEC_RS64_CNTL__MEC_PIPE0_RESET__SHIFT 0x10 +#define CP_MEC_RS64_CNTL__MEC_PIPE1_RESET__SHIFT 0x11 +#define CP_MEC_RS64_CNTL__MEC_PIPE2_RESET__SHIFT 0x12 +#define CP_MEC_RS64_CNTL__MEC_PIPE3_RESET__SHIFT 0x13 +#define CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE__SHIFT 0x1a +#define CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE__SHIFT 0x1b +#define CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE__SHIFT 0x1c +#define CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE__SHIFT 0x1d +#define CP_MEC_RS64_CNTL__MEC_HALT__SHIFT 0x1e +#define CP_MEC_RS64_CNTL__MEC_STEP__SHIFT 0x1f +#define CP_MEC_RS64_CNTL__SPARE_MASK 0x0000000FL +#define CP_MEC_RS64_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L +#define CP_MEC_RS64_CNTL__MEC_PIPE0_RESET_MASK 0x00010000L +#define CP_MEC_RS64_CNTL__MEC_PIPE1_RESET_MASK 0x00020000L +#define CP_MEC_RS64_CNTL__MEC_PIPE2_RESET_MASK 0x00040000L +#define CP_MEC_RS64_CNTL__MEC_PIPE3_RESET_MASK 0x00080000L +#define CP_MEC_RS64_CNTL__MEC_PIPE0_ACTIVE_MASK 0x04000000L +#define CP_MEC_RS64_CNTL__MEC_PIPE1_ACTIVE_MASK 0x08000000L +#define CP_MEC_RS64_CNTL__MEC_PIPE2_ACTIVE_MASK 0x10000000L +#define CP_MEC_RS64_CNTL__MEC_PIPE3_ACTIVE_MASK 0x20000000L +#define CP_MEC_RS64_CNTL__MEC_HALT_MASK 0x40000000L +#define CP_MEC_RS64_CNTL__MEC_STEP_MASK 0x80000000L +//CP_MEC_MIE_LO +#define CP_MEC_MIE_LO__MEC_INT__SHIFT 0x0 +#define CP_MEC_MIE_LO__MEC_INT_MASK 0xFFFFFFFFL +//CP_MEC_MIE_HI +#define CP_MEC_MIE_HI__MEC_INT__SHIFT 0x0 +#define CP_MEC_MIE_HI__MEC_INT_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT +#define CP_MEC_RS64_INTERRUPT__MEC_INT__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT__MEC_INT_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INSTR_PNTR +#define CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define CP_MEC_RS64_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL +//CP_MEC_MIP_LO +#define CP_MEC_MIP_LO__MIP_LO__SHIFT 0x0 +#define CP_MEC_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL +//CP_MEC_MIP_HI +#define CP_MEC_MIP_HI__MIP_HI__SHIFT 0x0 +#define CP_MEC_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL +//CP_MEC_DC_BASE_CNTL +#define CP_MEC_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_MEC_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_MEC_DC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_MEC_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//CP_MEC_DC_OP_CNTL +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define CP_MEC_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define CP_MEC_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define CP_MEC_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +//CP_MEC_MTIMECMP_LO +#define CP_MEC_MTIMECMP_LO__TIME_LO__SHIFT 0x0 +#define CP_MEC_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL +//CP_MEC_MTIMECMP_HI +#define CP_MEC_MTIMECMP_HI__TIME_HI__SHIFT 0x0 +#define CP_MEC_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP0_LO +#define CP_MEC_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MEC_GP0_LO__DATA__SHIFT 0x1 +#define CP_MEC_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MEC_GP0_LO__DATA_MASK 0xFFFFFFFEL +//CP_MEC_GP0_HI +#define CP_MEC_GP0_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MEC_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MEC_GP1_LO +#define CP_MEC_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MEC_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP1_HI +#define CP_MEC_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MEC_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP2_LO +#define CP_MEC_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MEC_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP2_HI +#define CP_MEC_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MEC_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP3_LO +#define CP_MEC_GP3_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP3_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP3_HI +#define CP_MEC_GP3_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP3_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP4_LO +#define CP_MEC_GP4_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP4_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP4_HI +#define CP_MEC_GP4_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP4_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP5_LO +#define CP_MEC_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_MEC_GP5_LO__DATA__SHIFT 0x1 +#define CP_MEC_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_MEC_GP5_LO__DATA_MASK 0xFFFFFFFEL +//CP_MEC_GP5_HI +#define CP_MEC_GP5_HI__M_RET_ADDR__SHIFT 0x0 +#define CP_MEC_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_MEC_GP6_LO +#define CP_MEC_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_MEC_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP6_HI +#define CP_MEC_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_MEC_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP7_LO +#define CP_MEC_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_MEC_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_MEC_GP7_HI +#define CP_MEC_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_MEC_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_MEC_GP8_LO +#define CP_MEC_GP8_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP8_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP8_HI +#define CP_MEC_GP8_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP8_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP9_LO +#define CP_MEC_GP9_LO__DATA__SHIFT 0x0 +#define CP_MEC_GP9_LO__DATA_MASK 0xFFFFFFFFL +//CP_MEC_GP9_HI +#define CP_MEC_GP9_HI__DATA__SHIFT 0x0 +#define CP_MEC_GP9_HI__DATA_MASK 0xFFFFFFFFL +//CP_MEC_LOCAL_BASE0_LO +#define CP_MEC_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_BASE0_HI +#define CP_MEC_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_BASE0_HI__BASE0_HI_MASK 0x01FFFFFFL +//CP_MEC_LOCAL_MASK0_LO +#define CP_MEC_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_MASK0_HI +#define CP_MEC_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_MASK0_HI__MASK0_HI_MASK 0x01FFFFFFL +//CP_MEC_LOCAL_APERTURE +#define CP_MEC_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MEC_LOCAL_APERTURE__SCOPE__SHIFT 0x6 +#define CP_MEC_LOCAL_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_MEC_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +#define CP_MEC_LOCAL_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_MEC_LOCAL_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_MEC_LOCAL_INSTR_BASE_LO +#define CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_INSTR_BASE_HI +#define CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MEC_LOCAL_INSTR_MASK_LO +#define CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_INSTR_MASK_HI +#define CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x01FFFFFFL +//CP_MEC_LOCAL_INSTR_APERTURE +#define CP_MEC_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MEC_LOCAL_INSTR_APERTURE__SCOPE__SHIFT 0x6 +#define CP_MEC_LOCAL_INSTR_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_MEC_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +#define CP_MEC_LOCAL_INSTR_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_MEC_LOCAL_INSTR_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_MEC_LOCAL_SCRATCH_APERTURE +#define CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define CP_MEC_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//CP_MEC_LOCAL_SCRATCH_BASE_LO +#define CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MEC_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MEC_LOCAL_SCRATCH_BASE_HI +#define CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MEC_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MEC_RS64_PERFCOUNT_CNTL +#define CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 +#define CP_MEC_RS64_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL +//CP_MEC_RS64_PENDING_INTERRUPT +#define CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_MEC_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_MEC_RS64_EXCEPTION_STATUS +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION__SHIFT 0x0 +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR__SHIFT 0x1 +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION__SHIFT 0x2 +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT__SHIFT 0x3 +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR__SHIFT 0x4 +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION_MASK 0x00000001L +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR_MASK 0x00000002L +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION_MASK 0x00000004L +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT_MASK 0x00000008L +#define CP_MEC_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR_MASK 0x07FFFFF0L +//CP_MEC_RS64_PRGRM_CNTR_START_HI +#define CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define CP_MEC_RS64_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_16 +#define CP_MEC_RS64_INTERRUPT_DATA_16__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_16__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_17 +#define CP_MEC_RS64_INTERRUPT_DATA_17__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_17__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_18 +#define CP_MEC_RS64_INTERRUPT_DATA_18__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_18__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_19 +#define CP_MEC_RS64_INTERRUPT_DATA_19__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_19__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_20 +#define CP_MEC_RS64_INTERRUPT_DATA_20__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_20__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_21 +#define CP_MEC_RS64_INTERRUPT_DATA_21__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_21__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_22 +#define CP_MEC_RS64_INTERRUPT_DATA_22__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_22__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_23 +#define CP_MEC_RS64_INTERRUPT_DATA_23__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_23__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_24 +#define CP_MEC_RS64_INTERRUPT_DATA_24__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_24__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_25 +#define CP_MEC_RS64_INTERRUPT_DATA_25__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_25__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_26 +#define CP_MEC_RS64_INTERRUPT_DATA_26__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_26__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_27 +#define CP_MEC_RS64_INTERRUPT_DATA_27__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_27__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_28 +#define CP_MEC_RS64_INTERRUPT_DATA_28__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_28__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_29 +#define CP_MEC_RS64_INTERRUPT_DATA_29__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_29__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_30 +#define CP_MEC_RS64_INTERRUPT_DATA_30__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_30__DATA_MASK 0xFFFFFFFFL +//CP_MEC_RS64_INTERRUPT_DATA_31 +#define CP_MEC_RS64_INTERRUPT_DATA_31__DATA__SHIFT 0x0 +#define CP_MEC_RS64_INTERRUPT_DATA_31__DATA_MASK 0xFFFFFFFFL +//CP_CPC_IC_OP_CNTL +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 +#define CP_CPC_IC_OP_CNTL__RESERVED__SHIFT 0x2 +#define CP_CPC_IC_OP_CNTL__PRIME_START_PC__SHIFT 0x3 +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L +#define CP_CPC_IC_OP_CNTL__RESERVED_MASK 0x00000004L +#define CP_CPC_IC_OP_CNTL__PRIME_START_PC_MASK 0x00000008L +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_GFX_RS64_INTERRUPT0 +#define CP_GFX_RS64_INTERRUPT0__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTERRUPT0__ME_INT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_INTR_EN0 +#define CP_GFX_RS64_INTR_EN0__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTR_EN0__ME_INT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_INTR_EN1 +#define CP_GFX_RS64_INTR_EN1__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTR_EN1__ME_INT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_BASE_CNTL +#define CP_GFX_RS64_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_GFX_RS64_DC_BASE_CNTL__SCOPE__SHIFT 0x1a +#define CP_GFX_RS64_DC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_GFX_RS64_DC_BASE_CNTL__SCOPE_MASK 0x0C000000L +//CP_GFX_RS64_DC_OP_CNTL +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define CP_GFX_RS64_DC_OP_CNTL__DEPRECATED__SHIFT 0x3 +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define CP_GFX_RS64_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define CP_GFX_RS64_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +#define CP_GFX_RS64_DC_OP_CNTL__DEPRECATED_MASK 0x00000008L +//CP_GFX_RS64_LOCAL_BASE0_LO +#define CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_BASE0_HI +#define CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_MASK0_LO +#define CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_MASK0_HI +#define CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_APERTURE +#define CP_GFX_RS64_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_APERTURE__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_LOCAL_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +#define CP_GFX_RS64_LOCAL_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_LOCAL_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_LOCAL_INSTR_BASE_LO +#define CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_INSTR_BASE_HI +#define CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_INSTR_MASK_LO +#define CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_INSTR_MASK_HI +#define CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_LOCAL_INSTR_APERTURE +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_LOCAL_INSTR_APERTURE__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_LOCAL_SCRATCH_APERTURE +#define CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CP_PFP_RS64_EXCEPTION_STATUS +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION__SHIFT 0x0 +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR__SHIFT 0x1 +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION__SHIFT 0x2 +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT__SHIFT 0x3 +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR__SHIFT 0x4 +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION_MASK 0x00000001L +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR_MASK 0x00000002L +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION_MASK 0x00000004L +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT_MASK 0x00000008L +#define CP_PFP_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR_MASK 0x07FFFFF0L +//CP_GFX_RS64_PERFCOUNT_CNTL0 +#define CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL__SHIFT 0x0 +#define CP_GFX_RS64_PERFCOUNT_CNTL0__EVENT_SEL_MASK 0x0000001FL +//CP_GFX_RS64_PERFCOUNT_CNTL1 +#define CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL__SHIFT 0x0 +#define CP_GFX_RS64_PERFCOUNT_CNTL1__EVENT_SEL_MASK 0x0000001FL +//CP_GFX_RS64_MIP_LO0 +#define CP_GFX_RS64_MIP_LO0__MIP_LO__SHIFT 0x0 +#define CP_GFX_RS64_MIP_LO0__MIP_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIP_LO1 +#define CP_GFX_RS64_MIP_LO1__MIP_LO__SHIFT 0x0 +#define CP_GFX_RS64_MIP_LO1__MIP_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIP_HI0 +#define CP_GFX_RS64_MIP_HI0__MIP_HI__SHIFT 0x0 +#define CP_GFX_RS64_MIP_HI0__MIP_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIP_HI1 +#define CP_GFX_RS64_MIP_HI1__MIP_HI__SHIFT 0x0 +#define CP_GFX_RS64_MIP_HI1__MIP_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_LO0 +#define CP_GFX_RS64_MTIMECMP_LO0__TIME_LO__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_LO0__TIME_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_LO1 +#define CP_GFX_RS64_MTIMECMP_LO1__TIME_LO__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_LO1__TIME_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_HI0 +#define CP_GFX_RS64_MTIMECMP_HI0__TIME_HI__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_HI0__TIME_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MTIMECMP_HI1 +#define CP_GFX_RS64_MTIMECMP_HI1__TIME_HI__SHIFT 0x0 +#define CP_GFX_RS64_MTIMECMP_HI1__TIME_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP0_LO0 +#define CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP0_LO0__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP0_LO0__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP0_LO0__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP0_LO1 +#define CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP0_LO1__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP0_LO1__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP0_LO1__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP0_HI0 +#define CP_GFX_RS64_GP0_HI0__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP0_HI0__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP0_HI1 +#define CP_GFX_RS64_GP0_HI1__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP0_HI1__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_LO0 +#define CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP1_LO0__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_LO1 +#define CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP1_LO1__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_HI0 +#define CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP1_HI0__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP1_HI1 +#define CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP1_HI1__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_LO0 +#define CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP2_LO0__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_LO1 +#define CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP2_LO1__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_HI0 +#define CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP2_HI0__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP2_HI1 +#define CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP2_HI1__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_LO0 +#define CP_GFX_RS64_GP3_LO0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_LO0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_LO1 +#define CP_GFX_RS64_GP3_LO1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_LO1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_HI0 +#define CP_GFX_RS64_GP3_HI0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_HI0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP3_HI1 +#define CP_GFX_RS64_GP3_HI1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP3_HI1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_LO0 +#define CP_GFX_RS64_GP4_LO0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_LO0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_LO1 +#define CP_GFX_RS64_GP4_LO1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_LO1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_HI0 +#define CP_GFX_RS64_GP4_HI0__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_HI0__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP4_HI1 +#define CP_GFX_RS64_GP4_HI1__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP4_HI1__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP5_LO0 +#define CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP5_LO0__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP5_LO0__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP5_LO0__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP5_LO1 +#define CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED__SHIFT 0x0 +#define CP_GFX_RS64_GP5_LO1__DATA__SHIFT 0x1 +#define CP_GFX_RS64_GP5_LO1__PG_VIRT_HALTED_MASK 0x00000001L +#define CP_GFX_RS64_GP5_LO1__DATA_MASK 0xFFFFFFFEL +//CP_GFX_RS64_GP5_HI0 +#define CP_GFX_RS64_GP5_HI0__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP5_HI0__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP5_HI1 +#define CP_GFX_RS64_GP5_HI1__M_RET_ADDR__SHIFT 0x0 +#define CP_GFX_RS64_GP5_HI1__M_RET_ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP6_LO +#define CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP6_HI +#define CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP7_LO +#define CP_GFX_RS64_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define CP_GFX_RS64_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP7_HI +#define CP_GFX_RS64_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define CP_GFX_RS64_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP8_LO +#define CP_GFX_RS64_GP8_LO__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP8_LO__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP8_HI +#define CP_GFX_RS64_GP8_HI__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP8_HI__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP9_LO +#define CP_GFX_RS64_GP9_LO__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP9_LO__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_GP9_HI +#define CP_GFX_RS64_GP9_HI__DATA__SHIFT 0x0 +#define CP_GFX_RS64_GP9_HI__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_INSTR_PNTR0 +#define CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR__SHIFT 0x0 +#define CP_GFX_RS64_INSTR_PNTR0__INSTR_PNTR_MASK 0x000FFFFFL +//CP_GFX_RS64_INSTR_PNTR1 +#define CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR__SHIFT 0x0 +#define CP_GFX_RS64_INSTR_PNTR1__INSTR_PNTR_MASK 0x000FFFFFL +//CP_GFX_RS64_PENDING_INTERRUPT0 +#define CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_GFX_RS64_PENDING_INTERRUPT0__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_PENDING_INTERRUPT1 +#define CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT__SHIFT 0x0 +#define CP_GFX_RS64_PENDING_INTERRUPT1__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_BASE0 +#define CP_GFX_RS64_DC_APERTURE0_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_MASK0 +#define CP_GFX_RS64_DC_APERTURE0_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_CNTL0 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE0_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE1_BASE0 +#define CP_GFX_RS64_DC_APERTURE1_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_MASK0 +#define CP_GFX_RS64_DC_APERTURE1_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_CNTL0 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE1_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE2_BASE0 +#define CP_GFX_RS64_DC_APERTURE2_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_MASK0 +#define CP_GFX_RS64_DC_APERTURE2_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_CNTL0 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE2_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE3_BASE0 +#define CP_GFX_RS64_DC_APERTURE3_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_MASK0 +#define CP_GFX_RS64_DC_APERTURE3_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_CNTL0 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE3_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE4_BASE0 +#define CP_GFX_RS64_DC_APERTURE4_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_MASK0 +#define CP_GFX_RS64_DC_APERTURE4_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_CNTL0 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE4_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE5_BASE0 +#define CP_GFX_RS64_DC_APERTURE5_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_MASK0 +#define CP_GFX_RS64_DC_APERTURE5_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_CNTL0 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE5_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE6_BASE0 +#define CP_GFX_RS64_DC_APERTURE6_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_MASK0 +#define CP_GFX_RS64_DC_APERTURE6_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_CNTL0 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE6_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE7_BASE0 +#define CP_GFX_RS64_DC_APERTURE7_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_MASK0 +#define CP_GFX_RS64_DC_APERTURE7_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_CNTL0 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE7_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE8_BASE0 +#define CP_GFX_RS64_DC_APERTURE8_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_MASK0 +#define CP_GFX_RS64_DC_APERTURE8_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_CNTL0 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE8_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE9_BASE0 +#define CP_GFX_RS64_DC_APERTURE9_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_MASK0 +#define CP_GFX_RS64_DC_APERTURE9_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_CNTL0 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE9_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE10_BASE0 +#define CP_GFX_RS64_DC_APERTURE10_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_MASK0 +#define CP_GFX_RS64_DC_APERTURE10_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_CNTL0 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE10_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE11_BASE0 +#define CP_GFX_RS64_DC_APERTURE11_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_MASK0 +#define CP_GFX_RS64_DC_APERTURE11_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_CNTL0 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE11_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE12_BASE0 +#define CP_GFX_RS64_DC_APERTURE12_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_MASK0 +#define CP_GFX_RS64_DC_APERTURE12_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_CNTL0 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE12_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE13_BASE0 +#define CP_GFX_RS64_DC_APERTURE13_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_MASK0 +#define CP_GFX_RS64_DC_APERTURE13_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_CNTL0 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE13_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE14_BASE0 +#define CP_GFX_RS64_DC_APERTURE14_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_MASK0 +#define CP_GFX_RS64_DC_APERTURE14_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_CNTL0 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE14_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE15_BASE0 +#define CP_GFX_RS64_DC_APERTURE15_BASE0__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_BASE0__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_MASK0 +#define CP_GFX_RS64_DC_APERTURE15_MASK0__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_MASK0__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_CNTL0 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE15_CNTL0__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE0_BASE1 +#define CP_GFX_RS64_DC_APERTURE0_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_MASK1 +#define CP_GFX_RS64_DC_APERTURE0_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE0_CNTL1 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE0_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE1_BASE1 +#define CP_GFX_RS64_DC_APERTURE1_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_MASK1 +#define CP_GFX_RS64_DC_APERTURE1_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE1_CNTL1 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE1_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE2_BASE1 +#define CP_GFX_RS64_DC_APERTURE2_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_MASK1 +#define CP_GFX_RS64_DC_APERTURE2_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE2_CNTL1 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE2_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE3_BASE1 +#define CP_GFX_RS64_DC_APERTURE3_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_MASK1 +#define CP_GFX_RS64_DC_APERTURE3_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE3_CNTL1 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE3_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE4_BASE1 +#define CP_GFX_RS64_DC_APERTURE4_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_MASK1 +#define CP_GFX_RS64_DC_APERTURE4_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE4_CNTL1 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE4_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE5_BASE1 +#define CP_GFX_RS64_DC_APERTURE5_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_MASK1 +#define CP_GFX_RS64_DC_APERTURE5_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE5_CNTL1 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE5_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE6_BASE1 +#define CP_GFX_RS64_DC_APERTURE6_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_MASK1 +#define CP_GFX_RS64_DC_APERTURE6_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE6_CNTL1 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE6_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE7_BASE1 +#define CP_GFX_RS64_DC_APERTURE7_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_MASK1 +#define CP_GFX_RS64_DC_APERTURE7_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE7_CNTL1 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE7_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE8_BASE1 +#define CP_GFX_RS64_DC_APERTURE8_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_MASK1 +#define CP_GFX_RS64_DC_APERTURE8_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE8_CNTL1 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE8_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE9_BASE1 +#define CP_GFX_RS64_DC_APERTURE9_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_MASK1 +#define CP_GFX_RS64_DC_APERTURE9_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE9_CNTL1 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE9_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE10_BASE1 +#define CP_GFX_RS64_DC_APERTURE10_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_MASK1 +#define CP_GFX_RS64_DC_APERTURE10_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE10_CNTL1 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE10_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE11_BASE1 +#define CP_GFX_RS64_DC_APERTURE11_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_MASK1 +#define CP_GFX_RS64_DC_APERTURE11_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE11_CNTL1 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE11_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE12_BASE1 +#define CP_GFX_RS64_DC_APERTURE12_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_MASK1 +#define CP_GFX_RS64_DC_APERTURE12_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE12_CNTL1 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE12_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE13_BASE1 +#define CP_GFX_RS64_DC_APERTURE13_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_MASK1 +#define CP_GFX_RS64_DC_APERTURE13_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE13_CNTL1 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE13_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE14_BASE1 +#define CP_GFX_RS64_DC_APERTURE14_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_MASK1 +#define CP_GFX_RS64_DC_APERTURE14_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE14_CNTL1 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE14_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_GFX_RS64_DC_APERTURE15_BASE1 +#define CP_GFX_RS64_DC_APERTURE15_BASE1__BASE__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_BASE1__BASE_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_MASK1 +#define CP_GFX_RS64_DC_APERTURE15_MASK1__MASK__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_MASK1__MASK_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DC_APERTURE15_CNTL1 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID__SHIFT 0x0 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE__SHIFT 0x4 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__ENABLE__SHIFT 0x5 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__SCOPE__SHIFT 0x6 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__TEMPORAL__SHIFT 0x8 +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__VMID_MASK 0x0000000FL +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__BYPASS_MODE_MASK 0x00000010L +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__ENABLE_MASK 0x00000020L +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__SCOPE_MASK 0x000000C0L +#define CP_GFX_RS64_DC_APERTURE15_CNTL1__TEMPORAL_MASK 0x00000700L +//CP_ME_RS64_EXCEPTION_STATUS +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION__SHIFT 0x0 +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR__SHIFT 0x1 +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION__SHIFT 0x2 +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT__SHIFT 0x3 +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR__SHIFT 0x4 +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION_MASK 0x00000001L +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR_MASK 0x00000002L +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION_MASK 0x00000004L +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT_MASK 0x00000008L +#define CP_ME_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR_MASK 0x07FFFFF0L +//CP_GFX_RS64_INTERRUPT1 +#define CP_GFX_RS64_INTERRUPT1__ME_INT__SHIFT 0x0 +#define CP_GFX_RS64_INTERRUPT1__ME_INT_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_chdec +//CH_ARB_CTRL +#define CH_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 +#define CH_ARB_CTRL__FGCG_DISABLE__SHIFT 0x2 +#define CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x3 +#define CH_ARB_CTRL__CHICKEN_BITS__SHIFT 0x4 +#define CH_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000001L +#define CH_ARB_CTRL__FGCG_DISABLE_MASK 0x00000004L +#define CH_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000008L +#define CH_ARB_CTRL__CHICKEN_BITS_MASK 0x00000FF0L +//CH_DRAM_BURST_MASK +#define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 +#define CH_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL +//CH_ARB_STATUS +#define CH_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 +#define CH_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 +#define CH_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L +#define CH_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L +//CH_DRAM_BURST_CTRL +#define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 +#define CH_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 +#define CH_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L +#define CH_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L +//CHA_CHC_CREDITS +#define CHA_CHC_CREDITS__CHC_REQ_CREDITS__SHIFT 0x0 +#define CHA_CHC_CREDITS__CHC_DATA_CREDITS__SHIFT 0x8 +#define CHA_CHC_CREDITS__CHC_REQ_CREDITS_MASK 0x000000FFL +#define CHA_CHC_CREDITS__CHC_DATA_CREDITS_MASK 0x0000FF00L +//CHA_CLIENT_FREE_DELAY +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT 0x0 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT 0x3 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT 0x6 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT 0x9 +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT 0xc +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK 0x00000007L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK 0x00000038L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK 0x000001C0L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK 0x00000E00L +#define CHA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK 0x00007000L +//CHI_CHR_REP_FGCG_OVERRIDE +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE__SHIFT 0x0 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE__SHIFT 0x1 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIW_REP_FGCG_OVERRIDE_MASK 0x00000001L +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHIR_REP_FGCG_OVERRIDE_MASK 0x00000002L +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L +#define CHI_CHR_REP_FGCG_OVERRIDE__CHA_CHR_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L +//CHC_CTRL +#define CHC_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 +#define CHC_CTRL__GL2_REQ_CREDITS__SHIFT 0x4 +#define CHC_CTRL__GL2_DATA_CREDITS__SHIFT 0xb +#define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x12 +#define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x13 +#define CHC_CTRL__DISABLE_CMPSWAP_DATA_REPLICATE__SHIFT 0x14 +#define CHC_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL +#define CHC_CTRL__GL2_REQ_CREDITS_MASK 0x000007F0L +#define CHC_CTRL__GL2_DATA_CREDITS_MASK 0x0003F800L +#define CHC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00040000L +#define CHC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00080000L +#define CHC_CTRL__DISABLE_CMPSWAP_DATA_REPLICATE_MASK 0x00100000L +//CHC_STATUS +#define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 +#define CHC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 +#define CHC_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 +#define CHC_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 +#define CHC_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 +#define CHC_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 +#define CHC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 +#define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 +#define CHC_STATUS__GL2_RH_BUSY__SHIFT 0x9 +#define CHC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa +#define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x15 +#define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x16 +#define CHC_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x17 +#define CHC_STATUS__BUFFER_FULL__SHIFT 0x18 +#define CHC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L +#define CHC_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L +#define CHC_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L +#define CHC_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L +#define CHC_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L +#define CHC_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L +#define CHC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L +#define CHC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L +#define CHC_STATUS__GL2_RH_BUSY_MASK 0x00000200L +#define CHC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x001FFC00L +#define CHC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00200000L +#define CHC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00400000L +#define CHC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00800000L +#define CHC_STATUS__BUFFER_FULL_MASK 0x01000000L +//CHC_STATUS2 +#define CHC_STATUS2__DCC_OUT_ERROR_CODE__SHIFT 0x0 +#define CHC_STATUS2__DCC_OUT_ERROR_CODE_MASK 0x00000FFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_glarbdec +//GLARB_ARB_CTRL +#define GLARB_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 +#define GLARB_ARB_CTRL__FGCG_DISABLE__SHIFT 0x4 +#define GLARB_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x5 +#define GLARB_ARB_CTRL__GCRD_TARGET_DISABLE__SHIFT 0x6 +#define GLARB_ARB_CTRL__NPS_MODE__SHIFT 0x12 +#define GLARB_ARB_CTRL__CHICKEN_BITS__SHIFT 0x14 +#define GLARB_ARB_CTRL__NUM_MEM_PIPES_MASK 0x0000000FL +#define GLARB_ARB_CTRL__FGCG_DISABLE_MASK 0x00000010L +#define GLARB_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000020L +#define GLARB_ARB_CTRL__GCRD_TARGET_DISABLE_MASK 0x0003FFC0L +#define GLARB_ARB_CTRL__NPS_MODE_MASK 0x000C0000L +#define GLARB_ARB_CTRL__CHICKEN_BITS_MASK 0x01F00000L +//GLARB_DRAM_BURST_MASK +#define GLARB_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 +#define GLARB_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL +//GLARB_ARB_STATUS +#define GLARB_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 +#define GLARB_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 +#define GLARB_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L +#define GLARB_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L +//GLARB_DRAM_BURST_CTRL +#define GLARB_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 +#define GLARB_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 +#define GLARB_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE__SHIFT 0x4 +#define GLARB_DRAM_BURST_CTRL__GATHER_64B_BURST_DISABLE__SHIFT 0x5 +#define GLARB_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE__SHIFT 0x6 +#define GLARB_DRAM_BURST_CTRL__GATHER_32B_BURST_DISABLE__SHIFT 0x7 +#define GLARB_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE__SHIFT 0x8 +#define GLARB_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L +#define GLARB_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L +#define GLARB_DRAM_BURST_CTRL__GATHER_64B_MEMORY_BURST_DISABLE_MASK 0x00000010L +#define GLARB_DRAM_BURST_CTRL__GATHER_64B_BURST_DISABLE_MASK 0x00000020L +#define GLARB_DRAM_BURST_CTRL__GATHER_32B_MEMORY_BURST_DISABLE_MASK 0x00000040L +#define GLARB_DRAM_BURST_CTRL__GATHER_32B_BURST_DISABLE_MASK 0x00000080L +#define GLARB_DRAM_BURST_CTRL__WRITE_BURSTABLE_STALL_DISABLE_MASK 0x00000100L +//GLARBA_GLARBC_CREDITS +#define GLARBA_GLARBC_CREDITS__GLARBC_REQ_CREDITS__SHIFT 0x0 +#define GLARBA_GLARBC_CREDITS__GLARBC_DATA_CREDITS__SHIFT 0x8 +#define GLARBA_GLARBC_CREDITS__GLARBCG_REQ_CREDITS__SHIFT 0x10 +#define GLARBA_GLARBC_CREDITS__GLARBC_REQ_CREDITS_MASK 0x000000FFL +#define GLARBA_GLARBC_CREDITS__GLARBC_DATA_CREDITS_MASK 0x0000FF00L +#define GLARBA_GLARBC_CREDITS__GLARBCG_REQ_CREDITS_MASK 0x00FF0000L +//GLARBA_CLIENT_FREE_DELAY +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT 0x0 +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT 0x3 +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT 0x6 +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT 0x9 +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT 0xc +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK 0x00000007L +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK 0x00000038L +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK 0x000001C0L +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK 0x00000E00L +#define GLARBA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK 0x00007000L +//GLARBI_GLARBR_REP_FGCG_OVERRIDE +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBIW_REP_FGCG_OVERRIDE__SHIFT 0x0 +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBIR_REP_FGCG_OVERRIDE__SHIFT 0x1 +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBR_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBR_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBIW_REP_FGCG_OVERRIDE_MASK 0x00000001L +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBIR_REP_FGCG_OVERRIDE_MASK 0x00000002L +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBR_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L +#define GLARBI_GLARBR_REP_FGCG_OVERRIDE__GLARBA_GLARBR_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L +//GLARBC_CTRL +#define GLARBC_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 +#define GLARBC_CTRL__GL2_REQ_CREDITS__SHIFT 0x4 +#define GLARBC_CTRL__GL2_DATA_CREDITS__SHIFT 0xb +#define GLARBC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x12 +#define GLARBC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x13 +#define GLARBC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT__SHIFT 0x14 +#define GLARBC_CTRL__OC_EA_REQ_D_CREDIT__SHIFT 0x15 +#define GLARBC_CTRL__OC_EA_REQ_I_CREDIT__SHIFT 0x1a +#define GLARBC_CTRL__CREST_MODE_ENABLE__SHIFT 0x1f +#define GLARBC_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL +#define GLARBC_CTRL__GL2_REQ_CREDITS_MASK 0x000007F0L +#define GLARBC_CTRL__GL2_DATA_CREDITS_MASK 0x0003F800L +#define GLARBC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00040000L +#define GLARBC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00080000L +#define GLARBC_CTRL__DISABLE_PERF_WR_DATA_ALLOC_COUNT_MASK 0x00100000L +#define GLARBC_CTRL__OC_EA_REQ_D_CREDIT_MASK 0x03E00000L +#define GLARBC_CTRL__OC_EA_REQ_I_CREDIT_MASK 0x7C000000L +#define GLARBC_CTRL__CREST_MODE_ENABLE_MASK 0x80000000L +//GLARBC_STATUS +#define GLARBC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 +#define GLARBC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 +#define GLARBC_STATUS__SRC_DATA_FIFO_VC0_FULL__SHIFT 0x2 +#define GLARBC_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 +#define GLARBC_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 +#define GLARBC_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 +#define GLARBC_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 +#define GLARBC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 +#define GLARBC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 +#define GLARBC_STATUS__GL2_RH_BUSY__SHIFT 0x9 +#define GLARBC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa +#define GLARBC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 +#define GLARBC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 +#define GLARBC_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 +#define GLARBC_STATUS__BUFFER_FULL__SHIFT 0x17 +#define GLARBC_STATUS__DCC_OUT_ERROR_CODE__SHIFT 0x18 +#define GLARBC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L +#define GLARBC_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L +#define GLARBC_STATUS__SRC_DATA_FIFO_VC0_FULL_MASK 0x00000004L +#define GLARBC_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L +#define GLARBC_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L +#define GLARBC_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L +#define GLARBC_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L +#define GLARBC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L +#define GLARBC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L +#define GLARBC_STATUS__GL2_RH_BUSY_MASK 0x00000200L +#define GLARBC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L +#define GLARBC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L +#define GLARBC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L +#define GLARBC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L +#define GLARBC_STATUS__BUFFER_FULL_MASK 0x00800000L +#define GLARBC_STATUS__DCC_OUT_ERROR_CODE_MASK 0x1F000000L +//GLARBC_CTRL2 +#define GLARBC_CTRL2__DCC_COMP_TO_CONSTANT_EN__SHIFT 0x0 +#define GLARBC_CTRL2__DCC_COMP_TO_SINGLE_EN__SHIFT 0x1 +#define GLARBC_CTRL2__DCC_COMP_ERROR_DETECTION_EN__SHIFT 0x2 +#define GLARBC_CTRL2__DCC_CLEAR_ERROR_CODE__SHIFT 0x6 +#define GLARBC_CTRL2__DCC_COMP_TRANSFER_SIZE_ENABLE__SHIFT 0x7 +#define GLARBC_CTRL2__DCC_COMP_SKIP_LOW_COMP_RATIOS__SHIFT 0xa +#define GLARBC_CTRL2__DCC_COMP_TO_CONSTANT_EN_MASK 0x00000001L +#define GLARBC_CTRL2__DCC_COMP_TO_SINGLE_EN_MASK 0x00000002L +#define GLARBC_CTRL2__DCC_COMP_ERROR_DETECTION_EN_MASK 0x0000003CL +#define GLARBC_CTRL2__DCC_CLEAR_ERROR_CODE_MASK 0x00000040L +#define GLARBC_CTRL2__DCC_COMP_TRANSFER_SIZE_ENABLE_MASK 0x00000380L +#define GLARBC_CTRL2__DCC_COMP_SKIP_LOW_COMP_RATIOS_MASK 0x00000400L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfddec +//CPG_PERFCOUNTER1_LO +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER1_HI +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_LO +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPG_PERFCOUNTER0_HI +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_LO +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER1_HI +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_LO +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPC_PERFCOUNTER0_HI +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_LO +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER1_HI +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_LO +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CPF_PERFCOUNTER0_HI +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CPF_LATENCY_STATS_DATA +#define CPF_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPF_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_LATENCY_STATS_DATA +#define CPG_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPG_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//CPC_LATENCY_STATS_DATA +#define CPC_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define CPC_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_LO +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER0_HI +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_LO +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBM_PERFCOUNTER1_HI +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER0_LO +#define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER0_HI +#define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER1_LO +#define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER1_HI +#define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER2_LO +#define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER2_HI +#define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER3_LO +#define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE1_PERFCOUNTER3_HI +#define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER0_LO +#define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER0_HI +#define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER1_LO +#define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER1_HI +#define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER2_LO +#define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER2_HI +#define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER3_LO +#define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_DIST_PERFCOUNTER3_HI +#define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GC_EA_CPWD_PERFCOUNTER0_LO +#define GC_EA_CPWD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GC_EA_CPWD_PERFCOUNTER0_HI +#define GC_EA_CPWD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GC_EA_CPWD_PERFCOUNTER1_LO +#define GC_EA_CPWD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GC_EA_CPWD_PERFCOUNTER1_HI +#define GC_EA_CPWD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER0_LO +#define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER0_HI +#define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER1_LO +#define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER1_HI +#define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER2_LO +#define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER2_HI +#define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER3_LO +#define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHC_PERFCOUNTER3_HI +#define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER0_LO +#define GLARBA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER0_HI +#define GLARBA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER1_LO +#define GLARBA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER1_HI +#define GLARBA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER2_LO +#define GLARBA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER2_HI +#define GLARBA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER3_LO +#define GLARBA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBA_PERFCOUNTER3_HI +#define GLARBA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER0_LO +#define GLARBC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER0_HI +#define GLARBC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER1_LO +#define GLARBC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER1_HI +#define GLARBC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER2_LO +#define GLARBC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER2_HI +#define GLARBC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER3_LO +#define GLARBC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GLARBC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GLARBC_PERFCOUNTER3_HI +#define GLARBC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GLARBC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_LO +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER0_HI +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_LO +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RLC_PERFCOUNTER1_HI +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER0_LO +#define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GCR_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER0_HI +#define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GCR_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER1_LO +#define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GCR_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER1_HI +#define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GCR_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER0_LO +#define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER0_HI +#define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER1_LO +#define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER1_HI +#define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER2_LO +#define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER2_HI +#define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER3_LO +#define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CHA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CHA_PERFCOUNTER3_HI +#define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfsdec +//CPG_PERFCOUNTER1_SELECT +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPG_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT1 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPG_PERFCOUNTER0_SELECT +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CPG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPC_PERFCOUNTER1_SELECT +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L +//CPC_PERFCOUNTER0_SELECT1 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER1_SELECT +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPF_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT1 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//CPF_PERFCOUNTER0_SELECT +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CPF_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CP_PERFMON_CNTL +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//CPC_PERFCOUNTER0_SELECT +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CPC_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//CPF_TC_PERF_COUNTER_WINDOW_SELECT +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x00000007L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPF_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPG_TC_PERF_COUNTER_WINDOW_SELECT +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPG_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CPF_LATENCY_STATS_SELECT +#define CPF_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPF_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPF_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPF_LATENCY_STATS_SELECT__INDEX_MASK 0x0000000FL +#define CPF_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPF_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPG_LATENCY_STATS_SELECT +#define CPG_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPG_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPG_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPG_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL +#define CPG_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPG_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPC_LATENCY_STATS_SELECT +#define CPC_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define CPC_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define CPC_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define CPC_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL +#define CPC_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define CPC_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//CPC_TC_PERF_COUNTER_WINDOW_SELECT +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define CPC_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//CP_DRAW_OBJECT +#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 +#define CP_DRAW_OBJECT__OBJECT_MASK 0xFFFFFFFFL +//CP_DRAW_OBJECT_COUNTER +#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 +#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0x0000FFFFL +//CP_DRAW_WINDOW_MASK_HI +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_HI +#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xFFFFFFFFL +//CP_DRAW_WINDOW_LO +#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 +#define CP_DRAW_WINDOW_LO__MIN_MASK 0x0000FFFFL +#define CP_DRAW_WINDOW_LO__MAX_MASK 0xFFFF0000L +//CP_DRAW_WINDOW_CNTL +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 +#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x00000001L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x00000002L +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x00000004L +#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x00000100L +//GRBM_PERFCOUNTER0_SELECT +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER0_SELECT__CANE_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER0_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER0_SELECT__CANE_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//GRBM_PERFCOUNTER1_SELECT +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBM_PERFCOUNTER1_SELECT__CANE_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x00400000L +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBM_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBM_PERFCOUNTER1_SELECT__UTCL2_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBM_PERFCOUNTER1_SELECT__CANE_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//GRBM_PERFCOUNTER0_SELECT_HI +#define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 +#define GRBM_PERFCOUNTER0_SELECT_HI__GLARB_BUSY_USER_DEFINED_MASK__SHIFT 0x2 +#define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 +#define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 +#define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBM_PERFCOUNTER0_SELECT_HI__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER0_SELECT_HI__CANE_STAT_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER0_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L +#define GRBM_PERFCOUNTER0_SELECT_HI__GLARB_BUSY_USER_DEFINED_MASK_MASK 0x00000004L +#define GRBM_PERFCOUNTER0_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L +#define GRBM_PERFCOUNTER0_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L +#define GRBM_PERFCOUNTER0_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBM_PERFCOUNTER0_SELECT_HI__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBM_PERFCOUNTER0_SELECT_HI__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER0_SELECT_HI__CANE_STAT_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +//GRBM_PERFCOUNTER1_SELECT_HI +#define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1 +#define GRBM_PERFCOUNTER1_SELECT_HI__GLARB_BUSY_USER_DEFINED_MASK__SHIFT 0x2 +#define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK__SHIFT 0x3 +#define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK__SHIFT 0x4 +#define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBM_PERFCOUNTER1_SELECT_HI__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER1_SELECT_HI__CANE_STAT_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER1_SELECT_HI__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x00000002L +#define GRBM_PERFCOUNTER1_SELECT_HI__GLARB_BUSY_USER_DEFINED_MASK_MASK 0x00000004L +#define GRBM_PERFCOUNTER1_SELECT_HI__SDMA_BUSY_USER_DEFINED_MASK_MASK 0x00000008L +#define GRBM_PERFCOUNTER1_SELECT_HI__CH_BUSY_USER_DEFINED_MASK_MASK 0x00000010L +#define GRBM_PERFCOUNTER1_SELECT_HI__PMM_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBM_PERFCOUNTER1_SELECT_HI__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBM_PERFCOUNTER1_SELECT_HI__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBM_PERFCOUNTER1_SELECT_HI__CANE_STAT_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +//GE1_PERFCOUNTER0_SELECT +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER0_SELECT1 +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE1_PERFCOUNTER1_SELECT +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER1_SELECT1 +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE1_PERFCOUNTER2_SELECT +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER2_SELECT1 +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE1_PERFCOUNTER3_SELECT +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GE1_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE1_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE1_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE1_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE1_PERFCOUNTER3_SELECT1 +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE1_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE1_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER0_SELECT +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER0_SELECT1 +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER1_SELECT +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER1_SELECT1 +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER2_SELECT +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER2_SELECT1 +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER3_SELECT +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_DIST_PERFCOUNTER3_SELECT1 +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_DIST_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GC_EA_CPWD_PERFCOUNTER0_SELECT +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GC_EA_CPWD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GC_EA_CPWD_PERFCOUNTER0_SELECT1 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GC_EA_CPWD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GC_EA_CPWD_PERFCOUNTER1_SELECT +#define GC_EA_CPWD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GC_EA_CPWD_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c +#define GC_EA_CPWD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GC_EA_CPWD_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER0_SELECT +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CHC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER0_SELECT1 +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHC_PERFCOUNTER1_SELECT +#define CHC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define CHC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER1_SELECT1 +#define CHC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHC_PERFCOUNTER2_SELECT +#define CHC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define CHC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER2_SELECT1 +#define CHC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHC_PERFCOUNTER3_SELECT +#define CHC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CHC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define CHC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CHC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//CHC_PERFCOUNTER3_SELECT1 +#define CHC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBA_PERFCOUNTER0_SELECT +#define GLARBA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBA_PERFCOUNTER0_SELECT1 +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBA_PERFCOUNTER1_SELECT +#define GLARBA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBA_PERFCOUNTER1_SELECT1 +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBA_PERFCOUNTER2_SELECT +#define GLARBA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBA_PERFCOUNTER2_SELECT1 +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBA_PERFCOUNTER3_SELECT +#define GLARBA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBA_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBA_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBA_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBA_PERFCOUNTER3_SELECT1 +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBA_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBC_PERFCOUNTER0_SELECT +#define GLARBC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBC_PERFCOUNTER0_SELECT1 +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBC_PERFCOUNTER1_SELECT +#define GLARBC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBC_PERFCOUNTER1_SELECT1 +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBC_PERFCOUNTER2_SELECT +#define GLARBC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBC_PERFCOUNTER2_SELECT1 +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GLARBC_PERFCOUNTER3_SELECT +#define GLARBC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GLARBC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GLARBC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GLARBC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GLARBC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GLARBC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GLARBC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GLARBC_PERFCOUNTER3_SELECT1 +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GLARBC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RLC_SPM_PERFMON_CNTL +#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0x0 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_START_MODE__SHIFT 0xe +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_TYPE__SHIFT 0xf +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0x00000FFFL +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x00003000L +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_START_MODE_MASK 0x00004000L +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_TYPE_MASK 0x00008000L +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xFFFF0000L +//RLC_SPM_PERFMON_RING_BASE_LO +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xFFFFFFFFL +//RLC_SPM_PERFMON_RING_BASE_HI +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x19 +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0x01FFFFFFL +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xFE000000L +//RLC_SPM_PERFMON_RING_SIZE +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xFFFFFFFFL +//RLC_SPM_RING_WRPTR +#define RLC_SPM_RING_WRPTR__RESERVED__SHIFT 0x0 +#define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR__SHIFT 0x5 +#define RLC_SPM_RING_WRPTR__RESERVED_MASK 0x0000001FL +#define RLC_SPM_RING_WRPTR__PERFMON_RING_WRPTR_MASK 0xFFFFFFE0L +//RLC_SPM_RING_RDPTR +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xFFFFFFFFL +//RLC_SPM_SEGMENT_THRESHOLD +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 +#define RLC_SPM_SEGMENT_THRESHOLD__RESERVED__SHIFT 0x8 +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0x000000FFL +#define RLC_SPM_SEGMENT_THRESHOLD__RESERVED_MASK 0xFFFFFF00L +//RLC_SPM_PERFMON_SEGMENT_SIZE +#define RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT__SHIFT 0x10 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT__SHIFT 0x18 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__TOTAL_NUM_SEGMENT_MASK 0x0000FFFFL +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_SEGMENT_MASK 0x00FF0000L +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE_NUM_SEGMENT_MASK 0xFF000000L +//RLC_SPM_GLOBAL_MUXSEL_ADDR +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__ADDR_MASK 0x000003FFL +//RLC_SPM_GLOBAL_MUXSEL_DATA +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1__SHIFT 0x10 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL0_MASK 0x0000FFFFL +#define RLC_SPM_GLOBAL_MUXSEL_DATA__SEL1_MASK 0xFFFF0000L +//RLC_SPM_SE_MUXSEL_ADDR +#define RLC_SPM_SE_MUXSEL_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_ADDR__ADDR_MASK 0x000003FFL +//RLC_SPM_SE_MUXSEL_DATA +#define RLC_SPM_SE_MUXSEL_DATA__SEL0__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_DATA__SEL1__SHIFT 0x10 +#define RLC_SPM_SE_MUXSEL_DATA__SEL0_MASK 0x0000FFFFL +#define RLC_SPM_SE_MUXSEL_DATA__SEL1_MASK 0xFFFF0000L +//RLC_SPM_SE_USER_DATA_0 +#define RLC_SPM_SE_USER_DATA_0__LO__SHIFT 0x0 +#define RLC_SPM_SE_USER_DATA_0__HI__SHIFT 0x10 +#define RLC_SPM_SE_USER_DATA_0__LO_MASK 0x0000FFFFL +#define RLC_SPM_SE_USER_DATA_0__HI_MASK 0xFFFF0000L +//RLC_SPM_SE_USER_DATA_1 +#define RLC_SPM_SE_USER_DATA_1__LO__SHIFT 0x0 +#define RLC_SPM_SE_USER_DATA_1__HI__SHIFT 0x10 +#define RLC_SPM_SE_USER_DATA_1__LO_MASK 0x0000FFFFL +#define RLC_SPM_SE_USER_DATA_1__HI_MASK 0xFFFF0000L +//RLC_SPM_SE_USER_DATA_2 +#define RLC_SPM_SE_USER_DATA_2__LO__SHIFT 0x0 +#define RLC_SPM_SE_USER_DATA_2__HI__SHIFT 0x10 +#define RLC_SPM_SE_USER_DATA_2__LO_MASK 0x0000FFFFL +#define RLC_SPM_SE_USER_DATA_2__HI_MASK 0xFFFF0000L +//RLC_SPM_SE_USER_DATA_3 +#define RLC_SPM_SE_USER_DATA_3__LO__SHIFT 0x0 +#define RLC_SPM_SE_USER_DATA_3__HI__SHIFT 0x10 +#define RLC_SPM_SE_USER_DATA_3__LO_MASK 0x0000FFFFL +#define RLC_SPM_SE_USER_DATA_3__HI_MASK 0xFFFF0000L +//RLC_SPM_ACCUM_DATARAM_ADDR +#define RLC_SPM_ACCUM_DATARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_ADDR__ADDR_MASK 0x0000007FL +//RLC_SPM_ACCUM_DATARAM_DATA +#define RLC_SPM_ACCUM_DATARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_ACCUM_SWA_DATARAM_ADDR +#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_ACCUM_SWA_DATARAM_ADDR__ADDR_MASK 0x0000007FL +//RLC_SPM_ACCUM_SWA_DATARAM_DATA +#define RLC_SPM_ACCUM_SWA_DATARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_ACCUM_SWA_DATARAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_ACCUM_CTRLRAM_ADDR +#define RLC_SPM_ACCUM_CTRLRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR__ADDR_MASK 0x000007FFL +//RLC_SPM_ACCUM_CTRLRAM_DATA +#define RLC_SPM_ACCUM_CTRLRAM_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRLRAM_DATA__DATA_MASK 0x000000FFL +//RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset__SHIFT 0x8 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset__SHIFT 0x10 +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__global_offset_MASK 0x000000FFL +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_se_offset_MASK 0x0000FF00L +#define RLC_SPM_ACCUM_CTRLRAM_ADDR_OFFSET__spmwithaccum_global_offset_MASK 0x00FF0000L +//RLC_SPM_ACCUM_STATUS +#define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted__SHIFT 0x0 +#define RLC_SPM_ACCUM_STATUS__AccumDone__SHIFT 0x8 +#define RLC_SPM_ACCUM_STATUS__SpmDone__SHIFT 0x9 +#define RLC_SPM_ACCUM_STATUS__AccumOverflow__SHIFT 0xa +#define RLC_SPM_ACCUM_STATUS__AccumArmed__SHIFT 0xb +#define RLC_SPM_ACCUM_STATUS__SequenceInProgress__SHIFT 0xc +#define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress__SHIFT 0xd +#define RLC_SPM_ACCUM_STATUS__AllFifosEmpty__SHIFT 0xe +#define RLC_SPM_ACCUM_STATUS__FSMIsIdle__SHIFT 0xf +#define RLC_SPM_ACCUM_STATUS__SwaAccumDone__SHIFT 0x10 +#define RLC_SPM_ACCUM_STATUS__SwaSpmDone__SHIFT 0x11 +#define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow__SHIFT 0x12 +#define RLC_SPM_ACCUM_STATUS__SwaAccumArmed__SHIFT 0x13 +#define RLC_SPM_ACCUM_STATUS__AllSegsDone__SHIFT 0x14 +#define RLC_SPM_ACCUM_STATUS__RearmSwaPending__SHIFT 0x15 +#define RLC_SPM_ACCUM_STATUS__RearmSppPending__SHIFT 0x16 +#define RLC_SPM_ACCUM_STATUS__MultiSampleAborted__SHIFT 0x17 +#define RLC_SPM_ACCUM_STATUS__NumbSamplesCompleted_MASK 0x000000FFL +#define RLC_SPM_ACCUM_STATUS__AccumDone_MASK 0x00000100L +#define RLC_SPM_ACCUM_STATUS__SpmDone_MASK 0x00000200L +#define RLC_SPM_ACCUM_STATUS__AccumOverflow_MASK 0x00000400L +#define RLC_SPM_ACCUM_STATUS__AccumArmed_MASK 0x00000800L +#define RLC_SPM_ACCUM_STATUS__SequenceInProgress_MASK 0x00001000L +#define RLC_SPM_ACCUM_STATUS__FinalSequenceInProgress_MASK 0x00002000L +#define RLC_SPM_ACCUM_STATUS__AllFifosEmpty_MASK 0x00004000L +#define RLC_SPM_ACCUM_STATUS__FSMIsIdle_MASK 0x00008000L +#define RLC_SPM_ACCUM_STATUS__SwaAccumDone_MASK 0x00010000L +#define RLC_SPM_ACCUM_STATUS__SwaSpmDone_MASK 0x00020000L +#define RLC_SPM_ACCUM_STATUS__SwaAccumOverflow_MASK 0x00040000L +#define RLC_SPM_ACCUM_STATUS__SwaAccumArmed_MASK 0x00080000L +#define RLC_SPM_ACCUM_STATUS__AllSegsDone_MASK 0x00100000L +#define RLC_SPM_ACCUM_STATUS__RearmSwaPending_MASK 0x00200000L +#define RLC_SPM_ACCUM_STATUS__RearmSppPending_MASK 0x00400000L +#define RLC_SPM_ACCUM_STATUS__MultiSampleAborted_MASK 0x00800000L +//RLC_SPM_ACCUM_CTRL +#define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors__SHIFT 0x0 +#define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation__SHIFT 0x1 +#define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum__SHIFT 0x2 +#define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock__SHIFT 0x3 +#define RLC_SPM_ACCUM_CTRL__StrobeStartSpm__SHIFT 0x4 +#define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum__SHIFT 0x8 +#define RLC_SPM_ACCUM_CTRL__StrobeStartSwa__SHIFT 0x9 +#define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires__SHIFT 0xa +#define RLC_SPM_ACCUM_CTRL__StrobeResetPerfMonitors_MASK 0x00000001L +#define RLC_SPM_ACCUM_CTRL__StrobeStartAccumulation_MASK 0x00000002L +#define RLC_SPM_ACCUM_CTRL__StrobeRearmAccum_MASK 0x00000004L +#define RLC_SPM_ACCUM_CTRL__StrobeResetSpmBlock_MASK 0x00000008L +#define RLC_SPM_ACCUM_CTRL__StrobeStartSpm_MASK 0x000000F0L +#define RLC_SPM_ACCUM_CTRL__StrobeRearmSwaAccum_MASK 0x00000100L +#define RLC_SPM_ACCUM_CTRL__StrobeStartSwa_MASK 0x00000200L +#define RLC_SPM_ACCUM_CTRL__StrobePerfmonSampleWires_MASK 0x00000400L +//RLC_SPM_ACCUM_MODE +#define RLC_SPM_ACCUM_MODE__EnableAccum__SHIFT 0x0 +#define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode__SHIFT 0x1 +#define RLC_SPM_ACCUM_MODE__EnableSPPMode__SHIFT 0x2 +#define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable__SHIFT 0x3 +#define RLC_SPM_ACCUM_MODE__RESERVED_4__SHIFT 0x4 +#define RLC_SPM_ACCUM_MODE__AutoAccumEn__SHIFT 0x5 +#define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn__SHIFT 0x6 +#define RLC_SPM_ACCUM_MODE__AutoSpmEn__SHIFT 0x7 +#define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn__SHIFT 0x8 +#define RLC_SPM_ACCUM_MODE__Globals_LoadOverride__SHIFT 0x9 +#define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride__SHIFT 0xa +#define RLC_SPM_ACCUM_MODE__SE0_LoadOverride__SHIFT 0xb +#define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride__SHIFT 0xc +#define RLC_SPM_ACCUM_MODE__SE1_LoadOverride__SHIFT 0xd +#define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride__SHIFT 0xe +#define RLC_SPM_ACCUM_MODE__RESERVED_16_15__SHIFT 0xf +#define RLC_SPM_ACCUM_MODE__RESERVED_18_17__SHIFT 0x11 +#define RLC_SPM_ACCUM_MODE__RESERVED_20_19__SHIFT 0x13 +#define RLC_SPM_ACCUM_MODE__RESERVED_22_21__SHIFT 0x15 +#define RLC_SPM_ACCUM_MODE__RESERVED_24_23__SHIFT 0x17 +#define RLC_SPM_ACCUM_MODE__RESERVED_26_25__SHIFT 0x19 +#define RLC_SPM_ACCUM_MODE__RESERVED_31_27__SHIFT 0x1b +#define RLC_SPM_ACCUM_MODE__EnableAccum_MASK 0x00000001L +#define RLC_SPM_ACCUM_MODE__EnableSpmWithAccumMode_MASK 0x00000002L +#define RLC_SPM_ACCUM_MODE__EnableSPPMode_MASK 0x00000004L +#define RLC_SPM_ACCUM_MODE__AutoResetPerfmonDisable_MASK 0x00000008L +#define RLC_SPM_ACCUM_MODE__RESERVED_4_MASK 0x00000010L +#define RLC_SPM_ACCUM_MODE__AutoAccumEn_MASK 0x00000020L +#define RLC_SPM_ACCUM_MODE__SwaAutoAccumEn_MASK 0x00000040L +#define RLC_SPM_ACCUM_MODE__AutoSpmEn_MASK 0x00000080L +#define RLC_SPM_ACCUM_MODE__SwaAutoSpmEn_MASK 0x00000100L +#define RLC_SPM_ACCUM_MODE__Globals_LoadOverride_MASK 0x00000200L +#define RLC_SPM_ACCUM_MODE__Globals_SwaLoadOverride_MASK 0x00000400L +#define RLC_SPM_ACCUM_MODE__SE0_LoadOverride_MASK 0x00000800L +#define RLC_SPM_ACCUM_MODE__SE0_SwaLoadOverride_MASK 0x00001000L +#define RLC_SPM_ACCUM_MODE__SE1_LoadOverride_MASK 0x00002000L +#define RLC_SPM_ACCUM_MODE__SE1_SwaLoadOverride_MASK 0x00004000L +#define RLC_SPM_ACCUM_MODE__RESERVED_16_15_MASK 0x00018000L +#define RLC_SPM_ACCUM_MODE__RESERVED_18_17_MASK 0x00060000L +#define RLC_SPM_ACCUM_MODE__RESERVED_20_19_MASK 0x00180000L +#define RLC_SPM_ACCUM_MODE__RESERVED_22_21_MASK 0x00600000L +#define RLC_SPM_ACCUM_MODE__RESERVED_24_23_MASK 0x01800000L +#define RLC_SPM_ACCUM_MODE__RESERVED_26_25_MASK 0x06000000L +#define RLC_SPM_ACCUM_MODE__RESERVED_31_27_MASK 0xF8000000L +//RLC_SPM_ACCUM_THRESHOLD +#define RLC_SPM_ACCUM_THRESHOLD__Threshold__SHIFT 0x0 +#define RLC_SPM_ACCUM_THRESHOLD__Threshold_MASK 0x0000FFFFL +//RLC_SPM_ACCUM_SAMPLES_REQUESTED +#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested__SHIFT 0x0 +#define RLC_SPM_ACCUM_SAMPLES_REQUESTED__SamplesRequested_MASK 0x000000FFL +//RLC_SPM_ACCUM_DATARAM_WRCOUNT +#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_WRCOUNT__DataRamWrCount_MASK 0x0007FFFFL +//RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region__SHIFT 0x0 +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region__SHIFT 0x8 +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__spp_addr_region_MASK 0x000000FFL +#define RLC_SPM_ACCUM_DATARAM_32BITCNTRS_REGIONS__swa_addr_region_MASK 0x0000FF00L +//RLC_SPM_PAUSE +#define RLC_SPM_PAUSE__PAUSE__SHIFT 0x0 +#define RLC_SPM_PAUSE__PAUSED__SHIFT 0x1 +#define RLC_SPM_PAUSE__PAUSE_MASK 0x00000001L +#define RLC_SPM_PAUSE__PAUSED_MASK 0x00000002L +//RLC_SPM_STATUS +#define RLC_SPM_STATUS__CTL_BUSY__SHIFT 0x0 +#define RLC_SPM_STATUS__RSPM_REG_BUSY__SHIFT 0x1 +#define RLC_SPM_STATUS__SPM_RSPM_BUSY__SHIFT 0x2 +#define RLC_SPM_STATUS__SPM_RSPM_IO_BUSY__SHIFT 0x3 +#define RLC_SPM_STATUS__SE_RSPM_IO_BUSY__SHIFT 0x4 +#define RLC_SPM_STATUS__ACCUM_BUSY__SHIFT 0xf +#define RLC_SPM_STATUS__FSM_MASTER_STATE__SHIFT 0x10 +#define RLC_SPM_STATUS__FSM_MEMORY_STATE__SHIFT 0x14 +#define RLC_SPM_STATUS__CTL_REQ_STATE__SHIFT 0x18 +#define RLC_SPM_STATUS__CTL_RET_STATE__SHIFT 0x1a +#define RLC_SPM_STATUS__CTL_BUSY_MASK 0x00000001L +#define RLC_SPM_STATUS__RSPM_REG_BUSY_MASK 0x00000002L +#define RLC_SPM_STATUS__SPM_RSPM_BUSY_MASK 0x00000004L +#define RLC_SPM_STATUS__SPM_RSPM_IO_BUSY_MASK 0x00000008L +#define RLC_SPM_STATUS__SE_RSPM_IO_BUSY_MASK 0x00000FF0L +#define RLC_SPM_STATUS__ACCUM_BUSY_MASK 0x00008000L +#define RLC_SPM_STATUS__FSM_MASTER_STATE_MASK 0x000F0000L +#define RLC_SPM_STATUS__FSM_MEMORY_STATE_MASK 0x00F00000L +#define RLC_SPM_STATUS__CTL_REQ_STATE_MASK 0x03000000L +#define RLC_SPM_STATUS__CTL_RET_STATE_MASK 0x04000000L +//RLC_SPM_GFXCLOCK_LOWCOUNT +#define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT__SHIFT 0x0 +#define RLC_SPM_GFXCLOCK_LOWCOUNT__GFXCLOCK_LOWCOUNT_MASK 0xFFFFFFFFL +//RLC_SPM_GFXCLOCK_HIGHCOUNT +#define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT__SHIFT 0x0 +#define RLC_SPM_GFXCLOCK_HIGHCOUNT__GFXCLOCK_HIGHCOUNT_MASK 0xFFFFFFFFL +//RLC_SPM_GTS_TRIGGER_VALUE_LO +#define RLC_SPM_GTS_TRIGGER_VALUE_LO__VALUE_LO__SHIFT 0x0 +#define RLC_SPM_GTS_TRIGGER_VALUE_LO__VALUE_LO_MASK 0xFFFFFFFFL +//RLC_SPM_GTS_TRIGGER_VALUE_HI +#define RLC_SPM_GTS_TRIGGER_VALUE_HI__VALUE_HI__SHIFT 0x0 +#define RLC_SPM_GTS_TRIGGER_VALUE_HI__VALUE_HI_MASK 0x00FFFFFFL +//RLC_SPM_GLOBAL_USER_DATA_0 +#define RLC_SPM_GLOBAL_USER_DATA_0__LO__SHIFT 0x0 +#define RLC_SPM_GLOBAL_USER_DATA_0__HI__SHIFT 0x10 +#define RLC_SPM_GLOBAL_USER_DATA_0__LO_MASK 0x0000FFFFL +#define RLC_SPM_GLOBAL_USER_DATA_0__HI_MASK 0xFFFF0000L +//RLC_SPM_GLOBAL_USER_DATA_1 +#define RLC_SPM_GLOBAL_USER_DATA_1__LO__SHIFT 0x0 +#define RLC_SPM_GLOBAL_USER_DATA_1__HI__SHIFT 0x10 +#define RLC_SPM_GLOBAL_USER_DATA_1__LO_MASK 0x0000FFFFL +#define RLC_SPM_GLOBAL_USER_DATA_1__HI_MASK 0xFFFF0000L +//RLC_SPM_GLOBAL_USER_DATA_2 +#define RLC_SPM_GLOBAL_USER_DATA_2__LO__SHIFT 0x0 +#define RLC_SPM_GLOBAL_USER_DATA_2__HI__SHIFT 0x10 +#define RLC_SPM_GLOBAL_USER_DATA_2__LO_MASK 0x0000FFFFL +#define RLC_SPM_GLOBAL_USER_DATA_2__HI_MASK 0xFFFF0000L +//RLC_SPM_GLOBAL_USER_DATA_3 +#define RLC_SPM_GLOBAL_USER_DATA_3__LO__SHIFT 0x0 +#define RLC_SPM_GLOBAL_USER_DATA_3__HI__SHIFT 0x10 +#define RLC_SPM_GLOBAL_USER_DATA_3__LO_MASK 0x0000FFFFL +#define RLC_SPM_GLOBAL_USER_DATA_3__HI_MASK 0xFFFF0000L +//RLC_SPM_MODE +#define RLC_SPM_MODE__MODE__SHIFT 0x0 +#define RLC_SPM_MODE__MODE_MASK 0x00000001L +//RLC_SPM_RSPM_REQ_DATA +#define RLC_SPM_RSPM_REQ_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_RSPM_REQ_DATA__DATA_MASK 0x0000000FL +//RLC_SPM_RSPM_REQ_OP +#define RLC_SPM_RSPM_REQ_OP__OP__SHIFT 0x0 +#define RLC_SPM_RSPM_REQ_OP__OP_MASK 0x0000000FL +//RLC_SPM_RSPM_RET_DATA +#define RLC_SPM_RSPM_RET_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_RSPM_RET_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_RSPM_RET_OP +#define RLC_SPM_RSPM_RET_OP__OP__SHIFT 0x0 +#define RLC_SPM_RSPM_RET_OP__VALID__SHIFT 0x8 +#define RLC_SPM_RSPM_RET_OP__OP_MASK 0x0000000FL +#define RLC_SPM_RSPM_RET_OP__VALID_MASK 0x00000100L +//RLC_SPM_SE_RSPM_REQ_DATA +#define RLC_SPM_SE_RSPM_REQ_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_REQ_DATA__DATA_MASK 0x0000000FL +//RLC_SPM_SE_RSPM_REQ_OP +#define RLC_SPM_SE_RSPM_REQ_OP__OP__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_REQ_OP__OP_MASK 0x0000000FL +//RLC_SPM_SE_RSPM_RET_DATA +#define RLC_SPM_SE_RSPM_RET_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_RET_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_SE_RSPM_RET_OP +#define RLC_SPM_SE_RSPM_RET_OP__OP__SHIFT 0x0 +#define RLC_SPM_SE_RSPM_RET_OP__VALID__SHIFT 0x8 +#define RLC_SPM_SE_RSPM_RET_OP__OP_MASK 0x0000000FL +#define RLC_SPM_SE_RSPM_RET_OP__VALID_MASK 0x00000100L +//RLC_SPM_RSPM_CMD +#define RLC_SPM_RSPM_CMD__CMD__SHIFT 0x0 +#define RLC_SPM_RSPM_CMD__CMD_MASK 0x0000000FL +//RLC_SPM_RSPM_CMD_ACK +#define RLC_SPM_RSPM_CMD_ACK__SE0_ACK__SHIFT 0x0 +#define RLC_SPM_RSPM_CMD_ACK__SE1_ACK__SHIFT 0x1 +#define RLC_SPM_RSPM_CMD_ACK__SE2_ACK__SHIFT 0x2 +#define RLC_SPM_RSPM_CMD_ACK__SE3_ACK__SHIFT 0x3 +#define RLC_SPM_RSPM_CMD_ACK__SE4_ACK__SHIFT 0x4 +#define RLC_SPM_RSPM_CMD_ACK__SE5_ACK__SHIFT 0x5 +#define RLC_SPM_RSPM_CMD_ACK__SE6_ACK__SHIFT 0x6 +#define RLC_SPM_RSPM_CMD_ACK__SE7_ACK__SHIFT 0x7 +#define RLC_SPM_RSPM_CMD_ACK__SPM_ACK__SHIFT 0x8 +#define RLC_SPM_RSPM_CMD_ACK__SE0_ACK_MASK 0x00000001L +#define RLC_SPM_RSPM_CMD_ACK__SE1_ACK_MASK 0x00000002L +#define RLC_SPM_RSPM_CMD_ACK__SE2_ACK_MASK 0x00000004L +#define RLC_SPM_RSPM_CMD_ACK__SE3_ACK_MASK 0x00000008L +#define RLC_SPM_RSPM_CMD_ACK__SE4_ACK_MASK 0x00000010L +#define RLC_SPM_RSPM_CMD_ACK__SE5_ACK_MASK 0x00000020L +#define RLC_SPM_RSPM_CMD_ACK__SE6_ACK_MASK 0x00000040L +#define RLC_SPM_RSPM_CMD_ACK__SE7_ACK_MASK 0x00000080L +#define RLC_SPM_RSPM_CMD_ACK__SPM_ACK_MASK 0x00000100L +//RLC_SPM_SPARE +#define RLC_SPM_SPARE__SPARE__SHIFT 0x0 +#define RLC_SPM_SPARE__SPARE_MASK 0xFFFFFFFFL +//RLC_PERFMON_CNTL +#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define RLC_PERFMON_CNTL__RESERVED_9_3__SHIFT 0x3 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define RLC_PERFMON_CNTL__RESERVED__SHIFT 0xb +#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x00000007L +#define RLC_PERFMON_CNTL__RESERVED_9_3_MASK 0x000003F8L +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +#define RLC_PERFMON_CNTL__RESERVED_MASK 0xFFFFF800L +//RLC_PERFCOUNTER0_SELECT +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL +//RLC_PERFCOUNTER1_SELECT +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x000000FFL +//RLC_GPU_IOV_PERF_CNT_CNTL +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT__SHIFT 0x1 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET__SHIFT 0x2 +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED__SHIFT 0x3 +#define RLC_GPU_IOV_PERF_CNT_CNTL__ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_PERF_CNT_CNTL__MODE_SELECT_MASK 0x00000002L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESET_MASK 0x00000004L +#define RLC_GPU_IOV_PERF_CNT_CNTL__RESERVED_MASK 0xFFFFFFF8L +//RLC_GPU_IOV_PERF_CNT_WR_ADDR +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID__SHIFT 0x5 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED__SHIFT 0x7 +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__VFID_MASK 0x0000001FL +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__CNT_ID_MASK 0x00000060L +#define RLC_GPU_IOV_PERF_CNT_WR_ADDR__RESERVED_MASK 0xFFFFFF80L +//RLC_GPU_IOV_PERF_CNT_WR_DATA +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_WR_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_PERF_CNT_RD_ADDR +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID__SHIFT 0x5 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED__SHIFT 0x7 +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__VFID_MASK 0x0000001FL +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__CNT_ID_MASK 0x00000060L +#define RLC_GPU_IOV_PERF_CNT_RD_ADDR__RESERVED_MASK 0xFFFFFF80L +//RLC_GPU_IOV_PERF_CNT_RD_DATA +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_PERF_CNT_RD_DATA__DATA_MASK 0xFFFFFFFFL +//GCR_PERFCOUNTER0_SELECT +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GCR_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GCR_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GCR_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GCR_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GCR_PERFCOUNTER0_SELECT1 +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GCR_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GCR_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GCR_PERFCOUNTER1_SELECT +#define GCR_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GCR_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GCR_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GCR_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GCR_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GCR_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GCR_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GCR_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GCR_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GCR_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GCR_PERFCOUNTER1_SELECT1 +#define GCR_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GCR_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GCR_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GCR_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GCR_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GCR_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GCR_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GCR_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHA_PERFCOUNTER0_SELECT +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CHA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER0_SELECT1 +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHA_PERFCOUNTER1_SELECT +#define CHA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define CHA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER1_SELECT1 +#define CHA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHA_PERFCOUNTER2_SELECT +#define CHA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define CHA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER2_SELECT1 +#define CHA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CHA_PERFCOUNTER3_SELECT +#define CHA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CHA_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define CHA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define CHA_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define CHA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CHA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define CHA_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CHA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CHA_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CHA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//CHA_PERFCOUNTER3_SELECT1 +#define CHA_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CHA_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define CHA_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CHA_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CHA_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CHA_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CHA_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CHA_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gdfll_xvmin_xvmin_xvmin_reg_blk +//XVMIN_XVMIN_WR_DATA +#define XVMIN_XVMIN_WR_DATA__XVMINDATA__SHIFT 0x0 +#define XVMIN_XVMIN_WR_DATA__XVMINDATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_hypdec +//RLC_GPU_IOV_VF_ENABLE +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x00000001L +#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0x0000FFFEL +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xFFFF0000L +//RLC_FED_DRVR_STATUS +#define RLC_FED_DRVR_STATUS__PENDING__SHIFT 0x0 +#define RLC_FED_DRVR_STATUS__PENDING_MASK 0x00000007L +//RLC_GPU_IOV_CFG_REG6 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7 +#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa +#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x0000007FL +#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x00000080L +#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x00000300L +#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xFFFFFC00L +//RLC_SDMA0_STATUS +#define RLC_SDMA0_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA0_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA1_STATUS +#define RLC_SDMA1_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA1_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA2_STATUS +#define RLC_SDMA2_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA2_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA3_STATUS +#define RLC_SDMA3_STATUS__STATUS__SHIFT 0x0 +#define RLC_SDMA3_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA0_BUSY_STATUS +#define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA0_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA1_BUSY_STATUS +#define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA1_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA2_BUSY_STATUS +#define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA2_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_SDMA3_BUSY_STATUS +#define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS__SHIFT 0x0 +#define RLC_SDMA3_BUSY_STATUS__BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_CFG_REG8 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_VF_DOORBELL_STATUS +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS__PF_DOORBELL_STATUS_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_SET +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__VF_DOORBELL_STATUS_SET_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_SET__PF_DOORBELL_STATUS_SET_MASK 0x80000000L +//RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR__SHIFT 0x0 +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR__SHIFT 0x1f +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__VF_DOORBELL_STATUS_CLR_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VF_DOORBELL_STATUS_CLR__PF_DOORBELL_STATUS_CLR_MASK 0x80000000L +//RLC_GPU_IOV_VF_MASK +#define RLC_GPU_IOV_VF_MASK__VF_MASK__SHIFT 0x0 +#define RLC_GPU_IOV_VF_MASK__RESERVED__SHIFT 0x1f +#define RLC_GPU_IOV_VF_MASK__VF_MASK_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VF_MASK__RESERVED_MASK 0x80000000L +//RLC_HYP_SEMAPHORE_0 +#define RLC_HYP_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL +//RLC_HYP_SEMAPHORE_1 +#define RLC_HYP_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL +//RLC_BUSY_CLK_CNTL +#define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY__SHIFT 0x0 +#define RLC_BUSY_CLK_CNTL__RESERVED__SHIFT 0x6 +#define RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY__SHIFT 0x8 +#define RLC_BUSY_CLK_CNTL__BUSY_OFF_LATENCY_MASK 0x0000003FL +#define RLC_BUSY_CLK_CNTL__RESERVED_MASK 0x000000C0L +#define RLC_BUSY_CLK_CNTL__GRBM_BUSY_OFF_LATENCY_MASK 0x00003F00L +//RLC_CLK_CNTL +#define RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE__SHIFT 0x0 +#define RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE__SHIFT 0x1 +#define RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE__SHIFT 0x2 +#define RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE__SHIFT 0x3 +#define RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE__SHIFT 0x4 +#define RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE__SHIFT 0x5 +#define RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE__SHIFT 0x6 +#define RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE__SHIFT 0x7 +#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE__SHIFT 0x8 +#define RLC_CLK_CNTL__RESERVED_9__SHIFT 0x9 +#define RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE__SHIFT 0xa +#define RLC_CLK_CNTL__RESERVED_11__SHIFT 0xb +#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE__SHIFT 0xc +#define RLC_CLK_CNTL__RLC_DFLL_ICG_OVERRIDE__SHIFT 0xd +#define RLC_CLK_CNTL__RESERVED_15__SHIFT 0xf +#define RLC_CLK_CNTL__RLC_LX6_CORE_ICG_OVERRIDE__SHIFT 0x10 +#define RLC_CLK_CNTL__RLC_LX6_ICG_OVERRIDE__SHIFT 0x11 +#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE__SHIFT 0x12 +#define RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE__SHIFT 0x13 +#define RLC_CLK_CNTL__RLC_BRIDGE_ICG_OVERRIDE__SHIFT 0x14 +#define RLC_CLK_CNTL__RLC_DMA_ICG_OVERRIDE__SHIFT 0x15 +#define RLC_CLK_CNTL__RESERVED__SHIFT 0x16 +#define RLC_CLK_CNTL__RLC_SRM_ICG_OVERRIDE_MASK 0x00000001L +#define RLC_CLK_CNTL__RLC_IMU_ICG_OVERRIDE_MASK 0x00000002L +#define RLC_CLK_CNTL__RLC_SPM_ICG_OVERRIDE_MASK 0x00000004L +#define RLC_CLK_CNTL__RLC_SPM_RSPM_ICG_OVERRIDE_MASK 0x00000008L +#define RLC_CLK_CNTL__RLC_GPM_ICG_OVERRIDE_MASK 0x00000010L +#define RLC_CLK_CNTL__RLC_CMN_ICG_OVERRIDE_MASK 0x00000020L +#define RLC_CLK_CNTL__RLC_TC_ICG_OVERRIDE_MASK 0x00000040L +#define RLC_CLK_CNTL__RLC_REG_ICG_OVERRIDE_MASK 0x00000080L +#define RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK 0x00000100L +#define RLC_CLK_CNTL__RESERVED_9_MASK 0x00000200L +#define RLC_CLK_CNTL__RLC_SPP_ICG_OVERRIDE_MASK 0x00000400L +#define RLC_CLK_CNTL__RESERVED_11_MASK 0x00000800L +#define RLC_CLK_CNTL__RLC_TC_FGCG_REP_OVERRIDE_MASK 0x00001000L +#define RLC_CLK_CNTL__RLC_DFLL_ICG_OVERRIDE_MASK 0x00002000L +#define RLC_CLK_CNTL__RESERVED_15_MASK 0x00008000L +#define RLC_CLK_CNTL__RLC_LX6_CORE_ICG_OVERRIDE_MASK 0x00010000L +#define RLC_CLK_CNTL__RLC_LX6_ICG_OVERRIDE_MASK 0x00020000L +#define RLC_CLK_CNTL__RLC_UTCL2_FGCG_OVERRIDE_MASK 0x00040000L +#define RLC_CLK_CNTL__RLC_IH_GASKET_ICG_OVERRIDE_MASK 0x00080000L +#define RLC_CLK_CNTL__RLC_BRIDGE_ICG_OVERRIDE_MASK 0x00100000L +#define RLC_CLK_CNTL__RLC_DMA_ICG_OVERRIDE_MASK 0x00200000L +#define RLC_CLK_CNTL__RESERVED_MASK 0xFFC00000L +//RLC_GPU_IOV_SCH_BLOCK +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver__SHIFT 0x4 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size__SHIFT 0x8 +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED__SHIFT 0x10 +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_ID_MASK 0x0000000FL +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Ver_MASK 0x000000F0L +#define RLC_GPU_IOV_SCH_BLOCK__Sch_Block_Size_MASK 0x0000FF00L +#define RLC_GPU_IOV_SCH_BLOCK__RESERVED_MASK 0xFFFF0000L +//RLC_GPU_IOV_CFG_REG1 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4 +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 +#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6 +#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8 +#define RLC_GPU_IOV_CFG_REG1__PF_VF__SHIFT 0xf +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10 +#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18 +#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0x0000000FL +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x00000010L +#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L +#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0x000000C0L +#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0x00007F00L +#define RLC_GPU_IOV_CFG_REG1__PF_VF_MASK 0x00008000L +#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0x00FF0000L +#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xFF000000L +//RLC_GPU_IOV_CFG_REG2 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_VM_BUSY_STATUS +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_VM_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_0__ACTIVE_FUNCTIONS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_ACTIVE_FCN_ID +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_6_5__SHIFT 0x5 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x7 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__ACTIVE_FCN_ID_STATUS__SHIFT 0x8 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_31_12__SHIFT 0xc +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0x0000001FL +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_6_5_MASK 0x00000060L +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x00000080L +#define RLC_GPU_IOV_ACTIVE_FCN_ID__ACTIVE_FCN_ID_STATUS_MASK 0x00000F00L +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_31_12_MASK 0xFFFFF000L +//RLC_GPU_IOV_SCH_3 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_3__Time_Quanta_Def_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_1 +#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SCH_2 +#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0 +#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xFFFFFFFFL +//RLC_IH_COOKIE +#define RLC_IH_COOKIE__DATA__SHIFT 0x0 +#define RLC_IH_COOKIE__DATA_MASK 0xFFFFFFFFL +//RLC_IH_COOKIE_CNTL +#define RLC_IH_COOKIE_CNTL__CREDIT__SHIFT 0x0 +#define RLC_IH_COOKIE_CNTL__RESET_COUNTER__SHIFT 0x2 +#define RLC_IH_COOKIE_CNTL__CREDIT_MASK 0x00000003L +#define RLC_IH_COOKIE_CNTL__RESET_COUNTER_MASK 0x00000004L +//RLC_HYP_RLCG_UCODE_CHKSUM +#define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define RLC_HYP_RLCG_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SMU_RESPONSE +#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_VIRT_RESET_REQ +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0 +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f +#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0x7FFFFFFFL +#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000L +//RLC_GPU_IOV_RLC_RESPONSE +#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xFFFFFFFFL +//RLC_HYP_SEMAPHORE_2 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL +//RLC_HYP_SEMAPHORE_3 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 +#define RLC_HYP_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL +//RLC_GPM_UCODE_ADDR +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xe +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFFL +#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xFFFFC000L +//RLC_GPM_UCODE_DATA +#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//RLC_GPM_IRAM_ADDR +#define RLC_GPM_IRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_IRAM_ADDR__ADDR_MASK 0xFFFFFFFFL +//RLC_GPM_IRAM_DATA +#define RLC_GPM_IRAM_DATA__DATA__SHIFT 0x0 +#define RLC_GPM_IRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_LX6_DRAM_ADDR +#define RLC_LX6_DRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_LX6_DRAM_ADDR__ADDR_MASK 0x000007FFL +//RLC_LX6_DRAM_DATA +#define RLC_LX6_DRAM_DATA__DATA__SHIFT 0x0 +#define RLC_LX6_DRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_LX6_IRAM_ADDR +#define RLC_LX6_IRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_LX6_IRAM_ADDR__ADDR_MASK 0x00000FFFL +//RLC_LX6_IRAM_DATA +#define RLC_LX6_IRAM_DATA__DATA__SHIFT 0x0 +#define RLC_LX6_IRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_SCRATCH_ADDR +#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x0000FFFFL +//RLC_GPM_SCRATCH_DATA +#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_DRAM_ADDR +#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xd +#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x00001FFFL +#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xFFFFE000L +//RLC_SRM_DRAM_DATA +#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_DRAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_ARAM_ADDR +#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xd +#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x00001FFFL +#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xFFFFE000L +//RLC_SRM_ARAM_DATA +#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_ARAM_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GTS_OFFSET_LSB +#define RLC_GTS_OFFSET_LSB__DATA__SHIFT 0x0 +#define RLC_GTS_OFFSET_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_GTS_OFFSET_MSB +#define RLC_GTS_OFFSET_MSB__DATA__SHIFT 0x0 +#define RLC_GTS_OFFSET_MSB__DATA_MASK 0xFFFFFFFFL +//RLC_GTS_OFFSET_SNAP_LSB +#define RLC_GTS_OFFSET_SNAP_LSB__DATA__SHIFT 0x0 +#define RLC_GTS_OFFSET_SNAP_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_GTS_OFFSET_SNAP_MSB +#define RLC_GTS_OFFSET_SNAP_MSB__DATA__SHIFT 0x0 +#define RLC_GTS_OFFSET_SNAP_MSB__DATA_MASK 0xFFFFFFFFL +//RLC_GAP_PWROK +#define RLC_GAP_PWROK__GAP_PWROK__SHIFT 0x0 +#define RLC_GAP_PWROK__GAP_PWROK_MASK 0x00000001L +//RLC_GAP_PWROK_COUNT +#define RLC_GAP_PWROK_COUNT__COUNT__SHIFT 0x0 +#define RLC_GAP_PWROK_COUNT__COUNT_MASK 0x0000000FL +//GLARB_HASH_CFG +#define GLARB_HASH_CFG__HPA_HASH_EN__SHIFT 0x0 +#define GLARB_HASH_CFG__CHANNEL_HASH_EN__SHIFT 0x13 +#define GLARB_HASH_CFG__RESERVED__SHIFT 0x14 +#define GLARB_HASH_CFG__HPA_HASH_EN_MASK 0x00000001L +#define GLARB_HASH_CFG__CHANNEL_HASH_EN_MASK 0x00080000L +#define GLARB_HASH_CFG__RESERVED_MASK 0xFFF00000L +//CH_PIPE_STEER +#define CH_PIPE_STEER__PIPE0__SHIFT 0x0 +#define CH_PIPE_STEER__PIPE1__SHIFT 0x1 +#define CH_PIPE_STEER__MODE__SHIFT 0x2 +#define CH_PIPE_STEER__PIPE0_MASK 0x00000001L +#define CH_PIPE_STEER__PIPE1_MASK 0x00000002L +#define CH_PIPE_STEER__MODE_MASK 0x00000004L +//GLARB_PIPE_STEER_LSB +#define GLARB_PIPE_STEER_LSB__PIPE0__SHIFT 0x0 +#define GLARB_PIPE_STEER_LSB__PIPE1__SHIFT 0x4 +#define GLARB_PIPE_STEER_LSB__PIPE2__SHIFT 0x8 +#define GLARB_PIPE_STEER_LSB__PIPE3__SHIFT 0xc +#define GLARB_PIPE_STEER_LSB__PIPE4__SHIFT 0x10 +#define GLARB_PIPE_STEER_LSB__PIPE5__SHIFT 0x14 +#define GLARB_PIPE_STEER_LSB__PIPE6__SHIFT 0x18 +#define GLARB_PIPE_STEER_LSB__PIPE7__SHIFT 0x1c +#define GLARB_PIPE_STEER_LSB__PIPE0_MASK 0x0000000FL +#define GLARB_PIPE_STEER_LSB__PIPE1_MASK 0x000000F0L +#define GLARB_PIPE_STEER_LSB__PIPE2_MASK 0x00000F00L +#define GLARB_PIPE_STEER_LSB__PIPE3_MASK 0x0000F000L +#define GLARB_PIPE_STEER_LSB__PIPE4_MASK 0x000F0000L +#define GLARB_PIPE_STEER_LSB__PIPE5_MASK 0x00F00000L +#define GLARB_PIPE_STEER_LSB__PIPE6_MASK 0x0F000000L +#define GLARB_PIPE_STEER_LSB__PIPE7_MASK 0xF0000000L +//GLARB_PIPE_STEER_MSB +#define GLARB_PIPE_STEER_MSB__PIPE8__SHIFT 0x0 +#define GLARB_PIPE_STEER_MSB__PIPE9__SHIFT 0x4 +#define GLARB_PIPE_STEER_MSB__PIPE10__SHIFT 0x8 +#define GLARB_PIPE_STEER_MSB__PIPE11__SHIFT 0xc +#define GLARB_PIPE_STEER_MSB__MODE__SHIFT 0x10 +#define GLARB_PIPE_STEER_MSB__PIPE8_MASK 0x0000000FL +#define GLARB_PIPE_STEER_MSB__PIPE9_MASK 0x000000F0L +#define GLARB_PIPE_STEER_MSB__PIPE10_MASK 0x00000F00L +#define GLARB_PIPE_STEER_MSB__PIPE11_MASK 0x0000F000L +#define GLARB_PIPE_STEER_MSB__MODE_MASK 0x00010000L +//CH_HASH_CFG +#define CH_HASH_CFG__CHANNEL_FLIP__SHIFT 0x12 +#define CH_HASH_CFG__CHANNEL_HASH_EN__SHIFT 0x13 +#define CH_HASH_CFG__RESERVED__SHIFT 0x14 +#define CH_HASH_CFG__CHANNEL_FLIP_MASK 0x00040000L +#define CH_HASH_CFG__CHANNEL_HASH_EN_MASK 0x00080000L +#define CH_HASH_CFG__RESERVED_MASK 0xFFF00000L +//GLARB_LPDDR_PIPE_STEER_LSB +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE0__SHIFT 0x0 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE1__SHIFT 0x4 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE2__SHIFT 0x8 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE3__SHIFT 0xc +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE4__SHIFT 0x10 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE5__SHIFT 0x14 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE6__SHIFT 0x18 +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE7__SHIFT 0x1c +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE0_MASK 0x0000000FL +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE1_MASK 0x000000F0L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE2_MASK 0x00000F00L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE3_MASK 0x0000F000L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE4_MASK 0x000F0000L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE5_MASK 0x00F00000L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE6_MASK 0x0F000000L +#define GLARB_LPDDR_PIPE_STEER_LSB__PIPE7_MASK 0xF0000000L +//GLARB_LPDDR_PIPE_STEER_MSB +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE8__SHIFT 0x0 +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE9__SHIFT 0x4 +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE10__SHIFT 0x8 +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE11__SHIFT 0xc +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE8_MASK 0x0000000FL +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE9_MASK 0x000000F0L +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE10_MASK 0x00000F00L +#define GLARB_LPDDR_PIPE_STEER_MSB__PIPE11_MASK 0x0000F000L +//GLARB_LOCAL_CAC +#define GLARB_LOCAL_CAC__THRESHOLD__SHIFT 0x0 +#define GLARB_LOCAL_CAC__OVERRIDE_EN__SHIFT 0x10 +#define GLARB_LOCAL_CAC__OVERRIDE_VAL__SHIFT 0x11 +#define GLARB_LOCAL_CAC__THRESHOLD_MASK 0x0000FFFFL +#define GLARB_LOCAL_CAC__OVERRIDE_EN_MASK 0x00010000L +#define GLARB_LOCAL_CAC__OVERRIDE_VAL_MASK 0x1FFE0000L +//GLARB_AID_SEL_CFG +#define GLARB_AID_SEL_CFG__AS_SEL__SHIFT 0x0 +#define GLARB_AID_SEL_CFG__RESERVED__SHIFT 0x5 +#define GLARB_AID_SEL_CFG__AS_SEL_MASK 0x0000001FL +#define GLARB_AID_SEL_CFG__RESERVED_MASK 0xFFFFFFE0L +//GC_USER_FULL_SA_UNIT_DISABLE +#define GC_USER_FULL_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 +#define GC_USER_FULL_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x03FFFF00L +//GC_USER_SA_UNIT_DISABLE +#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 +#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x00FFFF00L +//GC_USER_HBM_DISABLE +#define GC_USER_HBM_DISABLE__GC_USER_HBM_DISABLE__SHIFT 0x10 +#define GC_USER_HBM_DISABLE__GC_USER_HBM_DISABLE_MASK 0x0FFF0000L +//RLC_GPU_IOV_SDMA0_STATUS +#define RLC_GPU_IOV_SDMA0_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA1_STATUS +#define RLC_GPU_IOV_SDMA1_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA2_STATUS +#define RLC_GPU_IOV_SDMA2_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA2_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA3_STATUS +#define RLC_GPU_IOV_SDMA3_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA3_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA4_STATUS +#define RLC_GPU_IOV_SDMA4_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA4_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA5_STATUS +#define RLC_GPU_IOV_SDMA5_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA5_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA6_STATUS +#define RLC_GPU_IOV_SDMA6_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA6_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA7_STATUS +#define RLC_GPU_IOV_SDMA7_STATUS__STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA7_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA0_BUSY_STATUS +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA1_BUSY_STATUS +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA2_BUSY_STATUS +#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA2_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA3_BUSY_STATUS +#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA3_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA4_BUSY_STATUS +#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA4_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA5_BUSY_STATUS +#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA5_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA6_BUSY_STATUS +#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA6_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL +//RLC_GPU_IOV_SDMA7_BUSY_STATUS +#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0 +#define RLC_GPU_IOV_SDMA7_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cphypdec +//CP_HYP_CONTEXT_RANGE_BASE +#define CP_HYP_CONTEXT_RANGE_BASE__BASE__SHIFT 0x0 +#define CP_HYP_CONTEXT_RANGE_BASE__BASE_MASK 0x0003FFFFL +//CP_HYP_CONTEXT_RANGE_END +#define CP_HYP_CONTEXT_RANGE_END__END__SHIFT 0x0 +#define CP_HYP_CONTEXT_RANGE_END__END_MASK 0x0003FFFFL +//CP_HYP_PFP_UCODE_ADDR +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_ADDR__PIPE_SEL__SHIFT 0x1f +#define CP_HYP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000000FFL +#define CP_HYP_PFP_UCODE_ADDR__PIPE_SEL_MASK 0x80000000L +//CP_PFP_UCODE_ADDR +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_PFP_UCODE_ADDR__PIPE_SEL__SHIFT 0x1f +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x000000FFL +#define CP_PFP_UCODE_ADDR__PIPE_SEL_MASK 0x80000000L +//CP_HYP_PFP_UCODE_DATA +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_PFP_UCODE_DATA +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_ME_UCODE_ADDR +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_ME_UCODE_ADDR__PIPE_SEL__SHIFT 0x1f +#define CP_HYP_ME_UCODE_ADDR__UCODE_ADDR_MASK 0x000000FFL +#define CP_HYP_ME_UCODE_ADDR__PIPE_SEL_MASK 0x80000000L +//CP_ME_RAM_RADDR +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 +#define CP_ME_RAM_RADDR__PIPE_SEL__SHIFT 0x1f +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x000000FFL +#define CP_ME_RAM_RADDR__PIPE_SEL_MASK 0x80000000L +//CP_ME_RAM_WADDR +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 +#define CP_ME_RAM_WADDR__PIPE_SEL__SHIFT 0x1f +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x000000FFL +#define CP_ME_RAM_WADDR__PIPE_SEL_MASK 0x80000000L +//CP_HYP_ME_UCODE_DATA +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_ME_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_ME_RAM_DATA +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xFFFFFFFFL +//CP_HYP_MEC1_UCODE_ADDR +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_ADDR__PIPE_SEL__SHIFT 0x1e +#define CP_HYP_MEC1_UCODE_ADDR__UCODE_ADDR_MASK 0x000000FFL +#define CP_HYP_MEC1_UCODE_ADDR__PIPE_SEL_MASK 0xC0000000L +//CP_MEC_ME1_UCODE_ADDR +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_ADDR__PIPE_SEL__SHIFT 0x1e +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x000000FFL +#define CP_MEC_ME1_UCODE_ADDR__PIPE_SEL_MASK 0xC0000000L +//CP_HYP_MEC1_UCODE_DATA +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_HYP_MEC1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_MEC_ME1_UCODE_DATA +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//CP_HYP_PFP_UCODE_CHKSUM +#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//CP_HYP_ME_UCODE_CHKSUM +#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define CP_HYP_ME_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//CP_HYP_MEC_ME1_UCODE_CHKSUM +#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define CP_HYP_MEC_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//CP_PFP_IC_BASE_LO +#define CP_PFP_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_PFP_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_PFP_IC_BASE_HI +#define CP_PFP_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_PFP_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_PFP_IC_BASE_CNTL +#define CP_PFP_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_PFP_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_PFP_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_PFP_IC_BASE_CNTL__SCOPE__SHIFT 0x1a +#define CP_PFP_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_PFP_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_PFP_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_PFP_IC_BASE_CNTL__SCOPE_MASK 0x0C000000L +//CP_PFP_IC_OP_CNTL +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 +#define CP_PFP_IC_OP_CNTL__PRIME_START_PC__SHIFT 0x3 +#define CP_PFP_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_PFP_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L +#define CP_PFP_IC_OP_CNTL__PRIME_START_PC_MASK 0x00000008L +#define CP_PFP_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_PFP_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_ME_IC_BASE_LO +#define CP_ME_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_ME_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_ME_IC_BASE_HI +#define CP_ME_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_ME_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_ME_IC_BASE_CNTL +#define CP_ME_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_ME_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_ME_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_ME_IC_BASE_CNTL__SCOPE__SHIFT 0x1a +#define CP_ME_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_ME_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_ME_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_ME_IC_BASE_CNTL__SCOPE_MASK 0x0C000000L +//CP_ME_IC_OP_CNTL +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 +#define CP_ME_IC_OP_CNTL__PRIME_START_PC__SHIFT 0x3 +#define CP_ME_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_ME_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define CP_ME_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L +#define CP_ME_IC_OP_CNTL__PRIME_START_PC_MASK 0x00000008L +#define CP_ME_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define CP_ME_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//CP_CPC_IC_BASE_LO +#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_CPC_IC_BASE_HI +#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0x01FFFFFFL +//CP_CPC_IC_BASE_CNTL +#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_CPC_IC_BASE_CNTL__PER_PIPE__SHIFT 0x5 +#define CP_CPC_IC_BASE_CNTL__SCOPE__SHIFT 0x6 +#define CP_CPC_IC_BASE_CNTL__TEMPORAL__SHIFT 0x8 +#define CP_CPC_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_CPC_IC_BASE_CNTL__PER_PIPE_MASK 0x00000020L +#define CP_CPC_IC_BASE_CNTL__SCOPE_MASK 0x000000C0L +#define CP_CPC_IC_BASE_CNTL__TEMPORAL_MASK 0x00000700L +#define CP_CPC_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//CP_MES_IC_BASE_LO +#define CP_MES_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_MES_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_MES_MIBASE_LO +#define CP_MES_MIBASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_MES_MIBASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//CP_MES_IC_BASE_HI +#define CP_MES_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_MES_IC_BASE_HI__IC_BASE_HI_MASK 0x01FFFFFFL +//CP_MES_MIBASE_HI +#define CP_MES_MIBASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_MES_MIBASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//CP_MES_IC_BASE_CNTL +#define CP_MES_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_MES_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define CP_MES_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_MES_IC_BASE_CNTL__SCOPE__SHIFT 0x1a +#define CP_MES_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define CP_MES_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define CP_MES_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +#define CP_MES_IC_BASE_CNTL__SCOPE_MASK 0x0C000000L +//CP_MES_DC_BASE_LO +#define CP_MES_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_MES_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_MES_MDBASE_LO +#define CP_MES_MDBASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MES_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MES_DC_BASE_HI +#define CP_MES_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_MES_DC_BASE_HI__DC_BASE_HI_MASK 0x01FFFFFFL +//CP_MES_MDBASE_HI +#define CP_MES_MDBASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MES_MDBASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MES_MIBOUND_LO +#define CP_MES_MIBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MES_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MES_MIBOUND_HI +#define CP_MES_MIBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MES_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//CP_MES_MDBOUND_LO +#define CP_MES_MDBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MES_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MES_MDBOUND_HI +#define CP_MES_MDBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MES_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//CP_HYP_PFP_UCODE_VERS +#define CP_HYP_PFP_UCODE_VERS__ENGINE__SHIFT 0x0 +#define CP_HYP_PFP_UCODE_VERS__COMMON__SHIFT 0xa +#define CP_HYP_PFP_UCODE_VERS__HEADER__SHIFT 0x14 +#define CP_HYP_PFP_UCODE_VERS__STEP__SHIFT 0x1e +#define CP_HYP_PFP_UCODE_VERS__ENGINE_MASK 0x000003FFL +#define CP_HYP_PFP_UCODE_VERS__COMMON_MASK 0x000FFC00L +#define CP_HYP_PFP_UCODE_VERS__HEADER_MASK 0x3FF00000L +#define CP_HYP_PFP_UCODE_VERS__STEP_MASK 0xC0000000L +//CP_HYP_ME_UCODE_VERS +#define CP_HYP_ME_UCODE_VERS__ENGINE__SHIFT 0x0 +#define CP_HYP_ME_UCODE_VERS__COMMON__SHIFT 0xa +#define CP_HYP_ME_UCODE_VERS__HEADER__SHIFT 0x14 +#define CP_HYP_ME_UCODE_VERS__STEP__SHIFT 0x1e +#define CP_HYP_ME_UCODE_VERS__ENGINE_MASK 0x000003FFL +#define CP_HYP_ME_UCODE_VERS__COMMON_MASK 0x000FFC00L +#define CP_HYP_ME_UCODE_VERS__HEADER_MASK 0x3FF00000L +#define CP_HYP_ME_UCODE_VERS__STEP_MASK 0xC0000000L +//CP_GFX_RS64_DC_BASE0_LO +#define CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_DC_BASE0_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_DC_BASE1_LO +#define CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_GFX_RS64_DC_BASE1_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_GFX_RS64_DC_BASE0_HI +#define CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_DC_BASE0_HI__DC_BASE_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_DC_BASE1_HI +#define CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_GFX_RS64_DC_BASE1_HI__DC_BASE_HI_MASK 0x0000FFFFL +//CP_GFX_RS64_MIBOUND_LO +#define CP_GFX_RS64_MIBOUND_LO__BOUND__SHIFT 0x0 +#define CP_GFX_RS64_MIBOUND_LO__BOUND_MASK 0xFFFFFFFFL +//CP_GFX_RS64_MIBOUND_HI +#define CP_GFX_RS64_MIBOUND_HI__BOUND__SHIFT 0x0 +#define CP_GFX_RS64_MIBOUND_HI__BOUND_MASK 0xFFFFFFFFL +//CP_MEC_DC_BASE_LO +#define CP_MEC_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 +#define CP_MEC_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L +//CP_MEC_MDBASE_LO +#define CP_MEC_MDBASE_LO__BASE_LO__SHIFT 0x10 +#define CP_MEC_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L +//CP_MEC_DC_BASE_HI +#define CP_MEC_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 +#define CP_MEC_DC_BASE_HI__DC_BASE_HI_MASK 0x01FFFFFFL +//CP_MEC_MDBASE_HI +#define CP_MEC_MDBASE_HI__BASE_HI__SHIFT 0x0 +#define CP_MEC_MDBASE_HI__BASE_HI_MASK 0x01FFFFFFL +//CP_MEC_MIBOUND_LO +#define CP_MEC_MIBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MEC_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MEC_MIBOUND_HI +#define CP_MEC_MIBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MEC_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//CP_MEC_MDBOUND_LO +#define CP_MEC_MDBOUND_LO__BOUND_LO__SHIFT 0x0 +#define CP_MEC_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//CP_MEC_MDBOUND_HI +#define CP_MEC_MDBOUND_HI__BOUND_HI__SHIFT 0x0 +#define CP_MEC_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_grbm_hypdec +//GRBM_GFX_INDEX_SR_SELECT +#define GRBM_GFX_INDEX_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_SELECT__VF_PF__SHIFT 0x1f +#define GRBM_GFX_INDEX_SR_SELECT__INDEX_MASK 0x00000007L +#define GRBM_GFX_INDEX_SR_SELECT__VF_PF_MASK 0x80000000L +//GRBM_GFX_INDEX_SR_DATA +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX_SR_DATA__SA_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_INDEX_MASK 0x0000007FL +#define GRBM_GFX_INDEX_SR_DATA__SA_INDEX_MASK 0x00000300L +#define GRBM_GFX_INDEX_SR_DATA__SE_INDEX_MASK 0x000F0000L +#define GRBM_GFX_INDEX_SR_DATA__SA_BROADCAST_WRITES_MASK 0x20000000L +#define GRBM_GFX_INDEX_SR_DATA__INSTANCE_BROADCAST_WRITES_MASK 0x40000000L +#define GRBM_GFX_INDEX_SR_DATA__SE_BROADCAST_WRITES_MASK 0x80000000L +//GRBM_GFX_CNTL_SR_SELECT +#define GRBM_GFX_CNTL_SR_SELECT__INDEX__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_SELECT__VF_PF__SHIFT 0x1f +#define GRBM_GFX_CNTL_SR_SELECT__INDEX_MASK 0x00000007L +#define GRBM_GFX_CNTL_SR_SELECT__VF_PF_MASK 0x80000000L +//GRBM_GFX_CNTL_SR_DATA +#define GRBM_GFX_CNTL_SR_DATA__PIPEID__SHIFT 0x0 +#define GRBM_GFX_CNTL_SR_DATA__MEID__SHIFT 0x2 +#define GRBM_GFX_CNTL_SR_DATA__VMID__SHIFT 0x4 +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID__SHIFT 0x8 +#define GRBM_GFX_CNTL_SR_DATA__CTXID__SHIFT 0xb +#define GRBM_GFX_CNTL_SR_DATA__PIPEID_MASK 0x00000003L +#define GRBM_GFX_CNTL_SR_DATA__MEID_MASK 0x0000000CL +#define GRBM_GFX_CNTL_SR_DATA__VMID_MASK 0x000000F0L +#define GRBM_GFX_CNTL_SR_DATA__QUEUEID_MASK 0x00000700L +#define GRBM_GFX_CNTL_SR_DATA__CTXID_MASK 0x00003800L +//GC_IH_COOKIE_0_PTR_HIGH +#define GC_IH_COOKIE_0_PTR_HIGH__ADDR__SHIFT 0x0 +#define GC_IH_COOKIE_0_PTR_HIGH__ADDR_MASK 0x0000FFFFL +//GC_IH_COOKIE_0_PTR +#define GC_IH_COOKIE_0_PTR__ADDR__SHIFT 0x0 +#define GC_IH_COOKIE_0_PTR__ADDR_MASK 0xFFFFFFFFL +//GRBM_SE_REMAP_CNTL +#define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN__SHIFT 0x0 +#define GRBM_SE_REMAP_CNTL__SE0_REMAP__SHIFT 0x1 +#define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN__SHIFT 0x4 +#define GRBM_SE_REMAP_CNTL__SE1_REMAP__SHIFT 0x5 +#define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN__SHIFT 0x8 +#define GRBM_SE_REMAP_CNTL__SE2_REMAP__SHIFT 0x9 +#define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN__SHIFT 0xc +#define GRBM_SE_REMAP_CNTL__SE3_REMAP__SHIFT 0xd +#define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN__SHIFT 0x10 +#define GRBM_SE_REMAP_CNTL__SE4_REMAP__SHIFT 0x11 +#define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN__SHIFT 0x14 +#define GRBM_SE_REMAP_CNTL__SE5_REMAP__SHIFT 0x15 +#define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN__SHIFT 0x18 +#define GRBM_SE_REMAP_CNTL__SE6_REMAP__SHIFT 0x19 +#define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN__SHIFT 0x1c +#define GRBM_SE_REMAP_CNTL__SE7_REMAP__SHIFT 0x1d +#define GRBM_SE_REMAP_CNTL__SE0_REMAP_EN_MASK 0x00000001L +#define GRBM_SE_REMAP_CNTL__SE0_REMAP_MASK 0x0000000EL +#define GRBM_SE_REMAP_CNTL__SE1_REMAP_EN_MASK 0x00000010L +#define GRBM_SE_REMAP_CNTL__SE1_REMAP_MASK 0x000000E0L +#define GRBM_SE_REMAP_CNTL__SE2_REMAP_EN_MASK 0x00000100L +#define GRBM_SE_REMAP_CNTL__SE2_REMAP_MASK 0x00000E00L +#define GRBM_SE_REMAP_CNTL__SE3_REMAP_EN_MASK 0x00001000L +#define GRBM_SE_REMAP_CNTL__SE3_REMAP_MASK 0x0000E000L +#define GRBM_SE_REMAP_CNTL__SE4_REMAP_EN_MASK 0x00010000L +#define GRBM_SE_REMAP_CNTL__SE4_REMAP_MASK 0x000E0000L +#define GRBM_SE_REMAP_CNTL__SE5_REMAP_EN_MASK 0x00100000L +#define GRBM_SE_REMAP_CNTL__SE5_REMAP_MASK 0x00E00000L +#define GRBM_SE_REMAP_CNTL__SE6_REMAP_EN_MASK 0x01000000L +#define GRBM_SE_REMAP_CNTL__SE6_REMAP_MASK 0x0E000000L +#define GRBM_SE_REMAP_CNTL__SE7_REMAP_EN_MASK 0x10000000L +#define GRBM_SE_REMAP_CNTL__SE7_REMAP_MASK 0xE0000000L +//GRBM_SA_REMAP_CNTL +#define GRBM_SA_REMAP_CNTL__SE0_SA_REMAP__SHIFT 0x0 +#define GRBM_SA_REMAP_CNTL__SE1_SA_REMAP__SHIFT 0x2 +#define GRBM_SA_REMAP_CNTL__SE2_SA_REMAP__SHIFT 0x4 +#define GRBM_SA_REMAP_CNTL__SE3_SA_REMAP__SHIFT 0x6 +#define GRBM_SA_REMAP_CNTL__SE4_SA_REMAP__SHIFT 0x8 +#define GRBM_SA_REMAP_CNTL__SE5_SA_REMAP__SHIFT 0xa +#define GRBM_SA_REMAP_CNTL__SE6_SA_REMAP__SHIFT 0xc +#define GRBM_SA_REMAP_CNTL__SE7_SA_REMAP__SHIFT 0xe +#define GRBM_SA_REMAP_CNTL__SE0_SA_REMAP_MASK 0x00000003L +#define GRBM_SA_REMAP_CNTL__SE1_SA_REMAP_MASK 0x0000000CL +#define GRBM_SA_REMAP_CNTL__SE2_SA_REMAP_MASK 0x00000030L +#define GRBM_SA_REMAP_CNTL__SE3_SA_REMAP_MASK 0x000000C0L +#define GRBM_SA_REMAP_CNTL__SE4_SA_REMAP_MASK 0x00000300L +#define GRBM_SA_REMAP_CNTL__SE5_SA_REMAP_MASK 0x00000C00L +#define GRBM_SA_REMAP_CNTL__SE6_SA_REMAP_MASK 0x00003000L +#define GRBM_SA_REMAP_CNTL__SE7_SA_REMAP_MASK 0x0000C000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcdec +//RLC_CNTL +#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 +#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 +#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 +#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 +#define RLC_CNTL__POISON_INTR_ON_IH_COOKIE_OR_IH_GASKET__SHIFT 0x4 +#define RLC_CNTL__POISON_INTERRUPT_TO_PF__SHIFT 0x5 +#define RLC_CNTL__RESERVED__SHIFT 0x6 +#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x00000001L +#define RLC_CNTL__FORCE_RETRY_MASK 0x00000002L +#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x00000004L +#define RLC_CNTL__RLC_STEP_F32_MASK 0x00000008L +#define RLC_CNTL__POISON_INTR_ON_IH_COOKIE_OR_IH_GASKET_MASK 0x00000010L +#define RLC_CNTL__POISON_INTERRUPT_TO_PF_MASK 0x00000020L +#define RLC_CNTL__RESERVED_MASK 0xFFFFFFC0L +//RLC_F32_UCODE_VERSION +#define RLC_F32_UCODE_VERSION__THREAD0_VERSION__SHIFT 0x0 +#define RLC_F32_UCODE_VERSION__THREAD1_VERSION__SHIFT 0xa +#define RLC_F32_UCODE_VERSION__THREAD2_VERSION__SHIFT 0x14 +#define RLC_F32_UCODE_VERSION__THREAD0_VERSION_MASK 0x000003FFL +#define RLC_F32_UCODE_VERSION__THREAD1_VERSION_MASK 0x000FFC00L +#define RLC_F32_UCODE_VERSION__THREAD2_VERSION_MASK 0x3FF00000L +//RLC_STAT +#define RLC_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x1 +#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x2 +#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x3 +#define RLC_STAT__MC_BUSY__SHIFT 0x4 +#define RLC_STAT__RLC_THREAD_0_BUSY__SHIFT 0x5 +#define RLC_STAT__RLC_THREAD_1_BUSY__SHIFT 0x6 +#define RLC_STAT__RLC_THREAD_2_BUSY__SHIFT 0x7 +#define RLC_STAT__RLC_DMA_BUSY__SHIFT 0x8 +#define RLC_STAT__RESERVED__SHIFT 0x9 +#define RLC_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_STAT__RLC_SRM_BUSY_MASK 0x00000002L +#define RLC_STAT__RLC_GPM_BUSY_MASK 0x00000004L +#define RLC_STAT__RLC_SPM_BUSY_MASK 0x00000008L +#define RLC_STAT__MC_BUSY_MASK 0x00000010L +#define RLC_STAT__RLC_THREAD_0_BUSY_MASK 0x00000020L +#define RLC_STAT__RLC_THREAD_1_BUSY_MASK 0x00000040L +#define RLC_STAT__RLC_THREAD_2_BUSY_MASK 0x00000080L +#define RLC_STAT__RLC_DMA_BUSY_MASK 0x00000100L +#define RLC_STAT__RESERVED_MASK 0xFFFFFE00L +//RLC_ACTIVE_MASK +#define RLC_ACTIVE_MASK__SE__SHIFT 0x0 +#define RLC_ACTIVE_MASK__SE_MASK 0x000000FFL +//RLC_GFX_SE_STATUS +#define RLC_GFX_SE_STATUS__SQG_TTRACE_HALT__SHIFT 0x0 +#define RLC_GFX_SE_STATUS__SQG_TTRACE_HALT_MASK 0x00000003L +//RLC_REFCLOCK_TIMESTAMP_LSB +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_LSB__TIMESTAMP_LSB_MASK 0xFFFFFFFFL +//RLC_REFCLOCK_TIMESTAMP_MSB +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB__SHIFT 0x0 +#define RLC_REFCLOCK_TIMESTAMP_MSB__TIMESTAMP_MSB_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_0 +#define RLC_GPM_TIMER_INT_0__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_0__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_1 +#define RLC_GPM_TIMER_INT_1__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_1__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_2 +#define RLC_GPM_TIMER_INT_2__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_2__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_3 +#define RLC_GPM_TIMER_INT_3__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_3__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_INT_4 +#define RLC_GPM_TIMER_INT_4__TIMER__SHIFT 0x0 +#define RLC_GPM_TIMER_INT_4__TIMER_MASK 0xFFFFFFFFL +//RLC_GPM_TIMER_CTRL +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN__SHIFT 0x0 +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN__SHIFT 0x1 +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN__SHIFT 0x2 +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN__SHIFT 0x3 +#define RLC_GPM_TIMER_CTRL__TIMER_4_EN__SHIFT 0x4 +#define RLC_GPM_TIMER_CTRL__RESERVED_1__SHIFT 0x5 +#define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM__SHIFT 0x8 +#define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM__SHIFT 0x9 +#define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM__SHIFT 0xa +#define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM__SHIFT 0xb +#define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM__SHIFT 0xc +#define RLC_GPM_TIMER_CTRL__RESERVED_2__SHIFT 0xd +#define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR__SHIFT 0x10 +#define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR__SHIFT 0x11 +#define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR__SHIFT 0x12 +#define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR__SHIFT 0x13 +#define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR__SHIFT 0x14 +#define RLC_GPM_TIMER_CTRL__RESERVED__SHIFT 0x15 +#define RLC_GPM_TIMER_CTRL__TIMER_0_EN_MASK 0x00000001L +#define RLC_GPM_TIMER_CTRL__TIMER_1_EN_MASK 0x00000002L +#define RLC_GPM_TIMER_CTRL__TIMER_2_EN_MASK 0x00000004L +#define RLC_GPM_TIMER_CTRL__TIMER_3_EN_MASK 0x00000008L +#define RLC_GPM_TIMER_CTRL__TIMER_4_EN_MASK 0x00000010L +#define RLC_GPM_TIMER_CTRL__RESERVED_1_MASK 0x000000E0L +#define RLC_GPM_TIMER_CTRL__TIMER_0_AUTO_REARM_MASK 0x00000100L +#define RLC_GPM_TIMER_CTRL__TIMER_1_AUTO_REARM_MASK 0x00000200L +#define RLC_GPM_TIMER_CTRL__TIMER_2_AUTO_REARM_MASK 0x00000400L +#define RLC_GPM_TIMER_CTRL__TIMER_3_AUTO_REARM_MASK 0x00000800L +#define RLC_GPM_TIMER_CTRL__TIMER_4_AUTO_REARM_MASK 0x00001000L +#define RLC_GPM_TIMER_CTRL__RESERVED_2_MASK 0x0000E000L +#define RLC_GPM_TIMER_CTRL__TIMER_0_INT_CLEAR_MASK 0x00010000L +#define RLC_GPM_TIMER_CTRL__TIMER_1_INT_CLEAR_MASK 0x00020000L +#define RLC_GPM_TIMER_CTRL__TIMER_2_INT_CLEAR_MASK 0x00040000L +#define RLC_GPM_TIMER_CTRL__TIMER_3_INT_CLEAR_MASK 0x00080000L +#define RLC_GPM_TIMER_CTRL__TIMER_4_INT_CLEAR_MASK 0x00100000L +#define RLC_GPM_TIMER_CTRL__RESERVED_MASK 0xFFE00000L +//RLC_GPM_TIMER_STAT +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT__SHIFT 0x0 +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT__SHIFT 0x1 +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT__SHIFT 0x2 +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT__SHIFT 0x3 +#define RLC_GPM_TIMER_STAT__TIMER_4_STAT__SHIFT 0x4 +#define RLC_GPM_TIMER_STAT__RESERVED_1__SHIFT 0x5 +#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC__SHIFT 0x8 +#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC__SHIFT 0x9 +#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC__SHIFT 0xa +#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC__SHIFT 0xb +#define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC__SHIFT 0xc +#define RLC_GPM_TIMER_STAT__RESERVED_2__SHIFT 0xd +#define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC__SHIFT 0x10 +#define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC__SHIFT 0x11 +#define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC__SHIFT 0x12 +#define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC__SHIFT 0x13 +#define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC__SHIFT 0x14 +#define RLC_GPM_TIMER_STAT__RESERVED__SHIFT 0x15 +#define RLC_GPM_TIMER_STAT__TIMER_0_STAT_MASK 0x00000001L +#define RLC_GPM_TIMER_STAT__TIMER_1_STAT_MASK 0x00000002L +#define RLC_GPM_TIMER_STAT__TIMER_2_STAT_MASK 0x00000004L +#define RLC_GPM_TIMER_STAT__TIMER_3_STAT_MASK 0x00000008L +#define RLC_GPM_TIMER_STAT__TIMER_4_STAT_MASK 0x00000010L +#define RLC_GPM_TIMER_STAT__RESERVED_1_MASK 0x000000E0L +#define RLC_GPM_TIMER_STAT__TIMER_0_ENABLE_SYNC_MASK 0x00000100L +#define RLC_GPM_TIMER_STAT__TIMER_1_ENABLE_SYNC_MASK 0x00000200L +#define RLC_GPM_TIMER_STAT__TIMER_2_ENABLE_SYNC_MASK 0x00000400L +#define RLC_GPM_TIMER_STAT__TIMER_3_ENABLE_SYNC_MASK 0x00000800L +#define RLC_GPM_TIMER_STAT__TIMER_4_ENABLE_SYNC_MASK 0x00001000L +#define RLC_GPM_TIMER_STAT__RESERVED_2_MASK 0x0000E000L +#define RLC_GPM_TIMER_STAT__TIMER_0_AUTO_REARM_SYNC_MASK 0x00010000L +#define RLC_GPM_TIMER_STAT__TIMER_1_AUTO_REARM_SYNC_MASK 0x00020000L +#define RLC_GPM_TIMER_STAT__TIMER_2_AUTO_REARM_SYNC_MASK 0x00040000L +#define RLC_GPM_TIMER_STAT__TIMER_3_AUTO_REARM_SYNC_MASK 0x00080000L +#define RLC_GPM_TIMER_STAT__TIMER_4_AUTO_REARM_SYNC_MASK 0x00100000L +#define RLC_GPM_TIMER_STAT__RESERVED_MASK 0xFFE00000L +//RLC_GPM_LEGACY_INT_STAT +#define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED__SHIFT 0x0 +#define RLC_GPM_LEGACY_INT_STAT__RESERVED__SHIFT 0x1 +#define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED__SHIFT 0x2 +#define RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED__SHIFT 0x3 +#define RLC_GPM_LEGACY_INT_STAT__STORE_LOAD_TIMER3_EXPIRED_T0__SHIFT 0x4 +#define RLC_GPM_LEGACY_INT_STAT__SPP_PVT_INT_CHANGED_MASK 0x00000001L +#define RLC_GPM_LEGACY_INT_STAT__RESERVED_MASK 0x00000002L +#define RLC_GPM_LEGACY_INT_STAT__RLC_EOF_INT_CHANGED_MASK 0x00000004L +#define RLC_GPM_LEGACY_INT_STAT__RLC_PG_CNTL_CHANGED_MASK 0x00000008L +#define RLC_GPM_LEGACY_INT_STAT__STORE_LOAD_TIMER3_EXPIRED_T0_MASK 0x00000010L +//RLC_GPM_LEGACY_INT_CLEAR +#define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED__SHIFT 0x0 +#define RLC_GPM_LEGACY_INT_CLEAR__RESERVED__SHIFT 0x1 +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED__SHIFT 0x2 +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED__SHIFT 0x3 +#define RLC_GPM_LEGACY_INT_CLEAR__RESERVED_4__SHIFT 0x4 +#define RLC_GPM_LEGACY_INT_CLEAR__SPP_PVT_INT_CHANGED_MASK 0x00000001L +#define RLC_GPM_LEGACY_INT_CLEAR__RESERVED_MASK 0x00000002L +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_EOF_INT_CHANGED_MASK 0x00000004L +#define RLC_GPM_LEGACY_INT_CLEAR__RLC_PG_CNTL_CHANGED_MASK 0x00000008L +#define RLC_GPM_LEGACY_INT_CLEAR__RESERVED_4_MASK 0x00000010L +//RLC_INT_STAT +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID__SHIFT 0x0 +#define RLC_INT_STAT__CP_RLC_INT_PENDING__SHIFT 0x8 +#define RLC_INT_STAT__RESERVED__SHIFT 0x9 +#define RLC_INT_STAT__LAST_CP_RLC_INT_ID_MASK 0x000000FFL +#define RLC_INT_STAT__CP_RLC_INT_PENDING_MASK 0x00000100L +#define RLC_INT_STAT__RESERVED_MASK 0xFFFFFE00L +//RLC_MGCG_CTRL +#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 +#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 +#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 +#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 +#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 +#define RLC_MGCG_CTRL__SPARE__SHIFT 0xf +#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x00000001L +#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x00000002L +#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x00000004L +#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x00000078L +#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x00007F80L +#define RLC_MGCG_CTRL__SPARE_MASK 0xFFFF8000L +//RLC_MCA_DF_RASINTRCTRL_REG_CTRL +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VMID__SHIFT 0x0 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_SRCID__SHIFT 0x4 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_CTXID__SHIFT 0x8 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_ME_ID__SHIFT 0xb +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_PIPE_ID__SHIFT 0xd +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_QUEUE_ID__SHIFT 0xf +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_TMZ__SHIFT 0x12 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VF__SHIFT 0x13 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VFID__SHIFT 0x14 +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VMID_MASK 0x0000000FL +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_SRCID_MASK 0x000000F0L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_CTXID_MASK 0x00000700L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_ME_ID_MASK 0x00001800L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_PIPE_ID_MASK 0x00006000L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_QUEUE_ID_MASK 0x00038000L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_TMZ_MASK 0x00040000L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VF_MASK 0x00080000L +#define RLC_MCA_DF_RASINTRCTRL_REG_CTRL__MCA_GRBM_WR_VFID_MASK 0x01F00000L +//RLC_JUMP_TABLE_RESTORE +#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 +#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_2 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE__SHIFT 0x10 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0x000000FFL +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY_2__PERWGP_TIMEOUT_VALUE_MASK 0xFFFF0000L +//RLC_GPU_CLOCK_COUNT_LSB +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xFFFFFFFEL +//RLC_UCODE_CNTL +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xFFFFFFFFL +//RLC_GPM_THREAD_RESET +#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 +#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 +#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 +#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 +#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x00000001L +#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x00000002L +#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x00000004L +#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x00000008L +#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xFFFFFFF0L +//RLC_GPM_CP_DMA_COMPLETE_T0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T0__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T0__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPM_CP_DMA_COMPLETE_T1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA__SHIFT 0x0 +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED__SHIFT 0x1 +#define RLC_GPM_CP_DMA_COMPLETE_T1__DATA_MASK 0x00000001L +#define RLC_GPM_CP_DMA_COMPLETE_T1__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPM_THREAD_INVALIDATE_CACHE +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE__SHIFT 0x0 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE__SHIFT 0x1 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE__SHIFT 0x2 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE__SHIFT 0x3 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD0_INVALIDATE_CACHE_MASK 0x00000001L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD1_INVALIDATE_CACHE_MASK 0x00000002L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD2_INVALIDATE_CACHE_MASK 0x00000004L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__THREAD3_INVALIDATE_CACHE_MASK 0x00000008L +#define RLC_GPM_THREAD_INVALIDATE_CACHE__RESERVED_MASK 0xFFFFFFF0L +//RLC_MCA_DF_RASINTRCTRL_REG_LO +#define RLC_MCA_DF_RASINTRCTRL_REG_LO__ADDR__SHIFT 0x0 +#define RLC_MCA_DF_RASINTRCTRL_REG_LO__APERTURE__SHIFT 0x14 +#define RLC_MCA_DF_RASINTRCTRL_REG_LO__ADDR_MASK 0x000FFFFFL +#define RLC_MCA_DF_RASINTRCTRL_REG_LO__APERTURE_MASK 0xFFF00000L +//RLC_MCA_DF_RASINTRCTRL_REG_HI +#define RLC_MCA_DF_RASINTRCTRL_REG_HI__MCM_ADDR__SHIFT 0x0 +#define RLC_MCA_DF_RASINTRCTRL_REG_HI__MCM_ADDR_MASK 0x0000FFFFL +//RLC_MCA_INTR_CTRL +#define RLC_MCA_INTR_CTRL__MCA_INTR_HYSTERISIS_CNTR__SHIFT 0x0 +#define RLC_MCA_INTR_CTRL__MCA_INTR_BY_RLC_FW__SHIFT 0x10 +#define RLC_MCA_INTR_CTRL__MCA_INTR_HYSTERISIS_CNTR_MASK 0x0000FFFFL +#define RLC_MCA_INTR_CTRL__MCA_INTR_BY_RLC_FW_MASK 0x00010000L +//RLC_MCA_INTR_INFO +#define RLC_MCA_INTR_INFO__MCA_INTREQ_INFO__SHIFT 0x0 +#define RLC_MCA_INTR_INFO__MCA_FatalOut_INFO__SHIFT 0x8 +#define RLC_MCA_INTR_INFO__MCA_MASTERCOREID_REG_OFFSET__SHIFT 0x10 +#define RLC_MCA_INTR_INFO__MCA_INTERRUPT_SERVICED_BY_RLC_FW__SHIFT 0x1f +#define RLC_MCA_INTR_INFO__MCA_INTREQ_INFO_MASK 0x0000000FL +#define RLC_MCA_INTR_INFO__MCA_FatalOut_INFO_MASK 0x00000100L +#define RLC_MCA_INTR_INFO__MCA_MASTERCOREID_REG_OFFSET_MASK 0x01FF0000L +#define RLC_MCA_INTR_INFO__MCA_INTERRUPT_SERVICED_BY_RLC_FW_MASK 0x80000000L +//RLC_CLK_COUNT_GFXCLK_LSB +#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_GFXCLK_LSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_GFXCLK_MSB +#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_GFXCLK_MSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_REFCLK_LSB +#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_REFCLK_LSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_REFCLK_MSB +#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER__SHIFT 0x0 +#define RLC_CLK_COUNT_REFCLK_MSB__COUNTER_MASK 0xFFFFFFFFL +//RLC_CLK_COUNT_CTRL +#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN__SHIFT 0x0 +#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET__SHIFT 0x1 +#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE__SHIFT 0x2 +#define RLC_CLK_COUNT_CTRL__REFCLK_RUN__SHIFT 0x3 +#define RLC_CLK_COUNT_CTRL__REFCLK_RESET__SHIFT 0x4 +#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE__SHIFT 0x5 +#define RLC_CLK_COUNT_CTRL__GFXCLK_RUN_MASK 0x00000001L +#define RLC_CLK_COUNT_CTRL__GFXCLK_RESET_MASK 0x00000002L +#define RLC_CLK_COUNT_CTRL__GFXCLK_SAMPLE_MASK 0x00000004L +#define RLC_CLK_COUNT_CTRL__REFCLK_RUN_MASK 0x00000008L +#define RLC_CLK_COUNT_CTRL__REFCLK_RESET_MASK 0x00000010L +#define RLC_CLK_COUNT_CTRL__REFCLK_SAMPLE_MASK 0x00000020L +//RLC_CLK_COUNT_STAT +#define RLC_CLK_COUNT_STAT__GFXCLK_VALID__SHIFT 0x0 +#define RLC_CLK_COUNT_STAT__REFCLK_VALID__SHIFT 0x1 +#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC__SHIFT 0x2 +#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC__SHIFT 0x3 +#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC__SHIFT 0x4 +#define RLC_CLK_COUNT_STAT__RESERVED__SHIFT 0x5 +#define RLC_CLK_COUNT_STAT__GFXCLK_VALID_MASK 0x00000001L +#define RLC_CLK_COUNT_STAT__REFCLK_VALID_MASK 0x00000002L +#define RLC_CLK_COUNT_STAT__REFCLK_RUN_RESYNC_MASK 0x00000004L +#define RLC_CLK_COUNT_STAT__REFCLK_RESET_RESYNC_MASK 0x00000008L +#define RLC_CLK_COUNT_STAT__REFCLK_SAMPLE_RESYNC_MASK 0x00000010L +#define RLC_CLK_COUNT_STAT__RESERVED_MASK 0xFFFFFFE0L +//RLC_RLCG_DOORBELL_CNTL +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 +#define RLC_RLCG_DOORBELL_CNTL__RESERVED__SHIFT 0x8 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 +#define RLC_RLCG_DOORBELL_CNTL__RESERVED_31_22__SHIFT 0x16 +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L +#define RLC_RLCG_DOORBELL_CNTL__RESERVED_MASK 0x0000FF00L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L +#define RLC_RLCG_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L +#define RLC_RLCG_DOORBELL_CNTL__RESERVED_31_22_MASK 0xFFC00000L +//RLC_RLCG_DOORBELL_STAT +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L +#define RLC_RLCG_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L +//RLC_RLCG_DOORBELL_0_DATA_LO +#define RLC_RLCG_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_0_DATA_HI +#define RLC_RLCG_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_1_DATA_LO +#define RLC_RLCG_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_1_DATA_HI +#define RLC_RLCG_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_2_DATA_LO +#define RLC_RLCG_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_2_DATA_HI +#define RLC_RLCG_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_3_DATA_LO +#define RLC_RLCG_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCG_DOORBELL_3_DATA_HI +#define RLC_RLCG_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_32_RES_SEL +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x0000003FL +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xFFFFFFC0L +//RLC_GPU_CLOCK_32 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xFFFFFFFFL +//RLC_PG_CNTL +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 +#define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE__SHIFT 0x2 +#define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE__SHIFT 0x3 +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 +#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 +#define RLC_PG_CNTL__MEM_DS_DISABLE__SHIFT 0xd +#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe +#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 +#define RLC_PG_CNTL__RESERVED1__SHIFT 0x13 +#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable__SHIFT 0x15 +#define RLC_PG_CNTL__RESERVED2__SHIFT 0x16 +#define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE__SHIFT 0x17 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x00000001L +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x00000002L +#define RLC_PG_CNTL__DYN_PER_WGP_PG_ENABLE_MASK 0x00000004L +#define RLC_PG_CNTL__STATIC_PER_WGP_PG_ENABLE_MASK 0x00000008L +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x00000010L +#define RLC_PG_CNTL__RESERVED_MASK 0x00001FE0L +#define RLC_PG_CNTL__MEM_DS_DISABLE_MASK 0x00002000L +#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x00004000L +#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x00008000L +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x00010000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x00020000L +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x00040000L +#define RLC_PG_CNTL__RESERVED1_MASK 0x00180000L +#define RLC_PG_CNTL__Ultra_Low_Voltage_Enable_MASK 0x00200000L +#define RLC_PG_CNTL__RESERVED2_MASK 0x00400000L +#define RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK 0x00800000L +//RLC_GPM_THREAD_PRIORITY +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0x000000FFL +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0x0000FF00L +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0x00FF0000L +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xFF000000L +//RLC_GPM_THREAD_ENABLE +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 +#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x00000001L +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x00000002L +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x00000004L +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x00000008L +#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xFFFFFFF0L +//RLC_RLCG_DOORBELL_RANGE +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 +#define RLC_RLCG_DOORBELL_RANGE__RESERVED_15_12__SHIFT 0xc +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 +#define RLC_RLCG_DOORBELL_RANGE__RESERVED_31_28__SHIFT 0x1c +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L +#define RLC_RLCG_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL +#define RLC_RLCG_DOORBELL_RANGE__RESERVED_15_12_MASK 0x0000F000L +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L +#define RLC_RLCG_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L +#define RLC_RLCG_DOORBELL_RANGE__RESERVED_31_28_MASK 0xF0000000L +//RLC_CGTT_MGCG_OVERRIDE +#define RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE__SHIFT 0x0 +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE__SHIFT 0x1 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE__SHIFT 0x2 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE__SHIFT 0x3 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE__SHIFT 0x4 +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE__SHIFT 0x5 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE__SHIFT 0x6 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE__SHIFT 0x7 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE__SHIFT 0x8 +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 +#define RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE__SHIFT 0xa +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_11__SHIFT 0xb +#define RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK 0x00000001L +#define RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK 0x00000002L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK 0x00000004L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK 0x00000008L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK 0x00000010L +#define RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 0x00000020L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK 0x00000040L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK 0x00000080L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK 0x00000100L +#define RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L +#define RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK 0x00000400L +#define RLC_CGTT_MGCG_OVERRIDE__RESERVED_31_11_MASK 0xFFFFF800L +//RLC_CGCG_CGLS_CTRL +#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f +#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0x000000FCL +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x07FFFF00L +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x08000000L +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000L +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000L +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000L +//RLC_CGCG_RAMP_CTRL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0x0000000FL +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0x000000F0L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0x00000F00L +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0x0000F000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0x0FFF0000L +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xF0000000L +//RLC_DYN_PG_STATUS +#define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 +#define RLC_DYN_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_DYN_PG_REQUEST +#define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK__SHIFT 0x0 +#define RLC_DYN_PG_REQUEST__PG_REQUEST_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_PG_DELAY +#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 +#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0x000000FFL +#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0x0000FF00L +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0x00FF0000L +#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xFF000000L +//RLC_CGCG_CGLS_CTRL_2 +#define RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL_2__RESERVED__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL_2__CANE_STAT_BUSY_MASK_MASK 0x00000001L +#define RLC_CGCG_CGLS_CTRL_2__RESERVED_MASK 0xFFFFFFFEL +//RLC_PG_ALWAYS_ON_WGP_MASK +#define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK__SHIFT 0x0 +#define RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_MAX_PG_WGP +#define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP__SHIFT 0x0 +#define RLC_MAX_PG_WGP__SPARE__SHIFT 0x8 +#define RLC_MAX_PG_WGP__MAX_POWERED_UP_WGP_MASK 0x000000FFL +#define RLC_MAX_PG_WGP__SPARE_MASK 0xFFFFFF00L +//RLC_AUTO_PG_CTRL +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x00000001L +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x00000002L +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x00000004L +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x0007FFF8L +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xFFF80000L +//RLC_SERDES_RD_INDEX +#define RLC_SERDES_RD_INDEX__DATA_REG_ID__SHIFT 0x0 +#define RLC_SERDES_RD_INDEX__SPARE__SHIFT 0x2 +#define RLC_SERDES_RD_INDEX__DATA_REG_ID_MASK 0x00000003L +#define RLC_SERDES_RD_INDEX__SPARE_MASK 0xFFFFFFFCL +//RLC_SERDES_RD_DATA_0 +#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_1 +#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_2 +#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_RD_DATA_3 +#define RLC_SERDES_RD_DATA_3__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_3__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_MASK +#define RLC_SERDES_MASK__GC_CENTER_HUB_0__SHIFT 0x0 +#define RLC_SERDES_MASK__GC_CENTER_HUB_1__SHIFT 0x1 +#define RLC_SERDES_MASK__GC_CENTER_HUB_0_MASK 0x00000001L +#define RLC_SERDES_MASK__GC_CENTER_HUB_1_MASK 0x00000002L +//RLC_SERDES_CTRL +#define RLC_SERDES_CTRL__BPM_BROADCAST__SHIFT 0x0 +#define RLC_SERDES_CTRL__BPM_REG_WRITE__SHIFT 0x1 +#define RLC_SERDES_CTRL__BPM_LONG_CMD__SHIFT 0x2 +#define RLC_SERDES_CTRL__BPM_ADDR__SHIFT 0x4 +#define RLC_SERDES_CTRL__REG_ADDR__SHIFT 0x10 +#define RLC_SERDES_CTRL__BPM_BROADCAST_MASK 0x000001L +#define RLC_SERDES_CTRL__BPM_REG_WRITE_MASK 0x000002L +#define RLC_SERDES_CTRL__BPM_LONG_CMD_MASK 0x000004L +#define RLC_SERDES_CTRL__BPM_ADDR_MASK 0x007FF0L +#define RLC_SERDES_CTRL__REG_ADDR_MASK 0xFF0000L +//RLC_SERDES_DATA +#define RLC_SERDES_DATA__DATA__SHIFT 0x0 +#define RLC_SERDES_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SERDES_BUSY +#define RLC_SERDES_BUSY__GC_CENTER_HUB_0__SHIFT 0x0 +#define RLC_SERDES_BUSY__GC_CENTER_HUB_1__SHIFT 0x1 +#define RLC_SERDES_BUSY__RESERVED__SHIFT 0x2 +#define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY__SHIFT 0x1e +#define RLC_SERDES_BUSY__RD_PENDING__SHIFT 0x1f +#define RLC_SERDES_BUSY__GC_CENTER_HUB_0_MASK 0x00000001L +#define RLC_SERDES_BUSY__GC_CENTER_HUB_1_MASK 0x00000002L +#define RLC_SERDES_BUSY__RESERVED_MASK 0x3FFFFFFCL +#define RLC_SERDES_BUSY__RD_FIFO_NOT_EMPTY_MASK 0x40000000L +#define RLC_SERDES_BUSY__RD_PENDING_MASK 0x80000000L +//RLC_GPM_GENERAL_0 +#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_0__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_1 +#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_1__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_2 +#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_3 +#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_3__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_4 +#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_4__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_5 +#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_5__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_6 +#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_6__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_7 +#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_7__DATA_MASK 0xFFFFFFFFL +//RLC_STATIC_PG_STATUS +#define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK__SHIFT 0x0 +#define RLC_STATIC_PG_STATUS__PG_STATUS_WGP_MASK_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_16 +#define RLC_GPM_GENERAL_16__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_16__DATA_MASK 0xFFFFFFFFL +//RLC_PG_DELAY_3 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xFFFFFFFFL +//RLC_GPR_REG1 +#define RLC_GPR_REG1__DATA__SHIFT 0x0 +#define RLC_GPR_REG1__DATA_MASK 0xFFFFFFFFL +//RLC_GPR_REG2 +#define RLC_GPR_REG2__DATA__SHIFT 0x0 +#define RLC_GPR_REG2__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_INT_DISABLE_TH0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT__SHIFT 0x0 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE_INT_MASK 0xFFFFFFFFL +//RLC_GPM_LEGACY_INT_DISABLE +#define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED__SHIFT 0x0 +#define RLC_GPM_LEGACY_INT_DISABLE__RESERVED__SHIFT 0x1 +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED__SHIFT 0x2 +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED__SHIFT 0x3 +#define RLC_GPM_LEGACY_INT_DISABLE__STORE_LOAD_TIMER3_EXPIRED_T0__SHIFT 0x4 +#define RLC_GPM_LEGACY_INT_DISABLE__SPP_PVT_INT_CHANGED_MASK 0x00000001L +#define RLC_GPM_LEGACY_INT_DISABLE__RESERVED_MASK 0x00000002L +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_EOF_INT_CHANGED_MASK 0x00000004L +#define RLC_GPM_LEGACY_INT_DISABLE__RLC_PG_CNTL_CHANGED_MASK 0x00000008L +#define RLC_GPM_LEGACY_INT_DISABLE__STORE_LOAD_TIMER3_EXPIRED_T0_MASK 0x00000010L +//RLC_GPM_INT_FORCE_TH0 +#define RLC_GPM_INT_FORCE_TH0__FORCE_INT__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH0__FORCE_INT_MASK 0xFFFFFFFFL +//RLC_SRM_CNTL +#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 +#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 +#define RLC_SRM_CNTL__SRM_GPM_FIFO_RESET__SHIFT 0x2 +#define RLC_SRM_CNTL__RESERVED__SHIFT 0x3 +#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x00000001L +#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x00000002L +#define RLC_SRM_CNTL__SRM_GPM_FIFO_RESET_MASK 0x00000004L +#define RLC_SRM_CNTL__RESERVED_MASK 0xFFFFFFF8L +//RLC_SRM_GPM_COMMAND_STATUS +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_OVERFLOW__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x3 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_OVERFLOW_MASK 0x00000004L +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xFFFFFFF8L +//RLC_SRM_INDEX_CNTL_ADDR_0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_1 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_2 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_3 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_4 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_5 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_6 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_ADDR_7 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0x0003FFFFL +//RLC_SRM_INDEX_CNTL_DATA_0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_1 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_2 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_3 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_4 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_5 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_6 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_INDEX_CNTL_DATA_7 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xFFFFFFFFL +//RLC_SRM_STAT +#define RLC_SRM_STAT__SRM_BUSY__SHIFT 0x0 +#define RLC_SRM_STAT__RESERVED__SHIFT 0x1 +#define RLC_SRM_STAT__SRM_BUSY_MASK 0x00000001L +#define RLC_SRM_STAT__RESERVED_MASK 0xFFFFFFFEL +//RLC_LX6_UTCL1_ERROR_2 +#define RLC_LX6_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_LX6_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_8 +#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_8__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_9 +#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_9__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_10 +#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_10__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_11 +#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_11__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_12 +#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_12__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_CNTL_0 +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_GPM_UTCL1_CNTL_0__RESERVED_23_20__SHIFT 0x14 +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE__SHIFT 0x18 +#define RLC_GPM_UTCL1_CNTL_0__BYPASS__SHIFT 0x19 +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE__SHIFT 0x1a +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP__SHIFT 0x1c +#define RLC_GPM_UTCL1_CNTL_0__RESERVED__SHIFT 0x1d +#define RLC_GPM_UTCL1_CNTL_0__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_GPM_UTCL1_CNTL_0__RESERVED_23_20_MASK 0x00F00000L +#define RLC_GPM_UTCL1_CNTL_0__DROP_MODE_MASK 0x01000000L +#define RLC_GPM_UTCL1_CNTL_0__BYPASS_MASK 0x02000000L +#define RLC_GPM_UTCL1_CNTL_0__INVALIDATE_MASK 0x04000000L +#define RLC_GPM_UTCL1_CNTL_0__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_GPM_UTCL1_CNTL_0__FORCE_SNOOP_MASK 0x10000000L +#define RLC_GPM_UTCL1_CNTL_0__RESERVED_MASK 0xE0000000L +//RLC_SPM_UTCL1_CNTL +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_SPM_UTCL1_CNTL__RESERVED_23_20__SHIFT 0x14 +#define RLC_SPM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_SPM_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define RLC_SPM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_SPM_UTCL1_CNTL__RESERVED__SHIFT 0x1d +#define RLC_SPM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_SPM_UTCL1_CNTL__RESERVED_23_20_MASK 0x00F00000L +#define RLC_SPM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_SPM_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define RLC_SPM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_SPM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_SPM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define RLC_SPM_UTCL1_CNTL__RESERVED_MASK 0xE0000000L +//RLC_UTCL1_STATUS_2 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY__SHIFT 0x0 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY__SHIFT 0x1 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY__SHIFT 0x2 +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY__SHIFT 0x3 +#define RLC_UTCL1_STATUS_2__LX6_UTCL1_BUSY__SHIFT 0x4 +#define RLC_UTCL1_STATUS_2__DMA_UTCL1_BUSY__SHIFT 0x5 +#define RLC_UTCL1_STATUS_2__SRM_UTCL1_BUSY__SHIFT 0x6 +#define RLC_UTCL1_STATUS_2__DLG_UTCL1_BUSY__SHIFT 0x7 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans__SHIFT 0x8 +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans__SHIFT 0x9 +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans__SHIFT 0xa +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans__SHIFT 0xb +#define RLC_UTCL1_STATUS_2__LX6_UTCL1_StallOnTrans__SHIFT 0xc +#define RLC_UTCL1_STATUS_2__DMA_UTCL1_StallOnTrans__SHIFT 0xd +#define RLC_UTCL1_STATUS_2__SRM_UTCL1_StallOnTrans__SHIFT 0xe +#define RLC_UTCL1_STATUS_2__DLG_UTCL1_StallOnTrans__SHIFT 0xf +#define RLC_UTCL1_STATUS_2__RESERVED__SHIFT 0x10 +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_BUSY_MASK 0x00000001L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_BUSY_MASK 0x00000002L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_BUSY_MASK 0x00000004L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_BUSY_MASK 0x00000008L +#define RLC_UTCL1_STATUS_2__LX6_UTCL1_BUSY_MASK 0x00000010L +#define RLC_UTCL1_STATUS_2__DMA_UTCL1_BUSY_MASK 0x00000020L +#define RLC_UTCL1_STATUS_2__SRM_UTCL1_BUSY_MASK 0x00000040L +#define RLC_UTCL1_STATUS_2__DLG_UTCL1_BUSY_MASK 0x00000080L +#define RLC_UTCL1_STATUS_2__GPM_TH0_UTCL1_StallOnTrans_MASK 0x00000100L +#define RLC_UTCL1_STATUS_2__GPM_TH1_UTCL1_StallOnTrans_MASK 0x00000200L +#define RLC_UTCL1_STATUS_2__GPM_TH2_UTCL1_StallOnTrans_MASK 0x00000400L +#define RLC_UTCL1_STATUS_2__SPM_UTCL1_StallOnTrans_MASK 0x00000800L +#define RLC_UTCL1_STATUS_2__LX6_UTCL1_StallOnTrans_MASK 0x00001000L +#define RLC_UTCL1_STATUS_2__DMA_UTCL1_StallOnTrans_MASK 0x00002000L +#define RLC_UTCL1_STATUS_2__SRM_UTCL1_StallOnTrans_MASK 0x00004000L +#define RLC_UTCL1_STATUS_2__DLG_UTCL1_StallOnTrans_MASK 0x00008000L +#define RLC_UTCL1_STATUS_2__RESERVED_MASK 0xFFFF0000L +//RLC_SPM_UTCL1_ERROR_1 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_SPM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x0007FFC0L +//RLC_SPM_UTCL1_ERROR_2 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_SPM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_GPM_UTCL1_TH0_ERROR_1 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_GPM_UTCL1_TH0_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x0007FFC0L +//RLC_GPM_UTCL1_TH0_ERROR_2 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_GPM_UTCL1_TH0_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_SEMAPHORE_0 +#define RLC_SEMAPHORE_0__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_0__CLIENT_ID_MASK 0x0000001FL +//RLC_SEMAPHORE_1 +#define RLC_SEMAPHORE_1__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_1__CLIENT_ID_MASK 0x0000001FL +//RLC_SEMAPHORE_2 +#define RLC_SEMAPHORE_2__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_2__CLIENT_ID_MASK 0x0000001FL +//RLC_SEMAPHORE_3 +#define RLC_SEMAPHORE_3__CLIENT_ID__SHIFT 0x0 +#define RLC_SEMAPHORE_3__CLIENT_ID_MASK 0x0000001FL +//RLC_SRM_UTCL1_CNTL +#define RLC_SRM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_SRM_UTCL1_CNTL__RESERVED_23_20__SHIFT 0x14 +#define RLC_SRM_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_SRM_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define RLC_SRM_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_SRM_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_SRM_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_SRM_UTCL1_CNTL__RESERVED__SHIFT 0x1d +#define RLC_SRM_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_SRM_UTCL1_CNTL__RESERVED_23_20_MASK 0x00F00000L +#define RLC_SRM_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_SRM_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define RLC_SRM_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_SRM_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_SRM_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define RLC_SRM_UTCL1_CNTL__RESERVED_MASK 0xE0000000L +//RLC_SRM_UTCL1_ERROR_1 +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_SRM_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x0007FFC0L +//RLC_SRM_UTCL1_ERROR_2 +#define RLC_SRM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_SRM_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_DLG_UTCL1_ERROR_2 +#define RLC_DLG_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_DLG_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_UTCL1_STATUS +#define RLC_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RLC_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RLC_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RLC_UTCL1_STATUS__RESERVED__SHIFT 0x3 +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID__SHIFT 0x8 +#define RLC_UTCL1_STATUS__RESERVED_1__SHIFT 0xe +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID__SHIFT 0x10 +#define RLC_UTCL1_STATUS__RESERVED_2__SHIFT 0x16 +#define RLC_UTCL1_STATUS__PRT_UTCL1ID__SHIFT 0x18 +#define RLC_UTCL1_STATUS__RESERVED_3__SHIFT 0x1e +#define RLC_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RLC_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RLC_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +#define RLC_UTCL1_STATUS__RESERVED_MASK 0x000000F8L +#define RLC_UTCL1_STATUS__FAULT_UTCL1ID_MASK 0x00003F00L +#define RLC_UTCL1_STATUS__RESERVED_1_MASK 0x0000C000L +#define RLC_UTCL1_STATUS__RETRY_UTCL1ID_MASK 0x003F0000L +#define RLC_UTCL1_STATUS__RESERVED_2_MASK 0x00C00000L +#define RLC_UTCL1_STATUS__PRT_UTCL1ID_MASK 0x3F000000L +#define RLC_UTCL1_STATUS__RESERVED_3_MASK 0xC0000000L +//RLC_R2I_CNTL_0 +#define RLC_R2I_CNTL_0__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_0__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_1 +#define RLC_R2I_CNTL_1__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_1__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_2 +#define RLC_R2I_CNTL_2__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_2__Data_MASK 0xFFFFFFFFL +//RLC_R2I_CNTL_3 +#define RLC_R2I_CNTL_3__Data__SHIFT 0x0 +#define RLC_R2I_CNTL_3__Data_MASK 0xFFFFFFFFL +//RLC_GPM_INT_STAT_TH0 +#define RLC_GPM_INT_STAT_TH0__STATUS__SHIFT 0x0 +#define RLC_GPM_INT_STAT_TH0__STATUS_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_13 +#define RLC_GPM_GENERAL_13__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_13__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_14 +#define RLC_GPM_GENERAL_14__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_14__DATA_MASK 0xFFFFFFFFL +//RLC_GPM_GENERAL_15 +#define RLC_GPM_GENERAL_15__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_15__DATA_MASK 0xFFFFFFFFL +//RLC_LX6_UTCL1_ERROR_1 +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_LX6_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x0007FFC0L +//RLC_LX6_UTCL1_CNTL +#define RLC_LX6_UTCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define RLC_LX6_UTCL1_CNTL__RESERVED_23_20__SHIFT 0x14 +#define RLC_LX6_UTCL1_CNTL__DROP_MODE__SHIFT 0x18 +#define RLC_LX6_UTCL1_CNTL__BYPASS__SHIFT 0x19 +#define RLC_LX6_UTCL1_CNTL__INVALIDATE__SHIFT 0x1a +#define RLC_LX6_UTCL1_CNTL__FRAG_LIMIT_MODE__SHIFT 0x1b +#define RLC_LX6_UTCL1_CNTL__FORCE_SNOOP__SHIFT 0x1c +#define RLC_LX6_UTCL1_CNTL__RESERVED__SHIFT 0x1d +#define RLC_LX6_UTCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x000FFFFFL +#define RLC_LX6_UTCL1_CNTL__RESERVED_23_20_MASK 0x00F00000L +#define RLC_LX6_UTCL1_CNTL__DROP_MODE_MASK 0x01000000L +#define RLC_LX6_UTCL1_CNTL__BYPASS_MASK 0x02000000L +#define RLC_LX6_UTCL1_CNTL__INVALIDATE_MASK 0x04000000L +#define RLC_LX6_UTCL1_CNTL__FRAG_LIMIT_MODE_MASK 0x08000000L +#define RLC_LX6_UTCL1_CNTL__FORCE_SNOOP_MASK 0x10000000L +#define RLC_LX6_UTCL1_CNTL__RESERVED_MASK 0xE0000000L +//RLC_DMA_UTCL1_ERROR_1 +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqError__SHIFT 0x0 +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqErrorVmid__SHIFT 0x2 +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB__SHIFT 0x6 +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqError_MASK 0x00000003L +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqErrorVmid_MASK 0x0000003CL +#define RLC_DMA_UTCL1_ERROR_1__Translated_ReqErrorAddr_MSB_MASK 0x0007FFC0L +//RLC_DMA_UTCL1_ERROR_2 +#define RLC_DMA_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB__SHIFT 0x0 +#define RLC_DMA_UTCL1_ERROR_2__Translated_ReqErrorAddr_LSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT_1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_GPU_CLOCK_COUNT_LSB_2 +#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB_2__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB_2 +#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB_2__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_CAPTURE_GPU_CLOCK_COUNT_2 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED__SHIFT 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__CAPTURE_MASK 0x00000001L +#define RLC_CAPTURE_GPU_CLOCK_COUNT_2__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCV_DOORBELL_RANGE +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 +#define RLC_RLCV_DOORBELL_RANGE__RESERVED__SHIFT 0x1c +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L +#define RLC_RLCV_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L +#define RLC_RLCV_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L +#define RLC_RLCV_DOORBELL_RANGE__RESERVED_MASK 0xF0000000L +//RLC_RLCV_DOORBELL_CNTL +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 +#define RLC_RLCV_DOORBELL_CNTL__RESERVED__SHIFT 0x16 +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L +#define RLC_RLCV_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L +#define RLC_RLCV_DOORBELL_CNTL__RESERVED_MASK 0xFFC00000L +//RLC_RLCV_DOORBELL_STAT +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L +#define RLC_RLCV_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L +//RLC_RLCV_DOORBELL_0_DATA_LO +#define RLC_RLCV_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_0_DATA_HI +#define RLC_RLCV_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_1_DATA_LO +#define RLC_RLCV_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_1_DATA_HI +#define RLC_RLCV_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_2_DATA_LO +#define RLC_RLCV_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_2_DATA_HI +#define RLC_RLCV_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_3_DATA_LO +#define RLC_RLCV_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_RLCV_DOORBELL_3_DATA_HI +#define RLC_RLCV_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 +#define RLC_RLCV_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_LSB_1 +#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_LSB_1__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_MSB_1 +#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB_1__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_RLCV_SPARE_INT +#define RLC_RLCV_SPARE_INT__INTERRUPT__SHIFT 0x0 +#define RLC_RLCV_SPARE_INT__RESERVED__SHIFT 0x1 +#define RLC_RLCV_SPARE_INT__INTERRUPT_MASK 0x00000001L +#define RLC_RLCV_SPARE_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_SMU_CLK_REQ +#define RLC_SMU_CLK_REQ__VALID__SHIFT 0x0 +#define RLC_SMU_CLK_REQ__VALID_MASK 0x00000001L +//RLC_SPARE +#define RLC_SPARE__SPARE__SHIFT 0x0 +#define RLC_SPARE__SPARE_MASK 0xFFFFFFFFL +//RLC_SPP_CTRL +#define RLC_SPP_CTRL__ENABLE__SHIFT 0x0 +#define RLC_SPP_CTRL__ENABLE_PPROF__SHIFT 0x1 +#define RLC_SPP_CTRL__ENABLE_PWR_OPT__SHIFT 0x2 +#define RLC_SPP_CTRL__PAUSE__SHIFT 0x3 +#define RLC_SPP_CTRL__ENABLE_MASK 0x00000001L +#define RLC_SPP_CTRL__ENABLE_PPROF_MASK 0x00000002L +#define RLC_SPP_CTRL__ENABLE_PWR_OPT_MASK 0x00000004L +#define RLC_SPP_CTRL__PAUSE_MASK 0x00000008L +//RLC_SPP_SHADER_PROFILE_EN +#define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE__SHIFT 0x0 +#define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE__SHIFT 0x2 +#define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE__SHIFT 0x3 +#define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE__SHIFT 0x4 +#define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE__SHIFT 0x5 +#define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION__SHIFT 0xb +#define RLC_SPP_SHADER_PROFILE_EN__CSG_START_CONDITION__SHIFT 0xc +#define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION__SHIFT 0xd +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS__SHIFT 0xe +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED__SHIFT 0xf +#define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK__SHIFT 0x10 +#define RLC_SPP_SHADER_PROFILE_EN__PS_ENABLE_MASK 0x00000001L +#define RLC_SPP_SHADER_PROFILE_EN__GS_ENABLE_MASK 0x00000004L +#define RLC_SPP_SHADER_PROFILE_EN__HS_ENABLE_MASK 0x00000008L +#define RLC_SPP_SHADER_PROFILE_EN__CSG_ENABLE_MASK 0x00000010L +#define RLC_SPP_SHADER_PROFILE_EN__CS_ENABLE_MASK 0x00000020L +#define RLC_SPP_SHADER_PROFILE_EN__PS_START_CONDITION_MASK 0x00000800L +#define RLC_SPP_SHADER_PROFILE_EN__CSG_START_CONDITION_MASK 0x00001000L +#define RLC_SPP_SHADER_PROFILE_EN__CS_START_CONDITION_MASK 0x00002000L +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_MISS_MASK 0x00004000L +#define RLC_SPP_SHADER_PROFILE_EN__FORCE_UNLOCKED_MASK 0x00008000L +#define RLC_SPP_SHADER_PROFILE_EN__ENABLE_PROF_INFO_LOCK_MASK 0x00010000L +//RLC_SPP_SSF_CAPTURE_EN +#define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE__SHIFT 0x0 +#define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE__SHIFT 0x2 +#define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE__SHIFT 0x3 +#define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE__SHIFT 0x4 +#define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE__SHIFT 0x5 +#define RLC_SPP_SSF_CAPTURE_EN__PS_ENABLE_MASK 0x00000001L +#define RLC_SPP_SSF_CAPTURE_EN__GS_ENABLE_MASK 0x00000004L +#define RLC_SPP_SSF_CAPTURE_EN__HS_ENABLE_MASK 0x00000008L +#define RLC_SPP_SSF_CAPTURE_EN__CSG_ENABLE_MASK 0x00000010L +#define RLC_SPP_SSF_CAPTURE_EN__CS_ENABLE_MASK 0x00000020L +//RLC_SPP_SSF_THRESHOLD_0 +#define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD__SHIFT 0x0 +#define RLC_SPP_SSF_THRESHOLD_0__RESERVED__SHIFT 0x10 +#define RLC_SPP_SSF_THRESHOLD_0__PS_THRESHOLD_MASK 0x0000FFFFL +#define RLC_SPP_SSF_THRESHOLD_0__RESERVED_MASK 0xFFFF0000L +//RLC_SPP_SSF_THRESHOLD_1 +#define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD__SHIFT 0x0 +#define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD__SHIFT 0x10 +#define RLC_SPP_SSF_THRESHOLD_1__GS_THRESHOLD_MASK 0x0000FFFFL +#define RLC_SPP_SSF_THRESHOLD_1__HS_THRESHOLD_MASK 0xFFFF0000L +//RLC_SPP_SSF_THRESHOLD_2 +#define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD__SHIFT 0x0 +#define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD__SHIFT 0x10 +#define RLC_SPP_SSF_THRESHOLD_2__CSG_THRESHOLD_MASK 0x0000FFFFL +#define RLC_SPP_SSF_THRESHOLD_2__CS_THRESHOLD_MASK 0xFFFF0000L +//RLC_SPP_INFLIGHT_RD_ADDR +#define RLC_SPP_INFLIGHT_RD_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPP_INFLIGHT_RD_ADDR__ADDR_MASK 0x0000001FL +//RLC_SPP_INFLIGHT_RD_DATA +#define RLC_SPP_INFLIGHT_RD_DATA__DATA__SHIFT 0x0 +#define RLC_SPP_INFLIGHT_RD_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPP_PROF_INFO_1 +#define RLC_SPP_PROF_INFO_1__SH_ID__SHIFT 0x0 +#define RLC_SPP_PROF_INFO_1__SH_ID_MASK 0xFFFFFFFFL +//RLC_SPP_PROF_INFO_2 +#define RLC_SPP_PROF_INFO_2__SH_TYPE__SHIFT 0x0 +#define RLC_SPP_PROF_INFO_2__CAM_HIT__SHIFT 0x5 +#define RLC_SPP_PROF_INFO_2__CAM_LOCK__SHIFT 0x6 +#define RLC_SPP_PROF_INFO_2__CAM_CONFLICT__SHIFT 0x7 +#define RLC_SPP_PROF_INFO_2__SH_TYPE_MASK 0x0000001FL +#define RLC_SPP_PROF_INFO_2__CAM_HIT_MASK 0x00000020L +#define RLC_SPP_PROF_INFO_2__CAM_LOCK_MASK 0x00000040L +#define RLC_SPP_PROF_INFO_2__CAM_CONFLICT_MASK 0x00000080L +//RLC_SPP_GLOBAL_SH_ID +#define RLC_SPP_GLOBAL_SH_ID__SH_ID__SHIFT 0x0 +#define RLC_SPP_GLOBAL_SH_ID__SH_ID_MASK 0xFFFFFFFFL +//RLC_SPP_GLOBAL_SH_ID_VALID +#define RLC_SPP_GLOBAL_SH_ID_VALID__VALID__SHIFT 0x0 +#define RLC_SPP_GLOBAL_SH_ID_VALID__VALID_MASK 0x00000001L +//RLC_SPP_STATUS +#define RLC_SPP_STATUS__RESERVED_0__SHIFT 0x0 +#define RLC_SPP_STATUS__SSF_BUSY__SHIFT 0x1 +#define RLC_SPP_STATUS__EVENT_ARB_BUSY__SHIFT 0x2 +#define RLC_SPP_STATUS__SPP_BUSY__SHIFT 0x1f +#define RLC_SPP_STATUS__RESERVED_0_MASK 0x00000001L +#define RLC_SPP_STATUS__SSF_BUSY_MASK 0x00000002L +#define RLC_SPP_STATUS__EVENT_ARB_BUSY_MASK 0x00000004L +#define RLC_SPP_STATUS__SPP_BUSY_MASK 0x80000000L +//RLC_SPP_PVT_STAT_0 +#define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER__SHIFT 0x8 +#define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER__SHIFT 0x10 +#define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER__SHIFT 0x18 +#define RLC_SPP_PVT_STAT_0__LEVEL_0_COUNTER_MASK 0x0000007FL +#define RLC_SPP_PVT_STAT_0__LEVEL_1_COUNTER_MASK 0x00007F00L +#define RLC_SPP_PVT_STAT_0__LEVEL_2_COUNTER_MASK 0x007F0000L +#define RLC_SPP_PVT_STAT_0__LEVEL_3_COUNTER_MASK 0x7F000000L +//RLC_SPP_PVT_STAT_1 +#define RLC_SPP_PVT_STAT_1__LEVEL_4_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER__SHIFT 0x8 +#define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER__SHIFT 0x10 +#define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER__SHIFT 0x18 +#define RLC_SPP_PVT_STAT_1__LEVEL_4_COUNTER_MASK 0x0000007FL +#define RLC_SPP_PVT_STAT_1__LEVEL_5_COUNTER_MASK 0x00007F00L +#define RLC_SPP_PVT_STAT_1__LEVEL_6_COUNTER_MASK 0x007F0000L +#define RLC_SPP_PVT_STAT_1__LEVEL_7_COUNTER_MASK 0x7F000000L +//RLC_SPP_PVT_STAT_2 +#define RLC_SPP_PVT_STAT_2__LEVEL_8_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_2__LEVEL_9_COUNTER__SHIFT 0x8 +#define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER__SHIFT 0x10 +#define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER__SHIFT 0x18 +#define RLC_SPP_PVT_STAT_2__LEVEL_8_COUNTER_MASK 0x0000007FL +#define RLC_SPP_PVT_STAT_2__LEVEL_9_COUNTER_MASK 0x00007F00L +#define RLC_SPP_PVT_STAT_2__LEVEL_10_COUNTER_MASK 0x007F0000L +#define RLC_SPP_PVT_STAT_2__LEVEL_11_COUNTER_MASK 0x7F000000L +//RLC_SPP_PVT_STAT_3 +#define RLC_SPP_PVT_STAT_3__LEVEL_12_COUNTER__SHIFT 0x0 +#define RLC_SPP_PVT_STAT_3__LEVEL_13_COUNTER__SHIFT 0x8 +#define RLC_SPP_PVT_STAT_3__LEVEL_14_COUNTER__SHIFT 0x10 +#define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER__SHIFT 0x18 +#define RLC_SPP_PVT_STAT_3__LEVEL_12_COUNTER_MASK 0x0000007FL +#define RLC_SPP_PVT_STAT_3__LEVEL_13_COUNTER_MASK 0x00007F00L +#define RLC_SPP_PVT_STAT_3__LEVEL_14_COUNTER_MASK 0x007F0000L +#define RLC_SPP_PVT_STAT_3__LEVEL_15_COUNTER_MASK 0x7F000000L +//RLC_SPP_PVT_LEVEL_MAX +#define RLC_SPP_PVT_LEVEL_MAX__LEVEL__SHIFT 0x0 +#define RLC_SPP_PVT_LEVEL_MAX__LEVEL_MASK 0x0000000FL +//RLC_SPP_STALL_STATE_UPDATE +#define RLC_SPP_STALL_STATE_UPDATE__STALL__SHIFT 0x0 +#define RLC_SPP_STALL_STATE_UPDATE__ENABLE__SHIFT 0x1 +#define RLC_SPP_STALL_STATE_UPDATE__STALL_MASK 0x00000001L +#define RLC_SPP_STALL_STATE_UPDATE__ENABLE_MASK 0x00000002L +//RLC_SPP_PBB_INFO +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE__SHIFT 0x0 +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID__SHIFT 0x1 +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE__SHIFT 0x2 +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID__SHIFT 0x3 +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_MASK 0x00000001L +#define RLC_SPP_PBB_INFO__PIPE0_OVERRIDE_VALID_MASK 0x00000002L +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_MASK 0x00000004L +#define RLC_SPP_PBB_INFO__PIPE1_OVERRIDE_VALID_MASK 0x00000008L +//RLC_SPP_RESET +#define RLC_SPP_RESET__SSF_RESET__SHIFT 0x0 +#define RLC_SPP_RESET__EVENT_ARB_RESET__SHIFT 0x1 +#define RLC_SPP_RESET__CAM_RESET__SHIFT 0x2 +#define RLC_SPP_RESET__PVT_RESET__SHIFT 0x3 +#define RLC_SPP_RESET__SSF_RESET_MASK 0x00000001L +#define RLC_SPP_RESET__EVENT_ARB_RESET_MASK 0x00000002L +#define RLC_SPP_RESET__CAM_RESET_MASK 0x00000004L +#define RLC_SPP_RESET__PVT_RESET_MASK 0x00000008L +//RLC_CAC_MASK_CNTL +#define RLC_CAC_MASK_CNTL__RLC_CAC_MASK__SHIFT 0x0 +#define RLC_CAC_MASK_CNTL__RLC_CAC_MASK_MASK 0xFFFFFFFFL +//RLC_POWER_RESIDENCY_CNTR_CTRL +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_POWER_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_CLK_RESIDENCY_CNTR_CTRL +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_CLK_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_DS_RESIDENCY_CNTR_CTRL +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_DS_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_DS_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_DS_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_ULV_RESIDENCY_CNTR_CTRL +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_ULV_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_PCC_RESIDENCY_CNTR_CTRL +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_PCC_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_GENERAL_RESIDENCY_CNTR_CTRL +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET__SHIFT 0x0 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE__SHIFT 0x1 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK__SHIFT 0x2 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK__SHIFT 0x3 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW__SHIFT 0x4 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED__SHIFT 0x5 +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_MASK 0x00000001L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_MASK 0x00000002L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESET_ACK_MASK 0x00000004L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__ENABLE_ACK_MASK 0x00000008L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__COUNTER_OVERFLOW_MASK 0x00000010L +#define RLC_GENERAL_RESIDENCY_CNTR_CTRL__RESERVED_MASK 0xFFFFFFE0L +//RLC_POWER_RESIDENCY_EVENT_CNTR +#define RLC_POWER_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_POWER_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_CLK_RESIDENCY_EVENT_CNTR +#define RLC_CLK_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_CLK_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_DS_RESIDENCY_EVENT_CNTR +#define RLC_DS_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_DS_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_ULV_RESIDENCY_EVENT_CNTR +#define RLC_ULV_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_ULV_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_PCC_RESIDENCY_EVENT_CNTR +#define RLC_PCC_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_PCC_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_GENERAL_RESIDENCY_EVENT_CNTR +#define RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA__SHIFT 0x0 +#define RLC_GENERAL_RESIDENCY_EVENT_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_POWER_RESIDENCY_REF_CNTR +#define RLC_POWER_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_POWER_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_CLK_RESIDENCY_REF_CNTR +#define RLC_CLK_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_CLK_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_DS_RESIDENCY_REF_CNTR +#define RLC_DS_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_DS_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_ULV_RESIDENCY_REF_CNTR +#define RLC_ULV_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_ULV_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_PCC_RESIDENCY_REF_CNTR +#define RLC_PCC_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_PCC_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_GENERAL_RESIDENCY_REF_CNTR +#define RLC_GENERAL_RESIDENCY_REF_CNTR__DATA__SHIFT 0x0 +#define RLC_GENERAL_RESIDENCY_REF_CNTR__DATA_MASK 0xFFFFFFFFL +//RLC_GFX_IH_CLIENT_CTRL +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_13__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_MASK__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_15__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_29__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_ERROR_CLEAR__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_CTRL__IH_HALT__SHIFT 0x1f +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_MASK_MASK 0x000000FFL +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_MASK_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_MASK_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_13_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_MASK_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_15_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_CTRL__SE_INTERRUPT_ERROR_CLEAR_MASK 0x00FF0000L +#define RLC_GFX_IH_CLIENT_CTRL__SDMA_INTERRUPT_ERROR_CLEAR_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_CTRL__UTCL2_INTERRUPT_ERROR_CLEAR_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_CTRL__RESERVED_29_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_CTRL__FED_INTERRUPT_ERROR_CLEAR_MASK 0x40000000L +#define RLC_GFX_IH_CLIENT_CTRL__IH_HALT_MASK 0x80000000L +//RLC_GFX_IH_ARBITER_STAT +#define RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED__SHIFT 0x0 +#define RLC_GFX_IH_ARBITER_STAT__RESERVED__SHIFT 0x10 +#define RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED__SHIFT 0x1c +#define RLC_GFX_IH_ARBITER_STAT__CLIENT_GRANTED_MASK 0x0000FFFFL +#define RLC_GFX_IH_ARBITER_STAT__RESERVED_MASK 0x0FFF0000L +#define RLC_GFX_IH_ARBITER_STAT__LAST_CLIENT_GRANTED_MASK 0xF0000000L +//RLC_GFX_IH_CLIENT_SE_STAT_L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING__SHIFT 0x4 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR__SHIFT 0x5 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW__SHIFT 0x6 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED__SHIFT 0x7 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING__SHIFT 0x14 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR__SHIFT 0x15 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW__SHIFT 0x16 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED__SHIFT 0x17 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED__SHIFT 0x1f +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LEVEL_MASK 0x0000000FL +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_LOADING_MASK 0x00000010L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_PROTOCOL_ERROR_MASK 0x00000020L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_BUFFER_OVERFLOW_MASK 0x00000040L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE0_RESERVED_MASK 0x00000080L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LEVEL_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_LOADING_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_PROTOCOL_ERROR_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_BUFFER_OVERFLOW_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE1_RESERVED_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LEVEL_MASK 0x000F0000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_LOADING_MASK 0x00100000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_PROTOCOL_ERROR_MASK 0x00200000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_BUFFER_OVERFLOW_MASK 0x00400000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE2_RESERVED_MASK 0x00800000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LEVEL_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_LOADING_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_PROTOCOL_ERROR_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_BUFFER_OVERFLOW_MASK 0x40000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_L__SE3_RESERVED_MASK 0x80000000L +//RLC_GFX_IH_CLIENT_SE_STAT_H +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING__SHIFT 0x4 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR__SHIFT 0x5 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW__SHIFT 0x6 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED__SHIFT 0x7 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING__SHIFT 0x14 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR__SHIFT 0x15 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW__SHIFT 0x16 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED__SHIFT 0x17 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED__SHIFT 0x1f +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LEVEL_MASK 0x0000000FL +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_LOADING_MASK 0x00000010L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_PROTOCOL_ERROR_MASK 0x00000020L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_BUFFER_OVERFLOW_MASK 0x00000040L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE4_RESERVED_MASK 0x00000080L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LEVEL_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_LOADING_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_PROTOCOL_ERROR_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_BUFFER_OVERFLOW_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE5_RESERVED_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LEVEL_MASK 0x000F0000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_LOADING_MASK 0x00100000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_PROTOCOL_ERROR_MASK 0x00200000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_BUFFER_OVERFLOW_MASK 0x00400000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE6_RESERVED_MASK 0x00800000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LEVEL_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_LOADING_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_PROTOCOL_ERROR_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_BUFFER_OVERFLOW_MASK 0x40000000L +#define RLC_GFX_IH_CLIENT_SE_STAT_H__SE7_RESERVED_MASK 0x80000000L +//RLC_GFX_IH_CLIENT_SDMA_STAT +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING__SHIFT 0x4 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR__SHIFT 0x5 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW__SHIFT 0x6 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED__SHIFT 0x7 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING__SHIFT 0xc +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR__SHIFT 0xd +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW__SHIFT 0xe +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED__SHIFT 0xf +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING__SHIFT 0x14 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR__SHIFT 0x15 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW__SHIFT 0x16 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED__SHIFT 0x17 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING__SHIFT 0x1c +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR__SHIFT 0x1d +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW__SHIFT 0x1e +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED__SHIFT 0x1f +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LEVEL_MASK 0x0000000FL +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_LOADING_MASK 0x00000010L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_PROTOCOL_ERROR_MASK 0x00000020L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_BUFFER_OVERFLOW_MASK 0x00000040L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA0_RESERVED_MASK 0x00000080L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LEVEL_MASK 0x00000F00L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_LOADING_MASK 0x00001000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_PROTOCOL_ERROR_MASK 0x00002000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_BUFFER_OVERFLOW_MASK 0x00004000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA1_RESERVED_MASK 0x00008000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LEVEL_MASK 0x000F0000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_LOADING_MASK 0x00100000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_PROTOCOL_ERROR_MASK 0x00200000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_BUFFER_OVERFLOW_MASK 0x00400000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA2_RESERVED_MASK 0x00800000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LEVEL_MASK 0x0F000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_LOADING_MASK 0x10000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_PROTOCOL_ERROR_MASK 0x20000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_BUFFER_OVERFLOW_MASK 0x40000000L +#define RLC_GFX_IH_CLIENT_SDMA_STAT__SDMA3_RESERVED_MASK 0x80000000L +//RLC_GFX_IH_CLIENT_OTHER_STAT +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED__SHIFT 0x0 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED__SHIFT 0x8 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LEVEL__SHIFT 0x10 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LOADING__SHIFT 0x14 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_PROTOCOL_ERROR__SHIFT 0x15 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_OVERFLOW__SHIFT 0x16 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_RESERVED__SHIFT 0x17 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_24__SHIFT 0x18 +#define RLC_GFX_IH_CLIENT_OTHER_STAT__UTCL2_RESERVED_MASK 0x000000FFL +#define RLC_GFX_IH_CLIENT_OTHER_STAT__PMM_RESERVED_MASK 0x0000FF00L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LEVEL_MASK 0x000F0000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_LOADING_MASK 0x00100000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_PROTOCOL_ERROR_MASK 0x00200000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_BUFFER_OVERFLOW_MASK 0x00400000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__FED_RESERVED_MASK 0x00800000L +#define RLC_GFX_IH_CLIENT_OTHER_STAT__RESERVED_31_24_MASK 0xFF000000L +//RLC_SPM_GLOBAL_DELAY_IND_ADDR +#define RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_DELAY_IND_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_GLOBAL_DELAY_IND_DATA +#define RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_GLOBAL_DELAY_IND_DATA__DATA_MASK 0x0000003FL +//RLC_SPM_SE_DELAY_IND_ADDR +#define RLC_SPM_SE_DELAY_IND_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_SE_DELAY_IND_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_SE_DELAY_IND_DATA +#define RLC_SPM_SE_DELAY_IND_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_SE_DELAY_IND_DATA__DATA_MASK 0x0000003FL +//RLC_SPM_GLOBAL_BLK_EN_MASK_IND_ADDR +#define RLC_SPM_GLOBAL_BLK_EN_MASK_IND_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_BLK_EN_MASK_IND_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_GLOBAL_BLK_EN_MASK_IND_DATA +#define RLC_SPM_GLOBAL_BLK_EN_MASK_IND_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_GLOBAL_BLK_EN_MASK_IND_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_SPM_SE_BLK_EN_MASK_IND_ADDR +#define RLC_SPM_SE_BLK_EN_MASK_IND_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPM_SE_BLK_EN_MASK_IND_ADDR__ADDR_MASK 0x00000FFFL +//RLC_SPM_SE_BLK_EN_MASK_IND_DATA +#define RLC_SPM_SE_BLK_EN_MASK_IND_DATA__DATA__SHIFT 0x0 +#define RLC_SPM_SE_BLK_EN_MASK_IND_DATA__DATA_MASK 0xFFFFFFFFL +//RLC_GFX_IH_22BEAT_STAT +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_LEVEL__SHIFT 0x0 +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_LOADING__SHIFT 0x8 +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_PROTOCOL_ERROR__SHIFT 0x9 +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_OVERFLOW__SHIFT 0xa +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_RESERVED__SHIFT 0xb +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_LEVEL_MASK 0x000000FFL +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_LOADING_MASK 0x00000100L +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_PROTOCOL_ERROR_MASK 0x00000200L +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_BUFFER_OVERFLOW_MASK 0x00000400L +#define RLC_GFX_IH_22BEAT_STAT__UTCL2_RESERVED_MASK 0xFFFFF800L +//RLC_GFX_IH_ARBITER_STAT_22BEAT +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__CLIENT_GRANTED__SHIFT 0x0 +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__RESERVED__SHIFT 0x10 +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__LAST_CLIENT_GRANTED__SHIFT 0x1c +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__CLIENT_GRANTED_MASK 0x0000FFFFL +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__RESERVED_MASK 0x0FFF0000L +#define RLC_GFX_IH_ARBITER_STAT_22BEAT__LAST_CLIENT_GRANTED_MASK 0xF0000000L +//RLC_LX6_CNTL +#define RLC_LX6_CNTL__BRESET__SHIFT 0x0 +#define RLC_LX6_CNTL__RUNSTALL__SHIFT 0x1 +#define RLC_LX6_CNTL__PDEBUG_ENABLE__SHIFT 0x2 +#define RLC_LX6_CNTL__STAT_VECTOR_SEL__SHIFT 0x3 +#define RLC_LX6_CNTL__BRESET_MASK 0x00000001L +#define RLC_LX6_CNTL__RUNSTALL_MASK 0x00000002L +#define RLC_LX6_CNTL__PDEBUG_ENABLE_MASK 0x00000004L +#define RLC_LX6_CNTL__STAT_VECTOR_SEL_MASK 0x00000008L +//RLC_LX6_STATUS +#define RLC_LX6_STATUS__CORE0_CORE_BUSY__SHIFT 0x0 +#define RLC_LX6_STATUS__CORE0_PIF_GASKET_BUSY__SHIFT 0x1 +#define RLC_LX6_STATUS__CORE0_INT_PENDING__SHIFT 0x2 +#define RLC_LX6_STATUS__CORE0_GRBMT_BUSY__SHIFT 0x3 +#define RLC_LX6_STATUS__CORE1_CORE_BUSY__SHIFT 0x4 +#define RLC_LX6_STATUS__CORE1_PIF_GASKET_BUSY__SHIFT 0x5 +#define RLC_LX6_STATUS__CORE1_INT_PENDING__SHIFT 0x6 +#define RLC_LX6_STATUS__CORE1_GRBMT_BUSY__SHIFT 0x7 +#define RLC_LX6_STATUS__GRBMT_BUSY__SHIFT 0x8 +#define RLC_LX6_STATUS__CORE0_CORE_BUSY_MASK 0x00000001L +#define RLC_LX6_STATUS__CORE0_PIF_GASKET_BUSY_MASK 0x00000002L +#define RLC_LX6_STATUS__CORE0_INT_PENDING_MASK 0x00000004L +#define RLC_LX6_STATUS__CORE0_GRBMT_BUSY_MASK 0x00000008L +#define RLC_LX6_STATUS__CORE1_CORE_BUSY_MASK 0x00000010L +#define RLC_LX6_STATUS__CORE1_PIF_GASKET_BUSY_MASK 0x00000020L +#define RLC_LX6_STATUS__CORE1_INT_PENDING_MASK 0x00000040L +#define RLC_LX6_STATUS__CORE1_GRBMT_BUSY_MASK 0x00000080L +#define RLC_LX6_STATUS__GRBMT_BUSY_MASK 0x00000100L +//RLC_LX6_FW_STATUS +#define RLC_LX6_FW_STATUS__STATUS__SHIFT 0x0 +#define RLC_LX6_FW_STATUS__STATUS_MASK 0xFFFFFFFFL +//RLC_LX6_FW_VERSION +#define RLC_LX6_FW_VERSION__VERSION__SHIFT 0x0 +#define RLC_LX6_FW_VERSION__VERSION_MASK 0xFFFFFFFFL +//RLC_XT_CORE_STATUS +#define RLC_XT_CORE_STATUS__P_WAIT_MODE__SHIFT 0x0 +#define RLC_XT_CORE_STATUS__P_FATAL_ERROR__SHIFT 0x1 +#define RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR__SHIFT 0x2 +#define RLC_XT_CORE_STATUS__P_WAIT_MODE_MASK 0x00000001L +#define RLC_XT_CORE_STATUS__P_FATAL_ERROR_MASK 0x00000002L +#define RLC_XT_CORE_STATUS__DOUBLE_EXCEPTION_ERROR_MASK 0x00000004L +//RLC_XT_CORE_INTERRUPT +#define RLC_XT_CORE_INTERRUPT__EXTINT1__SHIFT 0x0 +#define RLC_XT_CORE_INTERRUPT__EXTINT2__SHIFT 0x1a +#define RLC_XT_CORE_INTERRUPT__NMI__SHIFT 0x1b +#define RLC_XT_CORE_INTERRUPT__EXTINT1_MASK 0x03FFFFFFL +#define RLC_XT_CORE_INTERRUPT__EXTINT2_MASK 0x04000000L +#define RLC_XT_CORE_INTERRUPT__NMI_MASK 0x08000000L +//RLC_XT_CORE_FAULT_INFO +#define RLC_XT_CORE_FAULT_INFO__FAULT_INFO__SHIFT 0x0 +#define RLC_XT_CORE_FAULT_INFO__FAULT_INFO_MASK 0xFFFFFFFFL +//RLC_XT_CORE_ALT_RESET_VEC +#define RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC__SHIFT 0x0 +#define RLC_XT_CORE_ALT_RESET_VEC__ALT_RESET_VEC_MASK 0xFFFFFFFFL +//RLC_XT_CORE_RESERVED +#define RLC_XT_CORE_RESERVED__RESERVED__SHIFT 0x0 +#define RLC_XT_CORE_RESERVED__RESERVED_MASK 0xFFFFFFFFL +//RLC_XT_INT_VEC_FORCE +#define RLC_XT_INT_VEC_FORCE__NUM_0__SHIFT 0x0 +#define RLC_XT_INT_VEC_FORCE__NUM_1__SHIFT 0x1 +#define RLC_XT_INT_VEC_FORCE__NUM_2__SHIFT 0x2 +#define RLC_XT_INT_VEC_FORCE__NUM_3__SHIFT 0x3 +#define RLC_XT_INT_VEC_FORCE__NUM_4__SHIFT 0x4 +#define RLC_XT_INT_VEC_FORCE__NUM_5__SHIFT 0x5 +#define RLC_XT_INT_VEC_FORCE__NUM_6__SHIFT 0x6 +#define RLC_XT_INT_VEC_FORCE__NUM_7__SHIFT 0x7 +#define RLC_XT_INT_VEC_FORCE__NUM_8__SHIFT 0x8 +#define RLC_XT_INT_VEC_FORCE__NUM_9__SHIFT 0x9 +#define RLC_XT_INT_VEC_FORCE__NUM_10__SHIFT 0xa +#define RLC_XT_INT_VEC_FORCE__NUM_11__SHIFT 0xb +#define RLC_XT_INT_VEC_FORCE__NUM_12__SHIFT 0xc +#define RLC_XT_INT_VEC_FORCE__NUM_13__SHIFT 0xd +#define RLC_XT_INT_VEC_FORCE__NUM_14__SHIFT 0xe +#define RLC_XT_INT_VEC_FORCE__NUM_15__SHIFT 0xf +#define RLC_XT_INT_VEC_FORCE__NUM_16__SHIFT 0x10 +#define RLC_XT_INT_VEC_FORCE__NUM_17__SHIFT 0x11 +#define RLC_XT_INT_VEC_FORCE__NUM_18__SHIFT 0x12 +#define RLC_XT_INT_VEC_FORCE__NUM_19__SHIFT 0x13 +#define RLC_XT_INT_VEC_FORCE__NUM_20__SHIFT 0x14 +#define RLC_XT_INT_VEC_FORCE__NUM_21__SHIFT 0x15 +#define RLC_XT_INT_VEC_FORCE__NUM_22__SHIFT 0x16 +#define RLC_XT_INT_VEC_FORCE__NUM_23__SHIFT 0x17 +#define RLC_XT_INT_VEC_FORCE__NUM_24__SHIFT 0x18 +#define RLC_XT_INT_VEC_FORCE__NUM_25__SHIFT 0x19 +#define RLC_XT_INT_VEC_FORCE__NUM_0_MASK 0x00000001L +#define RLC_XT_INT_VEC_FORCE__NUM_1_MASK 0x00000002L +#define RLC_XT_INT_VEC_FORCE__NUM_2_MASK 0x00000004L +#define RLC_XT_INT_VEC_FORCE__NUM_3_MASK 0x00000008L +#define RLC_XT_INT_VEC_FORCE__NUM_4_MASK 0x00000010L +#define RLC_XT_INT_VEC_FORCE__NUM_5_MASK 0x00000020L +#define RLC_XT_INT_VEC_FORCE__NUM_6_MASK 0x00000040L +#define RLC_XT_INT_VEC_FORCE__NUM_7_MASK 0x00000080L +#define RLC_XT_INT_VEC_FORCE__NUM_8_MASK 0x00000100L +#define RLC_XT_INT_VEC_FORCE__NUM_9_MASK 0x00000200L +#define RLC_XT_INT_VEC_FORCE__NUM_10_MASK 0x00000400L +#define RLC_XT_INT_VEC_FORCE__NUM_11_MASK 0x00000800L +#define RLC_XT_INT_VEC_FORCE__NUM_12_MASK 0x00001000L +#define RLC_XT_INT_VEC_FORCE__NUM_13_MASK 0x00002000L +#define RLC_XT_INT_VEC_FORCE__NUM_14_MASK 0x00004000L +#define RLC_XT_INT_VEC_FORCE__NUM_15_MASK 0x00008000L +#define RLC_XT_INT_VEC_FORCE__NUM_16_MASK 0x00010000L +#define RLC_XT_INT_VEC_FORCE__NUM_17_MASK 0x00020000L +#define RLC_XT_INT_VEC_FORCE__NUM_18_MASK 0x00040000L +#define RLC_XT_INT_VEC_FORCE__NUM_19_MASK 0x00080000L +#define RLC_XT_INT_VEC_FORCE__NUM_20_MASK 0x00100000L +#define RLC_XT_INT_VEC_FORCE__NUM_21_MASK 0x00200000L +#define RLC_XT_INT_VEC_FORCE__NUM_22_MASK 0x00400000L +#define RLC_XT_INT_VEC_FORCE__NUM_23_MASK 0x00800000L +#define RLC_XT_INT_VEC_FORCE__NUM_24_MASK 0x01000000L +#define RLC_XT_INT_VEC_FORCE__NUM_25_MASK 0x02000000L +//RLC_XT_INT_VEC_CLEAR +#define RLC_XT_INT_VEC_CLEAR__NUM_0__SHIFT 0x0 +#define RLC_XT_INT_VEC_CLEAR__NUM_1__SHIFT 0x1 +#define RLC_XT_INT_VEC_CLEAR__NUM_2__SHIFT 0x2 +#define RLC_XT_INT_VEC_CLEAR__NUM_3__SHIFT 0x3 +#define RLC_XT_INT_VEC_CLEAR__NUM_4__SHIFT 0x4 +#define RLC_XT_INT_VEC_CLEAR__NUM_5__SHIFT 0x5 +#define RLC_XT_INT_VEC_CLEAR__NUM_6__SHIFT 0x6 +#define RLC_XT_INT_VEC_CLEAR__NUM_7__SHIFT 0x7 +#define RLC_XT_INT_VEC_CLEAR__NUM_8__SHIFT 0x8 +#define RLC_XT_INT_VEC_CLEAR__NUM_9__SHIFT 0x9 +#define RLC_XT_INT_VEC_CLEAR__NUM_10__SHIFT 0xa +#define RLC_XT_INT_VEC_CLEAR__NUM_11__SHIFT 0xb +#define RLC_XT_INT_VEC_CLEAR__NUM_12__SHIFT 0xc +#define RLC_XT_INT_VEC_CLEAR__NUM_13__SHIFT 0xd +#define RLC_XT_INT_VEC_CLEAR__NUM_14__SHIFT 0xe +#define RLC_XT_INT_VEC_CLEAR__NUM_15__SHIFT 0xf +#define RLC_XT_INT_VEC_CLEAR__NUM_16__SHIFT 0x10 +#define RLC_XT_INT_VEC_CLEAR__NUM_17__SHIFT 0x11 +#define RLC_XT_INT_VEC_CLEAR__NUM_18__SHIFT 0x12 +#define RLC_XT_INT_VEC_CLEAR__NUM_19__SHIFT 0x13 +#define RLC_XT_INT_VEC_CLEAR__NUM_20__SHIFT 0x14 +#define RLC_XT_INT_VEC_CLEAR__NUM_21__SHIFT 0x15 +#define RLC_XT_INT_VEC_CLEAR__NUM_22__SHIFT 0x16 +#define RLC_XT_INT_VEC_CLEAR__NUM_23__SHIFT 0x17 +#define RLC_XT_INT_VEC_CLEAR__NUM_24__SHIFT 0x18 +#define RLC_XT_INT_VEC_CLEAR__NUM_25__SHIFT 0x19 +#define RLC_XT_INT_VEC_CLEAR__NUM_0_MASK 0x00000001L +#define RLC_XT_INT_VEC_CLEAR__NUM_1_MASK 0x00000002L +#define RLC_XT_INT_VEC_CLEAR__NUM_2_MASK 0x00000004L +#define RLC_XT_INT_VEC_CLEAR__NUM_3_MASK 0x00000008L +#define RLC_XT_INT_VEC_CLEAR__NUM_4_MASK 0x00000010L +#define RLC_XT_INT_VEC_CLEAR__NUM_5_MASK 0x00000020L +#define RLC_XT_INT_VEC_CLEAR__NUM_6_MASK 0x00000040L +#define RLC_XT_INT_VEC_CLEAR__NUM_7_MASK 0x00000080L +#define RLC_XT_INT_VEC_CLEAR__NUM_8_MASK 0x00000100L +#define RLC_XT_INT_VEC_CLEAR__NUM_9_MASK 0x00000200L +#define RLC_XT_INT_VEC_CLEAR__NUM_10_MASK 0x00000400L +#define RLC_XT_INT_VEC_CLEAR__NUM_11_MASK 0x00000800L +#define RLC_XT_INT_VEC_CLEAR__NUM_12_MASK 0x00001000L +#define RLC_XT_INT_VEC_CLEAR__NUM_13_MASK 0x00002000L +#define RLC_XT_INT_VEC_CLEAR__NUM_14_MASK 0x00004000L +#define RLC_XT_INT_VEC_CLEAR__NUM_15_MASK 0x00008000L +#define RLC_XT_INT_VEC_CLEAR__NUM_16_MASK 0x00010000L +#define RLC_XT_INT_VEC_CLEAR__NUM_17_MASK 0x00020000L +#define RLC_XT_INT_VEC_CLEAR__NUM_18_MASK 0x00040000L +#define RLC_XT_INT_VEC_CLEAR__NUM_19_MASK 0x00080000L +#define RLC_XT_INT_VEC_CLEAR__NUM_20_MASK 0x00100000L +#define RLC_XT_INT_VEC_CLEAR__NUM_21_MASK 0x00200000L +#define RLC_XT_INT_VEC_CLEAR__NUM_22_MASK 0x00400000L +#define RLC_XT_INT_VEC_CLEAR__NUM_23_MASK 0x00800000L +#define RLC_XT_INT_VEC_CLEAR__NUM_24_MASK 0x01000000L +#define RLC_XT_INT_VEC_CLEAR__NUM_25_MASK 0x02000000L +//RLC_XT_INT_VEC_MUX_SEL +#define RLC_XT_INT_VEC_MUX_SEL__MUX_SEL__SHIFT 0x0 +#define RLC_XT_INT_VEC_MUX_SEL__MUX_SEL_MASK 0x0000001FL +//RLC_XT_INT_VEC_MUX_INT_SEL +#define RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL__SHIFT 0x0 +#define RLC_XT_INT_VEC_MUX_INT_SEL__INT_SEL_MASK 0x0000003FL +//RLC_GPU_CLOCK_COUNT_SPM_LSB +#define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_SPM_LSB__GPU_CLOCKS_LSB_MASK 0xFFFFFFFFL +//RLC_GPU_CLOCK_COUNT_SPM_MSB +#define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_SPM_MSB__GPU_CLOCKS_MSB_MASK 0xFFFFFFFFL +//RLC_SPM_THREAD_TRACE_CTRL +#define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN__SHIFT 0x0 +#define RLC_SPM_THREAD_TRACE_CTRL__THREAD_TRACE_INT_EN_MASK 0x00000001L +//RLC_SPP_CAM_ADDR +#define RLC_SPP_CAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPP_CAM_ADDR__ADDR_MASK 0x000000FFL +//RLC_SPP_CAM_DATA +#define RLC_SPP_CAM_DATA__DATA__SHIFT 0x0 +#define RLC_SPP_CAM_DATA__TAG__SHIFT 0x8 +#define RLC_SPP_CAM_DATA__DATA_MASK 0x000000FFL +#define RLC_SPP_CAM_DATA__TAG_MASK 0xFFFFFF00L +//RLC_SPP_CAM_EXT_ADDR +#define RLC_SPP_CAM_EXT_ADDR__ADDR__SHIFT 0x0 +#define RLC_SPP_CAM_EXT_ADDR__ADDR_MASK 0x000000FFL +//RLC_SPP_CAM_EXT_DATA +#define RLC_SPP_CAM_EXT_DATA__VALID__SHIFT 0x0 +#define RLC_SPP_CAM_EXT_DATA__LOCK__SHIFT 0x1 +#define RLC_SPP_CAM_EXT_DATA__VALID_MASK 0x00000001L +#define RLC_SPP_CAM_EXT_DATA__LOCK_MASK 0x00000002L +//RLC_CPAXI_DOORBELL_MON_CTRL +#define RLC_CPAXI_DOORBELL_MON_CTRL__EN__SHIFT 0x0 +#define RLC_CPAXI_DOORBELL_MON_CTRL__ID__SHIFT 0x1 +#define RLC_CPAXI_DOORBELL_MON_CTRL__EN_MASK 0x00000001L +#define RLC_CPAXI_DOORBELL_MON_CTRL__ID_MASK 0x0000003EL +//RLC_CPAXI_DOORBELL_MON_STAT +#define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH__SHIFT 0x0 +#define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR__SHIFT 0x1 +#define RLC_CPAXI_DOORBELL_MON_STAT__ADDR__SHIFT 0x2 +#define RLC_CPAXI_DOORBELL_MON_STAT__ID_MATCH_MASK 0x00000001L +#define RLC_CPAXI_DOORBELL_MON_STAT__MATCH_CLEAR_MASK 0x00000002L +#define RLC_CPAXI_DOORBELL_MON_STAT__ADDR_MASK 0x0FFFFFFCL +//RLC_CPAXI_DOORBELL_MON_DATA_LSB +#define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA__SHIFT 0x0 +#define RLC_CPAXI_DOORBELL_MON_DATA_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_CPAXI_DOORBELL_MON_DATA_MSB +#define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA__SHIFT 0x0 +#define RLC_CPAXI_DOORBELL_MON_DATA_MSB__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_RANGE +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED__SHIFT 0x0 +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR__SHIFT 0x2 +#define RLC_XT_DOORBELL_RANGE__RESERVED_15_12__SHIFT 0xc +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED__SHIFT 0x10 +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR__SHIFT 0x12 +#define RLC_XT_DOORBELL_RANGE__RESERVED_31_28__SHIFT 0x1c +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_RESERVED_MASK 0x00000003L +#define RLC_XT_DOORBELL_RANGE__LOWER_ADDR_MASK 0x00000FFCL +#define RLC_XT_DOORBELL_RANGE__RESERVED_15_12_MASK 0x0000F000L +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_RESERVED_MASK 0x00030000L +#define RLC_XT_DOORBELL_RANGE__UPPER_ADDR_MASK 0x0FFC0000L +#define RLC_XT_DOORBELL_RANGE__RESERVED_31_28_MASK 0xF0000000L +//RLC_XT_DOORBELL_CNTL +#define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE__SHIFT 0x0 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE__SHIFT 0x2 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE__SHIFT 0x4 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE__SHIFT 0x6 +#define RLC_XT_DOORBELL_CNTL__RESERVED_15_8__SHIFT 0x8 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID__SHIFT 0x10 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN__SHIFT 0x15 +#define RLC_XT_DOORBELL_CNTL__RESERVED_31_22__SHIFT 0x16 +#define RLC_XT_DOORBELL_CNTL__DOORBELL_0_MODE_MASK 0x00000003L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_1_MODE_MASK 0x0000000CL +#define RLC_XT_DOORBELL_CNTL__DOORBELL_2_MODE_MASK 0x00000030L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_3_MODE_MASK 0x000000C0L +#define RLC_XT_DOORBELL_CNTL__RESERVED_15_8_MASK 0x0000FF00L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_MASK 0x001F0000L +#define RLC_XT_DOORBELL_CNTL__DOORBELL_ID_EN_MASK 0x00200000L +#define RLC_XT_DOORBELL_CNTL__RESERVED_31_22_MASK 0xFFC00000L +//RLC_XT_DOORBELL_STAT +#define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID__SHIFT 0x0 +#define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID__SHIFT 0x1 +#define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID__SHIFT 0x2 +#define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID__SHIFT 0x3 +#define RLC_XT_DOORBELL_STAT__DOORBELL_0_VALID_MASK 0x00000001L +#define RLC_XT_DOORBELL_STAT__DOORBELL_1_VALID_MASK 0x00000002L +#define RLC_XT_DOORBELL_STAT__DOORBELL_2_VALID_MASK 0x00000004L +#define RLC_XT_DOORBELL_STAT__DOORBELL_3_VALID_MASK 0x00000008L +//RLC_XT_DOORBELL_0_DATA_LO +#define RLC_XT_DOORBELL_0_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_0_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_0_DATA_HI +#define RLC_XT_DOORBELL_0_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_0_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_1_DATA_LO +#define RLC_XT_DOORBELL_1_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_1_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_1_DATA_HI +#define RLC_XT_DOORBELL_1_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_1_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_2_DATA_LO +#define RLC_XT_DOORBELL_2_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_2_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_2_DATA_HI +#define RLC_XT_DOORBELL_2_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_2_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_3_DATA_LO +#define RLC_XT_DOORBELL_3_DATA_LO__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_3_DATA_LO__DATA_MASK 0xFFFFFFFFL +//RLC_XT_DOORBELL_3_DATA_HI +#define RLC_XT_DOORBELL_3_DATA_HI__DATA__SHIFT 0x0 +#define RLC_XT_DOORBELL_3_DATA_HI__DATA_MASK 0xFFFFFFFFL +//RLC_MEM_SLP_CNTL +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE__SHIFT 0x2 +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE__SHIFT 0x3 +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE__SHIFT 0x4 +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE__SHIFT 0x5 +#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x6 +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE__SHIFT 0x18 +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE__SHIFT 0x19 +#define RLC_MEM_SLP_CNTL__RLC_DMA_MEM_LS_OVERRIDE__SHIFT 0x1a +#define RLC_MEM_SLP_CNTL__RLC_DMA_MEM_DS_OVERRIDE__SHIFT 0x1b +#define RLC_MEM_SLP_CNTL__RLC_TC_MEM_LS_OVERRIDE__SHIFT 0x1c +#define RLC_MEM_SLP_CNTL__RLC_TC_MEM_DS_OVERRIDE__SHIFT 0x1d +#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x1e +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x00000001L +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x00000002L +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_LS_OVERRIDE_MASK 0x00000004L +#define RLC_MEM_SLP_CNTL__RLC_SRM_MEM_DS_OVERRIDE_MASK 0x00000008L +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_LS_OVERRIDE_MASK 0x00000010L +#define RLC_MEM_SLP_CNTL__RLC_SPM_MEM_DS_OVERRIDE_MASK 0x00000020L +#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x00000040L +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x00000080L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0x0000FF00L +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0x00FF0000L +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_LS_OVERRIDE_MASK 0x01000000L +#define RLC_MEM_SLP_CNTL__RLC_SPP_MEM_DS_OVERRIDE_MASK 0x02000000L +#define RLC_MEM_SLP_CNTL__RLC_DMA_MEM_LS_OVERRIDE_MASK 0x04000000L +#define RLC_MEM_SLP_CNTL__RLC_DMA_MEM_DS_OVERRIDE_MASK 0x08000000L +#define RLC_MEM_SLP_CNTL__RLC_TC_MEM_LS_OVERRIDE_MASK 0x10000000L +#define RLC_MEM_SLP_CNTL__RLC_TC_MEM_DS_OVERRIDE_MASK 0x20000000L +#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xC0000000L +//RLC_RLCV_SAFE_MODE +#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_SMU_SAFE_MODE +#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SMU_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_RLCV_COMMAND +#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 +#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 +#define RLC_RLCV_COMMAND__CMD_MASK 0x0000000FL +#define RLC_RLCV_COMMAND__RESERVED_MASK 0xFFFFFFF0L +//RLC_SMU_MESSAGE +#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 +#define RLC_SMU_MESSAGE__CMD_MASK 0xFFFFFFFFL +//RLC_SMU_MESSAGE_1 +#define RLC_SMU_MESSAGE_1__CMD__SHIFT 0x0 +#define RLC_SMU_MESSAGE_1__CMD_MASK 0xFFFFFFFFL +//RLC_SMU_MESSAGE_2 +#define RLC_SMU_MESSAGE_2__CMD__SHIFT 0x0 +#define RLC_SMU_MESSAGE_2__CMD_MASK 0xFFFFFFFFL +//RLC_SRM_GPM_COMMAND +#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 +#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x12 +#define RLC_SRM_GPM_COMMAND__RESERVED__SHIFT 0x1f +#define RLC_SRM_GPM_COMMAND__OP_MASK 0x00000001L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x00000002L +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x0000001CL +#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x0003FFE0L +#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x7FFC0000L +#define RLC_SRM_GPM_COMMAND__RESERVED_MASK 0x80000000L +//RLC_SRM_GPM_ABORT +#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 +#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 +#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x00000001L +#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xFFFFFFFEL +//RLC_SMU_COMMAND +#define RLC_SMU_COMMAND__CMD__SHIFT 0x0 +#define RLC_SMU_COMMAND__CMD_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_1 +#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_2 +#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_3 +#define RLC_SMU_ARGUMENT_3__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_3__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_4 +#define RLC_SMU_ARGUMENT_4__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_4__ARG_MASK 0xFFFFFFFFL +//RLC_SMU_ARGUMENT_5 +#define RLC_SMU_ARGUMENT_5__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_5__ARG_MASK 0xFFFFFFFFL +//RLC_IMU_BOOTLOAD_ADDR_HI +#define RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define RLC_IMU_BOOTLOAD_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//RLC_IMU_BOOTLOAD_ADDR_LO +#define RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO__SHIFT 0x0 +#define RLC_IMU_BOOTLOAD_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL +//RLC_IMU_BOOTLOAD_SIZE +#define RLC_IMU_BOOTLOAD_SIZE__SIZE__SHIFT 0x0 +#define RLC_IMU_BOOTLOAD_SIZE__RESERVED__SHIFT 0x1a +#define RLC_IMU_BOOTLOAD_SIZE__SIZE_MASK 0x03FFFFFFL +#define RLC_IMU_BOOTLOAD_SIZE__RESERVED_MASK 0xFC000000L +//RLC_IMU_MISC +#define RLC_IMU_MISC__THROTTLE_GFX__SHIFT 0x0 +#define RLC_IMU_MISC__EARLY_MGCG__SHIFT 0x1 +#define RLC_IMU_MISC__RESERVED__SHIFT 0x2 +#define RLC_IMU_MISC__THROTTLE_GFX_MASK 0x00000001L +#define RLC_IMU_MISC__EARLY_MGCG_MASK 0x00000002L +#define RLC_IMU_MISC__RESERVED_MASK 0xFFFFFFFCL +//RLC_IMU_RESET_VECTOR +#define RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT__SHIFT 0x0 +#define RLC_IMU_RESET_VECTOR__VDDGFX_EXIT__SHIFT 0x1 +#define RLC_IMU_RESET_VECTOR__VECTOR__SHIFT 0x2 +#define RLC_IMU_RESET_VECTOR__RESERVED__SHIFT 0x8 +#define RLC_IMU_RESET_VECTOR__COLD_BOOT_EXIT_MASK 0x00000001L +#define RLC_IMU_RESET_VECTOR__VDDGFX_EXIT_MASK 0x00000002L +#define RLC_IMU_RESET_VECTOR__VECTOR_MASK 0x000000FCL +#define RLC_IMU_RESET_VECTOR__RESERVED_MASK 0xFFFFFF00L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_rlcsdec +//RLC_RLCS_DEC_START +//RLC_RLCS_DEC_DUMP_ADDR +//RLC_RLCS_EXCEPTION_REG_1 +#define RLC_RLCS_EXCEPTION_REG_1__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_1__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_1__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_1__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_EXCEPTION_REG_2 +#define RLC_RLCS_EXCEPTION_REG_2__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_2__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_2__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_2__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_EXCEPTION_REG_3 +#define RLC_RLCS_EXCEPTION_REG_3__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_3__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_3__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_3__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_EXCEPTION_REG_4 +#define RLC_RLCS_EXCEPTION_REG_4__ADDR__SHIFT 0x0 +#define RLC_RLCS_EXCEPTION_REG_4__RESERVED__SHIFT 0x12 +#define RLC_RLCS_EXCEPTION_REG_4__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_EXCEPTION_REG_4__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_FENCE_CNTL +#define RLC_RLCS_FENCE_CNTL__MODE__SHIFT 0x0 +#define RLC_RLCS_FENCE_CNTL__SRC_ID_EXC_EN__SHIFT 0x2 +#define RLC_RLCS_FENCE_CNTL__SRC_ID_EXC__SHIFT 0x4 +#define RLC_RLCS_FENCE_CNTL__MODE_MASK 0x00000003L +#define RLC_RLCS_FENCE_CNTL__SRC_ID_EXC_EN_MASK 0x00000004L +#define RLC_RLCS_FENCE_CNTL__SRC_ID_EXC_MASK 0x000000F0L +//RLC_RLCS_CGCG_REQUEST +#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST__SHIFT 0x0 +#define RLC_RLCS_CGCG_REQUEST__RESERVED__SHIFT 0x1 +#define RLC_RLCS_CGCG_REQUEST__CGCG_REQUEST_MASK 0x00000001L +#define RLC_RLCS_CGCG_REQUEST__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_CGCG_STATUS +#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS__SHIFT 0x0 +#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS__SHIFT 0x2 +#define RLC_RLCS_CGCG_STATUS__RESERVED__SHIFT 0x3 +#define RLC_RLCS_CGCG_STATUS__CGCG_RAMP_STATUS_MASK 0x00000003L +#define RLC_RLCS_CGCG_STATUS__GFX_CLK_STATUS_MASK 0x00000004L +#define RLC_RLCS_CGCG_STATUS__RESERVED_MASK 0xFFFFFFF8L +//RLC_RLCS_SOC_DS_CNTL +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW__SHIFT 0x0 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_4_3__SHIFT 0x3 +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_5__SHIFT 0x5 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x10 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x11 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK__SHIFT 0x12 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK__SHIFT 0x13 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK__SHIFT 0x14 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK__SHIFT 0x15 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK__SHIFT 0x16 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK__SHIFT 0x17 +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_31_24__SHIFT 0x18 +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_ALLOW_MASK 0x00000001L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_4_3_MASK 0x00000018L +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_5_MASK 0x00000020L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00010000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00020000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_2_BUSY_MASK_MASK 0x00040000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_3_BUSY_MASK_MASK 0x00080000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_4_BUSY_MASK_MASK 0x00100000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_5_BUSY_MASK_MASK 0x00200000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_6_BUSY_MASK_MASK 0x00400000L +#define RLC_RLCS_SOC_DS_CNTL__SOC_CLK_DS_SDMA_7_BUSY_MASK_MASK 0x00800000L +#define RLC_RLCS_SOC_DS_CNTL__RESERVED_31_24_MASK 0xFF000000L +//RLC_RLCS_GFX_DS_CNTL +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW__SHIFT 0x0 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK__SHIFT 0x1 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK__SHIFT 0x2 +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_4_3__SHIFT 0x3 +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_5__SHIFT 0x5 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK__SHIFT 0x6 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK__SHIFT 0x7 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK__SHIFT 0x8 +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_15_9__SHIFT 0x9 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK__SHIFT 0x10 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK__SHIFT 0x11 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK__SHIFT 0x12 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK__SHIFT 0x13 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK__SHIFT 0x14 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK__SHIFT 0x15 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK__SHIFT 0x16 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK__SHIFT 0x17 +#define RLC_RLCS_GFX_DS_CNTL__RESERVED__SHIFT 0x18 +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_ALLOW_MASK 0x00000001L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_RLC_BUSY_MASK_MASK 0x00000002L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_CP_BUSY_MASK_MASK 0x00000004L +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_4_3_MASK 0x00000018L +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_5_MASK 0x00000020L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_GFX_PWR_STALLED_MASK_MASK 0x00000040L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_NON3D_PWR_STALLED_MASK_MASK 0x00000080L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_IMU_DISABLE_MASK_MASK 0x00000100L +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_15_9_MASK 0x0000FE00L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_0_BUSY_MASK_MASK 0x00010000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_1_BUSY_MASK_MASK 0x00020000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_2_BUSY_MASK_MASK 0x00040000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_3_BUSY_MASK_MASK 0x00080000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_4_BUSY_MASK_MASK 0x00100000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_5_BUSY_MASK_MASK 0x00200000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_6_BUSY_MASK_MASK 0x00400000L +#define RLC_RLCS_GFX_DS_CNTL__GFX_CLK_DS_SDMA_7_BUSY_MASK_MASK 0x00800000L +#define RLC_RLCS_GFX_DS_CNTL__RESERVED_MASK 0xFF000000L +//RLC_RLCS_GFX_DS_ALLOW_MASK_CNTL +//RLC_GPM_STAT +#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 +#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 +#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc +#define RLC_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd +#define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe +#define RLC_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf +#define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 +#define RLC_GPM_STAT__CMP_power_status__SHIFT 0x12 +#define RLC_GPM_STAT__RESERVED_1__SHIFT 0x13 +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 +#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 +#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_GPM_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L +#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L +#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L +#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L +#define RLC_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L +#define RLC_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L +#define RLC_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L +#define RLC_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L +#define RLC_GPM_STAT__CMP_power_status_MASK 0x00040000L +#define RLC_GPM_STAT__RESERVED_1_MASK 0x00180000L +#define RLC_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L +#define RLC_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L +#define RLC_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L +#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L +//RLC_RLCS_GPM_STAT +#define RLC_RLCS_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 +#define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 +#define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 +#define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 +#define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 +#define RLC_RLCS_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 +#define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa +#define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb +#define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP__SHIFT 0xd +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN__SHIFT 0xe +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP__SHIFT 0xf +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN__SHIFT 0x10 +#define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 +#define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS__SHIFT 0x12 +#define RLC_RLCS_GPM_STAT__RESERVED_1__SHIFT 0x13 +#define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS__SHIFT 0x15 +#define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE__SHIFT 0x16 +#define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS__SHIFT 0x17 +#define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_RLCS_GPM_STAT__RLC_BUSY_MASK 0x00000001L +#define RLC_RLCS_GPM_STAT__GFX_POWER_STATUS_MASK 0x00000002L +#define RLC_RLCS_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x00000004L +#define RLC_RLCS_GPM_STAT__GFX_LS_STATUS_MASK 0x00000008L +#define RLC_RLCS_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x00000010L +#define RLC_RLCS_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x00000020L +#define RLC_RLCS_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x00000040L +#define RLC_RLCS_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x00000080L +#define RLC_RLCS_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x00000100L +#define RLC_RLCS_GPM_STAT__SAVING_REGISTERS_MASK 0x00000200L +#define RLC_RLCS_GPM_STAT__RESTORING_REGISTERS_MASK 0x00000400L +#define RLC_RLCS_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x00000800L +#define RLC_RLCS_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x00001000L +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_UP_MASK 0x00002000L +#define RLC_RLCS_GPM_STAT__STATIC_WGP_POWERING_DOWN_MASK 0x00004000L +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_UP_MASK 0x00008000L +#define RLC_RLCS_GPM_STAT__DYN_WGP_POWERING_DOWN_MASK 0x00010000L +#define RLC_RLCS_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x00020000L +#define RLC_RLCS_GPM_STAT__CMP_POWER_STATUS_MASK 0x00040000L +#define RLC_RLCS_GPM_STAT__RESERVED_1_MASK 0x00180000L +#define RLC_RLCS_GPM_STAT__MGCG_OVERRIDE_STATUS_MASK 0x00200000L +#define RLC_RLCS_GPM_STAT__RLC_EXEC_ROM_CODE_MASK 0x00400000L +#define RLC_RLCS_GPM_STAT__FGCG_OVERRIDE_STATUS_MASK 0x00800000L +#define RLC_RLCS_GPM_STAT__PG_ERROR_STATUS_MASK 0xFF000000L +//RLC_RLCS_ABORTED_PD_SEQUENCE +#define RLC_RLCS_ABORTED_PD_SEQUENCE__APS__SHIFT 0x0 +#define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED__SHIFT 0x10 +#define RLC_RLCS_ABORTED_PD_SEQUENCE__APS_MASK 0x0000FFFFL +#define RLC_RLCS_ABORTED_PD_SEQUENCE__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_IOV_CMD_STATUS +#define RLC_RLCS_IOV_CMD_STATUS__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_CMD_STATUS__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IOV_CNTX_LOC_SIZE +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED__SHIFT 0x8 +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__DATA_MASK 0x000000FFL +#define RLC_RLCS_IOV_CNTX_LOC_SIZE__RESERVED_MASK 0xFFFFFF00L +//RLC_RLCS_IOV_SCH_BLOCK +#define RLC_RLCS_IOV_SCH_BLOCK__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_SCH_BLOCK__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IOV_VM_BUSY_STATUS +#define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA__SHIFT 0x0 +#define RLC_RLCS_IOV_VM_BUSY_STATUS__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GPM_STAT_2 +#define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR__SHIFT 0x0 +#define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED__SHIFT 0x1 +#define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS__SHIFT 0x2 +#define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS__SHIFT 0x3 +#define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS__SHIFT 0x4 +#define RLC_RLCS_GPM_STAT_2__RESERVED__SHIFT 0x5 +#define RLC_RLCS_GPM_STAT_2__TC_TRANS_ERROR_MASK 0x00000001L +#define RLC_RLCS_GPM_STAT_2__RLC_PWR_NON3D_STALLED_MASK 0x00000002L +#define RLC_RLCS_GPM_STAT_2__GFX_PWR_STALLED_STATUS_MASK 0x00000004L +#define RLC_RLCS_GPM_STAT_2__GFX_ULV_STATUS_MASK 0x00000008L +#define RLC_RLCS_GPM_STAT_2__GFX_GENERAL_STATUS_MASK 0x00000010L +#define RLC_RLCS_GPM_STAT_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_RLCS_GRBM_SOFT_RESET +#define RLC_RLCS_GRBM_SOFT_RESET__RESET__SHIFT 0x0 +#define RLC_RLCS_GRBM_SOFT_RESET__RESERVED__SHIFT 0x1 +#define RLC_RLCS_GRBM_SOFT_RESET__RESET_MASK 0x00000001L +#define RLC_RLCS_GRBM_SOFT_RESET__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_PG_CHANGE_STATUS +#define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED__SHIFT 0x0 +#define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED__SHIFT 0x1 +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED__SHIFT 0x2 +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED__SHIFT 0x3 +#define RLC_RLCS_PG_CHANGE_STATUS__RESERVED__SHIFT 0x4 +#define RLC_RLCS_PG_CHANGE_STATUS__PG_CNTL_CHANGED_MASK 0x00000001L +#define RLC_RLCS_PG_CHANGE_STATUS__PG_REG_CHANGED_MASK 0x00000002L +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_STATUS_CHANGED_MASK 0x00000004L +#define RLC_RLCS_PG_CHANGE_STATUS__DYN_PG_REQ_CHANGED_MASK 0x00000008L +#define RLC_RLCS_PG_CHANGE_STATUS__RESERVED_MASK 0xFFFFFFF0L +//RLC_RLCS_PG_CHANGE_READ +#define RLC_RLCS_PG_CHANGE_READ__RESERVED__SHIFT 0x0 +#define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED__SHIFT 0x1 +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED__SHIFT 0x2 +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED__SHIFT 0x3 +#define RLC_RLCS_PG_CHANGE_READ__RESERVED_MASK 0x00000001L +#define RLC_RLCS_PG_CHANGE_READ__PG_REG_CHANGED_MASK 0x00000002L +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_STATUS_CHANGED_MASK 0x00000004L +#define RLC_RLCS_PG_CHANGE_READ__DYN_PG_REQ_CHANGED_MASK 0x00000008L +//RLC_RLCS_IH_SEMAPHORE +#define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID__SHIFT 0x0 +#define RLC_RLCS_IH_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL +//RLC_RLCS_IH_COOKIE_SEMAPHORE +#define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID__SHIFT 0x0 +#define RLC_RLCS_IH_COOKIE_SEMAPHORE__CLIENT_ID_MASK 0x0000001FL +//RLC_RLCS_CP_INT_CTRL_1 +#define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK__SHIFT 0x0 +#define RLC_RLCS_CP_INT_CTRL_1__RESERVED__SHIFT 0x1 +#define RLC_RLCS_CP_INT_CTRL_1__INTERRUPT_ACK_MASK 0x00000001L +#define RLC_RLCS_CP_INT_CTRL_1__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_CP_INT_CTRL_2 +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN__SHIFT 0x0 +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN__SHIFT 0x1 +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE__SHIFT 0x2 +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE__SHIFT 0x3 +#define RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING__SHIFT 0x4 +#define RLC_RLCS_CP_INT_CTRL_2__RESERVED__SHIFT 0x5 +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_EN_MASK 0x00000001L +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_EN_MASK 0x00000002L +#define RLC_RLCS_CP_INT_CTRL_2__IDLE_AUTO_ACK_ACTIVE_MASK 0x00000004L +#define RLC_RLCS_CP_INT_CTRL_2__BUSY_AUTO_ACK_ACTIVE_MASK 0x00000008L +#define RLC_RLCS_CP_INT_CTRL_2__INTERRUPT_PENDING_MASK 0x00000010L +#define RLC_RLCS_CP_INT_CTRL_2__RESERVED_MASK 0xFFFFFFE0L +//RLC_RLCS_CP_INT_INFO_1 +#define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 +#define RLC_RLCS_CP_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL +//RLC_RLCS_CP_INT_INFO_2 +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 +#define RLC_RLCS_CP_INT_INFO_2__RESERVED__SHIFT 0x19 +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL +#define RLC_RLCS_CP_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L +#define RLC_RLCS_CP_INT_INFO_2__RESERVED_MASK 0xFE000000L +//RLC_RLCS_SPM_INT_CTRL +#define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK__SHIFT 0x0 +#define RLC_RLCS_SPM_INT_CTRL__RESERVED__SHIFT 0x1 +#define RLC_RLCS_SPM_INT_CTRL__INTERRUPT_ACK_MASK 0x00000001L +#define RLC_RLCS_SPM_INT_CTRL__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_SPM_INT_INFO_1 +#define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 +#define RLC_RLCS_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL +//RLC_RLCS_SPM_INT_INFO_2 +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 +#define RLC_RLCS_SPM_INT_INFO_2__RESERVED__SHIFT 0x19 +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL +#define RLC_RLCS_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x01FF0000L +#define RLC_RLCS_SPM_INT_INFO_2__RESERVED_MASK 0xFE000000L +//RLC_RLCS_DSM_TRIG +#define RLC_RLCS_DSM_TRIG__START__SHIFT 0x0 +#define RLC_RLCS_DSM_TRIG__RESERVED__SHIFT 0x1 +#define RLC_RLCS_DSM_TRIG__START_MASK 0x00000001L +#define RLC_RLCS_DSM_TRIG__RESERVED_MASK 0xFFFFFFFEL +//RLC_RLCS_BOOTLOAD_STATUS +#define RLC_RLCS_BOOTLOAD_STATUS__GFX_FUSE_DIST_DONE__SHIFT 0x0 +#define RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE__SHIFT 0x1 +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED__SHIFT 0x4 +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE__SHIFT 0x5 +#define RLC_RLCS_BOOTLOAD_STATUS__STATUS_6_30__SHIFT 0x6 +#define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE__SHIFT 0x1f +#define RLC_RLCS_BOOTLOAD_STATUS__GFX_FUSE_DIST_DONE_MASK 0x00000001L +#define RLC_RLCS_BOOTLOAD_STATUS__GFX_INIT_DONE_MASK 0x00000002L +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_LOADED_MASK 0x00000010L +#define RLC_RLCS_BOOTLOAD_STATUS__RLC_GPM_IRAM_DONE_MASK 0x00000020L +#define RLC_RLCS_BOOTLOAD_STATUS__STATUS_6_30_MASK 0x7FFFFFC0L +#define RLC_RLCS_BOOTLOAD_STATUS__BOOTLOAD_COMPLETE_MASK 0x80000000L +//RLC_RLCS_GRBM_IDLE_BUSY_STAT +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE__SHIFT 0x0 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY__SHIFT 0x10 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY__SHIFT 0x11 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY__SHIFT 0x12 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY__SHIFT 0x13 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY__SHIFT 0x14 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY__SHIFT 0x15 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY__SHIFT 0x16 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY__SHIFT 0x17 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED__SHIFT 0x18 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED__SHIFT 0x19 +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED__SHIFT 0x1a +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED__SHIFT 0x1b +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED__SHIFT 0x1c +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED__SHIFT 0x1d +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED__SHIFT 0x1e +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED__SHIFT 0x1f +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__GRBM_RLC_GC_STAT_IDLE_MASK 0x00000003L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_MASK 0x00010000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_MASK 0x00020000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_MASK 0x00040000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_MASK 0x00080000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_MASK 0x00100000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_MASK 0x00200000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_MASK 0x00400000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_MASK 0x00800000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_0_BUSY_CHANGED_MASK 0x01000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_1_BUSY_CHANGED_MASK 0x02000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_2_BUSY_CHANGED_MASK 0x04000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_3_BUSY_CHANGED_MASK 0x08000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_4_BUSY_CHANGED_MASK 0x10000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_5_BUSY_CHANGED_MASK 0x20000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_6_BUSY_CHANGED_MASK 0x40000000L +#define RLC_RLCS_GRBM_IDLE_BUSY_STAT__SDMA_7_BUSY_CHANGED_MASK 0x80000000L +//RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR__SHIFT 0x0 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR__SHIFT 0x1 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR__SHIFT 0x2 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR__SHIFT 0x3 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR__SHIFT 0x4 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR__SHIFT 0x5 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR__SHIFT 0x6 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR__SHIFT 0x7 +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA0_BUSY_INT_CLEAR_MASK 0x00000001L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA1_BUSY_INT_CLEAR_MASK 0x00000002L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA2_BUSY_INT_CLEAR_MASK 0x00000004L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA3_BUSY_INT_CLEAR_MASK 0x00000008L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA4_BUSY_INT_CLEAR_MASK 0x00000010L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA5_BUSY_INT_CLEAR_MASK 0x00000020L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA6_BUSY_INT_CLEAR_MASK 0x00000040L +#define RLC_RLCS_GRBM_IDLE_BUSY_INT_CNTL__SDMA7_BUSY_INT_CLEAR_MASK 0x00000080L +//RLC_RLCS_CMP_IDLE_CNTL +#define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR__SHIFT 0x0 +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST__SHIFT 0x1 +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE__SHIFT 0x2 +#define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS__SHIFT 0x3 +#define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT__SHIFT 0xb +#define RLC_RLCS_CMP_IDLE_CNTL__RESERVED__SHIFT 0x13 +#define RLC_RLCS_CMP_IDLE_CNTL__INT_CLEAR_MASK 0x00000001L +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_HYST_MASK 0x00000002L +#define RLC_RLCS_CMP_IDLE_CNTL__CMP_IDLE_MASK 0x00000004L +#define RLC_RLCS_CMP_IDLE_CNTL__MAX_HYSTERESIS_MASK 0x000007F8L +#define RLC_RLCS_CMP_IDLE_CNTL__HYSTERESIS_CNT_MASK 0x0007F800L +#define RLC_RLCS_CMP_IDLE_CNTL__RESERVED_MASK 0xFFF80000L +//RLC_RLCS_GENERAL_0 +#define RLC_RLCS_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_1 +#define RLC_RLCS_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_2 +#define RLC_RLCS_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_2__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_3 +#define RLC_RLCS_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_3__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_4 +#define RLC_RLCS_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_4__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_5 +#define RLC_RLCS_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_5__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_6 +#define RLC_RLCS_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_6__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_7 +#define RLC_RLCS_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_7__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_8 +#define RLC_RLCS_GENERAL_8__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_8__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_9 +#define RLC_RLCS_GENERAL_9__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_9__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_10 +#define RLC_RLCS_GENERAL_10__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_10__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_11 +#define RLC_RLCS_GENERAL_11__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_11__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_12 +#define RLC_RLCS_GENERAL_12__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_12__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_13 +#define RLC_RLCS_GENERAL_13__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_13__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_14 +#define RLC_RLCS_GENERAL_14__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_14__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_15 +#define RLC_RLCS_GENERAL_15__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_15__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GENERAL_16 +#define RLC_RLCS_GENERAL_16__DATA__SHIFT 0x0 +#define RLC_RLCS_GENERAL_16__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_AUXILIARY_REG_1 +#define RLC_RLCS_AUXILIARY_REG_1__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_1__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_1__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_1__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_AUXILIARY_REG_2 +#define RLC_RLCS_AUXILIARY_REG_2__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_2__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_2__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_2__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_AUXILIARY_REG_3 +#define RLC_RLCS_AUXILIARY_REG_3__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_3__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_3__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_3__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_AUXILIARY_REG_4 +#define RLC_RLCS_AUXILIARY_REG_4__ADDR__SHIFT 0x0 +#define RLC_RLCS_AUXILIARY_REG_4__RESERVED__SHIFT 0x12 +#define RLC_RLCS_AUXILIARY_REG_4__ADDR_MASK 0x0003FFFFL +#define RLC_RLCS_AUXILIARY_REG_4__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_SPM_SQTT_MODE +#define RLC_RLCS_SPM_SQTT_MODE__MODE__SHIFT 0x0 +#define RLC_RLCS_SPM_SQTT_MODE__MODE_MASK 0x00000001L +//RLC_RLCS_CP_DMA_SRCID_OVER +#define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE__SHIFT 0x0 +#define RLC_RLCS_CP_DMA_SRCID_OVER__SRCID_OVERRIDE_MASK 0x00000001L +//RLC_RLCS_BOOTLOAD_ID_STATUS1 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED__SHIFT 0x0 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED__SHIFT 0x1 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED__SHIFT 0x2 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED__SHIFT 0x3 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED__SHIFT 0x4 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED__SHIFT 0x5 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED__SHIFT 0x6 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED__SHIFT 0x7 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED__SHIFT 0x8 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED__SHIFT 0x9 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED__SHIFT 0xa +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED__SHIFT 0xb +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED__SHIFT 0xc +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED__SHIFT 0xd +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED__SHIFT 0xe +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED__SHIFT 0xf +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED__SHIFT 0x10 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED__SHIFT 0x11 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED__SHIFT 0x12 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED__SHIFT 0x13 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED__SHIFT 0x14 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED__SHIFT 0x15 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED__SHIFT 0x16 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED__SHIFT 0x17 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED__SHIFT 0x18 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED__SHIFT 0x19 +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED__SHIFT 0x1a +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED__SHIFT 0x1b +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED__SHIFT 0x1c +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED__SHIFT 0x1d +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED__SHIFT 0x1e +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED__SHIFT 0x1f +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_0_LOADED_MASK 0x00000001L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_1_LOADED_MASK 0x00000002L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_2_LOADED_MASK 0x00000004L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_3_LOADED_MASK 0x00000008L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_4_LOADED_MASK 0x00000010L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_5_LOADED_MASK 0x00000020L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_6_LOADED_MASK 0x00000040L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_7_LOADED_MASK 0x00000080L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_8_LOADED_MASK 0x00000100L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_9_LOADED_MASK 0x00000200L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_10_LOADED_MASK 0x00000400L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_11_LOADED_MASK 0x00000800L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_12_LOADED_MASK 0x00001000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_13_LOADED_MASK 0x00002000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_14_LOADED_MASK 0x00004000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_15_LOADED_MASK 0x00008000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_16_LOADED_MASK 0x00010000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_17_LOADED_MASK 0x00020000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_18_LOADED_MASK 0x00040000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_19_LOADED_MASK 0x00080000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_20_LOADED_MASK 0x00100000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_21_LOADED_MASK 0x00200000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_22_LOADED_MASK 0x00400000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_23_LOADED_MASK 0x00800000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_24_LOADED_MASK 0x01000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_25_LOADED_MASK 0x02000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_26_LOADED_MASK 0x04000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_27_LOADED_MASK 0x08000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_28_LOADED_MASK 0x10000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_29_LOADED_MASK 0x20000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_30_LOADED_MASK 0x40000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS1__ID_31_LOADED_MASK 0x80000000L +//RLC_RLCS_BOOTLOAD_ID_STATUS2 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED__SHIFT 0x0 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED__SHIFT 0x1 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED__SHIFT 0x2 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED__SHIFT 0x3 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED__SHIFT 0x4 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED__SHIFT 0x5 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED__SHIFT 0x6 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED__SHIFT 0x7 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED__SHIFT 0x8 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED__SHIFT 0x9 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED__SHIFT 0xa +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED__SHIFT 0xb +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED__SHIFT 0xc +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED__SHIFT 0xd +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED__SHIFT 0xe +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED__SHIFT 0xf +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED__SHIFT 0x10 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED__SHIFT 0x11 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED__SHIFT 0x12 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED__SHIFT 0x13 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED__SHIFT 0x14 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED__SHIFT 0x15 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED__SHIFT 0x16 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED__SHIFT 0x17 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED__SHIFT 0x18 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED__SHIFT 0x19 +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED__SHIFT 0x1a +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED__SHIFT 0x1b +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED__SHIFT 0x1c +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED__SHIFT 0x1d +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED__SHIFT 0x1e +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED__SHIFT 0x1f +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_32_LOADED_MASK 0x00000001L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_33_LOADED_MASK 0x00000002L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_34_LOADED_MASK 0x00000004L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_35_LOADED_MASK 0x00000008L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_36_LOADED_MASK 0x00000010L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_37_LOADED_MASK 0x00000020L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_38_LOADED_MASK 0x00000040L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_39_LOADED_MASK 0x00000080L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_40_LOADED_MASK 0x00000100L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_41_LOADED_MASK 0x00000200L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_42_LOADED_MASK 0x00000400L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_43_LOADED_MASK 0x00000800L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_44_LOADED_MASK 0x00001000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_45_LOADED_MASK 0x00002000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_46_LOADED_MASK 0x00004000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_47_LOADED_MASK 0x00008000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_48_LOADED_MASK 0x00010000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_49_LOADED_MASK 0x00020000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_50_LOADED_MASK 0x00040000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_51_LOADED_MASK 0x00080000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_52_LOADED_MASK 0x00100000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_53_LOADED_MASK 0x00200000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_54_LOADED_MASK 0x00400000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_55_LOADED_MASK 0x00800000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_56_LOADED_MASK 0x01000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_57_LOADED_MASK 0x02000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_58_LOADED_MASK 0x04000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_59_LOADED_MASK 0x08000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_60_LOADED_MASK 0x10000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_61_LOADED_MASK 0x20000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_62_LOADED_MASK 0x40000000L +#define RLC_RLCS_BOOTLOAD_ID_STATUS2__ID_63_LOADED_MASK 0x80000000L +//RLC_RLCS_KMD_LOG_CNTL1 +#define RLC_RLCS_KMD_LOG_CNTL1__DATA__SHIFT 0x0 +#define RLC_RLCS_KMD_LOG_CNTL1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_KMD_LOG_CNTL2 +#define RLC_RLCS_KMD_LOG_CNTL2__DATA__SHIFT 0x0 +#define RLC_RLCS_KMD_LOG_CNTL2__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GPM_LEGACY_INT_STAT +#define RLC_RLCS_GPM_LEGACY_INT_STAT__RESERVED__SHIFT 0x0 +#define RLC_RLCS_GPM_LEGACY_INT_STAT__RESERVED_MASK 0x00000001L +//RLC_RLCS_GPM_LEGACY_INT_DISABLE +#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__RESERVED__SHIFT 0x0 +#define RLC_RLCS_GPM_LEGACY_INT_DISABLE__RESERVED_MASK 0x00000001L +//RLC_RLCS_GCR_DATA_0 +#define RLC_RLCS_GCR_DATA_0__PHASE_0__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_0__PHASE_1__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_0__PHASE_0_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_0__PHASE_1_MASK 0xFFFF0000L +//RLC_RLCS_GCR_DATA_1 +#define RLC_RLCS_GCR_DATA_1__PHASE_2__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_1__PHASE_3__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_1__PHASE_2_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_1__PHASE_3_MASK 0xFFFF0000L +//RLC_RLCS_GCR_DATA_2 +#define RLC_RLCS_GCR_DATA_2__PHASE_4__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_2__PHASE_5__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_2__PHASE_4_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_2__PHASE_5_MASK 0xFFFF0000L +//RLC_RLCS_GCR_DATA_3 +#define RLC_RLCS_GCR_DATA_3__PHASE_6__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_3__PHASE_7__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_3__PHASE_6_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_3__PHASE_7_MASK 0xFFFF0000L +//RLC_RLCS_GCR_DATA_4 +#define RLC_RLCS_GCR_DATA_4__PHASE_8__SHIFT 0x0 +#define RLC_RLCS_GCR_DATA_4__PHASE_9__SHIFT 0x10 +#define RLC_RLCS_GCR_DATA_4__PHASE_8_MASK 0x0000FFFFL +#define RLC_RLCS_GCR_DATA_4__PHASE_9_MASK 0xFFFF0000L +//RLC_RLCS_GCR_STATUS +#define RLC_RLCS_GCR_STATUS__GCR_BUSY__SHIFT 0x0 +#define RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT__SHIFT 0x1 +#define RLC_RLCS_GCR_STATUS__RESERVED_2__SHIFT 0x5 +#define RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG__SHIFT 0x8 +#define RLC_RLCS_GCR_STATUS__RESERVED__SHIFT 0x10 +#define RLC_RLCS_GCR_STATUS__GCR_BUSY_MASK 0x00000001L +#define RLC_RLCS_GCR_STATUS__GCR_OUT_COUNT_MASK 0x0000001EL +#define RLC_RLCS_GCR_STATUS__RESERVED_2_MASK 0x000000E0L +#define RLC_RLCS_GCR_STATUS__GCRIU_CLI_RSP_TAG_MASK 0x0000FF00L +#define RLC_RLCS_GCR_STATUS__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_PERFMON_CLK_CNTL_UCODE +#define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE__SHIFT 0x0 +#define RLC_RLCS_PERFMON_CLK_CNTL_UCODE__PERFMON_CLOCK_STATE_MASK 0x00000001L +//RLC_RLCS_UTCL2_CNTL +#define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE__SHIFT 0x0 +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE__SHIFT 0x1 +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE__SHIFT 0x2 +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE__SHIFT 0x3 +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE__SHIFT 0x5 +#define RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION__SHIFT 0x6 +#define RLC_RLCS_UTCL2_CNTL__RESERVED__SHIFT 0x7 +#define RLC_RLCS_UTCL2_CNTL__MTYPE_NO_PTE_MODE_MASK 0x00000001L +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_MASK 0x00000002L +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_MASK 0x00000004L +#define RLC_RLCS_UTCL2_CNTL__GPA_OVERRIDE_VALUE_MASK 0x00000018L +#define RLC_RLCS_UTCL2_CNTL__VF_OVERRIDE_VALUE_MASK 0x00000020L +#define RLC_RLCS_UTCL2_CNTL__IGNORE_PTE_PERMISSION_MASK 0x00000040L +#define RLC_RLCS_UTCL2_CNTL__RESERVED_MASK 0xFFFFFF80L +//RLC_RLCS_IMU_RLC_MSG_DATA0 +#define RLC_RLCS_IMU_RLC_MSG_DATA0__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA1 +#define RLC_RLCS_IMU_RLC_MSG_DATA1__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA2 +#define RLC_RLCS_IMU_RLC_MSG_DATA2__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA2__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA3 +#define RLC_RLCS_IMU_RLC_MSG_DATA3__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA3__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_DATA4 +#define RLC_RLCS_IMU_RLC_MSG_DATA4__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_DATA4__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_CONTROL +#define RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_CONTROL__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RLC_MSG_CNTL +#define RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG__SHIFT 0x1 +#define RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_RLC_MSG_CNTL__DONETOG_MASK 0x00000001L +#define RLC_RLCS_IMU_RLC_MSG_CNTL__CHGTOG_MASK 0x00000002L +#define RLC_RLCS_IMU_RLC_MSG_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_RLC_IMU_MSG_DATA0 +#define RLC_RLCS_RLC_IMU_MSG_DATA0__DATA__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_MSG_DATA0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_RLC_IMU_MSG_CONTROL +#define RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_MSG_CONTROL__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_RLC_IMU_MSG_CNTL +#define RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG__SHIFT 0x1 +#define RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_RLC_IMU_MSG_CNTL__CHGTOG_MASK 0x00000001L +#define RLC_RLCS_RLC_IMU_MSG_CNTL__DONETOG_MASK 0x00000002L +#define RLC_RLCS_RLC_IMU_MSG_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_IMU_RLC_MUTEX_CNTL +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE__SHIFT 0x1 +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__REQ_MASK 0x00000001L +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__ACQUIRE_MASK 0x00000002L +#define RLC_RLCS_IMU_RLC_MUTEX_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_IMU_RLC_STATUS +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF__SHIFT 0x0 +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS__SHIFT 0x1 +#define RLC_RLCS_IMU_RLC_STATUS__STATUS_14_2__SHIFT 0x2 +#define RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS__SHIFT 0xf +#define RLC_RLCS_IMU_RLC_STATUS__RESERVED__SHIFT 0x10 +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_GFXOFF_MASK 0x00000001L +#define RLC_RLCS_IMU_RLC_STATUS__ALLOW_FA_DCS_MASK 0x00000002L +#define RLC_RLCS_IMU_RLC_STATUS__STATUS_14_2_MASK 0x00007FFCL +#define RLC_RLCS_IMU_RLC_STATUS__DISABLE_GFXCLK_DS_MASK 0x00008000L +#define RLC_RLCS_IMU_RLC_STATUS__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_RLC_IMU_STATUS +#define RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE__SHIFT 0x0 +#define RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE__SHIFT 0x1 +#define RLC_RLCS_RLC_IMU_STATUS__STATUS_3_2__SHIFT 0x2 +#define RLC_RLCS_RLC_IMU_STATUS__RESERVED__SHIFT 0x4 +#define RLC_RLCS_RLC_IMU_STATUS__PWR_DOWN_ACTIVE_MASK 0x00000001L +#define RLC_RLCS_RLC_IMU_STATUS__RLC_ALIVE_MASK 0x00000002L +#define RLC_RLCS_RLC_IMU_STATUS__STATUS_3_2_MASK 0x0000000CL +#define RLC_RLCS_RLC_IMU_STATUS__RESERVED_MASK 0xFFFFFFF0L +//RLC_RLCS_IMU_RAM_DATA_1 +#define RLC_RLCS_IMU_RAM_DATA_1__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_DATA_1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_1_LSB +#define RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_1_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_1_MSB +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED__SHIFT 0x10 +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__DATA_MASK 0x0000FFFFL +#define RLC_RLCS_IMU_RAM_ADDR_1_MSB__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_IMU_RAM_DATA_0 +#define RLC_RLCS_IMU_RAM_DATA_0__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_0_LSB +#define RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_0_LSB__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IMU_RAM_ADDR_0_MSB +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED__SHIFT 0x10 +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__DATA_MASK 0x0000FFFFL +#define RLC_RLCS_IMU_RAM_ADDR_0_MSB__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_IMU_RAM_CNTL +#define RLC_RLCS_IMU_RAM_CNTL__REQTOG__SHIFT 0x0 +#define RLC_RLCS_IMU_RAM_CNTL__ACKTOG__SHIFT 0x1 +#define RLC_RLCS_IMU_RAM_CNTL__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_RAM_CNTL__REQTOG_MASK 0x00000001L +#define RLC_RLCS_IMU_RAM_CNTL__ACKTOG_MASK 0x00000002L +#define RLC_RLCS_IMU_RAM_CNTL__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_IMU_GFX_DOORBELL_FENCE +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE__SHIFT 0x0 +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK__SHIFT 0x1 +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED__SHIFT 0x2 +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ENABLE_MASK 0x00000001L +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__ACK_MASK 0x00000002L +#define RLC_RLCS_IMU_GFX_DOORBELL_FENCE__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_SDMA_INT_CNTL_1 +#define RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID__SHIFT 0x1 +#define RLC_RLCS_SDMA_INT_CNTL_1__RESERVED__SHIFT 0x2 +#define RLC_RLCS_SDMA_INT_CNTL_1__INTERRUPT_ACK_MASK 0x00000001L +#define RLC_RLCS_SDMA_INT_CNTL_1__RESP_ID_MASK 0x00000002L +#define RLC_RLCS_SDMA_INT_CNTL_1__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_SDMA_INT_CNTL_2 +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE__SHIFT 0x1 +#define RLC_RLCS_SDMA_INT_CNTL_2__RESERVED__SHIFT 0x2 +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_EN_MASK 0x00000001L +#define RLC_RLCS_SDMA_INT_CNTL_2__AUTO_ACK_ACTIVE_MASK 0x00000002L +#define RLC_RLCS_SDMA_INT_CNTL_2__RESERVED_MASK 0xFFFFFFFCL +//RLC_RLCS_SDMA_INT_STAT +#define RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST__SHIFT 0x8 +#define RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID__SHIFT 0x10 +#define RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING__SHIFT 0x11 +#define RLC_RLCS_SDMA_INT_STAT__RESERVED__SHIFT 0x12 +#define RLC_RLCS_SDMA_INT_STAT__REQ_IDLE_HIST_MASK 0x000000FFL +#define RLC_RLCS_SDMA_INT_STAT__REQ_BUSY_HIST_MASK 0x0000FF00L +#define RLC_RLCS_SDMA_INT_STAT__LAST_SDMA_RLC_INT_ID_MASK 0x00010000L +#define RLC_RLCS_SDMA_INT_STAT__SDMA_RLC_INT_PENDING_MASK 0x00020000L +#define RLC_RLCS_SDMA_INT_STAT__RESERVED_MASK 0xFFFC0000L +//RLC_RLCS_SDMA_INT_INFO +#define RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW__SHIFT 0x0 +#define RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW__SHIFT 0x8 +#define RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID__SHIFT 0x10 +#define RLC_RLCS_SDMA_INT_INFO__RESERVED__SHIFT 0x11 +#define RLC_RLCS_SDMA_INT_INFO__REQ_IDLE_TO_FW_MASK 0x000000FFL +#define RLC_RLCS_SDMA_INT_INFO__REQ_BUSY_TO_FW_MASK 0x0000FF00L +#define RLC_RLCS_SDMA_INT_INFO__INTERRUPT_ID_MASK 0x00010000L +#define RLC_RLCS_SDMA_INT_INFO__RESERVED_MASK 0xFFFE0000L +//RLC_RLCS_GFX_MEM_POWER_CTRL_0 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_0__DATA__SHIFT 0x0 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_0__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GFX_MEM_POWER_CTRL_1 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_1__DATA__SHIFT 0x0 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_1__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_GFX_MEM_POWER_CTRL_2 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_2__DATA__SHIFT 0x0 +#define RLC_RLCS_GFX_MEM_POWER_CTRL_2__DATA_MASK 0xFFFFFFFFL +//RLC_RLCS_IH_CTRL_1 +#define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1__SHIFT 0x0 +#define RLC_RLCS_IH_CTRL_1__IH_CONTEXT_ID_1_MASK 0xFFFFFFFFL +//RLC_RLCS_IH_CTRL_2 +#define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2__SHIFT 0x0 +#define RLC_RLCS_IH_CTRL_2__IH_RING_ID__SHIFT 0x8 +#define RLC_RLCS_IH_CTRL_2__IH_VM_ID__SHIFT 0x10 +#define RLC_RLCS_IH_CTRL_2__RESERVED__SHIFT 0x14 +#define RLC_RLCS_IH_CTRL_2__IH_CONTEXT_ID_2_MASK 0x000000FFL +#define RLC_RLCS_IH_CTRL_2__IH_RING_ID_MASK 0x0000FF00L +#define RLC_RLCS_IH_CTRL_2__IH_VM_ID_MASK 0x000F0000L +#define RLC_RLCS_IH_CTRL_2__RESERVED_MASK 0xFFF00000L +//RLC_RLCS_IH_CTRL_3 +#define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID__SHIFT 0x0 +#define RLC_RLCS_IH_CTRL_3__IH_VF_ID__SHIFT 0x8 +#define RLC_RLCS_IH_CTRL_3__IH_VF__SHIFT 0xd +#define RLC_RLCS_IH_CTRL_3__RESERVED__SHIFT 0xe +#define RLC_RLCS_IH_CTRL_3__IH_SOURCE_ID_MASK 0x000000FFL +#define RLC_RLCS_IH_CTRL_3__IH_VF_ID_MASK 0x00001F00L +#define RLC_RLCS_IH_CTRL_3__IH_VF_MASK 0x00002000L +#define RLC_RLCS_IH_CTRL_3__RESERVED_MASK 0xFFFFC000L +//RLC_RLCS_IH_STATUS +#define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT__SHIFT 0x0 +#define RLC_RLCS_IH_STATUS__IH_BUSY__SHIFT 0x6 +#define RLC_RLCS_IH_STATUS__IH_WRITE_DONE__SHIFT 0x7 +#define RLC_RLCS_IH_STATUS__RESERVED__SHIFT 0x8 +#define RLC_RLCS_IH_STATUS__IH_CREDIT_COUNT_MASK 0x0000003FL +#define RLC_RLCS_IH_STATUS__IH_BUSY_MASK 0x00000040L +#define RLC_RLCS_IH_STATUS__IH_WRITE_DONE_MASK 0x00000080L +#define RLC_RLCS_IH_STATUS__RESERVED_MASK 0xFFFFFF00L +//RLC_RLCS_FED_STATUS +#define RLC_RLCS_FED_STATUS__RLC_FED_ERR__SHIFT 0x0 +#define RLC_RLCS_FED_STATUS__UTCL2_FED_ERR__SHIFT 0x1 +#define RLC_RLCS_FED_STATUS__GE_FED_ERR__SHIFT 0x2 +#define RLC_RLCS_FED_STATUS__CPC_FED_ERR__SHIFT 0x3 +#define RLC_RLCS_FED_STATUS__CPF_FED_ERR__SHIFT 0x4 +#define RLC_RLCS_FED_STATUS__CPG_FED_ERR__SHIFT 0x5 +#define RLC_RLCS_FED_STATUS__SDMA0_FED_ERR__SHIFT 0x6 +#define RLC_RLCS_FED_STATUS__SDMA1_FED_ERR__SHIFT 0x7 +#define RLC_RLCS_FED_STATUS__RESERVED_9_8__SHIFT 0x8 +#define RLC_RLCS_FED_STATUS__SE0_FED_ERR__SHIFT 0xa +#define RLC_RLCS_FED_STATUS__SE1_FED_ERR__SHIFT 0xb +#define RLC_RLCS_FED_STATUS__CANE_FED_ERR__SHIFT 0xc +#define RLC_RLCS_FED_STATUS__RESERVED_17_13__SHIFT 0xd +#define RLC_RLCS_FED_STATUS__AID0_FED_ERR__SHIFT 0x12 +#define RLC_RLCS_FED_STATUS__AID1_FED_ERR__SHIFT 0x13 +#define RLC_RLCS_FED_STATUS__RLC_FED_ERR_MASK 0x00000001L +#define RLC_RLCS_FED_STATUS__UTCL2_FED_ERR_MASK 0x00000002L +#define RLC_RLCS_FED_STATUS__GE_FED_ERR_MASK 0x00000004L +#define RLC_RLCS_FED_STATUS__CPC_FED_ERR_MASK 0x00000008L +#define RLC_RLCS_FED_STATUS__CPF_FED_ERR_MASK 0x00000010L +#define RLC_RLCS_FED_STATUS__CPG_FED_ERR_MASK 0x00000020L +#define RLC_RLCS_FED_STATUS__SDMA0_FED_ERR_MASK 0x00000040L +#define RLC_RLCS_FED_STATUS__SDMA1_FED_ERR_MASK 0x00000080L +#define RLC_RLCS_FED_STATUS__RESERVED_9_8_MASK 0x00000300L +#define RLC_RLCS_FED_STATUS__SE0_FED_ERR_MASK 0x00000400L +#define RLC_RLCS_FED_STATUS__SE1_FED_ERR_MASK 0x00000800L +#define RLC_RLCS_FED_STATUS__CANE_FED_ERR_MASK 0x00001000L +#define RLC_RLCS_FED_STATUS__RESERVED_17_13_MASK 0x0003E000L +#define RLC_RLCS_FED_STATUS__AID0_FED_ERR_MASK 0x00040000L +#define RLC_RLCS_FED_STATUS__AID1_FED_ERR_MASK 0x00080000L +//RLC_RLCS_FED_RESP +#define RLC_RLCS_FED_RESP__RLC_FED_ACK__SHIFT 0x0 +#define RLC_RLCS_FED_RESP__UTCL2_FED_ACK__SHIFT 0x1 +#define RLC_RLCS_FED_RESP__GE_FED_ACK__SHIFT 0x2 +#define RLC_RLCS_FED_RESP__CPC_FED_ACK__SHIFT 0x3 +#define RLC_RLCS_FED_RESP__CPF_FED_ACK__SHIFT 0x4 +#define RLC_RLCS_FED_RESP__CPG_FED_ACK__SHIFT 0x5 +#define RLC_RLCS_FED_RESP__SDMA0_FED_ACK__SHIFT 0x6 +#define RLC_RLCS_FED_RESP__SDMA1_FED_ACK__SHIFT 0x7 +#define RLC_RLCS_FED_RESP__CANE_FED_ACK__SHIFT 0xc +#define RLC_RLCS_FED_RESP__SE0_FED_ACK__SHIFT 0xd +#define RLC_RLCS_FED_RESP__SE1_FED_ACK__SHIFT 0xe +#define RLC_RLCS_FED_RESP__RLC_FED_ACK_MASK 0x00000001L +#define RLC_RLCS_FED_RESP__UTCL2_FED_ACK_MASK 0x00000002L +#define RLC_RLCS_FED_RESP__GE_FED_ACK_MASK 0x00000004L +#define RLC_RLCS_FED_RESP__CPC_FED_ACK_MASK 0x00000008L +#define RLC_RLCS_FED_RESP__CPF_FED_ACK_MASK 0x00000010L +#define RLC_RLCS_FED_RESP__CPG_FED_ACK_MASK 0x00000020L +#define RLC_RLCS_FED_RESP__SDMA0_FED_ACK_MASK 0x00000040L +#define RLC_RLCS_FED_RESP__SDMA1_FED_ACK_MASK 0x00000080L +#define RLC_RLCS_FED_RESP__CANE_FED_ACK_MASK 0x00001000L +#define RLC_RLCS_FED_RESP__SE0_FED_ACK_MASK 0x00002000L +#define RLC_RLCS_FED_RESP__SE1_FED_ACK_MASK 0x00004000L +//RLC_RLCS_FED_INT_MASK +#define RLC_RLCS_FED_INT_MASK__RLC__SHIFT 0x0 +#define RLC_RLCS_FED_INT_MASK__UTCL2__SHIFT 0x1 +#define RLC_RLCS_FED_INT_MASK__GE__SHIFT 0x2 +#define RLC_RLCS_FED_INT_MASK__CPC__SHIFT 0x3 +#define RLC_RLCS_FED_INT_MASK__CPF__SHIFT 0x4 +#define RLC_RLCS_FED_INT_MASK__CPG__SHIFT 0x5 +#define RLC_RLCS_FED_INT_MASK__SDMA0__SHIFT 0x6 +#define RLC_RLCS_FED_INT_MASK__SDMA1__SHIFT 0x7 +#define RLC_RLCS_FED_INT_MASK__RESERVED_9_8__SHIFT 0x8 +#define RLC_RLCS_FED_INT_MASK__SE0__SHIFT 0xa +#define RLC_RLCS_FED_INT_MASK__SE1__SHIFT 0xb +#define RLC_RLCS_FED_INT_MASK__CANE__SHIFT 0xc +#define RLC_RLCS_FED_INT_MASK__RESERVED_17_13__SHIFT 0xd +#define RLC_RLCS_FED_INT_MASK__AID0__SHIFT 0x12 +#define RLC_RLCS_FED_INT_MASK__AID1__SHIFT 0x13 +#define RLC_RLCS_FED_INT_MASK__RLC_MASK 0x00000001L +#define RLC_RLCS_FED_INT_MASK__UTCL2_MASK 0x00000002L +#define RLC_RLCS_FED_INT_MASK__GE_MASK 0x00000004L +#define RLC_RLCS_FED_INT_MASK__CPC_MASK 0x00000008L +#define RLC_RLCS_FED_INT_MASK__CPF_MASK 0x00000010L +#define RLC_RLCS_FED_INT_MASK__CPG_MASK 0x00000020L +#define RLC_RLCS_FED_INT_MASK__SDMA0_MASK 0x00000040L +#define RLC_RLCS_FED_INT_MASK__SDMA1_MASK 0x00000080L +#define RLC_RLCS_FED_INT_MASK__RESERVED_9_8_MASK 0x00000300L +#define RLC_RLCS_FED_INT_MASK__SE0_MASK 0x00000400L +#define RLC_RLCS_FED_INT_MASK__SE1_MASK 0x00000800L +#define RLC_RLCS_FED_INT_MASK__CANE_MASK 0x00001000L +#define RLC_RLCS_FED_INT_MASK__RESERVED_17_13_MASK 0x0003E000L +#define RLC_RLCS_FED_INT_MASK__AID0_MASK 0x00040000L +#define RLC_RLCS_FED_INT_MASK__AID1_MASK 0x00080000L +//RLC_RLCS_MEM_FED +#define RLC_RLCS_MEM_FED__RESERVED_3_0__SHIFT 0x0 +#define RLC_RLCS_MEM_FED__LX6_RD_ERR__SHIFT 0x4 +#define RLC_RLCS_MEM_FED__TH2_RD_ERR__SHIFT 0x5 +#define RLC_RLCS_MEM_FED__TH1_RD_ERR__SHIFT 0x6 +#define RLC_RLCS_MEM_FED__TH0_RD_ERR__SHIFT 0x7 +#define RLC_RLCS_MEM_FED__DMA_RD_ERR__SHIFT 0x8 +#define RLC_RLCS_MEM_FED__SRM_RD_ERR__SHIFT 0x9 +#define RLC_RLCS_MEM_FED__RESERVED_11_10__SHIFT 0xa +#define RLC_RLCS_MEM_FED__LX6_TR_ERR__SHIFT 0xc +#define RLC_RLCS_MEM_FED__TH2_TR_ERR__SHIFT 0xd +#define RLC_RLCS_MEM_FED__TH1_TR_ERR__SHIFT 0xe +#define RLC_RLCS_MEM_FED__TH0_TR_ERR__SHIFT 0xf +#define RLC_RLCS_MEM_FED__SPM_TR_ERR__SHIFT 0x10 +#define RLC_RLCS_MEM_FED__DMA_TR_ERR__SHIFT 0x11 +#define RLC_RLCS_MEM_FED__DLG_TR_ERR__SHIFT 0x12 +#define RLC_RLCS_MEM_FED__SRM_TR_ERR__SHIFT 0x13 +#define RLC_RLCS_MEM_FED__RESERVED_3_0_MASK 0x0000000FL +#define RLC_RLCS_MEM_FED__LX6_RD_ERR_MASK 0x00000010L +#define RLC_RLCS_MEM_FED__TH2_RD_ERR_MASK 0x00000020L +#define RLC_RLCS_MEM_FED__TH1_RD_ERR_MASK 0x00000040L +#define RLC_RLCS_MEM_FED__TH0_RD_ERR_MASK 0x00000080L +#define RLC_RLCS_MEM_FED__DMA_RD_ERR_MASK 0x00000100L +#define RLC_RLCS_MEM_FED__SRM_RD_ERR_MASK 0x00000200L +#define RLC_RLCS_MEM_FED__RESERVED_11_10_MASK 0x00000C00L +#define RLC_RLCS_MEM_FED__LX6_TR_ERR_MASK 0x00001000L +#define RLC_RLCS_MEM_FED__TH2_TR_ERR_MASK 0x00002000L +#define RLC_RLCS_MEM_FED__TH1_TR_ERR_MASK 0x00004000L +#define RLC_RLCS_MEM_FED__TH0_TR_ERR_MASK 0x00008000L +#define RLC_RLCS_MEM_FED__SPM_TR_ERR_MASK 0x00010000L +#define RLC_RLCS_MEM_FED__DMA_TR_ERR_MASK 0x00020000L +#define RLC_RLCS_MEM_FED__DLG_TR_ERR_MASK 0x00040000L +#define RLC_RLCS_MEM_FED__SRM_TR_ERR_MASK 0x00080000L +//RLC_RLCS_SE_PWR_CTRL +#define RLC_RLCS_SE_PWR_CTRL__SE_GFXCLK_CLKEN__SHIFT 0x0 +#define RLC_RLCS_SE_PWR_CTRL__SE_GFX_HARD_RESETB__SHIFT 0x8 +#define RLC_RLCS_SE_PWR_CTRL__SE_EA_HARD_RESETB__SHIFT 0x10 +#define RLC_RLCS_SE_PWR_CTRL__SE_GFXCLK_CLKEN_MASK 0x00000003L +#define RLC_RLCS_SE_PWR_CTRL__SE_GFX_HARD_RESETB_MASK 0x00000300L +#define RLC_RLCS_SE_PWR_CTRL__SE_EA_HARD_RESETB_MASK 0x00030000L +//RLC_UTCL2_FED_STATUS_SNAP +#define RLC_UTCL2_FED_STATUS_SNAP__UTCL2_FED_STATUS_SNAP__SHIFT 0x0 +#define RLC_UTCL2_FED_STATUS_SNAP__UTCL2_FED_STATUS_SNAP_MASK 0xFFFFFFFFL +//RLC_SE0_FED_STATUS_SNAP +#define RLC_SE0_FED_STATUS_SNAP__SE0_FED_STATUS_SNAP__SHIFT 0x0 +#define RLC_SE0_FED_STATUS_SNAP__SE0_FED_STATUS_SNAP_MASK 0xFFFFFFFFL +//RLC_SE1_FED_STATUS_SNAP +#define RLC_SE1_FED_STATUS_SNAP__SE1_FED_STATUS_SNAP__SHIFT 0x0 +#define RLC_SE1_FED_STATUS_SNAP__SE1_FED_STATUS_SNAP_MASK 0xFFFFFFFFL +//RLC_CANE_FED_STATUS_SNAP +#define RLC_CANE_FED_STATUS_SNAP__CANE_FED_STATUS_SNAP__SHIFT 0x0 +#define RLC_CANE_FED_STATUS_SNAP__CANE_FED_STATUS_SNAP_MASK 0xFFFFFFFFL +//RLC_CONSOLIDATED_FED_STS +#define RLC_CONSOLIDATED_FED_STS__RLC_CONSOLIDATED_FED_STS__SHIFT 0x0 +#define RLC_CONSOLIDATED_FED_STS__NEED_TO_APPLY_FLR__SHIFT 0x10 +#define RLC_CONSOLIDATED_FED_STS__RESERVED__SHIFT 0x11 +#define RLC_CONSOLIDATED_FED_STS__RLC_CONSOLIDATED_FED_STS_MASK 0x0000FFFFL +#define RLC_CONSOLIDATED_FED_STS__NEED_TO_APPLY_FLR_MASK 0x00010000L +#define RLC_CONSOLIDATED_FED_STS__RESERVED_MASK 0xFFFE0000L +//RLC_HOST_FED_ACK +#define RLC_HOST_FED_ACK__RLC_HOST_FED_ACK__SHIFT 0x0 +#define RLC_HOST_FED_ACK__RESERVED__SHIFT 0x10 +#define RLC_HOST_FED_ACK__RLC_HOST_FED_ACK_MASK 0x0000FFFFL +#define RLC_HOST_FED_ACK__RESERVED_MASK 0xFFFF0000L +//RLC_RLCS_SB_RLC_ROM_STATUS +#define RLC_RLCS_SB_RLC_ROM_STATUS__STATUS__SHIFT 0x0 +#define RLC_RLCS_SB_RLC_ROM_STATUS__STATUS_MASK 0x00000003L +//RLC_RLCS_SB_ROM_STATUS +#define RLC_RLCS_SB_ROM_STATUS__RESERVED__SHIFT 0x1f +#define RLC_RLCS_SB_ROM_STATUS__RESERVED_MASK 0x80000000L +//RLC_RLCS_UTCL2_BUSY_CNTL +#define RLC_RLCS_UTCL2_BUSY_CNTL__AUTO_HDSHK__SHIFT 0x0 +#define RLC_RLCS_UTCL2_BUSY_CNTL__ACK__SHIFT 0x1 +#define RLC_RLCS_UTCL2_BUSY_CNTL__SPARE__SHIFT 0x2 +#define RLC_RLCS_UTCL2_BUSY_CNTL__HW_CHK_DIS__SHIFT 0x4 +#define RLC_RLCS_UTCL2_BUSY_CNTL__AUTO_HDSHK_MASK 0x00000001L +#define RLC_RLCS_UTCL2_BUSY_CNTL__ACK_MASK 0x00000002L +#define RLC_RLCS_UTCL2_BUSY_CNTL__SPARE_MASK 0x0000000CL +#define RLC_RLCS_UTCL2_BUSY_CNTL__HW_CHK_DIS_MASK 0x00000070L +//RLC_RLCS_UTCL2_BUSY_STAT +#define RLC_RLCS_UTCL2_BUSY_STAT__REQ_STATUS__SHIFT 0x0 +#define RLC_RLCS_UTCL2_BUSY_STAT__ACK_STATUS__SHIFT 0x1 +#define RLC_RLCS_UTCL2_BUSY_STAT__REQ_STATUS_MASK 0x00000001L +#define RLC_RLCS_UTCL2_BUSY_STAT__ACK_STATUS_MASK 0x00000002L +//RLC_RLCS_DEC_END + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pfvfdec_rlc +//RLC_SAFE_MODE +#define RLC_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SAFE_MODE__CMD_MASK 0x00000001L +#define RLC_SAFE_MODE__MESSAGE_MASK 0x0000001EL +#define RLC_SAFE_MODE__RESERVED1_MASK 0x000000E0L +#define RLC_SAFE_MODE__RESPONSE_MASK 0x00000F00L +#define RLC_SAFE_MODE__RESERVED_MASK 0xFFFFF000L +//RLC_SPM_SAMPLE_CNT +#define RLC_SPM_SAMPLE_CNT__COUNT__SHIFT 0x0 +#define RLC_SPM_SAMPLE_CNT__COUNT_MASK 0xFFFFFFFFL +//RLC_SPM_MC_CNTL +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT 0x0 +#define RLC_SPM_MC_CNTL__RLC_SPM_SDR__SHIFT 0x4 +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR__SHIFT 0x6 +#define RLC_SPM_MC_CNTL__RLC_SPM_FED__SHIFT 0x7 +#define RLC_SPM_MC_CNTL__RLC_SPM_TEMPORAL__SHIFT 0x8 +#define RLC_SPM_MC_CNTL__RLC_SPM_COMP__SHIFT 0xb +#define RLC_SPM_MC_CNTL__RLC_SPM_COMP_OVER__SHIFT 0xd +#define RLC_SPM_MC_CNTL__RLC_SPM_RO__SHIFT 0xe +#define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL__SHIFT 0xf +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER__SHIFT 0x10 +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE__SHIFT 0x11 +#define RLC_SPM_MC_CNTL__RESERVED__SHIFT 0x13 +#define RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK 0x0000000FL +#define RLC_SPM_MC_CNTL__RLC_SPM_SDR_MASK 0x00000030L +#define RLC_SPM_MC_CNTL__RLC_SPM_PERF_CNTR_MASK 0x00000040L +#define RLC_SPM_MC_CNTL__RLC_SPM_FED_MASK 0x00000080L +#define RLC_SPM_MC_CNTL__RLC_SPM_TEMPORAL_MASK 0x00000700L +#define RLC_SPM_MC_CNTL__RLC_SPM_COMP_MASK 0x00001800L +#define RLC_SPM_MC_CNTL__RLC_SPM_COMP_OVER_MASK 0x00002000L +#define RLC_SPM_MC_CNTL__RLC_SPM_RO_MASK 0x00004000L +#define RLC_SPM_MC_CNTL__RLC_SPM_NOFILL_MASK 0x00008000L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_OVER_MASK 0x00010000L +#define RLC_SPM_MC_CNTL__RLC_SPM_MTYPE_MASK 0x00060000L +#define RLC_SPM_MC_CNTL__RESERVED_MASK 0xFFF80000L +//RLC_SPM_INT_CNTL +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 +#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x00000001L +#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xFFFFFFFEL +//RLC_SPM_INT_STATUS +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 +#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x00000001L +#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xFFFFFFFEL +//RLC_SPM_INT_INFO_1 +#define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1__SHIFT 0x0 +#define RLC_SPM_INT_INFO_1__INTERRUPT_INFO_1_MASK 0xFFFFFFFFL +//RLC_SPM_INT_INFO_2 +#define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2__SHIFT 0x0 +#define RLC_SPM_INT_INFO_2__INTERRUPT_ID__SHIFT 0x10 +#define RLC_SPM_INT_INFO_2__RESERVED__SHIFT 0x18 +#define RLC_SPM_INT_INFO_2__INTERRUPT_INFO_2_MASK 0x0000FFFFL +#define RLC_SPM_INT_INFO_2__INTERRUPT_ID_MASK 0x00FF0000L +#define RLC_SPM_INT_INFO_2__RESERVED_MASK 0xFF000000L +//RLC_CSIB_ADDR_LO +#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xFFFFFFFFL +//RLC_CSIB_ADDR_HI +#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0x01FFFFFFL +//RLC_CSIB_LENGTH +#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 +#define RLC_CSIB_LENGTH__LENGTH_MASK 0xFFFFFFFFL +//RLC_CP_SCHEDULERS +#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 +#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 +#define RLC_CP_SCHEDULERS__scheduler0_MASK 0x000000FFL +#define RLC_CP_SCHEDULERS__scheduler1_MASK 0x0000FF00L +//RLC_CP_EOF_INT +#define RLC_CP_EOF_INT__INTERRUPT__SHIFT 0x0 +#define RLC_CP_EOF_INT__RESERVED__SHIFT 0x1 +#define RLC_CP_EOF_INT__INTERRUPT_MASK 0x00000001L +#define RLC_CP_EOF_INT__RESERVED_MASK 0xFFFFFFFEL +//RLC_CP_EOF_INT_CNTL +#define RLC_CP_EOF_INT_CNTL__DATA__SHIFT 0x0 +#define RLC_CP_EOF_INT_CNTL__DATA_MASK 0xFFFFFFFFL +//RLC_SPARE_INT_0 +#define RLC_SPARE_INT_0__DATA__SHIFT 0x0 +#define RLC_SPARE_INT_0__PROCESSING__SHIFT 0x1e +#define RLC_SPARE_INT_0__COMPLETE__SHIFT 0x1f +#define RLC_SPARE_INT_0__DATA_MASK 0x3FFFFFFFL +#define RLC_SPARE_INT_0__PROCESSING_MASK 0x40000000L +#define RLC_SPARE_INT_0__COMPLETE_MASK 0x80000000L +//RLC_SPARE_INT_1 +#define RLC_SPARE_INT_1__DATA__SHIFT 0x0 +#define RLC_SPARE_INT_1__PROCESSING__SHIFT 0x1e +#define RLC_SPARE_INT_1__COMPLETE__SHIFT 0x1f +#define RLC_SPARE_INT_1__DATA_MASK 0x3FFFFFFFL +#define RLC_SPARE_INT_1__PROCESSING_MASK 0x40000000L +#define RLC_SPARE_INT_1__COMPLETE_MASK 0x80000000L +//RLC_SPARE_INT_2 +#define RLC_SPARE_INT_2__DATA__SHIFT 0x0 +#define RLC_SPARE_INT_2__PROCESSING__SHIFT 0x1e +#define RLC_SPARE_INT_2__COMPLETE__SHIFT 0x1f +#define RLC_SPARE_INT_2__DATA_MASK 0x3FFFFFFFL +#define RLC_SPARE_INT_2__PROCESSING_MASK 0x40000000L +#define RLC_SPARE_INT_2__COMPLETE_MASK 0x80000000L +//RLC_RLCV_SPARE_INT_1 +#define RLC_RLCV_SPARE_INT_1__INTERRUPT__SHIFT 0x0 +#define RLC_RLCV_SPARE_INT_1__RESERVED__SHIFT 0x1 +#define RLC_RLCV_SPARE_INT_1__INTERRUPT_MASK 0x00000001L +#define RLC_RLCV_SPARE_INT_1__RESERVED_MASK 0xFFFFFFFEL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pwrdec +//GRBMX_GLARB_BUSY_MASK +#define GRBMX_GLARB_BUSY_MASK__GLARB0C_BUSY_MASK__SHIFT 0x0 +#define GRBMX_GLARB_BUSY_MASK__GLARB0A_BUSY_MASK__SHIFT 0xf +#define GRBMX_GLARB_BUSY_MASK__GLARB1C_BUSY_MASK__SHIFT 0x10 +#define GRBMX_GLARB_BUSY_MASK__GLARB1A_BUSY_MASK__SHIFT 0x1f +#define GRBMX_GLARB_BUSY_MASK__GLARB0C_BUSY_MASK_MASK 0x00000FFFL +#define GRBMX_GLARB_BUSY_MASK__GLARB0A_BUSY_MASK_MASK 0x00008000L +#define GRBMX_GLARB_BUSY_MASK__GLARB1C_BUSY_MASK_MASK 0x0FFF0000L +#define GRBMX_GLARB_BUSY_MASK__GLARB1A_BUSY_MASK_MASK 0x80000000L +//CGTT_IA_CLK_CTRL +#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_IA_CLK_CTRL__DIST_OVERRIDE__SHIFT 0x1a +#define CGTT_IA_CLK_CTRL__PERF_OVERRIDE__SHIFT 0x1b +#define CGTT_IA_CLK_CTRL__PCM_OVERRIDE__SHIFT 0x1c +#define CGTT_IA_CLK_CTRL__TESS_DIST_OVERRIDE__SHIFT 0x1d +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_IA_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_IA_CLK_CTRL__DIST_OVERRIDE_MASK 0x04000000L +#define CGTT_IA_CLK_CTRL__PERF_OVERRIDE_MASK 0x08000000L +#define CGTT_IA_CLK_CTRL__PCM_OVERRIDE_MASK 0x10000000L +#define CGTT_IA_CLK_CTRL__TESS_DIST_OVERRIDE_MASK 0x20000000L +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_WD_CLK_CTRL +#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_WD_CLK_CTRL__FE_OUT_OVERRIDE__SHIFT 0x17 +#define CGTT_WD_CLK_CTRL__UNUSED__SHIFT 0x18 +#define CGTT_WD_CLK_CTRL__DMA_PROC0_OVERRIDE__SHIFT 0x19 +#define CGTT_WD_CLK_CTRL__DMA_PROC1_OVERRIDE__SHIFT 0x1a +#define CGTT_WD_CLK_CTRL__PERF_OVERRIDE__SHIFT 0x1b +#define CGTT_WD_CLK_CTRL__DMA_OVERRIDE__SHIFT 0x1c +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_WD_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_WD_CLK_CTRL__FE_OUT_OVERRIDE_MASK 0x00800000L +#define CGTT_WD_CLK_CTRL__UNUSED_MASK 0x01000000L +#define CGTT_WD_CLK_CTRL__DMA_PROC0_OVERRIDE_MASK 0x02000000L +#define CGTT_WD_CLK_CTRL__DMA_PROC1_OVERRIDE_MASK 0x04000000L +#define CGTT_WD_CLK_CTRL__PERF_OVERRIDE_MASK 0x08000000L +#define CGTT_WD_CLK_CTRL__DMA_OVERRIDE_MASK 0x10000000L +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000L +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_CP_CLK_CTRL +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CP_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CP_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_CPF_CLK_CTRL +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1a +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT__SHIFT 0x1b +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP__SHIFT 0x1c +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX__SHIFT 0x1d +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CPF_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CPF_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x04000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PRT_MASK 0x08000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_CMP_MASK 0x10000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_GFX_MASK 0x20000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_CPC_CLK_CTRL +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_CPC_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_CPC_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//CGTT_RLC_CLK_CTRL +#define CGTT_RLC_CLK_CTRL__RESERVED__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__RESERVED_MASK 0xFFFFFFFFL +//GFX_ICG_GCR_CTRL +#define GFX_ICG_GCR_CTRL__ON_DELAY__SHIFT 0x0 +#define GFX_ICG_GCR_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define GFX_ICG_GCR_CTRL__ON_DELAY_MASK 0x0000000FL +#define GFX_ICG_GCR_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define GFX_ICG_GCR_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//GC_EA_CPWD_ICG_CTRL +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x0 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_DRAM_FE__SHIFT 0x1 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_IO_FE__SHIFT 0x2 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x3 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x4 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_MAM__SHIFT 0x5 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_CREST__SHIFT 0x6 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_GMI__SHIFT 0x7 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_HDM__SHIFT 0x8 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_PRB__SHIFT 0x9 +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_LPDDR__SHIFT 0xa +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x00000001L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_DRAM_FE_MASK 0x00000002L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_IO_FE_MASK 0x00000004L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x00000008L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x00000010L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_MAM_MASK 0x00000020L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_CREST_MASK 0x00000040L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_GMI_MASK 0x00000080L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_HDM_MASK 0x00000100L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_PRB_MASK 0x00000200L +#define GC_EA_CPWD_ICG_CTRL__SOFT_OVERRIDE_LPDDR_MASK 0x00000400L +//GFX_ICG_GC_CAC_CLK_CTRL +#define GFX_ICG_GC_CAC_CLK_CTRL__GC_CAC_DYNAMIC_ICG_OVERRIDE__SHIFT 0x0 +#define GFX_ICG_GC_CAC_CLK_CTRL__GC_CAC_REG_ICG_OVERRIDE__SHIFT 0x1 +#define GFX_ICG_GC_CAC_CLK_CTRL__GC_CAC_DYNAMIC_ICG_OVERRIDE_MASK 0x00000001L +#define GFX_ICG_GC_CAC_CLK_CTRL__GC_CAC_REG_ICG_OVERRIDE_MASK 0x00000002L +//GFX_ICG_GRBM_CTRL +#define GFX_ICG_GRBM_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_SE__SHIFT 0x10 +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define GFX_ICG_GRBM_CTRL__OFF_HYSTERESIS_MASK 0x000003F0L +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_SE_MASK 0x00FF0000L +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define GFX_ICG_GRBM_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +//CC_GC_HBM_DISABLE +#define CC_GC_HBM_DISABLE__CC_GC_HBM_DISABLE__SHIFT 0x10 +#define CC_GC_HBM_DISABLE__CC_GC_HBM_DISABLE_MASK 0x0FFF0000L +//GRBMX_LPDDR_DISABLE_0 +#define GRBMX_LPDDR_DISABLE_0__DISABLE__SHIFT 0x10 +#define GRBMX_LPDDR_DISABLE_0__DISABLE_MASK 0xFFFF0000L +//GRBMX_LPDDR_DISABLE_1 +#define GRBMX_LPDDR_DISABLE_1__DISABLE__SHIFT 0x10 +#define GRBMX_LPDDR_DISABLE_1__DISABLE_MASK 0xFFFF0000L +//GLARBI_GLARBR_MGCG_OVERRIDE +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x0 +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x2 +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000001L +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L +#define GLARBI_GLARBR_MGCG_OVERRIDE__GLARBA_GLARBIW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000004L +//ICG_GLARBA_CTRL +#define ICG_GLARBA_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GLARBA_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GLARBA_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GLARBA_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GLARBA_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GLARBA_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GLARBA_CTRL__LOCAL_CAC_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_GLARBA_CTRL__GCRD_CLK_OVERRIDE__SHIFT 0x7 +#define ICG_GLARBA_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GLARBA_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GLARBA_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GLARBA_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GLARBA_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GLARBA_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_GLARBA_CTRL__LOCAL_CAC_CLK_OVERRIDE_MASK 0x00000040L +#define ICG_GLARBA_CTRL__GCRD_CLK_OVERRIDE_MASK 0x00000080L +//ICG_GLARBC_CLK_CTRL +#define ICG_GLARBC_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GLARBC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GLARBC_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GLARBC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GLARBC_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GLARBC_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GLARBC_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_GLARBC_CLK_CTRL__GCR_CLK_OVERRIDE__SHIFT 0x7 +#define ICG_GLARBC_CLK_CTRL__CREST_RET_CLK_OVERRIDE__SHIFT 0x8 +#define ICG_GLARBC_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GLARBC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GLARBC_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GLARBC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GLARBC_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GLARBC_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_GLARBC_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000040L +#define ICG_GLARBC_CLK_CTRL__GCR_CLK_OVERRIDE_MASK 0x00000080L +#define ICG_GLARBC_CLK_CTRL__CREST_RET_CLK_OVERRIDE_MASK 0x00000100L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_pspdec +//GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID0_SECLEVEL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID1_SECLEVEL__SHIFT 0x4 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID2_SECLEVEL__SHIFT 0x8 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID3_SECLEVEL__SHIFT 0xc +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID4_SECLEVEL__SHIFT 0x10 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID5_SECLEVEL__SHIFT 0x14 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID6_SECLEVEL__SHIFT 0x18 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID7_SECLEVEL__SHIFT 0x1c +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID0_SECLEVEL_MASK 0x0000000FL +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID1_SECLEVEL_MASK 0x000000F0L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID2_SECLEVEL_MASK 0x00000F00L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID3_SECLEVEL_MASK 0x0000F000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID4_SECLEVEL_MASK 0x000F0000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID5_SECLEVEL_MASK 0x00F00000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID6_SECLEVEL_MASK 0x0F000000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP0__CID7_SECLEVEL_MASK 0xF0000000L +//GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID8_SECLEVEL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID9_SECLEVEL__SHIFT 0x4 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID10_SECLEVEL__SHIFT 0x8 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID11_SECLEVEL__SHIFT 0xc +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID12_SECLEVEL__SHIFT 0x10 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID13_SECLEVEL__SHIFT 0x14 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID14_SECLEVEL__SHIFT 0x18 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID15_SECLEVEL__SHIFT 0x1c +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID8_SECLEVEL_MASK 0x0000000FL +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID9_SECLEVEL_MASK 0x000000F0L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID10_SECLEVEL_MASK 0x00000F00L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID11_SECLEVEL_MASK 0x0000F000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID12_SECLEVEL_MASK 0x000F0000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID13_SECLEVEL_MASK 0x00F00000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID14_SECLEVEL_MASK 0x0F000000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP1__CID15_SECLEVEL_MASK 0xF0000000L +//GC_EA_CPWD_SDP_ERR_CTRL +#define GC_EA_CPWD_SDP_ERR_CTRL__INJ_GC_TO_SDP_ERREVENT__SHIFT 0x0 +#define GC_EA_CPWD_SDP_ERR_CTRL__INJ_SDP_TO_GC_UER__SHIFT 0x1 +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_READ_RESPONSE_PARITY_EN__SHIFT 0x2 +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_WRITE_RESPONSE_PARITY_EN__SHIFT 0x3 +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_PROBE_PARITY_EN__SHIFT 0x4 +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_PROBE_RSP_PARITY_EN__SHIFT 0x5 +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_ACKCH_PARITY_EN__SHIFT 0x6 +#define GC_EA_CPWD_SDP_ERR_CTRL__INJ_GC_TO_SDP_ERREVENT_MASK 0x00000001L +#define GC_EA_CPWD_SDP_ERR_CTRL__INJ_SDP_TO_GC_UER_MASK 0x00000002L +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_READ_RESPONSE_PARITY_EN_MASK 0x00000004L +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_WRITE_RESPONSE_PARITY_EN_MASK 0x00000008L +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_PROBE_PARITY_EN_MASK 0x00000010L +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_PROBE_RSP_PARITY_EN_MASK 0x00000020L +#define GC_EA_CPWD_SDP_ERR_CTRL__SDP_ACKCH_PARITY_EN_MASK 0x00000040L +//GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID0_SECLEVEL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID1_SECLEVEL__SHIFT 0x4 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID2_SECLEVEL__SHIFT 0x8 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID3_SECLEVEL__SHIFT 0xc +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID4_SECLEVEL__SHIFT 0x10 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID5_SECLEVEL__SHIFT 0x14 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID6_SECLEVEL__SHIFT 0x18 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID7_SECLEVEL__SHIFT 0x1c +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID0_SECLEVEL_MASK 0x0000000FL +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID1_SECLEVEL_MASK 0x000000F0L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID2_SECLEVEL_MASK 0x00000F00L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID3_SECLEVEL_MASK 0x0000F000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID4_SECLEVEL_MASK 0x000F0000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID5_SECLEVEL_MASK 0x00F00000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID6_SECLEVEL_MASK 0x0F000000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP2__CID7_SECLEVEL_MASK 0xF0000000L +//GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID8_SECLEVEL__SHIFT 0x0 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID9_SECLEVEL__SHIFT 0x4 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID10_SECLEVEL__SHIFT 0x8 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID11_SECLEVEL__SHIFT 0xc +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID12_SECLEVEL__SHIFT 0x10 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID13_SECLEVEL__SHIFT 0x14 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID14_SECLEVEL__SHIFT 0x18 +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID15_SECLEVEL__SHIFT 0x1c +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID8_SECLEVEL_MASK 0x0000000FL +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID9_SECLEVEL_MASK 0x000000F0L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID10_SECLEVEL_MASK 0x00000F00L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID11_SECLEVEL_MASK 0x0000F000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID12_SECLEVEL_MASK 0x000F0000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID13_SECLEVEL_MASK 0x00F00000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID14_SECLEVEL_MASK 0x0F000000L +#define GC_EA_CPWD_SDP_SECLEVEL_NONIO_MAP3__CID15_SECLEVEL_MASK 0xF0000000L +//GRBM_SRCID_CAM_INDEX +#define GRBM_SRCID_CAM_INDEX__INDEX__SHIFT 0x0 +#define GRBM_SRCID_CAM_INDEX__INDEX_MASK 0x00000007L +//GRBM_SRCID_CAM_DATA +#define GRBM_SRCID_CAM_DATA__PROG_SRCID__SHIFT 0x0 +#define GRBM_SRCID_CAM_DATA__TRUST_LEVEL__SHIFT 0x18 +#define GRBM_SRCID_CAM_DATA__PROG_SRCID_MASK 0x0001FFFFL +#define GRBM_SRCID_CAM_DATA__TRUST_LEVEL_MASK 0x0F000000L +//GRBM_IOV_RANGE_ENABLE +#define GRBM_IOV_RANGE_ENABLE__ENABLE__SHIFT 0x0 +#define GRBM_IOV_RANGE_ENABLE__ENABLE_MASK 0xFFFFFFFFL +//GRBM_IOV_RANGE_READ_BLOCK_ENABLE +#define GRBM_IOV_RANGE_READ_BLOCK_ENABLE__ENABLE__SHIFT 0x0 +#define GRBM_IOV_RANGE_READ_BLOCK_ENABLE__ENABLE_MASK 0xFFFFFFFFL +//GRBM_SEC_CNTL +#define GRBM_SEC_CNTL__DEBUG_ENABLE__SHIFT 0x0 +#define GRBM_SEC_CNTL__DEBUG_ENABLE_MASK 0x00000001L +//GRBM_IOV_SPARE_RANGE_START +#define GRBM_IOV_SPARE_RANGE_START__START__SHIFT 0x0 +#define GRBM_IOV_SPARE_RANGE_START__START_MASK 0x0003FFFFL +//GRBM_IOV_SPARE_RANGE_END +#define GRBM_IOV_SPARE_RANGE_END__END__SHIFT 0x0 +#define GRBM_IOV_SPARE_RANGE_END__END_MASK 0x0003FFFFL +//GRBM_CAM_INDEX +#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x0000000FL +//GRBM_CAM_DATA +#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CAM_DATA__CAM_ADDR_MASK 0x0000FFFFL +#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xFFFF0000L +//GRBM_CAM_DATA_UPPER +#define GRBM_CAM_DATA_UPPER__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CAM_DATA_UPPER__CAM_ADDR_MASK 0x00000003L +#define GRBM_CAM_DATA_UPPER__CAM_REMAPADDR_MASK 0x00030000L +//RLC_REG_SEC_INT_STATUS +#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT__SHIFT 0x0 +#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT_OVERFLOW__SHIFT 0x10 +#define RLC_REG_SEC_INT_STATUS__RESERVED__SHIFT 0x11 +#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT_MASK 0x0000FFFFL +#define RLC_REG_SEC_INT_STATUS__FWL_VIOL_COUNT_OVERFLOW_MASK 0x00010000L +#define RLC_REG_SEC_INT_STATUS__RESERVED_MASK 0xFFFE0000L +//RLC_FWL_FIRST_VIOL_ADDR +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR__SHIFT 0x0 +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP__SHIFT 0x12 +#define RLC_FWL_FIRST_VIOL_ADDR__RESERVED__SHIFT 0x13 +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_ADDR_MASK 0x0003FFFFL +#define RLC_FWL_FIRST_VIOL_ADDR__VIOL_OP_MASK 0x00040000L +#define RLC_FWL_FIRST_VIOL_ADDR__RESERVED_MASK 0xFFF80000L +//RLC_FWL_FIRST_VIOL_ADDR_HI +#define RLC_FWL_FIRST_VIOL_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define RLC_FWL_FIRST_VIOL_ADDR_HI__RESERVED__SHIFT 0x1c +#define RLC_FWL_FIRST_VIOL_ADDR_HI__ADDR_HI_MASK 0x0FFFFFFFL +#define RLC_FWL_FIRST_VIOL_ADDR_HI__RESERVED_MASK 0xF0000000L +//RLC_UTC_BYPASS_CNTL +#define RLC_UTC_BYPASS_CNTL__SPM__SHIFT 0x0 +#define RLC_UTC_BYPASS_CNTL__TH0__SHIFT 0x1 +#define RLC_UTC_BYPASS_CNTL__TH1__SHIFT 0x2 +#define RLC_UTC_BYPASS_CNTL__TH2__SHIFT 0x3 +#define RLC_UTC_BYPASS_CNTL__LX6__SHIFT 0x4 +#define RLC_UTC_BYPASS_CNTL__DMA__SHIFT 0x5 +#define RLC_UTC_BYPASS_CNTL__SRM__SHIFT 0x6 +#define RLC_UTC_BYPASS_CNTL__DLG__SHIFT 0x7 +#define RLC_UTC_BYPASS_CNTL__RESERVED__SHIFT 0x8 +#define RLC_UTC_BYPASS_CNTL__SPM_MASK 0x00000001L +#define RLC_UTC_BYPASS_CNTL__TH0_MASK 0x00000002L +#define RLC_UTC_BYPASS_CNTL__TH1_MASK 0x00000004L +#define RLC_UTC_BYPASS_CNTL__TH2_MASK 0x00000008L +#define RLC_UTC_BYPASS_CNTL__LX6_MASK 0x00000010L +#define RLC_UTC_BYPASS_CNTL__DMA_MASK 0x00000020L +#define RLC_UTC_BYPASS_CNTL__SRM_MASK 0x00000040L +#define RLC_UTC_BYPASS_CNTL__DLG_MASK 0x00000080L +#define RLC_UTC_BYPASS_CNTL__RESERVED_MASK 0xFFFFFF00L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_cp_pspdec +//CP_MES_DM_INDEX_ADDR +#define CP_MES_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define CP_MES_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//CP_MES_DM_INDEX_DATA +#define CP_MES_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define CP_MES_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//CP_MEC_DM_INDEX_ADDR +#define CP_MEC_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define CP_MEC_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//CP_MEC_DM_INDEX_DATA +#define CP_MEC_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define CP_MEC_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DM_INDEX_ADDR +#define CP_GFX_RS64_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define CP_GFX_RS64_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//CP_GFX_RS64_DM_INDEX_DATA +#define CP_GFX_RS64_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define CP_GFX_RS64_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//CPG_PSP_DEBUG +#define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x0 +#define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL__SHIFT 0x2 +#define CPG_PSP_DEBUG__GPA_OVERRIDE__SHIFT 0x3 +#define CPG_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT 0x4 +#define CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT 0x5 +#define CPG_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT 0x6 +#define CPG_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L +#define CPG_PSP_DEBUG__VMID_VIOLATION_CNTL_MASK 0x00000004L +#define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L +#define CPG_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK 0x00000010L +#define CPG_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK 0x00000020L +#define CPG_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK 0x00000040L +//CPC_PSP_DEBUG +#define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL__SHIFT 0x0 +#define CPC_PSP_DEBUG__GPA_OVERRIDE__SHIFT 0x3 +#define CPC_PSP_DEBUG__UCODE_VF_OVERRIDE__SHIFT 0x4 +#define CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE__SHIFT 0x5 +#define CPC_PSP_DEBUG__SECURE_REG_OVERRIDE__SHIFT 0x6 +#define CPC_PSP_DEBUG__PRIV_VIOLATION_CNTL_MASK 0x00000003L +#define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L +#define CPC_PSP_DEBUG__UCODE_VF_OVERRIDE_MASK 0x00000010L +#define CPC_PSP_DEBUG__MTYPE_TMZ_OVERRIDE_MASK 0x00000020L +#define CPC_PSP_DEBUG__SECURE_REG_OVERRIDE_MASK 0x00000040L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_ch_pwrdec +//CHI_CHR_MGCG_OVERRIDE +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x0 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x2 +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000001L +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L +#define CHI_CHR_MGCG_OVERRIDE__CHA_CHIW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000004L +//ICG_CHA_CTRL +#define ICG_CHA_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_CHA_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_CHA_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_CHA_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_CHA_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_CHA_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_CHA_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_CHA_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L +//ICG_CHC_CLK_CTRL +#define ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_CHC_CLK_CTRL__OC_IREQ_CLK_OVERRIDE__SHIFT 0x7 +#define ICG_CHC_CLK_CTRL__OC_OREQ_CLK_OVERRIDE__SHIFT 0x8 +#define ICG_CHC_CLK_CTRL__DCC_COMP_CLK_OVERRIDE__SHIFT 0x9 +#define ICG_CHC_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_CHC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_CHC_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_CHC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_CHC_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_CHC_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_CHC_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000040L +#define ICG_CHC_CLK_CTRL__OC_IREQ_CLK_OVERRIDE_MASK 0x00000080L +#define ICG_CHC_CLK_CTRL__OC_OREQ_CLK_OVERRIDE_MASK 0x00000100L +#define ICG_CHC_CLK_CTRL__DCC_COMP_CLK_OVERRIDE_MASK 0x00000200L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gfx_imu_cpwd_gfx_imudec +//GFX_IMU_C2PMSG_0 +#define GFX_IMU_C2PMSG_0__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_0__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_1 +#define GFX_IMU_C2PMSG_1__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_1__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_2 +#define GFX_IMU_C2PMSG_2__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_2__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_3 +#define GFX_IMU_C2PMSG_3__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_3__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_4 +#define GFX_IMU_C2PMSG_4__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_4__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_5 +#define GFX_IMU_C2PMSG_5__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_5__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_6 +#define GFX_IMU_C2PMSG_6__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_6__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_7 +#define GFX_IMU_C2PMSG_7__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_7__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_8 +#define GFX_IMU_C2PMSG_8__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_8__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_9 +#define GFX_IMU_C2PMSG_9__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_9__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_10 +#define GFX_IMU_C2PMSG_10__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_10__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_11 +#define GFX_IMU_C2PMSG_11__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_11__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_12 +#define GFX_IMU_C2PMSG_12__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_12__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_13 +#define GFX_IMU_C2PMSG_13__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_13__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_14 +#define GFX_IMU_C2PMSG_14__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_14__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_15 +#define GFX_IMU_C2PMSG_15__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_15__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_16 +#define GFX_IMU_C2PMSG_16__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_16__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_17 +#define GFX_IMU_C2PMSG_17__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_17__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_18 +#define GFX_IMU_C2PMSG_18__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_18__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_19 +#define GFX_IMU_C2PMSG_19__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_19__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_20 +#define GFX_IMU_C2PMSG_20__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_20__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_21 +#define GFX_IMU_C2PMSG_21__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_21__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_22 +#define GFX_IMU_C2PMSG_22__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_22__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_23 +#define GFX_IMU_C2PMSG_23__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_23__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_24 +#define GFX_IMU_C2PMSG_24__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_24__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_25 +#define GFX_IMU_C2PMSG_25__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_25__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_26 +#define GFX_IMU_C2PMSG_26__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_26__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_27 +#define GFX_IMU_C2PMSG_27__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_27__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_28 +#define GFX_IMU_C2PMSG_28__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_28__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_29 +#define GFX_IMU_C2PMSG_29__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_29__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_30 +#define GFX_IMU_C2PMSG_30__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_30__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_31 +#define GFX_IMU_C2PMSG_31__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_31__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_32 +#define GFX_IMU_C2PMSG_32__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_32__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_33 +#define GFX_IMU_C2PMSG_33__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_33__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_34 +#define GFX_IMU_C2PMSG_34__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_34__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_35 +#define GFX_IMU_C2PMSG_35__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_35__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_36 +#define GFX_IMU_C2PMSG_36__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_36__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_37 +#define GFX_IMU_C2PMSG_37__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_37__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_38 +#define GFX_IMU_C2PMSG_38__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_38__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_39 +#define GFX_IMU_C2PMSG_39__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_39__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_40 +#define GFX_IMU_C2PMSG_40__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_40__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_41 +#define GFX_IMU_C2PMSG_41__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_41__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_42 +#define GFX_IMU_C2PMSG_42__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_42__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_43 +#define GFX_IMU_C2PMSG_43__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_43__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_44 +#define GFX_IMU_C2PMSG_44__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_44__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_45 +#define GFX_IMU_C2PMSG_45__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_45__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_46 +#define GFX_IMU_C2PMSG_46__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_46__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_47 +#define GFX_IMU_C2PMSG_47__DATA__SHIFT 0x0 +#define GFX_IMU_C2PMSG_47__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_MSG_FLAGS +#define GFX_IMU_MSG_FLAGS__STATUS__SHIFT 0x0 +#define GFX_IMU_MSG_FLAGS__STATUS_MASK 0xFFFFFFFFL +//GFX_IMU_C2PMSG_ACCESS_CTRL0 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0__SHIFT 0x0 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1__SHIFT 0x3 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2__SHIFT 0x6 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3__SHIFT 0x9 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4__SHIFT 0xc +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5__SHIFT 0xf +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6__SHIFT 0x12 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7__SHIFT 0x15 +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC0_MASK 0x00000007L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC1_MASK 0x00000038L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC2_MASK 0x000001C0L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC3_MASK 0x00000E00L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC4_MASK 0x00007000L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC5_MASK 0x00038000L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC6_MASK 0x001C0000L +#define GFX_IMU_C2PMSG_ACCESS_CTRL0__ACC7_MASK 0x00E00000L +//GFX_IMU_C2PMSG_ACCESS_CTRL1 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15__SHIFT 0x0 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23__SHIFT 0x3 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31__SHIFT 0x6 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39__SHIFT 0x9 +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47__SHIFT 0xc +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC8_15_MASK 0x00000007L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC16_23_MASK 0x00000038L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC24_31_MASK 0x000001C0L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC32_39_MASK 0x00000E00L +#define GFX_IMU_C2PMSG_ACCESS_CTRL1__ACC40_47_MASK 0x00007000L +//GFX_IMU_PWRMGT_IRQ_CTRL +#define GFX_IMU_PWRMGT_IRQ_CTRL__REQ__SHIFT 0x0 +#define GFX_IMU_PWRMGT_IRQ_CTRL__REQ_MASK 0x00000001L +//GFX_IMU_MP1_MUTEX +#define GFX_IMU_MP1_MUTEX__MUTEX__SHIFT 0x0 +#define GFX_IMU_MP1_MUTEX__MUTEX_MASK 0x00000003L +//GFX_IMU_RLC_DATA_4 +#define GFX_IMU_RLC_DATA_4__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_4__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_3 +#define GFX_IMU_RLC_DATA_3__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_3__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_2 +#define GFX_IMU_RLC_DATA_2__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_2__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_1 +#define GFX_IMU_RLC_DATA_1__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_1__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_DATA_0 +#define GFX_IMU_RLC_DATA_0__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_DATA_0__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_CMD +#define GFX_IMU_RLC_CMD__CMD__SHIFT 0x0 +#define GFX_IMU_RLC_CMD__CMD_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_MUTEX +#define GFX_IMU_RLC_MUTEX__MUTEX__SHIFT 0x0 +#define GFX_IMU_RLC_MUTEX__MUTEX_MASK 0x00000003L +//GFX_IMU_RLC_MSG_STATUS +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY__SHIFT 0x0 +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR__SHIFT 0x1 +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE__SHIFT 0x10 +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG__SHIFT 0x1e +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG__SHIFT 0x1f +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_BUSY_MASK 0x00000001L +#define GFX_IMU_RLC_MSG_STATUS__IMU2RLC_MSG_ERROR_MASK 0x00000002L +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_MSGDONE_MASK 0x00010000L +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_CHGTOG_MASK 0x40000000L +#define GFX_IMU_RLC_MSG_STATUS__RLC2IMU_DONETOG_MASK 0x80000000L +//RLC_GFX_IMU_DATA_0 +#define RLC_GFX_IMU_DATA_0__DATA__SHIFT 0x0 +#define RLC_GFX_IMU_DATA_0__DATA_MASK 0xFFFFFFFFL +//RLC_GFX_IMU_CMD +#define RLC_GFX_IMU_CMD__CMD__SHIFT 0x0 +#define RLC_GFX_IMU_CMD__CMD_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_STATUS +#define GFX_IMU_RLC_STATUS__PD_ACTIVE__SHIFT 0x0 +#define GFX_IMU_RLC_STATUS__RLC_ALIVE__SHIFT 0x1 +#define GFX_IMU_RLC_STATUS__TBD2__SHIFT 0x2 +#define GFX_IMU_RLC_STATUS__TBD3__SHIFT 0x3 +#define GFX_IMU_RLC_STATUS__PD_ACTIVE_MASK 0x00000001L +#define GFX_IMU_RLC_STATUS__RLC_ALIVE_MASK 0x00000002L +#define GFX_IMU_RLC_STATUS__TBD2_MASK 0x00000004L +#define GFX_IMU_RLC_STATUS__TBD3_MASK 0x00000008L +//GFX_IMU_STATUS +#define GFX_IMU_STATUS__ALLOW_GFXOFF__SHIFT 0x0 +#define GFX_IMU_STATUS__ALLOW_FA_DCS__SHIFT 0x1 +#define GFX_IMU_STATUS__TBD4__SHIFT 0x4 +#define GFX_IMU_STATUS__TBD5__SHIFT 0x5 +#define GFX_IMU_STATUS__TBD6__SHIFT 0x6 +#define GFX_IMU_STATUS__TBD7__SHIFT 0x7 +#define GFX_IMU_STATUS__TBD8__SHIFT 0x8 +#define GFX_IMU_STATUS__TBD9__SHIFT 0x9 +#define GFX_IMU_STATUS__TBD10__SHIFT 0xa +#define GFX_IMU_STATUS__TBD11__SHIFT 0xb +#define GFX_IMU_STATUS__TBD12__SHIFT 0xc +#define GFX_IMU_STATUS__TBD13__SHIFT 0xd +#define GFX_IMU_STATUS__TBD14__SHIFT 0xe +#define GFX_IMU_STATUS__DISABLE_GFXCLK_DS__SHIFT 0xf +#define GFX_IMU_STATUS__ALLOW_GFXOFF_MASK 0x00000001L +#define GFX_IMU_STATUS__ALLOW_FA_DCS_MASK 0x00000002L +#define GFX_IMU_STATUS__TBD4_MASK 0x00000010L +#define GFX_IMU_STATUS__TBD5_MASK 0x00000020L +#define GFX_IMU_STATUS__TBD6_MASK 0x00000040L +#define GFX_IMU_STATUS__TBD7_MASK 0x00000080L +#define GFX_IMU_STATUS__TBD8_MASK 0x00000100L +#define GFX_IMU_STATUS__TBD9_MASK 0x00000200L +#define GFX_IMU_STATUS__TBD10_MASK 0x00000400L +#define GFX_IMU_STATUS__TBD11_MASK 0x00000800L +#define GFX_IMU_STATUS__TBD12_MASK 0x00001000L +#define GFX_IMU_STATUS__TBD13_MASK 0x00002000L +#define GFX_IMU_STATUS__TBD14_MASK 0x00004000L +#define GFX_IMU_STATUS__DISABLE_GFXCLK_DS_MASK 0x00008000L +//GFX_IMU_SOC_DATA +#define GFX_IMU_SOC_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_SOC_DATA__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SOC_ADDR +#define GFX_IMU_SOC_ADDR__ADDR__SHIFT 0x0 +#define GFX_IMU_SOC_ADDR__ADDR_MASK 0xFFFFFFFFL +//GFX_IMU_SOC_REQ +#define GFX_IMU_SOC_REQ__REQ_BUSY__SHIFT 0x0 +#define GFX_IMU_SOC_REQ__R_W__SHIFT 0x1 +#define GFX_IMU_SOC_REQ__ERR__SHIFT 0x1f +#define GFX_IMU_SOC_REQ__REQ_BUSY_MASK 0x00000001L +#define GFX_IMU_SOC_REQ__R_W_MASK 0x00000002L +#define GFX_IMU_SOC_REQ__ERR_MASK 0x80000000L +//GFX_IMU_VF_CTRL +#define GFX_IMU_VF_CTRL__VF__SHIFT 0x0 +#define GFX_IMU_VF_CTRL__VFID__SHIFT 0x1 +#define GFX_IMU_VF_CTRL__QOS__SHIFT 0x7 +#define GFX_IMU_VF_CTRL__VF_MASK 0x00000001L +#define GFX_IMU_VF_CTRL__VFID_MASK 0x0000007EL +#define GFX_IMU_VF_CTRL__QOS_MASK 0x00000780L +//GFX_IMU_SCRATCH_0 +#define GFX_IMU_SCRATCH_0__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_0__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_1 +#define GFX_IMU_SCRATCH_1__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_1__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_2 +#define GFX_IMU_SCRATCH_2__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_2__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_3 +#define GFX_IMU_SCRATCH_3__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_3__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_4 +#define GFX_IMU_SCRATCH_4__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_4__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_5 +#define GFX_IMU_SCRATCH_5__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_5__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_6 +#define GFX_IMU_SCRATCH_6__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_6__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_7 +#define GFX_IMU_SCRATCH_7__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_7__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_8 +#define GFX_IMU_SCRATCH_8__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_8__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_9 +#define GFX_IMU_SCRATCH_9__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_9__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_10 +#define GFX_IMU_SCRATCH_10__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_10__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_11 +#define GFX_IMU_SCRATCH_11__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_11__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_12 +#define GFX_IMU_SCRATCH_12__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_12__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_13 +#define GFX_IMU_SCRATCH_13__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_13__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_14 +#define GFX_IMU_SCRATCH_14__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_14__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_SCRATCH_15 +#define GFX_IMU_SCRATCH_15__DATA__SHIFT 0x0 +#define GFX_IMU_SCRATCH_15__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_FW_GTS_LO +#define GFX_IMU_FW_GTS_LO__TSTAMP_LO__SHIFT 0x0 +#define GFX_IMU_FW_GTS_LO__TSTAMP_LO_MASK 0xFFFFFFFFL +//GFX_IMU_FW_GTS_HI +#define GFX_IMU_FW_GTS_HI__TSTAMP_HI__SHIFT 0x0 +#define GFX_IMU_FW_GTS_HI__TSTAMP_HI_MASK 0x00FFFFFFL +//GFX_IMU_GTS_OFFSET_LO +#define GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT 0x0 +#define GFX_IMU_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK 0xFFFFFFFFL +//GFX_IMU_GTS_OFFSET_HI +#define GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT 0x0 +#define GFX_IMU_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK 0x00FFFFFFL +//GFX_IMU_RLC_GTS_OFFSET_LO +#define GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO__SHIFT 0x0 +#define GFX_IMU_RLC_GTS_OFFSET_LO__GTS_OFFSET_LO_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_GTS_OFFSET_HI +#define GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI__SHIFT 0x0 +#define GFX_IMU_RLC_GTS_OFFSET_HI__GTS_OFFSET_HI_MASK 0x00FFFFFFL +//GFX_IMU_CORE_INT_STATUS +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_24__SHIFT 0x18 +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_25__SHIFT 0x19 +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_29__SHIFT 0x1d +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_24_MASK 0x01000000L +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_25_MASK 0x02000000L +#define GFX_IMU_CORE_INT_STATUS__INTERRUPT_29_MASK 0x20000000L +//GFX_IMU_PIC_INT_MASK +#define GFX_IMU_PIC_INT_MASK__MASK_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_MASK__MASK_1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_MASK__MASK_2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_MASK__MASK_3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_MASK__MASK_4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_MASK__MASK_5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_MASK__MASK_6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_MASK__MASK_7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_MASK__MASK_8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_MASK__MASK_9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_MASK__MASK_10__SHIFT 0xa +#define GFX_IMU_PIC_INT_MASK__MASK_11__SHIFT 0xb +#define GFX_IMU_PIC_INT_MASK__MASK_12__SHIFT 0xc +#define GFX_IMU_PIC_INT_MASK__MASK_13__SHIFT 0xd +#define GFX_IMU_PIC_INT_MASK__MASK_14__SHIFT 0xe +#define GFX_IMU_PIC_INT_MASK__MASK_15__SHIFT 0xf +#define GFX_IMU_PIC_INT_MASK__MASK_16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_MASK__MASK_17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_MASK__MASK_18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_MASK__MASK_19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_MASK__MASK_20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_MASK__MASK_21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_MASK__MASK_22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_MASK__MASK_23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_MASK__MASK_24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_MASK__MASK_25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_MASK__MASK_26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_MASK__MASK_27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_MASK__MASK_28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_MASK__MASK_29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_MASK__MASK_30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_MASK__MASK_31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_MASK__MASK_0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_MASK__MASK_1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_MASK__MASK_2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_MASK__MASK_3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_MASK__MASK_4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_MASK__MASK_5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_MASK__MASK_6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_MASK__MASK_7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_MASK__MASK_8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_MASK__MASK_9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_MASK__MASK_10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_MASK__MASK_11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_MASK__MASK_12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_MASK__MASK_13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_MASK__MASK_14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_MASK__MASK_15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_MASK__MASK_16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_MASK__MASK_17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_MASK__MASK_18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_MASK__MASK_19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_MASK__MASK_20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_MASK__MASK_21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_MASK__MASK_22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_MASK__MASK_23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_MASK__MASK_24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_MASK__MASK_25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_MASK__MASK_26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_MASK__MASK_27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_MASK__MASK_28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_MASK__MASK_29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_MASK__MASK_30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_MASK__MASK_31_MASK 0x80000000L +//GFX_IMU_PIC_INT_LVL +#define GFX_IMU_PIC_INT_LVL__LVL_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_LVL__LVL_1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_LVL__LVL_2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_LVL__LVL_3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_LVL__LVL_4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_LVL__LVL_5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_LVL__LVL_6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_LVL__LVL_7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_LVL__LVL_8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_LVL__LVL_9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_LVL__LVL_10__SHIFT 0xa +#define GFX_IMU_PIC_INT_LVL__LVL_11__SHIFT 0xb +#define GFX_IMU_PIC_INT_LVL__LVL_12__SHIFT 0xc +#define GFX_IMU_PIC_INT_LVL__LVL_13__SHIFT 0xd +#define GFX_IMU_PIC_INT_LVL__LVL_14__SHIFT 0xe +#define GFX_IMU_PIC_INT_LVL__LVL_15__SHIFT 0xf +#define GFX_IMU_PIC_INT_LVL__LVL_16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_LVL__LVL_17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_LVL__LVL_18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_LVL__LVL_19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_LVL__LVL_20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_LVL__LVL_21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_LVL__LVL_22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_LVL__LVL_23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_LVL__LVL_24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_LVL__LVL_25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_LVL__LVL_26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_LVL__LVL_27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_LVL__LVL_28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_LVL__LVL_29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_LVL__LVL_30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_LVL__LVL_31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_LVL__LVL_0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_LVL__LVL_1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_LVL__LVL_2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_LVL__LVL_3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_LVL__LVL_4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_LVL__LVL_5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_LVL__LVL_6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_LVL__LVL_7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_LVL__LVL_8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_LVL__LVL_9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_LVL__LVL_10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_LVL__LVL_11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_LVL__LVL_12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_LVL__LVL_13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_LVL__LVL_14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_LVL__LVL_15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_LVL__LVL_16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_LVL__LVL_17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_LVL__LVL_18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_LVL__LVL_19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_LVL__LVL_20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_LVL__LVL_21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_LVL__LVL_22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_LVL__LVL_23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_LVL__LVL_24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_LVL__LVL_25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_LVL__LVL_26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_LVL__LVL_27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_LVL__LVL_28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_LVL__LVL_29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_LVL__LVL_30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_LVL__LVL_31_MASK 0x80000000L +//GFX_IMU_PIC_INT_EDGE +#define GFX_IMU_PIC_INT_EDGE__EDGE_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_EDGE__EDGE_1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_EDGE__EDGE_2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_EDGE__EDGE_3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_EDGE__EDGE_4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_EDGE__EDGE_5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_EDGE__EDGE_6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_EDGE__EDGE_7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_EDGE__EDGE_8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_EDGE__EDGE_9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_EDGE__EDGE_10__SHIFT 0xa +#define GFX_IMU_PIC_INT_EDGE__EDGE_11__SHIFT 0xb +#define GFX_IMU_PIC_INT_EDGE__EDGE_12__SHIFT 0xc +#define GFX_IMU_PIC_INT_EDGE__EDGE_13__SHIFT 0xd +#define GFX_IMU_PIC_INT_EDGE__EDGE_14__SHIFT 0xe +#define GFX_IMU_PIC_INT_EDGE__EDGE_15__SHIFT 0xf +#define GFX_IMU_PIC_INT_EDGE__EDGE_16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_EDGE__EDGE_17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_EDGE__EDGE_18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_EDGE__EDGE_19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_EDGE__EDGE_20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_EDGE__EDGE_21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_EDGE__EDGE_22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_EDGE__EDGE_23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_EDGE__EDGE_24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_EDGE__EDGE_25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_EDGE__EDGE_26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_EDGE__EDGE_27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_EDGE__EDGE_28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_EDGE__EDGE_29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_EDGE__EDGE_30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_EDGE__EDGE_31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_EDGE__EDGE_0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_EDGE__EDGE_1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_EDGE__EDGE_2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_EDGE__EDGE_3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_EDGE__EDGE_4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_EDGE__EDGE_5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_EDGE__EDGE_6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_EDGE__EDGE_7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_EDGE__EDGE_8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_EDGE__EDGE_9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_EDGE__EDGE_10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_EDGE__EDGE_11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_EDGE__EDGE_12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_EDGE__EDGE_31_MASK 0x80000000L +//GFX_IMU_PIC_INT_PRI_0 +#define GFX_IMU_PIC_INT_PRI_0__PRI_0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_0__PRI_1__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_0__PRI_2__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_0__PRI_3__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_0__PRI_0_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_0__PRI_1_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_0__PRI_2_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_0__PRI_3_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_1 +#define GFX_IMU_PIC_INT_PRI_1__PRI_4__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_1__PRI_5__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_1__PRI_6__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_1__PRI_7__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_1__PRI_4_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_1__PRI_5_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_1__PRI_6_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_1__PRI_7_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_2 +#define GFX_IMU_PIC_INT_PRI_2__PRI_8__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_2__PRI_9__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_2__PRI_10__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_2__PRI_11__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_2__PRI_8_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_2__PRI_9_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_2__PRI_10_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_2__PRI_11_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_3 +#define GFX_IMU_PIC_INT_PRI_3__PRI_12__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_3__PRI_13__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_3__PRI_14__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_3__PRI_15__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_3__PRI_12_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_3__PRI_13_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_3__PRI_14_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_3__PRI_15_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_4 +#define GFX_IMU_PIC_INT_PRI_4__PRI_16__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_4__PRI_17__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_4__PRI_18__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_4__PRI_19__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_4__PRI_16_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_4__PRI_17_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_4__PRI_18_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_4__PRI_19_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_5 +#define GFX_IMU_PIC_INT_PRI_5__PRI_20__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_5__PRI_21__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_5__PRI_22__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_5__PRI_23__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_5__PRI_20_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_5__PRI_21_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_5__PRI_22_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_5__PRI_23_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_6 +#define GFX_IMU_PIC_INT_PRI_6__PRI_24__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_6__PRI_25__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_6__PRI_26__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_6__PRI_27__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_6__PRI_24_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_6__PRI_25_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_6__PRI_26_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_6__PRI_27_MASK 0xFF000000L +//GFX_IMU_PIC_INT_PRI_7 +#define GFX_IMU_PIC_INT_PRI_7__PRI_28__SHIFT 0x0 +#define GFX_IMU_PIC_INT_PRI_7__PRI_29__SHIFT 0x8 +#define GFX_IMU_PIC_INT_PRI_7__PRI_30__SHIFT 0x10 +#define GFX_IMU_PIC_INT_PRI_7__PRI_31__SHIFT 0x18 +#define GFX_IMU_PIC_INT_PRI_7__PRI_28_MASK 0x000000FFL +#define GFX_IMU_PIC_INT_PRI_7__PRI_29_MASK 0x0000FF00L +#define GFX_IMU_PIC_INT_PRI_7__PRI_30_MASK 0x00FF0000L +#define GFX_IMU_PIC_INT_PRI_7__PRI_31_MASK 0xFF000000L +//GFX_IMU_PIC_INT_STATUS +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS0__SHIFT 0x0 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS1__SHIFT 0x1 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS2__SHIFT 0x2 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS3__SHIFT 0x3 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS4__SHIFT 0x4 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS5__SHIFT 0x5 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS6__SHIFT 0x6 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS7__SHIFT 0x7 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS8__SHIFT 0x8 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS9__SHIFT 0x9 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS10__SHIFT 0xa +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS11__SHIFT 0xb +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS12__SHIFT 0xc +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS13__SHIFT 0xd +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS14__SHIFT 0xe +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS15__SHIFT 0xf +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS16__SHIFT 0x10 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS17__SHIFT 0x11 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS18__SHIFT 0x12 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS19__SHIFT 0x13 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS20__SHIFT 0x14 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS21__SHIFT 0x15 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS22__SHIFT 0x16 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS23__SHIFT 0x17 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS24__SHIFT 0x18 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS25__SHIFT 0x19 +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS26__SHIFT 0x1a +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS27__SHIFT 0x1b +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS28__SHIFT 0x1c +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS29__SHIFT 0x1d +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS30__SHIFT 0x1e +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS31__SHIFT 0x1f +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS0_MASK 0x00000001L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS1_MASK 0x00000002L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS2_MASK 0x00000004L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS3_MASK 0x00000008L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS4_MASK 0x00000010L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS5_MASK 0x00000020L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS6_MASK 0x00000040L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS7_MASK 0x00000080L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS8_MASK 0x00000100L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS9_MASK 0x00000200L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS10_MASK 0x00000400L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS11_MASK 0x00000800L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS12_MASK 0x00001000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS13_MASK 0x00002000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS14_MASK 0x00004000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS15_MASK 0x00008000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS16_MASK 0x00010000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS17_MASK 0x00020000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS18_MASK 0x00040000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS19_MASK 0x00080000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS20_MASK 0x00100000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS21_MASK 0x00200000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS22_MASK 0x00400000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS23_MASK 0x00800000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS24_MASK 0x01000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS25_MASK 0x02000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS26_MASK 0x04000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS27_MASK 0x08000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS28_MASK 0x10000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS29_MASK 0x20000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS30_MASK 0x40000000L +#define GFX_IMU_PIC_INT_STATUS__INT_STATUS31_MASK 0x80000000L +//GFX_IMU_PIC_INTR +#define GFX_IMU_PIC_INTR__INTR_n__SHIFT 0x0 +#define GFX_IMU_PIC_INTR__INTR_n_MASK 0x00000001L +//GFX_IMU_PIC_INTR_ID +#define GFX_IMU_PIC_INTR_ID__INTR_n__SHIFT 0x0 +#define GFX_IMU_PIC_INTR_ID__INTR_n_MASK 0x000000FFL +//GFX_IMU_IH_CTRL_1 +#define GFX_IMU_IH_CTRL_1__CONTEXT_ID__SHIFT 0x0 +#define GFX_IMU_IH_CTRL_1__CONTEXT_ID_MASK 0xFFFFFFFFL +//GFX_IMU_IH_CTRL_2 +#define GFX_IMU_IH_CTRL_2__CONTEXT_ID__SHIFT 0x0 +#define GFX_IMU_IH_CTRL_2__RING_ID__SHIFT 0x8 +#define GFX_IMU_IH_CTRL_2__VM_ID__SHIFT 0x10 +#define GFX_IMU_IH_CTRL_2__SRSTB__SHIFT 0x1f +#define GFX_IMU_IH_CTRL_2__CONTEXT_ID_MASK 0x000000FFL +#define GFX_IMU_IH_CTRL_2__RING_ID_MASK 0x0000FF00L +#define GFX_IMU_IH_CTRL_2__VM_ID_MASK 0x000F0000L +#define GFX_IMU_IH_CTRL_2__SRSTB_MASK 0x80000000L +//GFX_IMU_IH_CTRL_3 +#define GFX_IMU_IH_CTRL_3__SOURCE_ID__SHIFT 0x0 +#define GFX_IMU_IH_CTRL_3__VF_ID__SHIFT 0x8 +#define GFX_IMU_IH_CTRL_3__VF__SHIFT 0xd +#define GFX_IMU_IH_CTRL_3__SOURCE_ID_MASK 0x000000FFL +#define GFX_IMU_IH_CTRL_3__VF_ID_MASK 0x00001F00L +#define GFX_IMU_IH_CTRL_3__VF_MASK 0x00002000L +//GFX_IMU_IH_STATUS +#define GFX_IMU_IH_STATUS__IH_BUSY__SHIFT 0x0 +#define GFX_IMU_IH_STATUS__IH_BUSY_MASK 0x00000001L +//GFX_IMU_FUSESTRAP +//GFX_IMU_GFXCLK_BYPASS_CTRL +#define GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL__SHIFT 0x0 +#define GFX_IMU_GFXCLK_BYPASS_CTRL__BYPASS_SEL_MASK 0x00000001L +//GFX_IMU_CLK_CTRL +#define GFX_IMU_CLK_CTRL__CG_OVR__SHIFT 0x0 +#define GFX_IMU_CLK_CTRL__CG_OVR_CORE__SHIFT 0x1 +#define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV__SHIFT 0x10 +#define GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD__SHIFT 0x1c +#define GFX_IMU_CLK_CTRL__CG_OVR_MASK 0x00000001L +#define GFX_IMU_CLK_CTRL__CG_OVR_CORE_MASK 0x00000002L +#define GFX_IMU_CLK_CTRL__GFXBYPASSCLK_DIV_MASK 0x007F0000L +#define GFX_IMU_CLK_CTRL__COOLDOWN_PERIOD_MASK 0xF0000000L +//GFX_IMU_DOORBELL_CONTROL +#define GFX_IMU_DOORBELL_CONTROL__OVR_EN__SHIFT 0x0 +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR__SHIFT 0x1 +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS__SHIFT 0x1f +#define GFX_IMU_DOORBELL_CONTROL__OVR_EN_MASK 0x00000001L +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_OVR_MASK 0x00000002L +#define GFX_IMU_DOORBELL_CONTROL__FENCE_EN_STATUS_MASK 0x80000000L +//GFX_IMU_RLC_CG_CTRL +#define GFX_IMU_RLC_CG_CTRL__FORCE_CGCG__SHIFT 0x0 +#define GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN__SHIFT 0x1 +#define GFX_IMU_RLC_CG_CTRL__FORCE_CGCG_MASK 0x00000001L +#define GFX_IMU_RLC_CG_CTRL__MGCG_EARLY_EN_MASK 0x00000002L +//GFX_IMU_RLC_THROTTLE_GFX +#define GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN__SHIFT 0x0 +#define GFX_IMU_RLC_THROTTLE_GFX__THROTTLE_EN_MASK 0x00000001L +//GFX_IMU_RLC_RESET_VECTOR +#define GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF__SHIFT 0x0 +#define GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT__SHIFT 0x2 +#define GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT__SHIFT 0x3 +#define GFX_IMU_RLC_RESET_VECTOR__VECTOR__SHIFT 0x6 +#define GFX_IMU_RLC_RESET_VECTOR__COLD_VS_GFXOFF_MASK 0x00000001L +#define GFX_IMU_RLC_RESET_VECTOR__WARM_RESET_EXIT_MASK 0x00000004L +#define GFX_IMU_RLC_RESET_VECTOR__VF_FLR_EXIT_MASK 0x00000008L +#define GFX_IMU_RLC_RESET_VECTOR__VECTOR_MASK 0x000000C0L +//GFX_IMU_RLC_OVERRIDE +#define GFX_IMU_RLC_OVERRIDE__DS_ALLOW__SHIFT 0x0 +#define GFX_IMU_RLC_OVERRIDE__DS_ALLOW_MASK 0x00000001L +//GFX_IMU_DPM_CONTROL +#define GFX_IMU_DPM_CONTROL__ACC_RESET__SHIFT 0x0 +#define GFX_IMU_DPM_CONTROL__ACC_START__SHIFT 0x1 +#define GFX_IMU_DPM_CONTROL__BUSY_MASK__SHIFT 0x2 +#define GFX_IMU_DPM_CONTROL__ACC_RESET_MASK 0x00000001L +#define GFX_IMU_DPM_CONTROL__ACC_START_MASK 0x00000002L +#define GFX_IMU_DPM_CONTROL__BUSY_MASK_MASK 0x0003FFFCL +//GFX_IMU_DPM_ACC +#define GFX_IMU_DPM_ACC__COUNT__SHIFT 0x0 +#define GFX_IMU_DPM_ACC__COUNT_MASK 0x00FFFFFFL +//GFX_IMU_DPM_REF_COUNTER +#define GFX_IMU_DPM_REF_COUNTER__COUNT__SHIFT 0x0 +#define GFX_IMU_DPM_REF_COUNTER__COUNT_MASK 0x00FFFFFFL +//GFX_IMU_RLC_RAM_INDEX +#define GFX_IMU_RLC_RAM_INDEX__INDEX__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_INDEX__RLC_INDEX__SHIFT 0x10 +#define GFX_IMU_RLC_RAM_INDEX__RAM_VALID__SHIFT 0x1f +#define GFX_IMU_RLC_RAM_INDEX__INDEX_MASK 0x000000FFL +#define GFX_IMU_RLC_RAM_INDEX__RLC_INDEX_MASK 0x00FF0000L +#define GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK 0x80000000L +//GFX_IMU_RLC_RAM_ADDR_HIGH +#define GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_ADDR_HIGH__ADDR_MSB_MASK 0x0000FFFFL +//GFX_IMU_RLC_RAM_ADDR_LOW +#define GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_ADDR_LOW__ADDR_LSB_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_RAM_DATA +#define GFX_IMU_RLC_RAM_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_RLC_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_FENCE_CTRL +#define GFX_IMU_FENCE_CTRL__ENABLED__SHIFT 0x0 +#define GFX_IMU_FENCE_CTRL__ARM_LOG__SHIFT 0x1 +#define GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS__SHIFT 0x3 +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN__SHIFT 0x8 +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR__SHIFT 0x9 +#define GFX_IMU_FENCE_CTRL__ENABLED_MASK 0x00000001L +#define GFX_IMU_FENCE_CTRL__ARM_LOG_MASK 0x00000002L +#define GFX_IMU_FENCE_CTRL__FLUSH_ARBITER_CREDITS_MASK 0x00000008L +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_EN_MASK 0x00000100L +#define GFX_IMU_FENCE_CTRL__GFX_REG_FENCE_OVR_MASK 0x00000200L +//GFX_IMU_FENCE_LOG_INIT +#define GFX_IMU_FENCE_LOG_INIT__UNIT_ID__SHIFT 0x0 +#define GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID__SHIFT 0x7 +#define GFX_IMU_FENCE_LOG_INIT__UNIT_ID_MASK 0x0000007FL +#define GFX_IMU_FENCE_LOG_INIT__INITIATOR_ID_MASK 0x0001FF80L +//GFX_IMU_FENCE_LOG_ADDR +#define GFX_IMU_FENCE_LOG_ADDR__ADDR__SHIFT 0x2 +#define GFX_IMU_FENCE_LOG_ADDR__ADDR_MASK 0x000FFFFCL +//GFX_IMU_PROGRAM_CTR +#define GFX_IMU_PROGRAM_CTR__PC__SHIFT 0x0 +#define GFX_IMU_PROGRAM_CTR__PC_MASK 0xFFFFFFFFL +//GFX_IMU_CORE_CTRL +#define GFX_IMU_CORE_CTRL__CRESET__SHIFT 0x0 +#define GFX_IMU_CORE_CTRL__CSTALL__SHIFT 0x1 +#define GFX_IMU_CORE_CTRL__CDBGENABLE__SHIFT 0x2 +#define GFX_IMU_CORE_CTRL__DRESET__SHIFT 0x3 +#define GFX_IMU_CORE_CTRL__HALT_ON_RESET__SHIFT 0x4 +#define GFX_IMU_CORE_CTRL__BREAK_IN__SHIFT 0x8 +#define GFX_IMU_CORE_CTRL__BREAK_OUT_ACK__SHIFT 0x9 +#define GFX_IMU_CORE_CTRL__CRESET_MASK 0x00000001L +#define GFX_IMU_CORE_CTRL__CSTALL_MASK 0x00000002L +#define GFX_IMU_CORE_CTRL__CDBGENABLE_MASK 0x00000004L +#define GFX_IMU_CORE_CTRL__DRESET_MASK 0x00000008L +#define GFX_IMU_CORE_CTRL__HALT_ON_RESET_MASK 0x00000010L +#define GFX_IMU_CORE_CTRL__BREAK_IN_MASK 0x00000100L +#define GFX_IMU_CORE_CTRL__BREAK_OUT_ACK_MASK 0x00000200L +//GFX_IMU_CORE_STATUS +#define GFX_IMU_CORE_STATUS__CBUSY__SHIFT 0x0 +#define GFX_IMU_CORE_STATUS__PWAIT_MODE__SHIFT 0x1 +#define GFX_IMU_CORE_STATUS__CINTLEVEL__SHIFT 0x4 +#define GFX_IMU_CORE_STATUS__BREAK_IN_ACK__SHIFT 0x8 +#define GFX_IMU_CORE_STATUS__BREAK_OUT__SHIFT 0x9 +#define GFX_IMU_CORE_STATUS__P_FATAL_ERROR__SHIFT 0xb +#define GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL__SHIFT 0x18 +#define GFX_IMU_CORE_STATUS__FAULT_TYPE__SHIFT 0x1c +#define GFX_IMU_CORE_STATUS__CBUSY_MASK 0x00000001L +#define GFX_IMU_CORE_STATUS__PWAIT_MODE_MASK 0x00000002L +#define GFX_IMU_CORE_STATUS__CINTLEVEL_MASK 0x000000F0L +#define GFX_IMU_CORE_STATUS__BREAK_IN_ACK_MASK 0x00000100L +#define GFX_IMU_CORE_STATUS__BREAK_OUT_MASK 0x00000200L +#define GFX_IMU_CORE_STATUS__P_FATAL_ERROR_MASK 0x00000800L +#define GFX_IMU_CORE_STATUS__FAULT_SEVERITY_LEVEL_MASK 0x0F000000L +#define GFX_IMU_CORE_STATUS__FAULT_TYPE_MASK 0xF0000000L +//GFX_IMU_PWROKRAW +#define GFX_IMU_PWROKRAW__PWROKRAW__SHIFT 0x0 +#define GFX_IMU_PWROKRAW__PWROKRAW_MASK 0x00000001L +//GFX_IMU_PWROK +#define GFX_IMU_PWROK__PWROK__SHIFT 0x0 +#define GFX_IMU_PWROK__PWROK_MASK 0x00000001L +//GFX_IMU_GAP_PWROK +#define GFX_IMU_GAP_PWROK__GAP_PWROK__SHIFT 0x0 +#define GFX_IMU_GAP_PWROK__GAP_PWROK_MASK 0x00000001L +//GFX_IMU_RESETn +#define GFX_IMU_RESETn__Cpl_RESETn__SHIFT 0x0 +#define GFX_IMU_RESETn__Cpl_RESETn_MASK 0x00000001L +//GFX_IMU_GFX_RESET_CTRL +#define GFX_IMU_GFX_RESET_CTRL__HARD_RESETB__SHIFT 0x0 +#define GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB__SHIFT 0x3 +#define GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB__SHIFT 0x4 +#define GFX_IMU_GFX_RESET_CTRL__DFLL_SRESETB__SHIFT 0x5 +#define GFX_IMU_GFX_RESET_CTRL__HARD_RESETB_MASK 0x00000001L +#define GFX_IMU_GFX_RESET_CTRL__SDMA_RESETB_MASK 0x00000008L +#define GFX_IMU_GFX_RESET_CTRL__GRBM_RESETB_MASK 0x00000010L +#define GFX_IMU_GFX_RESET_CTRL__DFLL_SRESETB_MASK 0x00000020L +//GFX_IMU_VDCI_RESET_CTRL +#define GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn__SHIFT 0x0 +#define GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET__SHIFT 0x1 +#define GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET__SHIFT 0x2 +#define GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn__SHIFT 0x4 +#define GFX_IMU_VDCI_RESET_CTRL__SOC2GFX_VDCI_RESETn_MASK 0x00000001L +#define GFX_IMU_VDCI_RESET_CTRL__SOC_EA_SDF_VDCI_RESET_MASK 0x00000002L +#define GFX_IMU_VDCI_RESET_CTRL__SOC_UTCL2_ATHUB_VDCI_RESET_MASK 0x00000004L +#define GFX_IMU_VDCI_RESET_CTRL__IMU2GFX_VDCI_RESETn_MASK 0x00000010L +//GFX_IMU_GFX_ISO_CTRL +#define GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn__SHIFT 0x0 +#define GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN__SHIFT 0x1 +#define GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN__SHIFT 0x2 +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn__SHIFT 0x3 +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn__SHIFT 0x4 +#define GFX_IMU_GFX_ISO_CTRL__GFX2IMU_ISOn_MASK 0x00000001L +#define GFX_IMU_GFX_ISO_CTRL__SOC_EA_SDF_VDCI_ISOn_EN_MASK 0x00000002L +#define GFX_IMU_GFX_ISO_CTRL__SOC_UTCL2_ATHUB_VDCI_ISOn_EN_MASK 0x00000004L +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_ISOn_MASK 0x00000008L +#define GFX_IMU_GFX_ISO_CTRL__GFX2SOC_CLK_ISOn_MASK 0x00000010L +//GFX_IMU_TIMER0_CTRL0 +#define GFX_IMU_TIMER0_CTRL0__START_STOP__SHIFT 0x0 +#define GFX_IMU_TIMER0_CTRL0__CLEAR__SHIFT 0x8 +#define GFX_IMU_TIMER0_CTRL0__UP_DOWN__SHIFT 0x10 +#define GFX_IMU_TIMER0_CTRL0__PULSE_EN__SHIFT 0x18 +#define GFX_IMU_TIMER0_CTRL0__START_STOP_MASK 0x00000001L +#define GFX_IMU_TIMER0_CTRL0__CLEAR_MASK 0x00000100L +#define GFX_IMU_TIMER0_CTRL0__UP_DOWN_MASK 0x00010000L +#define GFX_IMU_TIMER0_CTRL0__PULSE_EN_MASK 0x01000000L +//GFX_IMU_TIMER0_CTRL1 +#define GFX_IMU_TIMER0_CTRL1__PWM_EN__SHIFT 0x0 +#define GFX_IMU_TIMER0_CTRL1__TS_MODE__SHIFT 0x8 +#define GFX_IMU_TIMER0_CTRL1__SAT_EN__SHIFT 0x10 +#define GFX_IMU_TIMER0_CTRL1__PWM_EN_MASK 0x00000001L +#define GFX_IMU_TIMER0_CTRL1__TS_MODE_MASK 0x00000100L +#define GFX_IMU_TIMER0_CTRL1__SAT_EN_MASK 0x00010000L +//GFX_IMU_TIMER0_CMP_AUTOINC +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER0_CMP_AUTOINC__AUTOINC_EN3_MASK 0x00000008L +//GFX_IMU_TIMER0_CMP_INTEN +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER0_CMP_INTEN__INT_EN3_MASK 0x00000008L +//GFX_IMU_TIMER0_CMP0 +#define GFX_IMU_TIMER0_CMP0__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP0__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER0_CMP1 +#define GFX_IMU_TIMER0_CMP1__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP1__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER0_CMP3 +#define GFX_IMU_TIMER0_CMP3__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_CMP3__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER0_VALUE +#define GFX_IMU_TIMER0_VALUE__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER0_VALUE__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_CTRL0 +#define GFX_IMU_TIMER1_CTRL0__START_STOP__SHIFT 0x0 +#define GFX_IMU_TIMER1_CTRL0__CLEAR__SHIFT 0x8 +#define GFX_IMU_TIMER1_CTRL0__UP_DOWN__SHIFT 0x10 +#define GFX_IMU_TIMER1_CTRL0__PULSE_EN__SHIFT 0x18 +#define GFX_IMU_TIMER1_CTRL0__START_STOP_MASK 0x00000001L +#define GFX_IMU_TIMER1_CTRL0__CLEAR_MASK 0x00000100L +#define GFX_IMU_TIMER1_CTRL0__UP_DOWN_MASK 0x00010000L +#define GFX_IMU_TIMER1_CTRL0__PULSE_EN_MASK 0x01000000L +//GFX_IMU_TIMER1_CTRL1 +#define GFX_IMU_TIMER1_CTRL1__PWM_EN__SHIFT 0x0 +#define GFX_IMU_TIMER1_CTRL1__TS_MODE__SHIFT 0x8 +#define GFX_IMU_TIMER1_CTRL1__SAT_EN__SHIFT 0x10 +#define GFX_IMU_TIMER1_CTRL1__PWM_EN_MASK 0x00000001L +#define GFX_IMU_TIMER1_CTRL1__TS_MODE_MASK 0x00000100L +#define GFX_IMU_TIMER1_CTRL1__SAT_EN_MASK 0x00010000L +//GFX_IMU_TIMER1_CMP_AUTOINC +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER1_CMP_AUTOINC__AUTOINC_EN3_MASK 0x00000008L +//GFX_IMU_TIMER1_CMP_INTEN +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN0__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN1__SHIFT 0x1 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN2__SHIFT 0x2 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN3__SHIFT 0x3 +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN0_MASK 0x00000001L +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN1_MASK 0x00000002L +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN2_MASK 0x00000004L +#define GFX_IMU_TIMER1_CMP_INTEN__INT_EN3_MASK 0x00000008L +//GFX_IMU_TIMER1_CMP0 +#define GFX_IMU_TIMER1_CMP0__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP0__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_CMP1 +#define GFX_IMU_TIMER1_CMP1__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP1__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_CMP3 +#define GFX_IMU_TIMER1_CMP3__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_CMP3__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_TIMER1_VALUE +#define GFX_IMU_TIMER1_VALUE__VALUE__SHIFT 0x0 +#define GFX_IMU_TIMER1_VALUE__VALUE_MASK 0xFFFFFFFFL +//GFX_IMU_FUSE_CTRL +#define GFX_IMU_FUSE_CTRL__DIV_OVR__SHIFT 0x0 +#define GFX_IMU_FUSE_CTRL__DIV_OVR_EN__SHIFT 0x5 +#define GFX_IMU_FUSE_CTRL__FORCE_DONE__SHIFT 0x6 +#define GFX_IMU_FUSE_CTRL__DIV_OVR_MASK 0x0000001FL +#define GFX_IMU_FUSE_CTRL__DIV_OVR_EN_MASK 0x00000020L +#define GFX_IMU_FUSE_CTRL__FORCE_DONE_MASK 0x00000040L +//GFX_IMU_D_RAM_ADDR +#define GFX_IMU_D_RAM_ADDR__ADDR__SHIFT 0x2 +#define GFX_IMU_D_RAM_ADDR__ADDR_MASK 0x0000FFFCL +//GFX_IMU_D_RAM_DATA +#define GFX_IMU_D_RAM_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_D_RAM_DATA__DATA_MASK 0xFFFFFFFFL +//GFX_IMU_GFX_IH_GASKET_CTRL +#define GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB__SHIFT 0x0 +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL__SHIFT 0x10 +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW__SHIFT 0x14 +#define GFX_IMU_GFX_IH_GASKET_CTRL__SRSTB_MASK 0x00000001L +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_LEVEL_MASK 0x000F0000L +#define GFX_IMU_GFX_IH_GASKET_CTRL__BUFFER_OVERFLOW_MASK 0x00100000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gfx_imu_cpwd_gfx_imu_pspdec +//GFX_IMU_RLC_BOOTLOADER_ADDR_HI +#define GFX_IMU_RLC_BOOTLOADER_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define GFX_IMU_RLC_BOOTLOADER_ADDR_HI__ADDR_HI_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_BOOTLOADER_ADDR_LO +#define GFX_IMU_RLC_BOOTLOADER_ADDR_LO__ADDR_LO__SHIFT 0x0 +#define GFX_IMU_RLC_BOOTLOADER_ADDR_LO__ADDR_LO_MASK 0xFFFFFFFFL +//GFX_IMU_RLC_BOOTLOADER_SIZE +#define GFX_IMU_RLC_BOOTLOADER_SIZE__SIZE__SHIFT 0x0 +#define GFX_IMU_RLC_BOOTLOADER_SIZE__SIZE_MASK 0x03FFFFFFL +//GFX_IMU_I_RAM_ADDR +#define GFX_IMU_I_RAM_ADDR__ADDR__SHIFT 0x2 +#define GFX_IMU_I_RAM_ADDR__ADDR_MASK 0x0000FFFCL +//GFX_IMU_I_RAM_DATA +#define GFX_IMU_I_RAM_DATA__DATA__SHIFT 0x0 +#define GFX_IMU_I_RAM_DATA__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_grbmhdec +//GRBMH_CNTL +#define GRBMH_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define GRBMH_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f +#define GRBMH_CNTL__READ_TIMEOUT_MASK 0x000000FFL +#define GRBMH_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L +//GRBMH_INTF_CNTL +#define GRBMH_INTF_CNTL__RSMUSE_PATH_DISABLE__SHIFT 0x0 +#define GRBMH_INTF_CNTL__GRBM_PATH_DISABLE__SHIFT 0x1 +#define GRBMH_INTF_CNTL__RSMUSE_PATH_DISABLE_MASK 0x00000001L +#define GRBMH_INTF_CNTL__GRBM_PATH_DISABLE_MASK 0x00000002L +//GRBMH_STATUS +#define GRBMH_STATUS__SC_CLEAN__SHIFT 0x0 +#define GRBMH_STATUS__DB_CLEAN__SHIFT 0x1 +#define GRBMH_STATUS__CB_CLEAN__SHIFT 0x2 +#define GRBMH_STATUS__UTCL1_BUSY__SHIFT 0x3 +#define GRBMH_STATUS__TCP_BUSY__SHIFT 0x4 +#define GRBMH_STATUS__GL1CC_BUSY__SHIFT 0x5 +#define GRBMH_STATUS__GL1XCC_BUSY__SHIFT 0x6 +#define GRBMH_STATUS__GE_BUSY__SHIFT 0x9 +#define GRBMH_STATUS__RLC_BUSY__SHIFT 0xa +#define GRBMH_STATUS__WGS_BUSY__SHIFT 0xb +#define GRBMH_STATUS__EA_LINK_BUSY__SHIFT 0xc +#define GRBMH_STATUS__EA_BUSY__SHIFT 0xd +#define GRBMH_STATUS__GL2C_BUSY__SHIFT 0xe +#define GRBMH_STATUS__GL2A_BUSY__SHIFT 0xf +#define GRBMH_STATUS__SC_BUSY__SHIFT 0x11 +#define GRBMH_STATUS__GL1A_BUSY__SHIFT 0x12 +#define GRBMH_STATUS__BCI_BUSY__SHIFT 0x14 +#define GRBMH_STATUS__SQG_BUSY__SHIFT 0x17 +#define GRBMH_STATUS__PA_BUSY__SHIFT 0x18 +#define GRBMH_STATUS__TA_BUSY__SHIFT 0x19 +#define GRBMH_STATUS__SX_BUSY__SHIFT 0x1a +#define GRBMH_STATUS__SPI_BUSY__SHIFT 0x1b +#define GRBMH_STATUS__DB_BUSY__SHIFT 0x1e +#define GRBMH_STATUS__CB_BUSY__SHIFT 0x1f +#define GRBMH_STATUS__SC_CLEAN_MASK 0x00000001L +#define GRBMH_STATUS__DB_CLEAN_MASK 0x00000002L +#define GRBMH_STATUS__CB_CLEAN_MASK 0x00000004L +#define GRBMH_STATUS__UTCL1_BUSY_MASK 0x00000008L +#define GRBMH_STATUS__TCP_BUSY_MASK 0x00000010L +#define GRBMH_STATUS__GL1CC_BUSY_MASK 0x00000020L +#define GRBMH_STATUS__GL1XCC_BUSY_MASK 0x00000040L +#define GRBMH_STATUS__GE_BUSY_MASK 0x00000200L +#define GRBMH_STATUS__RLC_BUSY_MASK 0x00000400L +#define GRBMH_STATUS__WGS_BUSY_MASK 0x00000800L +#define GRBMH_STATUS__EA_LINK_BUSY_MASK 0x00001000L +#define GRBMH_STATUS__EA_BUSY_MASK 0x00002000L +#define GRBMH_STATUS__GL2C_BUSY_MASK 0x00004000L +#define GRBMH_STATUS__GL2A_BUSY_MASK 0x00008000L +#define GRBMH_STATUS__SC_BUSY_MASK 0x00020000L +#define GRBMH_STATUS__GL1A_BUSY_MASK 0x00040000L +#define GRBMH_STATUS__BCI_BUSY_MASK 0x00100000L +#define GRBMH_STATUS__SQG_BUSY_MASK 0x00800000L +#define GRBMH_STATUS__PA_BUSY_MASK 0x01000000L +#define GRBMH_STATUS__TA_BUSY_MASK 0x02000000L +#define GRBMH_STATUS__SX_BUSY_MASK 0x04000000L +#define GRBMH_STATUS__SPI_BUSY_MASK 0x08000000L +#define GRBMH_STATUS__DB_BUSY_MASK 0x40000000L +#define GRBMH_STATUS__CB_BUSY_MASK 0x80000000L +//GRBMH_FGCG0_TARG +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG0_CHICK_BIT__SHIFT 0x0 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG1_CHICK_BIT__SHIFT 0x1 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG2_CHICK_BIT__SHIFT 0x2 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG3_CHICK_BIT__SHIFT 0x3 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG4_CHICK_BIT__SHIFT 0x4 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG5_CHICK_BIT__SHIFT 0x5 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG6_CHICK_BIT__SHIFT 0x6 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG7_CHICK_BIT__SHIFT 0x7 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG8_CHICK_BIT__SHIFT 0x8 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG9_CHICK_BIT__SHIFT 0x9 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG10_CHICK_BIT__SHIFT 0xa +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG11_CHICK_BIT__SHIFT 0xb +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG12_CHICK_BIT__SHIFT 0xc +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG13_CHICK_BIT__SHIFT 0xd +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG14_CHICK_BIT__SHIFT 0xe +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG15_CHICK_BIT__SHIFT 0xf +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG16_CHICK_BIT__SHIFT 0x10 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG17_CHICK_BIT__SHIFT 0x11 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG18_CHICK_BIT__SHIFT 0x12 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG19_CHICK_BIT__SHIFT 0x13 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG20_CHICK_BIT__SHIFT 0x14 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG21_CHICK_BIT__SHIFT 0x15 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG22_CHICK_BIT__SHIFT 0x16 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG23_CHICK_BIT__SHIFT 0x17 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG24_CHICK_BIT__SHIFT 0x18 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG25_CHICK_BIT__SHIFT 0x19 +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG26_CHICK_BIT__SHIFT 0x1a +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG27_CHICK_BIT__SHIFT 0x1b +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG28_CHICK_BIT__SHIFT 0x1c +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG29_CHICK_BIT__SHIFT 0x1d +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG30_CHICK_BIT__SHIFT 0x1e +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG31_CHICK_BIT__SHIFT 0x1f +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG0_CHICK_BIT_MASK 0x00000001L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG1_CHICK_BIT_MASK 0x00000002L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG2_CHICK_BIT_MASK 0x00000004L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG3_CHICK_BIT_MASK 0x00000008L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG4_CHICK_BIT_MASK 0x00000010L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG5_CHICK_BIT_MASK 0x00000020L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG6_CHICK_BIT_MASK 0x00000040L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG7_CHICK_BIT_MASK 0x00000080L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG8_CHICK_BIT_MASK 0x00000100L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG9_CHICK_BIT_MASK 0x00000200L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG10_CHICK_BIT_MASK 0x00000400L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG11_CHICK_BIT_MASK 0x00000800L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG12_CHICK_BIT_MASK 0x00001000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG13_CHICK_BIT_MASK 0x00002000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG14_CHICK_BIT_MASK 0x00004000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG15_CHICK_BIT_MASK 0x00008000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG16_CHICK_BIT_MASK 0x00010000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG17_CHICK_BIT_MASK 0x00020000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG18_CHICK_BIT_MASK 0x00040000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG19_CHICK_BIT_MASK 0x00080000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG20_CHICK_BIT_MASK 0x00100000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG21_CHICK_BIT_MASK 0x00200000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG22_CHICK_BIT_MASK 0x00400000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG23_CHICK_BIT_MASK 0x00800000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG24_CHICK_BIT_MASK 0x01000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG25_CHICK_BIT_MASK 0x02000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG26_CHICK_BIT_MASK 0x04000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG27_CHICK_BIT_MASK 0x08000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG28_CHICK_BIT_MASK 0x10000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG29_CHICK_BIT_MASK 0x20000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG30_CHICK_BIT_MASK 0x40000000L +#define GRBMH_FGCG0_TARG__FGCG_GRBMH_TARG31_CHICK_BIT_MASK 0x80000000L +//GRBMH_SOFT_RESET +#define GRBMH_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x0 +#define GRBMH_SOFT_RESET__SOFT_RESET_SX__SHIFT 0x1 +#define GRBMH_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x2 +#define GRBMH_SOFT_RESET__SOFT_RESET_WGS__SHIFT 0x4 +#define GRBMH_SOFT_RESET__SOFT_RESET_RLCSE__SHIFT 0x5 +#define GRBMH_SOFT_RESET__SOFT_RESET_WGPCAC__SHIFT 0x6 +#define GRBMH_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x7 +#define GRBMH_SOFT_RESET__SOFT_RESET_TA__SHIFT 0x9 +#define GRBMH_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00000001L +#define GRBMH_SOFT_RESET__SOFT_RESET_SX_MASK 0x00000002L +#define GRBMH_SOFT_RESET__SOFT_RESET_EA_MASK 0x00000004L +#define GRBMH_SOFT_RESET__SOFT_RESET_WGS_MASK 0x00000010L +#define GRBMH_SOFT_RESET__SOFT_RESET_RLCSE_MASK 0x00000020L +#define GRBMH_SOFT_RESET__SOFT_RESET_WGPCAC_MASK 0x00000040L +#define GRBMH_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00000080L +#define GRBMH_SOFT_RESET__SOFT_RESET_TA_MASK 0x00000200L +//GRBMH_READ_ERROR +#define GRBMH_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define GRBMH_READ_ERROR__READ_PIPEID__SHIFT 0x14 +#define GRBMH_READ_ERROR__READ_MEID__SHIFT 0x16 +#define GRBMH_READ_ERROR__READ_REQUESTER_RLC__SHIFT 0x1b +#define GRBMH_READ_ERROR__READ_REQUESTER_AID_GFX_PIPE0__SHIFT 0x1c +#define GRBMH_READ_ERROR__READ_REQUESTER_AID_NBP_PIPE__SHIFT 0x1e +#define GRBMH_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define GRBMH_READ_ERROR__READ_ADDRESS_MASK 0x000FFFFCL +#define GRBMH_READ_ERROR__READ_PIPEID_MASK 0x00300000L +#define GRBMH_READ_ERROR__READ_MEID_MASK 0x00C00000L +#define GRBMH_READ_ERROR__READ_REQUESTER_RLC_MASK 0x08000000L +#define GRBMH_READ_ERROR__READ_REQUESTER_AID_GFX_PIPE0_MASK 0x10000000L +#define GRBMH_READ_ERROR__READ_REQUESTER_AID_NBP_PIPE_MASK 0x40000000L +#define GRBMH_READ_ERROR__READ_ERROR_MASK 0x80000000L +//GRBMH_GFX_CLKEN_CNTL +#define GRBMH_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define GRBMH_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define GRBMH_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL +#define GRBMH_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L +//GRBMH_FGCG2_MISC +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_SPI_CHICK_BIT__SHIFT 0x0 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_SQG_CHICK_BIT__SHIFT 0x1 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGS_CHICK_BIT__SHIFT 0x2 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_GESE_CHICK_BIT__SHIFT 0x3 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP0_CHICK_BIT__SHIFT 0x4 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP1_CHICK_BIT__SHIFT 0x5 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_MSFLLRS0_CHICK_BIT__SHIFT 0x6 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_MSFLLRS1_CHICK_BIT__SHIFT 0x7 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP4_CHICK_BIT__SHIFT 0x8 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP5_CHICK_BIT__SHIFT 0x9 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP6_CHICK_BIT__SHIFT 0xa +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP7_CHICK_BIT__SHIFT 0xb +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB0_CHICK_BIT__SHIFT 0xc +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB1_CHICK_BIT__SHIFT 0xd +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB2_CHICK_BIT__SHIFT 0xe +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB3_CHICK_BIT__SHIFT 0xf +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB4_CHICK_BIT__SHIFT 0x10 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB5_CHICK_BIT__SHIFT 0x11 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB6_CHICK_BIT__SHIFT 0x12 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB7_CHICK_BIT__SHIFT 0x13 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP8_CHICK_BIT__SHIFT 0x14 +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_SPI_CHICK_BIT_MASK 0x00000001L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_SQG_CHICK_BIT_MASK 0x00000002L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGS_CHICK_BIT_MASK 0x00000004L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_GESE_CHICK_BIT_MASK 0x00000008L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP0_CHICK_BIT_MASK 0x00000010L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP1_CHICK_BIT_MASK 0x00000020L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_MSFLLRS0_CHICK_BIT_MASK 0x00000040L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_MSFLLRS1_CHICK_BIT_MASK 0x00000080L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP4_CHICK_BIT_MASK 0x00000100L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP5_CHICK_BIT_MASK 0x00000200L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP6_CHICK_BIT_MASK 0x00000400L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP7_CHICK_BIT_MASK 0x00000800L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB0_CHICK_BIT_MASK 0x00001000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB1_CHICK_BIT_MASK 0x00002000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB2_CHICK_BIT_MASK 0x00004000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB3_CHICK_BIT_MASK 0x00008000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB4_CHICK_BIT_MASK 0x00010000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB5_CHICK_BIT_MASK 0x00020000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB6_CHICK_BIT_MASK 0x00040000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_RB7_CHICK_BIT_MASK 0x00080000L +#define GRBMH_FGCG2_MISC__FGCG_GRBMH_WGP8_CHICK_BIT_MASK 0x00100000L +//GRBMH_FGCG1_TARGVF +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF0_CHICK_BIT__SHIFT 0x0 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF1_CHICK_BIT__SHIFT 0x1 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF2_CHICK_BIT__SHIFT 0x2 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF3_CHICK_BIT__SHIFT 0x3 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF4_CHICK_BIT__SHIFT 0x4 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF5_CHICK_BIT__SHIFT 0x5 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF6_CHICK_BIT__SHIFT 0x6 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF7_CHICK_BIT__SHIFT 0x7 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF8_CHICK_BIT__SHIFT 0x8 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF9_CHICK_BIT__SHIFT 0x9 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF10_CHICK_BIT__SHIFT 0xa +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF11_CHICK_BIT__SHIFT 0xb +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF12_CHICK_BIT__SHIFT 0xc +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF13_CHICK_BIT__SHIFT 0xd +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF14_CHICK_BIT__SHIFT 0xe +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF15_CHICK_BIT__SHIFT 0xf +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF16_CHICK_BIT__SHIFT 0x10 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF17_CHICK_BIT__SHIFT 0x11 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF18_CHICK_BIT__SHIFT 0x12 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF19_CHICK_BIT__SHIFT 0x13 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF20_CHICK_BIT__SHIFT 0x14 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF21_CHICK_BIT__SHIFT 0x15 +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF22_CHICK_BIT__SHIFT 0x16 +#define GRBMH_FGCG1_TARGVF__AID_READ_ERROR_CHICK_BIT__SHIFT 0x17 +#define GRBMH_FGCG1_TARGVF__SE_STRAP_MATCH_ENABLE_CHICK_BIT__SHIFT 0x18 +#define GRBMH_FGCG1_TARGVF__GRBMH_RLCSE_reg_clken_CHICK_BIT__SHIFT 0x19 +#define GRBMH_FGCG1_TARGVF__GRBM_GRBMH_reg_clken_CHICK_BIT__SHIFT 0x1a +#define GRBMH_FGCG1_TARGVF__AID_FGCG_CHICK_BIT__SHIFT 0x1b +#define GRBMH_FGCG1_TARGVF__GRBMH_GRBM_fgcg_CHICK_BIT__SHIFT 0x1c +#define GRBMH_FGCG1_TARGVF__GRBMH_SPI_reg_clken_CHICK_BIT__SHIFT 0x1d +#define GRBMH_FGCG1_TARGVF__GRBM_WGS_reg_clken_CHICK_BIT__SHIFT 0x1e +#define GRBMH_FGCG1_TARGVF__GRBMH_ALWAYSON_reg_clken_CHICK_BIT__SHIFT 0x1f +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF0_CHICK_BIT_MASK 0x00000001L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF1_CHICK_BIT_MASK 0x00000002L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF2_CHICK_BIT_MASK 0x00000004L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF3_CHICK_BIT_MASK 0x00000008L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF4_CHICK_BIT_MASK 0x00000010L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF5_CHICK_BIT_MASK 0x00000020L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF6_CHICK_BIT_MASK 0x00000040L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF7_CHICK_BIT_MASK 0x00000080L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF8_CHICK_BIT_MASK 0x00000100L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF9_CHICK_BIT_MASK 0x00000200L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF10_CHICK_BIT_MASK 0x00000400L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF11_CHICK_BIT_MASK 0x00000800L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF12_CHICK_BIT_MASK 0x00001000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF13_CHICK_BIT_MASK 0x00002000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF14_CHICK_BIT_MASK 0x00004000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF15_CHICK_BIT_MASK 0x00008000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF16_CHICK_BIT_MASK 0x00010000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF17_CHICK_BIT_MASK 0x00020000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF18_CHICK_BIT_MASK 0x00040000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF19_CHICK_BIT_MASK 0x00080000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF20_CHICK_BIT_MASK 0x00100000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF21_CHICK_BIT_MASK 0x00200000L +#define GRBMH_FGCG1_TARGVF__FGCG_GRBMH_TARGVF22_CHICK_BIT_MASK 0x00400000L +#define GRBMH_FGCG1_TARGVF__AID_READ_ERROR_CHICK_BIT_MASK 0x00800000L +#define GRBMH_FGCG1_TARGVF__SE_STRAP_MATCH_ENABLE_CHICK_BIT_MASK 0x01000000L +#define GRBMH_FGCG1_TARGVF__GRBMH_RLCSE_reg_clken_CHICK_BIT_MASK 0x02000000L +#define GRBMH_FGCG1_TARGVF__GRBM_GRBMH_reg_clken_CHICK_BIT_MASK 0x04000000L +#define GRBMH_FGCG1_TARGVF__AID_FGCG_CHICK_BIT_MASK 0x08000000L +#define GRBMH_FGCG1_TARGVF__GRBMH_GRBM_fgcg_CHICK_BIT_MASK 0x10000000L +#define GRBMH_FGCG1_TARGVF__GRBMH_SPI_reg_clken_CHICK_BIT_MASK 0x20000000L +#define GRBMH_FGCG1_TARGVF__GRBM_WGS_reg_clken_CHICK_BIT_MASK 0x40000000L +#define GRBMH_FGCG1_TARGVF__GRBMH_ALWAYSON_reg_clken_CHICK_BIT_MASK 0x80000000L +//GRBMH_NOWHERE +#define GRBMH_NOWHERE__DATA__SHIFT 0x0 +#define GRBMH_NOWHERE__DATA_MASK 0xFFFFFFFFL +//GRBMH_INVALID_PIPE +#define GRBMH_INVALID_PIPE__ADDR__SHIFT 0x2 +#define GRBMH_INVALID_PIPE__PIPEID__SHIFT 0x14 +#define GRBMH_INVALID_PIPE__MEID__SHIFT 0x16 +#define GRBMH_INVALID_PIPE__QUEUEID__SHIFT 0x18 +#define GRBMH_INVALID_PIPE__SSRCID__SHIFT 0x1b +#define GRBMH_INVALID_PIPE__INVALID_PIPE__SHIFT 0x1f +#define GRBMH_INVALID_PIPE__ADDR_MASK 0x000FFFFCL +#define GRBMH_INVALID_PIPE__PIPEID_MASK 0x00300000L +#define GRBMH_INVALID_PIPE__MEID_MASK 0x00C00000L +#define GRBMH_INVALID_PIPE__QUEUEID_MASK 0x07000000L +#define GRBMH_INVALID_PIPE__SSRCID_MASK 0x78000000L +#define GRBMH_INVALID_PIPE__INVALID_PIPE_MASK 0x80000000L +//GRBMH_SYNC +#define GRBMH_SYNC__GFX_PIPE0_PERFMON_SYNC__SHIFT 0x0 +#define GRBMH_SYNC__GFX_PIPE0_SYNC__SHIFT 0x10 +#define GRBMH_SYNC__GFX_SYNC_SET_CLR__SHIFT 0x1f +#define GRBMH_SYNC__GFX_PIPE0_PERFMON_SYNC_MASK 0x00000001L +#define GRBMH_SYNC__GFX_PIPE0_SYNC_MASK 0x00010000L +#define GRBMH_SYNC__GFX_SYNC_SET_CLR_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_padec +//GE_RATE_CNTL_1 +#define GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT__SHIFT 0x0 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT__SHIFT 0x4 +#define GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT__SHIFT 0x8 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT__SHIFT 0xc +#define GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT__SHIFT 0x10 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT__SHIFT 0x14 +#define GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM__SHIFT 0x18 +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM__SHIFT 0x1c +#define GE_RATE_CNTL_1__ADD_X_CLKS_LS_VERT_MASK 0x0000000FL +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_LS_VERT_MASK 0x000000F0L +#define GE_RATE_CNTL_1__ADD_X_CLKS_HS_VERT_MASK 0x00000F00L +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_HS_VERT_MASK 0x0000F000L +#define GE_RATE_CNTL_1__ADD_X_CLKS_ES_VERT_MASK 0x000F0000L +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_ES_VERT_MASK 0x00F00000L +#define GE_RATE_CNTL_1__ADD_X_CLKS_GS_PRIM_MASK 0x0F000000L +#define GE_RATE_CNTL_1__AFTER_Y_TRANS_GS_PRIM_MASK 0xF0000000L +//GE_RATE_CNTL_2 +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS__SHIFT 0x10 +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES__SHIFT 0x14 +#define GE_RATE_CNTL_2__MERGED_HS_GS_MODE__SHIFT 0x18 +#define GE_RATE_CNTL_2__MERGED_LS_ES_MODE__SHIFT 0x19 +#define GE_RATE_CNTL_2__ENABLE_RATE_CNTL__SHIFT 0x1a +#define GE_RATE_CNTL_2__SWAP_PRIORITY__SHIFT 0x1b +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_HS_GS_MASK 0x000F0000L +#define GE_RATE_CNTL_2__ADD_X_CLKS_MERGED_LS_ES_MASK 0x00F00000L +#define GE_RATE_CNTL_2__MERGED_HS_GS_MODE_MASK 0x01000000L +#define GE_RATE_CNTL_2__MERGED_LS_ES_MODE_MASK 0x02000000L +#define GE_RATE_CNTL_2__ENABLE_RATE_CNTL_MASK 0x04000000L +#define GE_RATE_CNTL_2__SWAP_PRIORITY_MASK 0x08000000L +//CC_GC_SHADER_ARRAY_CONFIG +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L +//GE_SE_CNTL_STATUS +#define GE_SE_CNTL_STATUS__TE_BUSY__SHIFT 0x0 +#define GE_SE_CNTL_STATUS__NGG_BUSY__SHIFT 0x1 +#define GE_SE_CNTL_STATUS__HS_BUSY__SHIFT 0x2 +#define GE_SE_CNTL_STATUS__TE_BUSY_MASK 0x00000001L +#define GE_SE_CNTL_STATUS__NGG_BUSY_MASK 0x00000002L +#define GE_SE_CNTL_STATUS__HS_BUSY_MASK 0x00000004L +//GE_SPI_IF_SAFE_REG +#define GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA__SHIFT 0x0 +#define GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA__SHIFT 0x6 +#define GE_SPI_IF_SAFE_REG__GE_SPI_GRP__SHIFT 0xc +#define GE_SPI_IF_SAFE_REG__GE_SPI_LS_ES_DATA_MASK 0x0000003FL +#define GE_SPI_IF_SAFE_REG__GE_SPI_HS_GS_DATA_MASK 0x00000FC0L +#define GE_SPI_IF_SAFE_REG__GE_SPI_GRP_MASK 0x0003F000L +//GE_PA_IF_SAFE_REG +#define GE_PA_IF_SAFE_REG__GE_PA_CSB__SHIFT 0x0 +#define GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD__SHIFT 0xa +#define GE_PA_IF_SAFE_REG__GE_PA_CSB_MASK 0x000003FFL +#define GE_PA_IF_SAFE_REG__GE_PA_PAYLOAD_MASK 0x000FFC00L +//PA_SU_DEBUG_CNTL +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0 +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x0000003FL +//PA_CL_CNTL_STATUS +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000L +//PA_CL_ENHANCE +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET__SHIFT 0x6 +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS__SHIFT 0x7 +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC__SHIFT 0x8 +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION__SHIFT 0x9 +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER__SHIFT 0xb +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH__SHIFT 0xc +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH__SHIFT 0xe +#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE__SHIFT 0x11 +#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE__SHIFT 0x12 +#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE__SHIFT 0x13 +#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE__SHIFT 0x14 +#define PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE__SHIFT 0x15 +#define PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL__SHIFT 0x16 +#define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO__SHIFT 0x17 +#define PA_CL_ENHANCE__PA_W_GL1X_SRC_CLK_OVERRIDE__SHIFT 0x18 +#define PA_CL_ENHANCE__PA_W_GL1X_REQ_CLK_OVERRIDE__SHIFT 0x19 +#define PA_CL_ENHANCE__PA_R_GL1X_REQ_CLK_OVERRIDE__SHIFT 0x1a +#define PA_CL_ENHANCE__PAF_GEWD_CSB_CLK_OVERRIDE__SHIFT 0x1b +#define PA_CL_ENHANCE__BROADCAST_PMODE_PRIMS__SHIFT 0x1c +#define PA_CL_ENHANCE__BROADCAST_PERP_ENDCAP_PRIMS__SHIFT 0x1d +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x00000001L +#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x00000006L +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x00000008L +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x00000010L +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x00000020L +#define PA_CL_ENHANCE__IGNORE_PIPELINE_RESET_MASK 0x00000040L +#define PA_CL_ENHANCE__KILL_INNER_EDGE_FLAGS_MASK 0x00000080L +#define PA_CL_ENHANCE__NGG_PA_TO_ALL_SC_MASK 0x00000100L +#define PA_CL_ENHANCE__TC_LATENCY_TIME_STAMP_RESOLUTION_MASK 0x00000600L +#define PA_CL_ENHANCE__NGG_BYPASS_PRIM_FILTER_MASK 0x00000800L +#define PA_CL_ENHANCE__NGG_SIDEBAND_MEMORY_DEPTH_MASK 0x00003000L +#define PA_CL_ENHANCE__NGG_PRIM_INDICES_FIFO_DEPTH_MASK 0x0001C000L +#define PA_CL_ENHANCE__PROG_NEAR_CLIP_PLANE_ENABLE_MASK 0x00020000L +#define PA_CL_ENHANCE__POLY_INNER_EDGE_FLAG_DISABLE_MASK 0x00040000L +#define PA_CL_ENHANCE__TC_REQUEST_PERF_CNTR_ENABLE_MASK 0x00080000L +#define PA_CL_ENHANCE__DISABLE_PA_PH_INTF_FINE_CLOCK_GATE_MASK 0x00100000L +#define PA_CL_ENHANCE__DISABLE_PA_SX_REQ_INTF_FINE_CLOCK_GATE_MASK 0x00200000L +#define PA_CL_ENHANCE__ENABLE_PA_RATE_CNTL_MASK 0x00400000L +#define PA_CL_ENHANCE__CLAMP_NEGATIVE_BB_TO_ZERO_MASK 0x00800000L +#define PA_CL_ENHANCE__PA_W_GL1X_SRC_CLK_OVERRIDE_MASK 0x01000000L +#define PA_CL_ENHANCE__PA_W_GL1X_REQ_CLK_OVERRIDE_MASK 0x02000000L +#define PA_CL_ENHANCE__PA_R_GL1X_REQ_CLK_OVERRIDE_MASK 0x04000000L +#define PA_CL_ENHANCE__PAF_GEWD_CSB_CLK_OVERRIDE_MASK 0x08000000L +#define PA_CL_ENHANCE__BROADCAST_PMODE_PRIMS_MASK 0x10000000L +#define PA_CL_ENHANCE__BROADCAST_PERP_ENDCAP_PRIMS_MASK 0x20000000L +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000L +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000L +//PA_CL_RESET_DEBUG +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 +#define PA_CL_RESET_DEBUG__DISABLE_PAF_WR_SHUNT__SHIFT 0x1 +#define PA_CL_RESET_DEBUG__DISABLE_PAB_RD_SHUNT__SHIFT 0x2 +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x00000001L +#define PA_CL_RESET_DEBUG__DISABLE_PAF_WR_SHUNT_MASK 0x00000002L +#define PA_CL_RESET_DEBUG__DISABLE_PAB_RD_SHUNT_MASK 0x00000004L +//PA_SU_CNTL_STATUS +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000L +//PA_SC_FIFO_DEPTH_CNTL +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x000003FFL +//PA_PH_DEBUG_CNTL +#define PA_PH_DEBUG_CNTL__PH_DEBUG_INDX__SHIFT 0x0 +#define PA_PH_DEBUG_CNTL__PH_DEBUG_CLEAR_ASSERT_ON_ERROR_BITS__SHIFT 0x8 +#define PA_PH_DEBUG_CNTL__PH_DEBUG_CLEAR_EVENT_HISTORY_DATA__SHIFT 0x9 +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_VPZ_FLUSH_DFSM_AND_SOP_EVENTS_IN_EVENT_HISTORY_DATA__SHIFT 0xa +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_DEBUG_CNTL_EVENTS_IN_EVENT_HISTORY_DATA__SHIFT 0xb +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_0__SHIFT 0xc +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_1__SHIFT 0x12 +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_2__SHIFT 0x18 +#define PA_PH_DEBUG_CNTL__PH_DEBUG_INDX_MASK 0x000000FFL +#define PA_PH_DEBUG_CNTL__PH_DEBUG_CLEAR_ASSERT_ON_ERROR_BITS_MASK 0x00000100L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_CLEAR_EVENT_HISTORY_DATA_MASK 0x00000200L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_VPZ_FLUSH_DFSM_AND_SOP_EVENTS_IN_EVENT_HISTORY_DATA_MASK 0x00000400L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_DEBUG_CNTL_EVENTS_IN_EVENT_HISTORY_DATA_MASK 0x00000800L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_0_MASK 0x0003F000L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_1_MASK 0x00FC0000L +#define PA_PH_DEBUG_CNTL__PH_DEBUG_FILTER_EVENT_2_MASK 0x3F000000L +//PA_SC_DEBUG_CNTL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_CLEAR_ASSERT_ON_ERROR_BITS__SHIFT 0x8 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_CLEAR_EVENT_HISTORY_DATA__SHIFT 0x9 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_VPZ_FLUSH_DFSM_AND_SOP_EVENTS_IN_EVENT_HISTORY_DATA__SHIFT 0xa +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_DEBUG_CNTL_EVENTS_IN_EVENT_HISTORY_DATA__SHIFT 0xb +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_0__SHIFT 0xc +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_1__SHIFT 0x12 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_2__SHIFT 0x18 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_BUS_FLOP_EN__SHIFT 0x1e +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x000000FFL +#define PA_SC_DEBUG_CNTL__SC_DEBUG_CLEAR_ASSERT_ON_ERROR_BITS_MASK 0x00000100L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_CLEAR_EVENT_HISTORY_DATA_MASK 0x00000200L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_VPZ_FLUSH_DFSM_AND_SOP_EVENTS_IN_EVENT_HISTORY_DATA_MASK 0x00000400L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_DEBUG_CNTL_EVENTS_IN_EVENT_HISTORY_DATA_MASK 0x00000800L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_0_MASK 0x0003F000L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_1_MASK 0x00FC0000L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_FILTER_EVENT_2_MASK 0x3F000000L +#define PA_SC_DEBUG_CNTL__SC_DEBUG_BUS_FLOP_EN_MASK 0x40000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_sqdec +//SQ_CONFIG +#define SQ_CONFIG__ECO_SPARE__SHIFT 0x0 +#define SQ_CONFIG__DISABLE_SGPR_RD_PERSIST__SHIFT 0x7 +#define SQ_CONFIG__NEW_TRANS_ARB_SCHEME__SHIFT 0x8 +#define SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP__SHIFT 0x9 +#define SQ_CONFIG__DISABLE_SGPR_RD_KILL__SHIFT 0xa +#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0xb +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS__SHIFT 0x12 +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS__SHIFT 0x13 +#define SQ_CONFIG__WCLK_HYSTERESIS_CNT__SHIFT 0x15 +#define SQ_CONFIG__DISABLE_ILLEGAL_OPCODE_DETECTION__SHIFT 0x17 +#define SQ_CONFIG__DISABLE_ILLEGAL_TO_NOP_DETECTION__SHIFT 0x18 +#define SQ_CONFIG__DISABLE_ILLEGAL_EXPORT_DETECTION__SHIFT 0x19 +#define SQ_CONFIG__DISABLE_ILLEGAL_CLAUSE_DETECTION__SHIFT 0x1a +#define SQ_CONFIG__DISABLE_END_CLAUSE_TX__SHIFT 0x1b +#define SQ_CONFIG__DISABLE_DIFF_WAVE_VALU_COISSUE__SHIFT 0x1c +#define SQ_CONFIG__DISABLE_IHP_STALL__SHIFT 0x1d +#define SQ_CONFIG__DISABLE_SP_SINGLE_ISSUE_WAVE64_TRANS__SHIFT 0x1e +#define SQ_CONFIG__DISABLE_ISC_PREFETCH_LIMITER__SHIFT 0x1f +#define SQ_CONFIG__ECO_SPARE_MASK 0x0000007FL +#define SQ_CONFIG__DISABLE_SGPR_RD_PERSIST_MASK 0x00000080L +#define SQ_CONFIG__NEW_TRANS_ARB_SCHEME_MASK 0x00000100L +#define SQ_CONFIG__DISABLE_VMEM_EXEC_ZERO_SKIP_MASK 0x00000200L +#define SQ_CONFIG__DISABLE_SGPR_RD_KILL_MASK 0x00000400L +#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x0003F800L +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_GS_MASK 0x00040000L +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_GS_MASK 0x00180000L +#define SQ_CONFIG__WCLK_HYSTERESIS_CNT_MASK 0x00600000L +#define SQ_CONFIG__DISABLE_ILLEGAL_OPCODE_DETECTION_MASK 0x00800000L +#define SQ_CONFIG__DISABLE_ILLEGAL_TO_NOP_DETECTION_MASK 0x01000000L +#define SQ_CONFIG__DISABLE_ILLEGAL_EXPORT_DETECTION_MASK 0x02000000L +#define SQ_CONFIG__DISABLE_ILLEGAL_CLAUSE_DETECTION_MASK 0x04000000L +#define SQ_CONFIG__DISABLE_END_CLAUSE_TX_MASK 0x08000000L +#define SQ_CONFIG__DISABLE_DIFF_WAVE_VALU_COISSUE_MASK 0x10000000L +#define SQ_CONFIG__DISABLE_IHP_STALL_MASK 0x20000000L +#define SQ_CONFIG__DISABLE_SP_SINGLE_ISSUE_WAVE64_TRANS_MASK 0x40000000L +#define SQ_CONFIG__DISABLE_ISC_PREFETCH_LIMITER_MASK 0x80000000L +//SQC_CONFIG +#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 +#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 +#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 +#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 +#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 +#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 +#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0x9 +#define SQC_CONFIG__EVICT_LRU__SHIFT 0xa +#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xc +#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xd +#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0xe +#define SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE__SHIFT 0x16 +#define SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG__SHIFT 0x17 +#define SQC_CONFIG__PIT_PM_STATUS_FGCG_OVERRIDE__SHIFT 0x1a +#define SQC_CONFIG__EXEC_POP_CNT_25PCT__SHIFT 0x1b +#define SQC_CONFIG__SQC_SQ_INV_REG_GCR_SEL__SHIFT 0x1c +#define SQC_CONFIG__SPARE__SHIFT 0x1d +#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x00000003L +#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0x0000000CL +#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x00000030L +#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x00000040L +#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x00000080L +#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x00000100L +#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x00000200L +#define SQC_CONFIG__EVICT_LRU_MASK 0x00000C00L +#define SQC_CONFIG__FORCE_2_BANK_MASK 0x00001000L +#define SQC_CONFIG__FORCE_1_BANK_MASK 0x00002000L +#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0x003FC000L +#define SQC_CONFIG__CACHE_CTRL_GCR_FIX_DISABLE_MASK 0x00400000L +#define SQC_CONFIG__CACHE_CTRL_ALMOST_MAX_INFLIGHT_CONFIG_MASK 0x03800000L +#define SQC_CONFIG__PIT_PM_STATUS_FGCG_OVERRIDE_MASK 0x04000000L +#define SQC_CONFIG__EXEC_POP_CNT_25PCT_MASK 0x08000000L +#define SQC_CONFIG__SQC_SQ_INV_REG_GCR_SEL_MASK 0x10000000L +#define SQC_CONFIG__SPARE_MASK 0xE0000000L +//SQ_RANDOM_WAVE_PRI +#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 +#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 +#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa +#define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID__SHIFT 0x1f +#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x0000007FL +#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x00000380L +#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x00FFFC00L +#define SQ_RANDOM_WAVE_PRI__FORCE_IB_ARB_PRIO_MSK_VALID_MASK 0x80000000L +//SQG_STATUS +#define SQG_STATUS__REG_BUSY__SHIFT 0x0 +#define SQG_STATUS__POWEROFF_RESTORE__SHIFT 0x1 +#define SQG_STATUS__REG_BUSY_MASK 0x00000001L +#define SQG_STATUS__POWEROFF_RESTORE_MASK 0x00000002L +//SQ_FIFO_SIZES +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 +#define SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED__SHIFT 0xc +#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED__SHIFT 0xe +#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE__SHIFT 0x10 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 +#define SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT__SHIFT 0x14 +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0x0000000FL +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0x00000300L +#define SQ_FIFO_SIZES__EXPORT_BUF_GS_RESERVED_MASK 0x00003000L +#define SQ_FIFO_SIZES__EXPORT_BUF_PS_RESERVED_MASK 0x0000C000L +#define SQ_FIFO_SIZES__EXPORT_BUF_REDUCE_MASK 0x00030000L +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0x000C0000L +#define SQ_FIFO_SIZES__EXPORT_BUF_PRIMPOS_LIMIT_MASK 0x00300000L +//SQ_DSM_CNTL +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x00000001L +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x00000002L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x00000004L +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x00000008L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x00000100L +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x00000200L +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x00000400L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x00010000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x00020000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x00040000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x00080000L +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x00100000L +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x00200000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x01000000L +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x02000000L +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x04000000L +//SQ_DSM_CNTL2 +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT__SHIFT 0x3 +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY__SHIFT 0x5 +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT__SHIFT 0x6 +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY__SHIFT 0x8 +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT__SHIFT 0x9 +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY__SHIFT 0xb +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY__SHIFT 0xe +#define SQ_DSM_CNTL2__SP_INJECT_DELAY__SHIFT 0x14 +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY__SHIFT 0x1a +#define SQ_DSM_CNTL2__SGPR_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SQ_DSM_CNTL2__SGPR_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SQ_DSM_CNTL2__LDS_D_ENABLE_ERROR_INJECT_MASK 0x00000018L +#define SQ_DSM_CNTL2__LDS_D_SELECT_INJECT_DELAY_MASK 0x00000020L +#define SQ_DSM_CNTL2__LDS_I_ENABLE_ERROR_INJECT_MASK 0x000000C0L +#define SQ_DSM_CNTL2__LDS_I_SELECT_INJECT_DELAY_MASK 0x00000100L +#define SQ_DSM_CNTL2__SP_ENABLE_ERROR_INJECT_MASK 0x00000600L +#define SQ_DSM_CNTL2__SP_SELECT_INJECT_DELAY_MASK 0x00000800L +#define SQ_DSM_CNTL2__LDS_INJECT_DELAY_MASK 0x000FC000L +#define SQ_DSM_CNTL2__SP_INJECT_DELAY_MASK 0x03F00000L +#define SQ_DSM_CNTL2__SQ_INJECT_DELAY_MASK 0xFC000000L +//SQ_PIT_WEIGHT +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP0__SHIFT 0x0 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP1__SHIFT 0x3 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP2__SHIFT 0x6 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP3__SHIFT 0x9 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP4__SHIFT 0xc +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP5__SHIFT 0xf +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP6__SHIFT 0x12 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP7__SHIFT 0x15 +#define SQ_PIT_WEIGHT__UNUSED__SHIFT 0x18 +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP0_MASK 0x00000007L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP1_MASK 0x00000038L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP2_MASK 0x000001C0L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP3_MASK 0x00000E00L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP4_MASK 0x00007000L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP5_MASK 0x00038000L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP6_MASK 0x001C0000L +#define SQ_PIT_WEIGHT__PIT_WEIGHT_GRP7_MASK 0x00E00000L +#define SQ_PIT_WEIGHT__UNUSED_MASK 0xFF000000L +//SQG_THREAD_TRACE_CONFIG +#define SQG_THREAD_TRACE_CONFIG__ALL_VMID__SHIFT 0x0 +#define SQG_THREAD_TRACE_CONFIG__ALL_VMID_MASK 0x00000001L +//SP_CONFIG +#define SP_CONFIG__ECO_SPARE__SHIFT 0x0 +#define SP_CONFIG__MGCG_SYNC_PULSE__SHIFT 0x1 +#define SP_CONFIG__DISABLE_MGCG_OVERSHOOT_MITIGATION__SHIFT 0x2 +#define SP_CONFIG__DISABLE_TRANS_COEXEC__SHIFT 0x3 +#define SP_CONFIG__CAC_COUNTER_OVERRIDE__SHIFT 0x4 +#define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE__SHIFT 0x5 +#define SP_CONFIG__DISABLE_XDL_COEXEC__SHIFT 0x6 +#define SP_CONFIG__ECO_SPARE_2__SHIFT 0x7 +#define SP_CONFIG__ECO_SPARE_MASK 0x00000001L +#define SP_CONFIG__MGCG_SYNC_PULSE_MASK 0x00000002L +#define SP_CONFIG__DISABLE_MGCG_OVERSHOOT_MITIGATION_MASK 0x00000004L +#define SP_CONFIG__DISABLE_TRANS_COEXEC_MASK 0x00000008L +#define SP_CONFIG__CAC_COUNTER_OVERRIDE_MASK 0x00000010L +#define SP_CONFIG__SP_SX_EXPVDATA_FGCG_OVERRIDE_MASK 0x00000020L +#define SP_CONFIG__DISABLE_XDL_COEXEC_MASK 0x00000040L +#define SP_CONFIG__ECO_SPARE_2_MASK 0x00000380L +//SQ_ARB_CONFIG +#define SQ_ARB_CONFIG__WG_RR_INTERVAL__SHIFT 0x0 +#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL__SHIFT 0x4 +#define SQ_ARB_CONFIG__WG_RR_INTERVAL_MASK 0x00000003L +#define SQ_ARB_CONFIG__FWD_PROG_INTERVAL_MASK 0x00000030L +//SQ_DYN_VGPR +#define SQ_DYN_VGPR__WAVE_LIMIT__SHIFT 0x0 +#define SQ_DYN_VGPR__FWD_PROGRESS__SHIFT 0x4 +#define SQ_DYN_VGPR__MAX_BLOCK_ALLOC__SHIFT 0x5 +#define SQ_DYN_VGPR__BLOCK_SIZE__SHIFT 0x8 +#define SQ_DYN_VGPR__WAVE_LIMIT_MASK 0x0000000FL +#define SQ_DYN_VGPR__FWD_PROGRESS_MASK 0x00000010L +#define SQ_DYN_VGPR__MAX_BLOCK_ALLOC_MASK 0x000000E0L +#define SQ_DYN_VGPR__BLOCK_SIZE_MASK 0x00000100L +//SQ_SHADER_CYCLES_LO +#define SQ_SHADER_CYCLES_LO__CYCLES_LO__SHIFT 0x0 +#define SQ_SHADER_CYCLES_LO__CYCLES_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_CYCLES_HI +#define SQ_SHADER_CYCLES_HI__CYCLES_HI__SHIFT 0x0 +#define SQ_SHADER_CYCLES_HI__CYCLES_HI_MASK 0x0FFFFFFFL +//SQ_DEBUG_HOST_TRAP_STATUS +#define SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT__SHIFT 0x0 +#define SQ_DEBUG_HOST_TRAP_STATUS__PENDING_COUNT_MASK 0x0000007FL +//SQG_GL1X_CTRL +#define SQG_GL1X_CTRL__TEMPORAL__SHIFT 0x0 +#define SQG_GL1X_CTRL__SCOPE__SHIFT 0x4 +#define SQG_GL1X_CTRL__TEMPORAL_MASK 0x00000007L +#define SQG_GL1X_CTRL__SCOPE_MASK 0x00000030L +//SQG_GL1X_STATUS +#define SQG_GL1X_STATUS__ACK_ERR_DETECTED__SHIFT 0x0 +#define SQG_GL1X_STATUS__XNACK_ERR_DETECTED__SHIFT 0x1 +#define SQG_GL1X_STATUS__ACK_ERR_DETECTED_MASK 0x00000001L +#define SQG_GL1X_STATUS__XNACK_ERR_DETECTED_MASK 0x00000002L +//SQG_CONFIG +#define SQG_CONFIG__SQG_ICPFT_EN__SHIFT 0x0 +#define SQG_CONFIG__SQG_ICPFT_CLR__SHIFT 0x1 +#define SQG_CONFIG__XNACK_INTR_MASK__SHIFT 0x10 +#define SQG_CONFIG__SQG_ICPFT_EN_MASK 0x00000001L +#define SQG_CONFIG__SQG_ICPFT_CLR_MASK 0x00000002L +#define SQG_CONFIG__XNACK_INTR_MASK_MASK 0xFFFF0000L +//SQ_PERF_SNAPSHOT_CTRL +#define SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK__SHIFT 0x1 +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL__SHIFT 0x11 +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL__SHIFT 0x12 +#define SQ_PERF_SNAPSHOT_CTRL__TEST_MODE__SHIFT 0x16 +#define SQ_PERF_SNAPSHOT_CTRL__RANDOM_SEED__SHIFT 0x17 +#define SQ_PERF_SNAPSHOT_CTRL__TIMER_ON_OFF_MASK 0x00000001L +#define SQ_PERF_SNAPSHOT_CTRL__VMID_MASK_MASK 0x0001FFFEL +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_SEL_MASK 0x00020000L +#define SQ_PERF_SNAPSHOT_CTRL__COUNT_INTERVAL_MASK 0x003C0000L +#define SQ_PERF_SNAPSHOT_CTRL__TEST_MODE_MASK 0x00400000L +#define SQ_PERF_SNAPSHOT_CTRL__RANDOM_SEED_MASK 0x07800000L +//CC_GC_SHADER_RATE_CONFIG_1 +#define CC_GC_SHADER_RATE_CONFIG_1__SHADER_RATE__SHIFT 0x1 +#define CC_GC_SHADER_RATE_CONFIG_1__SHADER_RATE_MASK 0x000007FEL +//SQ_INTERRUPT_AUTO_MASK +#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 +#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0x00FFFFFFL +//SQ_INTERRUPT_MSG_CTRL +#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 +#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x00000001L +//SQ_WATCH0_ADDR_H +#define SQ_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH0_ADDR_H__ADDR_MASK 0x01FFFFFFL +//SQ_WATCH0_ADDR_L +#define SQ_WATCH0_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH0_CNTL +#define SQ_WATCH0_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH0_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH0_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH0_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH0_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH0_CNTL__VALID_MASK 0x80000000L +//SQ_WATCH1_ADDR_H +#define SQ_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH1_ADDR_H__ADDR_MASK 0x01FFFFFFL +//SQ_WATCH1_ADDR_L +#define SQ_WATCH1_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH1_CNTL +#define SQ_WATCH1_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH1_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH1_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH1_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH1_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH1_CNTL__VALID_MASK 0x80000000L +//SQ_WATCH2_ADDR_H +#define SQ_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH2_ADDR_H__ADDR_MASK 0x01FFFFFFL +//SQ_WATCH2_ADDR_L +#define SQ_WATCH2_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH2_CNTL +#define SQ_WATCH2_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH2_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH2_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH2_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH2_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH2_CNTL__VALID_MASK 0x80000000L +//SQ_WATCH3_ADDR_H +#define SQ_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define SQ_WATCH3_ADDR_H__ADDR_MASK 0x01FFFFFFL +//SQ_WATCH3_ADDR_L +#define SQ_WATCH3_ADDR_L__ADDR__SHIFT 0x6 +#define SQ_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFFC0L +//SQ_WATCH3_CNTL +#define SQ_WATCH3_CNTL__MASK__SHIFT 0x0 +#define SQ_WATCH3_CNTL__VMID__SHIFT 0x18 +#define SQ_WATCH3_CNTL__VALID__SHIFT 0x1f +#define SQ_WATCH3_CNTL__MASK_MASK 0x00FFFFFFL +#define SQ_WATCH3_CNTL__VMID_MASK 0x0F000000L +#define SQ_WATCH3_CNTL__VALID_MASK 0x80000000L +//SQG_UTCL0_STATUS +#define SQG_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQG_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQG_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQG_UTCL0_STATUS__RESERVED__SHIFT 0x3 +#define SQG_UTCL0_STATUS__UNUSED__SHIFT 0x8 +#define SQG_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQG_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQG_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L +#define SQG_UTCL0_STATUS__RESERVED_MASK 0x000000F8L +#define SQG_UTCL0_STATUS__UNUSED_MASK 0xFFFFFF00L +//SQG_UTCL0_CNTL1 +#define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQG_UTCL0_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQG_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQG_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQG_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 +#define SQG_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define SQG_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define SQG_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE__SHIFT 0x19 +#define SQG_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQG_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQG_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQG_UTCL0_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define SQG_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQG_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQG_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQG_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQG_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define SQG_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define SQG_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE_MASK 0x02000000L +#define SQG_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQG_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQG_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQG_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQG_UTCL0_CNTL2 +#define SQG_UTCL0_CNTL2__SPARE__SHIFT 0x0 +#define SQG_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT 0x8 +#define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQG_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa +#define SQG_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQG_UTCL0_CNTL2__DISABLE_BURST__SHIFT 0x11 +#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define SQG_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQG_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define SQG_UTCL0_CNTL2__BIG_PAGE_DISABLE__SHIFT 0x1f +#define SQG_UTCL0_CNTL2__SPARE_MASK 0x000000FFL +#define SQG_UTCL0_CNTL2__COMP_SYNC_DISABLE_MASK 0x00000100L +#define SQG_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQG_UTCL0_CNTL2__ANY_LINE_VALID_MASK 0x00000400L +#define SQG_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQG_UTCL0_CNTL2__DISABLE_BURST_MASK 0x00020000L +#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define SQG_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define SQG_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define SQG_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define SQG_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define SQG_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define SQG_UTCL0_CNTL2__BIG_PAGE_DISABLE_MASK 0x80000000L +//SQG_UTCL0_RETRY +#define SQG_UTCL0_RETRY__INCR__SHIFT 0x0 +#define SQG_UTCL0_RETRY__COUNT__SHIFT 0x8 +#define SQG_UTCL0_RETRY__INCR_MASK 0x000000FFL +#define SQG_UTCL0_RETRY__COUNT_MASK 0x00000F00L +//SQG_VMID_FED_STATUS +#define SQG_VMID_FED_STATUS__VMID_MASK__SHIFT 0x0 +#define SQG_VMID_FED_STATUS__VMID_MASK_MASK 0x0000FFFFL +//SQG_VMID_FED_CLEAR +#define SQG_VMID_FED_CLEAR__VMID_MASK__SHIFT 0x0 +#define SQG_VMID_FED_CLEAR__VMID_MASK_MASK 0x0000FFFFL +//SQG_SE_PIT_CONTROL +#define SQG_SE_PIT_CONTROL__PIT_PM_ENABLE__SHIFT 0x0 +#define SQG_SE_PIT_CONTROL__PIT_PM_PRIMING_COOLDOWN__SHIFT 0x1 +#define SQG_SE_PIT_CONTROL__PIT_PM_STATUS_AVG_LENGTH__SHIFT 0x6 +#define SQG_SE_PIT_CONTROL__PIT_PM_IDLE_THRESHOLD__SHIFT 0x8 +#define SQG_SE_PIT_CONTROL__PIT_PM_IDLE_CYCLES__SHIFT 0xc +#define SQG_SE_PIT_CONTROL__PIT_PM_ACTIVE_THRESHOLD__SHIFT 0x12 +#define SQG_SE_PIT_CONTROL__PIT_PM_ACTIVE_CYCLES__SHIFT 0x16 +#define SQG_SE_PIT_CONTROL__PIT_PM_ENABLE_MASK 0x00000001L +#define SQG_SE_PIT_CONTROL__PIT_PM_PRIMING_COOLDOWN_MASK 0x00000006L +#define SQG_SE_PIT_CONTROL__PIT_PM_STATUS_AVG_LENGTH_MASK 0x000000C0L +#define SQG_SE_PIT_CONTROL__PIT_PM_IDLE_THRESHOLD_MASK 0x00000F00L +#define SQG_SE_PIT_CONTROL__PIT_PM_IDLE_CYCLES_MASK 0x0003F000L +#define SQG_SE_PIT_CONTROL__PIT_PM_ACTIVE_THRESHOLD_MASK 0x003C0000L +#define SQG_SE_PIT_CONTROL__PIT_PM_ACTIVE_CYCLES_MASK 0x0FC00000L +//SQG_UTCL0_RETRY_TIMER_THRESHOLD_HI +#define SQG_UTCL0_RETRY_TIMER_THRESHOLD_HI__VALUE__SHIFT 0x0 +#define SQG_UTCL0_RETRY_TIMER_THRESHOLD_HI__VALUE_MASK 0xFFFFFFFFL +//SQG_UTCL0_RETRY_TIMER_THRESHOLD_LO +#define SQG_UTCL0_RETRY_TIMER_THRESHOLD_LO__VALUE__SHIFT 0x0 +#define SQG_UTCL0_RETRY_TIMER_THRESHOLD_LO__VALUE_MASK 0xFFFFFFFFL +//SQG_WS_INSERTION_COUNT +#define SQG_WS_INSERTION_COUNT__COUNT__SHIFT 0x0 +#define SQG_WS_INSERTION_COUNT__COUNT_MASK 0x0000FFFFL +//SQG_WS_SPI_STATUS +#define SQG_WS_SPI_STATUS__COUNT__SHIFT 0x0 +#define SQG_WS_SPI_STATUS__WS_COUNT__SHIFT 0x10 +#define SQG_WS_SPI_STATUS__COUNT_MASK 0x0000FFFFL +#define SQG_WS_SPI_STATUS__WS_COUNT_MASK 0xFFFF0000L +//SQ_IND_INDEX +#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 +#define SQ_IND_INDEX__WORKITEM_ID__SHIFT 0x5 +#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xb +#define SQ_IND_INDEX__INDEX__SHIFT 0x10 +#define SQ_IND_INDEX__WAVE_ID_MASK 0x0000001FL +#define SQ_IND_INDEX__WORKITEM_ID_MASK 0x000007E0L +#define SQ_IND_INDEX__AUTO_INCR_MASK 0x00000800L +#define SQ_IND_INDEX__INDEX_MASK 0xFFFF0000L +//SQ_IND_DATA +#define SQ_IND_DATA__DATA__SHIFT 0x0 +#define SQ_IND_DATA__DATA_MASK 0xFFFFFFFFL +//SQ_CMD +#define SQ_CMD__CMD__SHIFT 0x0 +#define SQ_CMD__MODE__SHIFT 0x4 +#define SQ_CMD__CHECK_VMID__SHIFT 0x7 +#define SQ_CMD__DATA__SHIFT 0x8 +#define SQ_CMD__WAVE_ID__SHIFT 0x10 +#define SQ_CMD__QUEUE_ID__SHIFT 0x18 +#define SQ_CMD__VM_ID__SHIFT 0x1c +#define SQ_CMD__CMD_MASK 0x0000000FL +#define SQ_CMD__MODE_MASK 0x00000070L +#define SQ_CMD__CHECK_VMID_MASK 0x00000080L +#define SQ_CMD__DATA_MASK 0x00000F00L +#define SQ_CMD__WAVE_ID_MASK 0x001F0000L +#define SQ_CMD__QUEUE_ID_MASK 0x07000000L +#define SQ_CMD__VM_ID_MASK 0xF0000000L +//SQC_WSM_CONTROL +#define SQC_WSM_CONTROL__WS_GO__SHIFT 0x0 +#define SQC_WSM_CONTROL__WS_INTENSITY__SHIFT 0x1 +#define SQC_WSM_CONTROL__WS_PRIORITY_MODE__SHIFT 0x3 +#define SQC_WSM_CONTROL__WS_PERIOD__SHIFT 0x4 +#define SQC_WSM_CONTROL__WS_RATE__SHIFT 0xc +#define SQC_WSM_CONTROL__WS_PERIOD_COUNT__SHIFT 0x14 +#define SQC_WSM_CONTROL__WS_GO_MASK 0x00000001L +#define SQC_WSM_CONTROL__WS_INTENSITY_MASK 0x00000006L +#define SQC_WSM_CONTROL__WS_PRIORITY_MODE_MASK 0x00000008L +#define SQC_WSM_CONTROL__WS_PERIOD_MASK 0x00000FF0L +#define SQC_WSM_CONTROL__WS_RATE_MASK 0x000FF000L +#define SQC_WSM_CONTROL__WS_PERIOD_COUNT_MASK 0x00F00000L +//SQC_PIT_CONTROL0 +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_DIDT_THRESHOLD_2__SHIFT 0x0 +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_DIDT_THRESHOLD_4__SHIFT 0x3 +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_DIDT_THRESHOLD_2__SHIFT 0x6 +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_DIDT_THRESHOLD_4__SHIFT 0x9 +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_LEVEL__SHIFT 0xc +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_RATE__SHIFT 0xf +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_CYCLES__SHIFT 0x11 +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_LEVEL__SHIFT 0x15 +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_RATE__SHIFT 0x18 +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_CYCLES__SHIFT 0x1a +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_DIDT_THRESHOLD_2_MASK 0x00000007L +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_DIDT_THRESHOLD_4_MASK 0x00000038L +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_DIDT_THRESHOLD_2_MASK 0x000001C0L +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_DIDT_THRESHOLD_4_MASK 0x00000E00L +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_LEVEL_MASK 0x00007000L +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_RATE_MASK 0x00018000L +#define SQC_PIT_CONTROL0__PIT_PRIMED_US_THROTTLE_CYCLES_MASK 0x001E0000L +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_LEVEL_MASK 0x00E00000L +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_RATE_MASK 0x03000000L +#define SQC_PIT_CONTROL0__PIT_PRIMED_OS_THROTTLE_CYCLES_MASK 0x3C000000L +//SQC_PIT_CONTROL1 +#define SQC_PIT_CONTROL1__LOCAL_THROTTLE_EN__SHIFT 0x0 +#define SQC_PIT_CONTROL1__LOCAL_US_DIDT_THRESHOLD_2__SHIFT 0x1 +#define SQC_PIT_CONTROL1__LOCAL_US_DIDT_THRESHOLD_4__SHIFT 0x4 +#define SQC_PIT_CONTROL1__LOCAL_OS_DIDT_THRESHOLD_2__SHIFT 0x7 +#define SQC_PIT_CONTROL1__LOCAL_OS_DIDT_THRESHOLD_4__SHIFT 0xa +#define SQC_PIT_CONTROL1__LOCAL_US_THROTTLE_RATE__SHIFT 0xd +#define SQC_PIT_CONTROL1__LOCAL_US_THROTTLE_CYCLES__SHIFT 0xf +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_LEVEL__SHIFT 0x13 +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_RATE__SHIFT 0x16 +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_CYCLES__SHIFT 0x18 +#define SQC_PIT_CONTROL1__LOCAL_THROTTLE_EN_MASK 0x00000001L +#define SQC_PIT_CONTROL1__LOCAL_US_DIDT_THRESHOLD_2_MASK 0x0000000EL +#define SQC_PIT_CONTROL1__LOCAL_US_DIDT_THRESHOLD_4_MASK 0x00000070L +#define SQC_PIT_CONTROL1__LOCAL_OS_DIDT_THRESHOLD_2_MASK 0x00000380L +#define SQC_PIT_CONTROL1__LOCAL_OS_DIDT_THRESHOLD_4_MASK 0x00001C00L +#define SQC_PIT_CONTROL1__LOCAL_US_THROTTLE_RATE_MASK 0x00006000L +#define SQC_PIT_CONTROL1__LOCAL_US_THROTTLE_CYCLES_MASK 0x00078000L +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_LEVEL_MASK 0x00380000L +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_RATE_MASK 0x00C00000L +#define SQC_PIT_CONTROL1__LOCAL_OS_THROTTLE_CYCLES_MASK 0x0F000000L +//SQC_PIT_CONTROL2 +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_WINDOW__SHIFT 0x0 +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_IDLE_THRESHOLD__SHIFT 0x2 +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_ACTIVE_THRESHOLD__SHIFT 0x8 +#define SQC_PIT_CONTROL2__PIT_PF_LEVEL__SHIFT 0xe +#define SQC_PIT_CONTROL2__PIT_PF_CYCLES__SHIFT 0x13 +#define SQC_PIT_CONTROL2__PIT_PF_CYCLES_MIN__SHIFT 0x17 +#define SQC_PIT_CONTROL2__PIT_PRIMED_US_INITIAL_DELAY_SA_STEP__SHIFT 0x1b +#define SQC_PIT_CONTROL2__PIT_PRIMED_US_INITIAL_DELAY_WGP_STEP__SHIFT 0x1d +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_WINDOW_MASK 0x00000003L +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_IDLE_THRESHOLD_MASK 0x000000FCL +#define SQC_PIT_CONTROL2__PIT_STATUS_AVG_ACTIVE_THRESHOLD_MASK 0x00003F00L +#define SQC_PIT_CONTROL2__PIT_PF_LEVEL_MASK 0x0007C000L +#define SQC_PIT_CONTROL2__PIT_PF_CYCLES_MASK 0x00780000L +#define SQC_PIT_CONTROL2__PIT_PF_CYCLES_MIN_MASK 0x07800000L +#define SQC_PIT_CONTROL2__PIT_PRIMED_US_INITIAL_DELAY_SA_STEP_MASK 0x18000000L +#define SQC_PIT_CONTROL2__PIT_PRIMED_US_INITIAL_DELAY_WGP_STEP_MASK 0x60000000L +//SQC_UTCL0_RETRY +#define SQC_UTCL0_RETRY__INCR__SHIFT 0x0 +#define SQC_UTCL0_RETRY__COUNT__SHIFT 0x8 +#define SQC_UTCL0_RETRY__INCR_MASK 0x000000FFL +#define SQC_UTCL0_RETRY__COUNT_MASK 0x00000F00L +//SQC_MISC_CONFIG +#define SQC_MISC_CONFIG__SQC_SQ_MGCG_OVERSHOOT_PROG_DELAY__SHIFT 0x0 +#define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE__SHIFT 0x5 +#define SQC_MISC_CONFIG__SQ_SPI_MSG_FGCG_OVERRIDE__SHIFT 0x6 +#define SQC_MISC_CONFIG__SPI_SQ_EXPALLOC_FGCG_OVERRIDE__SHIFT 0x7 +#define SQC_MISC_CONFIG__SQC_SQ_DATA_RET_FGCG_OVERRIDE__SHIFT 0x8 +#define SQC_MISC_CONFIG__SQC_SQ_INST_RET_FGCG_OVERRIDE__SHIFT 0x9 +#define SQC_MISC_CONFIG__SQC_GCR_RSP_FGCG_OVERRIDE__SHIFT 0xa +#define SQC_MISC_CONFIG__ICLK_MGCG_DISABLE__SHIFT 0xb +#define SQC_MISC_CONFIG__ICLK_BANK_MGCG_DISABLE__SHIFT 0xc +#define SQC_MISC_CONFIG__DCLK_MGCG_DISABLE__SHIFT 0xd +#define SQC_MISC_CONFIG__GCLK_MGCG_DISABLE__SHIFT 0xe +#define SQC_MISC_CONFIG__MCLK_MGCG_DISABLE__SHIFT 0xf +#define SQC_MISC_CONFIG__PCLK_MGCG_DISABLE__SHIFT 0x10 +#define SQC_MISC_CONFIG__BCLK_MGCG_DISABLE__SHIFT 0x11 +#define SQC_MISC_CONFIG__SQC_TA_RESET_FGCG_OVERRIDE__SHIFT 0x12 +#define SQC_MISC_CONFIG__SQC_MCA_FGCG_OVERRIDE__SHIFT 0x13 +#define SQC_MISC_CONFIG__DCLK_BANK_MGCG_DISABLE__SHIFT 0x14 +#define SQC_MISC_CONFIG__SQC_SQ_BARRIER_DONE_FGCG_OVERRIDE__SHIFT 0x15 +#define SQC_MISC_CONFIG__SQC_SQ_MSGDONE_FGCG_OVERRIDE__SHIFT 0x16 +#define SQC_MISC_CONFIG__CMCLK_MGCG_DISABLE__SHIFT 0x17 +#define SQC_MISC_CONFIG__SQC_GL1_CLKEN_OVERRIDE__SHIFT 0x18 +#define SQC_MISC_CONFIG__SQC_CORE_OVERRIDE__SHIFT 0x19 +#define SQC_MISC_CONFIG__ICLK_HMF_BS_MGCG_DISABLE__SHIFT 0x1a +#define SQC_MISC_CONFIG__ICLK_CC_MGCG_DISABLE__SHIFT 0x1b +#define SQC_MISC_CONFIG__DCLK_HMF_BS_MGCG_DISABLE__SHIFT 0x1c +#define SQC_MISC_CONFIG__DCLK_CC_MGCG_DISABLE__SHIFT 0x1d +#define SQC_MISC_CONFIG__SQC_SQ_INVALIDATE_FGCG_DISABLE__SHIFT 0x1e +#define SQC_MISC_CONFIG__SQC_UTCL0_FGCG_OVERRIDE__SHIFT 0x1f +#define SQC_MISC_CONFIG__SQC_SQ_MGCG_OVERSHOOT_PROG_DELAY_MASK 0x0000001FL +#define SQC_MISC_CONFIG__SQC_SPI_TTRACE_FGCG_OVERRIDE_MASK 0x00000020L +#define SQC_MISC_CONFIG__SQ_SPI_MSG_FGCG_OVERRIDE_MASK 0x00000040L +#define SQC_MISC_CONFIG__SPI_SQ_EXPALLOC_FGCG_OVERRIDE_MASK 0x00000080L +#define SQC_MISC_CONFIG__SQC_SQ_DATA_RET_FGCG_OVERRIDE_MASK 0x00000100L +#define SQC_MISC_CONFIG__SQC_SQ_INST_RET_FGCG_OVERRIDE_MASK 0x00000200L +#define SQC_MISC_CONFIG__SQC_GCR_RSP_FGCG_OVERRIDE_MASK 0x00000400L +#define SQC_MISC_CONFIG__ICLK_MGCG_DISABLE_MASK 0x00000800L +#define SQC_MISC_CONFIG__ICLK_BANK_MGCG_DISABLE_MASK 0x00001000L +#define SQC_MISC_CONFIG__DCLK_MGCG_DISABLE_MASK 0x00002000L +#define SQC_MISC_CONFIG__GCLK_MGCG_DISABLE_MASK 0x00004000L +#define SQC_MISC_CONFIG__MCLK_MGCG_DISABLE_MASK 0x00008000L +#define SQC_MISC_CONFIG__PCLK_MGCG_DISABLE_MASK 0x00010000L +#define SQC_MISC_CONFIG__BCLK_MGCG_DISABLE_MASK 0x00020000L +#define SQC_MISC_CONFIG__SQC_TA_RESET_FGCG_OVERRIDE_MASK 0x00040000L +#define SQC_MISC_CONFIG__SQC_MCA_FGCG_OVERRIDE_MASK 0x00080000L +#define SQC_MISC_CONFIG__DCLK_BANK_MGCG_DISABLE_MASK 0x00100000L +#define SQC_MISC_CONFIG__SQC_SQ_BARRIER_DONE_FGCG_OVERRIDE_MASK 0x00200000L +#define SQC_MISC_CONFIG__SQC_SQ_MSGDONE_FGCG_OVERRIDE_MASK 0x00400000L +#define SQC_MISC_CONFIG__CMCLK_MGCG_DISABLE_MASK 0x00800000L +#define SQC_MISC_CONFIG__SQC_GL1_CLKEN_OVERRIDE_MASK 0x01000000L +#define SQC_MISC_CONFIG__SQC_CORE_OVERRIDE_MASK 0x02000000L +#define SQC_MISC_CONFIG__ICLK_HMF_BS_MGCG_DISABLE_MASK 0x04000000L +#define SQC_MISC_CONFIG__ICLK_CC_MGCG_DISABLE_MASK 0x08000000L +#define SQC_MISC_CONFIG__DCLK_HMF_BS_MGCG_DISABLE_MASK 0x10000000L +#define SQC_MISC_CONFIG__DCLK_CC_MGCG_DISABLE_MASK 0x20000000L +#define SQC_MISC_CONFIG__SQC_SQ_INVALIDATE_FGCG_DISABLE_MASK 0x40000000L +#define SQC_MISC_CONFIG__SQC_UTCL0_FGCG_OVERRIDE_MASK 0x80000000L +//SQ_TIMEOUT_CONFIG +#define SQ_TIMEOUT_CONFIG__PERIOD_SEL__SHIFT 0x0 +#define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE__SHIFT 0x6 +#define SQ_TIMEOUT_CONFIG__PERIOD_SEL_MASK 0x0000003FL +#define SQ_TIMEOUT_CONFIG__TIMEOUT_FATAL_DISABLE_MASK 0x00000040L +//SQ_TIMEOUT_STATUS_SIMD01 +#define SQ_TIMEOUT_STATUS_SIMD01__WAVE_TIMEOUT__SHIFT 0x0 +#define SQ_TIMEOUT_STATUS_SIMD01__WAVE_TIMEOUT_MASK 0xFFFFFFFFL +//SQ_TIMEOUT_STATUS_SIMD23 +#define SQ_TIMEOUT_STATUS_SIMD23__WAVE_TIMEOUT__SHIFT 0x0 +#define SQ_TIMEOUT_STATUS_SIMD23__WAVE_TIMEOUT_MASK 0xFFFFFFFFL +//SQC_UTCL0_STATUS +#define SQC_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define SQC_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define SQC_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 +#define SQC_UTCL0_STATUS__RESERVED__SHIFT 0x3 +#define SQC_UTCL0_STATUS__UNUSED__SHIFT 0x8 +#define SQC_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define SQC_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define SQC_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L +#define SQC_UTCL0_STATUS__RESERVED_MASK 0x000000F8L +#define SQC_UTCL0_STATUS__UNUSED_MASK 0xFFFFFF00L +//SQC_UTCL0_CNTL1 +#define SQC_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define SQC_UTCL0_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define SQC_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define SQC_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 +#define SQC_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define SQC_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 +#define SQC_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define SQC_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define SQC_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE__SHIFT 0x19 +#define SQC_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a +#define SQC_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define SQC_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQC_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQC_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define SQC_UTCL0_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define SQC_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define SQC_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L +#define SQC_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define SQC_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L +#define SQC_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define SQC_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define SQC_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE_MASK 0x02000000L +#define SQC_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L +#define SQC_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define SQC_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define SQC_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//SQC_UTCL0_CNTL2 +#define SQC_UTCL0_CNTL2__SPARE__SHIFT 0x0 +#define SQC_UTCL0_CNTL2__COMP_SYNC_DISABLE__SHIFT 0x8 +#define SQC_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define SQC_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa +#define SQC_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define SQC_UTCL0_CNTL2__DISABLE_BURST__SHIFT 0x11 +#define SQC_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define SQC_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define SQC_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define SQC_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define SQC_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define SQC_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define SQC_UTCL0_CNTL2__BIG_PAGE_DISABLE__SHIFT 0x1f +#define SQC_UTCL0_CNTL2__SPARE_MASK 0x000000FFL +#define SQC_UTCL0_CNTL2__COMP_SYNC_DISABLE_MASK 0x00000100L +#define SQC_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define SQC_UTCL0_CNTL2__ANY_LINE_VALID_MASK 0x00000400L +#define SQC_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define SQC_UTCL0_CNTL2__DISABLE_BURST_MASK 0x00020000L +#define SQC_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define SQC_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define SQC_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define SQC_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define SQC_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define SQC_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define SQC_UTCL0_CNTL2__BIG_PAGE_DISABLE_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_shsdec +//SX_DEBUG_BUSY +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ3__SHIFT 0x0 +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ2__SHIFT 0x1 +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ1__SHIFT 0x2 +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALID__SHIFT 0x3 +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ3__SHIFT 0x4 +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ2__SHIFT 0x5 +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ1__SHIFT 0x6 +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALID__SHIFT 0x7 +#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x9 +#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0xa +#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0xb +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0xc +#define SX_DEBUG_BUSY__SX_SX_IN_VALID__SHIFT 0xd +#define SX_DEBUG_BUSY__SX_SX_OUT_VALID__SHIFT 0xe +#define SX_DEBUG_BUSY__RESERVED__SHIFT 0xf +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ3_MASK 0x00000001L +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ2_MASK 0x00000002L +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALIDQ1_MASK 0x00000004L +#define SX_DEBUG_BUSY__COL_WRCTRL1_VALID_MASK 0x00000008L +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ3_MASK 0x00000010L +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ2_MASK 0x00000020L +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALIDQ1_MASK 0x00000040L +#define SX_DEBUG_BUSY__COL_WRCTRL0_VALID_MASK 0x00000080L +#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x00000200L +#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x00000400L +#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x00000800L +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x00001000L +#define SX_DEBUG_BUSY__SX_SX_IN_VALID_MASK 0x00002000L +#define SX_DEBUG_BUSY__SX_SX_OUT_VALID_MASK 0x00004000L +#define SX_DEBUG_BUSY__RESERVED_MASK 0xFFFF8000L +//SX_DEBUG_BUSY_2 +#define SX_DEBUG_BUSY_2__COL_SCBD0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1 +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2 +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4 +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5 +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7 +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8 +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_2__COL_DBIF3_QUAD_FREE__SHIFT 0xf +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_2__COL_DBIF2_QUAD_FREE__SHIFT 0x12 +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_2__COL_DBIF1_QUAD_FREE__SHIFT 0x15 +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_2__COL_DBIF0_QUAD_FREE__SHIFT 0x18 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_2__COL_SCBD0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x00000002L +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x00000004L +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x00000010L +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x00000020L +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x00000080L +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x00000100L +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x00000400L +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x00000800L +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_2__COL_DBIF3_QUAD_FREE_MASK 0x00008000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_2__COL_DBIF2_QUAD_FREE_MASK 0x00040000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_2__COL_DBIF1_QUAD_FREE_MASK 0x00200000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_2__COL_DBIF0_QUAD_FREE_MASK 0x01000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_3 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_4 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK7_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_4__COL_BUFF3_BANK6_VAL1_BUSY_MASK 0x80000000L +//SX_DEBUG_1 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 +#define SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE__SHIFT 0x7 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc +#define SX_DEBUG_1__DISABLE_REP_FGCG__SHIFT 0xd +#define SX_DEBUG_1__DISABLE_RAM_FGCG__SHIFT 0xf +#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT__SHIFT 0x11 +#define SX_DEBUG_1__DISABLE_BC_RB_PLUS__SHIFT 0x12 +#define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING__SHIFT 0x13 +#define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT__SHIFT 0x14 +#define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT__SHIFT 0x16 +#define SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT__SHIFT 0x17 +#define SX_DEBUG_1__DISABLE_DBIF_PIX_ENABLE_FGCG__SHIFT 0x18 +#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x19 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x0000007FL +#define SX_DEBUG_1__ENABLE_FIFO_DEBUG_WRITE_MASK 0x00000080L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x00000100L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x00000200L +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x00000400L +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x00000800L +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x00001000L +#define SX_DEBUG_1__DISABLE_REP_FGCG_MASK 0x00002000L +#define SX_DEBUG_1__DISABLE_RAM_FGCG_MASK 0x00008000L +#define SX_DEBUG_1__DISABLE_COL_VAL_READ_OPT_MASK 0x00020000L +#define SX_DEBUG_1__DISABLE_BC_RB_PLUS_MASK 0x00040000L +#define SX_DEBUG_1__DISABLE_NATIVE_DOWNCVT_FMT_MAPPING_MASK 0x00080000L +#define SX_DEBUG_1__DISABLE_SCBD_READ_PWR_OPT_MASK 0x00100000L +#define SX_DEBUG_1__DISABLE_DOWNCVT_PWR_OPT_MASK 0x00400000L +#define SX_DEBUG_1__DISABLE_POS_BUFF_REUSE_OPT_MASK 0x00800000L +#define SX_DEBUG_1__DISABLE_DBIF_PIX_ENABLE_FGCG_MASK 0x01000000L +#define SX_DEBUG_1__DEBUG_DATA_MASK 0xFE000000L +//SX_DEBUG_BUSY_5 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK6_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK6_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK5_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_5__COL_BUFF3_BANK4_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK7_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK6_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK5_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_5__COL_BUFF2_BANK4_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL3_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL2_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL1_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK7_VAL0_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL3_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL2_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_5__COL_BUFF1_BANK6_VAL1_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_6 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK6_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_6__COL_REQ3_CREDIT_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_6__COL_REQ3_FLOP_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_6__COL_REQ2_CREDIT_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_6__COL_REQ2_FLOP_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_6__COL_REQ1_CREDIT_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_6__COL_REQ1_FLOP_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_6__COL_REQ0_CREDIT_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK6_VAL0_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL3_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL2_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL1_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK5_VAL0_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL3_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL2_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL1_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_6__COL_BUFF1_BANK4_VAL0_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL3_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL2_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL1_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK7_VAL0_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL3_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL2_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL1_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK6_VAL0_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL3_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL2_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL1_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK5_VAL0_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL3_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL2_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL1_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_6__COL_BUFF0_BANK4_VAL0_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_6__COL_REQ3_CREDIT_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_6__COL_REQ3_FLOP_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_6__COL_REQ2_CREDIT_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_6__COL_REQ2_FLOP_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_6__COL_REQ1_CREDIT_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_6__COL_REQ1_FLOP_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_6__COL_REQ0_CREDIT_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_7 +#define SX_DEBUG_BUSY_7__COL_REQ0_FLOP_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_7__COL_SCBD1_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1__SHIFT 0x2 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1_ADJ__SHIFT 0x3 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ2__SHIFT 0x4 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ3__SHIFT 0x5 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ4__SHIFT 0x6 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ5__SHIFT 0x7 +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALID_OUT__SHIFT 0x8 +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1__SHIFT 0x9 +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1_ADJ__SHIFT 0xa +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ2__SHIFT 0xb +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ3__SHIFT 0xc +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ4__SHIFT 0xd +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ5__SHIFT 0xe +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALID_OUT__SHIFT 0xf +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1__SHIFT 0x10 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1_ADJ__SHIFT 0x11 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ2__SHIFT 0x12 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ3__SHIFT 0x13 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ4__SHIFT 0x14 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ5__SHIFT 0x15 +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALID_OUT__SHIFT 0x16 +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1__SHIFT 0x17 +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1_ADJ__SHIFT 0x18 +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ2__SHIFT 0x19 +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ3__SHIFT 0x1a +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ4__SHIFT 0x1b +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ5__SHIFT 0x1c +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALID_OUT__SHIFT 0x1d +#define SX_DEBUG_BUSY_7__RESERVED__SHIFT 0x1e +#define SX_DEBUG_BUSY_7__COL_REQ0_FLOP_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_7__COL_SCBD1_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1_MASK 0x00000004L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ1_ADJ_MASK 0x00000008L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ2_MASK 0x00000010L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ3_MASK 0x00000020L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ4_MASK 0x00000040L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALIDQ5_MASK 0x00000080L +#define SX_DEBUG_BUSY_7__COL_BLEND3_DATA_VALID_OUT_MASK 0x00000100L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1_MASK 0x00000200L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ1_ADJ_MASK 0x00000400L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ2_MASK 0x00000800L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ3_MASK 0x00001000L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ4_MASK 0x00002000L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALIDQ5_MASK 0x00004000L +#define SX_DEBUG_BUSY_7__COL_BLEND2_DATA_VALID_OUT_MASK 0x00008000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1_MASK 0x00010000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ1_ADJ_MASK 0x00020000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ2_MASK 0x00040000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ3_MASK 0x00080000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ4_MASK 0x00100000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALIDQ5_MASK 0x00200000L +#define SX_DEBUG_BUSY_7__COL_BLEND1_DATA_VALID_OUT_MASK 0x00400000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1_MASK 0x00800000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ1_ADJ_MASK 0x01000000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ2_MASK 0x02000000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ3_MASK 0x04000000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ4_MASK 0x08000000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALIDQ5_MASK 0x10000000L +#define SX_DEBUG_BUSY_7__COL_BLEND0_DATA_VALID_OUT_MASK 0x20000000L +#define SX_DEBUG_BUSY_7__RESERVED_MASK 0xC0000000L +//SX_DEBUG_BUSY_8 +#define SX_DEBUG_BUSY_8__POS_BANK7VAL3_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_8__POS_BANK7VAL2_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_8__POS_BANK7VAL1_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_8__POS_BANK7VAL0_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_8__POS_BANK6VAL3_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_8__POS_BANK6VAL2_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_8__POS_BANK6VAL1_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_8__POS_BANK6VAL0_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_8__POS_BANK5VAL3_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_8__POS_BANK5VAL2_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_8__POS_BANK5VAL1_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_8__POS_BANK5VAL0_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_8__POS_BANK4VAL3_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_8__POS_BANK4VAL2_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_8__POS_BANK4VAL1_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_8__POS_BANK4VAL0_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_8__POS_BANK3VAL3_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_8__POS_BANK3VAL2_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_8__POS_BANK3VAL1_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_8__POS_BANK3VAL0_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_8__POS_BANK2VAL3_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_8__POS_BANK2VAL2_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_8__POS_BANK2VAL1_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_8__POS_BANK2VAL0_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_8__POS_BANK1VAL3_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_8__POS_BANK1VAL2_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_8__POS_BANK1VAL1_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_8__POS_BANK1VAL0_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_8__POS_BANK0VAL3_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_8__POS_BANK0VAL2_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_8__POS_BANK0VAL1_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_8__POS_BANK0VAL0_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_8__POS_BANK7VAL3_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_8__POS_BANK7VAL2_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_8__POS_BANK7VAL1_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_8__POS_BANK7VAL0_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_8__POS_BANK6VAL3_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_8__POS_BANK6VAL2_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_8__POS_BANK6VAL1_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_8__POS_BANK6VAL0_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_8__POS_BANK5VAL3_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_8__POS_BANK5VAL2_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_8__POS_BANK5VAL1_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_8__POS_BANK5VAL0_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_8__POS_BANK4VAL3_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_8__POS_BANK4VAL2_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_8__POS_BANK4VAL1_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_8__POS_BANK4VAL0_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_8__POS_BANK3VAL3_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_8__POS_BANK3VAL2_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_8__POS_BANK3VAL1_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_8__POS_BANK3VAL0_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_8__POS_BANK2VAL3_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_8__POS_BANK2VAL2_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_8__POS_BANK2VAL1_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_8__POS_BANK2VAL0_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_8__POS_BANK1VAL3_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_8__POS_BANK1VAL2_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_8__POS_BANK1VAL1_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_8__POS_BANK1VAL0_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_8__POS_BANK0VAL3_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_8__POS_BANK0VAL2_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_8__POS_BANK0VAL1_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_8__POS_BANK0VAL0_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_9 +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL3_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL2_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL1_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL0_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL3_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL2_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL1_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL0_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL3_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL2_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL1_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL0_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL3_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL2_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL1_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL0_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL3_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL2_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL1_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL0_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL3_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL2_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL1_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL0_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL3_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL2_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL1_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL0_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL3_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL2_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL1_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL0_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL3_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL2_BUSY_MASK 0x00000002L +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL1_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_9__IDX_BANK7VAL0_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL3_BUSY_MASK 0x00000010L +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL2_BUSY_MASK 0x00000020L +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL1_BUSY_MASK 0x00000040L +#define SX_DEBUG_BUSY_9__IDX_BANK6VAL0_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL3_BUSY_MASK 0x00000100L +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL2_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL1_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_9__IDX_BANK5VAL0_BUSY_MASK 0x00000800L +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL3_BUSY_MASK 0x00001000L +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL2_BUSY_MASK 0x00002000L +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL1_BUSY_MASK 0x00004000L +#define SX_DEBUG_BUSY_9__IDX_BANK4VAL0_BUSY_MASK 0x00008000L +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL3_BUSY_MASK 0x00010000L +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL2_BUSY_MASK 0x00020000L +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL1_BUSY_MASK 0x00040000L +#define SX_DEBUG_BUSY_9__IDX_BANK3VAL0_BUSY_MASK 0x00080000L +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL3_BUSY_MASK 0x00100000L +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL2_BUSY_MASK 0x00200000L +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL1_BUSY_MASK 0x00400000L +#define SX_DEBUG_BUSY_9__IDX_BANK2VAL0_BUSY_MASK 0x00800000L +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL3_BUSY_MASK 0x01000000L +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL2_BUSY_MASK 0x02000000L +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL1_BUSY_MASK 0x04000000L +#define SX_DEBUG_BUSY_9__IDX_BANK1VAL0_BUSY_MASK 0x08000000L +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL3_BUSY_MASK 0x10000000L +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL2_BUSY_MASK 0x20000000L +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL1_BUSY_MASK 0x40000000L +#define SX_DEBUG_BUSY_9__IDX_BANK0VAL0_BUSY_MASK 0x80000000L +//SX_DEBUG_BUSY_10 +#define SX_DEBUG_BUSY_10__POS_SCBD_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_10__POS_FREE_OR_VALIDS__SHIFT 0x1 +#define SX_DEBUG_BUSY_10__POS_REQUESTER_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_10__PA_SX_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ3__SHIFT 0x4 +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ2__SHIFT 0x5 +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ1__SHIFT 0x6 +#define SX_DEBUG_BUSY_10__IDX_SCBD_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_10__IDX_FREE_OR_VALIDS__SHIFT 0x8 +#define SX_DEBUG_BUSY_10__IDX_REQUESTER_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_10__PA_SX_IDX_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ3__SHIFT 0xb +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ2__SHIFT 0xc +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ1__SHIFT 0xd +#define SX_DEBUG_BUSY_10__RESERVED__SHIFT 0xe +#define SX_DEBUG_BUSY_10__POS_SCBD_BUSY_MASK 0x00000001L +#define SX_DEBUG_BUSY_10__POS_FREE_OR_VALIDS_MASK 0x00000002L +#define SX_DEBUG_BUSY_10__POS_REQUESTER_BUSY_MASK 0x00000004L +#define SX_DEBUG_BUSY_10__PA_SX_BUSY_MASK 0x00000008L +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ3_MASK 0x00000010L +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ2_MASK 0x00000020L +#define SX_DEBUG_BUSY_10__POS_WRCTRL1_VALIDQ1_MASK 0x00000040L +#define SX_DEBUG_BUSY_10__IDX_SCBD_BUSY_MASK 0x00000080L +#define SX_DEBUG_BUSY_10__IDX_FREE_OR_VALIDS_MASK 0x00000100L +#define SX_DEBUG_BUSY_10__IDX_REQUESTER_BUSY_MASK 0x00000200L +#define SX_DEBUG_BUSY_10__PA_SX_IDX_BUSY_MASK 0x00000400L +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ3_MASK 0x00000800L +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ2_MASK 0x00001000L +#define SX_DEBUG_BUSY_10__IDX_WRCTRL1_VALIDQ1_MASK 0x00002000L +#define SX_DEBUG_BUSY_10__RESERVED_MASK 0xFFFFC000L +//SPI_PS_MAX_WAVE_ID +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID__SHIFT 0x10 +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +#define SPI_PS_MAX_WAVE_ID__MAX_COLLISION_WAVE_ID_MASK 0x03FF0000L +//SPI_SCRATCH_ADDR_STATUS +#define SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED__SHIFT 0x1 +#define SPI_SCRATCH_ADDR_STATUS__ME_ID__SHIFT 0x2 +#define SPI_SCRATCH_ADDR_STATUS__PIPE_ID__SHIFT 0x4 +#define SPI_SCRATCH_ADDR_STATUS__OVERFLOW_DETECTED_MASK 0x00000002L +#define SPI_SCRATCH_ADDR_STATUS__ME_ID_MASK 0x0000000CL +#define SPI_SCRATCH_ADDR_STATUS__PIPE_ID_MASK 0x00000030L +//SPI_GFX_CNTL +#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 +#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x00000001L +//SPI_DEBUG_CNTL_2 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_0__SHIFT 0x0 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_1__SHIFT 0x1 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_2__SHIFT 0x2 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_3__SHIFT 0x3 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_4__SHIFT 0x4 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_5__SHIFT 0x5 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_6__SHIFT 0x6 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_7__SHIFT 0x7 +#define SPI_DEBUG_CNTL_2__DISABLE_INTRA_PRIM_CONFLICT__SHIFT 0x8 +#define SPI_DEBUG_CNTL_2__DISABLE_PS_AGE_SORT__SHIFT 0x9 +#define SPI_DEBUG_CNTL_2__DISABLE_VSGS_AGE_SORT__SHIFT 0xa +#define SPI_DEBUG_CNTL_2__PA_CSB_DEPTH__SHIFT 0xb +#define SPI_DEBUG_CNTL_2__DISABLE_PSUD_SAME_ADDR_OPT__SHIFT 0xf +#define SPI_DEBUG_CNTL_2__SPI_S_WAVE_WR_CTL_BUSY__SHIFT 0x10 +#define SPI_DEBUG_CNTL_2__DISABLE_EARLY_COL_QUEUE_RD__SHIFT 0x11 +#define SPI_DEBUG_CNTL_2__DISABLE_EGM_SAME_ADDR_OPT__SHIFT 0x12 +#define SPI_DEBUG_CNTL_2__SPI_S_WB_WCT_BUSY__SHIFT 0x16 +#define SPI_DEBUG_CNTL_2__DISABLE_CSG_CRAWLER_ACTIVE_FGCG_OPT__SHIFT 0x17 +#define SPI_DEBUG_CNTL_2__DISABLE_CSC_CRAWLER_ACTIVE_FGCG_OPT__SHIFT 0x18 +#define SPI_DEBUG_CNTL_2__ECO_SPARE_0_MASK 0x00000001L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_1_MASK 0x00000002L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_2_MASK 0x00000004L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_3_MASK 0x00000008L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_4_MASK 0x00000010L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_5_MASK 0x00000020L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_6_MASK 0x00000040L +#define SPI_DEBUG_CNTL_2__ECO_SPARE_7_MASK 0x00000080L +#define SPI_DEBUG_CNTL_2__DISABLE_INTRA_PRIM_CONFLICT_MASK 0x00000100L +#define SPI_DEBUG_CNTL_2__DISABLE_PS_AGE_SORT_MASK 0x00000200L +#define SPI_DEBUG_CNTL_2__DISABLE_VSGS_AGE_SORT_MASK 0x00000400L +#define SPI_DEBUG_CNTL_2__PA_CSB_DEPTH_MASK 0x00007800L +#define SPI_DEBUG_CNTL_2__DISABLE_PSUD_SAME_ADDR_OPT_MASK 0x00008000L +#define SPI_DEBUG_CNTL_2__SPI_S_WAVE_WR_CTL_BUSY_MASK 0x00010000L +#define SPI_DEBUG_CNTL_2__DISABLE_EARLY_COL_QUEUE_RD_MASK 0x00020000L +#define SPI_DEBUG_CNTL_2__DISABLE_EGM_SAME_ADDR_OPT_MASK 0x00040000L +#define SPI_DEBUG_CNTL_2__SPI_S_WB_WCT_BUSY_MASK 0x00400000L +#define SPI_DEBUG_CNTL_2__DISABLE_CSG_CRAWLER_ACTIVE_FGCG_OPT_MASK 0x00800000L +#define SPI_DEBUG_CNTL_2__DISABLE_CSC_CRAWLER_ACTIVE_FGCG_OPT_MASK 0x01000000L +//SPI_DEBUG_CNTL_3 +#define SPI_DEBUG_CNTL_3__CSC_PUSH_CREDITS__SHIFT 0x0 +#define SPI_DEBUG_CNTL_3__CSC_POP_CREDITS__SHIFT 0x5 +#define SPI_DEBUG_CNTL_3__CSC_PUSH_CREDITS_MASK 0x0000001FL +#define SPI_DEBUG_CNTL_3__CSC_POP_CREDITS_MASK 0x000003E0L +//SPI_DEBUG_CNTL +#define SPI_DEBUG_CNTL__DEBUG_GFX_PIPE_SEL__SHIFT 0x0 +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1 +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4 +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12 +#define SPI_DEBUG_CNTL__PS_PSTNT_STATE_PIPELINE_ENABLE__SHIFT 0x13 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14 +#define SPI_DEBUG_CNTL__CGTS_VBUS_SP0_OVERRIDE__SHIFT 0x15 +#define SPI_DEBUG_CNTL__CGTS_VBUS_SP1_OVERRIDE__SHIFT 0x16 +#define SPI_DEBUG_CNTL__ENABLE_FIFO_DEBUG_WRITE__SHIFT 0x17 +#define SPI_DEBUG_CNTL__CGTT_LEGACY_MODE__SHIFT 0x18 +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19 +#define SPI_DEBUG_CNTL__DEBUG_PIXEL_PIPE_SEL__SHIFT 0x1c +#define SPI_DEBUG_CNTL__BCI_PIPE_PER_STAGE_CG_OVERRIDE__SHIFT 0x1e +#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f +#define SPI_DEBUG_CNTL__DEBUG_GFX_PIPE_SEL_MASK 0x00000001L +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0x0000000EL +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x000003F0L +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0x0000FC00L +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x00010000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x00020000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x00040000L +#define SPI_DEBUG_CNTL__PS_PSTNT_STATE_PIPELINE_ENABLE_MASK 0x00080000L +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x00100000L +#define SPI_DEBUG_CNTL__CGTS_VBUS_SP0_OVERRIDE_MASK 0x00200000L +#define SPI_DEBUG_CNTL__CGTS_VBUS_SP1_OVERRIDE_MASK 0x00400000L +#define SPI_DEBUG_CNTL__ENABLE_FIFO_DEBUG_WRITE_MASK 0x00800000L +#define SPI_DEBUG_CNTL__CGTT_LEGACY_MODE_MASK 0x01000000L +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0x0E000000L +#define SPI_DEBUG_CNTL__DEBUG_PIXEL_PIPE_SEL_MASK 0x30000000L +#define SPI_DEBUG_CNTL__BCI_PIPE_PER_STAGE_CG_OVERRIDE_MASK 0x40000000L +#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000L +//SPI_DEBUG_READ +#define SPI_DEBUG_READ__DATA__SHIFT 0x0 +#define SPI_DEBUG_READ__DATA_MASK 0xFFFFFFFFL +//SPI_DSM_CNTL +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA__SHIFT 0x0 +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 +#define SPI_DSM_CNTL__SPI_SR_MEM_DSM_IRRITATOR_DATA_MASK 0x00000003L +#define SPI_DSM_CNTL__SPI_SR_MEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L +//SPI_DSM_CNTL2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT__SHIFT 0x0 +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY__SHIFT 0x2 +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY__SHIFT 0x3 +#define SPI_DSM_CNTL2__SPI_SR_MEM_ENABLE_ERROR_INJECT_MASK 0x00000003L +#define SPI_DSM_CNTL2__SPI_SR_MEM_SELECT_INJECT_DELAY_MASK 0x00000004L +#define SPI_DSM_CNTL2__SPI_SR_MEM_INJECT_DELAY_MASK 0x000001F8L +//SPI_EDC_CNT +#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT__SHIFT 0x0 +#define SPI_EDC_CNT__SPI_SR_MEM_SED_COUNT_MASK 0x00000003L +//SPIRA_DEBUG_READ +#define SPIRA_DEBUG_READ__DATA__SHIFT 0x0 +#define SPIRA_DEBUG_READ__DATA_MASK 0xFFFFFFFFL +//SPI_DEBUG_BUSY +#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x0 +#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x1 +#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x2 +#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x3 +#define SPI_DEBUG_BUSY__PS2_BUSY__SHIFT 0x4 +#define SPI_DEBUG_BUSY__PS3_BUSY__SHIFT 0x5 +#define SPI_DEBUG_BUSY__CSG0_BUSY__SHIFT 0x6 +#define SPI_DEBUG_BUSY__CSG1_BUSY__SHIFT 0x7 +#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8 +#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9 +#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa +#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb +#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc +#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd +#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe +#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x12 +#define SPI_DEBUG_BUSY__OFC_LDS_BUSY__SHIFT 0x13 +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x14 +#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x15 +#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x16 +#define SPI_DEBUG_BUSY__RSRC_ALLOC_BUSY__SHIFT 0x17 +#define SPI_DEBUG_BUSY__PWS_BUSY__SHIFT 0x18 +#define SPI_DEBUG_BUSY__SPP_BUSY__SHIFT 0x19 +#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x00000001L +#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x00000002L +#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x00000004L +#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x00000008L +#define SPI_DEBUG_BUSY__PS2_BUSY_MASK 0x00000010L +#define SPI_DEBUG_BUSY__PS3_BUSY_MASK 0x00000020L +#define SPI_DEBUG_BUSY__CSG0_BUSY_MASK 0x00000040L +#define SPI_DEBUG_BUSY__CSG1_BUSY_MASK 0x00000080L +#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x00000100L +#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x00000200L +#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x00000400L +#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x00000800L +#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x00001000L +#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x00002000L +#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x00004000L +#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x00008000L +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x00040000L +#define SPI_DEBUG_BUSY__OFC_LDS_BUSY_MASK 0x00080000L +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x00100000L +#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x00200000L +#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x00400000L +#define SPI_DEBUG_BUSY__RSRC_ALLOC_BUSY_MASK 0x00800000L +#define SPI_DEBUG_BUSY__PWS_BUSY_MASK 0x01000000L +#define SPI_DEBUG_BUSY__SPP_BUSY_MASK 0x02000000L +//SPI_CONFIG_PS_CU_EN +#define SPI_CONFIG_PS_CU_EN__PKR_OFFSET__SHIFT 0x0 +#define SPI_CONFIG_PS_CU_EN__PKR2_OFFSET__SHIFT 0x4 +#define SPI_CONFIG_PS_CU_EN__PKR3_OFFSET__SHIFT 0x8 +#define SPI_CONFIG_PS_CU_EN__PKR_OFFSET_MASK 0x0000000FL +#define SPI_CONFIG_PS_CU_EN__PKR2_OFFSET_MASK 0x000000F0L +#define SPI_CONFIG_PS_CU_EN__PKR3_OFFSET_MASK 0x00000F00L +//SPI_CONFIG_CU_MASK_GFX0 +#define SPI_CONFIG_CU_MASK_GFX0__HS_CU_EN__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_GFX0__GS_CU_EN__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_GFX0__HS_CU_EN_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_GFX0__GS_CU_EN_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_HP3D0 +#define SPI_CONFIG_CU_MASK_HP3D0__HS_CU_EN__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_HP3D0__GS_CU_EN__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_HP3D0__HS_CU_EN_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_HP3D0__GS_CU_EN_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_GFX1 +#define SPI_CONFIG_CU_MASK_GFX1__PS_CU_EN__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_GFX1__CSG_CU_EN__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_GFX1__PS_CU_EN_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_GFX1__CSG_CU_EN_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_HP3D1 +#define SPI_CONFIG_CU_MASK_HP3D1__PS_CU_EN__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_HP3D1__CSG_CU_EN__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_HP3D1__PS_CU_EN_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_HP3D1__CSG_CU_EN_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS0 +#define SPI_CONFIG_CU_MASK_CS0__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS0__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS0__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS0__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS1 +#define SPI_CONFIG_CU_MASK_CS1__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS1__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS1__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS1__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS2 +#define SPI_CONFIG_CU_MASK_CS2__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS2__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS2__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS2__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS3 +#define SPI_CONFIG_CU_MASK_CS3__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS3__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS3__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS3__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS4 +#define SPI_CONFIG_CU_MASK_CS4__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS4__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS4__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS4__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS5 +#define SPI_CONFIG_CU_MASK_CS5__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS5__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS5__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS5__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS6 +#define SPI_CONFIG_CU_MASK_CS6__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS6__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS6__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS6__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_CONFIG_CU_MASK_CS7 +#define SPI_CONFIG_CU_MASK_CS7__CU_EN_SA0__SHIFT 0x0 +#define SPI_CONFIG_CU_MASK_CS7__CU_EN_SA1__SHIFT 0x10 +#define SPI_CONFIG_CU_MASK_CS7__CU_EN_SA0_MASK 0x0000FFFFL +#define SPI_CONFIG_CU_MASK_CS7__CU_EN_SA1_MASK 0xFFFF0000L +//SPI_WF_LIFETIME_CNTL +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 +#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0x0000000FL +#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x00000010L +//SPI_WF_LIFETIME_LIMIT_0 +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_2 +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_3 +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_4 +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_LIMIT_5 +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_0 +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_2 +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_4 +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_6 +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_7 +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_9 +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_11 +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_13 +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_14 +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_15 +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_16 +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_17 +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_18 +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_19 +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_20 +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000L +//SPI_WF_LIFETIME_DEBUG +#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0 +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f +#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000L +//SPI_WF_LIFETIME_STATUS_21 +#define SPI_WF_LIFETIME_STATUS_21__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_21__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_21__MAX_CNT_MASK 0x7FFFFFFFL +#define SPI_WF_LIFETIME_STATUS_21__INT_SENT_MASK 0x80000000L +//SPI_WGP_WORK_PENDING +#define SPI_WGP_WORK_PENDING__SPI_WGP_WORK_PENDING__SHIFT 0x0 +#define SPI_WGP_WORK_PENDING__SA0_WGP8_WORK_PENDING__SHIFT 0x10 +#define SPI_WGP_WORK_PENDING__RESERVED__SHIFT 0x11 +#define SPI_WGP_WORK_PENDING__SPI_WGP_WORK_PENDING_MASK 0x0000FFFFL +#define SPI_WGP_WORK_PENDING__SA0_WGP8_WORK_PENDING_MASK 0x00010000L +#define SPI_WGP_WORK_PENDING__RESERVED_MASK 0xFFFE0000L +//SPI_CREST_MODE +#define SPI_CREST_MODE__ENABLE_CREST__SHIFT 0x0 +#define SPI_CREST_MODE__ENABLE_CREST_MASK 0x00000001L +//SPI_SLAVE_DEBUG_BUSY +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0 +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1 +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2 +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x4 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x5 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x6 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0x7 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER_BUSY__SHIFT 0x8 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WR_WCTL_BUSY__SHIFT 0x9 +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0xa +#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0xb +#define SPI_SLAVE_DEBUG_BUSY__WR_CTL_MUX_BUSY__SHIFT 0xc +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x00000001L +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x00000002L +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x00000004L +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x00000008L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x00000010L +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x00000020L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x00000040L +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x00000080L +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER_BUSY_MASK 0x00000100L +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WR_WCTL_BUSY_MASK 0x00000200L +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x00000400L +#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x00000800L +#define SPI_SLAVE_DEBUG_BUSY__WR_CTL_MUX_BUSY_MASK 0x00001000L +//SPI_LB_CTR_CTRL +#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 +#define SPI_LB_CTR_CTRL__WAVES_SELECT__SHIFT 0x1 +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ__SHIFT 0x3 +#define SPI_LB_CTR_CTRL__RESET_COUNTS__SHIFT 0x4 +#define SPI_LB_CTR_CTRL__LOAD_MASK 0x00000001L +#define SPI_LB_CTR_CTRL__WAVES_SELECT_MASK 0x00000006L +#define SPI_LB_CTR_CTRL__CLEAR_ON_READ_MASK 0x00000008L +#define SPI_LB_CTR_CTRL__RESET_COUNTS_MASK 0x00000010L +//SPI_LB_WGP_MASK +#define SPI_LB_WGP_MASK__WGP_MASK__SHIFT 0x0 +#define SPI_LB_WGP_MASK__WGP_MASK_MASK 0x0000FFFFL +//SPI_LB_DATA_REG +#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 +#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xFFFFFFFFL +//SPI_PG_ENABLE_STATIC_WGP_MASK +#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK__SHIFT 0x0 +#define SPI_PG_ENABLE_STATIC_WGP_MASK__WGP_MASK_MASK 0x0000FFFFL +//SPI_GDS_CREDITS +#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 +#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0x000000FFL +#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0x0000FF00L +//SPI_SX_EXPORT_BUFFER_SIZES +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0x0000FFFFL +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xFFFF0000L +//SPI_SX_SCOREBOARD_BUFFER_SIZES +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0x0000FFFFL +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xFFFF0000L +//SPI_CSQ_WF_ACTIVE_STATUS +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xFFFFFFFFL +//SPI_CSQ_WF_ACTIVE_COUNT_0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_0__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_1 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_1__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_2 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_2__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_3 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_3__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_4 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_4__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_5 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_5__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_6 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_6__EVENTS_MASK 0x07FF0000L +//SPI_CSQ_WF_ACTIVE_COUNT_7 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x000007FFL +#define SPI_CSQ_WF_ACTIVE_COUNT_7__EVENTS_MASK 0x07FF0000L +//SPI_LB_DATA_WAVES +#define SPI_LB_DATA_WAVES__COUNT0__SHIFT 0x0 +#define SPI_LB_DATA_WAVES__COUNT1__SHIFT 0x10 +#define SPI_LB_DATA_WAVES__COUNT0_MASK 0x0000FFFFL +#define SPI_LB_DATA_WAVES__COUNT1_MASK 0xFFFF0000L +//SPI_LB_DATA_PERWGP_WAVE_HSGS +#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS__SHIFT 0x0 +#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS__SHIFT 0x10 +#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_HS_MASK 0x0000FFFFL +#define SPI_LB_DATA_PERWGP_WAVE_HSGS__WGP_USED_GS_MASK 0xFFFF0000L +//SPI_LB_DATA_PERWGP_WAVE_PS +#define SPI_LB_DATA_PERWGP_WAVE_PS__WGP_USED_PS__SHIFT 0x0 +#define SPI_LB_DATA_PERWGP_WAVE_PS__WGP_USED_PS_MASK 0x0000FFFFL +//SPI_LB_DATA_PERWGP_WAVE_CS +#define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE__SHIFT 0x0 +#define SPI_LB_DATA_PERWGP_WAVE_CS__ACTIVE_MASK 0x0000FFFFL +//SPI_WF_ACTIVE_COUNT_GFX +#define SPI_WF_ACTIVE_COUNT_GFX__WF_ALLOCATED__SHIFT 0x0 +#define SPI_WF_ACTIVE_COUNT_GFX__WF_ACTIVE__SHIFT 0x8 +#define SPI_WF_ACTIVE_COUNT_GFX__WF_ALLOCATED_MASK 0x000000FFL +#define SPI_WF_ACTIVE_COUNT_GFX__WF_ACTIVE_MASK 0x00FFFF00L +//SPI_WF_ACTIVE_COUNT_HPG +#define SPI_WF_ACTIVE_COUNT_HPG__WF_ALLOCATED__SHIFT 0x0 +#define SPI_WF_ACTIVE_COUNT_HPG__WF_ACTIVE__SHIFT 0x8 +#define SPI_WF_ACTIVE_COUNT_HPG__WF_ALLOCATED_MASK 0x000000FFL +#define SPI_WF_ACTIVE_COUNT_HPG__WF_ACTIVE_MASK 0x00FFFF00L +//SPIS_DEBUG_READ +#define SPIS_DEBUG_READ__DATA__SHIFT 0x0 +#define SPIS_DEBUG_READ__DATA_MASK 0xFFFFFFFFL +//BCI_DEBUG_READ +#define BCI_DEBUG_READ__DATA__SHIFT 0x0 +#define BCI_DEBUG_READ__DATA_MASK 0x00FFFFFFL +//SPI_P0_TRAP_SCREEN_PSBA_LO +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSBA_HI +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0x000000FFL +//SPI_P0_TRAP_SCREEN_PSMA_LO +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P0_TRAP_SCREEN_PSMA_HI +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0x000000FFL +//SPI_P0_TRAP_SCREEN_GPR_MIN +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x0000003FL +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x000003C0L +//SPI_P1_TRAP_SCREEN_PSBA_LO +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSBA_HI +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0x000000FFL +//SPI_P1_TRAP_SCREEN_PSMA_LO +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_P1_TRAP_SCREEN_PSMA_HI +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0x000000FFL +//SPI_P1_TRAP_SCREEN_GPR_MIN +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x0000003FL +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x000003C0L +//SPI_GFX_CRAWLER_CONFIG +#define SPI_GFX_CRAWLER_CONFIG__PS_DEPTH__SHIFT 0x0 +#define SPI_GFX_CRAWLER_CONFIG__GS_DEPTH__SHIFT 0x5 +#define SPI_GFX_CRAWLER_CONFIG__HS_DEPTH__SHIFT 0xb +#define SPI_GFX_CRAWLER_CONFIG__PS_ALLOC_DEPTH__SHIFT 0x11 +#define SPI_GFX_CRAWLER_CONFIG__PS_LDS_DONE_DEPTH__SHIFT 0x16 +#define SPI_GFX_CRAWLER_CONFIG__PS_LDS_DONE_CNTL__SHIFT 0x19 +#define SPI_GFX_CRAWLER_CONFIG__RA_PSWAVE_CREDITS__SHIFT 0x1a +#define SPI_GFX_CRAWLER_CONFIG__PS_DEPTH_MASK 0x0000001FL +#define SPI_GFX_CRAWLER_CONFIG__GS_DEPTH_MASK 0x000007E0L +#define SPI_GFX_CRAWLER_CONFIG__HS_DEPTH_MASK 0x0001F800L +#define SPI_GFX_CRAWLER_CONFIG__PS_ALLOC_DEPTH_MASK 0x003E0000L +#define SPI_GFX_CRAWLER_CONFIG__PS_LDS_DONE_DEPTH_MASK 0x01C00000L +#define SPI_GFX_CRAWLER_CONFIG__PS_LDS_DONE_CNTL_MASK 0x02000000L +#define SPI_GFX_CRAWLER_CONFIG__RA_PSWAVE_CREDITS_MASK 0x1C000000L +//SPI_CS_CRAWLER_CONFIG +#define SPI_CS_CRAWLER_CONFIG__CSG_DEPTH__SHIFT 0x0 +#define SPI_CS_CRAWLER_CONFIG__CSC_DEPTH__SHIFT 0x6 +#define SPI_CS_CRAWLER_CONFIG__CSG_DEPTH_MASK 0x0000003FL +#define SPI_CS_CRAWLER_CONFIG__CSC_DEPTH_MASK 0x00000FC0L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_tpdec +//TD_CNTL +#define TD_CNTL__DISABLE_MEDIAN_CALC_FOR_CUBECORNER_PHANTOM_TEXELS__SHIFT 0x0 +#define TD_CNTL__PRESERVE_VGPR_ON_UTC_ERROR__SHIFT 0xd +#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 +#define TD_CNTL__FORCE_RT_BVH4_ARBITER_TO_PING_PONG__SHIFT 0x11 +#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 +#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 +#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 +#define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT__SHIFT 0x16 +#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 +#define TD_CNTL__ARBITER_ROUND_ROBIN__SHIFT 0x18 +#define TD_CNTL__ARBITER_OLDEST_PRIORITY__SHIFT 0x19 +#define TD_CNTL__DONE_SCOREBOARD_DEPTH__SHIFT 0x1a +#define TD_CNTL__DISABLE_MEDIAN_CALC_FOR_CUBECORNER_PHANTOM_TEXELS_MASK 0x00000001L +#define TD_CNTL__PRESERVE_VGPR_ON_UTC_ERROR_MASK 0x00002000L +#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x00010000L +#define TD_CNTL__FORCE_RT_BVH4_ARBITER_TO_PING_PONG_MASK 0x00020000L +#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x00080000L +#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x00100000L +#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x00200000L +#define TD_CNTL__DISABLE_ROUND_TO_ZERO_FOR_LARGE_FLOAT_TO_SMALL_FLOAT_MASK 0x00400000L +#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x00800000L +#define TD_CNTL__ARBITER_ROUND_ROBIN_MASK 0x01000000L +#define TD_CNTL__ARBITER_OLDEST_PRIORITY_MASK 0x02000000L +#define TD_CNTL__DONE_SCOREBOARD_DEPTH_MASK 0xFC000000L +//TD_STATUS +#define TD_STATUS__BUSY__SHIFT 0x1f +#define TD_STATUS__BUSY_MASK 0x80000000L +//TD_DEBUG_DATA +#define TD_DEBUG_DATA__DATA__SHIFT 0x0 +#define TD_DEBUG_DATA__DATA_MASK 0xFFFFFFFFL +//TD_POWER_CNTL +#define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT__SHIFT 0x6 +#define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON__SHIFT 0x7 +#define TD_POWER_CNTL__ENABLE_DEBUG_REG__SHIFT 0x8 +#define TD_POWER_CNTL__DISABLE_NOFILTER_FORMATTER_POWER_OPT_MASK 0x00000040L +#define TD_POWER_CNTL__FORCE_NOFILTER_D16_FORMATTERS_ON_MASK 0x00000080L +#define TD_POWER_CNTL__ENABLE_DEBUG_REG_MASK 0x00000100L +//TD_CNTL2 +#define TD_CNTL2__LDS_RETURN_FIFO_CREDIT__SHIFT 0x0 +#define TD_CNTL2__MULTI_CYCLE_16FP__SHIFT 0x3 +#define TD_CNTL2__DISABLE_BLEND_PRT_FOR_LOADS__SHIFT 0x4 +#define TD_CNTL2__LDS_RETURN_FIFO_CREDIT_MASK 0x00000007L +#define TD_CNTL2__MULTI_CYCLE_16FP_MASK 0x00000008L +#define TD_CNTL2__DISABLE_BLEND_PRT_FOR_LOADS_MASK 0x00000010L +//TD_DSM_CNTL +//TD_DSM_CNTL2 +//TD_SCRATCH +#define TD_SCRATCH__SCRATCH__SHIFT 0x0 +#define TD_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL +//TA_CNTL +#define TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE__SHIFT 0x0 +#define TA_CNTL__TA_INPUT_RDATA_PER_BANK_FGCG_OVERRIDE__SHIFT 0x2 +#define TA_CNTL__TA_INPUT_CFIFO_VEC64_OPT_OVERRIDE__SHIFT 0x3 +#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x8 +#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 +#define TA_CNTL__TA_SQ_XNACK_FGCG_DISABLE_MASK 0x00000001L +#define TA_CNTL__TA_INPUT_RDATA_PER_BANK_FGCG_OVERRIDE_MASK 0x00000004L +#define TA_CNTL__TA_INPUT_CFIFO_VEC64_OPT_OVERRIDE_MASK 0x00000008L +#define TA_CNTL__ALIGNER_CREDIT_MASK 0x00001F00L +#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xFFC00000L +//TA_CNTL_AUX +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 +#define TA_CNTL_AUX__DEPTH_AS_PITCH_DIS__SHIFT 0x1 +#define TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM__SHIFT 0x2 +#define TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS__SHIFT 0x3 +#define TA_CNTL_AUX__DERIV_ADJUST_DIS__SHIFT 0x4 +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE__SHIFT 0x5 +#define TA_CNTL_AUX__GATHERH_DST_SEL__SHIFT 0x6 +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE__SHIFT 0x7 +#define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP__SHIFT 0x8 +#define TA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT 0x9 +#define TA_CNTL_AUX__ANISO_HALF_THRESH__SHIFT 0xa +#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS__SHIFT 0xc +#define TA_CNTL_AUX__ANISO_STEP_ORDER__SHIFT 0xd +#define TA_CNTL_AUX__ANISO_STEP__SHIFT 0xe +#define TA_CNTL_AUX__MINMAG_UNNORM__SHIFT 0xf +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 +#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 +#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE__SHIFT 0x17 +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE__SHIFT 0x18 +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a +#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP__SHIFT 0x1c +#define TA_CNTL_AUX__TRUNC_SMALL_NEG__SHIFT 0x1d +#define TA_CNTL_AUX__ARRAY_ROUND_MODE__SHIFT 0x1e +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x00000001L +#define TA_CNTL_AUX__DEPTH_AS_PITCH_DIS_MASK 0x00000002L +#define TA_CNTL_AUX__CORNER_SAMPLES_MIN_DIM_MASK 0x00000004L +#define TA_CNTL_AUX__OVERRIDE_QUAD_MODE_DIS_MASK 0x00000008L +#define TA_CNTL_AUX__DERIV_ADJUST_DIS_MASK 0x00000010L +#define TA_CNTL_AUX__TFAULT_EN_OVERRIDE_MASK 0x00000020L +#define TA_CNTL_AUX__GATHERH_DST_SEL_MASK 0x00000040L +#define TA_CNTL_AUX__DISABLE_GATHER4_BC_SWIZZLE_MASK 0x00000080L +#define TA_CNTL_AUX__ANISO_MAG_STEP_CLAMP_MASK 0x00000100L +#define TA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK 0x00000200L +#define TA_CNTL_AUX__ANISO_HALF_THRESH_MASK 0x00000C00L +#define TA_CNTL_AUX__ANISO_ERROR_FP_VBIAS_MASK 0x00001000L +#define TA_CNTL_AUX__ANISO_STEP_ORDER_MASK 0x00002000L +#define TA_CNTL_AUX__ANISO_STEP_MASK 0x00004000L +#define TA_CNTL_AUX__MINMAG_UNNORM_MASK 0x00008000L +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x00010000L +#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x00020000L +#define TA_CNTL_AUX__ANISO_TAP_MASK 0x00040000L +#define TA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L +#define TA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L +#define TA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLE_C_DFMT_DISABLE_MASK 0x00800000L +#define TA_CNTL_AUX__DETERMINISM_SAMPLER_MSAA_DISABLE_MASK 0x01000000L +#define TA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L +#define TA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L +#define TA_CNTL_AUX__CUBEMAP_SLICE_CLAMP_MASK 0x10000000L +#define TA_CNTL_AUX__TRUNC_SMALL_NEG_MASK 0x20000000L +#define TA_CNTL_AUX__ARRAY_ROUND_MODE_MASK 0xC0000000L +//TA_CNTL2 +#define TA_CNTL2__STORE_COMPONENT_MODE__SHIFT 0x0 +#define TA_CNTL2__MAX_RQ_ID__SHIFT 0x4 +#define TA_CNTL2__ELEMSIZE_HASH_DIS__SHIFT 0x11 +#define TA_CNTL2__TRUNCATE_COORD_MODE__SHIFT 0x12 +#define TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS__SHIFT 0x13 +#define TA_CNTL2__PRTPLUS_ACCUM_MODE__SHIFT 0x14 +#define TA_CNTL2__STORE_COMPONENT_MODE_MASK 0x00000001L +#define TA_CNTL2__MAX_RQ_ID_MASK 0x00000070L +#define TA_CNTL2__ELEMSIZE_HASH_DIS_MASK 0x00020000L +#define TA_CNTL2__TRUNCATE_COORD_MODE_MASK 0x00040000L +#define TA_CNTL2__ELIMINATE_UNLIT_QUAD_DIS_MASK 0x00080000L +#define TA_CNTL2__PRTPLUS_ACCUM_MODE_MASK 0x00300000L +//TA_STATUS +#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc +#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd +#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe +#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 +#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 +#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 +#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 +#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 +#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 +#define TA_STATUS__IN_BUSY__SHIFT 0x18 +#define TA_STATUS__FG_BUSY__SHIFT 0x19 +#define TA_STATUS__LA_BUSY__SHIFT 0x1a +#define TA_STATUS__FL_BUSY__SHIFT 0x1b +#define TA_STATUS__TA_BUSY__SHIFT 0x1c +#define TA_STATUS__FA_BUSY__SHIFT 0x1d +#define TA_STATUS__AL_BUSY__SHIFT 0x1e +#define TA_STATUS__BUSY__SHIFT 0x1f +#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x00001000L +#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x00002000L +#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x00004000L +#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x00010000L +#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x00020000L +#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x00040000L +#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x00100000L +#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x00200000L +#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x00400000L +#define TA_STATUS__IN_BUSY_MASK 0x01000000L +#define TA_STATUS__FG_BUSY_MASK 0x02000000L +#define TA_STATUS__LA_BUSY_MASK 0x04000000L +#define TA_STATUS__FL_BUSY_MASK 0x08000000L +#define TA_STATUS__TA_BUSY_MASK 0x10000000L +#define TA_STATUS__FA_BUSY_MASK 0x20000000L +#define TA_STATUS__AL_BUSY_MASK 0x40000000L +#define TA_STATUS__BUSY_MASK 0x80000000L +//TA_SCRATCH +#define TA_SCRATCH__SCRATCH__SHIFT 0x0 +#define TA_SCRATCH__SCRATCH_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_rbdec +//DB_DEBUG +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 +#define DB_DEBUG__ENABLE_COMPRESSION_ON_BYPASS__SHIFT 0x2 +#define DB_DEBUG__DISABLE_TILE_RATE_1XAA__SHIFT 0x3 +#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d +#define DB_DEBUG__RESERVED_FIELD_1__SHIFT 0x1e +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x00000001L +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x00000002L +#define DB_DEBUG__ENABLE_COMPRESSION_ON_BYPASS_MASK 0x00000004L +#define DB_DEBUG__DISABLE_TILE_RATE_1XAA_MASK 0x00000008L +#define DB_DEBUG__FORCE_Z_MODE_MASK 0x00000030L +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x00000040L +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x00000080L +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x00000300L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0x00000C00L +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x00003000L +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x00004000L +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x00008000L +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x00010000L +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x00040000L +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x00180000L +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x00400000L +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00800000L +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0x0F000000L +#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000L +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000L +#define DB_DEBUG__RESERVED_FIELD_1_MASK 0xC0000000L +//DB_DEBUG2 +#define DB_DEBUG2__TRAP_ENABLE__SHIFT 0x1 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL__SHIFT 0x5 +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ__SHIFT 0x6 +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL__SHIFT 0x7 +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE__SHIFT 0x8 +#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 +#define DB_DEBUG2__FORCE_PERF_COUNTERS_ON__SHIFT 0xe +#define DB_DEBUG2__FL_FLUSH_ONE_STILE_AT_A_TIME__SHIFT 0x10 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 +#define DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x14 +#define DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES__SHIFT 0x15 +#define DB_DEBUG2__FL_DISABLE_PLANE_REPACK__SHIFT 0x1a +#define DB_DEBUG2__DEBUG_BUS_FLOP_EN__SHIFT 0x1b +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f +#define DB_DEBUG2__TRAP_ENABLE_MASK 0x00000002L +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x00000008L +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x00000010L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_MASK 0x00000020L +#define DB_DEBUG2__DISABLE_PREZL_FIFO_STALL_REZ_MASK 0x00000040L +#define DB_DEBUG2__ENABLE_VIEWPORT_STALL_ON_ALL_MASK 0x00000080L +#define DB_DEBUG2__OPTIMIZE_HIZ_MATCHES_FB_DISABLE_MASK 0x00000100L +#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x00003E00L +#define DB_DEBUG2__FORCE_PERF_COUNTERS_ON_MASK 0x00004000L +#define DB_DEBUG2__FL_FLUSH_ONE_STILE_AT_A_TIME_MASK 0x00010000L +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x00020000L +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x00040000L +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x00080000L +#define DB_DEBUG2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00100000L +#define DB_DEBUG2__ENABLE_FULL_TILE_WAVE_BREAK_FOR_ALL_TILES_MASK 0x00200000L +#define DB_DEBUG2__FL_DISABLE_PLANE_REPACK_MASK 0x04000000L +#define DB_DEBUG2__DEBUG_BUS_FLOP_EN_MASK 0x08000000L +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000L +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000L +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000L +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000L +//DB_DEBUG3 +#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA__SHIFT 0x1 +#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf +#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH__SHIFT 0x10 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b +#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT__SHIFT 0x1f +#define DB_DEBUG3__DISABLE_RELOAD_CONTEXT_DRAW_DATA_MASK 0x00000002L +#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x00000004L +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x00000008L +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00000010L +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x00000100L +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x00000400L +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x00002000L +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x00004000L +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x00008000L +#define DB_DEBUG3__DISABLE_SLOCS_PER_CTXT_MATCH_MASK 0x00010000L +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x00020000L +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x00200000L +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x00800000L +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x04000000L +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x08000000L +#define DB_DEBUG3__DISABLE_MULTIDTAG_FL_PANIC_REQUIREMENT_MASK 0x80000000L +//DB_DEBUG4 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 +#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK__SHIFT 0x4 +#define DB_DEBUG4__DISABLE_SEPARATE_SX_CLK__SHIFT 0x5 +#define DB_DEBUG4__DISABLE_1PLANE_PMASK_OPTIMIZATION__SHIFT 0x7 +#define DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK__SHIFT 0x8 +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0xc +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP__SHIFT 0xd +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE__SHIFT 0xf +#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT__SHIFT 0x10 +#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT__SHIFT 0x1e +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x00000001L +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x00000002L +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x00000004L +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x00000008L +#define DB_DEBUG4__DISABLE_SEPARATE_OP_PIPE_CLK_MASK 0x00000010L +#define DB_DEBUG4__DISABLE_SEPARATE_SX_CLK_MASK 0x00000020L +#define DB_DEBUG4__DISABLE_1PLANE_PMASK_OPTIMIZATION_MASK 0x00000080L +#define DB_DEBUG4__DISABLE_SEPARATE_DBG_CLK_MASK 0x00000100L +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x00001000L +#define DB_DEBUG4__DISABLE_DTT_FAST_HTILENACK_LOOKUP_MASK 0x00002000L +#define DB_DEBUG4__DISABLE_DYNAMIC_RAM_LIGHT_SLEEP_MODE_MASK 0x00008000L +#define DB_DEBUG4__DISABLE_HIZ_TS_COLLISION_DETECT_MASK 0x00010000L +#define DB_DEBUG4__LATE_ACK_SCOREBOARD_MULTIPLE_SLOT_MASK 0x40000000L +//DB_CREDIT_LIMIT +#define DB_CREDIT_LIMIT__DB_SC_UPDATE_CREDITS__SHIFT 0x0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 +#define DB_CREDIT_LIMIT__DB_CB_EXPORT_CREDITS__SHIFT 0xa +#define DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS__SHIFT 0xd +#define DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS__SHIFT 0x12 +#define DB_CREDIT_LIMIT__DB_SC_UPDATE_CREDITS_MASK 0x0000001FL +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x000003E0L +#define DB_CREDIT_LIMIT__DB_CB_EXPORT_CREDITS_MASK 0x00001C00L +#define DB_CREDIT_LIMIT__DB_SC_WAVE_CREDITS_MASK 0x0003E000L +#define DB_CREDIT_LIMIT__DB_SC_FREE_WAVE_CREDITS_MASK 0x007C0000L +//DB_WATERMARKS +#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 +#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x8 +#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0x10 +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x18 +#define DB_WATERMARKS__DEPTH_FREE_MASK 0x000000FFL +#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x0000FF00L +#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0x00FF0000L +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0xFF000000L +//DB_FREE_CACHELINES +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x8 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0x10 +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x000000FFL +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x0000FF00L +#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x00FF0000L +//DB_FIFO_DEPTH1 +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x18 +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0xFF000000L +//DB_FIFO_DEPTH2 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x01FF0000L +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xFE000000L +//DB_RING_CONTROL +#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 +#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x00000003L +//DB_MEM_ARB_WATERMARKS +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK__SHIFT 0x0 +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK__SHIFT 0x8 +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK__SHIFT 0x10 +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK__SHIFT 0x18 +#define DB_MEM_ARB_WATERMARKS__CLIENT0_WATERMARK_MASK 0x00000007L +#define DB_MEM_ARB_WATERMARKS__CLIENT1_WATERMARK_MASK 0x00000700L +#define DB_MEM_ARB_WATERMARKS__CLIENT2_WATERMARK_MASK 0x00070000L +#define DB_MEM_ARB_WATERMARKS__CLIENT3_WATERMARK_MASK 0x07000000L +//DB_FIFO_DEPTH3 +#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH3__QUAD_READ_REQS__SHIFT 0x18 +#define DB_FIFO_DEPTH3__LTILE_PROBE_FIFO_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH3__OSB_WAVE_TABLE_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH3__OREO_WAVE_HIDE_DEPTH_MASK 0x00FF0000L +#define DB_FIFO_DEPTH3__QUAD_READ_REQS_MASK 0xFF000000L +//DB_DEBUG6 +#define DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT__SHIFT 0x0 +#define DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT__SHIFT 0x1 +#define DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT__SHIFT 0x2 +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ALL__SHIFT 0x3 +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ID__SHIFT 0x4 +#define DB_DEBUG6__OREO_TRANSITION_EVENT_EN__SHIFT 0xa +#define DB_DEBUG6__NEVER_DB_SC_WAVE_CONFLICT__SHIFT 0xb +#define DB_DEBUG6__DISABLE_PWS_PLUS_STC_TAG_LIVENESS_STALL__SHIFT 0xc +#define DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID__SHIFT 0xd +#define DB_DEBUG6__NEVER_DB_SC_WAVE_HARD_CONFLICT__SHIFT 0xf +#define DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL__SHIFT 0x10 +#define DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT__SHIFT 0x18 +#define DB_DEBUG6__FORCE_MAX_STILES_IN_WAVE_CHECK__SHIFT 0x19 +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX__SHIFT 0x1a +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC__SHIFT 0x1b +#define DB_DEBUG6__FORCE_ZC_WRITEMASK_TO_FULL__SHIFT 0x1c +#define DB_DEBUG6__SPARE_BITS_31_28__SHIFT 0x1d +#define DB_DEBUG6__FORCE_DB_SC_WAVE_CONFLICT_MASK 0x00000001L +#define DB_DEBUG6__FORCE_DB_SC_WAVE_HARD_CONFLICT_MASK 0x00000002L +#define DB_DEBUG6__FORCE_DB_SC_QUAD_CONFLICT_MASK 0x00000004L +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ALL_MASK 0x00000008L +#define DB_DEBUG6__OREO_TRANSITION_EVENT_ID_MASK 0x000003F0L +#define DB_DEBUG6__OREO_TRANSITION_EVENT_EN_MASK 0x00000400L +#define DB_DEBUG6__NEVER_DB_SC_WAVE_CONFLICT_MASK 0x00000800L +#define DB_DEBUG6__DISABLE_PWS_PLUS_STC_TAG_LIVENESS_STALL_MASK 0x00001000L +#define DB_DEBUG6__SET_DB_PERFMON_PWS_PIPE_ID_MASK 0x00006000L +#define DB_DEBUG6__NEVER_DB_SC_WAVE_HARD_CONFLICT_MASK 0x00008000L +#define DB_DEBUG6__FTWB_MAX_TIMEOUT_VAL_MASK 0x00FF0000L +#define DB_DEBUG6__DISABLE_LQO_SMT_RAM_OPT_MASK 0x01000000L +#define DB_DEBUG6__FORCE_MAX_STILES_IN_WAVE_CHECK_MASK 0x02000000L +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_FIX_MASK 0x04000000L +#define DB_DEBUG6__DISABLE_OSB_DEADLOCK_WAIT_PANIC_MASK 0x08000000L +#define DB_DEBUG6__FORCE_ZC_WRITEMASK_TO_FULL_MASK 0x10000000L +#define DB_DEBUG6__SPARE_BITS_31_28_MASK 0xE0000000L +//DB_EXCEPTION_CONTROL +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE__SHIFT 0x0 +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE__SHIFT 0x1 +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE__SHIFT 0x2 +#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD__SHIFT 0x4 +#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE__SHIFT 0x8 +#define DB_EXCEPTION_CONTROL__CAM_FREE_WATERMARK__SHIFT 0x18 +#define DB_EXCEPTION_CONTROL__EARLY_Z_PANIC_DISABLE_MASK 0x00000001L +#define DB_EXCEPTION_CONTROL__LATE_Z_PANIC_DISABLE_MASK 0x00000002L +#define DB_EXCEPTION_CONTROL__RE_Z_PANIC_DISABLE_MASK 0x00000004L +#define DB_EXCEPTION_CONTROL__AUTO_FLUSH_QUAD_MASK 0x00000010L +#define DB_EXCEPTION_CONTROL__FORCE_SUMMARIZE_MASK 0x00000F00L +#define DB_EXCEPTION_CONTROL__CAM_FREE_WATERMARK_MASK 0xFF000000L +//DB_DEBUG7 +#define DB_DEBUG7__SPARE_BITS__SHIFT 0x0 +#define DB_DEBUG7__SPARE_BITS_MASK 0xFFFFFFFFL +//DB_DEBUG5 +#define DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT__SHIFT 0x3 +#define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK__SHIFT 0x4 +#define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS__SHIFT 0x5 +#define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT__SHIFT 0x7 +#define DB_DEBUG5__DISABLE_VRS_1X2_2XAA__SHIFT 0x8 +#define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE__SHIFT 0x9 +#define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX__SHIFT 0xd +#define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED__SHIFT 0xe +#define DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK__SHIFT 0xf +#define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ__SHIFT 0x10 +#define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE__SHIFT 0x11 +#define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT__SHIFT 0x12 +#define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT__SHIFT 0x13 +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z__SHIFT 0x14 +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL__SHIFT 0x15 +#define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK__SHIFT 0x16 +#define DB_DEBUG5__SPARE_BITS__SHIFT 0x18 +#define DB_DEBUG5__DISABLE_2SRC_VRS_HARD_CONFLICT_MASK 0x00000008L +#define DB_DEBUG5__DISABLE_FLQ_MCC_DTILEID_CHECK_MASK 0x00000010L +#define DB_DEBUG5__DISABLE_NOZ_POWER_SAVINGS_MASK 0x00000020L +#define DB_DEBUG5__DISABLE_MGCG_GATING_ON_SHADER_WAIT_MASK 0x00000080L +#define DB_DEBUG5__DISABLE_VRS_1X2_2XAA_MASK 0x00000100L +#define DB_DEBUG5__ENABLE_FULL_TILE_WAVE_BREAK_ON_COARSE_MASK 0x00000200L +#define DB_DEBUG5__DISABLE_PSL_AUTO_MODE_FIX_MASK 0x00002000L +#define DB_DEBUG5__DISABLE_FORCE_ZMASK_EXPANDED_MASK 0x00004000L +#define DB_DEBUG5__DISABLE_SEPARATE_LQO_CLK_MASK 0x00008000L +#define DB_DEBUG5__DISABLE_Z_WITHOUT_PLANES_FLQ_MASK 0x00010000L +#define DB_DEBUG5__PRESERVE_QMASK_FOR_POSTZ_OP_PIPE_MASK 0x00020000L +#define DB_DEBUG5__Z_NACK_BEHAVIOR_ONLY_WHEN_Z_IS_PRT_MASK 0x00040000L +#define DB_DEBUG5__S_NACK_BEHAVIOR_ONLY_WHEN_S_IS_PRT_MASK 0x00080000L +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_Z_MASK 0x00100000L +#define DB_DEBUG5__DISABLE_RESIDENCY_CHECK_STENCIL_MASK 0x00200000L +#define DB_DEBUG5__DISABLE_LQO_FTCQ_DUAL_QUAD_REGION_CHECK_MASK 0x00400000L +#define DB_DEBUG5__SPARE_BITS_MASK 0xFF000000L +//DB_MEM_CONFIG +#define DB_MEM_CONFIG__Z_SCOPE__SHIFT 0x0 +#define DB_MEM_CONFIG__STENCIL_SCOPE__SHIFT 0x2 +#define DB_MEM_CONFIG__OCCLUSION_SCOPE__SHIFT 0x4 +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_Z__SHIFT 0x6 +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_STENCIL__SHIFT 0x7 +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_OCCLUSION__SHIFT 0x8 +#define DB_MEM_CONFIG__Z_OVERRIDE_COMPRESSION_MODE__SHIFT 0x9 +#define DB_MEM_CONFIG__STENCIL_OVERRIDE_COMPRESSION_MODE__SHIFT 0xb +#define DB_MEM_CONFIG__OCCLUSION_OVERRIDE_COMPRESSION_MODE__SHIFT 0xd +#define DB_MEM_CONFIG__FL_DISABLE_SINGLE_COMPRESS__SHIFT 0xf +#define DB_MEM_CONFIG__Z_SCOPE_MASK 0x00000003L +#define DB_MEM_CONFIG__STENCIL_SCOPE_MASK 0x0000000CL +#define DB_MEM_CONFIG__OCCLUSION_SCOPE_MASK 0x00000030L +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_Z_MASK 0x00000040L +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_STENCIL_MASK 0x00000080L +#define DB_MEM_CONFIG__ENABLE_OVERRIDE_COMP_MODE_OCCLUSION_MASK 0x00000100L +#define DB_MEM_CONFIG__Z_OVERRIDE_COMPRESSION_MODE_MASK 0x00000600L +#define DB_MEM_CONFIG__STENCIL_OVERRIDE_COMPRESSION_MODE_MASK 0x00001800L +#define DB_MEM_CONFIG__OCCLUSION_OVERRIDE_COMPRESSION_MODE_MASK 0x00006000L +#define DB_MEM_CONFIG__FL_DISABLE_SINGLE_COMPRESS_MASK 0x00008000L +//DB_ARB_CONFIG +#define DB_ARB_CONFIG__ARB_MODE__SHIFT 0x0 +#define DB_ARB_CONFIG__CREDITS_MAX_RD__SHIFT 0x2 +#define DB_ARB_CONFIG__CREDITS_WEIGHT_RD__SHIFT 0x7 +#define DB_ARB_CONFIG__CREDITS_MAX_WR__SHIFT 0xc +#define DB_ARB_CONFIG__CREDITS_WEIGHT_WR__SHIFT 0x11 +#define DB_ARB_CONFIG__ARB_MODE_MASK 0x00000003L +#define DB_ARB_CONFIG__CREDITS_MAX_RD_MASK 0x0000007CL +#define DB_ARB_CONFIG__CREDITS_WEIGHT_RD_MASK 0x00000F80L +#define DB_ARB_CONFIG__CREDITS_MAX_WR_MASK 0x0001F000L +#define DB_ARB_CONFIG__CREDITS_WEIGHT_WR_MASK 0x003E0000L +//DB_DFD_INDIRECT_SEL +#define DB_DFD_INDIRECT_SEL__DFD_INDEX__SHIFT 0x0 +#define DB_DFD_INDIRECT_SEL__DFD_INDEX_MASK 0x000000FFL +//DB_DFD_INDIRECT_DAT +#define DB_DFD_INDIRECT_DAT__DFD_DATA__SHIFT 0x0 +#define DB_DFD_INDIRECT_DAT__DFD_DATA_MASK 0xFFFFFFFFL +//DB_SUMMARIZER_TIMEOUTS +#define DB_SUMMARIZER_TIMEOUTS__SUMM_CNTL_EVICT_TIMEOUT__SHIFT 0x0 +#define DB_SUMMARIZER_TIMEOUTS__SUMM_EVICT_TIMEOUT__SHIFT 0x10 +#define DB_SUMMARIZER_TIMEOUTS__SUMM_CNTL_EVICT_TIMEOUT_MASK 0x00000FFFL +#define DB_SUMMARIZER_TIMEOUTS__SUMM_EVICT_TIMEOUT_MASK 0x0FFF0000L +//DB_FGCG_SRAMS_CLK_CTRL +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0__SHIFT 0x0 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1__SHIFT 0x1 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2__SHIFT 0x2 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3__SHIFT 0x3 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4__SHIFT 0x4 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5__SHIFT 0x5 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6__SHIFT 0x6 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7__SHIFT 0x7 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8__SHIFT 0x8 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9__SHIFT 0x9 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10__SHIFT 0xa +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11__SHIFT 0xb +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12__SHIFT 0xc +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13__SHIFT 0xd +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14__SHIFT 0xe +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15__SHIFT 0xf +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16__SHIFT 0x10 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17__SHIFT 0x11 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18__SHIFT 0x12 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19__SHIFT 0x13 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20__SHIFT 0x14 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22__SHIFT 0x16 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23__SHIFT 0x17 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24__SHIFT 0x18 +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26__SHIFT 0x1a +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27__SHIFT 0x1b +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28__SHIFT 0x1c +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29__SHIFT 0x1d +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30__SHIFT 0x1e +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31__SHIFT 0x1f +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE0_MASK 0x00000001L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE1_MASK 0x00000002L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE2_MASK 0x00000004L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE3_MASK 0x00000008L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE4_MASK 0x00000010L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE5_MASK 0x00000020L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE6_MASK 0x00000040L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE7_MASK 0x00000080L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE8_MASK 0x00000100L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE9_MASK 0x00000200L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE10_MASK 0x00000400L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE11_MASK 0x00000800L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE12_MASK 0x00001000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE13_MASK 0x00002000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE14_MASK 0x00004000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE15_MASK 0x00008000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE16_MASK 0x00010000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE17_MASK 0x00020000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE18_MASK 0x00040000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE19_MASK 0x00080000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE20_MASK 0x00100000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE22_MASK 0x00400000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE23_MASK 0x00800000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE24_MASK 0x01000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE26_MASK 0x04000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE27_MASK 0x08000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE28_MASK 0x10000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE29_MASK 0x20000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE30_MASK 0x40000000L +#define DB_FGCG_SRAMS_CLK_CTRL__OVERRIDE31_MASK 0x80000000L +//DB_FGCG_INTERFACES_CLK_CTRL +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE__SHIFT 0x0 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE__SHIFT 0x2 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_GL1_COMP_REQ_OVERRIDE__SHIFT 0x3 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_GL1_SRC_OVERRIDE__SHIFT 0x4 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_UPDATE_OVERRIDE__SHIFT 0x5 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE__SHIFT 0x6 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE__SHIFT 0x7 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE__SHIFT 0x8 +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_QUAD_OVERRIDE_MASK 0x00000001L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_EXPORT_OVERRIDE_MASK 0x00000004L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_GL1_COMP_REQ_OVERRIDE_MASK 0x00000008L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_GL1_SRC_OVERRIDE_MASK 0x00000010L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_UPDATE_OVERRIDE_MASK 0x00000020L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_CB_RMIRET_OVERRIDE_MASK 0x00000040L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_WAVE_OVERRIDE_MASK 0x00000080L +#define DB_FGCG_INTERFACES_CLK_CTRL__DB_SC_FREE_WAVE_OVERRIDE_MASK 0x00000100L +//DB_FIFO_DEPTH4 +#define DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH__SHIFT 0x18 +#define DB_FIFO_DEPTH4__OSB_SQUAD_TABLE_DEPTH_MASK 0x000000FFL +#define DB_FIFO_DEPTH4__OSB_TILE_TABLE_DEPTH_MASK 0x0000FF00L +#define DB_FIFO_DEPTH4__OSB_SCORE_BOARD_DEPTH_MASK 0x00FF0000L +#define DB_FIFO_DEPTH4__OSB_EVENT_FIFO_DEPTH_MASK 0xFF000000L +//CC_RB_BACKEND_DISABLE +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x4 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x000000F0L +//GB_ADDR_CONFIG_1 +#define GB_ADDR_CONFIG_1__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG_1__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG_1__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG_1__NUM_PKRS__SHIFT 0x8 +#define GB_ADDR_CONFIG_1__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG_1__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG_1__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG_1__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG_1__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG_1__NUM_PKRS_MASK 0x00000700L +#define GB_ADDR_CONFIG_1__NUM_SHADER_ENGINES_MASK 0x00780000L +#define GB_ADDR_CONFIG_1__NUM_RB_PER_SE_MASK 0x0C000000L +//GB_BACKEND_MAP +#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 +#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xFFFFFFFFL +//GB_GPU_ID +#define GB_GPU_ID__GPU_ID__SHIFT 0x0 +#define GB_GPU_ID__GPU_ID_MASK 0x0000000FL +//GB_ADDR_CONFIG_READ +#define GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS__SHIFT 0x6 +#define GB_ADDR_CONFIG_READ__NUM_PKRS__SHIFT 0x8 +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE__SHIFT 0x1a +#define GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L +#define GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L +#define GB_ADDR_CONFIG_READ__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L +#define GB_ADDR_CONFIG_READ__NUM_PKRS_MASK 0x00000700L +#define GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00780000L +#define GB_ADDR_CONFIG_READ__NUM_RB_PER_SE_MASK 0x0C000000L +//CB_HW_CONTROL_4 +#define CB_HW_CONTROL_4__ENABLE_READ_RESIDENCY_TIMEOUT_CNTR__SHIFT 0x0 +#define CB_HW_CONTROL_4__THRESHOLD_READ_RESIDENCY_TIMEOUT_CNTR__SHIFT 0x1 +#define CB_HW_CONTROL_4__DISABLE_FRAGOP_MULTI_FRAGMENT__SHIFT 0xe +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD__SHIFT 0x10 +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD__SHIFT 0x11 +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD__SHIFT 0x12 +#define CB_HW_CONTROL_4__ENABLE_READ_RESIDENCY_TIMEOUT_CNTR_MASK 0x00000001L +#define CB_HW_CONTROL_4__THRESHOLD_READ_RESIDENCY_TIMEOUT_CNTR_MASK 0x00000006L +#define CB_HW_CONTROL_4__DISABLE_FRAGOP_MULTI_FRAGMENT_MASK 0x00004000L +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_RAW_HAZARD_MASK 0x00010000L +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_COARSE_RAW_HAZARD_MASK 0x00020000L +#define CB_HW_CONTROL_4__ENABLE_FRAGOP_STALLING_ON_DS_RAW_HAZARD_MASK 0x00040000L +//CB_HW_CONTROL_3 +#define CB_HW_CONTROL_3__FORCE_GLX_REQ_CLKEN_HIGH__SHIFT 0x3 +#define CB_HW_CONTROL_3__FORCE_GLX_SRC_CLKEN_HIGH__SHIFT 0x4 +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x6 +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0x7 +#define CB_HW_CONTROL_3__DISABLE_FMASK_OPT_WA_AND_FULLY_COVERED__SHIFT 0x15 +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_OVERRIDE_ROH_COMP__SHIFT 0x19 +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_INSERT_BUBBLES_B2B__SHIFT 0x1a +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_CLEAR_KEY_OVERRIDE_FROM_ILLEGAL_DECODE__SHIFT 0x1b +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_WAIT_SECOND_64B__SHIFT 0x1c +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_256B_CLEARS_BECOME_1FRAG__SHIFT 0x1d +#define CB_HW_CONTROL_3__FORCE_GLX_REQ_CLKEN_HIGH_MASK 0x00000008L +#define CB_HW_CONTROL_3__FORCE_GLX_SRC_CLKEN_HIGH_MASK 0x00000010L +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x00000040L +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x00000080L +#define CB_HW_CONTROL_3__DISABLE_FMASK_OPT_WA_AND_FULLY_COVERED_MASK 0x00200000L +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_OVERRIDE_ROH_COMP_MASK 0x02000000L +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_INSERT_BUBBLES_B2B_MASK 0x04000000L +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_CLEAR_KEY_OVERRIDE_FROM_ILLEGAL_DECODE_MASK 0x08000000L +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_WAIT_SECOND_64B_MASK 0x10000000L +#define CB_HW_CONTROL_3__DISABLE_READ_DAW_OPT_256B_CLEARS_BECOME_1FRAG_MASK 0x20000000L +//CB_HW_CONTROL +#define CB_HW_CONTROL__DISABLE_GRBM_BUSY_CNTR__SHIFT 0x0 +#define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION__SHIFT 0x1 +#define CB_HW_CONTROL__GLX_CREDITS__SHIFT 0x6 +#define CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES__SHIFT 0xc +#define CB_HW_CONTROL__DISABLE_EVICT_ILLEGAL_KEY_OVERRIDE__SHIFT 0xf +#define CB_HW_CONTROL__FORCE_EVICT_ALL_VALID__SHIFT 0x10 +#define CB_HW_CONTROL__FORCE_WAIT_EOP_DONE_FLUSH__SHIFT 0x12 +#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 +#define CB_HW_CONTROL__DISABLE_USE_OF_SET_HASH__SHIFT 0x14 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 +#define CB_HW_CONTROL__ENABLE_SINGLE_KEY_WR_OPT__SHIFT 0x16 +#define CB_HW_CONTROL__DISABLE_POWER_OPT_HC__SHIFT 0x17 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b +#define CB_HW_CONTROL__DISABLE_MULTICYCLE_WRITES__SHIFT 0x1c +#define CB_HW_CONTROL__DISABLE_HOLE_COLLAPSE__SHIFT 0x1d +#define CB_HW_CONTROL__DISABLE_FMASK_REREAD_OPT__SHIFT 0x1e +#define CB_HW_CONTROL__EN_KEY_OVERRIDE__SHIFT 0x1f +#define CB_HW_CONTROL__DISABLE_GRBM_BUSY_CNTR_MASK 0x00000001L +#define CB_HW_CONTROL__DISABLE_VRS_FILLRATE_OPTIMIZATION_MASK 0x00000002L +#define CB_HW_CONTROL__GLX_CREDITS_MASK 0x000003C0L +#define CB_HW_CONTROL__NUM_CCC_SKID_FIFO_ENTRIES_MASK 0x00007000L +#define CB_HW_CONTROL__DISABLE_EVICT_ILLEGAL_KEY_OVERRIDE_MASK 0x00008000L +#define CB_HW_CONTROL__FORCE_EVICT_ALL_VALID_MASK 0x00010000L +#define CB_HW_CONTROL__FORCE_WAIT_EOP_DONE_FLUSH_MASK 0x00040000L +#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x00080000L +#define CB_HW_CONTROL__DISABLE_USE_OF_SET_HASH_MASK 0x00100000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x00200000L +#define CB_HW_CONTROL__ENABLE_SINGLE_KEY_WR_OPT_MASK 0x00400000L +#define CB_HW_CONTROL__DISABLE_POWER_OPT_HC_MASK 0x00800000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x01000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x02000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x04000000L +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x08000000L +#define CB_HW_CONTROL__DISABLE_MULTICYCLE_WRITES_MASK 0x10000000L +#define CB_HW_CONTROL__DISABLE_HOLE_COLLAPSE_MASK 0x20000000L +#define CB_HW_CONTROL__DISABLE_FMASK_REREAD_OPT_MASK 0x40000000L +#define CB_HW_CONTROL__EN_KEY_OVERRIDE_MASK 0x80000000L +//CB_HW_CONTROL_1 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0x0 +#define CB_HW_CONTROL_1__DISABLE_SRC_FIFO_BYP__SHIFT 0x15 +#define CB_HW_CONTROL_1__DISABLE_RDLAT_FIFO_BYP__SHIFT 0x16 +#define CB_HW_CONTROL_1__ENABLE_COMPRESSION_ON_BYPASS__SHIFT 0x17 +#define CB_HW_CONTROL_1__COLOR_SCOPE__SHIFT 0x18 +#define CB_HW_CONTROL_1__GLX_NOFILL__SHIFT 0x1a +#define CB_HW_CONTROL_1__GLX_VQID__SHIFT 0x1b +#define CB_HW_CONTROL_1__GLX_PERF_CNTR_EN__SHIFT 0x1f +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x0000003FL +#define CB_HW_CONTROL_1__DISABLE_SRC_FIFO_BYP_MASK 0x00200000L +#define CB_HW_CONTROL_1__DISABLE_RDLAT_FIFO_BYP_MASK 0x00400000L +#define CB_HW_CONTROL_1__ENABLE_COMPRESSION_ON_BYPASS_MASK 0x00800000L +#define CB_HW_CONTROL_1__COLOR_SCOPE_MASK 0x03000000L +#define CB_HW_CONTROL_1__GLX_NOFILL_MASK 0x04000000L +#define CB_HW_CONTROL_1__GLX_VQID_MASK 0x78000000L +#define CB_HW_CONTROL_1__GLX_PERF_CNTR_EN_MASK 0x80000000L +//CB_HW_CONTROL_2 +#define CB_HW_CONTROL_2__RESERVED__SHIFT 0x0 +#define CB_HW_CONTROL_2__RESERVED_MASK 0x00000001L +//CB_HW_MEM_ARBITER_CTL +#define CB_HW_MEM_ARBITER_CTL__ARB_MODE__SHIFT 0x0 +#define CB_HW_MEM_ARBITER_CTL__READ_CYC_WEIGHT__SHIFT 0x1 +#define CB_HW_MEM_ARBITER_CTL__READ_CRED_CNT_MAX__SHIFT 0x7 +#define CB_HW_MEM_ARBITER_CTL__WRITE_CYC_WEIGHT__SHIFT 0xd +#define CB_HW_MEM_ARBITER_CTL__WRITE_CRED_CNT_MAX__SHIFT 0x13 +#define CB_HW_MEM_ARBITER_CTL__WRITE_CREDIT_MODE__SHIFT 0x1b +#define CB_HW_MEM_ARBITER_CTL__READ_CREDIT_MODE__SHIFT 0x1c +#define CB_HW_MEM_ARBITER_CTL__ARB_MODE_MASK 0x00000001L +#define CB_HW_MEM_ARBITER_CTL__READ_CYC_WEIGHT_MASK 0x0000003EL +#define CB_HW_MEM_ARBITER_CTL__READ_CRED_CNT_MAX_MASK 0x00000F80L +#define CB_HW_MEM_ARBITER_CTL__WRITE_CYC_WEIGHT_MASK 0x0003E000L +#define CB_HW_MEM_ARBITER_CTL__WRITE_CRED_CNT_MAX_MASK 0x00F80000L +#define CB_HW_MEM_ARBITER_CTL__WRITE_CREDIT_MODE_MASK 0x08000000L +#define CB_HW_MEM_ARBITER_CTL__READ_CREDIT_MODE_MASK 0x10000000L +//CB_FGCG_SRAM_OVERRIDE +#define CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG__SHIFT 0x0 +#define CB_FGCG_SRAM_OVERRIDE__DISABLE_FGCG_MASK 0x000007FFL +//CB_CACHE_EVICT_POINTS +#define CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT__SHIFT 0x0 +#define CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT__SHIFT 0x8 +#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT__SHIFT 0x18 +#define CB_CACHE_EVICT_POINTS__CC_COLOR_EVICT_POINT_MASK 0x000000FFL +#define CB_CACHE_EVICT_POINTS__CC_FMASK_EVICT_POINT_MASK 0x0000FF00L +#define CB_CACHE_EVICT_POINTS__CC_CACHE_EVICT_POINT_MASK 0xFF000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_spipdec2 +//SPI_PQEV_CTRL +#define SPI_PQEV_CTRL__SCAN_PERIOD__SHIFT 0x0 +#define SPI_PQEV_CTRL__QUEUE_DURATION__SHIFT 0xa +#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN__SHIFT 0x10 +#define SPI_PQEV_CTRL__SCAN_PERIOD_MASK 0x000003FFL +#define SPI_PQEV_CTRL__QUEUE_DURATION_MASK 0x0000FC00L +#define SPI_PQEV_CTRL__COMPUTE_PIPE_EN_MASK 0x00FF0000L +//SPI_EXP_THROTTLE_CTRL +#define SPI_EXP_THROTTLE_CTRL__ENABLE__SHIFT 0x0 +#define SPI_EXP_THROTTLE_CTRL__PERIOD__SHIFT 0x1 +#define SPI_EXP_THROTTLE_CTRL__UPSTEP__SHIFT 0x5 +#define SPI_EXP_THROTTLE_CTRL__DOWNSTEP__SHIFT 0x9 +#define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT__SHIFT 0xd +#define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT__SHIFT 0x10 +#define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD__SHIFT 0x13 +#define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT__SHIFT 0x1a +#define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET__SHIFT 0x1d +#define SPI_EXP_THROTTLE_CTRL__ENABLE_MASK 0x00000001L +#define SPI_EXP_THROTTLE_CTRL__PERIOD_MASK 0x0000001EL +#define SPI_EXP_THROTTLE_CTRL__UPSTEP_MASK 0x000001E0L +#define SPI_EXP_THROTTLE_CTRL__DOWNSTEP_MASK 0x00001E00L +#define SPI_EXP_THROTTLE_CTRL__LOW_STALL_MON_HIST_COUNT_MASK 0x0000E000L +#define SPI_EXP_THROTTLE_CTRL__HIGH_STALL_MON_HIST_COUNT_MASK 0x00070000L +#define SPI_EXP_THROTTLE_CTRL__EXP_STALL_THRESHOLD_MASK 0x03F80000L +#define SPI_EXP_THROTTLE_CTRL__SKEW_COUNT_MASK 0x1C000000L +#define SPI_EXP_THROTTLE_CTRL__THROTTLE_RESET_MASK 0x20000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_rmi_gfx_se_rmidec +//RMI_GENERAL_CNTL +#define RMI_GENERAL_CNTL__BURST_DISABLE__SHIFT 0x0 +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE__SHIFT 0x1 +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN__SHIFT 0x13 +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE__SHIFT 0x15 +#define RMI_GENERAL_CNTL__BURST_DISABLE_MASK 0x00000001L +#define RMI_GENERAL_CNTL__VMID_BYPASS_ENABLE_MASK 0x0001FFFEL +#define RMI_GENERAL_CNTL__RB0_HARVEST_EN_MASK 0x00080000L +#define RMI_GENERAL_CNTL__LOOPBACK_DIS_BY_REQ_TYPE_MASK 0x01E00000L +//RMI_GENERAL_CNTL1 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE__SHIFT 0x0 +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE__SHIFT 0x4 +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE__SHIFT 0x6 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK__SHIFT 0x8 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE__SHIFT 0x9 +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE__SHIFT 0xb +#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE__SHIFT 0xe +#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE__SHIFT 0xf +#define RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS__SHIFT 0x10 +#define RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS__SHIFT 0x16 +#define RMI_GENERAL_CNTL1__EARLY_WRACK_ENABLE_PER_MTYPE_MASK 0x0000000FL +#define RMI_GENERAL_CNTL1__TCIW0_64B_RD_STALL_MODE_MASK 0x00000030L +#define RMI_GENERAL_CNTL1__TCIW1_64B_RD_STALL_MODE_MASK 0x000000C0L +#define RMI_GENERAL_CNTL1__EARLY_WRACK_DISABLE_FOR_LOOPBACK_MASK 0x00000100L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_VALUE_MASK 0x00000600L +#define RMI_GENERAL_CNTL1__POLICY_OVERRIDE_MASK 0x00000800L +#define RMI_GENERAL_CNTL1__ARBITER_ADDRESS_CHANGE_ENABLE_MASK 0x00004000L +#define RMI_GENERAL_CNTL1__LAST_OF_BURST_INSERTION_DISABLE_MASK 0x00008000L +#define RMI_GENERAL_CNTL1__TCIW0_PRODUCER_CREDITS_MASK 0x003F0000L +#define RMI_GENERAL_CNTL1__TCIW1_PRODUCER_CREDITS_MASK 0x0FC00000L +//RMI_GENERAL_STATUS +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED__SHIFT 0x0 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR__SHIFT 0x1 +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR__SHIFT 0x2 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR__SHIFT 0x3 +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR__SHIFT 0x4 +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY__SHIFT 0x5 +#define RMI_GENERAL_STATUS__RESERVED_BIT_6__SHIFT 0x6 +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY__SHIFT 0x7 +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY__SHIFT 0x8 +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY__SHIFT 0x9 +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY__SHIFT 0xa +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xb +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY__SHIFT 0xc +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY__SHIFT 0xd +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY__SHIFT 0xe +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY__SHIFT 0xf +#define RMI_GENERAL_STATUS__RESERVED_BIT_18__SHIFT 0x12 +#define RMI_GENERAL_STATUS__RESERVED_BIT_19__SHIFT 0x13 +#define RMI_GENERAL_STATUS__RESERVED_BIT_20__SHIFT 0x14 +#define RMI_GENERAL_STATUS__RESERVED_BITS_28_21__SHIFT 0x15 +#define RMI_GENERAL_STATUS__RESERVED_BIT_29__SHIFT 0x1d +#define RMI_GENERAL_STATUS__RESERVED_BIT_30__SHIFT 0x1e +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR__SHIFT 0x1f +#define RMI_GENERAL_STATUS__GENERAL_RMI_ERRORS_COMBINED_MASK 0x00000001L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_OVERFLOW_ERROR_MASK 0x00000002L +#define RMI_GENERAL_STATUS__SKID_FIFO_0_UNDERFLOW_ERROR_MASK 0x00000004L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_OVERFLOW_ERROR_MASK 0x00000008L +#define RMI_GENERAL_STATUS__SKID_FIFO_1_UNDERFLOW_ERROR_MASK 0x00000010L +#define RMI_GENERAL_STATUS__RMI_XBAR_BUSY_MASK 0x00000020L +#define RMI_GENERAL_STATUS__RESERVED_BIT_6_MASK 0x00000040L +#define RMI_GENERAL_STATUS__RMI_SCOREBOARD_BUSY_MASK 0x00000080L +#define RMI_GENERAL_STATUS__TCIW0_PRT_FIFO_BUSY_MASK 0x00000100L +#define RMI_GENERAL_STATUS__TCIW_FRMTR0_BUSY_MASK 0x00000200L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR0_BUSY_MASK 0x00000400L +#define RMI_GENERAL_STATUS__WRREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00000800L +#define RMI_GENERAL_STATUS__RDREQ_CONSUMER_FIFO_0_BUSY_MASK 0x00001000L +#define RMI_GENERAL_STATUS__TCIW1_PRT_FIFO_BUSY_MASK 0x00002000L +#define RMI_GENERAL_STATUS__TCIW_FRMTR1_BUSY_MASK 0x00004000L +#define RMI_GENERAL_STATUS__TCIW_RTN_FRMTR1_BUSY_MASK 0x00008000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_18_MASK 0x00040000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_19_MASK 0x00080000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_20_MASK 0x00100000L +#define RMI_GENERAL_STATUS__RESERVED_BITS_28_21_MASK 0x1FE00000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_29_MASK 0x20000000L +#define RMI_GENERAL_STATUS__RESERVED_BIT_30_MASK 0x40000000L +#define RMI_GENERAL_STATUS__SKID_FIFO_FREESPACE_IS_ZERO_ERROR_MASK 0x80000000L +//RMI_SUBBLOCK_STATUS0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0__SHIFT 0x7 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0__SHIFT 0x8 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1__SHIFT 0x10 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1__SHIFT 0x11 +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT__SHIFT 0x12 +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE0_MASK 0x0000007FL +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE0_MASK 0x00000080L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE0_MASK 0x00000100L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_NUM_USED_PROBE1_MASK 0x0000FE00L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_FULL_PROBE1_MASK 0x00010000L +#define RMI_SUBBLOCK_STATUS0__UTC_EXT_LAT_HID_FIFO_EMPTY_PROBE1_MASK 0x00020000L +#define RMI_SUBBLOCK_STATUS0__TCIW0_INFLIGHT_CNT_MASK 0x0FFC0000L +//RMI_SUBBLOCK_STATUS1 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT__SHIFT 0x14 +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_0_FREE_SPACE_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS1__SKID_FIFO_1_FREE_SPACE_MASK 0x000FFC00L +#define RMI_SUBBLOCK_STATUS1__TCIW1_INFLIGHT_CNT_MASK 0x3FF00000L +//RMI_SUBBLOCK_STATUS2 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED__SHIFT 0x9 +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_0_NUM_USED_MASK 0x000001FFL +#define RMI_SUBBLOCK_STATUS2__PRT_FIFO_1_NUM_USED_MASK 0x0003FE00L +//RMI_SUBBLOCK_STATUS3 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL__SHIFT 0x0 +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL__SHIFT 0xa +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_0_FREE_SPACE_TOTAL_MASK 0x000003FFL +#define RMI_SUBBLOCK_STATUS3__SKID_FIFO_1_FREE_SPACE_TOTAL_MASK 0x000FFC00L +//RMI_XBAR_CONFIG +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE__SHIFT 0x0 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE__SHIFT 0x2 +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_CONFIG__ARBITER_DIS__SHIFT 0x7 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ__SHIFT 0x8 +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE__SHIFT 0xc +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0__SHIFT 0xd +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_OVERRIDE_MASK 0x00000003L +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_REQ_TYPE_OVERRIDE_MASK 0x0000003CL +#define RMI_XBAR_CONFIG__XBAR_MUX_CONFIG_CB_DB_OVERRIDE_MASK 0x00000040L +#define RMI_XBAR_CONFIG__ARBITER_DIS_MASK 0x00000080L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_MASK 0x00000F00L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_REQ_OVERRIDE_MASK 0x00001000L +#define RMI_XBAR_CONFIG__XBAR_EN_IN_RB0_MASK 0x00002000L +//RMI_PROBE_POP_LOGIC_CNTL +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH__SHIFT 0x0 +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS__SHIFT 0x7 +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2__SHIFT 0x8 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH__SHIFT 0xa +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS__SHIFT 0x11 +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_0_MAX_DEPTH_MASK 0x0000007FL +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE0_DIS_MASK 0x00000080L +#define RMI_PROBE_POP_LOGIC_CNTL__REDUCE_MAX_XLAT_CHAIN_SIZE_BY_2_MASK 0x00000300L +#define RMI_PROBE_POP_LOGIC_CNTL__EXT_LAT_FIFO_1_MAX_DEPTH_MASK 0x0001FC00L +#define RMI_PROBE_POP_LOGIC_CNTL__XLAT_COMBINE1_DIS_MASK 0x00020000L +//RMI_UTC_XNACK_N_MISC_CNTL +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC__SHIFT 0x0 +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE__SHIFT 0xc +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE__SHIFT 0xd +#define RMI_UTC_XNACK_N_MISC_CNTL__MASTER_XNACK_TIMER_INC_MASK 0x000000FFL +#define RMI_UTC_XNACK_N_MISC_CNTL__IND_XNACK_TIMER_START_VALUE_MASK 0x00000F00L +#define RMI_UTC_XNACK_N_MISC_CNTL__UTCL1_PERM_MODE_MASK 0x00001000L +#define RMI_UTC_XNACK_N_MISC_CNTL__CP_VMID_RESET_REQUEST_DISABLE_MASK 0x00002000L +//RMI_DEMUX_CNTL +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN__SHIFT 0x2 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x6 +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE__SHIFT 0xe +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN__SHIFT 0x12 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x16 +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE__SHIFT 0x1e +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_OVERRIDE_EN_MASK 0x00000004L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_STALL_TIMER_START_VALUE_MASK 0x00003FC0L +#define RMI_DEMUX_CNTL__DEMUX_ARB0_MODE_MASK 0x0000C000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_OVERRIDE_EN_MASK 0x00040000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_STALL_TIMER_START_VALUE_MASK 0x3FC00000L +#define RMI_DEMUX_CNTL__DEMUX_ARB1_MODE_MASK 0xC0000000L +//RMI_UTCL1_CNTL1 +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define RMI_UTCL1_CNTL1__RESP_MODE__SHIFT 0x3 +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define RMI_UTCL1_CNTL1__CLIENTID__SHIFT 0x7 +#define RMI_UTCL1_CNTL1__USERVM_DIS__SHIFT 0x10 +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO__SHIFT 0x11 +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB__SHIFT 0x12 +#define RMI_UTCL1_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID__SHIFT 0x17 +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define RMI_UTCL1_CNTL1__FORCE_MISS__SHIFT 0x1a +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define RMI_UTCL1_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define RMI_UTCL1_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define RMI_UTCL1_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define RMI_UTCL1_CNTL1__RESP_MODE_MASK 0x00000018L +#define RMI_UTCL1_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define RMI_UTCL1_CNTL1__CLIENTID_MASK 0x0000FF80L +#define RMI_UTCL1_CNTL1__USERVM_DIS_MASK 0x00010000L +#define RMI_UTCL1_CNTL1__ENABLE_PUSH_LFIFO_MASK 0x00020000L +#define RMI_UTCL1_CNTL1__ENABLE_LFIFO_PRI_ARB_MASK 0x00040000L +#define RMI_UTCL1_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define RMI_UTCL1_CNTL1__REG_INV_ALL_VMID_MASK 0x00800000L +#define RMI_UTCL1_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define RMI_UTCL1_CNTL1__CLIENT_INVALIDATE_ALL_VMID_MASK 0x02000000L +#define RMI_UTCL1_CNTL1__FORCE_MISS_MASK 0x04000000L +#define RMI_UTCL1_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define RMI_UTCL1_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define RMI_UTCL1_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//RMI_UTCL1_CNTL2 +#define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 0x0 +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define RMI_UTCL1_CNTL2__LINE_VALID__SHIFT 0xa +#define RMI_UTCL1_CNTL2__DIS_EDC__SHIFT 0xb +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE__SHIFT 0xc +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT__SHIFT 0xd +#define RMI_UTCL1_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK__SHIFT 0xf +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE__SHIFT 0x10 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR__SHIFT 0x13 +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID__SHIFT 0x15 +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ__SHIFT 0x19 +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD__SHIFT 0x1b +#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT__SHIFT 0x1c +#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT__SHIFT 0x1d +#define RMI_UTCL1_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define RMI_UTCL1_CNTL2__RESERVED__SHIFT 0x1f +#define RMI_UTCL1_CNTL2__UTC_SPARE_MASK 0x000000FFL +#define RMI_UTCL1_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define RMI_UTCL1_CNTL2__LINE_VALID_MASK 0x00000400L +#define RMI_UTCL1_CNTL2__DIS_EDC_MASK 0x00000800L +#define RMI_UTCL1_CNTL2__GPUVM_INV_MODE_MASK 0x00001000L +#define RMI_UTCL1_CNTL2__SHOOTDOWN_OPT_MASK 0x00002000L +#define RMI_UTCL1_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define RMI_UTCL1_CNTL2__FORCE_GPUVM_INV_ACK_MASK 0x00008000L +#define RMI_UTCL1_CNTL2__UTCL1_ARB_BURST_MODE_MASK 0x00030000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_RD_WR_MASK 0x00080000L +#define RMI_UTCL1_CNTL2__UTCL1_ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define RMI_UTCL1_CNTL2__UTCL1_PERF_EVENT_VMID_MASK 0x01E00000L +#define RMI_UTCL1_CNTL2__UTCL1_DIS_DUAL_L2_REQ_MASK 0x02000000L +#define RMI_UTCL1_CNTL2__UTCL1_FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define RMI_UTCL1_CNTL2__PERM_MODE_OVRD_MASK 0x08000000L +#define RMI_UTCL1_CNTL2__LINE_INVALIDATE_OPT_MASK 0x10000000L +#define RMI_UTCL1_CNTL2__GPUVM_16K_DEFAULT_MASK 0x20000000L +#define RMI_UTCL1_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define RMI_UTCL1_CNTL2__RESERVED_MASK 0x80000000L +//RMI_UTC_UNIT_CONFIG +#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN__SHIFT 0x0 +#define RMI_UTC_UNIT_CONFIG__TMZ_REQ_EN_MASK 0x0000FFFFL +//RMI_TCIW_FORMATTER0_CNTL +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER0_CNTL__TCIW0_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER0_CNTL__RMI_IN0_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER0_CNTL__ALL_FAULT_RET0_DATA_MASK 0x80000000L +//RMI_TCIW_FORMATTER1_CNTL +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE__SHIFT 0x0 +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW__SHIFT 0x1 +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ__SHIFT 0x9 +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS__SHIFT 0x1d +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST__SHIFT 0x1e +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA__SHIFT 0x1f +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_OVERRIDE_MASK 0x00000001L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_TIME_OUT_WINDOW_MASK 0x000001FEL +#define RMI_TCIW_FORMATTER1_CNTL__TCIW1_MAX_ALLOWED_INFLIGHT_REQ_MASK 0x0007FE00L +#define RMI_TCIW_FORMATTER1_CNTL__RMI_IN1_REORDER_DIS_MASK 0x20000000L +#define RMI_TCIW_FORMATTER1_CNTL__WR_COMBINE1_DIS_AT_LAST_OF_BURST_MASK 0x40000000L +#define RMI_TCIW_FORMATTER1_CNTL__ALL_FAULT_RET1_DATA_MASK 0x80000000L +//RMI_SCOREBOARD_CNTL +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH__SHIFT 0x0 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0__SHIFT 0x1 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH__SHIFT 0x2 +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1__SHIFT 0x3 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN__SHIFT 0x5 +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE__SHIFT 0x6 +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE__SHIFT 0x9 +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB0_FLUSH_MASK 0x00000001L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB0_MASK 0x00000002L +#define RMI_SCOREBOARD_CNTL__COMPLETE_RB1_FLUSH_MASK 0x00000004L +#define RMI_SCOREBOARD_CNTL__REQ_IN_RE_EN_AFTER_FLUSH_RB1_MASK 0x00000008L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_EN_MASK 0x00000020L +#define RMI_SCOREBOARD_CNTL__VMID_INVAL_FLUSH_TYPE_OVERRIDE_VALUE_MASK 0x00000040L +#define RMI_SCOREBOARD_CNTL__FORCE_VMID_INVAL_DONE_TIMER_START_VALUE_MASK 0x001FFE00L +//RMI_SCOREBOARD_STATUS0 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG__SHIFT 0x1 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID__SHIFT 0x2 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE__SHIFT 0x12 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE__SHIFT 0x13 +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE__SHIFT 0x14 +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE__SHIFT 0x15 +#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT__SHIFT 0x16 +#define RMI_SCOREBOARD_STATUS0__CURRENT_SESSION_ID_MASK 0x00000001L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_IN_PROG_MASK 0x00000002L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_REQ_VMID_MASK 0x0003FFFCL +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_UTC_DONE_MASK 0x00040000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_DONE_MASK 0x00080000L +#define RMI_SCOREBOARD_STATUS0__CP_VMID_INV_FLUSH_TYPE_MASK 0x00100000L +#define RMI_SCOREBOARD_STATUS0__FORCE_VMID_INV_DONE_MASK 0x00200000L +#define RMI_SCOREBOARD_STATUS0__COUNTER_SELECT_MASK 0x07C00000L +//RMI_SCOREBOARD_STATUS1 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED__SHIFT 0xe +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1__SHIFT 0xf +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB0_MASK 0x00002000L +#define RMI_SCOREBOARD_STATUS1__MULTI_VMID_INVAL_FROM_CP_DETECTED_MASK 0x00004000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_RB1_MASK 0x07FF8000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_UNDERFLOW_RB1_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS1__RUNNING_CNT_OVERFLOW_RB1_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS1__COM_FLUSH_IN_PROG_RB0_MASK 0x40000000L +//RMI_SCOREBOARD_STATUS2 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0__SHIFT 0x0 +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0__SHIFT 0xc +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1__SHIFT 0xd +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1__SHIFT 0x19 +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1__SHIFT 0x1a +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0__SHIFT 0x1b +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0__SHIFT 0x1c +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1__SHIFT 0x1d +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0__SHIFT 0x1e +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1__SHIFT 0x1f +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB0_MASK 0x00000FFFL +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB0_MASK 0x00001000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_RB1_MASK 0x01FFE000L +#define RMI_SCOREBOARD_STATUS2__SNAPSHOT_CNT_UNDERFLOW_RB1_MASK 0x02000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB1_MASK 0x04000000L +#define RMI_SCOREBOARD_STATUS2__COM_FLUSH_DONE_RB0_MASK 0x08000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB0_MASK 0x10000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_IN_PROG_RB1_MASK 0x20000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB0_MASK 0x40000000L +#define RMI_SCOREBOARD_STATUS2__TIME_STAMP_FLUSH_DONE_RB1_MASK 0x80000000L +//RMI_XBAR_ARBITER_CONFIG +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x2 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL__SHIFT 0x3 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN__SHIFT 0x4 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN__SHIFT 0x5 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE__SHIFT 0x6 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE__SHIFT 0x10 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR__SHIFT 0x12 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL__SHIFT 0x13 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN__SHIFT 0x14 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN__SHIFT 0x15 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE__SHIFT 0x16 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE__SHIFT 0x18 +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_MASK 0x00000003L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00000004L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_MASK 0x00000008L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_BREAK_LOB_ON_IDLEIN_MASK 0x00000010L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_MODE_OVERRIDE_EN_MASK 0x00000020L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_OVERRIDE_MASK 0x000000C0L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB0_STALL_TIMER_START_VALUE_MASK 0x0000FF00L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_MASK 0x00030000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_WEIGHTEDRR_MASK 0x00040000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_MASK 0x00080000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_BREAK_LOB_ON_IDLEIN_MASK 0x00100000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_MODE_OVERRIDE_EN_MASK 0x00200000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_OVERRIDE_MASK 0x00C00000L +#define RMI_XBAR_ARBITER_CONFIG__XBAR_ARB1_STALL_TIMER_START_VALUE_MASK 0xFF000000L +//RMI_XBAR_ARBITER_CONFIG_1 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD__SHIFT 0x0 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR__SHIFT 0x8 +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_RD_MASK 0x000000FFL +#define RMI_XBAR_ARBITER_CONFIG_1__XBAR_ARB_ROUND_ROBIN_WEIGHT_RB0_WR_MASK 0x0000FF00L +//RMI_CLOCK_CNTRL +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK__SHIFT 0x0 +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK__SHIFT 0x5 +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK__SHIFT 0xa +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK__SHIFT 0xf +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_BUSY_MASK_MASK 0x0000001FL +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_BUSY_MASK_MASK 0x000003E0L +#define RMI_CLOCK_CNTRL__DYN_CLK_RB0_WAKEUP_MASK_MASK 0x00007C00L +#define RMI_CLOCK_CNTRL__DYN_CLK_CMN_WAKEUP_MASK_MASK 0x000F8000L +//RMI_UTCL1_STATUS +#define RMI_UTCL1_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define RMI_UTCL1_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define RMI_UTCL1_STATUS__PRT_DETECTED__SHIFT 0x2 +#define RMI_UTCL1_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define RMI_UTCL1_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define RMI_UTCL1_STATUS__PRT_DETECTED_MASK 0x00000004L +//RMI_RB_GLX_CID_MAP +#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP__SHIFT 0x0 +#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP__SHIFT 0x4 +#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP__SHIFT 0x8 +#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP__SHIFT 0xc +#define RMI_RB_GLX_CID_MAP__DB_Z_MAP__SHIFT 0x10 +#define RMI_RB_GLX_CID_MAP__DB_S_MAP__SHIFT 0x14 +#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP__SHIFT 0x18 +#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP__SHIFT 0x1c +#define RMI_RB_GLX_CID_MAP__CB_COLOR_MAP_MASK 0x0000000FL +#define RMI_RB_GLX_CID_MAP__CB_FMASK_MAP_MASK 0x000000F0L +#define RMI_RB_GLX_CID_MAP__CB_CMASK_MAP_MASK 0x00000F00L +#define RMI_RB_GLX_CID_MAP__CB_DCC_MAP_MASK 0x0000F000L +#define RMI_RB_GLX_CID_MAP__DB_Z_MAP_MASK 0x000F0000L +#define RMI_RB_GLX_CID_MAP__DB_S_MAP_MASK 0x00F00000L +#define RMI_RB_GLX_CID_MAP__DB_TILE_MAP_MASK 0x0F000000L +#define RMI_RB_GLX_CID_MAP__DB_ZPCPSD_MAP_MASK 0xF0000000L +//RMI_XNACK_DEBUG +#define RMI_XNACK_DEBUG__XNACK_PER_VMID__SHIFT 0x0 +#define RMI_XNACK_DEBUG__XNACK_PER_VMID_MASK 0x0000FFFFL +//RMI_SPARE +#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE__SHIFT 0x1 +#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE__SHIFT 0x2 +#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE__SHIFT 0x3 +#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS__SHIFT 0x4 +#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS__SHIFT 0x5 +#define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE__SHIFT 0x6 +#define RMI_SPARE__SPARE_BIT_7__SHIFT 0x7 +#define RMI_SPARE__NOFILL_RMI_CID_CC__SHIFT 0x8 +#define RMI_SPARE__NOFILL_RMI_CID_FC__SHIFT 0x9 +#define RMI_SPARE__NOFILL_RMI_CID_CM__SHIFT 0xa +#define RMI_SPARE__NOFILL_RMI_CID_DC__SHIFT 0xb +#define RMI_SPARE__NOFILL_RMI_CID_Z__SHIFT 0xc +#define RMI_SPARE__NOFILL_RMI_CID_S__SHIFT 0xd +#define RMI_SPARE__NOFILL_RMI_CID_TILE__SHIFT 0xe +#define RMI_SPARE__SPARE_BIT_15_0__SHIFT 0xf +#define RMI_SPARE__ARBITER_ADDRESS_MASK__SHIFT 0x10 +#define RMI_SPARE__RMI_2_GL1_128B_READ_DISABLE_MASK 0x00000002L +#define RMI_SPARE__RMI_2_GL1_REPEATER_FGCG_DISABLE_MASK 0x00000004L +#define RMI_SPARE__RMI_2_RB_REPEATER_FGCG_DISABLE_MASK 0x00000008L +#define RMI_SPARE__EARLY_WRITE_ACK_ENABLE_C_RW_NOA_RESOLVE_DIS_MASK 0x00000010L +#define RMI_SPARE__RMI_REORDER_BYPASS_CHANNEL_DIS_MASK 0x00000020L +#define RMI_SPARE__XNACK_RETURN_DATA_OVERRIDE_MASK 0x00000040L +#define RMI_SPARE__SPARE_BIT_7_MASK 0x00000080L +#define RMI_SPARE__NOFILL_RMI_CID_CC_MASK 0x00000100L +#define RMI_SPARE__NOFILL_RMI_CID_FC_MASK 0x00000200L +#define RMI_SPARE__NOFILL_RMI_CID_CM_MASK 0x00000400L +#define RMI_SPARE__NOFILL_RMI_CID_DC_MASK 0x00000800L +#define RMI_SPARE__NOFILL_RMI_CID_Z_MASK 0x00001000L +#define RMI_SPARE__NOFILL_RMI_CID_S_MASK 0x00002000L +#define RMI_SPARE__NOFILL_RMI_CID_TILE_MASK 0x00004000L +#define RMI_SPARE__SPARE_BIT_15_0_MASK 0x00008000L +#define RMI_SPARE__ARBITER_ADDRESS_MASK_MASK 0xFFFF0000L +//RMI_SPARE_1 +#define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE__SHIFT 0x0 +#define RMI_SPARE_1__SPARE_BIT_9__SHIFT 0x1 +#define RMI_SPARE_1__SPARE_BIT_10__SHIFT 0x2 +#define RMI_SPARE_1__SPARE_BIT_11__SHIFT 0x3 +#define RMI_SPARE_1__SPARE_BIT_12__SHIFT 0x4 +#define RMI_SPARE_1__SPARE_BIT_13__SHIFT 0x5 +#define RMI_SPARE_1__SPARE_BIT_14__SHIFT 0x6 +#define RMI_SPARE_1__SPARE_BIT_15__SHIFT 0x7 +#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID__SHIFT 0x8 +#define RMI_SPARE_1__SPARE_BIT_16_1__SHIFT 0x10 +#define RMI_SPARE_1__EARLY_WRACK_FIFO_DISABLE_MASK 0x00000001L +#define RMI_SPARE_1__SPARE_BIT_9_MASK 0x00000002L +#define RMI_SPARE_1__SPARE_BIT_10_MASK 0x00000004L +#define RMI_SPARE_1__SPARE_BIT_11_MASK 0x00000008L +#define RMI_SPARE_1__SPARE_BIT_12_MASK 0x00000010L +#define RMI_SPARE_1__SPARE_BIT_13_MASK 0x00000020L +#define RMI_SPARE_1__SPARE_BIT_14_MASK 0x00000040L +#define RMI_SPARE_1__SPARE_BIT_15_MASK 0x00000080L +#define RMI_SPARE_1__RMI_REORDER_DIS_BY_CID_MASK 0x0000FF00L +#define RMI_SPARE_1__SPARE_BIT_16_1_MASK 0xFFFF0000L +//RMI_SPARE_2 +#define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID__SHIFT 0x0 +#define RMI_SPARE_2__SPARE_BIT_8_2__SHIFT 0x10 +#define RMI_SPARE_2__SPARE_BIT_8_3__SHIFT 0x18 +#define RMI_SPARE_2__ERROR_ZERO_BYTE_MASK_CID_MASK 0x0000FFFFL +#define RMI_SPARE_2__SPARE_BIT_8_2_MASK 0x00FF0000L +#define RMI_SPARE_2__SPARE_BIT_8_3_MASK 0xFF000000L +//CC_RMI_REDUNDANCY +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 +#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 +#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L +#define CC_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L +#define CC_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L +#define CC_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_utcl1dec +//UTCL1_CTRL_1 +#define UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS__SHIFT 0x0 +#define UTCL1_CTRL_1__UTCL1_TCP_BYPASS__SHIFT 0x1 +#define UTCL1_CTRL_1__UTCL1_SQCI_BYPASS__SHIFT 0x2 +#define UTCL1_CTRL_1__UTCL1_SQCD_BYPASS__SHIFT 0x3 +#define UTCL1_CTRL_1__UTCL1_RMI_BYPASS__SHIFT 0x4 +#define UTCL1_CTRL_1__UTCL1_SQG_BYPASS__SHIFT 0x5 +#define UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID__SHIFT 0x6 +#define UTCL1_CTRL_1__RESERVED_0__SHIFT 0x7 +#define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE__SHIFT 0x8 +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1__SHIFT 0x9 +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2__SHIFT 0xb +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3__SHIFT 0xd +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4__SHIFT 0xf +#define UTCL1_CTRL_1__RESERVED_1__SHIFT 0x11 +#define UTCL1_CTRL_1__UTCL1_CACHE_CORE_BYPASS_MASK 0x00000001L +#define UTCL1_CTRL_1__UTCL1_TCP_BYPASS_MASK 0x00000002L +#define UTCL1_CTRL_1__UTCL1_SQCI_BYPASS_MASK 0x00000004L +#define UTCL1_CTRL_1__UTCL1_SQCD_BYPASS_MASK 0x00000008L +#define UTCL1_CTRL_1__UTCL1_RMI_BYPASS_MASK 0x00000010L +#define UTCL1_CTRL_1__UTCL1_SQG_BYPASS_MASK 0x00000020L +#define UTCL1_CTRL_1__UTCL1_FORCE_RANGE_INV_TO_VMID_MASK 0x00000040L +#define UTCL1_CTRL_1__RESERVED_0_MASK 0x00000080L +#define UTCL1_CTRL_1__UTCL1_FORCE_INV_ALL_DONE_MASK 0x00000100L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_1_MASK 0x00000600L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_2_MASK 0x00001800L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_3_MASK 0x00006000L +#define UTCL1_CTRL_1__UTCL1_PAGE_SIZE_4_MASK 0x00018000L +#define UTCL1_CTRL_1__RESERVED_1_MASK 0xFFFE0000L +//UTCL1_HASH_CTRL +#define UTCL1_HASH_CTRL__UTCL1_BANK_SELECT_BASE__SHIFT 0x0 +#define UTCL1_HASH_CTRL__UTCL1_BANK_MASK0__SHIFT 0x5 +#define UTCL1_HASH_CTRL__UTCL1_BANK_MASK1__SHIFT 0x9 +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK0__SHIFT 0xd +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK1__SHIFT 0x11 +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK2__SHIFT 0x15 +#define UTCL1_HASH_CTRL__UTCL1_XOR_ONLY_HIGHER_WAYS__SHIFT 0x19 +#define UTCL1_HASH_CTRL__UTCL1_WAY_SELECT_OFFSET__SHIFT 0x1a +#define UTCL1_HASH_CTRL__RESERVED__SHIFT 0x1f +#define UTCL1_HASH_CTRL__UTCL1_BANK_SELECT_BASE_MASK 0x0000001FL +#define UTCL1_HASH_CTRL__UTCL1_BANK_MASK0_MASK 0x000001E0L +#define UTCL1_HASH_CTRL__UTCL1_BANK_MASK1_MASK 0x00001E00L +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK0_MASK 0x0001E000L +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK1_MASK 0x001E0000L +#define UTCL1_HASH_CTRL__UTCL1_WAY_SEL_MASK2_MASK 0x01E00000L +#define UTCL1_HASH_CTRL__UTCL1_XOR_ONLY_HIGHER_WAYS_MASK 0x02000000L +#define UTCL1_HASH_CTRL__UTCL1_WAY_SELECT_OFFSET_MASK 0x7C000000L +#define UTCL1_HASH_CTRL__RESERVED_MASK 0x80000000L +//UTCL1_ALOG +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD__SHIFT 0x0 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS__SHIFT 0x3 +#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE__SHIFT 0x4 +#define UTCL1_ALOG__UTCL1_ALOG_MODE__SHIFT 0x5 +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW__SHIFT 0x6 +#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS__SHIFT 0x9 +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD__SHIFT 0xa +#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN__SHIFT 0xc +#define UTCL1_ALOG__UTCL1_ALOG_CLEAN__SHIFT 0xf +#define UTCL1_ALOG__UTCL1_ALOG_IDLE__SHIFT 0x10 +#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE__SHIFT 0x11 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS__SHIFT 0x17 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC__SHIFT 0x18 +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_THRESHOLD_MASK 0x00000007L +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER2_BYPASS_MASK 0x00000008L +#define UTCL1_ALOG__UTCL1_ALOG_ACTIVE_MASK 0x00000010L +#define UTCL1_ALOG__UTCL1_ALOG_MODE_MASK 0x00000020L +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_LOCK_WINDOW_MASK 0x000001C0L +#define UTCL1_ALOG__UTCL1_ALOG_ONLY_MISS_MASK 0x00000200L +#define UTCL1_ALOG__UTCL1_ALOG_MODE2_INTR_THRESHOLD_MASK 0x00000C00L +#define UTCL1_ALOG__UTCL1_ALOG_SPACE_EN_MASK 0x00007000L +#define UTCL1_ALOG__UTCL1_ALOG_CLEAN_MASK 0x00008000L +#define UTCL1_ALOG__UTCL1_ALOG_IDLE_MASK 0x00010000L +#define UTCL1_ALOG__UTCL1_ALOG_TRACK_SEGMENT_SIZE_MASK 0x007E0000L +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_FILTER1_BYPASS_MASK 0x00800000L +#define UTCL1_ALOG__UTCL1_ALOG_MODE1_INTR_ON_ALLOC_MASK 0x01000000L +//UTCL1_STATUS +#define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY__SHIFT 0x0 +#define UTCL1_STATUS__UTCL1_MH_BUSY__SHIFT 0x1 +#define UTCL1_STATUS__UTCL1_INV_BUSY__SHIFT 0x2 +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ__SHIFT 0x3 +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET__SHIFT 0x4 +#define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK__SHIFT 0x5 +#define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS__SHIFT 0x7 +#define UTCL1_STATUS__RESERVED__SHIFT 0x8 +#define UTCL1_STATUS__UTCL1_HIT_PATH_BUSY_MASK 0x00000001L +#define UTCL1_STATUS__UTCL1_MH_BUSY_MASK 0x00000002L +#define UTCL1_STATUS__UTCL1_INV_BUSY_MASK 0x00000004L +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_REQ_MASK 0x00000008L +#define UTCL1_STATUS__UTCL1_PENDING_UTCL2_RET_MASK 0x00000010L +#define UTCL1_STATUS__UTCL1_LAST_UTCL2_RET_XNACK_MASK 0x00000060L +#define UTCL1_STATUS__UTCL1_RANGE_INV_IN_PROGRESS_MASK 0x00000080L +#define UTCL1_STATUS__RESERVED_MASK 0x00000100L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_shdec +//SPI_SHADER_PGM_CHKSUM_PS +#define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM__SHIFT 0x0 +#define SPI_SHADER_PGM_CHKSUM_PS__CHECKSUM_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC3_PS +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0x0000FFFFL +//SPI_SHADER_PGM_RSRC4_PS +#define SPI_SHADER_PGM_RSRC4_PS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_PS__LDS_GROUP_SIZE__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC4_PS__DIDT_THROTTLE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC4_PS__WAVE_LIMIT_MASK 0x000003FFL +#define SPI_SHADER_PGM_RSRC4_PS__LDS_GROUP_SIZE_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC4_PS__DIDT_THROTTLE_MASK 0x00001000L +#define SPI_SHADER_PGM_RSRC4_PS__INST_PREF_SIZE_MASK 0x00FF0000L +#define SPI_SHADER_PGM_RSRC4_PS__IMAGE_OP_MASK 0x80000000L +//SPI_SHADER_PGM_LO_PS +#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_PS +#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0x000000FFL +//SPI_SHADER_PGM_RSRC1_PS +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_PS__WG_RR_EN__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_PS__DISABLE_PERF__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_PS__WG_RR_EN_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_PS__DISABLE_PERF_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_PS__FWD_PROGRESS_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_PS__LOAD_PROVOKING_VTX_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000L +#define SPI_SHADER_PGM_RSRC1_PS__FP16_OVFL_MASK 0x20000000L +//SPI_SHADER_PGM_RSRC2_PS +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0x0000FF00L +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x01FF0000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_COLLISION_WAVEID_MASK 0x02000000L +#define SPI_SHADER_PGM_RSRC2_PS__LOAD_INTRAWAVE_COLLISION_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MSB_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_PS__SHARED_VGPR_CNT_MASK 0xF0000000L +//SPI_SHADER_USER_DATA_PS_0 +#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_1 +#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_2 +#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_3 +#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_4 +#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_5 +#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_6 +#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_7 +#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_8 +#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_9 +#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_10 +#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_11 +#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_12 +#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_13 +#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_14 +#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_15 +#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_16 +#define SPI_SHADER_USER_DATA_PS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_17 +#define SPI_SHADER_USER_DATA_PS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_18 +#define SPI_SHADER_USER_DATA_PS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_19 +#define SPI_SHADER_USER_DATA_PS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_20 +#define SPI_SHADER_USER_DATA_PS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_21 +#define SPI_SHADER_USER_DATA_PS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_22 +#define SPI_SHADER_USER_DATA_PS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_23 +#define SPI_SHADER_USER_DATA_PS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_24 +#define SPI_SHADER_USER_DATA_PS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_25 +#define SPI_SHADER_USER_DATA_PS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_26 +#define SPI_SHADER_USER_DATA_PS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_27 +#define SPI_SHADER_USER_DATA_PS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_28 +#define SPI_SHADER_USER_DATA_PS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_29 +#define SPI_SHADER_USER_DATA_PS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_30 +#define SPI_SHADER_USER_DATA_PS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_PS_31 +#define SPI_SHADER_USER_DATA_PS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_REQ_CTRL_PS +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN__SHIFT 0x0 +#define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_EN_MASK 0x00000001L +#define SPI_SHADER_REQ_CTRL_PS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define SPI_SHADER_REQ_CTRL_PS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define SPI_SHADER_REQ_CTRL_PS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define SPI_SHADER_REQ_CTRL_PS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define SPI_SHADER_REQ_CTRL_PS__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define SPI_SHADER_REQ_CTRL_PS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +//SPI_SHADER_GS_OUT_CONFIG_PS +#define SPI_SHADER_GS_OUT_CONFIG_PS__VS_EXPORT_COUNT__SHIFT 0x0 +#define SPI_SHADER_GS_OUT_CONFIG_PS__PRIM_EXPORT_COUNT__SHIFT 0x5 +#define SPI_SHADER_GS_OUT_CONFIG_PS__NO_PC_EXPORT__SHIFT 0xa +#define SPI_SHADER_GS_OUT_CONFIG_PS__NUM_INTERP__SHIFT 0xb +#define SPI_SHADER_GS_OUT_CONFIG_PS__NUM_PRIM_INTERP__SHIFT 0x11 +#define SPI_SHADER_GS_OUT_CONFIG_PS__VS_EXPORT_COUNT_MASK 0x0000001FL +#define SPI_SHADER_GS_OUT_CONFIG_PS__PRIM_EXPORT_COUNT_MASK 0x000003E0L +#define SPI_SHADER_GS_OUT_CONFIG_PS__NO_PC_EXPORT_MASK 0x00000400L +#define SPI_SHADER_GS_OUT_CONFIG_PS__NUM_INTERP_MASK 0x0001F800L +#define SPI_SHADER_GS_OUT_CONFIG_PS__NUM_PRIM_INTERP_MASK 0x003E0000L +//SPI_SHADER_USER_ACCUM_PS_0 +#define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_0__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_PS_1 +#define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_1__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_PS_2 +#define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_2__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_PS_3 +#define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_PS_3__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_PGM_CHKSUM_GS +#define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM__SHIFT 0x0 +#define SPI_SHADER_PGM_CHKSUM_GS__CHECKSUM_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_LO_GS +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_GS +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_GS +#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_GS +#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_ES +#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0x000000FFL +//SPI_SHADER_PGM_RSRC3_GS +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC4_GS +#define SPI_SHADER_PGM_RSRC4_GS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_GS__GLG_EN_OVERRIDE__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC4_GS__GLG_FORCE_DISABLE__SHIFT 0xb +#define SPI_SHADER_PGM_RSRC4_GS__DIDT_THROTTLE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN__SHIFT 0xe +#define SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN__SHIFT 0xf +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC4_GS__WAVE_LIMIT_MASK 0x000003FFL +#define SPI_SHADER_PGM_RSRC4_GS__GLG_EN_OVERRIDE_MASK 0x00000400L +#define SPI_SHADER_PGM_RSRC4_GS__GLG_FORCE_DISABLE_MASK 0x00000800L +#define SPI_SHADER_PGM_RSRC4_GS__DIDT_THROTTLE_MASK 0x00001000L +#define SPI_SHADER_PGM_RSRC4_GS__PH_THROTTLE_EN_MASK 0x00004000L +#define SPI_SHADER_PGM_RSRC4_GS__SPI_THROTTLE_EN_MASK 0x00008000L +#define SPI_SHADER_PGM_RSRC4_GS__SPI_SHADER_LATE_ALLOC_GS_MASK 0x007F0000L +#define SPI_SHADER_PGM_RSRC4_GS__INST_PREF_SIZE_MASK 0x7F800000L +#define SPI_SHADER_PGM_RSRC4_GS__IMAGE_OP_MASK 0x80000000L +//SPI_SHADER_PGM_LO_ES +#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC1_GS +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_GS__WG_RR_EN__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_GS__DISABLE_PERF__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_GS__WG_RR_EN_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_GS__DISABLE_PERF_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x01000000L +#define SPI_SHADER_PGM_RSRC1_GS__FWD_PROGRESS_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_GS__WGP_MODE_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000L +#define SPI_SHADER_PGM_RSRC1_GS__GS_VGPR_COMP_CNT_MASK 0x60000000L +#define SPI_SHADER_PGM_RSRC1_GS__FP16_OVFL_MASK 0x80000000L +//SPI_SHADER_PGM_RSRC2_GS +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE__SHIFT 0x13 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0x0000FF80L +#define SPI_SHADER_PGM_RSRC2_GS__ES_VGPR_COMP_CNT_MASK 0x00030000L +#define SPI_SHADER_PGM_RSRC2_GS__OC_LDS_EN_MASK 0x00040000L +#define SPI_SHADER_PGM_RSRC2_GS__LDS_SIZE_MASK 0x07F80000L +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MSB_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_GS__SHARED_VGPR_CNT_MASK 0xF0000000L +//SPI_SHADER_USER_DATA_GS_0 +#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_1 +#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_2 +#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_3 +#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_4 +#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_5 +#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_6 +#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_7 +#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_8 +#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_9 +#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_10 +#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_11 +#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_12 +#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_13 +#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_14 +#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_15 +#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_16 +#define SPI_SHADER_USER_DATA_GS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_17 +#define SPI_SHADER_USER_DATA_GS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_18 +#define SPI_SHADER_USER_DATA_GS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_19 +#define SPI_SHADER_USER_DATA_GS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_20 +#define SPI_SHADER_USER_DATA_GS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_21 +#define SPI_SHADER_USER_DATA_GS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_22 +#define SPI_SHADER_USER_DATA_GS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_23 +#define SPI_SHADER_USER_DATA_GS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_24 +#define SPI_SHADER_USER_DATA_GS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_25 +#define SPI_SHADER_USER_DATA_GS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_26 +#define SPI_SHADER_USER_DATA_GS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_27 +#define SPI_SHADER_USER_DATA_GS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_28 +#define SPI_SHADER_USER_DATA_GS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_29 +#define SPI_SHADER_USER_DATA_GS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_30 +#define SPI_SHADER_USER_DATA_GS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_GS_31 +#define SPI_SHADER_USER_DATA_GS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_GS_MESHLET_DIM +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X__SHIFT 0x0 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y__SHIFT 0x8 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z__SHIFT 0x10 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE__SHIFT 0x18 +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_X_MASK 0x000000FFL +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Y_MASK 0x0000FF00L +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_NUM_THREAD_Z_MASK 0x00FF0000L +#define SPI_SHADER_GS_MESHLET_DIM__MESHLET_THREADGROUP_SIZE_MASK 0xFF000000L +//SPI_SHADER_GS_MESHLET_EXP_ALLOC +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS__SHIFT 0x0 +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS__SHIFT 0x9 +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_VERTS_MASK 0x000001FFL +#define SPI_SHADER_GS_MESHLET_EXP_ALLOC__MAX_EXP_PRIMS_MASK 0x0003FE00L +//SPI_SHADER_GS_MESHLET_CTRL +#define SPI_SHADER_GS_MESHLET_CTRL__INTERLEAVE_BITS_X__SHIFT 0x0 +#define SPI_SHADER_GS_MESHLET_CTRL__INTERLEAVE_BITS_Y__SHIFT 0x4 +#define SPI_SHADER_GS_MESHLET_CTRL__INTERLEAVE_BITS_X_MASK 0x0000000FL +#define SPI_SHADER_GS_MESHLET_CTRL__INTERLEAVE_BITS_Y_MASK 0x000000F0L +//SPI_SHADER_REQ_CTRL_ESGS +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN__SHIFT 0x0 +#define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_EN_MASK 0x00000001L +#define SPI_SHADER_REQ_CTRL_ESGS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define SPI_SHADER_REQ_CTRL_ESGS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define SPI_SHADER_REQ_CTRL_ESGS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define SPI_SHADER_REQ_CTRL_ESGS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define SPI_SHADER_REQ_CTRL_ESGS__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define SPI_SHADER_REQ_CTRL_ESGS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +//SPI_SHADER_GS_OUT_CONFIG_PS_GS +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__VS_EXPORT_COUNT__SHIFT 0x0 +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__PRIM_EXPORT_COUNT__SHIFT 0x5 +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NO_PC_EXPORT__SHIFT 0xa +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NUM_INTERP__SHIFT 0xb +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NUM_PRIM_INTERP__SHIFT 0x11 +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__VS_EXPORT_COUNT_MASK 0x0000001FL +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__PRIM_EXPORT_COUNT_MASK 0x000003E0L +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NO_PC_EXPORT_MASK 0x00000400L +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NUM_INTERP_MASK 0x0001F800L +#define SPI_SHADER_GS_OUT_CONFIG_PS_GS__NUM_PRIM_INTERP_MASK 0x003E0000L +//SPI_SHADER_USER_ACCUM_ESGS_0 +#define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_0__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_ESGS_1 +#define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_1__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_ESGS_2 +#define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_2__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_ESGS_3 +#define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_ESGS_3__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_PGM_CHKSUM_HS +#define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM__SHIFT 0x0 +#define SPI_SHADER_PGM_CHKSUM_HS__CHECKSUM_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_LO_HS +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_ADDR_HI_HS +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ADDR_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_LO_HS +#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_HS +#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_HI_LS +#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0x000000FFL +//SPI_SHADER_PGM_RSRC3_HS +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_HS__CU_EN_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC4_HS +#define SPI_SHADER_PGM_RSRC4_HS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC4_HS__GLG_EN_OVERRIDE__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC4_HS__GLG_FORCE_DISABLE__SHIFT 0xb +#define SPI_SHADER_PGM_RSRC4_HS__DIDT_THROTTLE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP__SHIFT 0x1f +#define SPI_SHADER_PGM_RSRC4_HS__WAVE_LIMIT_MASK 0x000003FFL +#define SPI_SHADER_PGM_RSRC4_HS__GLG_EN_OVERRIDE_MASK 0x00000400L +#define SPI_SHADER_PGM_RSRC4_HS__GLG_FORCE_DISABLE_MASK 0x00000800L +#define SPI_SHADER_PGM_RSRC4_HS__DIDT_THROTTLE_MASK 0x00001000L +#define SPI_SHADER_PGM_RSRC4_HS__INST_PREF_SIZE_MASK 0x00FF0000L +#define SPI_SHADER_PGM_RSRC4_HS__IMAGE_OP_MASK 0x80000000L +//SPI_SHADER_PGM_LO_LS +#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xFFFFFFFFL +//SPI_SHADER_PGM_RSRC1_HS +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_HS__WG_RR_EN__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_HS__DISABLE_PERF__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x0000003FL +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x000003C0L +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0x00000C00L +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0x000FF000L +#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x00100000L +#define SPI_SHADER_PGM_RSRC1_HS__WG_RR_EN_MASK 0x00200000L +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x00400000L +#define SPI_SHADER_PGM_RSRC1_HS__DISABLE_PERF_MASK 0x00800000L +#define SPI_SHADER_PGM_RSRC1_HS__FWD_PROGRESS_MASK 0x02000000L +#define SPI_SHADER_PGM_RSRC1_HS__WGP_MODE_MASK 0x04000000L +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC1_HS__LS_VGPR_COMP_CNT_MASK 0x30000000L +#define SPI_SHADER_PGM_RSRC1_HS__FP16_OVFL_MASK 0x40000000L +//SPI_SHADER_PGM_RSRC2_HS +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE__SHIFT 0x12 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x00000001L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x0000003EL +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x00000040L +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x00000080L +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x00000100L +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x0003FE00L +#define SPI_SHADER_PGM_RSRC2_HS__LDS_SIZE_MASK 0x07FC0000L +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MSB_MASK 0x08000000L +#define SPI_SHADER_PGM_RSRC2_HS__SHARED_VGPR_CNT_MASK 0xF0000000L +//SPI_SHADER_USER_DATA_HS_0 +#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_1 +#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_2 +#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_3 +#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_4 +#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_5 +#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_6 +#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_7 +#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_8 +#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_9 +#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_10 +#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_11 +#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_12 +#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_13 +#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_14 +#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_15 +#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_16 +#define SPI_SHADER_USER_DATA_HS_16__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_16__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_17 +#define SPI_SHADER_USER_DATA_HS_17__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_17__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_18 +#define SPI_SHADER_USER_DATA_HS_18__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_18__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_19 +#define SPI_SHADER_USER_DATA_HS_19__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_19__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_20 +#define SPI_SHADER_USER_DATA_HS_20__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_20__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_21 +#define SPI_SHADER_USER_DATA_HS_21__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_21__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_22 +#define SPI_SHADER_USER_DATA_HS_22__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_22__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_23 +#define SPI_SHADER_USER_DATA_HS_23__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_23__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_24 +#define SPI_SHADER_USER_DATA_HS_24__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_24__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_25 +#define SPI_SHADER_USER_DATA_HS_25__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_25__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_26 +#define SPI_SHADER_USER_DATA_HS_26__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_26__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_27 +#define SPI_SHADER_USER_DATA_HS_27__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_27__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_28 +#define SPI_SHADER_USER_DATA_HS_28__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_28__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_29 +#define SPI_SHADER_USER_DATA_HS_29__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_29__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_30 +#define SPI_SHADER_USER_DATA_HS_30__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_30__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_USER_DATA_HS_31 +#define SPI_SHADER_USER_DATA_HS_31__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_31__DATA_MASK 0xFFFFFFFFL +//SPI_SHADER_REQ_CTRL_LSHS +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN__SHIFT 0x0 +#define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_EN_MASK 0x00000001L +#define SPI_SHADER_REQ_CTRL_LSHS__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define SPI_SHADER_REQ_CTRL_LSHS__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define SPI_SHADER_REQ_CTRL_LSHS__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define SPI_SHADER_REQ_CTRL_LSHS__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define SPI_SHADER_REQ_CTRL_LSHS__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define SPI_SHADER_REQ_CTRL_LSHS__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +//SPI_SHADER_USER_ACCUM_LSHS_0 +#define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_0__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_LSHS_1 +#define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_1__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_LSHS_2 +#define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_2__CONTRIBUTION_MASK 0x0000007FL +//SPI_SHADER_USER_ACCUM_LSHS_3 +#define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION__SHIFT 0x0 +#define SPI_SHADER_USER_ACCUM_LSHS_3__CONTRIBUTION_MASK 0x0000007FL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_spipdec +//SPI_ARB_PRIORITY +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc +#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe +#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x00000007L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x00000038L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x000001C0L +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0x00000E00L +#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x00003000L +#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0x0000C000L +#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x00030000L +#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0x000C0000L +//SPI_ARB_CYCLES_0 +#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xFFFF0000L +//SPI_ARB_CYCLES_1 +#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0x0000FFFFL +#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xFFFF0000L +//SPI_WCL_PIPE_PERCENT_GFX +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_HP3D +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x0000007FL +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x0001F000L +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x07C00000L +//SPI_WCL_PIPE_PERCENT_CS0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS1 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS2 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS3 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS4 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS5 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS6 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x0000007FL +//SPI_WCL_PIPE_PERCENT_CS7 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x0000007FL +//SPI_USER_ACCUM_VMID_CNTL +#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM__SHIFT 0x0 +#define SPI_USER_ACCUM_VMID_CNTL__EN_USER_ACCUM_MASK 0x0000000FL +//SPI_GDBG_PER_VMID_CNTL +#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID__SHIFT 0x0 +#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE__SHIFT 0x1 +#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN__SHIFT 0x3 +#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN__SHIFT 0x4 +#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE__SHIFT 0xd +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START__SHIFT 0xe +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END__SHIFT 0xf +#define SPI_GDBG_PER_VMID_CNTL__STALL_VMID_MASK 0x00000001L +#define SPI_GDBG_PER_VMID_CNTL__LAUNCH_MODE_MASK 0x00000006L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_EN_MASK 0x00000008L +#define SPI_GDBG_PER_VMID_CNTL__EXCP_EN_MASK 0x00001FF0L +#define SPI_GDBG_PER_VMID_CNTL__EXCP_REPLACE_MASK 0x00002000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_START_MASK 0x00004000L +#define SPI_GDBG_PER_VMID_CNTL__TRAP_ON_END_MASK 0x00008000L +//SPI_COMPUTE_QUEUE_RESET +#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 +#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x00000001L +//SPI_COMPUTE_WF_CTX_SAVE +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x00000001L +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x00000004L +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000L +//SPI_SAVE_RESTORE_STATUS +#define SPI_SAVE_RESTORE_STATUS__PERFCOUNTER_EN__SHIFT 0x0 +#define SPI_SAVE_RESTORE_STATUS__THREAD_TRACE_EN__SHIFT 0x1 +#define SPI_SAVE_RESTORE_STATUS__PERFCOUNTER_EN_MASK 0x00000001L +#define SPI_SAVE_RESTORE_STATUS__THREAD_TRACE_EN_MASK 0x00000002L +//SPI_CONFIG_DIDT_CNTL +#define SPI_CONFIG_DIDT_CNTL__DELAY_SELECT__SHIFT 0x0 +#define SPI_CONFIG_DIDT_CNTL__INCR_EVENT__SHIFT 0x6 +#define SPI_CONFIG_DIDT_CNTL__THRESHOLD__SHIFT 0x8 +#define SPI_CONFIG_DIDT_CNTL__STALL_WAVES__SHIFT 0xe +#define SPI_CONFIG_DIDT_CNTL__STALL_RATE__SHIFT 0x10 +#define SPI_CONFIG_DIDT_CNTL__THROTTLE_EN__SHIFT 0x15 +#define SPI_CONFIG_DIDT_CNTL__DELAY_SELECT_MASK 0x0000003FL +#define SPI_CONFIG_DIDT_CNTL__INCR_EVENT_MASK 0x000000C0L +#define SPI_CONFIG_DIDT_CNTL__THRESHOLD_MASK 0x00003F00L +#define SPI_CONFIG_DIDT_CNTL__STALL_WAVES_MASK 0x0000C000L +#define SPI_CONFIG_DIDT_CNTL__STALL_RATE_MASK 0x001F0000L +#define SPI_CONFIG_DIDT_CNTL__THROTTLE_EN_MASK 0x00200000L +//SPI_CONFIG_DIDT_TYPEMASK +#define SPI_CONFIG_DIDT_TYPEMASK__GFX_TYPE_ENABLE__SHIFT 0x0 +#define SPI_CONFIG_DIDT_TYPEMASK__ACE_TYPE_ENABLE__SHIFT 0x4 +#define SPI_CONFIG_DIDT_TYPEMASK__GFX_TYPE_ENABLE_MASK 0x0000000FL +#define SPI_CONFIG_DIDT_TYPEMASK__ACE_TYPE_ENABLE_MASK 0x00000FF0L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_tcpdec +//TCP_WATCH0_ADDR_H +#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH0_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH0_ADDR_L +#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH0_CNTL +#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH0_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH0_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH1_ADDR_H +#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH1_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH1_ADDR_L +#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH1_CNTL +#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH1_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH1_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH2_ADDR_H +#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH2_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH2_ADDR_L +#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH2_CNTL +#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH2_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH2_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000L +//TCP_WATCH3_ADDR_H +#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH3_ADDR_H__ADDR_MASK 0x0000FFFFL +//TCP_WATCH3_ADDR_L +#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x7 +#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xFFFFFF80L +//TCP_WATCH3_CNTL +#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH3_CNTL__MASK_MASK 0x007FFFFFL +#define TCP_WATCH3_CNTL__VMID_MASK 0x0F000000L +#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000L +#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gfxdec0 +//DB_RENDER_CONTROL +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 +#define DB_RENDER_CONTROL__RESERVED_FIELD_1__SHIFT 0x2 +#define DB_RENDER_CONTROL__RESERVED_FIELD_2__SHIFT 0x3 +#define DB_RENDER_CONTROL__RESERVED_FIELD_4__SHIFT 0x4 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 +#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 +#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc +#define DB_RENDER_CONTROL__PS_INVOKE_DISABLE__SHIFT 0xe +#define DB_RENDER_CONTROL__OREO_MODE__SHIFT 0x10 +#define DB_RENDER_CONTROL__FORCE_OREO_MODE__SHIFT 0x12 +#define DB_RENDER_CONTROL__FORCE_EXPORT_ORDER__SHIFT 0x13 +#define DB_RENDER_CONTROL__MAX_ALLOWED_STILES_IN_WAVE__SHIFT 0x14 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x00000002L +#define DB_RENDER_CONTROL__RESERVED_FIELD_1_MASK 0x00000004L +#define DB_RENDER_CONTROL__RESERVED_FIELD_2_MASK 0x00000008L +#define DB_RENDER_CONTROL__RESERVED_FIELD_4_MASK 0x00000010L +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x00000020L +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x00000040L +#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x00000080L +#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0x00000F00L +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x00001000L +#define DB_RENDER_CONTROL__PS_INVOKE_DISABLE_MASK 0x00004000L +#define DB_RENDER_CONTROL__OREO_MODE_MASK 0x00030000L +#define DB_RENDER_CONTROL__FORCE_OREO_MODE_MASK 0x00040000L +#define DB_RENDER_CONTROL__FORCE_EXPORT_ORDER_MASK 0x00080000L +#define DB_RENDER_CONTROL__MAX_ALLOWED_STILES_IN_WAVE_MASK 0x00F00000L +//DB_DEPTH_VIEW +#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0x10 +#define DB_DEPTH_VIEW__SLICE_START_MASK 0x00003FFFL +#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0x3FFF0000L +//DB_DEPTH_VIEW1 +#define DB_DEPTH_VIEW1__Z_READ_ONLY__SHIFT 0x18 +#define DB_DEPTH_VIEW1__STENCIL_READ_ONLY__SHIFT 0x19 +#define DB_DEPTH_VIEW1__MIPID__SHIFT 0x1a +#define DB_DEPTH_VIEW1__Z_READ_ONLY_MASK 0x01000000L +#define DB_DEPTH_VIEW1__STENCIL_READ_ONLY_MASK 0x02000000L +#define DB_DEPTH_VIEW1__MIPID_MASK 0x7C000000L +//DB_RENDER_OVERRIDE +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa +#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0x0000000CL +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x00000030L +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x00000040L +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000080L +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000100L +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x00000200L +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x00000400L +#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x00000800L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x00001000L +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x00006000L +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x00180000L +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x03E00000L +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x04000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x08000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000L +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000L +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000L +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000L +//DB_RENDER_OVERRIDE2 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_5__SHIFT 0x5 +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_6__SHIFT 0x6 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_1__SHIFT 0x9 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa +#define DB_RENDER_OVERRIDE2__FORCE_SUMM_Z_RANGE_TO_MAX__SHIFT 0xb +#define DB_RENDER_OVERRIDE2__FORCE_SUMM_STENCIL_RANGE_TO_MAX__SHIFT 0xc +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_2__SHIFT 0xd +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL__SHIFT 0x19 +#define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE__SHIFT 0x1b +#define DB_RENDER_OVERRIDE2__DISABLE_NOZ__SHIFT 0x1d +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x00000003L +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x0000001CL +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_5_MASK 0x00000020L +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_6_MASK 0x00000040L +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x00000080L +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x00000100L +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_1_MASK 0x00000200L +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000400L +#define DB_RENDER_OVERRIDE2__FORCE_SUMM_Z_RANGE_TO_MAX_MASK 0x00000800L +#define DB_RENDER_OVERRIDE2__FORCE_SUMM_STENCIL_RANGE_TO_MAX_MASK 0x00001000L +#define DB_RENDER_OVERRIDE2__RESERVED_FIELD_2_MASK 0x001FE000L +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x00200000L +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x00800000L +#define DB_RENDER_OVERRIDE2__ALLOW_PARTIAL_RES_HIER_KILL_MASK 0x02000000L +#define DB_RENDER_OVERRIDE2__CENTROID_COMPUTATION_MODE_MASK 0x18000000L +#define DB_RENDER_OVERRIDE2__DISABLE_NOZ_MASK 0x20000000L +//DB_DEPTH_SIZE_XY +#define DB_DEPTH_SIZE_XY__X_MAX__SHIFT 0x0 +#define DB_DEPTH_SIZE_XY__Y_MAX__SHIFT 0x10 +#define DB_DEPTH_SIZE_XY__X_MAX_MASK 0x0000FFFFL +#define DB_DEPTH_SIZE_XY__Y_MAX_MASK 0xFFFF0000L +//DB_Z_INFO +#define DB_Z_INFO__FORMAT__SHIFT 0x0 +#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 +#define DB_Z_INFO__SW_MODE__SHIFT 0x4 +#define DB_Z_INFO__RESERVED_FIELD_2__SHIFT 0x9 +#define DB_Z_INFO__RESERVED_FIELD_11__SHIFT 0xb +#define DB_Z_INFO__RESERVED_FIELD_12__SHIFT 0xc +#define DB_Z_INFO__RESERVED_FIELD_1__SHIFT 0xd +#define DB_Z_INFO__MAXMIP__SHIFT 0xf +#define DB_Z_INFO__RESERVED_FIELD_20__SHIFT 0x14 +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 +#define DB_Z_INFO__RESERVED_FIELD_27__SHIFT 0x1b +#define DB_Z_INFO__RESERVED_FIELD_28__SHIFT 0x1c +#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d +#define DB_Z_INFO__FORMAT_MASK 0x00000003L +#define DB_Z_INFO__NUM_SAMPLES_MASK 0x0000000CL +#define DB_Z_INFO__SW_MODE_MASK 0x000001F0L +#define DB_Z_INFO__RESERVED_FIELD_2_MASK 0x00000600L +#define DB_Z_INFO__RESERVED_FIELD_11_MASK 0x00000800L +#define DB_Z_INFO__RESERVED_FIELD_12_MASK 0x00001000L +#define DB_Z_INFO__RESERVED_FIELD_1_MASK 0x00006000L +#define DB_Z_INFO__MAXMIP_MASK 0x000F8000L +#define DB_Z_INFO__RESERVED_FIELD_20_MASK 0x00100000L +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x07800000L +#define DB_Z_INFO__RESERVED_FIELD_27_MASK 0x08000000L +#define DB_Z_INFO__RESERVED_FIELD_28_MASK 0x10000000L +#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000L +//DB_STENCIL_INFO +#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 +#define DB_STENCIL_INFO__SW_MODE__SHIFT 0x4 +#define DB_STENCIL_INFO__RESERVED_FIELD_2__SHIFT 0x9 +#define DB_STENCIL_INFO__RESERVED_FIELD_11__SHIFT 0xb +#define DB_STENCIL_INFO__RESERVED_FIELD_12__SHIFT 0xc +#define DB_STENCIL_INFO__RESERVED_FIELD_1__SHIFT 0xd +#define DB_STENCIL_INFO__RESERVED_FIELD_20__SHIFT 0x14 +#define DB_STENCIL_INFO__RESERVED_FIELD_27__SHIFT 0x1b +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d +#define DB_STENCIL_INFO__FORMAT_MASK 0x00000001L +#define DB_STENCIL_INFO__SW_MODE_MASK 0x000001F0L +#define DB_STENCIL_INFO__RESERVED_FIELD_2_MASK 0x00000600L +#define DB_STENCIL_INFO__RESERVED_FIELD_11_MASK 0x00000800L +#define DB_STENCIL_INFO__RESERVED_FIELD_12_MASK 0x00001000L +#define DB_STENCIL_INFO__RESERVED_FIELD_1_MASK 0x0000E000L +#define DB_STENCIL_INFO__RESERVED_FIELD_20_MASK 0x00100000L +#define DB_STENCIL_INFO__RESERVED_FIELD_27_MASK 0x08000000L +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000L +//DB_Z_READ_BASE +#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_Z_READ_BASE_HI +#define DB_Z_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_Z_WRITE_BASE +#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_Z_WRITE_BASE_HI +#define DB_Z_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_Z_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_READ_BASE +#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_READ_BASE_HI +#define DB_STENCIL_READ_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_READ_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_STENCIL_WRITE_BASE +#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//DB_STENCIL_WRITE_BASE_HI +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE_HI__BASE_HI_MASK 0x000000FFL +//DB_GL1_INTERFACE_CONTROL +#define DB_GL1_INTERFACE_CONTROL__Z_SPECULATIVE_READ__SHIFT 0x0 +#define DB_GL1_INTERFACE_CONTROL__STENCIL_SPECULATIVE_READ__SHIFT 0x2 +#define DB_GL1_INTERFACE_CONTROL__Z_COMPRESSION_MODE__SHIFT 0x4 +#define DB_GL1_INTERFACE_CONTROL__STENCIL_COMPRESSION_MODE__SHIFT 0x6 +#define DB_GL1_INTERFACE_CONTROL__OCCLUSION_COMPRESSION_MODE__SHIFT 0x8 +#define DB_GL1_INTERFACE_CONTROL__Z_SPECULATIVE_READ_MASK 0x00000003L +#define DB_GL1_INTERFACE_CONTROL__STENCIL_SPECULATIVE_READ_MASK 0x0000000CL +#define DB_GL1_INTERFACE_CONTROL__Z_COMPRESSION_MODE_MASK 0x00000030L +#define DB_GL1_INTERFACE_CONTROL__STENCIL_COMPRESSION_MODE_MASK 0x000000C0L +#define DB_GL1_INTERFACE_CONTROL__OCCLUSION_COMPRESSION_MODE_MASK 0x00000300L +//DB_MEM_TEMPORAL +#define DB_MEM_TEMPORAL__Z_TEMPORAL_READ__SHIFT 0x0 +#define DB_MEM_TEMPORAL__Z_TEMPORAL_WRITE__SHIFT 0x3 +#define DB_MEM_TEMPORAL__STENCIL_TEMPORAL_READ__SHIFT 0x6 +#define DB_MEM_TEMPORAL__STENCIL_TEMPORAL_WRITE__SHIFT 0x9 +#define DB_MEM_TEMPORAL__OCCLUSION_TEMPORAL_WRITE__SHIFT 0xc +#define DB_MEM_TEMPORAL__Z_TEMPORAL_READ_MASK 0x00000007L +#define DB_MEM_TEMPORAL__Z_TEMPORAL_WRITE_MASK 0x00000038L +#define DB_MEM_TEMPORAL__STENCIL_TEMPORAL_READ_MASK 0x000001C0L +#define DB_MEM_TEMPORAL__STENCIL_TEMPORAL_WRITE_MASK 0x00000E00L +#define DB_MEM_TEMPORAL__OCCLUSION_TEMPORAL_WRITE_MASK 0x00007000L +//DB_DEPTH_BOUNDS_MIN +#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xFFFFFFFFL +//DB_DEPTH_BOUNDS_MAX +#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xFFFFFFFFL +//DB_COUNT_CONTROL +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 +#define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x2 +#define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS__SHIFT 0x3 +#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc +#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x00000002L +#define DB_COUNT_CONTROL__DISABLE_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000004L +#define DB_COUNT_CONTROL__ENHANCED_CONSERVATIVE_ZPASS_COUNTS_MASK 0x00000008L +#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0x00000F00L +#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0x0000F000L +#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0x000F0000L +#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0x00F00000L +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x0F000000L +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xF0000000L +//DB_VIEWPORT_CONTROL +#define DB_VIEWPORT_CONTROL__DISABLE_VIEWPORT_CLAMP__SHIFT 0x0 +#define DB_VIEWPORT_CONTROL__DISABLE_VIEWPORT_CLAMP_MASK 0x00000001L +//DB_SPI_VRS_CENTER_LOCATION +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_1X1__SHIFT 0x0 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_1X1__SHIFT 0x4 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_2X1__SHIFT 0x8 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_2X1__SHIFT 0xc +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_1X2__SHIFT 0x10 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_1X2__SHIFT 0x14 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_2X2__SHIFT 0x18 +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_2X2__SHIFT 0x1c +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_1X1_MASK 0x0000000FL +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_1X1_MASK 0x000000F0L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_2X1_MASK 0x00000F00L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_2X1_MASK 0x0000F000L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_1X2_MASK 0x000F0000L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_1X2_MASK 0x00F00000L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_X_OFFSET_2X2_MASK 0x0F000000L +#define DB_SPI_VRS_CENTER_LOCATION__CENTER_Y_OFFSET_2X2_MASK 0xF0000000L +//DB_SHADER_CONTROL +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 +#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 +#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER__SHIFT 0x10 +#define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE__SHIFT 0x17 +#define DB_SHADER_CONTROL__OREO_BLEND_ENABLE__SHIFT 0x18 +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE__SHIFT 0x19 +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE__SHIFT 0x1a +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x00000001L +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x00000002L +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x00000004L +#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x00000030L +#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x00000040L +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x00000080L +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x00000100L +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x00000200L +#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x00000400L +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x00000800L +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x00001000L +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00006000L +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x00008000L +#define DB_SHADER_CONTROL__PRIMITIVE_ORDERED_PIXEL_SHADER_MASK 0x00010000L +#define DB_SHADER_CONTROL__PRE_SHADER_DEPTH_COVERAGE_ENABLE_MASK 0x00800000L +#define DB_SHADER_CONTROL__OREO_BLEND_ENABLE_MASK 0x01000000L +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_ENABLE_MASK 0x02000000L +#define DB_SHADER_CONTROL__OVERRIDE_INTRINSIC_RATE_MASK 0x1C000000L +//DB_DEPTH_CONTROL +#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 +#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 +#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 +#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 +#define DB_DEPTH_CONTROL__RESERVED_FIELD_30__SHIFT 0x1e +#define DB_DEPTH_CONTROL__RESERVED_FIELD_31__SHIFT 0x1f +#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x00000001L +#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x00000002L +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x00000004L +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x00000008L +#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x00000070L +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x00000080L +#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x00000700L +#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x00700000L +#define DB_DEPTH_CONTROL__RESERVED_FIELD_30_MASK 0x40000000L +#define DB_DEPTH_CONTROL__RESERVED_FIELD_31_MASK 0x80000000L +//DB_STENCIL_CONTROL +#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 +#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 +#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc +#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 +#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0x0000000FL +#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0x000000F0L +#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0x00000F00L +#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0x0000F000L +#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0x000F0000L +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0x00F00000L +//DB_EQAA +#define DB_EQAA__RESERVED_FIELD_1__SHIFT 0x0 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 +#define DB_EQAA__RESERVED_FIELD_17__SHIFT 0x11 +#define DB_EQAA__RESERVED_FIELD_18__SHIFT 0x12 +#define DB_EQAA__RESERVED_FIELD_19__SHIFT 0x13 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 +#define DB_EQAA__RESERVED_FIELD_21__SHIFT 0x15 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b +#define DB_EQAA__RESERVED_FIELD_1_MASK 0x00000007L +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x00000700L +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x00007000L +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x00010000L +#define DB_EQAA__RESERVED_FIELD_17_MASK 0x00020000L +#define DB_EQAA__RESERVED_FIELD_18_MASK 0x00040000L +#define DB_EQAA__RESERVED_FIELD_19_MASK 0x00080000L +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x00100000L +#define DB_EQAA__RESERVED_FIELD_21_MASK 0x00200000L +#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x07000000L +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x08000000L +//DB_ALPHA_TO_MASK +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe +#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x00000001L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x00000300L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0x00000C00L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x00003000L +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0x0000C000L +#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x00010000L +//TA_BC_BASE_ADDR +#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL +//TA_BC_BASE_ADDR_HI +#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL +//DB_STENCIL_REF +#define DB_STENCIL_REF__TESTVAL__SHIFT 0x0 +#define DB_STENCIL_REF__TESTVAL_BF__SHIFT 0x8 +#define DB_STENCIL_REF__TESTVAL_MASK 0x000000FFL +#define DB_STENCIL_REF__TESTVAL_BF_MASK 0x0000FF00L +//DB_STENCIL_OPVAL +#define DB_STENCIL_OPVAL__OPVAL__SHIFT 0x0 +#define DB_STENCIL_OPVAL__OPVAL_BF__SHIFT 0x8 +#define DB_STENCIL_OPVAL__OPVAL_MASK 0x000000FFL +#define DB_STENCIL_OPVAL__OPVAL_BF_MASK 0x0000FF00L +//DB_STENCIL_READ_MASK +#define DB_STENCIL_READ_MASK__TESTMASK__SHIFT 0x0 +#define DB_STENCIL_READ_MASK__TESTMASK_BF__SHIFT 0x8 +#define DB_STENCIL_READ_MASK__TESTMASK_MASK 0x000000FFL +#define DB_STENCIL_READ_MASK__TESTMASK_BF_MASK 0x0000FF00L +//DB_STENCIL_WRITE_MASK +#define DB_STENCIL_WRITE_MASK__WRITEMASK__SHIFT 0x0 +#define DB_STENCIL_WRITE_MASK__WRITEMASK_BF__SHIFT 0x8 +#define DB_STENCIL_WRITE_MASK__WRITEMASK_MASK 0x000000FFL +#define DB_STENCIL_WRITE_MASK__WRITEMASK_BF_MASK 0x0000FF00L +//SC_MEM_TEMPORAL +#define SC_MEM_TEMPORAL__VRS_TEMPORAL_READ__SHIFT 0x0 +#define SC_MEM_TEMPORAL__VRS_TEMPORAL_WRITE__SHIFT 0x3 +#define SC_MEM_TEMPORAL__HIZ_TEMPORAL_READ__SHIFT 0x6 +#define SC_MEM_TEMPORAL__HIZ_TEMPORAL_WRITE__SHIFT 0x9 +#define SC_MEM_TEMPORAL__HIS_TEMPORAL_READ__SHIFT 0xc +#define SC_MEM_TEMPORAL__HIS_TEMPORAL_WRITE__SHIFT 0xf +#define SC_MEM_TEMPORAL__VRS_TEMPORAL_READ_MASK 0x00000007L +#define SC_MEM_TEMPORAL__VRS_TEMPORAL_WRITE_MASK 0x00000038L +#define SC_MEM_TEMPORAL__HIZ_TEMPORAL_READ_MASK 0x000001C0L +#define SC_MEM_TEMPORAL__HIZ_TEMPORAL_WRITE_MASK 0x00000E00L +#define SC_MEM_TEMPORAL__HIS_TEMPORAL_READ_MASK 0x00007000L +#define SC_MEM_TEMPORAL__HIS_TEMPORAL_WRITE_MASK 0x00038000L +//SC_MEM_SPEC_READ +#define SC_MEM_SPEC_READ__VRS_SPECULATIVE_READ__SHIFT 0x0 +#define SC_MEM_SPEC_READ__HIZ_SPECULATIVE_READ__SHIFT 0x2 +#define SC_MEM_SPEC_READ__HIS_SPECULATIVE_READ__SHIFT 0x4 +#define SC_MEM_SPEC_READ__VRS_SPECULATIVE_READ_MASK 0x00000003L +#define SC_MEM_SPEC_READ__HIZ_SPECULATIVE_READ_MASK 0x0000000CL +#define SC_MEM_SPEC_READ__HIS_SPECULATIVE_READ_MASK 0x00000030L +//PA_SC_VPORT_0_TL +#define PA_SC_VPORT_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_0_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_0_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_0_BR +#define PA_SC_VPORT_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_0_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_0_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_1_TL +#define PA_SC_VPORT_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_1_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_1_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_1_BR +#define PA_SC_VPORT_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_1_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_1_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_2_TL +#define PA_SC_VPORT_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_2_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_2_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_2_BR +#define PA_SC_VPORT_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_2_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_2_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_3_TL +#define PA_SC_VPORT_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_3_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_3_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_3_BR +#define PA_SC_VPORT_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_3_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_3_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_4_TL +#define PA_SC_VPORT_4_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_4_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_4_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_4_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_4_BR +#define PA_SC_VPORT_4_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_4_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_4_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_4_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_5_TL +#define PA_SC_VPORT_5_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_5_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_5_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_5_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_5_BR +#define PA_SC_VPORT_5_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_5_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_5_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_5_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_6_TL +#define PA_SC_VPORT_6_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_6_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_6_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_6_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_6_BR +#define PA_SC_VPORT_6_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_6_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_6_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_6_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_7_TL +#define PA_SC_VPORT_7_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_7_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_7_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_7_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_7_BR +#define PA_SC_VPORT_7_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_7_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_7_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_7_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_8_TL +#define PA_SC_VPORT_8_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_8_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_8_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_8_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_8_BR +#define PA_SC_VPORT_8_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_8_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_8_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_8_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_9_TL +#define PA_SC_VPORT_9_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_9_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_9_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_9_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_9_BR +#define PA_SC_VPORT_9_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_9_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_9_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_9_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_10_TL +#define PA_SC_VPORT_10_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_10_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_10_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_10_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_10_BR +#define PA_SC_VPORT_10_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_10_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_10_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_10_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_11_TL +#define PA_SC_VPORT_11_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_11_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_11_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_11_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_11_BR +#define PA_SC_VPORT_11_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_11_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_11_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_11_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_12_TL +#define PA_SC_VPORT_12_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_12_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_12_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_12_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_12_BR +#define PA_SC_VPORT_12_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_12_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_12_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_12_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_13_TL +#define PA_SC_VPORT_13_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_13_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_13_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_13_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_13_BR +#define PA_SC_VPORT_13_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_13_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_13_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_13_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_14_TL +#define PA_SC_VPORT_14_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_14_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_14_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_14_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_14_BR +#define PA_SC_VPORT_14_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_14_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_14_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_14_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_15_TL +#define PA_SC_VPORT_15_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_15_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_15_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_15_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_15_BR +#define PA_SC_VPORT_15_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_15_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_15_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_15_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_SCISSOR_TL +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_SCISSOR_BR +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_WINDOW_OFFSET +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0x0000FFFFL +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xFFFF0000L +//PA_SC_WINDOW_SCISSOR_TL +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_WINDOW_SCISSOR_BR +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_CLIPRECT_RULE +#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 +#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0x0000FFFFL +//PA_SC_CLIPRECT_0_TL +#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_0_BR +#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_TL +#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_1_BR +#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_TL +#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_2_BR +#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_TL +#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7FFF0000L +//PA_SC_CLIPRECT_3_BR +#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x00007FFFL +#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7FFF0000L +//PA_SC_EDGERULE +#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 +#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 +#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc +#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 +#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 +#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c +#define PA_SC_EDGERULE__ER_TRI_MASK 0x0000000FL +#define PA_SC_EDGERULE__ER_POINT_MASK 0x000000F0L +#define PA_SC_EDGERULE__ER_RECT_MASK 0x00000F00L +#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x0003F000L +#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0x00FC0000L +#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0x0F000000L +#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xF0000000L +//PA_SU_HARDWARE_SCREEN_OFFSET +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x00000FFFL +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x0FFF0000L +//PA_SC_GENERIC_SCISSOR_TL +#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_GENERIC_SCISSOR_BR +#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_0_TL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_0_BR +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_1_TL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_1_BR +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_2_TL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_2_BR +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_3_TL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_3_BR +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_4_TL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_4_BR +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_5_TL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_5_BR +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_6_TL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_6_BR +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_7_TL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_7_BR +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_8_TL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_8_BR +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_9_TL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_9_BR +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_10_TL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_10_BR +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_11_TL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_11_BR +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_12_TL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_12_BR +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_13_TL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_13_BR +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_14_TL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_14_BR +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_15_TL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0xFFFF0000L +//PA_SC_VPORT_SCISSOR_15_BR +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x0000FFFFL +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0xFFFF0000L +//PA_CL_UCP_0_X +#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Y +#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_Z +#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_0_W +#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_X +#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Y +#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_Z +#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_1_W +#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_X +#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Y +#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_Z +#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_2_W +#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_X +#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Y +#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_Z +#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_3_W +#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_X +#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Y +#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_Z +#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_4_W +#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_X +#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Y +#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_Z +#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_UCP_5_W +#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_PROG_NEAR_CLIP_Z +#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_PROG_NEAR_CLIP_Z__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_RATE_CNTL +#define PA_RATE_CNTL__VERTEX_RATE__SHIFT 0x0 +#define PA_RATE_CNTL__PRIM_RATE__SHIFT 0x4 +#define PA_RATE_CNTL__VERTEX_RATE_MASK 0x0000000FL +#define PA_RATE_CNTL__PRIM_RATE_MASK 0x000000F0L +//PA_SC_RASTER_CONFIG +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 +#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 +#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 +#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa +#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc +#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe +#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 +#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 +#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 +#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 +#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a +#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0x0000000CL +#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x00000030L +#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x00000040L +#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x00000080L +#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x00000300L +#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0x00000C00L +#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x00003000L +#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0x0000C000L +#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x00030000L +#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0x000C0000L +#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x00300000L +#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x03000000L +#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0x0C000000L +#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000L +//PA_SC_RASTER_CONFIG_1 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x00000003L +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0x0000000CL +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x00000030L +//PA_SC_SCREEN_EXTENT_CONTROL +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x00000003L +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0x0000000CL +//PA_SC_TILE_STEERING_OVERRIDE +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT 0xc +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT 0x10 +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT 0x14 +#define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK 0x00003000L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK 0x00030000L +#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK 0x00300000L +//PA_SC_CLIPRECT_0_EXT +#define PA_SC_CLIPRECT_0_EXT__BR_X_EXT__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_EXT__BR_Y_EXT__SHIFT 0x2 +#define PA_SC_CLIPRECT_0_EXT__TL_X_EXT__SHIFT 0x4 +#define PA_SC_CLIPRECT_0_EXT__TL_Y_EXT__SHIFT 0x6 +#define PA_SC_CLIPRECT_0_EXT__BR_X_EXT_MASK 0x00000003L +#define PA_SC_CLIPRECT_0_EXT__BR_Y_EXT_MASK 0x0000000CL +#define PA_SC_CLIPRECT_0_EXT__TL_X_EXT_MASK 0x00000030L +#define PA_SC_CLIPRECT_0_EXT__TL_Y_EXT_MASK 0x000000C0L +//PA_SC_CLIPRECT_1_EXT +#define PA_SC_CLIPRECT_1_EXT__BR_X_EXT__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_EXT__BR_Y_EXT__SHIFT 0x2 +#define PA_SC_CLIPRECT_1_EXT__TL_X_EXT__SHIFT 0x4 +#define PA_SC_CLIPRECT_1_EXT__TL_Y_EXT__SHIFT 0x6 +#define PA_SC_CLIPRECT_1_EXT__BR_X_EXT_MASK 0x00000003L +#define PA_SC_CLIPRECT_1_EXT__BR_Y_EXT_MASK 0x0000000CL +#define PA_SC_CLIPRECT_1_EXT__TL_X_EXT_MASK 0x00000030L +#define PA_SC_CLIPRECT_1_EXT__TL_Y_EXT_MASK 0x000000C0L +//PA_SC_CLIPRECT_2_EXT +#define PA_SC_CLIPRECT_2_EXT__BR_X_EXT__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_EXT__BR_Y_EXT__SHIFT 0x2 +#define PA_SC_CLIPRECT_2_EXT__TL_X_EXT__SHIFT 0x4 +#define PA_SC_CLIPRECT_2_EXT__TL_Y_EXT__SHIFT 0x6 +#define PA_SC_CLIPRECT_2_EXT__BR_X_EXT_MASK 0x00000003L +#define PA_SC_CLIPRECT_2_EXT__BR_Y_EXT_MASK 0x0000000CL +#define PA_SC_CLIPRECT_2_EXT__TL_X_EXT_MASK 0x00000030L +#define PA_SC_CLIPRECT_2_EXT__TL_Y_EXT_MASK 0x000000C0L +//PA_SC_CLIPRECT_3_EXT +#define PA_SC_CLIPRECT_3_EXT__BR_X_EXT__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_EXT__BR_Y_EXT__SHIFT 0x2 +#define PA_SC_CLIPRECT_3_EXT__TL_X_EXT__SHIFT 0x4 +#define PA_SC_CLIPRECT_3_EXT__TL_Y_EXT__SHIFT 0x6 +#define PA_SC_CLIPRECT_3_EXT__BR_X_EXT_MASK 0x00000003L +#define PA_SC_CLIPRECT_3_EXT__BR_Y_EXT_MASK 0x0000000CL +#define PA_SC_CLIPRECT_3_EXT__TL_X_EXT_MASK 0x00000030L +#define PA_SC_CLIPRECT_3_EXT__TL_Y_EXT_MASK 0x000000C0L +//PA_SC_VRS_OVERRIDE_CNTL +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE__SHIFT 0x0 +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE__SHIFT 0x4 +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE__SHIFT 0xc +#define PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE__SHIFT 0xd +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT 0xe +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_OVERRIDE_RATE_COMBINER_MODE_MASK 0x00000007L +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_RATE_MASK 0x000000F0L +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_SURFACE_ENABLE_MASK 0x00001000L +#define PA_SC_VRS_OVERRIDE_CNTL__RATE_HINT_WRITE_BACK_ENABLE_MASK 0x00002000L +#define PA_SC_VRS_OVERRIDE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK 0x00004000L +//PA_SC_VRS_RATE_FEEDBACK_BASE +#define PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_FEEDBACK_BASE__BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_VRS_RATE_FEEDBACK_BASE_EXT +#define PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_FEEDBACK_BASE_EXT__BASE_256B_MASK 0x000000FFL +//PA_SC_VRS_RATE_FEEDBACK_SIZE_XY +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX__SHIFT 0x0 +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX__SHIFT 0x10 +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__X_MAX_MASK 0x00001FFFL +#define PA_SC_VRS_RATE_FEEDBACK_SIZE_XY__Y_MAX_MASK 0x1FFF0000L +//PA_SC_VRS_INFO +#define PA_SC_VRS_INFO__RATE_SW_MODE__SHIFT 0x0 +#define PA_SC_VRS_INFO__FEEDBACK_SW_MODE__SHIFT 0x3 +#define PA_SC_VRS_INFO__RATE_SW_MODE_MASK 0x00000007L +#define PA_SC_VRS_INFO__FEEDBACK_SW_MODE_MASK 0x00000038L +//PA_SC_VRS_RATE_BASE +#define PA_SC_VRS_RATE_BASE__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_BASE__BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_VRS_RATE_BASE_EXT +#define PA_SC_VRS_RATE_BASE_EXT__BASE_256B__SHIFT 0x0 +#define PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID__SHIFT 0x1c +#define PA_SC_VRS_RATE_BASE_EXT__BASE_256B_MASK 0x000000FFL +#define PA_SC_VRS_RATE_BASE_EXT__TB_SYNC_SIM_ID_MASK 0xF0000000L +//PA_SC_VRS_RATE_SIZE_XY +#define PA_SC_VRS_RATE_SIZE_XY__X_MAX__SHIFT 0x0 +#define PA_SC_VRS_RATE_SIZE_XY__Y_MAX__SHIFT 0x10 +#define PA_SC_VRS_RATE_SIZE_XY__X_MAX_MASK 0x00001FFFL +#define PA_SC_VRS_RATE_SIZE_XY__Y_MAX_MASK 0x1FFF0000L +//CB_RMI_GL2_CACHE_CONTROL +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY__SHIFT 0x2 +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY__SHIFT 0x16 +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_WR_POLICY_MASK 0x0000000CL +#define CB_RMI_GL2_CACHE_CONTROL__COLOR_RD_POLICY_MASK 0x00C00000L +//CB_BLEND_RED +#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 +#define CB_BLEND_RED__BLEND_RED_MASK 0xFFFFFFFFL +//CB_BLEND_GREEN +#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 +#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xFFFFFFFFL +//CB_BLEND_BLUE +#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 +#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xFFFFFFFFL +//CB_BLEND_ALPHA +#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 +#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xFFFFFFFFL +//PA_CL_GB_VERT_CLIP_ADJ +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_VERT_DISC_ADJ +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_CLIP_ADJ +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_GB_HORZ_DISC_ADJ +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_1 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_1 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_1 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_1 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_1 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_1 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_1 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_1 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_2 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_2 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_2 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_2 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_2 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_2 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_2 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_2 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_3 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_3 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_3 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_3 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_3 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_3 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_3 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_3 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_4 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_4 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_4 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_4 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_4 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_4 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_4 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_4 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_5 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_5 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_5 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_5 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_5 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_5 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_5 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_5 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_6 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_6 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_6 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_6 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_6 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_6 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_6 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_6 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_7 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_7 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_7 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_7 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_7 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_7 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_7 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_7 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_8 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_8 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_8 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_8 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_8 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_8 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_8 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_8 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_9 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_9 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_9 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_9 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_9 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_9 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_9 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_9 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_10 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_10 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_10 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_10 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_10 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_10 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_10 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_10 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_11 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_11 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_11 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_11 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_11 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_11 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_11 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_11 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_12 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_12 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_12 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_12 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_12 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_12 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_12 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_12 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_13 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_13 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_13 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_13 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_13 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_13 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_13 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_13 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_14 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_14 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_14 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_14 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_14 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_14 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_14 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_14 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XSCALE_15 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_XOFFSET_15 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YSCALE_15 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_YOFFSET_15 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZSCALE_15 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xFFFFFFFFL +//PA_CL_VPORT_ZOFFSET_15 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMIN_15 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xFFFFFFFFL +//PA_SC_VPORT_ZMAX_15 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xFFFFFFFFL +//SPI_PS_IN_CONTROL +#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe +#define SPI_PS_IN_CONTROL__PS_W32_EN__SHIFT 0xf +#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x00000040L +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x00004000L +#define SPI_PS_IN_CONTROL__PS_W32_EN_MASK 0x00008000L +//SPI_INTERP_CONTROL_0 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x00000001L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x00000002L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x0000001CL +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0x000000E0L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x00000700L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x00003800L +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x00004000L +//SPI_SHADER_IDX_FORMAT +#define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_IDX_FORMAT__IDX0_EXPORT_FORMAT_MASK 0x0000000FL +//SPI_SHADER_POS_FORMAT +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0x0000F000L +#define SPI_SHADER_POS_FORMAT__POS4_EXPORT_FORMAT_MASK 0x000F0000L +//SPI_SHADER_Z_FORMAT +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0x0000000FL +//SPI_SHADER_COL_FORMAT +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0x0000000FL +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0x000000F0L +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0x00000F00L +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0x0000F000L +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0x000F0000L +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0x00F00000L +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0x0F000000L +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xF0000000L +//SPI_BARYC_CNTL +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x00000001L +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x00000010L +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x00000100L +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x00001000L +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x00030000L +#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x00100000L +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x01000000L +//SPI_PS_INPUT_ENA +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ENA__COVERAGE_TO_SHADER_SELECT__SHIFT 0x10 +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x00008000L +#define SPI_PS_INPUT_ENA__COVERAGE_TO_SHADER_SELECT_MASK 0x00030000L +//SPI_PS_INPUT_ADDR +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x00000001L +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x00000002L +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x00000004L +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x00000008L +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x00000010L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x00000020L +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x00000040L +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x00000080L +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x00000100L +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x00000200L +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x00000400L +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x00000800L +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x00001000L +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x00002000L +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x00004000L +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x00008000L +//SPI_PS_INPUT_CNTL_0 +#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_0__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_0__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_0__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_1 +#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_1__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_1__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_1__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_2 +#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_2__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_2__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_2__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_3 +#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_3__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_3__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_3__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_4 +#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_4__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_4__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_4__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_5 +#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_5__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_5__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_5__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_6 +#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_6__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_6__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_6__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_7 +#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_7__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_7__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_7__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_8 +#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_8__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_8__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_8__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_9 +#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_9__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_9__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_9__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_10 +#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_10__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_10__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_10__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_11 +#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_11__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_11__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_11__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_12 +#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_12__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_12__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_12__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_13 +#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_13__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_13__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_13__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_14 +#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_14__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_14__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_14__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_15 +#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_15__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_15__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_15__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_16 +#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_16__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_16__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_16__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_17 +#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_17__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_17__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_17__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_18 +#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_18__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_18__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_18__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_19 +#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_19__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_19__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_19__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x00020000L +#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x00800000L +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_20 +#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_20__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_20__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_20__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_21 +#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_21__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_21__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_21__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_22 +#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_22__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_22__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_22__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_23 +#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_23__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_23__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_23__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_24 +#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_24__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_24__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_24__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_25 +#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_25__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_25__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_25__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_26 +#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_26__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_26__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_26__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_27 +#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_27__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_27__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_27__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_28 +#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_28__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_28__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_28__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_29 +#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_29__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_29__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_29__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_30 +#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_30__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_30__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_30__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x02000000L +//SPI_PS_INPUT_CNTL_31 +#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR__SHIFT 0xb +#define SPI_PS_INPUT_CNTL_31__PRIM_ATTR__SHIFT 0xc +#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x0000003FL +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x00000300L +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x00000400L +#define SPI_PS_INPUT_CNTL_31__ROTATE_PC_PTR_MASK 0x00000800L +#define SPI_PS_INPUT_CNTL_31__PRIM_ATTR_MASK 0x00001000L +#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x00040000L +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x00080000L +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x00100000L +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x00600000L +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x01000000L +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x02000000L +//SPI_BARYC_SSAA_CNTL +#define SPI_BARYC_SSAA_CNTL__CENTER_SSAA_MODE__SHIFT 0x0 +#define SPI_BARYC_SSAA_CNTL__CENTROID_SSAA_MODE__SHIFT 0x1 +#define SPI_BARYC_SSAA_CNTL__COVERED_CENTROID_IS_CENTER__SHIFT 0x2 +#define SPI_BARYC_SSAA_CNTL__CENTER_SSAA_MODE_MASK 0x00000001L +#define SPI_BARYC_SSAA_CNTL__CENTROID_SSAA_MODE_MASK 0x00000002L +#define SPI_BARYC_SSAA_CNTL__COVERED_CENTROID_IS_CENTER_MASK 0x00000004L +//SPI_TMPRING_SIZE +#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define SPI_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x3FFFF000L +//SPI_GFX_SCRATCH_BASE_LO +#define SPI_GFX_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define SPI_GFX_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//SPI_GFX_SCRATCH_BASE_HI +#define SPI_GFX_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define SPI_GFX_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL +//SX_PS_DOWNCONVERT_CONTROL +#define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE__SHIFT 0x0 +#define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE__SHIFT 0x1 +#define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE__SHIFT 0x2 +#define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE__SHIFT 0x3 +#define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE__SHIFT 0x4 +#define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE__SHIFT 0x5 +#define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE__SHIFT 0x6 +#define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE__SHIFT 0x7 +#define SX_PS_DOWNCONVERT_CONTROL__MRT0_FMT_MAPPING_DISABLE_MASK 0x00000001L +#define SX_PS_DOWNCONVERT_CONTROL__MRT1_FMT_MAPPING_DISABLE_MASK 0x00000002L +#define SX_PS_DOWNCONVERT_CONTROL__MRT2_FMT_MAPPING_DISABLE_MASK 0x00000004L +#define SX_PS_DOWNCONVERT_CONTROL__MRT3_FMT_MAPPING_DISABLE_MASK 0x00000008L +#define SX_PS_DOWNCONVERT_CONTROL__MRT4_FMT_MAPPING_DISABLE_MASK 0x00000010L +#define SX_PS_DOWNCONVERT_CONTROL__MRT5_FMT_MAPPING_DISABLE_MASK 0x00000020L +#define SX_PS_DOWNCONVERT_CONTROL__MRT6_FMT_MAPPING_DISABLE_MASK 0x00000040L +#define SX_PS_DOWNCONVERT_CONTROL__MRT7_FMT_MAPPING_DISABLE_MASK 0x00000080L +//SX_PS_DOWNCONVERT +#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 +#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 +#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 +#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc +#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 +#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 +#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 +#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c +#define SX_PS_DOWNCONVERT__MRT0_MASK 0x0000000FL +#define SX_PS_DOWNCONVERT__MRT1_MASK 0x000000F0L +#define SX_PS_DOWNCONVERT__MRT2_MASK 0x00000F00L +#define SX_PS_DOWNCONVERT__MRT3_MASK 0x0000F000L +#define SX_PS_DOWNCONVERT__MRT4_MASK 0x000F0000L +#define SX_PS_DOWNCONVERT__MRT5_MASK 0x00F00000L +#define SX_PS_DOWNCONVERT__MRT6_MASK 0x0F000000L +#define SX_PS_DOWNCONVERT__MRT7_MASK 0xF0000000L +//SX_BLEND_OPT_EPSILON +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0x0000000FL +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0x000000F0L +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0x00000F00L +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0x0000F000L +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0x000F0000L +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0x00F00000L +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0x0F000000L +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xF0000000L +//SX_BLEND_OPT_CONTROL +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x00000001L +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x00000002L +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x00000010L +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x00000020L +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x00000100L +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x00000200L +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x00001000L +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x00002000L +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x00010000L +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x00020000L +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x00100000L +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x00200000L +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x01000000L +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x02000000L +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000L +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000L +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000L +//SX_MRT0_BLEND_OPT +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT1_BLEND_OPT +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT2_BLEND_OPT +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT3_BLEND_OPT +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT4_BLEND_OPT +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT5_BLEND_OPT +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT6_BLEND_OPT +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//SX_MRT7_BLEND_OPT +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x00000007L +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x00000070L +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x00000700L +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x00070000L +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x00700000L +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x07000000L +//CB_BLEND0_CONTROL +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND1_CONTROL +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND2_CONTROL +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND3_CONTROL +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND4_CONTROL +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND5_CONTROL +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND6_CONTROL +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//CB_BLEND7_CONTROL +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x0000001FL +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0x000000E0L +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x00001F00L +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x001F0000L +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0x00E00000L +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1F000000L +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000L +#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000L +#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000L +//PA_CL_POINT_X_RAD +#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_Y_RAD +#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_SIZE +#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xFFFFFFFFL +//PA_CL_POINT_CULL_RAD +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xFFFFFFFFL +//GE_MAX_OUTPUT_PER_SUBGROUP +#define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP__SHIFT 0x0 +#define GE_MAX_OUTPUT_PER_SUBGROUP__MAX_VERTS_PER_SUBGROUP_MASK 0x000003FFL +//PA_CL_CLIP_CNTL +#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 +#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 +#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd +#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b +#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA__SHIFT 0x1c +#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x00000001L +#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x00000002L +#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x00000004L +#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x00000008L +#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x00000010L +#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x00000020L +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x00002000L +#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0x0000C000L +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x00010000L +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x00020000L +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x00040000L +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x00080000L +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x00100000L +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x00200000L +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x00400000L +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x01000000L +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x02000000L +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x04000000L +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x08000000L +#define PA_CL_CLIP_CNTL__ZCLIP_PROG_NEAR_ENA_MASK 0x10000000L +//PA_CL_VTE_CNTL +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x00000001L +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x00000002L +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x00000004L +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x00000008L +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x00000010L +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x00000020L +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100L +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200L +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x00000400L +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x00000800L +//PA_CL_VS_OUT_CNTL +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1b +#define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE__SHIFT 0x1c +#define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER__SHIFT 0x1d +#define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER__SHIFT 0x1e +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x00000001L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x00000002L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x00000004L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x00000008L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x00000010L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x00000020L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x00000040L +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x00000080L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x00000100L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x00000200L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x00000400L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x00000800L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x00001000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x00002000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x00004000L +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x00008000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x00010000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x00020000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x00040000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x00080000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x00100000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x00200000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x00400000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x00800000L +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x01000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x08000000L +#define PA_CL_VS_OUT_CNTL__USE_VTX_VRS_RATE_MASK 0x10000000L +#define PA_CL_VS_OUT_CNTL__BYPASS_VTX_RATE_COMBINER_MASK 0x20000000L +#define PA_CL_VS_OUT_CNTL__BYPASS_PRIM_RATE_COMBINER_MASK 0x40000000L +//PA_SU_SC_MODE_CNTL +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF__SHIFT 0x16 +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION__SHIFT 0x17 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x00000001L +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x00000002L +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x00000004L +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x00000018L +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0x000000E0L +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x00000700L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x00000800L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x00001000L +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x00002000L +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x00010000L +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x00080000L +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x00100000L +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x00200000L +#define PA_SU_SC_MODE_CNTL__RIGHT_TRIANGLE_ALTERNATE_GRADIENT_REF_MASK 0x00400000L +#define PA_SU_SC_MODE_CNTL__NEW_QUAD_DECOMPOSITION_MASK 0x00800000L +//PA_CL_NANINF_CNTL +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x00000001L +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x00000002L +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x00000004L +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x00000008L +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x00000010L +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x00000020L +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x00000040L +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x00000080L +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x00000100L +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x00000200L +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x00000400L +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x00000800L +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x00001000L +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x00002000L +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x00004000L +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x00100000L +//PA_SU_LINE_STIPPLE_CNTL +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x00000003L +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x00000004L +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x00000008L +//PA_SU_LINE_STIPPLE_SCALE +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xFFFFFFFFL +//PA_SU_PRIM_FILTER_CNTL +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000001L +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x00000010L +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x00000020L +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x00000040L +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x00000080L +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0x0000FF00L +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000L +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000L +//PA_SU_SMALL_PRIM_FILTER_CNTL +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE__SHIFT 0x0 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE__SHIFT 0x6 +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L +#define PA_SU_SMALL_PRIM_FILTER_CNTL__SC_1XMSAA_COMPATIBLE_DISABLE_MASK 0x00000040L +//PA_CL_NGG_CNTL +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF__SHIFT 0x0 +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA__SHIFT 0x1 +#define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH__SHIFT 0x2 +#define PA_CL_NGG_CNTL__VERTEX_REUSE_OFF_MASK 0x00000001L +#define PA_CL_NGG_CNTL__INDEX_BUF_EDGE_FLAG_ENA_MASK 0x00000002L +#define PA_CL_NGG_CNTL__VERTEX_REUSE_DEPTH_MASK 0x000003FCL +//PA_SU_OVER_RASTERIZATION_CNTL +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES__SHIFT 0x0 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES__SHIFT 0x1 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS__SHIFT 0x2 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES__SHIFT 0x3 +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW__SHIFT 0x4 +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_TRIANGLES_MASK 0x00000001L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_LINES_MASK 0x00000002L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_POINTS_MASK 0x00000004L +#define PA_SU_OVER_RASTERIZATION_CNTL__DISCARD_0_AREA_RECTANGLES_MASK 0x00000008L +#define PA_SU_OVER_RASTERIZATION_CNTL__USE_PROVOKING_ZW_MASK 0x00000010L +//PA_STEREO_CNTL +#define PA_STEREO_CNTL__STEREO_MODE__SHIFT 0x1 +#define PA_STEREO_CNTL__RT_SLICE_MODE__SHIFT 0x5 +#define PA_STEREO_CNTL__RT_SLICE_OFFSET__SHIFT 0x8 +#define PA_STEREO_CNTL__VP_ID_MODE__SHIFT 0x10 +#define PA_STEREO_CNTL__VP_ID_OFFSET__SHIFT 0x13 +#define PA_STEREO_CNTL__STEREO_MODE_MASK 0x0000001EL +#define PA_STEREO_CNTL__RT_SLICE_MODE_MASK 0x000000E0L +#define PA_STEREO_CNTL__RT_SLICE_OFFSET_MASK 0x00000F00L +#define PA_STEREO_CNTL__VP_ID_MODE_MASK 0x00070000L +#define PA_STEREO_CNTL__VP_ID_OFFSET_MASK 0x00780000L +//PA_STATE_STEREO_X +#define PA_STATE_STEREO_X__STEREO_X_OFFSET__SHIFT 0x0 +#define PA_STATE_STEREO_X__STEREO_X_OFFSET_MASK 0xFFFFFFFFL +//PA_CL_VRS_CNTL +#define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE__SHIFT 0x0 +#define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE__SHIFT 0x3 +#define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE__SHIFT 0x6 +#define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE__SHIFT 0x9 +#define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK__SHIFT 0xd +#define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO__SHIFT 0xe +#define PA_CL_VRS_CNTL__SAMPLE_COVERAGE_ENCODING__SHIFT 0xf +#define PA_CL_VRS_CNTL__VERTEX_RATE_COMBINER_MODE_MASK 0x00000007L +#define PA_CL_VRS_CNTL__PRIMITIVE_RATE_COMBINER_MODE_MASK 0x00000038L +#define PA_CL_VRS_CNTL__HTILE_RATE_COMBINER_MODE_MASK 0x000001C0L +#define PA_CL_VRS_CNTL__SAMPLE_ITER_COMBINER_MODE_MASK 0x00000E00L +#define PA_CL_VRS_CNTL__EXPOSE_VRS_PIXELS_MASK_MASK 0x00002000L +#define PA_CL_VRS_CNTL__CMASK_RATE_HINT_FORCE_ZERO_MASK 0x00004000L +#define PA_CL_VRS_CNTL__SAMPLE_COVERAGE_ENCODING_MASK 0x00008000L +//CB_TARGET_MASK +#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 +#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 +#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc +#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 +#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 +#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 +#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c +#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0x0000000FL +#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0x000000F0L +#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0x00000F00L +#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0x0000F000L +#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0x000F0000L +#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0x00F00000L +#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0x0F000000L +#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xF0000000L +//CB_SHADER_MASK +#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 +#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 +#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc +#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 +#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 +#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 +#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c +#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0x0000000FL +#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0x000000F0L +#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0x00000F00L +#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0x0000F000L +#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0x000F0000L +#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0x00F00000L +#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0x0F000000L +#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xF0000000L +//CB_COLOR_CONTROL +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 +#define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE__SHIFT 0x1 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 +#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 +#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x00000001L +#define CB_COLOR_CONTROL__ENABLE_1FRAG_PS_INVOKE_MASK 0x00000002L +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x00000008L +#define CB_COLOR_CONTROL__MODE_MASK 0x00000070L +#define CB_COLOR_CONTROL__ROP3_MASK 0x00FF0000L +//PA_SU_POINT_SIZE +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0x0000FFFFL +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xFFFF0000L +//PA_SU_POINT_MINMAX +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0x0000FFFFL +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xFFFF0000L +//PA_SU_LINE_CNTL +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 +#define PA_SU_LINE_CNTL__WIDTH_MASK 0x0000FFFFL +//PA_SC_LINE_STIPPLE +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0x0000FFFFL +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0x00FF0000L +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000L +//PA_SC_LINE_STIPPLE_RESET +#define PA_SC_LINE_STIPPLE_RESET__AUTO_RESET_CNTL__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE_RESET__AUTO_RESET_CNTL_MASK 0x00000003L +//PA_SC_MODE_CNTL_0 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE__SHIFT 0x5 +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB__SHIFT 0x6 +#define PA_SC_MODE_CNTL_0__IMPLICIT_VPORT_SCISSOR_ENABLE__SHIFT 0x7 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x00000002L +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x00000004L +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x00000008L +#define PA_SC_MODE_CNTL_0__ALTERNATE_RBS_PER_TILE_MASK 0x00000020L +#define PA_SC_MODE_CNTL_0__COARSE_TILE_STARTS_ON_EVEN_RB_MASK 0x00000040L +#define PA_SC_MODE_CNTL_0__IMPLICIT_VPORT_SCISSOR_ENABLE_MASK 0x00000080L +//PA_SC_MODE_CNTL_1 +#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c +#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x00000001L +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x00000002L +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x00000004L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x00000008L +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x00000070L +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x00000080L +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x00000100L +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x00000200L +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x00000400L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x00000800L +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x00001000L +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x00002000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x00004000L +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x00008000L +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x00010000L +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x00020000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x00040000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x00080000L +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0x00F00000L +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x01000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x02000000L +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x04000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x08000000L +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000L +//GE_SE_ENHANCE +#define GE_SE_ENHANCE__MISC__SHIFT 0x0 +#define GE_SE_ENHANCE__MISC_MASK 0xFFFFFFFFL +//VGT_REUSE_OFF +#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 +#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x00000001L +//VGT_DRAW_PAYLOAD_CNTL +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX__SHIFT 0x1 +#define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD__SHIFT 0x3 +#define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP__SHIFT 0x4 +#define VGT_DRAW_PAYLOAD_CNTL__UNUSED__SHIFT 0x5 +#define VGT_DRAW_PAYLOAD_CNTL__EN_VRS_RATE__SHIFT 0x6 +#define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L +#define VGT_DRAW_PAYLOAD_CNTL__EN_PRIM_PAYLOAD_MASK 0x00000008L +#define VGT_DRAW_PAYLOAD_CNTL__EN_DRAW_VP_MASK 0x00000010L +#define VGT_DRAW_PAYLOAD_CNTL__UNUSED_MASK 0x00000020L +#define VGT_DRAW_PAYLOAD_CNTL__EN_VRS_RATE_MASK 0x00000040L +//DB_HTILE_SURFACE +#define DB_HTILE_SURFACE__RESERVED_FIELD_1__SHIFT 0x0 +#define DB_HTILE_SURFACE__RESERVED_FIELD_2__SHIFT 0x2 +#define DB_HTILE_SURFACE__RESERVED_FIELD_3__SHIFT 0x3 +#define DB_HTILE_SURFACE__RESERVED_FIELD_4__SHIFT 0x4 +#define DB_HTILE_SURFACE__RESERVED_FIELD_5__SHIFT 0xa +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 +#define DB_HTILE_SURFACE__RESERVED_FIELD_6__SHIFT 0x11 +#define DB_HTILE_SURFACE__RESERVED_FIELD_1_MASK 0x00000001L +#define DB_HTILE_SURFACE__RESERVED_FIELD_2_MASK 0x00000004L +#define DB_HTILE_SURFACE__RESERVED_FIELD_3_MASK 0x00000008L +#define DB_HTILE_SURFACE__RESERVED_FIELD_4_MASK 0x000003F0L +#define DB_HTILE_SURFACE__RESERVED_FIELD_5_MASK 0x0000FC00L +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x00010000L +#define DB_HTILE_SURFACE__RESERVED_FIELD_6_MASK 0x00020000L +//DB_SRESULTS_COMPARE_STATE0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0x000FF000L +//DB_SRESULTS_COMPARE_STATE1 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x00000007L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0x00000FF0L +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0x000FF000L +//VGT_GS_MAX_VERT_OUT +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x000007FFL +//VGT_GS_INSTANCE_CNT +#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 +#define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE__SHIFT 0x1f +#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x00000001L +#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x000000FCL +#define VGT_GS_INSTANCE_CNT__EN_MAX_VERT_OUT_PER_GS_INSTANCE_MASK 0x80000000L +//GE_NGG_SUBGRP_CNTL +#define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR__SHIFT 0x0 +#define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP__SHIFT 0x9 +#define GE_NGG_SUBGRP_CNTL__PRIM_AMP_FACTOR_MASK 0x000001FFL +#define GE_NGG_SUBGRP_CNTL__THDS_PER_SUBGRP_MASK 0x0003FE00L +//PA_SU_POLY_OFFSET_DB_FMT_CNTL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0x000000FFL +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x00000100L +//PA_SU_POLY_OFFSET_CLAMP +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_SCALE +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_FRONT_OFFSET +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_SCALE +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xFFFFFFFFL +//PA_SU_POLY_OFFSET_BACK_OFFSET +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xFFFFFFFFL +//PA_SC_HIZ_INFO +#define PA_SC_HIZ_INFO__SURFACE_ENABLE__SHIFT 0x0 +#define PA_SC_HIZ_INFO__FORMAT__SHIFT 0x1 +#define PA_SC_HIZ_INFO__SW_MODE__SHIFT 0x2 +#define PA_SC_HIZ_INFO__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x19 +#define PA_SC_HIZ_INFO__SURFACE_ENABLE_MASK 0x00000001L +#define PA_SC_HIZ_INFO__FORMAT_MASK 0x00000002L +#define PA_SC_HIZ_INFO__SW_MODE_MASK 0x0000001CL +#define PA_SC_HIZ_INFO__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x02000000L +//PA_SC_HIS_INFO +#define PA_SC_HIS_INFO__SURFACE_ENABLE__SHIFT 0x0 +#define PA_SC_HIS_INFO__SW_MODE__SHIFT 0x1 +#define PA_SC_HIS_INFO__SURFACE_ENABLE_MASK 0x00000001L +#define PA_SC_HIS_INFO__SW_MODE_MASK 0x0000000EL +//PA_SC_HIZ_BASE +#define PA_SC_HIZ_BASE__BASE_256B__SHIFT 0x0 +#define PA_SC_HIZ_BASE__BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_HIZ_BASE_EXT +#define PA_SC_HIZ_BASE_EXT__BASE_256B__SHIFT 0x0 +#define PA_SC_HIZ_BASE_EXT__BASE_256B_MASK 0x000000FFL +//PA_SC_HIZ_SIZE_XY +#define PA_SC_HIZ_SIZE_XY__X_MAX__SHIFT 0x0 +#define PA_SC_HIZ_SIZE_XY__Y_MAX__SHIFT 0x10 +#define PA_SC_HIZ_SIZE_XY__X_MAX_MASK 0x00001FFFL +#define PA_SC_HIZ_SIZE_XY__Y_MAX_MASK 0x1FFF0000L +//PA_SC_HIS_BASE +#define PA_SC_HIS_BASE__BASE_256B__SHIFT 0x0 +#define PA_SC_HIS_BASE__BASE_256B_MASK 0xFFFFFFFFL +//PA_SC_HIS_BASE_EXT +#define PA_SC_HIS_BASE_EXT__BASE_256B__SHIFT 0x0 +#define PA_SC_HIS_BASE_EXT__BASE_256B_MASK 0x000000FFL +//PA_SC_HIS_SIZE_XY +#define PA_SC_HIS_SIZE_XY__X_MAX__SHIFT 0x0 +#define PA_SC_HIS_SIZE_XY__Y_MAX__SHIFT 0x10 +#define PA_SC_HIS_SIZE_XY__X_MAX_MASK 0x00001FFFL +#define PA_SC_HIS_SIZE_XY__Y_MAX_MASK 0x1FFF0000L +//PA_SC_BINNER_OUTPUT_TIMEOUT_CNTL +#define PA_SC_BINNER_OUTPUT_TIMEOUT_CNTL__THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_OUTPUT_TIMEOUT_CNTL__THRESHOLD_MASK 0x0000FFFFL +//PA_SC_BINNER_DYNAMIC_BATCH_LIMIT +#define PA_SC_BINNER_DYNAMIC_BATCH_LIMIT__LIMIT__SHIFT 0x0 +#define PA_SC_BINNER_DYNAMIC_BATCH_LIMIT__LIMIT_MASK 0x000007FFL +//PA_SC_HISZ_CONTROL +#define PA_SC_HISZ_CONTROL__ROUND__SHIFT 0x0 +#define PA_SC_HISZ_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0x3 +#define PA_SC_HISZ_CONTROL__ROUND_MASK 0x00000007L +#define PA_SC_HISZ_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x00000018L +//PA_SC_HISZ_RENDER_OVERRIDE +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_HIS_ENABLE__SHIFT 0x2 +#define PA_SC_HISZ_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x4 +#define PA_SC_HISZ_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x5 +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0x6 +#define PA_SC_HISZ_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x8 +#define PA_SC_HISZ_RENDER_OVERRIDE__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0x9 +#define PA_SC_HISZ_RENDER_OVERRIDE__PRESERVE_ZRANGE__SHIFT 0xa +#define PA_SC_HISZ_RENDER_OVERRIDE__DISABLE_FAST_PASS__SHIFT 0xb +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x00000003L +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_HIS_ENABLE_MASK 0x0000000CL +#define PA_SC_HISZ_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x00000010L +#define PA_SC_HISZ_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x00000020L +#define PA_SC_HISZ_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x000000C0L +#define PA_SC_HISZ_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x00000100L +#define PA_SC_HISZ_RENDER_OVERRIDE__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x00000200L +#define PA_SC_HISZ_RENDER_OVERRIDE__PRESERVE_ZRANGE_MASK 0x00000400L +#define PA_SC_HISZ_RENDER_OVERRIDE__DISABLE_FAST_PASS_MASK 0x00000800L +//PA_SC_LINE_CNTL +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc +#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION__SHIFT 0xd +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x00000200L +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x00000400L +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x00000800L +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x00001000L +#define PA_SC_LINE_CNTL__EXTRA_DX_DY_PRECISION_MASK 0x00002000L +//PA_SC_AA_CONFIG +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 +#define PA_SC_AA_CONFIG__PS_ITER_SAMPLES__SHIFT 0x1e +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x00000007L +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x00000010L +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x00700000L +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x03000000L +#define PA_SC_AA_CONFIG__PS_ITER_SAMPLES_MASK 0xC0000000L +//PA_SU_VTX_CNTL +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x00000001L +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x00000006L +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x00000038L +//PA_SC_CENTROID_PRIORITY_0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xF0000000L +//PA_SC_CENTROID_PRIORITY_1 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0x0000000FL +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0x000000F0L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0x00000F00L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0x0000F000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0x000F0000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0x00F00000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0x0F000000L +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xF0000000L +//PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0x0000000FL +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0x000000F0L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0x00000F00L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0x0000F000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0x000F0000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0x00F00000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0x0F000000L +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xF0000000L +//PA_SC_AA_MASK_X0Y0_X1Y0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xFFFF0000L +//PA_SC_AA_MASK_X0Y1_X1Y1 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0x0000FFFFL +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xFFFF0000L +//PA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER +#define PA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_OUTPUT_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_BINNER_CNTL_0 +#define PA_SC_BINNER_CNTL_0__BINNING_MODE__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X__SHIFT 0x2 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y__SHIFT 0x3 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND__SHIFT 0x4 +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND__SHIFT 0x7 +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN__SHIFT 0xa +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN__SHIFT 0xd +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM__SHIFT 0x12 +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH__SHIFT 0x13 +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION__SHIFT 0x1b +#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1c +#define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE__SHIFT 0x1d +#define PA_SC_BINNER_CNTL_0__RESERVED_31__SHIFT 0x1f +#define PA_SC_BINNER_CNTL_0__BINNING_MODE_MASK 0x00000003L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_MASK 0x00000004L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_MASK 0x00000008L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_X_EXTEND_MASK 0x00000070L +#define PA_SC_BINNER_CNTL_0__BIN_SIZE_Y_EXTEND_MASK 0x00000380L +#define PA_SC_BINNER_CNTL_0__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L +#define PA_SC_BINNER_CNTL_0__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L +#define PA_SC_BINNER_CNTL_0__DISABLE_START_OF_PRIM_MASK 0x00040000L +#define PA_SC_BINNER_CNTL_0__FPOVS_PER_BATCH_MASK 0x07F80000L +#define PA_SC_BINNER_CNTL_0__OPTIMAL_BIN_SELECTION_MASK 0x08000000L +#define PA_SC_BINNER_CNTL_0__FLUSH_ON_BINNING_TRANSITION_MASK 0x10000000L +#define PA_SC_BINNER_CNTL_0__BIN_MAPPING_MODE_MASK 0x60000000L +#define PA_SC_BINNER_CNTL_0__RESERVED_31_MASK 0x80000000L +//PA_SC_BINNER_CNTL_1 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH__SHIFT 0x10 +#define PA_SC_BINNER_CNTL_1__MAX_ALLOC_COUNT_MASK 0x0000FFFFL +#define PA_SC_BINNER_CNTL_1__MAX_PRIM_PER_BATCH_MASK 0xFFFF0000L +//PA_SC_BINNER_CNTL_2 +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X__SHIFT 0x1 +#define PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT 0x2 +#define PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW__SHIFT 0x3 +#define PA_SC_BINNER_CNTL_2__RESERVED_LIGHT_SHAFT_DRAW_CALL_LIMIT__SHIFT 0x4 +#define PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN__SHIFT 0x7 +#define PA_SC_BINNER_CNTL_2__ZPP_ENABLED__SHIFT 0xb +#define PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED__SHIFT 0xc +#define PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD__SHIFT 0xd +#define PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION__SHIFT 0x15 +#define PA_SC_BINNER_CNTL_2__SBB_ENABLE__SHIFT 0x16 +#define PA_SC_BINNER_CNTL_2__ENABLE_PING_PONG_BIN_ORDER__SHIFT 0x17 +#define PA_SC_BINNER_CNTL_2__PING_PONG_BIN_ORDER_FLIP__SHIFT 0x18 +#define PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT__SHIFT 0x1a +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_X_MULT_BY_1P5X_MASK 0x00000001L +#define PA_SC_BINNER_CNTL_2__BIN_SIZE_Y_MULT_BY_1P5X_MASK 0x00000002L +#define PA_SC_BINNER_CNTL_2__ENABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK 0x00000004L +#define PA_SC_BINNER_CNTL_2__DUAL_LIGHT_SHAFT_IN_DRAW_MASK 0x00000008L +#define PA_SC_BINNER_CNTL_2__RESERVED_LIGHT_SHAFT_DRAW_CALL_LIMIT_MASK 0x00000070L +#define PA_SC_BINNER_CNTL_2__CONTEXT_DONE_EVENTS_PER_BIN_MASK 0x00000780L +#define PA_SC_BINNER_CNTL_2__ZPP_ENABLED_MASK 0x00000800L +#define PA_SC_BINNER_CNTL_2__ZPP_OPTIMIZATION_ENABLED_MASK 0x00001000L +#define PA_SC_BINNER_CNTL_2__ZPP_AREA_THRESHOLD_MASK 0x001FE000L +#define PA_SC_BINNER_CNTL_2__DISABLE_NOPCEXPORT_BREAKBATCH_CONDITION_MASK 0x00200000L +#define PA_SC_BINNER_CNTL_2__SBB_ENABLE_MASK 0x00400000L +#define PA_SC_BINNER_CNTL_2__ENABLE_PING_PONG_BIN_ORDER_MASK 0x00800000L +#define PA_SC_BINNER_CNTL_2__PING_PONG_BIN_ORDER_FLIP_MASK 0x03000000L +#define PA_SC_BINNER_CNTL_2__LIGHT_SHAFT_DRAW_CALL_LIMIT_MASK 0x7C000000L +//PA_SC_NGG_MODE_CNTL +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE__SHIFT 0x0 +#define PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT__SHIFT 0xc +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC__SHIFT 0xd +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT 0xe +#define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE__SHIFT 0x10 +#define PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT 0x18 +#define PA_SC_NGG_MODE_CNTL__MAX_DEALLOCS_IN_WAVE_MASK 0x000007FFL +#define PA_SC_NGG_MODE_CNTL__DISABLE_FPOG_AND_DEALLOC_CONFLICT_MASK 0x00001000L +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_DEALLOC_MASK 0x00002000L +#define PA_SC_NGG_MODE_CNTL__DISABLE_MAX_ATTRIBUTES_MASK 0x00004000L +#define PA_SC_NGG_MODE_CNTL__MAX_FPOVS_IN_WAVE_MASK 0x00FF0000L +#define PA_SC_NGG_MODE_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK 0xFF000000L +//PA_SC_CONSERVATIVE_RASTERIZATION_CNTL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE__SHIFT 0x0 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT__SHIFT 0x1 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE__SHIFT 0x5 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT__SHIFT 0x6 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE__SHIFT 0xa +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT__SHIFT 0xb +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET__SHIFT 0xc +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL__SHIFT 0xd +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL__SHIFT 0xe +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE__SHIFT 0xf +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE__SHIFT 0x10 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x12 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE__SHIFT 0x13 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE__SHIFT 0x14 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE__SHIFT 0x15 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE__SHIFT 0x16 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE__SHIFT 0x17 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE__SHIFT 0x18 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT__SHIFT 0x19 +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT__SHIFT 0x1b +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_ENABLE_MASK 0x00000001L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVER_RAST_SAMPLE_SELECT_MASK 0x0000001EL +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_ENABLE_MASK 0x00000020L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNDER_RAST_SAMPLE_SELECT_MASK 0x000003C0L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PBB_UNCERTAINTY_REGION_ENABLE_MASK 0x00000400L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_EXTENT_MASK 0x00000800L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__ZMM_TRI_OFFSET_MASK 0x00001000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_OVER_RAST_INNER_TO_NORMAL_MASK 0x00002000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OVERRIDE_UNDER_RAST_INNER_TO_NORMAL_MASK 0x00004000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__DEGENERATE_OVERRIDE_INNER_TO_NORMAL_DISABLE_MASK 0x00008000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MODE_MASK 0x00030000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__OUTER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00040000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__INNER_UNCERTAINTY_EDGERULE_OVERRIDE_MASK 0x00080000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__NULL_SQUAD_AA_MASK_ENABLE_MASK 0x00100000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__COVERAGE_AA_MASK_ENABLE_MASK 0x00200000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__PREZ_AA_MASK_ENABLE_MASK 0x00400000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__POSTZ_AA_MASK_ENABLE_MASK 0x00800000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__CENTROID_SAMPLE_OVERRIDE_MASK 0x01000000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_MULT_MASK 0x06000000L +#define PA_SC_CONSERVATIVE_RASTERIZATION_CNTL__UNCERTAINTY_REGION_PBB_MULT_MASK 0x18000000L +//PA_SC_SHADER_CONTROL +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID__SHIFT 0x2 +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION__SHIFT 0x3 +#define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE__SHIFT 0x5 +#define PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD__SHIFT 0x7 +#define PA_SC_SHADER_CONTROL__PS_ITER_SAMPLE__SHIFT 0x8 +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x00000003L +#define PA_SC_SHADER_CONTROL__LOAD_COLLISION_WAVEID_MASK 0x00000004L +#define PA_SC_SHADER_CONTROL__LOAD_INTRAWAVE_COLLISION_MASK 0x00000008L +#define PA_SC_SHADER_CONTROL__WAVE_BREAK_REGION_SIZE_MASK 0x00000060L +#define PA_SC_SHADER_CONTROL__DISABLE_OREO_CONFLICT_QUAD_MASK 0x00000080L +#define PA_SC_SHADER_CONTROL__PS_ITER_SAMPLE_MASK 0x00000100L +//PA_SC_SAMPLE_PROPERTIES +#define PA_SC_SAMPLE_PROPERTIES__MAX_SAMPLE_DIST__SHIFT 0x0 +#define PA_SC_SAMPLE_PROPERTIES__MAX_SAMPLE_DIST_MASK 0x0000000FL +//CB_COLOR0_BASE +#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR0_VIEW +#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR0_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR0_VIEW2 +#define CB_COLOR0_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR0_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR0_ATTRIB +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR0_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR0_FDCC_CONTROL +#define CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR0_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR0_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR0_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR0_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR0_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR0_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR0_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR0_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR0_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR0_ATTRIB2 +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR0_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR0_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR0_ATTRIB3 +#define CB_COLOR0_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR0_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR0_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR0_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR0_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR0_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR0_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR0_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR0_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR0_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR1_BASE +#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR1_VIEW +#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR1_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR1_VIEW2 +#define CB_COLOR1_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR1_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR1_ATTRIB +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR1_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR1_FDCC_CONTROL +#define CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR1_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR1_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR1_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR1_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR1_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR1_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR1_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR1_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR1_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR1_ATTRIB2 +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR1_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR1_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR1_ATTRIB3 +#define CB_COLOR1_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR1_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR1_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR1_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR1_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR1_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR1_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR1_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR1_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR1_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR2_BASE +#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR2_VIEW +#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR2_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR2_VIEW2 +#define CB_COLOR2_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR2_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR2_ATTRIB +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR2_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR2_FDCC_CONTROL +#define CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR2_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR2_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR2_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR2_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR2_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR2_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR2_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR2_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR2_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR2_ATTRIB2 +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR2_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR2_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR2_ATTRIB3 +#define CB_COLOR2_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR2_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR2_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR2_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR2_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR2_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR2_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR2_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR2_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR2_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR3_BASE +#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR3_VIEW +#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR3_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR3_VIEW2 +#define CB_COLOR3_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR3_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR3_ATTRIB +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR3_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR3_FDCC_CONTROL +#define CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR3_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR3_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR3_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR3_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR3_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR3_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR3_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR3_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR3_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR3_ATTRIB2 +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR3_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR3_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR3_ATTRIB3 +#define CB_COLOR3_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR3_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR3_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR3_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR3_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR3_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR3_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR3_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR3_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR3_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR4_BASE +#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR4_VIEW +#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR4_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR4_VIEW2 +#define CB_COLOR4_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR4_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR4_ATTRIB +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR4_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR4_FDCC_CONTROL +#define CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR4_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR4_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR4_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR4_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR4_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR4_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR4_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR4_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR4_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR4_ATTRIB2 +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR4_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR4_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR4_ATTRIB3 +#define CB_COLOR4_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR4_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR4_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR4_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR4_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR4_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR4_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR4_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR4_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR4_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR5_BASE +#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR5_VIEW +#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR5_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR5_VIEW2 +#define CB_COLOR5_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR5_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR5_ATTRIB +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR5_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR5_FDCC_CONTROL +#define CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR5_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR5_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR5_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR5_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR5_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR5_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR5_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR5_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR5_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR5_ATTRIB2 +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR5_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR5_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR5_ATTRIB3 +#define CB_COLOR5_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR5_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR5_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR5_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR5_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR5_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR5_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR5_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR5_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR5_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR6_BASE +#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR6_VIEW +#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR6_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR6_VIEW2 +#define CB_COLOR6_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR6_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR6_ATTRIB +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR6_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR6_FDCC_CONTROL +#define CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR6_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR6_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR6_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR6_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR6_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR6_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR6_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR6_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR6_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR6_ATTRIB2 +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR6_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR6_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR6_ATTRIB3 +#define CB_COLOR6_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR6_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR6_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR6_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR6_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR6_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR6_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR6_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR6_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR6_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR7_BASE +#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE__BASE_256B_MASK 0xFFFFFFFFL +//CB_COLOR7_VIEW +#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xe +#define CB_COLOR7_VIEW__SLICE_START_MASK 0x00003FFFL +#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0x0FFFC000L +//CB_COLOR7_VIEW2 +#define CB_COLOR7_VIEW2__MIP_LEVEL__SHIFT 0x0 +#define CB_COLOR7_VIEW2__MIP_LEVEL_MASK 0x0000001FL +//CB_COLOR7_ATTRIB +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0x0 +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x2 +#define CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX__SHIFT 0x3 +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x00000003L +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x00000004L +#define CB_COLOR7_ATTRIB__FORCE_LIMIT_COLOR_SECTOR_TO_256B_MAX_MASK 0x00000008L +//CB_COLOR7_FDCC_CONTROL +#define CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE__SHIFT 0x18 +#define CB_COLOR7_FDCC_CONTROL__COMPRESSION_MODE__SHIFT 0x1a +#define CB_COLOR7_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE__SHIFT 0x1c +#define CB_COLOR7_FDCC_CONTROL__MAX_COMP_FRAGS__SHIFT 0x1d +#define CB_COLOR7_FDCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0x00000004L +#define CB_COLOR7_FDCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x00000060L +#define CB_COLOR7_FDCC_CONTROL__FRAGMENT_COMPRESS_DISABLE_MASK 0x01000000L +#define CB_COLOR7_FDCC_CONTROL__COMPRESSION_MODE_MASK 0x0C000000L +#define CB_COLOR7_FDCC_CONTROL__ENABLE_MAX_COMP_FRAG_OVERRIDE_MASK 0x10000000L +#define CB_COLOR7_FDCC_CONTROL__MAX_COMP_FRAGS_MASK 0x60000000L +//CB_COLOR7_ATTRIB2 +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT__SHIFT 0x0 +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH__SHIFT 0x10 +#define CB_COLOR7_ATTRIB2__MIP0_HEIGHT_MASK 0x0000FFFFL +#define CB_COLOR7_ATTRIB2__MIP0_WIDTH_MASK 0xFFFF0000L +//CB_COLOR7_ATTRIB3 +#define CB_COLOR7_ATTRIB3__MIP0_DEPTH__SHIFT 0x0 +#define CB_COLOR7_ATTRIB3__COLOR_SW_MODE__SHIFT 0xf +#define CB_COLOR7_ATTRIB3__MAX_MIP__SHIFT 0x13 +#define CB_COLOR7_ATTRIB3__RESOURCE_TYPE__SHIFT 0x18 +#define CB_COLOR7_ATTRIB3__SPECULATIVE_READ__SHIFT 0x1a +#define CB_COLOR7_ATTRIB3__MIP0_DEPTH_MASK 0x00003FFFL +#define CB_COLOR7_ATTRIB3__COLOR_SW_MODE_MASK 0x00038000L +#define CB_COLOR7_ATTRIB3__MAX_MIP_MASK 0x00F80000L +#define CB_COLOR7_ATTRIB3__RESOURCE_TYPE_MASK 0x03000000L +#define CB_COLOR7_ATTRIB3__SPECULATIVE_READ_MASK 0x0C000000L +//CB_COLOR0_BASE_EXT +#define CB_COLOR0_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR1_BASE_EXT +#define CB_COLOR1_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR2_BASE_EXT +#define CB_COLOR2_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR3_BASE_EXT +#define CB_COLOR3_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR4_BASE_EXT +#define CB_COLOR4_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR5_BASE_EXT +#define CB_COLOR5_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR6_BASE_EXT +#define CB_COLOR6_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR7_BASE_EXT +#define CB_COLOR7_BASE_EXT__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE_EXT__BASE_256B_MASK 0x000000FFL +//CB_COLOR0_INFO +#define CB_COLOR0_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR0_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR0_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR0_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR1_INFO +#define CB_COLOR1_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR1_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR1_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR1_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR2_INFO +#define CB_COLOR2_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR2_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR2_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR2_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR3_INFO +#define CB_COLOR3_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR3_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR3_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR3_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR4_INFO +#define CB_COLOR4_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR4_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR4_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR4_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR5_INFO +#define CB_COLOR5_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR5_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR5_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR5_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR6_INFO +#define CB_COLOR6_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR6_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR6_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR6_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_COLOR7_INFO +#define CB_COLOR7_INFO__FORMAT__SHIFT 0x0 +#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR7_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL__SHIFT 0x13 +#define CB_COLOR7_INFO__FORMAT_MASK 0x0000001FL +#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x00000080L +#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x00000700L +#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x00001800L +#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x00008000L +#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x00010000L +#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x00020000L +#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x00040000L +#define CB_COLOR7_INFO__DISABLE_WA_FOR_PARTIAL_TARGET_MASK_ALL_MASK 0x00080000L +//CB_MEM0_INFO +#define CB_MEM0_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM0_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM0_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM0_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM1_INFO +#define CB_MEM1_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM1_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM1_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM1_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM2_INFO +#define CB_MEM2_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM2_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM2_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM2_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM3_INFO +#define CB_MEM3_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM3_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM3_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM3_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM4_INFO +#define CB_MEM4_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM4_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM4_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM4_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM5_INFO +#define CB_MEM5_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM5_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM5_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM5_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM6_INFO +#define CB_MEM6_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM6_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM6_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM6_INFO__TEMPORAL_WRITE_MASK 0x00000038L +//CB_MEM7_INFO +#define CB_MEM7_INFO__TEMPORAL_READ__SHIFT 0x0 +#define CB_MEM7_INFO__TEMPORAL_WRITE__SHIFT 0x3 +#define CB_MEM7_INFO__TEMPORAL_READ_MASK 0x00000007L +#define CB_MEM7_INFO__TEMPORAL_WRITE_MASK 0x00000038L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfvf_padec +//PA_SC_VRS_SURFACE_CNTL +#define PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x6 +#define PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE__SHIFT 0x7 +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE__SHIFT 0x8 +#define PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE__SHIFT 0xd +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE__SHIFT 0xe +#define PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE__SHIFT 0xf +#define PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE__SHIFT 0x10 +#define PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE__SHIFT 0x12 +#define PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS__SHIFT 0x13 +#define PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT__SHIFT 0x1a +#define PA_SC_VRS_SURFACE_CNTL__VRC_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000040L +#define PA_SC_VRS_SURFACE_CNTL__VRS_FEEDBACK_RATE_OVERRIDE_MASK 0x00000080L +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_EVENT_MASK_DISABLE_MASK 0x00001F00L +#define PA_SC_VRS_SURFACE_CNTL__VRC_PREFETCH_DISABLE_MASK 0x00002000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_FLUSH_NO_INV_DISABLE_MASK 0x00004000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_NONSTALLING_FLUSH_DISABLE_MASK 0x00008000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_PARTIAL_FLUSH_DISABLE_MASK 0x00010000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_EOP_SYNC_DISABLE_MASK 0x00040000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_MAX_TAGS_MASK 0x03F80000L +#define PA_SC_VRS_SURFACE_CNTL__VRC_EVICT_POINT_MASK 0xFC000000L +//PA_SC_ENHANCE +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x6 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x7 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0x8 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0x9 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xa +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xb +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xc +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xd +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0xe +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0xf +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x10 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x11 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x12 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x13 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x14 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x15 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x16 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x17 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x19 +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1a +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1b +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE__SHIFT 0x1c +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING__SHIFT 0x1d +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x00000001L +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x00000002L +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x00000004L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x00000008L +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x00000010L +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x00000020L +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x00000040L +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x00000080L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x00000100L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x00000200L +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00000400L +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x00000800L +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x00001000L +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x00002000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x00004000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x00008000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x00010000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x00020000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x00040000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x00080000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x00100000L +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x00200000L +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x00400000L +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x00800000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x02000000L +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x04000000L +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x08000000L +#define PA_SC_ENHANCE__IOO_DISABLE_SCAN_UNSELECTED_FIFOS_FOR_DUAL_GFX_RING_CHANGE_MASK 0x10000000L +#define PA_SC_ENHANCE__OOO_USE_ABSOLUTE_FIFO_COUNT_IN_THRESHOLD_SWITCHING_MASK 0x20000000L +//PA_SC_ENHANCE_1 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING__SHIFT 0x3 +#define PA_SC_ENHANCE_1__BYPASS_PBB__SHIFT 0x4 +#define PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE__SHIFT 0x5 +#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x6 +#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x7 +#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x8 +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB__SHIFT 0x9 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT__SHIFT 0xa +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM__SHIFT 0xb +#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_COUNT_PIXELS__SHIFT 0xd +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_STILE_INTF_FINE_CLOCK_GATE__SHIFT 0xe +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE__SHIFT 0x10 +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION__SHIFT 0x12 +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS__SHIFT 0x13 +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION__SHIFT 0x14 +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION__SHIFT 0x15 +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION__SHIFT 0x16 +#define PA_SC_ENHANCE_1__DISABLE_INTF_CG__SHIFT 0x17 +#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x18 +#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER__SHIFT 0x19 +#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION__SHIFT 0x1a +#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE__SHIFT 0x1b +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX__SHIFT 0x1c +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1__SHIFT 0x1d +#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI__SHIFT 0x1e +#define PA_SC_ENHANCE_1__RESERVED_31__SHIFT 0x1f +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x00000001L +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x00000006L +#define PA_SC_ENHANCE_1__DISABLE_SC_BINNING_MASK 0x00000008L +#define PA_SC_ENHANCE_1__BYPASS_PBB_MASK 0x00000010L +#define PA_SC_ENHANCE_1__DISABLE_NONBINNED_LIVE_PRIM_DG1_LS0_CL0_EOPKT_POKE_MASK 0x00000020L +#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x00000040L +#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x00000080L +#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x00000100L +#define PA_SC_ENHANCE_1__DISABLE_SC_PROCESS_RESET_PBB_MASK 0x00000200L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_OPT_MASK 0x00000400L +#define PA_SC_ENHANCE_1__ENABLE_DFSM_FLUSH_EVENT_TO_FLUSH_POPS_CAM_MASK 0x00000800L +#define PA_SC_ENHANCE_1__DEBUG_PIXEL_PICKER_COUNT_PIXELS_MASK 0x00002000L +#define PA_SC_ENHANCE_1__DISABLE_SC_DB_STILE_INTF_FINE_CLOCK_GATE_MASK 0x00004000L +#define PA_SC_ENHANCE_1__DISABLE_PACKER_ODC_ENHANCE_MASK 0x00010000L +#define PA_SC_ENHANCE_1__OPTIMAL_BIN_SELECTION_MASK 0x00040000L +#define PA_SC_ENHANCE_1__DISABLE_FORCE_SOP_ALL_EVENTS_MASK 0x00080000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_CLK_OPTIMIZATION_MASK 0x00100000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_SCISSOR_CLK_OPTIMIZATION_MASK 0x00200000L +#define PA_SC_ENHANCE_1__DISABLE_PBB_BINNING_CLK_OPTIMIZATION_MASK 0x00400000L +#define PA_SC_ENHANCE_1__DISABLE_INTF_CG_MASK 0x00800000L +#define PA_SC_ENHANCE_1__IOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x01000000L +#define PA_SC_ENHANCE_1__DISABLE_SHADER_PROFILING_FOR_POWER_MASK 0x02000000L +#define PA_SC_ENHANCE_1__FLUSH_ON_BINNING_TRANSITION_MASK 0x04000000L +#define PA_SC_ENHANCE_1__DISABLE_QUAD_PROC_FDCE_ENHANCE_MASK 0x08000000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_MASK 0x10000000L +#define PA_SC_ENHANCE_1__DISABLE_SC_PS_PA_ARBITER_FIX_1_MASK 0x20000000L +#define PA_SC_ENHANCE_1__PASS_VPZ_EVENT_TO_SPI_MASK 0x40000000L +#define PA_SC_ENHANCE_1__RESERVED_31_MASK 0x80000000L +//PA_SC_ENHANCE_2 +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE__SHIFT 0x2 +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE__SHIFT 0x3 +#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK__SHIFT 0x4 +#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK__SHIFT 0x5 +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD__SHIFT 0x7 +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH__SHIFT 0x8 +#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK__SHIFT 0x9 +#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS__SHIFT 0xa +#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE__SHIFT 0xb +#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE__SHIFT 0xc +#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP__SHIFT 0xd +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP__SHIFT 0xe +#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ__SHIFT 0xf +#define PA_SC_ENHANCE_2__RESERVED_16__SHIFT 0x10 +#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP__SHIFT 0x11 +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET__SHIFT 0x12 +#define PA_SC_ENHANCE_2__RESERVED_22__SHIFT 0x16 +#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO__SHIFT 0x17 +#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH__SHIFT 0x1a +#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT__SHIFT 0x1b +#define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT__SHIFT 0x1e +#define PA_SC_ENHANCE_2__RSVD__SHIFT 0x1f +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_QUAD_INTF_FINE_CLOCK_GATE_MASK 0x00000004L +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_PRIM_INTF_FINE_CLOCK_GATE_MASK 0x00000008L +#define PA_SC_ENHANCE_2__ENABLE_LPOV_WAVE_BREAK_MASK 0x00000010L +#define PA_SC_ENHANCE_2__ENABLE_FPOV_WAVE_BREAK_MASK 0x00000020L +#define PA_SC_ENHANCE_2__ENABLE_SC_SEND_DB_VPZ_FOR_EN_PRIM_PAYLOAD_MASK 0x00000080L +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPE_SWITCH_MASK 0x00000100L +#define PA_SC_ENHANCE_2__DISABLE_FULL_TILE_WAVE_BREAK_MASK 0x00000200L +#define PA_SC_ENHANCE_2__ENABLE_VPZ_INJECTION_BEFORE_NULL_PRIMS_MASK 0x00000400L +#define PA_SC_ENHANCE_2__PBB_TIMEOUT_THRESHOLD_MODE_MASK 0x00000800L +#define PA_SC_ENHANCE_2__DISABLE_PACKER_GRAD_FDCE_ENHANCE_MASK 0x00001000L +#define PA_SC_ENHANCE_2__DISABLE_SC_SPI_INTF_EARLY_WAKEUP_MASK 0x00002000L +#define PA_SC_ENHANCE_2__DISABLE_SC_BCI_INTF_EARLY_WAKEUP_MASK 0x00004000L +#define PA_SC_ENHANCE_2__DISABLE_EXPOSED_GT_DETAIL_RATE_TILE_COV_ADJ_MASK 0x00008000L +#define PA_SC_ENHANCE_2__RESERVED_16_MASK 0x00010000L +#define PA_SC_ENHANCE_2__PBB_MAIN_CLK_REG_BUSY_WAKEUP_MASK 0x00020000L +#define PA_SC_ENHANCE_2__DISABLE_BREAK_BATCH_ON_GFX_PIPELINE_RESET_MASK 0x00040000L +#define PA_SC_ENHANCE_2__RESERVED_22_MASK 0x00400000L +#define PA_SC_ENHANCE_2__PROCESS_RESET_FORCE_STILE_MASK_TO_ZERO_MASK 0x00800000L +#define PA_SC_ENHANCE_2__BREAK_WHEN_ONE_NULL_PRIM_BATCH_MASK 0x04000000L +#define PA_SC_ENHANCE_2__NULL_PRIM_BREAK_BATCH_LIMIT_MASK 0x38000000L +#define PA_SC_ENHANCE_2__DISABLE_MAX_DEALLOC_FORCE_EOV_RESET_N_WAVES_COUNT_MASK 0x40000000L +#define PA_SC_ENHANCE_2__RSVD_MASK 0x80000000L +//PA_SC_ENHANCE_3 +#define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA__SHIFT 0x0 +#define PA_SC_ENHANCE_3__ECO_SPARE2__SHIFT 0x1 +#define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST__SHIFT 0x2 +#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 +#define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION__SHIFT 0x4 +#define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN__SHIFT 0x5 +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER__SHIFT 0x6 +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER__SHIFT 0x7 +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS__SHIFT 0x8 +#define PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY__SHIFT 0x9 +#define PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES__SHIFT 0xa +#define PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION__SHIFT 0xb +#define PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED__SHIFT 0xc +#define PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION__SHIFT 0xd +#define PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION__SHIFT 0xe +#define PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN__SHIFT 0xf +#define PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS__SHIFT 0x10 +#define PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM__SHIFT 0x11 +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT 0x14 +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY__SHIFT 0x15 +#define PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE__SHIFT 0x16 +#define PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION__SHIFT 0x17 +#define PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY__SHIFT 0x18 +#define PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL__SHIFT 0x19 +#define PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL__SHIFT 0x1a +#define PA_SC_ENHANCE_3__APPLY_AA_MASK_AT_EXPOSED_RATE_FOR_VRS_COURSE_QUADS_WITH_CR__SHIFT 0x1b +#define PA_SC_ENHANCE_3__ECO_SPARE0__SHIFT 0x1c +#define PA_SC_ENHANCE_3__ECO_SPARE1__SHIFT 0x1d +#define PA_SC_ENHANCE_3__DISABLE_SC_GL1X_SRC_FINE_CLOCK_GATE__SHIFT 0x1e +#define PA_SC_ENHANCE_3__DISABLE_SC_GL1X_REQ_FINE_CLOCK_GATE__SHIFT 0x1f +#define PA_SC_ENHANCE_3__FORCE_USE_OF_SC_CENTROID_DATA_MASK 0x00000001L +#define PA_SC_ENHANCE_3__ECO_SPARE2_MASK 0x00000002L +#define PA_SC_ENHANCE_3__DISABLE_RB_MASK_COPY_FOR_NONP2_SA_PAIR_HARVEST_MASK 0x00000004L +#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L +#define PA_SC_ENHANCE_3__DISABLE_PKR_BCI_QUAD_NEW_PRIM_DATA_LOAD_OPTIMIZATION_MASK 0x00000010L +#define PA_SC_ENHANCE_3__DISABLE_CP_CONTEXT_DONE_PERFCOUNT_SAMPLE_EN_MASK 0x00000020L +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_FIRST_PHASE_FILTER_MASK 0x00000040L +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_MASK 0x00000080L +#define PA_SC_ENHANCE_3__ENABLE_SINGLE_PA_EOPKT_LAST_PHASE_FILTER_FOR_PBB_BINNED_PRIMS_MASK 0x00000100L +#define PA_SC_ENHANCE_3__DISABLE_SET_VPZ_DIRTY_EOPKT_LAST_PHASE_ONLY_MASK 0x00000200L +#define PA_SC_ENHANCE_3__DISABLE_PBB_EOP_OPTIMIZATION_WITH_SAME_CONTEXT_BATCHES_MASK 0x00000400L +#define PA_SC_ENHANCE_3__DISABLE_FAST_NULL_PRIM_OPTIMIZATION_MASK 0x00000800L +#define PA_SC_ENHANCE_3__USE_PBB_PRIM_STORAGE_WHEN_STALLED_MASK 0x00001000L +#define PA_SC_ENHANCE_3__DISABLE_LIGHT_VOLUME_RENDERING_OPTIMIZATION_MASK 0x00002000L +#define PA_SC_ENHANCE_3__DISABLE_ZPRE_PASS_OPTIMIZATION_MASK 0x00004000L +#define PA_SC_ENHANCE_3__DISABLE_EVENT_INCLUSION_IN_CONTEXT_STATES_PER_BIN_MASK 0x00008000L +#define PA_SC_ENHANCE_3__DISABLE_PIXEL_WAIT_SYNC_COUNTERS_MASK 0x00010000L +#define PA_SC_ENHANCE_3__DISABLE_SC_CPG_PSINVOC_SEDC_ISOLATION_ACCUM_MASK 0x00020000L +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_REZ_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK 0x00100000L +#define PA_SC_ENHANCE_3__DISABLE_PKR_FORCE_EOV_MAX_CLK_CNT_FOR_SPI_BACKPRESSURE_ONLY_MASK 0x00200000L +#define PA_SC_ENHANCE_3__DO_NOT_INCLUDE_OREO_WAVEID_IN_FORCE_EOV_MAX_CNT_DISABLE_MASK 0x00400000L +#define PA_SC_ENHANCE_3__DISABLE_PWS_PRE_DEPTH_WAIT_SYNC_VPZ_INSERTION_MASK 0x00800000L +#define PA_SC_ENHANCE_3__PKR_CNT_FORCE_EOV_AT_QS_EMPTY_ONLY_MASK 0x01000000L +#define PA_SC_ENHANCE_3__PKR_S0_FORCE_EOV_STALL_MASK 0x02000000L +#define PA_SC_ENHANCE_3__PKR_S1_FORCE_EOV_STALL_MASK 0x04000000L +#define PA_SC_ENHANCE_3__APPLY_AA_MASK_AT_EXPOSED_RATE_FOR_VRS_COURSE_QUADS_WITH_CR_MASK 0x08000000L +#define PA_SC_ENHANCE_3__ECO_SPARE0_MASK 0x10000000L +#define PA_SC_ENHANCE_3__ECO_SPARE1_MASK 0x20000000L +#define PA_SC_ENHANCE_3__DISABLE_SC_GL1X_SRC_FINE_CLOCK_GATE_MASK 0x40000000L +#define PA_SC_ENHANCE_3__DISABLE_SC_GL1X_REQ_FINE_CLOCK_GATE_MASK 0x80000000L +//PA_SC_BINNER_CNTL_OVERRIDE +#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE__SHIFT 0x0 +#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN__SHIFT 0xa +#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN__SHIFT 0xd +#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH__SHIFT 0x13 +#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE__SHIFT 0x1b +#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE__SHIFT 0x1c +#define PA_SC_BINNER_CNTL_OVERRIDE__BINNING_MODE_MASK 0x00000003L +#define PA_SC_BINNER_CNTL_OVERRIDE__CONTEXT_STATES_PER_BIN_MASK 0x00001C00L +#define PA_SC_BINNER_CNTL_OVERRIDE__PERSISTENT_STATES_PER_BIN_MASK 0x0003E000L +#define PA_SC_BINNER_CNTL_OVERRIDE__FPOVS_PER_BATCH_MASK 0x07F80000L +#define PA_SC_BINNER_CNTL_OVERRIDE__DIRECT_OVERRIDE_MODE_MASK 0x08000000L +#define PA_SC_BINNER_CNTL_OVERRIDE__OVERRIDE_MASK 0xF0000000L +//PA_SC_PBB_OVERRIDE_FLAG +#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE__SHIFT 0x0 +#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID__SHIFT 0x1 +#define PA_SC_PBB_OVERRIDE_FLAG__OVERRIDE_MASK 0x00000001L +#define PA_SC_PBB_OVERRIDE_FLAG__PIPE_ID_MASK 0x00000002L +//PA_SC_DSM_CNTL +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x00000001L +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x00000002L +//PA_SC_TILE_STEERING_CREST_OVERRIDE +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE__SHIFT 0x0 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT__SHIFT 0x1 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT__SHIFT 0x5 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT__SHIFT 0x8 +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE__SHIFT 0x1f +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__ONE_RB_MODE_ENABLE_MASK 0x00000001L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SE_SELECT_MASK 0x00000006L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__RB_SELECT_MASK 0x00000060L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__SA_SELECT_MASK 0x00000700L +#define PA_SC_TILE_STEERING_CREST_OVERRIDE__FORCE_TILE_STEERING_OVERRIDE_USE_MASK 0x80000000L +//PA_SC_FIFO_SIZE +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x15 +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x00007FC0L +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x001F8000L +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xFFE00000L +//PA_SC_IF_FIFO_SIZE +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x0000003FL +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0x00000FC0L +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x0003F000L +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0x00FC0000L +//PA_SC_PACKER_WAVE_ID_CNTL +#define PA_SC_PACKER_WAVE_ID_CNTL__WAVES_IN_FLIGHT_LIMIT__SHIFT 0x0 +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE__SHIFT 0xa +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN__SHIFT 0x10 +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE__SHIFT 0x11 +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN__SHIFT 0x17 +#define PA_SC_PACKER_WAVE_ID_CNTL__DEBUG_CONFLICT_QUAD__SHIFT 0x18 +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD__SHIFT 0x1f +#define PA_SC_PACKER_WAVE_ID_CNTL__WAVES_IN_FLIGHT_LIMIT_MASK 0x000001FFL +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_DB_WAVE_IF_FIFO_SIZE_MASK 0x0000FC00L +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_DB_WAVE_IF_FGCG_EN_MASK 0x00010000L +#define PA_SC_PACKER_WAVE_ID_CNTL__SC_SPI_WAVE_IF_FIFO_SIZE_MASK 0x007E0000L +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_SC_SPI_WAVE_IF_FGCG_EN_MASK 0x00800000L +#define PA_SC_PACKER_WAVE_ID_CNTL__DEBUG_CONFLICT_QUAD_MASK 0x0F000000L +#define PA_SC_PACKER_WAVE_ID_CNTL__DISABLE_OREO_CONFLICT_QUAD_MASK 0x80000000L +//PA_SC_ATM_CNTL +#define PA_SC_ATM_CNTL__SC_PC_IF_SIZE__SHIFT 0x0 +#define PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN__SHIFT 0x7 +#define PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE__SHIFT 0x8 +#define PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES__SHIFT 0x10 +#define PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES__SHIFT 0x11 +#define PA_SC_ATM_CNTL__SC_PC_IF_SIZE_MASK 0x0000003FL +#define PA_SC_ATM_CNTL__DISABLE_SC_PC_IF_FGCG_EN_MASK 0x00000080L +#define PA_SC_ATM_CNTL__MAX_ATTRIBUTES_IN_WAVE_MASK 0x0000FF00L +#define PA_SC_ATM_CNTL__DISABLE_MAX_ATTRIBUTES_MASK 0x00010000L +#define PA_SC_ATM_CNTL__SELECT_MAX_ATTRIBUTES_MASK 0x00020000L +//PA_SC_PKR_WAVE_TABLE_CNTL +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE__SHIFT 0x0 +#define PA_SC_PKR_WAVE_TABLE_CNTL__SIZE_MASK 0x0000003FL +//PA_SC_FORCE_EOV_MAX_CNTS +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0x0000FFFFL +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xFFFF0000L +//PA_SC_BINNER_EVENT_CNTL_0 +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_0__EVENT_STATE_CHANGE__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_0__RESERVED_0_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS1_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS2_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_0__SAMPLE_STREAMOUTSTATS3_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_TS_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_0__CONTEXT_DONE_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_0__CACHE_FLUSH_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_0__CS_PARTIAL_FLUSH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_SYNC_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_0__EVENT_STATE_CHANGE_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_0__VGT_STREAMOUT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_INCR_DE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_0__END_OF_PIPE_IB_END_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_0__RST_PIX_CNT_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_0__BREAK_BATCH_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_0__VS_PARTIAL_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_1 +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_1__PS_PARTIAL_FLUSH_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_HS_OUTPUT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_DFSM_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_1__RESET_TO_LOWEST_VGT_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_1__WAIT_SYNC_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_1__CACHE_FLUSH_AND_INV_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_START_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_STOP_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_START_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_1__PIPELINESTAT_STOP_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_1__PERFCOUNTER_SAMPLE_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_1__FLUSH_ES_OUTPUT_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_1__BIN_CONF_OVERRIDE_CHECK_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SAMPLE_PIPELINESTAT_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_1__SO_VGTSTREAMOUT_FLUSH_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_2 +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_2__SAMPLE_STREAMOUTSTATS_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_2__RESET_VTX_CNT_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_2__BLOCK_CONTEXT_DONE_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_35_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_2__VGT_FLUSH_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_2__TGID_ROLLOVER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_2__SQ_NON_EVENT_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_2__SC_SEND_DB_VPZ_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_2__BOTTOM_OF_PIPE_TS_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_2__RESERVED_41_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_2__DB_CACHE_FLUSH_AND_INV_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_DATA_TS_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_DB_META_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_DATA_TS_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_2__FLUSH_AND_INV_CB_META_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_2__CS_DONE_MASK 0xC0000000L +//PA_SC_BINNER_EVENT_CNTL_3 +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE__SHIFT 0x0 +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA__SHIFT 0x2 +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50__SHIFT 0x4 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START__SHIFT 0x6 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP__SHIFT 0x8 +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER__SHIFT 0xa +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW__SHIFT 0xc +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH__SHIFT 0xe +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL__SHIFT 0x10 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP__SHIFT 0x12 +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET__SHIFT 0x14 +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND__SHIFT 0x16 +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC__SHIFT 0x18 +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE__SHIFT 0x1a +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED__SHIFT 0x1c +#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE__SHIFT 0x1e +#define PA_SC_BINNER_EVENT_CNTL_3__PS_DONE_MASK 0x00000003L +#define PA_SC_BINNER_EVENT_CNTL_3__FLUSH_AND_INV_CB_PIXEL_DATA_MASK 0x0000000CL +#define PA_SC_BINNER_EVENT_CNTL_3__RESERVED_50_MASK 0x00000030L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_START_MASK 0x000000C0L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_STOP_MASK 0x00000300L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_MARKER_MASK 0x00000C00L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_DRAW_MASK 0x00003000L +#define PA_SC_BINNER_EVENT_CNTL_3__THREAD_TRACE_FINISH_MASK 0x0000C000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_CONTROL_MASK 0x00030000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_DUMP_MASK 0x000C0000L +#define PA_SC_BINNER_EVENT_CNTL_3__PIXEL_PIPE_STAT_RESET_MASK 0x00300000L +#define PA_SC_BINNER_EVENT_CNTL_3__CONTEXT_SUSPEND_MASK 0x00C00000L +#define PA_SC_BINNER_EVENT_CNTL_3__OFFCHIP_HS_DEALLOC_MASK 0x03000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_NGG_PIPELINE_MASK 0x0C000000L +#define PA_SC_BINNER_EVENT_CNTL_3__ENABLE_PIPELINE_NOT_USED_MASK 0x30000000L +#define PA_SC_BINNER_EVENT_CNTL_3__DRAW_DONE_MASK 0xC0000000L +//PA_SC_BINNER_TIMEOUT_COUNTER +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_TIMEOUT_COUNTER__THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_BINNER_PERF_CNTL_0 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x14 +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD__SHIFT 0x17 +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000003FFL +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_PRIMS_THRESHOLD_MASK 0x000FFC00L +#define PA_SC_BINNER_PERF_CNTL_0__BIN_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x00700000L +#define PA_SC_BINNER_PERF_CNTL_0__BATCH_HIST_NUM_CONTEXT_THRESHOLD_MASK 0x03800000L +//PA_SC_BINNER_PERF_CNTL_1 +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD__SHIFT 0x5 +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD__SHIFT 0xa +#define PA_SC_BINNER_PERF_CNTL_1__BIN_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x0000001FL +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_PERSISTENT_STATE_THRESHOLD_MASK 0x000003E0L +#define PA_SC_BINNER_PERF_CNTL_1__BATCH_HIST_NUM_TRIV_REJECTED_PRIMS_THRESHOLD_MASK 0x03FFFC00L +//PA_SC_BINNER_PERF_CNTL_2 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD__SHIFT 0xb +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_ROWS_PER_PRIM_THRESHOLD_MASK 0x000007FFL +#define PA_SC_BINNER_PERF_CNTL_2__BATCH_HIST_NUM_COLUMNS_PER_ROW_THRESHOLD_MASK 0x003FF800L +//PA_SC_BINNER_PERF_CNTL_3 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD__SHIFT 0x0 +#define PA_SC_BINNER_PERF_CNTL_3__BATCH_HIST_NUM_PS_WAVE_BREAKS_THRESHOLD_MASK 0xFFFFFFFFL +//PA_SC_P3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_HP3D_TRAP_SCREEN_HV_LOCK +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_SC_TRAP_SCREEN_HV_LOCK +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x00000001L +//PA_PH_INTERFACE_FIFO_SIZE +#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE__SHIFT 0x10 +#define PA_PH_INTERFACE_FIFO_SIZE__PA_PH_IF_FIFO_SIZE_MASK 0x000003FFL +#define PA_PH_INTERFACE_FIFO_SIZE__PH_SC_IF_FIFO_SIZE_MASK 0x003F0000L +//PA_PH_ENHANCE +#define PA_PH_ENHANCE__ECO_SPARE0__SHIFT 0x0 +#define PA_PH_ENHANCE__ECO_SPARE1__SHIFT 0x1 +#define PA_PH_ENHANCE__ECO_SPARE2__SHIFT 0x2 +#define PA_PH_ENHANCE__ECO_SPARE3__SHIFT 0x3 +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE__SHIFT 0x4 +#define PA_PH_ENHANCE__DISABLE_FOPKT__SHIFT 0x5 +#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET__SHIFT 0x6 +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE__SHIFT 0x7 +#define PA_PH_ENHANCE__DISABLE_PH_DEBUG_REG_FGCG__SHIFT 0x8 +#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG__SHIFT 0x9 +#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH__SHIFT 0xa +#define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT__SHIFT 0xd +#define PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS__SHIFT 0xe +#define PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON__SHIFT 0xf +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE__SHIFT 0x10 +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE__SHIFT 0x11 +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE__SHIFT 0x12 +#define PA_PH_ENHANCE__ECO_SPARE0_MASK 0x00000001L +#define PA_PH_ENHANCE__ECO_SPARE1_MASK 0x00000002L +#define PA_PH_ENHANCE__ECO_SPARE2_MASK 0x00000004L +#define PA_PH_ENHANCE__ECO_SPARE3_MASK 0x00000008L +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_FINE_CLOCK_GATE_MASK 0x00000010L +#define PA_PH_ENHANCE__DISABLE_FOPKT_MASK 0x00000020L +#define PA_PH_ENHANCE__DISABLE_FOPKT_SCAN_POST_RESET_MASK 0x00000040L +#define PA_PH_ENHANCE__DISABLE_PH_SC_INTF_CLKEN_CLOCK_GATE_MASK 0x00000080L +#define PA_PH_ENHANCE__DISABLE_PH_DEBUG_REG_FGCG_MASK 0x00000100L +#define PA_PH_ENHANCE__DISABLE_PH_PERF_REG_FGCG_MASK 0x00000200L +#define PA_PH_ENHANCE__ENABLE_PH_INTF_CLKEN_STRETCH_MASK 0x00001C00L +#define PA_PH_ENHANCE__DISABLE_USE_LAST_PH_ARBITER_PERFCOUNTER_SAMPLE_EVENT_MASK 0x00002000L +#define PA_PH_ENHANCE__USE_PERFCOUNTER_START_STOP_EVENTS_MASK 0x00004000L +#define PA_PH_ENHANCE__FORCE_PH_PERFCOUNTER_SAMPLE_ENABLE_ON_MASK 0x00008000L +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_MASK 0x00010000L +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_MODE_DISABLE_MASK 0x00020000L +#define PA_PH_ENHANCE__PH_SPI_GE_THROTTLE_PERFCOUNTER_COUNT_MODE_MASK 0x00040000L +//PA_SC_VRS_SURFACE_CNTL_1 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE__SHIFT 0x0 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE__SHIFT 0x1 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE__SHIFT 0x2 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTERFACE_RATE_16XAA__SHIFT 0x3 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL__SHIFT 0x4 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED__SHIFT 0x5 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT__SHIFT 0x6 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS__SHIFT 0x7 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTERFACE_RATE_8XAA__SHIFT 0x8 +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTRINSIC_RATE_GT_4XAA__SHIFT 0x9 +#define PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG__SHIFT 0xa +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION__SHIFT 0xc +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE__SHIFT 0xf +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE__SHIFT 0x13 +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING__SHIFT 0x14 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0__SHIFT 0x15 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1__SHIFT 0x16 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2__SHIFT 0x17 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3__SHIFT 0x18 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4__SHIFT 0x19 +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5__SHIFT 0x1a +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6__SHIFT 0x1b +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7__SHIFT 0x1c +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8__SHIFT 0x1d +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9__SHIFT 0x1e +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10__SHIFT 0x1f +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK 0x00000001L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_SHADER_KILL_ENABLE_MASK 0x00000002L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_MASK_OPS_ENABLE_MASK 0x00000004L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTERFACE_RATE_16XAA_MASK 0x00000008L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_Z_OR_STENCIL_MASK 0x00000010L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_PRE_SHADER_DEPTH_COVERAGE_ENABLED_MASK 0x00000020L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POST_DEPTH_IMPORT_MASK 0x00000040L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_POPS_MASK 0x00000080L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTERFACE_RATE_8XAA_MASK 0x00000100L +#define PA_SC_VRS_SURFACE_CNTL_1__FORCE_SC_VRS_RATE_FINE_INTRINSIC_RATE_GT_4XAA_MASK 0x00000200L +#define PA_SC_VRS_SURFACE_CNTL_1__USE_ONLY_VRS_RATE_FINE_CFG_MASK 0x00000400L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_VRS_RATE_NORMALIZATION_MASK 0x00001000L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_PS_ITER_RATE_COMBINER_PASSTHRU_OVERRIDE_MASK 0x00008000L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_CMASK_RATE_HINT_FORCE_ZERO_OVERRIDE_MASK 0x00080000L +#define PA_SC_VRS_SURFACE_CNTL_1__DISABLE_SSAA_DETAIL_TO_EXPOSED_RATE_CLAMPING_MASK 0x00100000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_0_MASK 0x00200000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_1_MASK 0x00400000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_2_MASK 0x00800000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_3_MASK 0x01000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_4_MASK 0x02000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_5_MASK 0x04000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_6_MASK 0x08000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_7_MASK 0x10000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_8_MASK 0x20000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_9_MASK 0x40000000L +#define PA_SC_VRS_SURFACE_CNTL_1__VRS_ECO_SPARE_10_MASK 0x80000000L +//PA_SC_HIZ_SURFACE_CNTL +#define PA_SC_HIZ_SURFACE_CNTL__HZC_OUTSTANDING_CONTEXT_FILTERING_DISABLE__SHIFT 0x5 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x6 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_DB_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x7 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_FLUSH_EVENT_MASK_DISABLE__SHIFT 0x8 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_PREFETCH_DISABLE__SHIFT 0xd +#define PA_SC_HIZ_SURFACE_CNTL__HZC_FLUSH_NO_INV_DISABLE__SHIFT 0xe +#define PA_SC_HIZ_SURFACE_CNTL__HZC_NONSTALLING_FLUSH_DISABLE__SHIFT 0xf +#define PA_SC_HIZ_SURFACE_CNTL__HZC_PARTIAL_FLUSH_DISABLE__SHIFT 0x10 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_EOP_SYNC_DISABLE__SHIFT 0x12 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_MAX_TAGS__SHIFT 0x13 +#define PA_SC_HIZ_SURFACE_CNTL__HZC_EVICT_POINT__SHIFT 0x1a +#define PA_SC_HIZ_SURFACE_CNTL__HZC_OUTSTANDING_CONTEXT_FILTERING_DISABLE_MASK 0x00000020L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000040L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_DB_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000080L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_FLUSH_EVENT_MASK_DISABLE_MASK 0x00001F00L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_PREFETCH_DISABLE_MASK 0x00002000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_FLUSH_NO_INV_DISABLE_MASK 0x00004000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_NONSTALLING_FLUSH_DISABLE_MASK 0x00008000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_PARTIAL_FLUSH_DISABLE_MASK 0x00010000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_EOP_SYNC_DISABLE_MASK 0x00040000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_MAX_TAGS_MASK 0x03F80000L +#define PA_SC_HIZ_SURFACE_CNTL__HZC_EVICT_POINT_MASK 0xFC000000L +//PA_SC_HIS_SURFACE_CNTL +#define PA_SC_HIS_SURFACE_CNTL__HSC_OUTSTANDING_CONTEXT_FILTERING_DISABLE__SHIFT 0x5 +#define PA_SC_HIS_SURFACE_CNTL__HSC_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x6 +#define PA_SC_HIS_SURFACE_CNTL__HSC_DB_CONTEXT_DONE_SYNC_DISABLE__SHIFT 0x7 +#define PA_SC_HIS_SURFACE_CNTL__HSC_FLUSH_EVENT_MASK_DISABLE__SHIFT 0x8 +#define PA_SC_HIS_SURFACE_CNTL__HSC_PREFETCH_DISABLE__SHIFT 0xd +#define PA_SC_HIS_SURFACE_CNTL__HSC_FLUSH_NO_INV_DISABLE__SHIFT 0xe +#define PA_SC_HIS_SURFACE_CNTL__HSC_NONSTALLING_FLUSH_DISABLE__SHIFT 0xf +#define PA_SC_HIS_SURFACE_CNTL__HSC_PARTIAL_FLUSH_DISABLE__SHIFT 0x10 +#define PA_SC_HIS_SURFACE_CNTL__HSC_EOP_SYNC_DISABLE__SHIFT 0x12 +#define PA_SC_HIS_SURFACE_CNTL__HSC_MAX_TAGS__SHIFT 0x13 +#define PA_SC_HIS_SURFACE_CNTL__HSC_EVICT_POINT__SHIFT 0x1a +#define PA_SC_HIS_SURFACE_CNTL__HSC_OUTSTANDING_CONTEXT_FILTERING_DISABLE_MASK 0x00000020L +#define PA_SC_HIS_SURFACE_CNTL__HSC_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000040L +#define PA_SC_HIS_SURFACE_CNTL__HSC_DB_CONTEXT_DONE_SYNC_DISABLE_MASK 0x00000080L +#define PA_SC_HIS_SURFACE_CNTL__HSC_FLUSH_EVENT_MASK_DISABLE_MASK 0x00001F00L +#define PA_SC_HIS_SURFACE_CNTL__HSC_PREFETCH_DISABLE_MASK 0x00002000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_FLUSH_NO_INV_DISABLE_MASK 0x00004000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_NONSTALLING_FLUSH_DISABLE_MASK 0x00008000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_PARTIAL_FLUSH_DISABLE_MASK 0x00010000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_EOP_SYNC_DISABLE_MASK 0x00040000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_MAX_TAGS_MASK 0x03F80000L +#define PA_SC_HIS_SURFACE_CNTL__HSC_EVICT_POINT_MASK 0xFC000000L +//PA_SC_HIZ_DEBUG +#define PA_SC_HIZ_DEBUG__FORCE_Z_MODE__SHIFT 0x1 +#define PA_SC_HIZ_DEBUG__FORCE_DEPTH_READ__SHIFT 0x3 +#define PA_SC_HIZ_DEBUG__FORCE_HIZ_ENABLE__SHIFT 0x4 +#define PA_SC_HIZ_DEBUG__FAST_Z_DISABLE__SHIFT 0x6 +#define PA_SC_HIZ_DEBUG__NOOP_CULL_DISABLE__SHIFT 0x7 +#define PA_SC_HIZ_DEBUG__FORCE_TILE_OP__SHIFT 0x8 +#define PA_SC_HIZ_DEBUG__FORCE_HITEST_RESULTS__SHIFT 0xc +#define PA_SC_HIZ_DEBUG__DISABLE_4X_TILE_PICKING__SHIFT 0x11 +#define PA_SC_HIZ_DEBUG__DISABLE_FAST_SET_WITHOUT_HIZ_SURFACE__SHIFT 0x12 +#define PA_SC_HIZ_DEBUG__FORCE_FULL_Z_RANGE__SHIFT 0x13 +#define PA_SC_HIZ_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x15 +#define PA_SC_HIZ_DEBUG__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x16 +#define PA_SC_HIZ_DEBUG__DISABLE_VPZ_EVENT_FILTERING__SHIFT 0x17 +#define PA_SC_HIZ_DEBUG__DISABLE_REPLICATE_DETAIL_LOCATIONS_TO_SURFACE_RATE_FOR_SURF_GT_DETAIL_RATE__SHIFT 0x18 +#define PA_SC_HIZ_DEBUG__DISABLE_SUMMARIZATION_MONOTONICITY__SHIFT 0x19 +#define PA_SC_HIZ_DEBUG__DISABLE_FAST_NO_OP_WITH_TILE_RATE__SHIFT 0x1a +#define PA_SC_HIZ_DEBUG__FORCE_Z_MODE_MASK 0x00000006L +#define PA_SC_HIZ_DEBUG__FORCE_DEPTH_READ_MASK 0x00000008L +#define PA_SC_HIZ_DEBUG__FORCE_HIZ_ENABLE_MASK 0x00000030L +#define PA_SC_HIZ_DEBUG__FAST_Z_DISABLE_MASK 0x00000040L +#define PA_SC_HIZ_DEBUG__NOOP_CULL_DISABLE_MASK 0x00000080L +#define PA_SC_HIZ_DEBUG__FORCE_TILE_OP_MASK 0x00000F00L +#define PA_SC_HIZ_DEBUG__FORCE_HITEST_RESULTS_MASK 0x0001F000L +#define PA_SC_HIZ_DEBUG__DISABLE_4X_TILE_PICKING_MASK 0x00020000L +#define PA_SC_HIZ_DEBUG__DISABLE_FAST_SET_WITHOUT_HIZ_SURFACE_MASK 0x00040000L +#define PA_SC_HIZ_DEBUG__FORCE_FULL_Z_RANGE_MASK 0x00180000L +#define PA_SC_HIZ_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x00200000L +#define PA_SC_HIZ_DEBUG__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x00400000L +#define PA_SC_HIZ_DEBUG__DISABLE_VPZ_EVENT_FILTERING_MASK 0x00800000L +#define PA_SC_HIZ_DEBUG__DISABLE_REPLICATE_DETAIL_LOCATIONS_TO_SURFACE_RATE_FOR_SURF_GT_DETAIL_RATE_MASK 0x01000000L +#define PA_SC_HIZ_DEBUG__DISABLE_SUMMARIZATION_MONOTONICITY_MASK 0x02000000L +#define PA_SC_HIZ_DEBUG__DISABLE_FAST_NO_OP_WITH_TILE_RATE_MASK 0x04000000L +//PA_SC_HIS_DEBUG +#define PA_SC_HIS_DEBUG__FORCE_STENCIL_READ__SHIFT 0x1 +#define PA_SC_HIS_DEBUG__FORCE_HIS_ENABLE__SHIFT 0x2 +#define PA_SC_HIS_DEBUG__FAST_STENCIL_DISABLE__SHIFT 0x6 +#define PA_SC_HIS_DEBUG__NOOP_CULL_DISABLE__SHIFT 0x7 +#define PA_SC_HIS_DEBUG__DISABLE_FULLY_COVERED_PRE_HISZ__SHIFT 0x8 +#define PA_SC_HIS_DEBUG__DISABLE_FULLY_COVERED_POST_HISZ__SHIFT 0x9 +#define PA_SC_HIS_DEBUG__DROP_UNLIT_STILES_AFTER_DETAIL_WALK__SHIFT 0xa +#define PA_SC_HIS_DEBUG__DROP_DUPLICATE_SC_DB_STILE_UPDATE_BEFORE_DETAIL_WALK__SHIFT 0xb +#define PA_SC_HIS_DEBUG__FULLY_COVERED_IS_STILE_QUAD_MASK_BASED__SHIFT 0xc +#define PA_SC_HIS_DEBUG__FORCE_SURFACE_ENABLED_TO_HISZ__SHIFT 0xd +#define PA_SC_HIS_DEBUG__USE_DETAIL_RATE_IN_PRE_HISZ_STW__SHIFT 0xe +#define PA_SC_HIS_DEBUG__DISABLE_SINGLE_STENCIL__SHIFT 0xf +#define PA_SC_HIS_DEBUG__DISABLE_SUMMARIZATION_MONOTONICITY__SHIFT 0x10 +#define PA_SC_HIS_DEBUG__DISABLE_FAST_NO_OP_WITH_TILE_RATE__SHIFT 0x11 +#define PA_SC_HIS_DEBUG__FORCE_STENCIL_READ_MASK 0x00000002L +#define PA_SC_HIS_DEBUG__FORCE_HIS_ENABLE_MASK 0x0000000CL +#define PA_SC_HIS_DEBUG__FAST_STENCIL_DISABLE_MASK 0x00000040L +#define PA_SC_HIS_DEBUG__NOOP_CULL_DISABLE_MASK 0x00000080L +#define PA_SC_HIS_DEBUG__DISABLE_FULLY_COVERED_PRE_HISZ_MASK 0x00000100L +#define PA_SC_HIS_DEBUG__DISABLE_FULLY_COVERED_POST_HISZ_MASK 0x00000200L +#define PA_SC_HIS_DEBUG__DROP_UNLIT_STILES_AFTER_DETAIL_WALK_MASK 0x00000400L +#define PA_SC_HIS_DEBUG__DROP_DUPLICATE_SC_DB_STILE_UPDATE_BEFORE_DETAIL_WALK_MASK 0x00000800L +#define PA_SC_HIS_DEBUG__FULLY_COVERED_IS_STILE_QUAD_MASK_BASED_MASK 0x00001000L +#define PA_SC_HIS_DEBUG__FORCE_SURFACE_ENABLED_TO_HISZ_MASK 0x00002000L +#define PA_SC_HIS_DEBUG__USE_DETAIL_RATE_IN_PRE_HISZ_STW_MASK 0x00004000L +#define PA_SC_HIS_DEBUG__DISABLE_SINGLE_STENCIL_MASK 0x00008000L +#define PA_SC_HIS_DEBUG__DISABLE_SUMMARIZATION_MONOTONICITY_MASK 0x00010000L +#define PA_SC_HIS_DEBUG__DISABLE_FAST_NO_OP_WITH_TILE_RATE_MASK 0x00020000L +//SC_MEM_SCOPE +#define SC_MEM_SCOPE__VRS_RATE_SCOPE__SHIFT 0x0 +#define SC_MEM_SCOPE__VRS_FEEDBACK_SCOPE__SHIFT 0x2 +#define SC_MEM_SCOPE__HIZ_SCOPE__SHIFT 0x4 +#define SC_MEM_SCOPE__HIS_SCOPE__SHIFT 0x6 +#define SC_MEM_SCOPE__VRS_RATE_SCOPE_MASK 0x00000003L +#define SC_MEM_SCOPE__VRS_FEEDBACK_SCOPE_MASK 0x0000000CL +#define SC_MEM_SCOPE__HIZ_SCOPE_MASK 0x00000030L +#define SC_MEM_SCOPE__HIS_SCOPE_MASK 0x000000C0L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfvf_sqdec +//SQ_RUNTIME_CONFIG +#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER__SHIFT 0x0 +#define SQ_RUNTIME_CONFIG__UNUSED_REGISTER_MASK 0x00000001L +//SQ_DEBUG_STS_GLOBAL +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY__SHIFT 0x1 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0__SHIFT 0x4 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_BUSY_MASK 0x00000002L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA0_MASK 0x0000FFF0L +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SA1_MASK 0x0FFF0000L +//SQ_DEBUG_STS_GLOBAL2 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1__SHIFT 0x8 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX0_MASK 0x000000FFL +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_GFX1_MASK 0x0000FF00L +#define SQ_DEBUG_STS_GLOBAL2__REG_FIFO_LEVEL_COMPUTE_MASK 0x00FF0000L +//SH_MEM_BASES +#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0xa +#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 +#define SH_MEM_BASES__PRIVATE_BASE_MASK 0x0000FC00L +#define SH_MEM_BASES__SHARED_BASE_MASK 0xFFFF0000L +//SH_MEM_CONFIG +#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 +#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x2 +#define SH_MEM_CONFIG__F8_MODE__SHIFT 0x8 +#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT 0xe +#define SH_MEM_CONFIG__ICACHE_USE_GL1__SHIFT 0x12 +#define SH_MEM_CONFIG__RETRY_DISABLE__SHIFT 0x13 +#define SH_MEM_CONFIG__RETRY_DEBUG__SHIFT 0x14 +#define SH_MEM_CONFIG__XCNT_DEBUG__SHIFT 0x15 +#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x00000001L +#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x00000004L +#define SH_MEM_CONFIG__F8_MODE_MASK 0x00000100L +#define SH_MEM_CONFIG__INITIAL_INST_PREFETCH_MASK 0x0000C000L +#define SH_MEM_CONFIG__ICACHE_USE_GL1_MASK 0x00040000L +#define SH_MEM_CONFIG__RETRY_DISABLE_MASK 0x00080000L +#define SH_MEM_CONFIG__RETRY_DEBUG_MASK 0x00100000L +#define SH_MEM_CONFIG__XCNT_DEBUG_MASK 0x00200000L +//SQ_DEBUG +#define SQ_DEBUG__SINGLE_MEMOP__SHIFT 0x0 +#define SQ_DEBUG__SINGLE_ALU_OP__SHIFT 0x1 +#define SQ_DEBUG__WAIT_DEP_CTR_ZERO__SHIFT 0x2 +#define SQ_DEBUG__SU_VDST_WKILL_DIS__SHIFT 0x3 +#define SQ_DEBUG__ADDR_OUT_OF_RANGE_REPORTING__SHIFT 0x4 +#define SQ_DEBUG__DISABLE_VGPR_DEALLOC__SHIFT 0x5 +#define SQ_DEBUG__SINGLE_MEMOP_MASK 0x00000001L +#define SQ_DEBUG__SINGLE_ALU_OP_MASK 0x00000002L +#define SQ_DEBUG__WAIT_DEP_CTR_ZERO_MASK 0x00000004L +#define SQ_DEBUG__SU_VDST_WKILL_DIS_MASK 0x00000008L +#define SQ_DEBUG__ADDR_OUT_OF_RANGE_REPORTING_MASK 0x00000010L +#define SQ_DEBUG__DISABLE_VGPR_DEALLOC_MASK 0x00000020L +//SQ_SHADER_TBA_LO +#define SQ_SHADER_TBA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TBA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TBA_HI +#define SQ_SHADER_TBA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TBA_HI__TRAP_EN__SHIFT 0x1f +#define SQ_SHADER_TBA_HI__ADDR_HI_MASK 0x0001FFFFL +#define SQ_SHADER_TBA_HI__TRAP_EN_MASK 0x80000000L +//SQ_SHADER_TMA_LO +#define SQ_SHADER_TMA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_SHADER_TMA_LO__ADDR_LO_MASK 0xFFFFFFFFL +//SQ_SHADER_TMA_HI +#define SQ_SHADER_TMA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_SHADER_TMA_HI__ADDR_HI_MASK 0x0001FFFFL +//SQ_IND_INDEX_USER +#define SQ_IND_INDEX_USER__WAVE_ID__SHIFT 0x0 +#define SQ_IND_INDEX_USER__WORKITEM_ID__SHIFT 0x5 +#define SQ_IND_INDEX_USER__AUTO_INCR__SHIFT 0xb +#define SQ_IND_INDEX_USER__INDEX__SHIFT 0x10 +#define SQ_IND_INDEX_USER__WAVE_ID_MASK 0x0000001FL +#define SQ_IND_INDEX_USER__WORKITEM_ID_MASK 0x000007E0L +#define SQ_IND_INDEX_USER__AUTO_INCR_MASK 0x00000800L +#define SQ_IND_INDEX_USER__INDEX_MASK 0xFFFF0000L +//SQ_CMD_USER +#define SQ_CMD_USER__CMD__SHIFT 0x0 +#define SQ_CMD_USER__MODE__SHIFT 0x4 +#define SQ_CMD_USER__CHECK_VMID__SHIFT 0x7 +#define SQ_CMD_USER__DATA__SHIFT 0x8 +#define SQ_CMD_USER__WAVE_ID__SHIFT 0x10 +#define SQ_CMD_USER__QUEUE_ID__SHIFT 0x18 +#define SQ_CMD_USER__VM_ID__SHIFT 0x1c +#define SQ_CMD_USER__CMD_MASK 0x0000000FL +#define SQ_CMD_USER__MODE_MASK 0x00000070L +#define SQ_CMD_USER__CHECK_VMID_MASK 0x00000080L +#define SQ_CMD_USER__DATA_MASK 0x00000F00L +#define SQ_CMD_USER__WAVE_ID_MASK 0x001F0000L +#define SQ_CMD_USER__QUEUE_ID_MASK 0x07000000L +#define SQ_CMD_USER__VM_ID_MASK 0xF0000000L +//SQ_IND_DATA_USER +#define SQ_IND_DATA_USER__DATA__SHIFT 0x0 +#define SQ_IND_DATA_USER__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_spidec +//SPI_CDBG_SYS_GFX +#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 +#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x00000001L +#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x00000004L +#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x00000010L +#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x00000040L +//SPI_CDBG_SYS_HP3D +#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_HP3D__CS_EN__SHIFT 0x6 +#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x00000001L +#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x00000004L +#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x00000010L +#define SPI_CDBG_SYS_HP3D__CS_EN_MASK 0x00000040L +//SPI_CDBG_SYS_CS0 +#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 +#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 +#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 +#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 +#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0x000000FFL +#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0x0000FF00L +#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0x00FF0000L +#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xFF000000L +//SPI_GDBG_WAVE_CNTL +#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_LAUNCH__SHIFT 0x1 +#define SPI_GDBG_WAVE_CNTL__STALL_STATUS__SHIFT 0x2 +#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL__STALL_LAUNCH_MASK 0x00000002L +#define SPI_GDBG_WAVE_CNTL__STALL_STATUS_MASK 0x00000004L +//SPI_GDBG_TRAP_CONFIG +#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN__SHIFT 0x10 +#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN__SHIFT 0x18 +#define SPI_GDBG_TRAP_CONFIG__PIPE0_EN_MASK 0x000000FFL +#define SPI_GDBG_TRAP_CONFIG__PIPE1_EN_MASK 0x0000FF00L +#define SPI_GDBG_TRAP_CONFIG__PIPE2_EN_MASK 0x00FF0000L +#define SPI_GDBG_TRAP_CONFIG__PIPE3_EN_MASK 0xFF000000L +//SPI_GDBG_WAVE_CNTL3 +#define SPI_GDBG_WAVE_CNTL3__STALL_PS__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL3__STALL_GS__SHIFT 0x2 +#define SPI_GDBG_WAVE_CNTL3__STALL_HS__SHIFT 0x3 +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG__SHIFT 0x4 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0__SHIFT 0x5 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1__SHIFT 0x6 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2__SHIFT 0x7 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3__SHIFT 0x8 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4__SHIFT 0x9 +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5__SHIFT 0xa +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6__SHIFT 0xb +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7__SHIFT 0xc +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION__SHIFT 0xd +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT__SHIFT 0x1c +#define SPI_GDBG_WAVE_CNTL3__STALL_PS_MASK 0x00000001L +#define SPI_GDBG_WAVE_CNTL3__STALL_GS_MASK 0x00000004L +#define SPI_GDBG_WAVE_CNTL3__STALL_HS_MASK 0x00000008L +#define SPI_GDBG_WAVE_CNTL3__STALL_CSG_MASK 0x00000010L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS0_MASK 0x00000020L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS1_MASK 0x00000040L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS2_MASK 0x00000080L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS3_MASK 0x00000100L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS4_MASK 0x00000200L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS5_MASK 0x00000400L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS6_MASK 0x00000800L +#define SPI_GDBG_WAVE_CNTL3__STALL_CS7_MASK 0x00001000L +#define SPI_GDBG_WAVE_CNTL3__STALL_DURATION_MASK 0x0FFFE000L +#define SPI_GDBG_WAVE_CNTL3__STALL_MULT_MASK 0x10000000L +//SPI_RESET_DEBUG +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x00000001L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x00000002L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x00000004L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x00000008L +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x00000010L +//GDS_COMPUTE_MAX_WAVE_ID +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0x00000FFFL +//SPI_ARB_CNTL_0 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT__SHIFT 0x0 +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT__SHIFT 0x4 +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT__SHIFT 0x8 +#define SPI_ARB_CNTL_0__EXP_ARB_COL_WT_MASK 0x0000000FL +#define SPI_ARB_CNTL_0__EXP_ARB_POS_WT_MASK 0x000000F0L +#define SPI_ARB_CNTL_0__EXP_ARB_GDS_WT_MASK 0x00000F00L +//SPI_FEATURE_CTRL +#define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT__SHIFT 0x0 +#define SPI_FEATURE_CTRL__RA_PROBE_IGNORE__SHIFT 0x4 +#define SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT__SHIFT 0x5 +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL__SHIFT 0xb +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL__SHIFT 0xd +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE__SHIFT 0xe +#define SPI_FEATURE_CTRL__TUNNELING_WAVE_LIMIT_MASK 0x0000000FL +#define SPI_FEATURE_CTRL__RA_PROBE_IGNORE_MASK 0x00000010L +#define SPI_FEATURE_CTRL__PS_THROTTLE_MAX_WAVE_LIMIT_MASK 0x000007E0L +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_WIF_CTRL_MASK 0x00001800L +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_OOO_CTRL_MASK 0x00002000L +#define SPI_FEATURE_CTRL__RA_PROBE_SKEW_DISABLE_MASK 0x00004000L +//SPI_SHADER_RSRC_LIMIT_CTRL +#define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32__SHIFT 0x0 +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32__SHIFT 0x5 +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE__SHIFT 0xc +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT__SHIFT 0xd +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL__SHIFT 0x13 +#define SPI_SHADER_RSRC_LIMIT_CTRL__NAMED_BARRIER_LIMIT__SHIFT 0x14 +#define SPI_SHADER_RSRC_LIMIT_CTRL__CLUSTER_LIMIT__SHIFT 0x1c +#define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE__SHIFT 0x1f +#define SPI_SHADER_RSRC_LIMIT_CTRL__WAVES_PER_SIMD32_MASK 0x0000001FL +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_PER_SIMD32_MASK 0x00000FE0L +#define SPI_SHADER_RSRC_LIMIT_CTRL__VGPR_WRAP_DISABLE_MASK 0x00001000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_MASK 0x0007E000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__BARRIER_LIMIT_HIERARCHY_LEVEL_MASK 0x00080000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__NAMED_BARRIER_LIMIT_MASK 0x00F00000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__CLUSTER_LIMIT_MASK 0x70000000L +#define SPI_SHADER_RSRC_LIMIT_CTRL__PERFORMANCE_LIMIT_ENABLE_MASK 0x80000000L +//PC_CONFIG_CNTL_0 +#define PC_CONFIG_CNTL_0__PQ_FIFO_DEPTH__SHIFT 0x0 +#define PC_CONFIG_CNTL_0__READ_RET_DEPTH__SHIFT 0x5 +#define PC_CONFIG_CNTL_0__MAX_PRIMS_PER_PROBE__SHIFT 0xa +#define PC_CONFIG_CNTL_0__GL1_CREDIT_COUNT__SHIFT 0xe +#define PC_CONFIG_CNTL_0__SC_PC_RATE_CNTL__SHIFT 0x12 +#define PC_CONFIG_CNTL_0__MW_PQ_RATE_CNTL__SHIFT 0x16 +#define PC_CONFIG_CNTL_0__PC_DEALLOC_TIMEOUT__SHIFT 0x1a +#define PC_CONFIG_CNTL_0__MW_DISABLE_EARLY_HIT__SHIFT 0x1e +#define PC_CONFIG_CNTL_0__DISABLE_DEALLOC_ON_TIMEOUT__SHIFT 0x1f +#define PC_CONFIG_CNTL_0__PQ_FIFO_DEPTH_MASK 0x0000001FL +#define PC_CONFIG_CNTL_0__READ_RET_DEPTH_MASK 0x000003E0L +#define PC_CONFIG_CNTL_0__MAX_PRIMS_PER_PROBE_MASK 0x00003C00L +#define PC_CONFIG_CNTL_0__GL1_CREDIT_COUNT_MASK 0x0003C000L +#define PC_CONFIG_CNTL_0__SC_PC_RATE_CNTL_MASK 0x003C0000L +#define PC_CONFIG_CNTL_0__MW_PQ_RATE_CNTL_MASK 0x03C00000L +#define PC_CONFIG_CNTL_0__PC_DEALLOC_TIMEOUT_MASK 0x3C000000L +#define PC_CONFIG_CNTL_0__MW_DISABLE_EARLY_HIT_MASK 0x40000000L +#define PC_CONFIG_CNTL_0__DISABLE_DEALLOC_ON_TIMEOUT_MASK 0x80000000L +//PC_CONFIG_CNTL_1 +#define PC_CONFIG_CNTL_1__DISABLE_LWC_SLOT_REUSE__SHIFT 0x0 +#define PC_CONFIG_CNTL_1__DISABLE_LWC_WAVE_REUSE__SHIFT 0x1 +#define PC_CONFIG_CNTL_1__LIMIT_BANK_ACCESS__SHIFT 0x2 +#define PC_CONFIG_CNTL_1__FORCE_BANK_SERIALIZE__SHIFT 0x3 +#define PC_CONFIG_CNTL_1__ENABLE_FIFO_DEBUG_WRITE__SHIFT 0x4 +#define PC_CONFIG_CNTL_1__DEBUG_REG_EN__SHIFT 0x5 +#define PC_CONFIG_CNTL_1__DEBUG_GROUP_SEL__SHIFT 0x6 +#define PC_CONFIG_CNTL_1__FORCE_SA_SERIALIZE__SHIFT 0xc +#define PC_CONFIG_CNTL_1__PC_GL1H_FGCG_OVERRIDE__SHIFT 0xd +#define PC_CONFIG_CNTL_1__PC_LDS_FGCG_OVERRIDE__SHIFT 0xe +#define PC_CONFIG_CNTL_1__PC_MAX_BCD__SHIFT 0xf +#define PC_CONFIG_CNTL_1__DISABLE_DEALLOC_ON_EVENT__SHIFT 0x11 +#define PC_CONFIG_CNTL_1__MAX_PSTATE_IDS__SHIFT 0x12 +#define PC_CONFIG_CNTL_1__MAX_PC_SPI_PROBES__SHIFT 0x14 +#define PC_CONFIG_CNTL_1__CMM_USE_POLICY__SHIFT 0x18 +#define PC_CONFIG_CNTL_1__SPECULATIVE_DATA_READ__SHIFT 0x1b +#define PC_CONFIG_CNTL_1__CMM_SCOPE__SHIFT 0x1d +#define PC_CONFIG_CNTL_1__DISABLE_DEALLOC_ON_PC_IDLE__SHIFT 0x1f +#define PC_CONFIG_CNTL_1__DISABLE_LWC_SLOT_REUSE_MASK 0x00000001L +#define PC_CONFIG_CNTL_1__DISABLE_LWC_WAVE_REUSE_MASK 0x00000002L +#define PC_CONFIG_CNTL_1__LIMIT_BANK_ACCESS_MASK 0x00000004L +#define PC_CONFIG_CNTL_1__FORCE_BANK_SERIALIZE_MASK 0x00000008L +#define PC_CONFIG_CNTL_1__ENABLE_FIFO_DEBUG_WRITE_MASK 0x00000010L +#define PC_CONFIG_CNTL_1__DEBUG_REG_EN_MASK 0x00000020L +#define PC_CONFIG_CNTL_1__DEBUG_GROUP_SEL_MASK 0x00000FC0L +#define PC_CONFIG_CNTL_1__FORCE_SA_SERIALIZE_MASK 0x00001000L +#define PC_CONFIG_CNTL_1__PC_GL1H_FGCG_OVERRIDE_MASK 0x00002000L +#define PC_CONFIG_CNTL_1__PC_LDS_FGCG_OVERRIDE_MASK 0x00004000L +#define PC_CONFIG_CNTL_1__PC_MAX_BCD_MASK 0x00018000L +#define PC_CONFIG_CNTL_1__DISABLE_DEALLOC_ON_EVENT_MASK 0x00020000L +#define PC_CONFIG_CNTL_1__MAX_PSTATE_IDS_MASK 0x000C0000L +#define PC_CONFIG_CNTL_1__MAX_PC_SPI_PROBES_MASK 0x00F00000L +#define PC_CONFIG_CNTL_1__CMM_USE_POLICY_MASK 0x07000000L +#define PC_CONFIG_CNTL_1__SPECULATIVE_DATA_READ_MASK 0x18000000L +#define PC_CONFIG_CNTL_1__CMM_SCOPE_MASK 0x60000000L +#define PC_CONFIG_CNTL_1__DISABLE_DEALLOC_ON_PC_IDLE_MASK 0x80000000L +//SPI_COMPUTE_WF_CTX_SAVE_STATUS +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY__SHIFT 0x0 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY__SHIFT 0x1 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY__SHIFT 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY__SHIFT 0x3 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY__SHIFT 0x4 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY__SHIFT 0x5 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY__SHIFT 0x6 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY__SHIFT 0x7 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY__SHIFT 0x8 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY__SHIFT 0x9 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY__SHIFT 0xa +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY__SHIFT 0xb +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY__SHIFT 0xc +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY__SHIFT 0xd +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY__SHIFT 0xe +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY__SHIFT 0xf +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY__SHIFT 0x10 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY__SHIFT 0x11 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY__SHIFT 0x12 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY__SHIFT 0x13 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY__SHIFT 0x14 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY__SHIFT 0x15 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY__SHIFT 0x16 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY__SHIFT 0x17 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY__SHIFT 0x18 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY__SHIFT 0x19 +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY__SHIFT 0x1a +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY__SHIFT 0x1b +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY__SHIFT 0x1c +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY__SHIFT 0x1d +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY__SHIFT 0x1e +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY__SHIFT 0x1f +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE0_SAVE_BUSY_MASK 0x00000001L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE1_SAVE_BUSY_MASK 0x00000002L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE2_SAVE_BUSY_MASK 0x00000004L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE3_SAVE_BUSY_MASK 0x00000008L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE4_SAVE_BUSY_MASK 0x00000010L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE5_SAVE_BUSY_MASK 0x00000020L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE6_SAVE_BUSY_MASK 0x00000040L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE0_QUEUE7_SAVE_BUSY_MASK 0x00000080L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE0_SAVE_BUSY_MASK 0x00000100L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE1_SAVE_BUSY_MASK 0x00000200L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE2_SAVE_BUSY_MASK 0x00000400L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE3_SAVE_BUSY_MASK 0x00000800L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE4_SAVE_BUSY_MASK 0x00001000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE5_SAVE_BUSY_MASK 0x00002000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE6_SAVE_BUSY_MASK 0x00004000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE1_QUEUE7_SAVE_BUSY_MASK 0x00008000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE0_SAVE_BUSY_MASK 0x00010000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE1_SAVE_BUSY_MASK 0x00020000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE2_SAVE_BUSY_MASK 0x00040000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE3_SAVE_BUSY_MASK 0x00080000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE4_SAVE_BUSY_MASK 0x00100000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE5_SAVE_BUSY_MASK 0x00200000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE6_SAVE_BUSY_MASK 0x00400000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE2_QUEUE7_SAVE_BUSY_MASK 0x00800000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE0_SAVE_BUSY_MASK 0x01000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE1_SAVE_BUSY_MASK 0x02000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE2_SAVE_BUSY_MASK 0x04000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE3_SAVE_BUSY_MASK 0x08000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE4_SAVE_BUSY_MASK 0x10000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE5_SAVE_BUSY_MASK 0x20000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE6_SAVE_BUSY_MASK 0x40000000L +#define SPI_COMPUTE_WF_CTX_SAVE_STATUS__PIPE3_QUEUE7_SAVE_BUSY_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_utcl1dec +//UTCL1_CTRL_0 +#define UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE__SHIFT 0x0 +#define UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE__SHIFT 0x1 +#define UTCL1_CTRL_0__UTCL1_MH_B2B_DUPLICATES_DET_DISABLE__SHIFT 0x2 +#define UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS_UNIFIED_IF__SHIFT 0x3 +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS__SHIFT 0x9 +#define UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE__SHIFT 0xd +#define UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE__SHIFT 0xe +#define UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE__SHIFT 0xf +#define UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID__SHIFT 0x10 +#define UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL__SHIFT 0x11 +#define UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE__SHIFT 0x12 +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE__SHIFT 0x13 +#define UTCL1_CTRL_0__GCRD_FGCG_DISABLE__SHIFT 0x14 +#define UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE__SHIFT 0x15 +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES__SHIFT 0x16 +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING__SHIFT 0x17 +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER__SHIFT 0x18 +#define UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL__SHIFT 0x19 +#define UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE__SHIFT 0x1b +#define UTCL1_CTRL_0__UTCL1_HIT_DETECTION_BASED_ON_PAGE_SIZE__SHIFT 0x1d +#define UTCL1_CTRL_0__UTCL1_MH_DUPL_DETECT_ON_NATIVE_PG_SZ__SHIFT 0x1e +#define UTCL1_CTRL_0__UTCL1_FORCE_INV_ALL__SHIFT 0x1f +#define UTCL1_CTRL_0__UTCL1_L0_REQ_VFIFO_DISABLE_MASK 0x00000001L +#define UTCL1_CTRL_0__UTCL1_UTCL2_INVACK_CDC_FIFO_DISABLE_MASK 0x00000002L +#define UTCL1_CTRL_0__UTCL1_MH_B2B_DUPLICATES_DET_DISABLE_MASK 0x00000004L +#define UTCL1_CTRL_0__UTCL1_UTCL2_REQ_CREDITS_UNIFIED_IF_MASK 0x000001F8L +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_CREDITS_MASK 0x00001E00L +#define UTCL1_CTRL_0__UTCL1_LIMIT_INV_TO_ONE_MASK 0x00002000L +#define UTCL1_CTRL_0__UTCL1_LIMIT_XLAT_TO_ONE_MASK 0x00004000L +#define UTCL1_CTRL_0__UTCL1_UTCL2_FGCG_REPEATERS_OVERRIDE_MASK 0x00008000L +#define UTCL1_CTRL_0__UTCL1_INV_FILTER_VMID_MASK 0x00010000L +#define UTCL1_CTRL_0__UTCL1_RANGE_INV_FORCE_CHK_ALL_MASK 0x00020000L +#define UTCL1_CTRL_0__UTCL1_UTCL0_RET_FGCG_REPEATERS_OVERRIDE_MASK 0x00040000L +#define UTCL1_CTRL_0__UTCL1_UTCL0_INVREQ_FGCG_REPEATERS_OVERRIDE_MASK 0x00080000L +#define UTCL1_CTRL_0__GCRD_FGCG_DISABLE_MASK 0x00100000L +#define UTCL1_CTRL_0__UTCL1_MH_RANGE_INV_TO_VMID_OVERRIDE_MASK 0x00200000L +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_DUPLICATES_MASK 0x00400000L +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_REQUEST_SQUASHING_MASK 0x00800000L +#define UTCL1_CTRL_0__UTCL1_MH_DISABLE_RECENT_BUFFER_MASK 0x01000000L +#define UTCL1_CTRL_0__UTCL1_XLAT_FAULT_LOCK_CTRL_MASK 0x06000000L +#define UTCL1_CTRL_0__UTCL1_REDUCE_CC_SIZE_MASK 0x18000000L +#define UTCL1_CTRL_0__UTCL1_HIT_DETECTION_BASED_ON_PAGE_SIZE_MASK 0x20000000L +#define UTCL1_CTRL_0__UTCL1_MH_DUPL_DETECT_ON_NATIVE_PG_SZ_MASK 0x40000000L +#define UTCL1_CTRL_0__UTCL1_FORCE_INV_ALL_MASK 0x80000000L +//UTCL1_UTCL0_INVREQ_DISABLE +#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE__SHIFT 0x0 +#define UTCL1_UTCL0_INVREQ_DISABLE__UTCL1_UTCL0_INVREQ_DISABLE_MASK 0xFFFFFFFFL +//UTCL1_CTRL_2 +#define UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD__SHIFT 0x0 +#define UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE__SHIFT 0x4 +#define UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM__SHIFT 0xa +#define UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE__SHIFT 0xb +#define UTCL1_CTRL_2__UTCL1_SPARE0__SHIFT 0xc +#define UTCL1_CTRL_2__UTCL2_UTCL1_RET_FGCG_REPEATERS_OVERRIDE__SHIFT 0xd +#define UTCL1_CTRL_2__UTCL1_IDENTITY_MODE_CONFIG_SELECTOR__SHIFT 0xe +#define UTCL1_CTRL_2__UTCL1_UTCL2_REQ_CREDITS_SA01__SHIFT 0x14 +#define UTCL1_CTRL_2__UTCL1_UTCL2_REQ_CREDITS_SAX__SHIFT 0x1a +#define UTCL1_CTRL_2__UTCL1_RNG_TO_VMID_INV_OVRD_MASK 0x0000000FL +#define UTCL1_CTRL_2__UTCL1_PMM_INTERRUPT_CREDITS_OVERRIDE_MASK 0x000003F0L +#define UTCL1_CTRL_2__UTCL1_CACHE_WRITE_PERM_MASK 0x00000400L +#define UTCL1_CTRL_2__UTCL1_PAGE_OVRD_DISABLE_MASK 0x00000800L +#define UTCL1_CTRL_2__UTCL1_SPARE0_MASK 0x00001000L +#define UTCL1_CTRL_2__UTCL2_UTCL1_RET_FGCG_REPEATERS_OVERRIDE_MASK 0x00002000L +#define UTCL1_CTRL_2__UTCL1_IDENTITY_MODE_CONFIG_SELECTOR_MASK 0x000FC000L +#define UTCL1_CTRL_2__UTCL1_UTCL2_REQ_CREDITS_SA01_MASK 0x03F00000L +#define UTCL1_CTRL_2__UTCL1_UTCL2_REQ_CREDITS_SAX_MASK 0xFC000000L +//UTCL1_FIFO_SIZING +#define UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH__SHIFT 0x0 +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW__SHIFT 0x3 +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH__SHIFT 0x10 +#define UTCL1_FIFO_SIZING__UTCL1_UTCL2_INVACK_CDC_FIFO_THRESH_MASK 0x00000007L +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_LOW_MASK 0x0000FFF8L +#define UTCL1_FIFO_SIZING__UTCL1_GENERAL_SIZING_CTRL_HIGH_MASK 0xFFFF0000L +//GCRD_SA0_TARGETS_DISABLE +#define GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE__SHIFT 0x0 +#define GCRD_SA0_TARGETS_DISABLE__GCRD_SA0_TARGETS_DISABLE_MASK 0x00FFFFFFL +//GCRD_SA1_TARGETS_DISABLE +#define GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE__SHIFT 0x0 +#define GCRD_SA1_TARGETS_DISABLE__GCRD_SA1_TARGETS_DISABLE_MASK 0x00FFFFFFL +//GCRD_CREDIT_SAFE +#define GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG__SHIFT 0x0 +#define GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG__SHIFT 0x4 +#define GCRD_CREDIT_SAFE__GCRD_RSP_CREDIT_SAFE_REG__SHIFT 0x8 +#define GCRD_CREDIT_SAFE__GCRD_CHAIN_CREDIT_SAFE_REG_MASK 0x00000007L +#define GCRD_CREDIT_SAFE__GCRD_TARGET_CREDIT_SAFE_REG_MASK 0x00000070L +#define GCRD_CREDIT_SAFE__GCRD_RSP_CREDIT_SAFE_REG_MASK 0x00000F00L +//UTCL1_IDENTITY_MODE0 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE0__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE0__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE0__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE1 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE1__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE1__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE1__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE2 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE2__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE2__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE2__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE3 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE3__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE3__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE3__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE4 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE4__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE4__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE4__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE5 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE5__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE5__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE5__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE6 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE6__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE6__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE6__RESERVED_MASK 0xFE000000L +//UTCL1_IDENTITY_MODE7 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_SNOOP__SHIFT 0x0 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_FRAG_SIZE__SHIFT 0x1 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PERM_GRANTED__SHIFT 0x7 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PERM_FAULT__SHIFT 0xb +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_XNACK__SHIFT 0xc +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PTE_TMZ__SHIFT 0xe +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_NO_PTE__SHIFT 0xf +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_SPA__SHIFT 0x10 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_IOSTEER__SHIFT 0x11 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_MTYPE__SHIFT 0x12 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_D__SHIFT 0x14 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PREFETCH_CODE__SHIFT 0x15 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_TEE__SHIFT 0x17 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_HDM__SHIFT 0x18 +#define UTCL1_IDENTITY_MODE7__RESERVED__SHIFT 0x19 +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_SNOOP_MASK 0x00000001L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_FRAG_SIZE_MASK 0x0000007EL +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PERM_GRANTED_MASK 0x00000780L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PERM_FAULT_MASK 0x00000800L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_XNACK_MASK 0x00003000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PTE_TMZ_MASK 0x00004000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_NO_PTE_MASK 0x00008000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_SPA_MASK 0x00010000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_IOSTEER_MASK 0x00020000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_MTYPE_MASK 0x000C0000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_D_MASK 0x00100000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_PREFETCH_CODE_MASK 0x00600000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_TEE_MASK 0x00800000L +#define UTCL1_IDENTITY_MODE7__UTCL1_UTCL0_RET_HDM_MASK 0x01000000L +#define UTCL1_IDENTITY_MODE7__RESERVED_MASK 0xFE000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_tcpdec +//TCP_INVALIDATE +#define TCP_INVALIDATE__START__SHIFT 0x0 +#define TCP_INVALIDATE__START_MASK 0x00000001L +//TCP_STATUS +#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 +#define TCP_STATUS__INPUT_BUSY_PORT0__SHIFT 0x1 +#define TCP_STATUS__INPUT_BUSY_PORT1__SHIFT 0x2 +#define TCP_STATUS__ADRS_BUSY_PORT0__SHIFT 0x3 +#define TCP_STATUS__ADRS_BUSY_PORT1__SHIFT 0x4 +#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x5 +#define TCP_STATUS__VM_BUSY__SHIFT 0x6 +#define TCP_STATUS__MEMIF_BUSY__SHIFT 0x7 +#define TCP_STATUS__GCR_BUSY__SHIFT 0x8 +#define TCP_STATUS__CNTRL_BUSY_PORT0__SHIFT 0x9 +#define TCP_STATUS__CNTRL_BUSY_PORT1__SHIFT 0xa +#define TCP_STATUS__LFIFO_BUSY_PORT0__SHIFT 0xb +#define TCP_STATUS__LFIFO_BUSY_PORT1__SHIFT 0xc +#define TCP_STATUS__OFIFO_BUSY_PORT0__SHIFT 0xd +#define TCP_STATUS__OFIFO_BUSY_PORT1__SHIFT 0xe +#define TCP_STATUS__OFIFO_QUEUE_BUSY_PORT0__SHIFT 0xf +#define TCP_STATUS__OFIFO_QUEUE_BUSY_PORT1__SHIFT 0x12 +#define TCP_STATUS__READ_BUSY_PORT1__SHIFT 0x15 +#define TCP_STATUS__READ_BUSY_PORT0__SHIFT 0x16 +#define TCP_STATUS__CL_PENDING__SHIFT 0x17 +#define TCP_STATUS__VRX_BUSY__SHIFT 0x18 +#define TCP_STATUS__PKR_BUSY_PORT0__SHIFT 0x19 +#define TCP_STATUS__PKR_BUSY_PORT1__SHIFT 0x1a +#define TCP_STATUS__LDS_BUSY_PORT0__SHIFT 0x1b +#define TCP_STATUS__LDS_BUSY_PORT1__SHIFT 0x1c +#define TCP_STATUS__XNACK_PRT__SHIFT 0x1d +#define TCP_STATUS__TCP_BUSY_MASK 0x00000001L +#define TCP_STATUS__INPUT_BUSY_PORT0_MASK 0x00000002L +#define TCP_STATUS__INPUT_BUSY_PORT1_MASK 0x00000004L +#define TCP_STATUS__ADRS_BUSY_PORT0_MASK 0x00000008L +#define TCP_STATUS__ADRS_BUSY_PORT1_MASK 0x00000010L +#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x00000020L +#define TCP_STATUS__VM_BUSY_MASK 0x00000040L +#define TCP_STATUS__MEMIF_BUSY_MASK 0x00000080L +#define TCP_STATUS__GCR_BUSY_MASK 0x00000100L +#define TCP_STATUS__CNTRL_BUSY_PORT0_MASK 0x00000200L +#define TCP_STATUS__CNTRL_BUSY_PORT1_MASK 0x00000400L +#define TCP_STATUS__LFIFO_BUSY_PORT0_MASK 0x00000800L +#define TCP_STATUS__LFIFO_BUSY_PORT1_MASK 0x00001000L +#define TCP_STATUS__OFIFO_BUSY_PORT0_MASK 0x00002000L +#define TCP_STATUS__OFIFO_BUSY_PORT1_MASK 0x00004000L +#define TCP_STATUS__OFIFO_QUEUE_BUSY_PORT0_MASK 0x00018000L +#define TCP_STATUS__OFIFO_QUEUE_BUSY_PORT1_MASK 0x000C0000L +#define TCP_STATUS__READ_BUSY_PORT1_MASK 0x00200000L +#define TCP_STATUS__READ_BUSY_PORT0_MASK 0x00400000L +#define TCP_STATUS__CL_PENDING_MASK 0x00800000L +#define TCP_STATUS__VRX_BUSY_MASK 0x01000000L +#define TCP_STATUS__PKR_BUSY_PORT0_MASK 0x02000000L +#define TCP_STATUS__PKR_BUSY_PORT1_MASK 0x04000000L +#define TCP_STATUS__LDS_BUSY_PORT0_MASK 0x08000000L +#define TCP_STATUS__LDS_BUSY_PORT1_MASK 0x10000000L +#define TCP_STATUS__XNACK_PRT_MASK 0x20000000L +//TCP_CNTL +#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 +#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 +#define TCP_CNTL__STORE_ATOMIC_COLLAPSE_CLAUSE_LIMIT__SHIFT 0x2 +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 +#define TCP_CNTL__TD_DATA_EN_OVERRIDE__SHIFT 0x6 +#define TCP_CNTL__TCP_SPILL_CACHE_DISABLE__SHIFT 0x7 +#define TCP_CNTL__DISABLE_WRITE_COMBINING__SHIFT 0x9 +#define TCP_CNTL__FORCE_SCOPE_EOW__SHIFT 0xa +#define TCP_CNTL__FORCE_TEMPORAL_EOW__SHIFT 0xb +#define TCP_CNTL__DISABLE_DCOPY_SET_THRASH_OPT__SHIFT 0xc +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf +#define TCP_CNTL__FORCE_EOW_SET_CNT__SHIFT 0x16 +#define TCP_CNTL__DISABLE_FULL_CL_ACCESS__SHIFT 0x1b +#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c +#define TCP_CNTL__ENABLE_64B_SCRATCH_STRIDE__SHIFT 0x1d +#define TCP_CNTL__ASTC_VE_MSB_TOLERANT__SHIFT 0x1f +#define TCP_CNTL__FORCE_HIT_MASK 0x00000001L +#define TCP_CNTL__FORCE_MISS_MASK 0x00000002L +#define TCP_CNTL__STORE_ATOMIC_COLLAPSE_CLAUSE_LIMIT_MASK 0x0000001CL +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x00000020L +#define TCP_CNTL__TD_DATA_EN_OVERRIDE_MASK 0x00000040L +#define TCP_CNTL__TCP_SPILL_CACHE_DISABLE_MASK 0x00000080L +#define TCP_CNTL__DISABLE_WRITE_COMBINING_MASK 0x00000200L +#define TCP_CNTL__FORCE_SCOPE_EOW_MASK 0x00000400L +#define TCP_CNTL__FORCE_TEMPORAL_EOW_MASK 0x00000800L +#define TCP_CNTL__DISABLE_DCOPY_SET_THRASH_OPT_MASK 0x00001000L +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x001F8000L +#define TCP_CNTL__FORCE_EOW_SET_CNT_MASK 0x07C00000L +#define TCP_CNTL__DISABLE_FULL_CL_ACCESS_MASK 0x08000000L +#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000L +#define TCP_CNTL__ENABLE_64B_SCRATCH_STRIDE_MASK 0x20000000L +#define TCP_CNTL__ASTC_VE_MSB_TOLERANT_MASK 0x80000000L +//TCP_CNTL2 +#define TCP_CNTL2__TCP_FMT_MGCG_DISABLE__SHIFT 0x8 +#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE__SHIFT 0x9 +#define TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE__SHIFT 0xa +#define TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE__SHIFT 0xb +#define TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE__SHIFT 0xc +#define TCP_CNTL2__V64_COMBINE_ENABLE__SHIFT 0xd +#define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE__SHIFT 0xe +#define TCP_CNTL2__TX_SP_READ_FGCG_DISABLE__SHIFT 0xf +#define TCP_CNTL2__POWER_OPT_DISABLE__SHIFT 0x10 +#define TCP_CNTL2__GCR_RSP_FGCG_DISABLE__SHIFT 0x11 +#define TCP_CNTL2__PERF_EN_OVERRIDE__SHIFT 0x12 +#define TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE__SHIFT 0x16 +#define TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE__SHIFT 0x17 +#define TCP_CNTL2__TCP_FORCE_2X_TO_LOAD__SHIFT 0x18 +#define TCP_CNTL2__DISABLE_FLAT_BUF_DATARAM_SWIZZLE__SHIFT 0x19 +#define TCP_CNTL2__VC_UTC_PERMISSIONS_ATOMIC_ALL_SCOPES__SHIFT 0x1a +#define TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE__SHIFT 0x1b +#define TCP_CNTL2__TCP_REQ_MGCG_DISABLE__SHIFT 0x1d +#define TCP_CNTL2__TCP_MISS_MGCG_DISABLE__SHIFT 0x1e +#define TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING__SHIFT 0x1f +#define TCP_CNTL2__TCP_FMT_MGCG_DISABLE_MASK 0x00000100L +#define TCP_CNTL2__TCPF_LATENCY_BYPASS_DISABLE_MASK 0x00000200L +#define TCP_CNTL2__TCP_WRITE_DATA_MGCG_DISABLE_MASK 0x00000400L +#define TCP_CNTL2__TCP_INNER_BLOCK_MGCG_DISABLE_MASK 0x00000800L +#define TCP_CNTL2__TCP_ADRS_IMG_CALC_MGCG_DISABLE_MASK 0x00001000L +#define TCP_CNTL2__V64_COMBINE_ENABLE_MASK 0x00002000L +#define TCP_CNTL2__TAGRAM_ADDR_SWIZZLE_DISABLE_MASK 0x00004000L +#define TCP_CNTL2__TX_SP_READ_FGCG_DISABLE_MASK 0x00008000L +#define TCP_CNTL2__POWER_OPT_DISABLE_MASK 0x00010000L +#define TCP_CNTL2__GCR_RSP_FGCG_DISABLE_MASK 0x00020000L +#define TCP_CNTL2__PERF_EN_OVERRIDE_MASK 0x000C0000L +#define TCP_CNTL2__TCP_GL1_REQ_CLKEN_DISABLE_MASK 0x00400000L +#define TCP_CNTL2__TCP_GL1R_SRC_CLKEN_DISABLE_MASK 0x00800000L +#define TCP_CNTL2__TCP_FORCE_2X_TO_LOAD_MASK 0x01000000L +#define TCP_CNTL2__DISABLE_FLAT_BUF_DATARAM_SWIZZLE_MASK 0x02000000L +#define TCP_CNTL2__VC_UTC_PERMISSIONS_ATOMIC_ALL_SCOPES_MASK 0x04000000L +#define TCP_CNTL2__TAGRAM_XY_BIAS_OVERRIDE_MASK 0x18000000L +#define TCP_CNTL2__TCP_REQ_MGCG_DISABLE_MASK 0x20000000L +#define TCP_CNTL2__TCP_MISS_MGCG_DISABLE_MASK 0x40000000L +#define TCP_CNTL2__DISABLE_MIPMAP_PARAM_CALC_SELF_GATING_MASK 0x80000000L +//TCP_CREDIT +#define TCP_CREDIT__LFIFO_RAM_DEPTH__SHIFT 0x0 +#define TCP_CREDIT__GL1_REQ_CREDIT__SHIFT 0xa +#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x11 +#define TCP_CREDIT__TD_RAM_CREDIT__SHIFT 0x17 +#define TCP_CREDIT__TD_DATA_CREDIT__SHIFT 0x1d +#define TCP_CREDIT__LFIFO_RAM_DEPTH_MASK 0x000003FFL +#define TCP_CREDIT__GL1_REQ_CREDIT_MASK 0x0001FC00L +#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x007E0000L +#define TCP_CREDIT__TD_RAM_CREDIT_MASK 0x0F800000L +#define TCP_CREDIT__TD_DATA_CREDIT_MASK 0xE0000000L +//TCP_DEBUG_DATA +#define TCP_DEBUG_DATA__DATA__SHIFT 0x0 +#define TCP_DEBUG_DATA__DATA_MASK 0xFFFFFFFFL +//TCP_COMPRESSION_CNTL +#define TCP_COMPRESSION_CNTL__IMAGE_COMPRESSION_OVERRIDE__SHIFT 0x0 +#define TCP_COMPRESSION_CNTL__IMAGE_BYPASS_COMPRESSION__SHIFT 0x1 +#define TCP_COMPRESSION_CNTL__IMAGE_WRITE_COMPRESSION_DISABLE__SHIFT 0x2 +#define TCP_COMPRESSION_CNTL__BUFFER_COMPRESSION_OVERRIDE__SHIFT 0x3 +#define TCP_COMPRESSION_CNTL__BUFFER_BYPASS_COMPRESSION__SHIFT 0x4 +#define TCP_COMPRESSION_CNTL__BUFFER_WRITE_COMPRESSION_DISABLE__SHIFT 0x5 +#define TCP_COMPRESSION_CNTL__FLAT_COMPRESSION_OVERRIDE__SHIFT 0x6 +#define TCP_COMPRESSION_CNTL__FLAT_BYPASS_COMPRESSION__SHIFT 0x7 +#define TCP_COMPRESSION_CNTL__FLAT_WRITE_COMPRESSION_DISABLE__SHIFT 0x8 +#define TCP_COMPRESSION_CNTL__BVH_BYPASS_COMPRESSION__SHIFT 0x9 +#define TCP_COMPRESSION_CNTL__BUF_SPECULATIVE_DATA_READ__SHIFT 0xa +#define TCP_COMPRESSION_CNTL__BUF_MAX_COMP_BLOCK_SIZE__SHIFT 0xc +#define TCP_COMPRESSION_CNTL__BUF_MAX_UNCOMP_BLOCK_SIZE__SHIFT 0xe +#define TCP_COMPRESSION_CNTL__BVH_SPECULATIVE_DATA_READ__SHIFT 0xf +#define TCP_COMPRESSION_CNTL__BVH_MAX_COMP_BLOCK_SIZE__SHIFT 0x11 +#define TCP_COMPRESSION_CNTL__BVH_MAX_UNCOMP_BLOCK_SIZE__SHIFT 0x13 +#define TCP_COMPRESSION_CNTL__IMAGE_COMPRESSION_OVERRIDE_MASK 0x00000001L +#define TCP_COMPRESSION_CNTL__IMAGE_BYPASS_COMPRESSION_MASK 0x00000002L +#define TCP_COMPRESSION_CNTL__IMAGE_WRITE_COMPRESSION_DISABLE_MASK 0x00000004L +#define TCP_COMPRESSION_CNTL__BUFFER_COMPRESSION_OVERRIDE_MASK 0x00000008L +#define TCP_COMPRESSION_CNTL__BUFFER_BYPASS_COMPRESSION_MASK 0x00000010L +#define TCP_COMPRESSION_CNTL__BUFFER_WRITE_COMPRESSION_DISABLE_MASK 0x00000020L +#define TCP_COMPRESSION_CNTL__FLAT_COMPRESSION_OVERRIDE_MASK 0x00000040L +#define TCP_COMPRESSION_CNTL__FLAT_BYPASS_COMPRESSION_MASK 0x00000080L +#define TCP_COMPRESSION_CNTL__FLAT_WRITE_COMPRESSION_DISABLE_MASK 0x00000100L +#define TCP_COMPRESSION_CNTL__BVH_BYPASS_COMPRESSION_MASK 0x00000200L +#define TCP_COMPRESSION_CNTL__BUF_SPECULATIVE_DATA_READ_MASK 0x00000C00L +#define TCP_COMPRESSION_CNTL__BUF_MAX_COMP_BLOCK_SIZE_MASK 0x00003000L +#define TCP_COMPRESSION_CNTL__BUF_MAX_UNCOMP_BLOCK_SIZE_MASK 0x00004000L +#define TCP_COMPRESSION_CNTL__BVH_SPECULATIVE_DATA_READ_MASK 0x00018000L +#define TCP_COMPRESSION_CNTL__BVH_MAX_COMP_BLOCK_SIZE_MASK 0x00060000L +#define TCP_COMPRESSION_CNTL__BVH_MAX_UNCOMP_BLOCK_SIZE_MASK 0x00080000L +//TCP_ARB +#define TCP_ARB__WEIGHT__SHIFT 0x0 +#define TCP_ARB__END_CLAUSE__SHIFT 0x3 +#define TCP_ARB__WEIGHT_MASK 0x00000007L +#define TCP_ARB__END_CLAUSE_MASK 0x00000008L +//TCP_UTCL0_CNTL1 +#define TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define TCP_UTCL0_CNTL1__GPUVM_64K_DEF__SHIFT 0x1 +#define TCP_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define TCP_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 +#define TCP_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define TCP_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 +#define TCP_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x11 +#define TCP_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x16 +#define TCP_UTCL0_CNTL1__ATOMIC_REQUESTER_EN__SHIFT 0x17 +#define TCP_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x18 +#define TCP_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x19 +#define TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1a +#define TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1d +#define TCP_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define TCP_UTCL0_CNTL1__GPUVM_64K_DEF_MASK 0x00000002L +#define TCP_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define TCP_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L +#define TCP_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define TCP_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L +#define TCP_UTCL0_CNTL1__REG_INV_VMID_MASK 0x001E0000L +#define TCP_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x00400000L +#define TCP_UTCL0_CNTL1__ATOMIC_REQUESTER_EN_MASK 0x00800000L +#define TCP_UTCL0_CNTL1__FORCE_MISS_MASK 0x01000000L +#define TCP_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x02000000L +#define TCP_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x1C000000L +#define TCP_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xE0000000L +//TCP_UTCL0_CNTL2 +#define TCP_UTCL0_CNTL2__SPARE__SHIFT 0x0 +#define TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define TCP_UTCL0_CNTL2__LINE_VALID__SHIFT 0xa +#define TCP_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define TCP_UTCL0_CNTL2__DISABLE_BURST__SHIFT 0x11 +#define TCP_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR__SHIFT 0x12 +#define TCP_UTCL0_CNTL2__PERF_EVENT_RD_WR__SHIFT 0x13 +#define TCP_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID__SHIFT 0x14 +#define TCP_UTCL0_CNTL2__PERF_EVENT_VMID__SHIFT 0x15 +#define TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define TCP_UTCL0_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE__SHIFT 0x1b +#define TCP_UTCL0_CNTL2__THRASHING_ENABLE__SHIFT 0x1c +#define TCP_UTCL0_CNTL2__DISABLE_SPECULATIVE_PREFETCH__SHIFT 0x1d +#define TCP_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define TCP_UTCL0_CNTL2__DISABLE_ILLEGAL_PCIE_ATOMIC__SHIFT 0x1f +#define TCP_UTCL0_CNTL2__SPARE_MASK 0x000000FFL +#define TCP_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define TCP_UTCL0_CNTL2__LINE_VALID_MASK 0x00000400L +#define TCP_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define TCP_UTCL0_CNTL2__DISABLE_BURST_MASK 0x00020000L +#define TCP_UTCL0_CNTL2__ENABLE_PERF_EVENT_RD_WR_MASK 0x00040000L +#define TCP_UTCL0_CNTL2__PERF_EVENT_RD_WR_MASK 0x00080000L +#define TCP_UTCL0_CNTL2__ENABLE_PERF_EVENT_VMID_MASK 0x00100000L +#define TCP_UTCL0_CNTL2__PERF_EVENT_VMID_MASK 0x01E00000L +#define TCP_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define TCP_UTCL0_CNTL2__THRASHING_TIMEOUT_PROTECT_ENABLE_MASK 0x08000000L +#define TCP_UTCL0_CNTL2__THRASHING_ENABLE_MASK 0x10000000L +#define TCP_UTCL0_CNTL2__DISABLE_SPECULATIVE_PREFETCH_MASK 0x20000000L +#define TCP_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define TCP_UTCL0_CNTL2__DISABLE_ILLEGAL_PCIE_ATOMIC_MASK 0x80000000L +//TCP_UTCL0_STATUS +#define TCP_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define TCP_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define TCP_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 +#define TCP_UTCL0_STATUS__TIMEOUT_DETECTED__SHIFT 0x3 +#define TCP_UTCL0_STATUS__VMID_BUSY__SHIFT 0x4 +#define TCP_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define TCP_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define TCP_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L +#define TCP_UTCL0_STATUS__TIMEOUT_DETECTED_MASK 0x00000008L +#define TCP_UTCL0_STATUS__VMID_BUSY_MASK 0x000FFFF0L +//TCP_RQID_HASH_CNTL +#define TCP_RQID_HASH_CNTL__WAVE_ID_LEFT_MASK__SHIFT 0x0 +#define TCP_RQID_HASH_CNTL__WAVE_ID_LEFT_SHIFT__SHIFT 0x4 +#define TCP_RQID_HASH_CNTL__WAVE_ID_RIGHT_MASK__SHIFT 0x7 +#define TCP_RQID_HASH_CNTL__WAVE_ID_RIGHT_SHIFT__SHIFT 0xb +#define TCP_RQID_HASH_CNTL__SIMD_ID_MASK__SHIFT 0xe +#define TCP_RQID_HASH_CNTL__SIMD_ID_SHIFT__SHIFT 0xf +#define TCP_RQID_HASH_CNTL__TYPE_MASK__SHIFT 0x12 +#define TCP_RQID_HASH_CNTL__TYPE_SHIFT__SHIFT 0x14 +#define TCP_RQID_HASH_CNTL__WAVE_ID_LEFT_MASK_MASK 0x0000000FL +#define TCP_RQID_HASH_CNTL__WAVE_ID_LEFT_SHIFT_MASK 0x00000070L +#define TCP_RQID_HASH_CNTL__WAVE_ID_RIGHT_MASK_MASK 0x00000780L +#define TCP_RQID_HASH_CNTL__WAVE_ID_RIGHT_SHIFT_MASK 0x00003800L +#define TCP_RQID_HASH_CNTL__SIMD_ID_MASK_MASK 0x00004000L +#define TCP_RQID_HASH_CNTL__SIMD_ID_SHIFT_MASK 0x00038000L +#define TCP_RQID_HASH_CNTL__TYPE_MASK_MASK 0x000C0000L +#define TCP_RQID_HASH_CNTL__TYPE_SHIFT_MASK 0x00700000L +//TCP_SET_HASH_CFG +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_192__SHIFT 0x1 +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_320__SHIFT 0x5 +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_384__SHIFT 0x9 +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_448__SHIFT 0xd +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_192_MASK 0x0000001EL +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_320_MASK 0x000001E0L +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_384_MASK 0x00001E00L +#define TCP_SET_HASH_CFG__SHIFT_BY_FOR_448_MASK 0x0001E000L +//TCP_SET_HASH_MASK_64_SET0 +#define TCP_SET_HASH_MASK_64_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_64_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_64_SET1 +#define TCP_SET_HASH_MASK_64_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_64_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_64_SET2 +#define TCP_SET_HASH_MASK_64_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_64_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_64_SET3 +#define TCP_SET_HASH_MASK_64_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_64_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_128_SET0 +#define TCP_SET_HASH_MASK_128_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_128_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_128_SET1 +#define TCP_SET_HASH_MASK_128_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_128_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_128_SET2 +#define TCP_SET_HASH_MASK_128_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_128_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_128_SET3 +#define TCP_SET_HASH_MASK_128_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_128_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_128_SET4 +#define TCP_SET_HASH_MASK_128_SET4__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_128_SET4__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_192_SET0 +#define TCP_SET_HASH_MASK_192_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_192_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_192_SET1 +#define TCP_SET_HASH_MASK_192_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_192_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_192_SET2 +#define TCP_SET_HASH_MASK_192_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_192_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_192_SET3 +#define TCP_SET_HASH_MASK_192_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_192_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET0 +#define TCP_SET_HASH_MASK_256_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET1 +#define TCP_SET_HASH_MASK_256_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET2 +#define TCP_SET_HASH_MASK_256_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET3 +#define TCP_SET_HASH_MASK_256_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET4 +#define TCP_SET_HASH_MASK_256_SET4__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET4__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_256_SET5 +#define TCP_SET_HASH_MASK_256_SET5__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_256_SET5__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_320_SET0 +#define TCP_SET_HASH_MASK_320_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_320_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_320_SET1 +#define TCP_SET_HASH_MASK_320_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_320_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_320_SET2 +#define TCP_SET_HASH_MASK_320_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_320_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_320_SET3 +#define TCP_SET_HASH_MASK_320_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_320_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_384_SET0 +#define TCP_SET_HASH_MASK_384_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_384_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_384_SET1 +#define TCP_SET_HASH_MASK_384_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_384_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_384_SET2 +#define TCP_SET_HASH_MASK_384_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_384_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_384_SET3 +#define TCP_SET_HASH_MASK_384_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_384_SET3__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_384_SET4 +#define TCP_SET_HASH_MASK_384_SET4__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_384_SET4__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_448_SET0 +#define TCP_SET_HASH_MASK_448_SET0__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_448_SET0__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_448_SET1 +#define TCP_SET_HASH_MASK_448_SET1__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_448_SET1__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_448_SET2 +#define TCP_SET_HASH_MASK_448_SET2__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_448_SET2__MASK_MASK 0x0007FFFFL +//TCP_SET_HASH_MASK_448_SET3 +#define TCP_SET_HASH_MASK_448_SET3__MASK__SHIFT 0x0 +#define TCP_SET_HASH_MASK_448_SET3__MASK_MASK 0x0007FFFFL +//TCP_CNTL3 +#define TCP_CNTL3__TCS_PORT_PRIORITY_EVENT__SHIFT 0x0 +#define TCP_CNTL3__TCS_PORT_PRIORITY_WEIGHT__SHIFT 0x2 +#define TCP_CNTL3__VRX_VC_PORT_PRIORITY_EVENT__SHIFT 0x7 +#define TCP_CNTL3__VRX_VC_PORT_PRIORITY_WEIGHT__SHIFT 0x9 +#define TCP_CNTL3__VRX_LDS_PORT_PRIORITY_EVENT__SHIFT 0xe +#define TCP_CNTL3__VRX_LDS_PORT_PRIORITY_WEIGHT__SHIFT 0x10 +#define TCP_CNTL3__QM_CAC_OUTPUT__SHIFT 0x15 +#define TCP_CNTL3__DISABLE_COALESCING_FOR_PAGE_TRANSLATION__SHIFT 0x1a +#define TCP_CNTL3__OOO_HWT_SHOOTDOWN_DRAIN_DIS__SHIFT 0x1b +#define TCP_CNTL3__ASYNC_INFLIGHT_VRX_SINGLE_PORT__SHIFT 0x1c +#define TCP_CNTL3__VC_DP_INV_STALL_EN__SHIFT 0x1d +#define TCP_CNTL3__DISABLE_EARLY_WRITE_ACK__SHIFT 0x1e +#define TCP_CNTL3__CL_256B_COMBINE_DIS__SHIFT 0x1f +#define TCP_CNTL3__TCS_PORT_PRIORITY_EVENT_MASK 0x00000003L +#define TCP_CNTL3__TCS_PORT_PRIORITY_WEIGHT_MASK 0x0000007CL +#define TCP_CNTL3__VRX_VC_PORT_PRIORITY_EVENT_MASK 0x00000180L +#define TCP_CNTL3__VRX_VC_PORT_PRIORITY_WEIGHT_MASK 0x00003E00L +#define TCP_CNTL3__VRX_LDS_PORT_PRIORITY_EVENT_MASK 0x0000C000L +#define TCP_CNTL3__VRX_LDS_PORT_PRIORITY_WEIGHT_MASK 0x001F0000L +#define TCP_CNTL3__QM_CAC_OUTPUT_MASK 0x00200000L +#define TCP_CNTL3__DISABLE_COALESCING_FOR_PAGE_TRANSLATION_MASK 0x04000000L +#define TCP_CNTL3__OOO_HWT_SHOOTDOWN_DRAIN_DIS_MASK 0x08000000L +#define TCP_CNTL3__ASYNC_INFLIGHT_VRX_SINGLE_PORT_MASK 0x10000000L +#define TCP_CNTL3__VC_DP_INV_STALL_EN_MASK 0x20000000L +#define TCP_CNTL3__DISABLE_EARLY_WRITE_ACK_MASK 0x40000000L +#define TCP_CNTL3__CL_256B_COMBINE_DIS_MASK 0x80000000L +//LDS_CONFIG +#define LDS_CONFIG__CONF_BIT_1__SHIFT 0x0 +#define LDS_CONFIG__PC_CNTRL_OUT_FGCG_OVERRIDE__SHIFT 0x1 +#define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE__SHIFT 0x2 +#define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE__SHIFT 0x3 +#define LDS_CONFIG__CONF_BIT_5__SHIFT 0x4 +#define LDS_CONFIG__CONF_BIT_6__SHIFT 0x5 +#define LDS_CONFIG__CONF_BIT_7__SHIFT 0x6 +#define LDS_CONFIG__CONF_BIT_8__SHIFT 0x7 +#define LDS_CONFIG__PEND_CNT_WIDTH__SHIFT 0x8 +#define LDS_CONFIG__LDSI_ROUNDROBIN_ARB__SHIFT 0xe +#define LDS_CONFIG__CONF_BIT_1_MASK 0x00000001L +#define LDS_CONFIG__PC_CNTRL_OUT_FGCG_OVERRIDE_MASK 0x00000002L +#define LDS_CONFIG__SP_TDDATA_FGCG_OVERRIDE_MASK 0x00000004L +#define LDS_CONFIG__SQC_PERF_FGCG_OVERRIDE_MASK 0x00000008L +#define LDS_CONFIG__CONF_BIT_5_MASK 0x00000010L +#define LDS_CONFIG__CONF_BIT_6_MASK 0x00000020L +#define LDS_CONFIG__CONF_BIT_7_MASK 0x00000040L +#define LDS_CONFIG__CONF_BIT_8_MASK 0x00000080L +#define LDS_CONFIG__PEND_CNT_WIDTH_MASK 0x00003F00L +#define LDS_CONFIG__LDSI_ROUNDROBIN_ARB_MASK 0x00004000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly2_spidec +//SPI_RESOURCE_RESERVE_CU_0 +#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_1 +#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_2 +#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_3 +#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_4 +#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_5 +#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_6 +#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_7 +#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_8 +#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_9 +#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_10 +#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_11 +#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_12 +#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_13 +#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_14 +#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_CU_15 +#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0x0000000FL +#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0x000000F0L +#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0x00000F00L +#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x00007000L +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x00078000L +//SPI_RESOURCE_RESERVE_EN_CU_0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_2 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_3 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_4 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_5 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_6 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_7 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_8 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_9 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_11 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_12 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_13 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_14 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0x00FF0000L +//SPI_RESOURCE_RESERVE_EN_CU_15 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x00000001L +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0x0000FFFEL +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0x00FF0000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly2_tcpdec +//TCP_UTCL0_THRASHING_CTRL +#define TCP_UTCL0_THRASHING_CTRL__THRASHING_EN__SHIFT 0x0 +#define TCP_UTCL0_THRASHING_CTRL__RETRY_FRAGMENT_THRESHOLD_DOWN_EN__SHIFT 0x2 +#define TCP_UTCL0_THRASHING_CTRL__RETRY_FRAGMENT_THRESHOLD_UP_EN__SHIFT 0x3 +#define TCP_UTCL0_THRASHING_CTRL__STALL_TIMEOUT_PROTECT_ENABLE__SHIFT 0x4 +#define TCP_UTCL0_THRASHING_CTRL__STALL_TARGET_FRAGMENT_SIZE__SHIFT 0x5 +#define TCP_UTCL0_THRASHING_CTRL__RETRY_TARGET_FRAGMENT_SIZE__SHIFT 0x9 +#define TCP_UTCL0_THRASHING_CTRL__THRASHING_EN_MASK 0x00000003L +#define TCP_UTCL0_THRASHING_CTRL__RETRY_FRAGMENT_THRESHOLD_DOWN_EN_MASK 0x00000004L +#define TCP_UTCL0_THRASHING_CTRL__RETRY_FRAGMENT_THRESHOLD_UP_EN_MASK 0x00000008L +#define TCP_UTCL0_THRASHING_CTRL__STALL_TIMEOUT_PROTECT_ENABLE_MASK 0x00000010L +#define TCP_UTCL0_THRASHING_CTRL__STALL_TARGET_FRAGMENT_SIZE_MASK 0x000001E0L +#define TCP_UTCL0_THRASHING_CTRL__RETRY_TARGET_FRAGMENT_SIZE_MASK 0x00001E00L +//TCP_UTCL0_RETRY_THRESHOLD_DOWN_COUNTER +#define TCP_UTCL0_RETRY_THRESHOLD_DOWN_COUNTER__DOWN_COUNTER__SHIFT 0x0 +#define TCP_UTCL0_RETRY_THRESHOLD_DOWN_COUNTER__DOWN_COUNTER_MASK 0xFFFFFFFFL +//TCP_UTCL0_RETRY_THRESHOLD_UP_COUNTER +#define TCP_UTCL0_RETRY_THRESHOLD_UP_COUNTER__UP_COUNTER__SHIFT 0x0 +#define TCP_UTCL0_RETRY_THRESHOLD_UP_COUNTER__UP_COUNTER_MASK 0xFFFFFFFFL +//TCP_UTCL0_XNACK_RETRY +#define TCP_UTCL0_XNACK_RETRY__INCR__SHIFT 0x0 +#define TCP_UTCL0_XNACK_RETRY__COUNT__SHIFT 0x8 +#define TCP_UTCL0_XNACK_RETRY__INCR_MASK 0x000000FFL +#define TCP_UTCL0_XNACK_RETRY__COUNT_MASK 0x00000F00L +//TCP_UTCL0_RETRY_TIMER_THRESHOLD_LO +#define TCP_UTCL0_RETRY_TIMER_THRESHOLD_LO__VALUE__SHIFT 0x0 +#define TCP_UTCL0_RETRY_TIMER_THRESHOLD_LO__VALUE_MASK 0xFFFFFFFFL +//TCP_UTCL0_RETRY_TIMER_THRESHOLD_HI +#define TCP_UTCL0_RETRY_TIMER_THRESHOLD_HI__VALUE__SHIFT 0x0 +#define TCP_UTCL0_RETRY_TIMER_THRESHOLD_HI__VALUE_MASK 0xFFFFFFFFL +//TXA_CNTL +#define TXA_CNTL__TA_SQ_XNACK_FGCG_DISABLE__SHIFT 0x0 +#define TXA_CNTL__TXA_CFG_CHG_STALL__SHIFT 0x1 +#define TXA_CNTL__TXA_ALIGNER_LDS_B96_LOAD_CYCLING__SHIFT 0x2 +#define TXA_CNTL__ALIGNER_CREDIT__SHIFT 0x8 +#define TXA_CNTL__ALIGNER_CREDIT_LDS__SHIFT 0x10 +#define TXA_CNTL__DISABLE_ASYNC_LOAD_DIRECT_COPY__SHIFT 0x15 +#define TXA_CNTL__DISABLE_ASYNC_STORE_DIRECT_COPY__SHIFT 0x16 +#define TXA_CNTL__INPUT_XNACK_RESET_CREDIT__SHIFT 0x17 +#define TXA_CNTL__ENABLE_B128_DIRECT_COPY_STORE__SHIFT 0x1a +#define TXA_CNTL__TA_SQ_XNACK_FGCG_DISABLE_MASK 0x00000001L +#define TXA_CNTL__TXA_CFG_CHG_STALL_MASK 0x00000002L +#define TXA_CNTL__TXA_ALIGNER_LDS_B96_LOAD_CYCLING_MASK 0x00000004L +#define TXA_CNTL__ALIGNER_CREDIT_MASK 0x00001F00L +#define TXA_CNTL__ALIGNER_CREDIT_LDS_MASK 0x001F0000L +#define TXA_CNTL__DISABLE_ASYNC_LOAD_DIRECT_COPY_MASK 0x00200000L +#define TXA_CNTL__DISABLE_ASYNC_STORE_DIRECT_COPY_MASK 0x00400000L +#define TXA_CNTL__INPUT_XNACK_RESET_CREDIT_MASK 0x03800000L +#define TXA_CNTL__ENABLE_B128_DIRECT_COPY_STORE_MASK 0x04000000L +//TXA_CNTL_AUX +#define TXA_CNTL_AUX__AUTO_ALIGN_FORMAT__SHIFT 0x9 +#define TXA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE__SHIFT 0x14 +#define TXA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE__SHIFT 0x15 +#define TXA_CNTL_AUX__DETERMINISM_MISC_DISABLE__SHIFT 0x16 +#define TXA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE__SHIFT 0x19 +#define TXA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE__SHIFT 0x1a +#define TXA_CNTL_AUX__AUTO_ALIGN_FORMAT_MASK 0x00000200L +#define TXA_CNTL_AUX__DETERMINISM_RESERVED_DISABLE_MASK 0x00100000L +#define TXA_CNTL_AUX__DETERMINISM_OPCODE_STRICT_DISABLE_MASK 0x00200000L +#define TXA_CNTL_AUX__DETERMINISM_MISC_DISABLE_MASK 0x00400000L +#define TXA_CNTL_AUX__DETERMINISM_WRITEOP_READFMT_DISABLE_MASK 0x02000000L +#define TXA_CNTL_AUX__DETERMINISM_DFMT_NFMT_DISABLE_MASK 0x04000000L +//TXA_CNTL2 +#define TXA_CNTL2__ELEMSIZE_HASH_DIS__SHIFT 0x11 +#define TXA_CNTL2__ELEMSIZE_HASH_DIS_MASK 0x00020000L +//TXA_STATUS +#define TXA_STATUS__TXA0_BUSY__SHIFT 0x10 +#define TXA_STATUS__TXA1_BUSY__SHIFT 0x11 +#define TXA_STATUS__TXA0_BUSY_MASK 0x00010000L +#define TXA_STATUS__TXA1_BUSY_MASK 0x00020000L +//TXA_TDM_ARB_CNTL +#define TXA_TDM_ARB_CNTL__INTERLEAVE_MODE__SHIFT 0x0 +#define TXA_TDM_ARB_CNTL__INTERLEAVE_STEP__SHIFT 0x2 +#define TXA_TDM_ARB_CNTL__PR_EN__SHIFT 0x6 +#define TXA_TDM_ARB_CNTL__BAL_TM_ON_BUS__SHIFT 0x8 +#define TXA_TDM_ARB_CNTL__PR_RATE__SHIFT 0x9 +#define TXA_TDM_ARB_CNTL__PR_CNTX_RESTORE__SHIFT 0xc +#define TXA_TDM_ARB_CNTL__DIS_DIRECT_FETCH__SHIFT 0xd +#define TXA_TDM_ARB_CNTL__REPLAY_SLEEP_CNT__SHIFT 0xe +#define TXA_TDM_ARB_CNTL__INFLIGHT_CNT_MAX__SHIFT 0x15 +#define TXA_TDM_ARB_CNTL__DIS_ASYNC_LOAD_DC__SHIFT 0x1e +#define TXA_TDM_ARB_CNTL__DIS_ASYNC_STORE_DC__SHIFT 0x1f +#define TXA_TDM_ARB_CNTL__INTERLEAVE_MODE_MASK 0x00000003L +#define TXA_TDM_ARB_CNTL__INTERLEAVE_STEP_MASK 0x0000003CL +#define TXA_TDM_ARB_CNTL__PR_EN_MASK 0x000000C0L +#define TXA_TDM_ARB_CNTL__BAL_TM_ON_BUS_MASK 0x00000100L +#define TXA_TDM_ARB_CNTL__PR_RATE_MASK 0x00000E00L +#define TXA_TDM_ARB_CNTL__PR_CNTX_RESTORE_MASK 0x00001000L +#define TXA_TDM_ARB_CNTL__DIS_DIRECT_FETCH_MASK 0x00002000L +#define TXA_TDM_ARB_CNTL__REPLAY_SLEEP_CNT_MASK 0x001FC000L +#define TXA_TDM_ARB_CNTL__INFLIGHT_CNT_MAX_MASK 0x3FE00000L +#define TXA_TDM_ARB_CNTL__DIS_ASYNC_LOAD_DC_MASK 0x40000000L +#define TXA_TDM_ARB_CNTL__DIS_ASYNC_STORE_DC_MASK 0x80000000L +//TCP_CREDIT2 +#define TCP_CREDIT2__LDSO0_ARB0_HANDLER_CREDIT__SHIFT 0x0 +#define TCP_CREDIT2__LDSO1_ARB1_HANDLER_CREDIT__SHIFT 0x4 +#define TCP_CREDIT2__VRX_TXD0_HANDLER_CREDIT__SHIFT 0x8 +#define TCP_CREDIT2__VRX_TXD1_HANDLER_CREDIT__SHIFT 0xc +#define TCP_CREDIT2__LDSO0_ARB0_HANDLER_CREDIT_MASK 0x0000000FL +#define TCP_CREDIT2__LDSO1_ARB1_HANDLER_CREDIT_MASK 0x000000F0L +#define TCP_CREDIT2__VRX_TXD0_HANDLER_CREDIT_MASK 0x00000F00L +#define TCP_CREDIT2__VRX_TXD1_HANDLER_CREDIT_MASK 0x0000F000L +//VC_CONGESTION_CONTROL +#define VC_CONGESTION_CONTROL__LFIFO_LIMIT__SHIFT 0x0 +#define VC_CONGESTION_CONTROL__SET_PENDING_LIMIT__SHIFT 0xa +#define VC_CONGESTION_CONTROL__UTCL0_LFIFO_LIMIT__SHIFT 0xf +#define VC_CONGESTION_CONTROL__LFIFO_LIMIT_MASK 0x000003FFL +#define VC_CONGESTION_CONTROL__SET_PENDING_LIMIT_MASK 0x00007C00L +#define VC_CONGESTION_CONTROL__UTCL0_LFIFO_LIMIT_MASK 0x007F8000L +//TXA_TDM_CNTL +#define TXA_TDM_CNTL__DIS_DONE_INTERLEAVE__SHIFT 0x0 +#define TXA_TDM_CNTL__DIS_CFG_STALL_UPD__SHIFT 0x1 +#define TXA_TDM_CNTL__EN_ADS_SLOT_RELEASE__SHIFT 0x2 +#define TXA_TDM_CNTL__EN_DC_STORE_B128__SHIFT 0x3 +#define TXA_TDM_CNTL__CTRL_SPARE0__SHIFT 0x4 +#define TXA_TDM_CNTL__CTRL_SPARE1__SHIFT 0x5 +#define TXA_TDM_CNTL__CTRL_SPARE2__SHIFT 0x6 +#define TXA_TDM_CNTL__CTRL_SPARE3__SHIFT 0x7 +#define TXA_TDM_CNTL__CTRL_SPARE4__SHIFT 0x8 +#define TXA_TDM_CNTL__DIS_DONE_INTERLEAVE_MASK 0x00000001L +#define TXA_TDM_CNTL__DIS_CFG_STALL_UPD_MASK 0x00000002L +#define TXA_TDM_CNTL__EN_ADS_SLOT_RELEASE_MASK 0x00000004L +#define TXA_TDM_CNTL__EN_DC_STORE_B128_MASK 0x00000008L +#define TXA_TDM_CNTL__CTRL_SPARE0_MASK 0x00000010L +#define TXA_TDM_CNTL__CTRL_SPARE1_MASK 0x00000020L +#define TXA_TDM_CNTL__CTRL_SPARE2_MASK 0x00000040L +#define TXA_TDM_CNTL__CTRL_SPARE3_MASK 0x00000080L +#define TXA_TDM_CNTL__CTRL_SPARE4_MASK 0x00000100L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gfxudec +//VGT_TF_RING_SIZE +#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 +#define VGT_TF_RING_SIZE__SIZE_MASK 0x0001FFFFL +//VGT_HS_OFFCHIP_PARAM +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0xa +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x000003FFL +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x00000C00L +//GE_POS_RING_BASE +#define GE_POS_RING_BASE__BASE__SHIFT 0x0 +#define GE_POS_RING_BASE__BASE_MASK 0xFFFFFFFFL +//GE_POS_RING_SIZE +#define GE_POS_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define GE_POS_RING_SIZE__MEM_SIZE_MASK 0x00003FFFL +//GE_PRIM_RING_BASE +#define GE_PRIM_RING_BASE__BASE__SHIFT 0x0 +#define GE_PRIM_RING_BASE__BASE_MASK 0xFFFFFFFFL +//GE_PRIM_RING_SIZE +#define GE_PRIM_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define GE_PRIM_RING_SIZE__SCOPE__SHIFT 0x10 +#define GE_PRIM_RING_SIZE__PAF_TEMPORAL__SHIFT 0x12 +#define GE_PRIM_RING_SIZE__PAB_TEMPORAL__SHIFT 0x15 +#define GE_PRIM_RING_SIZE__SPEC_DATA_READ__SHIFT 0x18 +#define GE_PRIM_RING_SIZE__FORCE_SE_SCOPE__SHIFT 0x1a +#define GE_PRIM_RING_SIZE__PAB_NOFILL__SHIFT 0x1b +#define GE_PRIM_RING_SIZE__MEM_SIZE_MASK 0x000007FFL +#define GE_PRIM_RING_SIZE__SCOPE_MASK 0x00030000L +#define GE_PRIM_RING_SIZE__PAF_TEMPORAL_MASK 0x001C0000L +#define GE_PRIM_RING_SIZE__PAB_TEMPORAL_MASK 0x00E00000L +#define GE_PRIM_RING_SIZE__SPEC_DATA_READ_MASK 0x03000000L +#define GE_PRIM_RING_SIZE__FORCE_SE_SCOPE_MASK 0x04000000L +#define GE_PRIM_RING_SIZE__PAB_NOFILL_MASK 0x08000000L +//PA_SU_LINE_STIPPLE_VALUE +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0x00FFFFFFL +//PA_SC_LINE_STIPPLE_STATE +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0x0000000FL +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0x0000FF00L +//PA_SC_SCREEN_EXTENT_MIN_0 +#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_0 +#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MIN_1 +#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xFFFF0000L +//PA_SC_SCREEN_EXTENT_MAX_1 +#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0x0000FFFFL +#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xFFFF0000L +//PA_SC_P3D_TRAP_SCREEN_HV_EN +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_P3D_TRAP_SCREEN_H +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x0000FFFFL +//PA_SC_P3D_TRAP_SCREEN_V +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x0000FFFFL +//PA_SC_P3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_P3D_TRAP_SCREEN_COUNT +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_HV_EN +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_HP3D_TRAP_SCREEN_H +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_V +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_HP3D_TRAP_SCREEN_COUNT +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_HV_EN +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x00000001L +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x00000002L +//PA_SC_TRAP_SCREEN_H +#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_V +#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_OCCURRENCE +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0x0000FFFFL +//PA_SC_TRAP_SCREEN_COUNT +#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0x0000FFFFL +//SQ_THREAD_TRACE_USERDATA_0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_1 +#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_2 +#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_3 +#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_4 +#define SQ_THREAD_TRACE_USERDATA_4__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_4__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_5 +#define SQ_THREAD_TRACE_USERDATA_5__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_5__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_6 +#define SQ_THREAD_TRACE_USERDATA_6__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_6__DATA_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_USERDATA_7 +#define SQ_THREAD_TRACE_USERDATA_7__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_7__DATA_MASK 0xFFFFFFFFL +//SQC_CACHES +#define SQC_CACHES__TARGET_INST__SHIFT 0x0 +#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 +#define SQC_CACHES__INVALIDATE__SHIFT 0x2 +#define SQC_CACHES__COMPLETE__SHIFT 0x10 +#define SQC_CACHES__TARGET_INST_MASK 0x00000001L +#define SQC_CACHES__TARGET_DATA_MASK 0x00000002L +#define SQC_CACHES__INVALIDATE_MASK 0x00000004L +#define SQC_CACHES__COMPLETE_MASK 0x00010000L +//TA_CS_BC_BASE_ADDR +#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xFFFFFFFFL +//TA_CS_BC_BASE_ADDR_HI +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL +//DB_OCCLUSION_COUNT0_LOW +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT0_HI +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT1_LOW +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT1_HI +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT2_LOW +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT2_HI +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7FFFFFFFL +//DB_OCCLUSION_COUNT3_LOW +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xFFFFFFFFL +//DB_OCCLUSION_COUNT3_HI +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7FFFFFFFL +//SPI_CONFIG_CNTL +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA__SHIFT 0x1c +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA__SHIFT 0x1d +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL__SHIFT 0x1e +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x001FFFFFL +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0x00E00000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x01000000L +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x02000000L +#define SPI_CONFIG_CNTL__ALLOC_ARB_LRU_ENA_MASK 0x10000000L +#define SPI_CONFIG_CNTL__EXP_ARB_LRU_ENA_MASK 0x20000000L +#define SPI_CONFIG_CNTL__PS_PKR_PRIORITY_CNTL_MASK 0xC0000000L +//SPI_CONFIG_CNTL_1 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x5 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL__SHIFT 0x9 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE__SHIFT 0xe +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE__SHIFT 0xf +#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT__SHIFT 0x10 +#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM__SHIFT 0x15 +#define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP__SHIFT 0x16 +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT__SHIFT 0x17 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x00000010L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000060L +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x00000080L +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MODE_MASK 0x00000100L +#define SPI_CONFIG_CNTL_1__OREO_EXPALLOC_STALL_MASK 0x00000200L +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x00003C00L +#define SPI_CONFIG_CNTL_1__CSC_PWR_SAVE_DISABLE_MASK 0x00004000L +#define SPI_CONFIG_CNTL_1__CSG_PWR_SAVE_DISABLE_MASK 0x00008000L +#define SPI_CONFIG_CNTL_1__MAX_VTX_SYNC_CNT_MASK 0x001F0000L +#define SPI_CONFIG_CNTL_1__EN_USER_ACCUM_MASK 0x00200000L +#define SPI_CONFIG_CNTL_1__SA_SCREEN_MAP_MASK 0x00400000L +#define SPI_CONFIG_CNTL_1__PS_GROUP_TIMEOUT_MASK 0xFF800000L +//SPI_CONFIG_CNTL_2 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 +#define SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE__SHIFT 0x9 +#define SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE__SHIFT 0xa +#define SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE__SHIFT 0xb +#define SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY__SHIFT 0xc +#define SPI_CONFIG_CNTL_2__SPP_TIMEOUT_CTR__SHIFT 0x11 +#define SPI_CONFIG_CNTL_2__PC_CONTEXT_DONE_SYNC_ENABLE__SHIFT 0x15 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0x0000000FL +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0x000000F0L +#define SPI_CONFIG_CNTL_2__PWS_CSG_WAIT_DISABLE_MASK 0x00000100L +#define SPI_CONFIG_CNTL_2__PWS_HS_WAIT_DISABLE_MASK 0x00000200L +#define SPI_CONFIG_CNTL_2__PWS_GS_WAIT_DISABLE_MASK 0x00000400L +#define SPI_CONFIG_CNTL_2__PWS_PS_WAIT_DISABLE_MASK 0x00000800L +#define SPI_CONFIG_CNTL_2__CSC_HALT_ACK_DELAY_MASK 0x0001F000L +#define SPI_CONFIG_CNTL_2__SPP_TIMEOUT_CTR_MASK 0x001E0000L +#define SPI_CONFIG_CNTL_2__PC_CONTEXT_DONE_SYNC_ENABLE_MASK 0x00200000L +//SPI_GS_THROTTLE_CNTL1 +#define SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL__SHIFT 0x0 +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE__SHIFT 0x4 +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE__SHIFT 0x8 +#define SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD__SHIFT 0xc +#define SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD__SHIFT 0x10 +#define SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL__SHIFT 0x14 +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE__SHIFT 0x18 +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE__SHIFT 0x1c +#define SPI_GS_THROTTLE_CNTL1__PH_POLL_INTERVAL_MASK 0x0000000FL +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_BASE_MASK 0x000000F0L +#define SPI_GS_THROTTLE_CNTL1__PH_THROTTLE_STEP_SIZE_MASK 0x00000F00L +#define SPI_GS_THROTTLE_CNTL1__SPI_VGPR_THRESHOLD_MASK 0x0000F000L +#define SPI_GS_THROTTLE_CNTL1__SPI_LDS_THRESHOLD_MASK 0x000F0000L +#define SPI_GS_THROTTLE_CNTL1__SPI_POLL_INTERVAL_MASK 0x00F00000L +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_BASE_MASK 0x0F000000L +#define SPI_GS_THROTTLE_CNTL1__SPI_THROTTLE_STEP_SIZE_MASK 0xF0000000L +//SPI_GS_THROTTLE_CNTL2 +#define SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE__SHIFT 0x0 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD__SHIFT 0x2 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR__SHIFT 0x6 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1__SHIFT 0x8 +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2__SHIFT 0xb +#define SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD__SHIFT 0xe +#define SPI_GS_THROTTLE_CNTL2__PH_MODE__SHIFT 0x10 +#define SPI_GS_THROTTLE_CNTL2__RESERVED__SHIFT 0x11 +#define SPI_GS_THROTTLE_CNTL2__SPI_THROTTLE_MODE_MASK 0x00000003L +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_MASK 0x0000003CL +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_THRESHOLD_FACTOR_MASK 0x000000C0L +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY1_MASK 0x00000700L +#define SPI_GS_THROTTLE_CNTL2__GRP_LIFETIME_PENALTY2_MASK 0x00003800L +#define SPI_GS_THROTTLE_CNTL2__PS_STALL_THRESHOLD_MASK 0x0000C000L +#define SPI_GS_THROTTLE_CNTL2__PH_MODE_MASK 0x00010000L +#define SPI_GS_THROTTLE_CNTL2__RESERVED_MASK 0xFFFE0000L +//SPI_ATTRIBUTE_RING_BASE +#define SPI_ATTRIBUTE_RING_BASE__BASE__SHIFT 0x0 +#define SPI_ATTRIBUTE_RING_BASE__BASE_MASK 0xFFFFFFFFL +//SPI_ATTRIBUTE_RING_SIZE +#define SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE__SHIFT 0x10 +#define SPI_ATTRIBUTE_RING_SIZE__L1_POLICY__SHIFT 0x11 +#define SPI_ATTRIBUTE_RING_SIZE__L2_POLICY__SHIFT 0x13 +#define SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC__SHIFT 0x15 +#define SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE__SHIFT 0x16 +#define SPI_ATTRIBUTE_RING_SIZE__MEM_SIZE_MASK 0x000000FFL +#define SPI_ATTRIBUTE_RING_SIZE__BIG_PAGE_MASK 0x00010000L +#define SPI_ATTRIBUTE_RING_SIZE__L1_POLICY_MASK 0x00060000L +#define SPI_ATTRIBUTE_RING_SIZE__L2_POLICY_MASK 0x00180000L +#define SPI_ATTRIBUTE_RING_SIZE__LLC_NOALLOC_MASK 0x00200000L +#define SPI_ATTRIBUTE_RING_SIZE__GL1_PERF_COUNTER_DISABLE_MASK 0x00400000L +//SPI_SQG_EVENT_CTL +#define SPI_SQG_EVENT_CTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x0 +#define SPI_SQG_EVENT_CTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x1 +#define SPI_SQG_EVENT_CTL__ENABLE_SQG_TOP_EVENTS_MASK 0x00000001L +#define SPI_SQG_EVENT_CTL__ENABLE_SQG_BOP_EVENTS_MASK 0x00000002L +//SPI_COMPUTE_WGS_CONTROL +#define SPI_COMPUTE_WGS_CONTROL__WGS_ENABLE__SHIFT 0x0 +#define SPI_COMPUTE_WGS_CONTROL__WGS_ENABLE_MASK 0x00000001L +//SPI_GRP_LAUNCH_GUARANTEE_ENABLE +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__ENABLE__SHIFT 0x0 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__HS_ASSIST_EN__SHIFT 0x1 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__GS_ASSIST_EN__SHIFT 0x2 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__MRT_ASSIST_EN__SHIFT 0x3 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CS_GLG_DISABLE__SHIFT 0x4 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__GFX_NUM_LOCK_WGP__SHIFT 0x5 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CS_NUM_LOCK_WGP__SHIFT 0x8 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__LOCK_PERIOD__SHIFT 0xb +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__LOCK_MAINT_COUNT__SHIFT 0xf +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CLUSTER_LOCK_DISABLE__SHIFT 0x12 +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__ENABLE_MASK 0x00000001L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__HS_ASSIST_EN_MASK 0x00000002L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__GS_ASSIST_EN_MASK 0x00000004L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__MRT_ASSIST_EN_MASK 0x00000008L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CS_GLG_DISABLE_MASK 0x00000010L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__GFX_NUM_LOCK_WGP_MASK 0x000000E0L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CS_NUM_LOCK_WGP_MASK 0x00000700L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__LOCK_PERIOD_MASK 0x00007800L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__LOCK_MAINT_COUNT_MASK 0x00038000L +#define SPI_GRP_LAUNCH_GUARANTEE_ENABLE__CLUSTER_LOCK_DISABLE_MASK 0x00040000L +//SPI_GRP_LAUNCH_GUARANTEE_CTRL +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__NUM_MRT_THRESHOLD__SHIFT 0x0 +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__GFX_PENDING_THRESHOLD__SHIFT 0x3 +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__PRIORITY_LOST_THRESHOLD__SHIFT 0x6 +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__ALLOC_SUCCESS_THRESHOLD__SHIFT 0xa +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__GFX_WAVE_THRESHOLD_HIGH__SHIFT 0xe +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__CS_WAVE_THRESHOLD_HIGH__SHIFT 0x13 +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__CU_MASK_ROTATE_PERIODS__SHIFT 0x18 +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__EQUAL_PRIORITY_LOST_THRESHOLD__SHIFT 0x1a +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__NUM_MRT_THRESHOLD_MASK 0x00000007L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__GFX_PENDING_THRESHOLD_MASK 0x00000038L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__PRIORITY_LOST_THRESHOLD_MASK 0x000003C0L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__ALLOC_SUCCESS_THRESHOLD_MASK 0x00003C00L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__GFX_WAVE_THRESHOLD_HIGH_MASK 0x0007C000L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__CS_WAVE_THRESHOLD_HIGH_MASK 0x00F80000L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__CU_MASK_ROTATE_PERIODS_MASK 0x03000000L +#define SPI_GRP_LAUNCH_GUARANTEE_CTRL__EQUAL_PRIORITY_LOST_THRESHOLD_MASK 0x3C000000L +//SPI_GOG_ALLOCATION_CTRL +#define SPI_GOG_ALLOCATION_CTRL__GOG_ALLOCATION_TIME_OUT__SHIFT 0x0 +#define SPI_GOG_ALLOCATION_CTRL__GOG_RETRY_DELAY__SHIFT 0x6 +#define SPI_GOG_ALLOCATION_CTRL__GOG_ALLOCATION_TIME_OUT_MASK 0x0000003FL +#define SPI_GOG_ALLOCATION_CTRL__GOG_RETRY_DELAY_MASK 0x00000FC0L +//SPI_TCP_CNTL +#define SPI_TCP_CNTL__DEFAULT_LDS_PARTITIONS__SHIFT 0x0 +#define SPI_TCP_CNTL__MIN_LDS_PARTITIONS__SHIFT 0x4 +#define SPI_TCP_CNTL__MAX_LDS_PARTITIONS__SHIFT 0xc +#define SPI_TCP_CNTL__IDLE_ALLOC_OPT_DIS__SHIFT 0x10 +#define SPI_TCP_CNTL__PARTIAL_DRAIN_DIS__SHIFT 0x11 +#define SPI_TCP_CNTL__LDS_PINGPONG_DIS__SHIFT 0x12 +#define SPI_TCP_CNTL__DEFAULT_LDS_PARTITIONS_MASK 0x00000007L +#define SPI_TCP_CNTL__MIN_LDS_PARTITIONS_MASK 0x00000070L +#define SPI_TCP_CNTL__MAX_LDS_PARTITIONS_MASK 0x00007000L +#define SPI_TCP_CNTL__IDLE_ALLOC_OPT_DIS_MASK 0x00010000L +#define SPI_TCP_CNTL__PARTIAL_DRAIN_DIS_MASK 0x00020000L +#define SPI_TCP_CNTL__LDS_PINGPONG_DIS_MASK 0x00040000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_comp_wgsdec +//WGS_COMPUTE_DISPATCH_INITIATOR +#define WGS_COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 +#define WGS_COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 +#define WGS_COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 +#define WGS_COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa +#define WGS_COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb +#define WGS_COMPUTE_DISPATCH_INITIATOR__PING_PONG_EN__SHIFT 0xc +#define WGS_COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE__SHIFT 0xd +#define WGS_COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe +#define WGS_COMPUTE_DISPATCH_INITIATOR__CS_W32_EN__SHIFT 0xf +#define WGS_COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN__SHIFT 0x10 +#define WGS_COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN__SHIFT 0x11 +#define WGS_COMPUTE_DISPATCH_INITIATOR__INTERLEAVE_2D_EN__SHIFT 0x12 +#define WGS_COMPUTE_DISPATCH_INITIATOR__WGS_DISPATCH__SHIFT 0x13 +#define WGS_COMPUTE_DISPATCH_INITIATOR__TTRACE_QUEUE_ID__SHIFT 0x1d +#define WGS_COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x00000001L +#define WGS_COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x00000002L +#define WGS_COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x00000004L +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x00000008L +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x00000010L +#define WGS_COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x00000020L +#define WGS_COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x00000040L +#define WGS_COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x00000400L +#define WGS_COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x00000800L +#define WGS_COMPUTE_DISPATCH_INITIATOR__PING_PONG_EN_MASK 0x00001000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__TUNNEL_ENABLE_MASK 0x00002000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x00004000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__CS_W32_EN_MASK 0x00008000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__AMP_SHADER_EN_MASK 0x00010000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__DISABLE_DISP_PREMPT_EN_MASK 0x00020000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__INTERLEAVE_2D_EN_MASK 0x00040000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__WGS_DISPATCH_MASK 0x00080000L +#define WGS_COMPUTE_DISPATCH_INITIATOR__TTRACE_QUEUE_ID_MASK 0xE0000000L +//WGS_COMPUTE_DIM_X +#define WGS_COMPUTE_DIM_X__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_DIM_X__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_DIM_Y +#define WGS_COMPUTE_DIM_Y__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_DIM_Z +#define WGS_COMPUTE_DIM_Z__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_START_X +#define WGS_COMPUTE_START_X__START__SHIFT 0x0 +#define WGS_COMPUTE_START_X__START_MASK 0xFFFFFFFFL +//WGS_COMPUTE_START_Y +#define WGS_COMPUTE_START_Y__START__SHIFT 0x0 +#define WGS_COMPUTE_START_Y__START_MASK 0xFFFFFFFFL +//WGS_COMPUTE_START_Z +#define WGS_COMPUTE_START_Z__START__SHIFT 0x0 +#define WGS_COMPUTE_START_Z__START_MASK 0xFFFFFFFFL +//WGS_COMPUTE_NUM_THREAD_X +#define WGS_COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 +#define WGS_COMPUTE_NUM_THREAD_X__INTERLEAVE_BITS_X__SHIFT 0xd +#define WGS_COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define WGS_COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0x00001FFFL +#define WGS_COMPUTE_NUM_THREAD_X__INTERLEAVE_BITS_X_MASK 0x0000E000L +#define WGS_COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//WGS_COMPUTE_NUM_THREAD_Y +#define WGS_COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 +#define WGS_COMPUTE_NUM_THREAD_Y__INTERLEAVE_BITS_Y__SHIFT 0xd +#define WGS_COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define WGS_COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0x00001FFFL +#define WGS_COMPUTE_NUM_THREAD_Y__INTERLEAVE_BITS_Y_MASK 0x0000E000L +#define WGS_COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//WGS_COMPUTE_NUM_THREAD_Z +#define WGS_COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 +#define WGS_COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define WGS_COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0x0000FFFFL +#define WGS_COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xFFFF0000L +//WGS_COMPUTE_PIPELINESTAT_ENABLE +#define WGS_COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 +#define WGS_COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x00000001L +//WGS_COMPUTE_PERFCOUNT_ENABLE +#define WGS_COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 +#define WGS_COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x00000001L +//WGS_COMPUTE_PGM_LO +#define WGS_COMPUTE_PGM_LO__DATA__SHIFT 0x0 +#define WGS_COMPUTE_PGM_LO__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_PGM_HI +#define WGS_COMPUTE_PGM_HI__DATA__SHIFT 0x0 +#define WGS_COMPUTE_PGM_HI__DATA_MASK 0x000000FFL +//WGS_COMPUTE_DISPATCH_PKT_ADDR_LO +#define WGS_COMPUTE_DISPATCH_PKT_ADDR_LO__DATA__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_PKT_ADDR_LO__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_DISPATCH_PKT_ADDR_HI +#define WGS_COMPUTE_DISPATCH_PKT_ADDR_HI__DATA__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_PKT_ADDR_HI__DATA_MASK 0x000000FFL +//WGS_COMPUTE_DISPATCH_SCRATCH_BASE_LO +#define WGS_COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_DISPATCH_SCRATCH_BASE_HI +#define WGS_COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_SCRATCH_BASE_HI__DATA_MASK 0x000000FFL +//WGS_COMPUTE_PGM_RSRC1 +#define WGS_COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 +#define WGS_COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 +#define WGS_COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa +#define WGS_COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc +#define WGS_COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 +#define WGS_COMPUTE_PGM_RSRC1__WG_RR_EN__SHIFT 0x15 +#define WGS_COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 +#define WGS_COMPUTE_PGM_RSRC1__DISABLE_PERF__SHIFT 0x17 +#define WGS_COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 +#define WGS_COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 +#define WGS_COMPUTE_PGM_RSRC1__FP16_OVFL__SHIFT 0x1a +#define WGS_COMPUTE_PGM_RSRC1__WGP_MODE__SHIFT 0x1d +#define WGS_COMPUTE_PGM_RSRC1__FWD_PROGRESS__SHIFT 0x1f +#define WGS_COMPUTE_PGM_RSRC1__VGPRS_MASK 0x0000003FL +#define WGS_COMPUTE_PGM_RSRC1__SGPRS_MASK 0x000003C0L +#define WGS_COMPUTE_PGM_RSRC1__PRIORITY_MASK 0x00000C00L +#define WGS_COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0x000FF000L +#define WGS_COMPUTE_PGM_RSRC1__PRIV_MASK 0x00100000L +#define WGS_COMPUTE_PGM_RSRC1__WG_RR_EN_MASK 0x00200000L +#define WGS_COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x00400000L +#define WGS_COMPUTE_PGM_RSRC1__DISABLE_PERF_MASK 0x00800000L +#define WGS_COMPUTE_PGM_RSRC1__BULKY_MASK 0x01000000L +#define WGS_COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x02000000L +#define WGS_COMPUTE_PGM_RSRC1__FP16_OVFL_MASK 0x04000000L +#define WGS_COMPUTE_PGM_RSRC1__WGP_MODE_MASK 0x20000000L +#define WGS_COMPUTE_PGM_RSRC1__FWD_PROGRESS_MASK 0x80000000L +//WGS_COMPUTE_PGM_RSRC2 +#define WGS_COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 +#define WGS_COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 +#define WGS_COMPUTE_PGM_RSRC2__DYNAMIC_VGPR__SHIFT 0x6 +#define WGS_COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 +#define WGS_COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 +#define WGS_COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 +#define WGS_COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa +#define WGS_COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb +#define WGS_COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd +#define WGS_COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf +#define WGS_COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 +#define WGS_COMPUTE_PGM_RSRC2__WGP_TAKEOVER__SHIFT 0x1f +#define WGS_COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x00000001L +#define WGS_COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x0000003EL +#define WGS_COMPUTE_PGM_RSRC2__DYNAMIC_VGPR_MASK 0x00000040L +#define WGS_COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x00000080L +#define WGS_COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x00000100L +#define WGS_COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x00000200L +#define WGS_COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x00000400L +#define WGS_COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x00001800L +#define WGS_COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x00006000L +#define WGS_COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0x00FF8000L +#define WGS_COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7F000000L +#define WGS_COMPUTE_PGM_RSRC2__WGP_TAKEOVER_MASK 0x80000000L +//WGS_COMPUTE_VMID +#define WGS_COMPUTE_VMID__DATA__SHIFT 0x0 +#define WGS_COMPUTE_VMID__DATA_MASK 0x0000000FL +//WGS_COMPUTE_RESOURCE_LIMITS +#define WGS_COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 +#define WGS_COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc +#define WGS_COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 +#define WGS_COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 +#define WGS_COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 +#define WGS_COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 +#define WGS_COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x000003FFL +#define WGS_COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0x0000F000L +#define WGS_COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x003F0000L +#define WGS_COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x00400000L +#define WGS_COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x00800000L +#define WGS_COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x07000000L +//WGS_COMPUTE_DESTINATION_EN_SE0 +#define WGS_COMPUTE_DESTINATION_EN_SE0__CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_DESTINATION_EN_SE0__CU_EN_MASK 0xFFFFFFFFL +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE0__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE0__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_DESTINATION_EN_SE1 +#define WGS_COMPUTE_DESTINATION_EN_SE1__CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_DESTINATION_EN_SE1__CU_EN_MASK 0xFFFFFFFFL +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE1 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE1__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE1__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_TMPRING_SIZE +#define WGS_COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define WGS_COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define WGS_COMPUTE_TMPRING_SIZE__WAVES_MASK 0x00000FFFL +#define WGS_COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x3FFFF000L +//WGS_COMPUTE_DESTINATION_EN_SE2 +#define WGS_COMPUTE_DESTINATION_EN_SE2__CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_DESTINATION_EN_SE2__CU_EN_MASK 0xFFFFFFFFL +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE2 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE2__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE2__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_DESTINATION_EN_SE3 +#define WGS_COMPUTE_DESTINATION_EN_SE3__CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_DESTINATION_EN_SE3__CU_EN_MASK 0xFFFFFFFFL +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE3 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE3__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE3__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_RESTART_X +#define WGS_COMPUTE_RESTART_X__RESTART__SHIFT 0x0 +#define WGS_COMPUTE_RESTART_X__RESTART_MASK 0xFFFFFFFFL +//WGS_COMPUTE_RESTART_Y +#define WGS_COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 +#define WGS_COMPUTE_RESTART_Y__RESTART_MASK 0xFFFFFFFFL +//WGS_COMPUTE_RESTART_Z +#define WGS_COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 +#define WGS_COMPUTE_RESTART_Z__RESTART_MASK 0xFFFFFFFFL +//WGS_COMPUTE_THREAD_TRACE_ENABLE +#define WGS_COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 +#define WGS_COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x00000001L +//WGS_COMPUTE_MISC_RESERVED +#define WGS_COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 +#define WGS_COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 +#define WGS_COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 +#define WGS_COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x0000000FL +#define WGS_COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x00000010L +#define WGS_COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x0001FFE0L +//WGS_COMPUTE_DISPATCH_ID +#define WGS_COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xFFFFFFFFL +//WGS_COMPUTE_THREADGROUP_ID +#define WGS_COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 +#define WGS_COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xFFFFFFFFL +//WGS_COMPUTE_REQ_CTRL +#define WGS_COMPUTE_REQ_CTRL__SOFT_GROUPING_EN__SHIFT 0x0 +#define WGS_COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU__SHIFT 0x1 +#define WGS_COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT__SHIFT 0x5 +#define WGS_COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS__SHIFT 0x9 +#define WGS_COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD__SHIFT 0xa +#define WGS_COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT__SHIFT 0xf +#define WGS_COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN__SHIFT 0x10 +#define WGS_COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD__SHIFT 0x11 +#define WGS_COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT__SHIFT 0x14 +#define WGS_COMPUTE_REQ_CTRL__SOFT_GROUPING_EN_MASK 0x00000001L +#define WGS_COMPUTE_REQ_CTRL__NUMBER_OF_REQUESTS_PER_CU_MASK 0x0000001EL +#define WGS_COMPUTE_REQ_CTRL__SOFT_GROUPING_ALLOCATION_TIMEOUT_MASK 0x000001E0L +#define WGS_COMPUTE_REQ_CTRL__HARD_LOCK_HYSTERESIS_MASK 0x00000200L +#define WGS_COMPUTE_REQ_CTRL__HARD_LOCK_LOW_THRESHOLD_MASK 0x00007C00L +#define WGS_COMPUTE_REQ_CTRL__PRODUCER_REQUEST_LOCKOUT_MASK 0x00008000L +#define WGS_COMPUTE_REQ_CTRL__GLOBAL_SCANNING_EN_MASK 0x00010000L +#define WGS_COMPUTE_REQ_CTRL__ALLOCATION_RATE_THROTTLING_THRESHOLD_MASK 0x000E0000L +#define WGS_COMPUTE_REQ_CTRL__DEDICATED_PREALLOCATION_BUFFER_LIMIT_MASK 0x07F00000L +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE8 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE8__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE8__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE8__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE8__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_USER_ACCUM_0 +#define WGS_COMPUTE_USER_ACCUM_0__CONTRIBUTION__SHIFT 0x0 +#define WGS_COMPUTE_USER_ACCUM_0__CONTRIBUTION_MASK 0x0000007FL +//WGS_COMPUTE_USER_ACCUM_1 +#define WGS_COMPUTE_USER_ACCUM_1__CONTRIBUTION__SHIFT 0x0 +#define WGS_COMPUTE_USER_ACCUM_1__CONTRIBUTION_MASK 0x0000007FL +//WGS_COMPUTE_USER_ACCUM_2 +#define WGS_COMPUTE_USER_ACCUM_2__CONTRIBUTION__SHIFT 0x0 +#define WGS_COMPUTE_USER_ACCUM_2__CONTRIBUTION_MASK 0x0000007FL +//WGS_COMPUTE_USER_ACCUM_3 +#define WGS_COMPUTE_USER_ACCUM_3__CONTRIBUTION__SHIFT 0x0 +#define WGS_COMPUTE_USER_ACCUM_3__CONTRIBUTION_MASK 0x0000007FL +//WGS_COMPUTE_PGM_RSRC3 +#define WGS_COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT__SHIFT 0x0 +#define WGS_COMPUTE_PGM_RSRC3__INST_PREF_SIZE__SHIFT 0x4 +#define WGS_COMPUTE_PGM_RSRC3__GLG_EN__SHIFT 0xd +#define WGS_COMPUTE_PGM_RSRC3__IMAGE_OP__SHIFT 0x1f +#define WGS_COMPUTE_PGM_RSRC3__SHARED_VGPR_CNT_MASK 0x0000000FL +#define WGS_COMPUTE_PGM_RSRC3__INST_PREF_SIZE_MASK 0x00000FF0L +#define WGS_COMPUTE_PGM_RSRC3__GLG_EN_MASK 0x00002000L +#define WGS_COMPUTE_PGM_RSRC3__IMAGE_OP_MASK 0x80000000L +//WGS_COMPUTE_DDID_INDEX +#define WGS_COMPUTE_DDID_INDEX__INDEX__SHIFT 0x0 +#define WGS_COMPUTE_DDID_INDEX__INDEX_MASK 0x000007FFL +//WGS_COMPUTE_SHADER_CHKSUM +#define WGS_COMPUTE_SHADER_CHKSUM__CHECKSUM__SHIFT 0x0 +#define WGS_COMPUTE_SHADER_CHKSUM__CHECKSUM_MASK 0xFFFFFFFFL +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE4 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE4__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE4__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE5 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE5__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE5__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE6 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE6__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE6__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_STATIC_THREAD_MGMT_SE7 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN__SHIFT 0x0 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN__SHIFT 0x10 +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE7__SA0_CU_EN_MASK 0x0000FFFFL +#define WGS_COMPUTE_STATIC_THREAD_MGMT_SE7__SA1_CU_EN_MASK 0xFFFF0000L +//WGS_COMPUTE_DISPATCH_INTERLEAVE +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_1D__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_X_SIZE__SHIFT 0x10 +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_Y_SIZE__SHIFT 0x18 +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_1D_MASK 0x000003FFL +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_X_SIZE_MASK 0x000F0000L +#define WGS_COMPUTE_DISPATCH_INTERLEAVE__INTERLEAVE_2D_Y_SIZE_MASK 0x0F000000L +//WGS_COMPUTE_RELAUNCH +#define WGS_COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 +#define WGS_COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e +#define WGS_COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f +#define WGS_COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3FFFFFFFL +#define WGS_COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000L +#define WGS_COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000L +//WGS_COMPUTE_WAVE_RESTORE_ADDR_LO +#define WGS_COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 +#define WGS_COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xFFFFFFFFL +//WGS_COMPUTE_WAVE_RESTORE_ADDR_HI +#define WGS_COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 +#define WGS_COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0x0000FFFFL +//WGS_COMPUTE_RELAUNCH2 +#define WGS_COMPUTE_RELAUNCH2__PAYLOAD__SHIFT 0x0 +#define WGS_COMPUTE_RELAUNCH2__IS_EVENT__SHIFT 0x1e +#define WGS_COMPUTE_RELAUNCH2__IS_STATE__SHIFT 0x1f +#define WGS_COMPUTE_RELAUNCH2__PAYLOAD_MASK 0x3FFFFFFFL +#define WGS_COMPUTE_RELAUNCH2__IS_EVENT_MASK 0x40000000L +#define WGS_COMPUTE_RELAUNCH2__IS_STATE_MASK 0x80000000L +//WGS_COMPUTE_PRESCALED_DIM_X +#define WGS_COMPUTE_PRESCALED_DIM_X__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_PRESCALED_DIM_X__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_PRESCALED_DIM_Y +#define WGS_COMPUTE_PRESCALED_DIM_Y__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_PRESCALED_DIM_Y__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_PRESCALED_DIM_Z +#define WGS_COMPUTE_PRESCALED_DIM_Z__SIZE__SHIFT 0x0 +#define WGS_COMPUTE_PRESCALED_DIM_Z__SIZE_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_0 +#define WGS_COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_0__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_1 +#define WGS_COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_1__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_2 +#define WGS_COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_2__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_3 +#define WGS_COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_3__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_4 +#define WGS_COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_4__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_5 +#define WGS_COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_5__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_6 +#define WGS_COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_6__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_7 +#define WGS_COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_7__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_8 +#define WGS_COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_8__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_9 +#define WGS_COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_9__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_10 +#define WGS_COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_10__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_11 +#define WGS_COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_11__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_12 +#define WGS_COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_12__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_13 +#define WGS_COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_13__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_14 +#define WGS_COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_14__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_USER_DATA_15 +#define WGS_COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 +#define WGS_COMPUTE_USER_DATA_15__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_DISPATCH_TUNNEL +#define WGS_COMPUTE_DISPATCH_TUNNEL__OFF_DELAY__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_TUNNEL__OFF_DELAY_MASK 0x00001FFFL +//WGS_COMPUTE_DISPATCH_END +#define WGS_COMPUTE_DISPATCH_END__DATA__SHIFT 0x0 +#define WGS_COMPUTE_DISPATCH_END__DATA_MASK 0xFFFFFFFFL +//WGS_COMPUTE_NOWHERE +#define WGS_COMPUTE_NOWHERE__DATA__SHIFT 0x0 +#define WGS_COMPUTE_NOWHERE__DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_wgsdec +//WGS_MGCG_SYNC_CNTL +#define WGS_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 +#define WGS_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 +#define WGS_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0x000000FFL +#define WGS_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0x0000FF00L +//WGS_INT_INFO +#define WGS_INT_INFO__RING_ID__SHIFT 0x0 +#define WGS_INT_INFO__VMID__SHIFT 0x8 +#define WGS_INT_INFO__RING_ID_MASK 0x000000FFL +#define WGS_INT_INFO__VMID_MASK 0x00000F00L +//WGS_INT_CNTXID_LO +#define WGS_INT_CNTXID_LO__DATA__SHIFT 0x0 +#define WGS_INT_CNTXID_LO__DATA_MASK 0xFFFFFFFFL +//WGS_INT_CNTXID_HI +#define WGS_INT_CNTXID_HI__DATA__SHIFT 0x0 +#define WGS_INT_CNTXID_HI__DATA_MASK 0x000000FFL +//WGS_ERROR +#define WGS_ERROR__RESERVED__SHIFT 0x0 +#define WGS_ERROR__RESERVED_MASK 0xFFFFFFFFL +//WGS_ENDIAN_SWAP +#define WGS_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0 +#define WGS_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x00000003L +//WGS_GEN_BASE_LO +#define WGS_GEN_BASE_LO__BASE_LO__SHIFT 0xc +#define WGS_GEN_BASE_LO__BASE_LO_MASK 0xFFFFF000L +//WGS_GEN_BASE_HI +#define WGS_GEN_BASE_HI__BASE_HI__SHIFT 0x0 +#define WGS_GEN_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//CGTT_WGS_CLK_CTRL +#define CGTT_WGS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_WGS_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_WGS_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_WGS_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_WGS_CLK_CTRL__RESERVED_SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L +#define CGTT_WGS_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000L +//WGS_ME1_UCODE_ADDR +#define WGS_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define WGS_ME1_UCODE_ADDR__PIPE_SEL__SHIFT 0x1e +#define WGS_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x007FFFFFL +#define WGS_ME1_UCODE_ADDR__PIPE_SEL_MASK 0xC0000000L +//WGS_ME1_UCODE_DATA +#define WGS_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define WGS_ME1_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL +//WGS_ME1_UCODE_CHKSUM +#define WGS_ME1_UCODE_CHKSUM__UCODE_CHKSUM__SHIFT 0x0 +#define WGS_ME1_UCODE_CHKSUM__UCODE_CHKSUM_MASK 0xFFFFFFFFL +//WGS_SUSPEND_CTX_SAVE_BASE_ADDR_LO +#define WGS_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define WGS_SUSPEND_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xFFFFF000L +//WGS_SUSPEND_CTX_SAVE_BASE_ADDR_HI +#define WGS_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define WGS_SUSPEND_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0x0000FFFFL +//WGS_SUSPEND_CTX_SAVE_CONTROL +#define WGS_SUSPEND_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define WGS_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE__SHIFT 0x17 +#define WGS_SUSPEND_CTX_SAVE_CONTROL__POLICY_MASK 0x00000018L +#define WGS_SUSPEND_CTX_SAVE_CONTROL__EXE_DISABLE_MASK 0x00800000L +//WGS_SUSPEND_CNTL_STACK_OFFSET +#define WGS_SUSPEND_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define WGS_SUSPEND_CNTL_STACK_OFFSET__OFFSET_MASK 0x0000FFFCL +//WGS_SUSPEND_CNTL_STACK_SIZE +#define WGS_SUSPEND_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define WGS_SUSPEND_CNTL_STACK_SIZE__SIZE_MASK 0x0000F000L +//WGS_SUSPEND_WG_STATE_OFFSET +#define WGS_SUSPEND_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define WGS_SUSPEND_WG_STATE_OFFSET__OFFSET_MASK 0x03FFFFFCL +//WGS_SUSPEND_CTX_SAVE_SIZE +#define WGS_SUSPEND_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define WGS_SUSPEND_CTX_SAVE_SIZE__SIZE_MASK 0x03FFF000L +//WGS_OS_PIPES +#define WGS_OS_PIPES__OS_PIPES__SHIFT 0x0 +#define WGS_OS_PIPES__OS_PIPES_MASK 0x000000FFL +//WGS_SUSPEND_RESUME_REQ +#define WGS_SUSPEND_RESUME_REQ__SUSPEND_REQ__SHIFT 0x0 +#define WGS_SUSPEND_RESUME_REQ__RESUME_REQ__SHIFT 0x1 +#define WGS_SUSPEND_RESUME_REQ__SUSPEND_REQ_MASK 0x00000001L +#define WGS_SUSPEND_RESUME_REQ__RESUME_REQ_MASK 0x00000002L +//WGS_IQ_WAIT_TIME3 +#define WGS_IQ_WAIT_TIME3__SUSPEND_QUE__SHIFT 0x0 +#define WGS_IQ_WAIT_TIME3__SUSPEND_QUE_MASK 0x000000FFL +//WGS_DDID_BASE_ADDR_LO +#define WGS_DDID_BASE_ADDR_LO__BASE_ADDR_LO__SHIFT 0x6 +#define WGS_DDID_BASE_ADDR_LO__BASE_ADDR_LO_MASK 0xFFFFFFC0L +//WGS_DDID_BASE_ADDR_HI +#define WGS_DDID_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define WGS_DDID_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0x0000FFFFL +//WGS_DDID_CNTL +#define WGS_DDID_CNTL__THRESHOLD__SHIFT 0x0 +#define WGS_DDID_CNTL__SIZE__SHIFT 0x10 +#define WGS_DDID_CNTL__NO_RING_MEMORY__SHIFT 0x13 +#define WGS_DDID_CNTL__POLICY__SHIFT 0x1c +#define WGS_DDID_CNTL__MODE__SHIFT 0x1e +#define WGS_DDID_CNTL__ENABLE__SHIFT 0x1f +#define WGS_DDID_CNTL__THRESHOLD_MASK 0x000000FFL +#define WGS_DDID_CNTL__SIZE_MASK 0x00010000L +#define WGS_DDID_CNTL__NO_RING_MEMORY_MASK 0x00080000L +#define WGS_DDID_CNTL__POLICY_MASK 0x30000000L +#define WGS_DDID_CNTL__MODE_MASK 0x40000000L +#define WGS_DDID_CNTL__ENABLE_MASK 0x80000000L +//WGS_RS64_PRGRM_CNTR_START +#define WGS_RS64_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define WGS_RS64_PRGRM_CNTR_START__IP_START_MASK 0xFFFFFFFFL +//WGS_MTVEC_LO +#define WGS_MTVEC_LO__ADDR_LO__SHIFT 0x0 +#define WGS_MTVEC_LO__ADDR_LO_MASK 0xFFFFFFFFL +//WGS_MTVEC_HI +#define WGS_MTVEC_HI__ADDR_LO__SHIFT 0x0 +#define WGS_MTVEC_HI__ADDR_LO_MASK 0xFFFFFFFFL +//WGS_RS64_CNTL +#define WGS_RS64_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define WGS_RS64_CNTL__RSRV8__SHIFT 0x10 +#define WGS_RS64_CNTL__RSRV7__SHIFT 0x11 +#define WGS_RS64_CNTL__RSRV6__SHIFT 0x12 +#define WGS_RS64_CNTL__RSRV5__SHIFT 0x13 +#define WGS_RS64_CNTL__RSRV4__SHIFT 0x1a +#define WGS_RS64_CNTL__RSRV3__SHIFT 0x1b +#define WGS_RS64_CNTL__RSRV2__SHIFT 0x1c +#define WGS_RS64_CNTL__RSRV1__SHIFT 0x1d +#define WGS_RS64_CNTL__MEC_HALT__SHIFT 0x1e +#define WGS_RS64_CNTL__MEC_STEP__SHIFT 0x1f +#define WGS_RS64_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L +#define WGS_RS64_CNTL__RSRV8_MASK 0x00010000L +#define WGS_RS64_CNTL__RSRV7_MASK 0x00020000L +#define WGS_RS64_CNTL__RSRV6_MASK 0x00040000L +#define WGS_RS64_CNTL__RSRV5_MASK 0x00080000L +#define WGS_RS64_CNTL__RSRV4_MASK 0x04000000L +#define WGS_RS64_CNTL__RSRV3_MASK 0x08000000L +#define WGS_RS64_CNTL__RSRV2_MASK 0x10000000L +#define WGS_RS64_CNTL__RSRV1_MASK 0x20000000L +#define WGS_RS64_CNTL__MEC_HALT_MASK 0x40000000L +#define WGS_RS64_CNTL__MEC_STEP_MASK 0x80000000L +//WGS_MIE_LO +#define WGS_MIE_LO__MEC_INT__SHIFT 0x0 +#define WGS_MIE_LO__MEC_INT_MASK 0xFFFFFFFFL +//WGS_MIE_HI +#define WGS_MIE_HI__MEC_INT__SHIFT 0x0 +#define WGS_MIE_HI__MEC_INT_MASK 0xFFFFFFFFL +//WGS_RS64_INTERRUPT +#define WGS_RS64_INTERRUPT__MEC_INT__SHIFT 0x0 +#define WGS_RS64_INTERRUPT__MEC_INT_MASK 0xFFFFFFFFL +//WGS_RS64_INSTR_PNTR +#define WGS_RS64_INSTR_PNTR__INSTR_PNTR__SHIFT 0x0 +#define WGS_RS64_INSTR_PNTR__INSTR_PNTR_MASK 0x000FFFFFL +//WGS_MIP_LO +#define WGS_MIP_LO__MIP_LO__SHIFT 0x0 +#define WGS_MIP_LO__MIP_LO_MASK 0xFFFFFFFFL +//WGS_MIP_HI +#define WGS_MIP_HI__MIP_HI__SHIFT 0x0 +#define WGS_MIP_HI__MIP_HI_MASK 0xFFFFFFFFL +//WGS_DC_BASE_CNTL +#define WGS_DC_BASE_CNTL__VMID__SHIFT 0x0 +#define WGS_DC_BASE_CNTL__VMID_MASK 0x0000000FL +//WGS_DC_OP_CNTL +#define WGS_DC_OP_CNTL__INVALIDATE_DCACHE__SHIFT 0x0 +#define WGS_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE__SHIFT 0x1 +#define WGS_DC_OP_CNTL__BYPASS_ALL__SHIFT 0x2 +#define WGS_DC_OP_CNTL__INVALIDATE_DCACHE_MASK 0x00000001L +#define WGS_DC_OP_CNTL__INVALIDATE_DCACHE_COMPLETE_MASK 0x00000002L +#define WGS_DC_OP_CNTL__BYPASS_ALL_MASK 0x00000004L +//WGS_MTIMECMP_LO +#define WGS_MTIMECMP_LO__TIME_LO__SHIFT 0x0 +#define WGS_MTIMECMP_LO__TIME_LO_MASK 0xFFFFFFFFL +//WGS_MTIMECMP_HI +#define WGS_MTIMECMP_HI__TIME_HI__SHIFT 0x0 +#define WGS_MTIMECMP_HI__TIME_HI_MASK 0xFFFFFFFFL +//WGS_GP0_LO +#define WGS_GP0_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define WGS_GP0_LO__DATA__SHIFT 0x1 +#define WGS_GP0_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define WGS_GP0_LO__DATA_MASK 0xFFFFFFFEL +//WGS_GP0_HI +#define WGS_GP0_HI__M_RET_ADDR__SHIFT 0x0 +#define WGS_GP0_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//WGS_GP1_LO +#define WGS_GP1_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define WGS_GP1_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//WGS_GP1_HI +#define WGS_GP1_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define WGS_GP1_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//WGS_GP2_LO +#define WGS_GP2_LO__STACK_PNTR_LO__SHIFT 0x0 +#define WGS_GP2_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//WGS_GP2_HI +#define WGS_GP2_HI__STACK_PNTR_HI__SHIFT 0x0 +#define WGS_GP2_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//WGS_GP3_LO +#define WGS_GP3_LO__DATA__SHIFT 0x0 +#define WGS_GP3_LO__DATA_MASK 0xFFFFFFFFL +//WGS_GP3_HI +#define WGS_GP3_HI__DATA__SHIFT 0x0 +#define WGS_GP3_HI__DATA_MASK 0xFFFFFFFFL +//WGS_GP4_LO +#define WGS_GP4_LO__DATA__SHIFT 0x0 +#define WGS_GP4_LO__DATA_MASK 0xFFFFFFFFL +//WGS_GP4_HI +#define WGS_GP4_HI__DATA__SHIFT 0x0 +#define WGS_GP4_HI__DATA_MASK 0xFFFFFFFFL +//WGS_GP5_LO +#define WGS_GP5_LO__PG_VIRT_HALTED__SHIFT 0x0 +#define WGS_GP5_LO__DATA__SHIFT 0x1 +#define WGS_GP5_LO__PG_VIRT_HALTED_MASK 0x00000001L +#define WGS_GP5_LO__DATA_MASK 0xFFFFFFFEL +//WGS_GP5_HI +#define WGS_GP5_HI__M_RET_ADDR__SHIFT 0x0 +#define WGS_GP5_HI__M_RET_ADDR_MASK 0xFFFFFFFFL +//WGS_GP6_LO +#define WGS_GP6_LO__RD_WR_SELECT_LO__SHIFT 0x0 +#define WGS_GP6_LO__RD_WR_SELECT_LO_MASK 0xFFFFFFFFL +//WGS_GP6_HI +#define WGS_GP6_HI__RD_WR_SELECT_HI__SHIFT 0x0 +#define WGS_GP6_HI__RD_WR_SELECT_HI_MASK 0xFFFFFFFFL +//WGS_GP7_LO +#define WGS_GP7_LO__STACK_PNTR_LO__SHIFT 0x0 +#define WGS_GP7_LO__STACK_PNTR_LO_MASK 0xFFFFFFFFL +//WGS_GP7_HI +#define WGS_GP7_HI__STACK_PNTR_HI__SHIFT 0x0 +#define WGS_GP7_HI__STACK_PNTR_HI_MASK 0xFFFFFFFFL +//WGS_GP8_LO +#define WGS_GP8_LO__DATA__SHIFT 0x0 +#define WGS_GP8_LO__DATA_MASK 0xFFFFFFFFL +//WGS_GP8_HI +#define WGS_GP8_HI__DATA__SHIFT 0x0 +#define WGS_GP8_HI__DATA_MASK 0xFFFFFFFFL +//WGS_GP9_LO +#define WGS_GP9_LO__DATA__SHIFT 0x0 +#define WGS_GP9_LO__DATA_MASK 0xFFFFFFFFL +//WGS_GP9_HI +#define WGS_GP9_HI__DATA__SHIFT 0x0 +#define WGS_GP9_HI__DATA_MASK 0xFFFFFFFFL +//WGS_DM_INDEX_ADDR +#define WGS_DM_INDEX_ADDR__ADDR__SHIFT 0x0 +#define WGS_DM_INDEX_ADDR__ADDR_MASK 0xFFFFFFFFL +//WGS_DM_INDEX_DATA +#define WGS_DM_INDEX_DATA__DATA__SHIFT 0x0 +#define WGS_DM_INDEX_DATA__DATA_MASK 0xFFFFFFFFL +//WGS_LOCAL_BASE0_LO +#define WGS_LOCAL_BASE0_LO__BASE0_LO__SHIFT 0x10 +#define WGS_LOCAL_BASE0_LO__BASE0_LO_MASK 0xFFFF0000L +//WGS_LOCAL_BASE0_HI +#define WGS_LOCAL_BASE0_HI__BASE0_HI__SHIFT 0x0 +#define WGS_LOCAL_BASE0_HI__BASE0_HI_MASK 0x0000FFFFL +//WGS_LOCAL_MASK0_LO +#define WGS_LOCAL_MASK0_LO__MASK0_LO__SHIFT 0x10 +#define WGS_LOCAL_MASK0_LO__MASK0_LO_MASK 0xFFFF0000L +//WGS_LOCAL_MASK0_HI +#define WGS_LOCAL_MASK0_HI__MASK0_HI__SHIFT 0x0 +#define WGS_LOCAL_MASK0_HI__MASK0_HI_MASK 0x0000FFFFL +//WGS_LOCAL_APERTURE +#define WGS_LOCAL_APERTURE__APERTURE__SHIFT 0x0 +#define WGS_LOCAL_APERTURE__SCOPE__SHIFT 0x6 +#define WGS_LOCAL_APERTURE__TEMPORAL__SHIFT 0x8 +#define WGS_LOCAL_APERTURE__APERTURE_MASK 0x00000007L +#define WGS_LOCAL_APERTURE__SCOPE_MASK 0x000000C0L +#define WGS_LOCAL_APERTURE__TEMPORAL_MASK 0x00000700L +//WGS_LOCAL_INSTR_BASE_LO +#define WGS_LOCAL_INSTR_BASE_LO__BASE_LO__SHIFT 0x10 +#define WGS_LOCAL_INSTR_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//WGS_LOCAL_INSTR_BASE_HI +#define WGS_LOCAL_INSTR_BASE_HI__BASE_HI__SHIFT 0x0 +#define WGS_LOCAL_INSTR_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//WGS_LOCAL_INSTR_MASK_LO +#define WGS_LOCAL_INSTR_MASK_LO__MASK_LO__SHIFT 0x10 +#define WGS_LOCAL_INSTR_MASK_LO__MASK_LO_MASK 0xFFFF0000L +//WGS_LOCAL_INSTR_MASK_HI +#define WGS_LOCAL_INSTR_MASK_HI__MASK_HI__SHIFT 0x0 +#define WGS_LOCAL_INSTR_MASK_HI__MASK_HI_MASK 0x0000FFFFL +//WGS_LOCAL_INSTR_APERTURE +#define WGS_LOCAL_INSTR_APERTURE__APERTURE__SHIFT 0x0 +#define WGS_LOCAL_INSTR_APERTURE__SCOPE__SHIFT 0x6 +#define WGS_LOCAL_INSTR_APERTURE__TEMPORAL__SHIFT 0x8 +#define WGS_LOCAL_INSTR_APERTURE__APERTURE_MASK 0x00000007L +#define WGS_LOCAL_INSTR_APERTURE__SCOPE_MASK 0x000000C0L +#define WGS_LOCAL_INSTR_APERTURE__TEMPORAL_MASK 0x00000700L +//WGS_LOCAL_SCRATCH_APERTURE +#define WGS_LOCAL_SCRATCH_APERTURE__APERTURE__SHIFT 0x0 +#define WGS_LOCAL_SCRATCH_APERTURE__APERTURE_MASK 0x00000007L +//WGS_LOCAL_SCRATCH_BASE_LO +#define WGS_LOCAL_SCRATCH_BASE_LO__BASE_LO__SHIFT 0x10 +#define WGS_LOCAL_SCRATCH_BASE_LO__BASE_LO_MASK 0xFFFF0000L +//WGS_LOCAL_SCRATCH_BASE_HI +#define WGS_LOCAL_SCRATCH_BASE_HI__BASE_HI__SHIFT 0x0 +#define WGS_LOCAL_SCRATCH_BASE_HI__BASE_HI_MASK 0x0000FFFFL +//WGS_RS64_PERFCOUNT_CNTL +#define WGS_RS64_PERFCOUNT_CNTL__EVENT_SEL__SHIFT 0x0 +#define WGS_RS64_PERFCOUNT_CNTL__EVENT_SEL_MASK 0x0000001FL +//WGS_RS64_PENDING_INTERRUPT +#define WGS_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT__SHIFT 0x0 +#define WGS_RS64_PENDING_INTERRUPT__PENDING_INTERRUPT_MASK 0xFFFFFFFFL +//WGS_RS64_EXCEPTION_STATUS +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION__SHIFT 0x0 +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR__SHIFT 0x1 +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION__SHIFT 0x2 +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT__SHIFT 0x3 +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR__SHIFT 0x4 +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_ILLEGAL_INSTRUCTION_MASK 0x00000001L +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_MISALIGNED_ADDR_MASK 0x00000002L +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_UNALIGNED_INSTRUTCION_MASK 0x00000004L +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_PAGE_FAULT_MASK 0x00000008L +#define WGS_RS64_EXCEPTION_STATUS__RS64_EXCEPTION_INSTRUCTION_ADDR_MASK 0x07FFFFF0L +//WGS_RS64_PRGRM_CNTR_START_HI +#define WGS_RS64_PRGRM_CNTR_START_HI__IP_START__SHIFT 0x0 +#define WGS_RS64_PRGRM_CNTR_START_HI__IP_START_MASK 0x3FFFFFFFL +//WGS_DC_BASE_LO +#define WGS_DC_BASE_LO__DC_BASE_LO__SHIFT 0x10 +#define WGS_DC_BASE_LO__DC_BASE_LO_MASK 0xFFFF0000L +//WGS_MDBASE_LO +#define WGS_MDBASE_LO__BASE_LO__SHIFT 0x10 +#define WGS_MDBASE_LO__BASE_LO_MASK 0xFFFF0000L +//WGS_DC_BASE_HI +#define WGS_DC_BASE_HI__DC_BASE_HI__SHIFT 0x0 +#define WGS_DC_BASE_HI__DC_BASE_HI_MASK 0x0000FFFFL +//WGS_MDBASE_HI +#define WGS_MDBASE_HI__BASE_HI__SHIFT 0x0 +#define WGS_MDBASE_HI__BASE_HI_MASK 0x0000FFFFL +//WGS_MIBOUND_LO +#define WGS_MIBOUND_LO__BOUND_LO__SHIFT 0x0 +#define WGS_MIBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//WGS_MIBOUND_HI +#define WGS_MIBOUND_HI__BOUND_HI__SHIFT 0x0 +#define WGS_MIBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//WGS_MDBOUND_LO +#define WGS_MDBOUND_LO__BOUND_LO__SHIFT 0x0 +#define WGS_MDBOUND_LO__BOUND_LO_MASK 0xFFFFFFFFL +//WGS_MDBOUND_HI +#define WGS_MDBOUND_HI__BOUND_HI__SHIFT 0x0 +#define WGS_MDBOUND_HI__BOUND_HI_MASK 0xFFFFFFFFL +//WGS_IC_OP_CNTL +#define WGS_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define WGS_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE__SHIFT 0x1 +#define WGS_IC_OP_CNTL__HALT_ON_PRIME__SHIFT 0x2 +#define WGS_IC_OP_CNTL__PRIME_START_PC__SHIFT 0x3 +#define WGS_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define WGS_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define WGS_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x00000001L +#define WGS_IC_OP_CNTL__INVALIDATE_CACHE_COMPLETE_MASK 0x00000002L +#define WGS_IC_OP_CNTL__HALT_ON_PRIME_MASK 0x00000004L +#define WGS_IC_OP_CNTL__PRIME_START_PC_MASK 0x00000008L +#define WGS_IC_OP_CNTL__PRIME_ICACHE_MASK 0x00000010L +#define WGS_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x00000020L +//WGS_INT_STATUS +#define WGS_INT_STATUS__SOURCE_ID__SHIFT 0x0 +#define WGS_INT_STATUS__SEND__SHIFT 0x8 +#define WGS_INT_STATUS__SOURCE_ID_MASK 0x000000FFL +#define WGS_INT_STATUS__SEND_MASK 0x00000100L +//WGS_IH_FREE_COUNT +#define WGS_IH_FREE_COUNT__COUNT__SHIFT 0x0 +#define WGS_IH_FREE_COUNT__COUNT_MASK 0x000000FFL +//WGS_ME1_PIPE_PRIORITY_CNTS +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0x000000FFL +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0x0000FF00L +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0x00FF0000L +#define WGS_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xFF000000L +//WGS_ME1_PIPE0_PRIORITY +#define WGS_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define WGS_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x00000003L +//WGS_ME1_PIPE1_PRIORITY +#define WGS_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define WGS_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x00000003L +//WGS_ME1_PIPE2_PRIORITY +#define WGS_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define WGS_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x00000003L +//WGS_ME1_PIPE3_PRIORITY +#define WGS_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define WGS_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x00000003L +//WGS_IQ_WAIT_TIME1 +#define WGS_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 +#define WGS_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 +#define WGS_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 +#define WGS_IQ_WAIT_TIME1__GWS__SHIFT 0x18 +#define WGS_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0x000000FFL +#define WGS_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0x0000FF00L +#define WGS_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0x00FF0000L +#define WGS_IQ_WAIT_TIME1__GWS_MASK 0xFF000000L +//WGS_IQ_WAIT_TIME2 +#define WGS_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 +#define WGS_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 +#define WGS_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 +#define WGS_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0x000000FFL +#define WGS_IQ_WAIT_TIME2__SCH_WAVE_MASK 0x0000FF00L +#define WGS_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xFF000000L +//WGS_IC_BASE_LO +#define WGS_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define WGS_IC_BASE_LO__IC_BASE_LO_MASK 0xFFFFF000L +//WGS_IC_BASE_HI +#define WGS_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define WGS_IC_BASE_HI__IC_BASE_HI_MASK 0x0000FFFFL +//WGS_IC_BASE_CNTL +#define WGS_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define WGS_IC_BASE_CNTL__PER_PIPE__SHIFT 0x5 +#define WGS_IC_BASE_CNTL__SCOPE__SHIFT 0x6 +#define WGS_IC_BASE_CNTL__TEMPORAL__SHIFT 0x8 +#define WGS_IC_BASE_CNTL__EXE_DISABLE__SHIFT 0x17 +#define WGS_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define WGS_IC_BASE_CNTL__VMID_MASK 0x0000000FL +#define WGS_IC_BASE_CNTL__PER_PIPE_MASK 0x00000020L +#define WGS_IC_BASE_CNTL__SCOPE_MASK 0x000000C0L +#define WGS_IC_BASE_CNTL__TEMPORAL_MASK 0x00000700L +#define WGS_IC_BASE_CNTL__EXE_DISABLE_MASK 0x00800000L +#define WGS_IC_BASE_CNTL__CACHE_POLICY_MASK 0x03000000L +//WGS_UCODE_VERS +#define WGS_UCODE_VERS__ENGINE__SHIFT 0x0 +#define WGS_UCODE_VERS__COMMON__SHIFT 0xa +#define WGS_UCODE_VERS__HEADER__SHIFT 0x14 +#define WGS_UCODE_VERS__STEP__SHIFT 0x1e +#define WGS_UCODE_VERS__ENGINE_MASK 0x000003FFL +#define WGS_UCODE_VERS__COMMON_MASK 0x000FFC00L +#define WGS_UCODE_VERS__HEADER_MASK 0x3FF00000L +#define WGS_UCODE_VERS__STEP_MASK 0xC0000000L +//WGS_BUSY_HYSTERESIS +#define WGS_BUSY_HYSTERESIS__CAC_ACTIVE__SHIFT 0x0 +#define WGS_BUSY_HYSTERESIS__CPC_BUSY__SHIFT 0x8 +#define WGS_BUSY_HYSTERESIS__CAC_ACTIVE_MASK 0x000000FFL +#define WGS_BUSY_HYSTERESIS__CPC_BUSY_MASK 0x0000FF00L +//WGS_STATUS +#define WGS_STATUS__MEC1_BUSY__SHIFT 0x0 +#define WGS_STATUS__MEC2_BUSY__SHIFT 0x1 +#define WGS_STATUS__DC0_BUSY__SHIFT 0x2 +#define WGS_STATUS__DC1_BUSY__SHIFT 0x3 +#define WGS_STATUS__RCIU1_BUSY__SHIFT 0x4 +#define WGS_STATUS__RCIU2_BUSY__SHIFT 0x5 +#define WGS_STATUS__ROQ1_BUSY__SHIFT 0x6 +#define WGS_STATUS__ROQ2_BUSY__SHIFT 0x7 +#define WGS_STATUS__TMZ_STATE__SHIFT 0x8 +#define WGS_STATUS__VMID_TMZ__SHIFT 0x9 +#define WGS_STATUS__TCIU_BUSY__SHIFT 0xa +#define WGS_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb +#define WGS_STATUS__QU_BUSY__SHIFT 0xc +#define WGS_STATUS__UTCL2IU_BUSY__SHIFT 0xd +#define WGS_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe +#define WGS_STATUS__GCRIU_BUSY__SHIFT 0xf +#define WGS_STATUS__MES_BUSY__SHIFT 0x10 +#define WGS_STATUS__MES_SCRATCH_RAM_BUSY__SHIFT 0x11 +#define WGS_STATUS__RCIU3_BUSY__SHIFT 0x12 +#define WGS_STATUS__MES_INSTRUCTION_CACHE_BUSY__SHIFT 0x13 +#define WGS_STATUS__MES_DATA_CACHE_BUSY__SHIFT 0x14 +#define WGS_STATUS__MEC_DATA_CACHE_BUSY__SHIFT 0x15 +#define WGS_STATUS__GL1_XNACK__SHIFT 0x16 +#define WGS_STATUS__RSRV__SHIFT 0x18 +#define WGS_STATUS__WGS_BUSY__SHIFT 0x1f +#define WGS_STATUS__MEC1_BUSY_MASK 0x00000001L +#define WGS_STATUS__MEC2_BUSY_MASK 0x00000002L +#define WGS_STATUS__DC0_BUSY_MASK 0x00000004L +#define WGS_STATUS__DC1_BUSY_MASK 0x00000008L +#define WGS_STATUS__RCIU1_BUSY_MASK 0x00000010L +#define WGS_STATUS__RCIU2_BUSY_MASK 0x00000020L +#define WGS_STATUS__ROQ1_BUSY_MASK 0x00000040L +#define WGS_STATUS__ROQ2_BUSY_MASK 0x00000080L +#define WGS_STATUS__TMZ_STATE_MASK 0x00000100L +#define WGS_STATUS__VMID_TMZ_MASK 0x00000200L +#define WGS_STATUS__TCIU_BUSY_MASK 0x00000400L +#define WGS_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L +#define WGS_STATUS__QU_BUSY_MASK 0x00001000L +#define WGS_STATUS__UTCL2IU_BUSY_MASK 0x00002000L +#define WGS_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L +#define WGS_STATUS__GCRIU_BUSY_MASK 0x00008000L +#define WGS_STATUS__MES_BUSY_MASK 0x00010000L +#define WGS_STATUS__MES_SCRATCH_RAM_BUSY_MASK 0x00020000L +#define WGS_STATUS__RCIU3_BUSY_MASK 0x00040000L +#define WGS_STATUS__MES_INSTRUCTION_CACHE_BUSY_MASK 0x00080000L +#define WGS_STATUS__MES_DATA_CACHE_BUSY_MASK 0x00100000L +#define WGS_STATUS__MEC_DATA_CACHE_BUSY_MASK 0x00200000L +#define WGS_STATUS__GL1_XNACK_MASK 0x00C00000L +#define WGS_STATUS__RSRV_MASK 0x7F000000L +#define WGS_STATUS__WGS_BUSY_MASK 0x80000000L +//WGS_BUSY_STAT +#define WGS_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 +#define WGS_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 +#define WGS_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 +#define WGS_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 +#define WGS_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 +#define WGS_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 +#define WGS_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 +#define WGS_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 +#define WGS_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 +#define WGS_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa +#define WGS_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb +#define WGS_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc +#define WGS_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd +#define WGS_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 +#define WGS_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 +#define WGS_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 +#define WGS_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 +#define WGS_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 +#define WGS_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 +#define WGS_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 +#define WGS_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 +#define WGS_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 +#define WGS_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a +#define WGS_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b +#define WGS_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c +#define WGS_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d +#define WGS_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L +#define WGS_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L +#define WGS_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L +#define WGS_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L +#define WGS_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L +#define WGS_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L +#define WGS_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L +#define WGS_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L +#define WGS_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L +#define WGS_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L +#define WGS_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L +#define WGS_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L +#define WGS_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L +#define WGS_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L +#define WGS_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L +#define WGS_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L +#define WGS_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L +#define WGS_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L +#define WGS_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L +#define WGS_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L +#define WGS_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L +#define WGS_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L +#define WGS_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L +#define WGS_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L +#define WGS_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L +#define WGS_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L +//WGS_STALLED_STAT1 +#define WGS_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 +#define WGS_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 +#define WGS_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 +#define WGS_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x7 +#define WGS_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd +#define WGS_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 +#define WGS_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 +#define WGS_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 +#define WGS_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 +#define WGS_STALLED_STAT1__GCRIU_WAITING_ON_FREE__SHIFT 0x19 +#define WGS_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L +#define WGS_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L +#define WGS_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L +#define WGS_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x00000080L +#define WGS_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L +#define WGS_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L +#define WGS_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L +#define WGS_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L +#define WGS_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L +#define WGS_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L +#define WGS_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L +#define WGS_STALLED_STAT1__GCRIU_WAITING_ON_FREE_MASK 0x02000000L +//WGS_BUSY_STAT2 +#define WGS_BUSY_STAT2__MES_LOAD_BUSY__SHIFT 0x0 +#define WGS_BUSY_STAT2__MES_MUTEX_BUSY__SHIFT 0x2 +#define WGS_BUSY_STAT2__MES_MESSAGE_BUSY__SHIFT 0x3 +#define WGS_BUSY_STAT2__MES_TC_BUSY__SHIFT 0x7 +#define WGS_BUSY_STAT2__MES_DMA_BUSY__SHIFT 0x8 +#define WGS_BUSY_STAT2__MES_PIPE0_BUSY__SHIFT 0xa +#define WGS_BUSY_STAT2__MES_PIPE1_BUSY__SHIFT 0xb +#define WGS_BUSY_STAT2__MES_PIPE2_BUSY__SHIFT 0xc +#define WGS_BUSY_STAT2__MES_PIPE3_BUSY__SHIFT 0xd +#define WGS_BUSY_STAT2__MEC1_PIPE0_DC_BUSY__SHIFT 0x12 +#define WGS_BUSY_STAT2__MEC1_PIPE1_DC_BUSY__SHIFT 0x13 +#define WGS_BUSY_STAT2__MEC1_PIPE2_DC_BUSY__SHIFT 0x14 +#define WGS_BUSY_STAT2__MEC1_PIPE3_DC_BUSY__SHIFT 0x15 +#define WGS_BUSY_STAT2__MES_LOAD_BUSY_MASK 0x00000001L +#define WGS_BUSY_STAT2__MES_MUTEX_BUSY_MASK 0x00000004L +#define WGS_BUSY_STAT2__MES_MESSAGE_BUSY_MASK 0x00000008L +#define WGS_BUSY_STAT2__MES_TC_BUSY_MASK 0x00000080L +#define WGS_BUSY_STAT2__MES_DMA_BUSY_MASK 0x00000100L +#define WGS_BUSY_STAT2__MES_PIPE0_BUSY_MASK 0x00000400L +#define WGS_BUSY_STAT2__MES_PIPE1_BUSY_MASK 0x00000800L +#define WGS_BUSY_STAT2__MES_PIPE2_BUSY_MASK 0x00001000L +#define WGS_BUSY_STAT2__MES_PIPE3_BUSY_MASK 0x00002000L +#define WGS_BUSY_STAT2__MEC1_PIPE0_DC_BUSY_MASK 0x00040000L +#define WGS_BUSY_STAT2__MEC1_PIPE1_DC_BUSY_MASK 0x00080000L +#define WGS_BUSY_STAT2__MEC1_PIPE2_DC_BUSY_MASK 0x00100000L +#define WGS_BUSY_STAT2__MEC1_PIPE3_DC_BUSY_MASK 0x00200000L +//WGS_ME1_HEADER_DUMP +#define WGS_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define WGS_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xFFFFFFFFL +//WGS_SCRATCH_INDEX +#define WGS_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define WGS_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE__SHIFT 0x1f +#define WGS_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x000001FFL +#define WGS_SCRATCH_INDEX__SCRATCH_INDEX_64BIT_MODE_MASK 0x80000000L +//WGS_SCRATCH_DATA +#define WGS_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define WGS_SCRATCH_DATA__SCRATCH_DATA_MASK 0xFFFFFFFFL +//WGS_LATENCY_STATS_SELECT +#define WGS_LATENCY_STATS_SELECT__INDEX__SHIFT 0x0 +#define WGS_LATENCY_STATS_SELECT__CLEAR__SHIFT 0x1e +#define WGS_LATENCY_STATS_SELECT__ENABLE__SHIFT 0x1f +#define WGS_LATENCY_STATS_SELECT__INDEX_MASK 0x0000001FL +#define WGS_LATENCY_STATS_SELECT__CLEAR_MASK 0x40000000L +#define WGS_LATENCY_STATS_SELECT__ENABLE_MASK 0x80000000L +//WGS_LATENCY_STATS_DATA +#define WGS_LATENCY_STATS_DATA__DATA__SHIFT 0x0 +#define WGS_LATENCY_STATS_DATA__DATA_MASK 0xFFFFFFFFL +//WGS_TC_PERF_COUNTER_WINDOW_SELECT +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__INDEX__SHIFT 0x0 +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS__SHIFT 0x1e +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE__SHIFT 0x1f +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__INDEX_MASK 0x0000001FL +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__ALWAYS_MASK 0x40000000L +#define WGS_TC_PERF_COUNTER_WINDOW_SELECT__ENABLE_MASK 0x80000000L +//WGS_DATA1 +#define WGS_DATA1__DATA__SHIFT 0x0 +#define WGS_DATA1__DATA_MASK 0xFFFFFFFFL +//WGS_DATA2 +#define WGS_DATA2__DATA__SHIFT 0x0 +#define WGS_DATA2__DATA_MASK 0xFFFFFFFFL +//WGS_DATA3 +#define WGS_DATA3__DATA__SHIFT 0x0 +#define WGS_DATA3__DATA_MASK 0xFFFFFFFFL +//WGS_DATA4 +#define WGS_DATA4__DATA__SHIFT 0x0 +#define WGS_DATA4__DATA_MASK 0xFFFFFFFFL +//WGS_DATA5 +#define WGS_DATA5__DATA__SHIFT 0x0 +#define WGS_DATA5__DATA_MASK 0xFFFFFFFFL +//WGS_DATA6 +#define WGS_DATA6__DATA__SHIFT 0x0 +#define WGS_DATA6__DATA_MASK 0xFFFFFFFFL +//WGS_DATA7 +#define WGS_DATA7__DATA__SHIFT 0x0 +#define WGS_DATA7__DATA_MASK 0xFFFFFFFFL +//WGS_DATA8 +#define WGS_DATA8__DATA__SHIFT 0x0 +#define WGS_DATA8__DATA_MASK 0xFFFFFFFFL +//WGS_DATA9 +#define WGS_DATA9__DATA__SHIFT 0x0 +#define WGS_DATA9__DATA_MASK 0xFFFFFFFFL +//WGS_DATA10 +#define WGS_DATA10__DATA__SHIFT 0x0 +#define WGS_DATA10__DATA_MASK 0xFFFFFFFFL +//WGS_DATA11 +#define WGS_DATA11__DATA__SHIFT 0x0 +#define WGS_DATA11__DATA_MASK 0xFFFFFFFFL +//WGS_DATA12 +#define WGS_DATA12__DATA__SHIFT 0x0 +#define WGS_DATA12__DATA_MASK 0xFFFFFFFFL +//WGS_DATA13 +#define WGS_DATA13__DATA__SHIFT 0x0 +#define WGS_DATA13__DATA_MASK 0xFFFFFFFFL +//WGS_DATA14 +#define WGS_DATA14__DATA__SHIFT 0x0 +#define WGS_DATA14__DATA_MASK 0xFFFFFFFFL +//WGS_DATA15 +#define WGS_DATA15__DATA__SHIFT 0x0 +#define WGS_DATA15__DATA_MASK 0xFFFFFFFFL +//WGS_DATA16 +#define WGS_DATA16__DATA__SHIFT 0x0 +#define WGS_DATA16__DATA_MASK 0xFFFFFFFFL +//WGS_METADATA_BASE_ADDR_LO +#define WGS_METADATA_BASE_ADDR_LO__MD_BASE_LO__SHIFT 0x2 +#define WGS_METADATA_BASE_ADDR_LO__MD_BASE_LO_MASK 0xFFFFFFFCL +//WGS_METADATA_BASE_ADDR_HI +#define WGS_METADATA_BASE_ADDR_HI__MD_BASE_HI__SHIFT 0x0 +#define WGS_METADATA_BASE_ADDR_HI__MD_BASE_HI_MASK 0x0000FFFFL +//WGS_METADATA_CNTL +#define WGS_METADATA_CNTL__VMID__SHIFT 0x0 +#define WGS_METADATA_CNTL__EVENT_MODE__SHIFT 0x4 +#define WGS_METADATA_CNTL__SCOPE__SHIFT 0x6 +#define WGS_METADATA_CNTL__TEMPORAL__SHIFT 0x8 +#define WGS_METADATA_CNTL__EVENT1__SHIFT 0xb +#define WGS_METADATA_CNTL__QUEUE_ID__SHIFT 0xc +#define WGS_METADATA_CNTL__VMID_MASK 0x0000000FL +#define WGS_METADATA_CNTL__EVENT_MODE_MASK 0x00000030L +#define WGS_METADATA_CNTL__SCOPE_MASK 0x000000C0L +#define WGS_METADATA_CNTL__TEMPORAL_MASK 0x00000700L +#define WGS_METADATA_CNTL__EVENT1_MASK 0x00000800L +#define WGS_METADATA_CNTL__QUEUE_ID_MASK 0x00007000L +//WGS_IQ_TIMER +#define WGS_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define WGS_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define WGS_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define WGS_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define WGS_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define WGS_IQ_TIMER__RESERVED3__SHIFT 0x10 +#define WGS_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define WGS_IQ_TIMER__RESERVED2__SHIFT 0x17 +#define WGS_IQ_TIMER__QUEUE_TYPE__SHIFT 0x1b +#define WGS_IQ_TIMER__REARM_TIMER__SHIFT 0x1c +#define WGS_IQ_TIMER__RESERVED1__SHIFT 0x1d +#define WGS_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define WGS_IQ_TIMER__WAIT_TIME_MASK 0x000000FFL +#define WGS_IQ_TIMER__RETRY_TYPE_MASK 0x00000700L +#define WGS_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x00000800L +#define WGS_IQ_TIMER__INTERRUPT_TYPE_MASK 0x00003000L +#define WGS_IQ_TIMER__CLOCK_COUNT_MASK 0x0000C000L +#define WGS_IQ_TIMER__RESERVED3_MASK 0x003F0000L +#define WGS_IQ_TIMER__QUANTUM_TIMER_MASK 0x00400000L +#define WGS_IQ_TIMER__RESERVED2_MASK 0x07800000L +#define WGS_IQ_TIMER__QUEUE_TYPE_MASK 0x08000000L +#define WGS_IQ_TIMER__REARM_TIMER_MASK 0x10000000L +#define WGS_IQ_TIMER__RESERVED1_MASK 0x60000000L +#define WGS_IQ_TIMER__ACTIVE_MASK 0x80000000L +//WGS_HALT_HYST_COUNT +#define WGS_HALT_HYST_COUNT__COUNT__SHIFT 0x0 +#define WGS_HALT_HYST_COUNT__COUNT_MASK 0x0000000FL +//WGS_IQ_TIMER_MESSAGE +#define WGS_IQ_TIMER_MESSAGE__MESSAGE__SHIFT 0x0 +#define WGS_IQ_TIMER_MESSAGE__MESSAGE_MASK 0x000000FFL +//WGS_RS64_THREAD_CNTL +#define WGS_RS64_THREAD_CNTL__MEC_STATUS__SHIFT 0x0 +#define WGS_RS64_THREAD_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define WGS_RS64_THREAD_CNTL__MEC_PIPE_RESET__SHIFT 0x10 +#define WGS_RS64_THREAD_CNTL__RSRV7__SHIFT 0x11 +#define WGS_RS64_THREAD_CNTL__RSRV6__SHIFT 0x12 +#define WGS_RS64_THREAD_CNTL__RSRV5__SHIFT 0x13 +#define WGS_RS64_THREAD_CNTL__MEC_PIPE_ACTIVE__SHIFT 0x1a +#define WGS_RS64_THREAD_CNTL__RSRV4__SHIFT 0x1b +#define WGS_RS64_THREAD_CNTL__RSRV3__SHIFT 0x1c +#define WGS_RS64_THREAD_CNTL__RSRV2__SHIFT 0x1d +#define WGS_RS64_THREAD_CNTL__SPARE__SHIFT 0x1e +#define WGS_RS64_THREAD_CNTL__RSRV1__SHIFT 0x1f +#define WGS_RS64_THREAD_CNTL__MEC_STATUS_MASK 0x0000000FL +#define WGS_RS64_THREAD_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x00000010L +#define WGS_RS64_THREAD_CNTL__MEC_PIPE_RESET_MASK 0x00010000L +#define WGS_RS64_THREAD_CNTL__RSRV7_MASK 0x00020000L +#define WGS_RS64_THREAD_CNTL__RSRV6_MASK 0x00040000L +#define WGS_RS64_THREAD_CNTL__RSRV5_MASK 0x00080000L +#define WGS_RS64_THREAD_CNTL__MEC_PIPE_ACTIVE_MASK 0x04000000L +#define WGS_RS64_THREAD_CNTL__RSRV4_MASK 0x08000000L +#define WGS_RS64_THREAD_CNTL__RSRV3_MASK 0x10000000L +#define WGS_RS64_THREAD_CNTL__RSRV2_MASK 0x20000000L +#define WGS_RS64_THREAD_CNTL__SPARE_MASK 0x40000000L +#define WGS_RS64_THREAD_CNTL__RSRV1_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gl1dec +//GL1_ARB_CTRL +#define GL1_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 +#define GL1_ARB_CTRL__FGCG_DISABLE__SHIFT 0x4 +#define GL1_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x5 +#define GL1_ARB_CTRL__CHICKEN_BITS__SHIFT 0x6 +#define GL1_ARB_CTRL__RETURN_ARB_MODE_COUNTER__SHIFT 0xe +#define GL1_ARB_CTRL__RETURN_256B_ARB_MODE_COUNTER__SHIFT 0x12 +#define GL1_ARB_CTRL__NUM_MEM_PIPES_MASK 0x0000000FL +#define GL1_ARB_CTRL__FGCG_DISABLE_MASK 0x00000010L +#define GL1_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000020L +#define GL1_ARB_CTRL__CHICKEN_BITS_MASK 0x00003FC0L +#define GL1_ARB_CTRL__RETURN_ARB_MODE_COUNTER_MASK 0x0003C000L +#define GL1_ARB_CTRL__RETURN_256B_ARB_MODE_COUNTER_MASK 0x003C0000L +//GL1_DRAM_BURST_MASK +#define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 +#define GL1_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL +//GL1_ARB_STATUS +#define GL1_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 +#define GL1_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 +#define GL1_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L +#define GL1_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L +//GL1_DRAM_BURST_CTRL +#define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 +#define GL1_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 +#define GL1_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L +#define GL1_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L +//GL1I_GL1R_REP_FGCG_OVERRIDE +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE__SHIFT 0x0 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE__SHIFT 0x1 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IR_REP_FGCG_OVERRIDE_MASK 0x00000001L +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1IW_REP_FGCG_OVERRIDE_MASK 0x00000002L +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L +#define GL1I_GL1R_REP_FGCG_OVERRIDE__GL1A_GL1R_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L +//GL1A_GL1C_CREDITS +#define GL1A_GL1C_CREDITS__GL1C_REQ_CREDITS__SHIFT 0x0 +#define GL1A_GL1C_CREDITS__GL1C_DATA_CREDITS__SHIFT 0x8 +#define GL1A_GL1C_CREDITS__GL1C_REQ_CREDITS_MASK 0x000000FFL +#define GL1A_GL1C_CREDITS__GL1C_DATA_CREDITS_MASK 0x0000FF00L +//GL1A_CLIENT_FREE_DELAY +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT 0x0 +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT 0x3 +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT 0x6 +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK 0x00000007L +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK 0x00000038L +#define GL1A_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK 0x000001C0L +//GL1X_ARB_CTRL +#define GL1X_ARB_CTRL__NUM_MEM_PIPES__SHIFT 0x0 +#define GL1X_ARB_CTRL__FGCG_DISABLE__SHIFT 0x2 +#define GL1X_ARB_CTRL__PERF_CNTR_EN_OVERRIDE__SHIFT 0x3 +#define GL1X_ARB_CTRL__CHICKEN_BITS__SHIFT 0x4 +#define GL1X_ARB_CTRL__NUM_MEM_PIPES_MASK 0x00000003L +#define GL1X_ARB_CTRL__FGCG_DISABLE_MASK 0x00000004L +#define GL1X_ARB_CTRL__PERF_CNTR_EN_OVERRIDE_MASK 0x00000008L +#define GL1X_ARB_CTRL__CHICKEN_BITS_MASK 0x00000FF0L +//GL1X_DRAM_BURST_MASK +#define GL1X_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK__SHIFT 0x0 +#define GL1X_DRAM_BURST_MASK__DRAM_BURST_ADDR_MASK_MASK 0x000000FFL +//GL1X_ARB_STATUS +#define GL1X_ARB_STATUS__REQ_ARB_BUSY__SHIFT 0x0 +#define GL1X_ARB_STATUS__RET_ARB_BUSY__SHIFT 0x1 +#define GL1X_ARB_STATUS__REQ_ARB_BUSY_MASK 0x00000001L +#define GL1X_ARB_STATUS__RET_ARB_BUSY_MASK 0x00000002L +//GL1X_DRAM_BURST_CTRL +#define GL1X_DRAM_BURST_CTRL__MAX_DRAM_BURST__SHIFT 0x0 +#define GL1X_DRAM_BURST_CTRL__BURST_DISABLE__SHIFT 0x3 +#define GL1X_DRAM_BURST_CTRL__MAX_DRAM_BURST_MASK 0x00000007L +#define GL1X_DRAM_BURST_CTRL__BURST_DISABLE_MASK 0x00000008L +//GL1XI_GL1XR_REP_FGCG_OVERRIDE +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XIR_REP_FGCG_OVERRIDE__SHIFT 0x0 +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XIW_REP_FGCG_OVERRIDE__SHIFT 0x1 +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XR_SRC_REP_FGCG_OVERRIDE__SHIFT 0x2 +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XR_RET_REP_FGCG_OVERRIDE__SHIFT 0x3 +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XIR_REP_FGCG_OVERRIDE_MASK 0x00000001L +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XIW_REP_FGCG_OVERRIDE_MASK 0x00000002L +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XR_SRC_REP_FGCG_OVERRIDE_MASK 0x00000004L +#define GL1XI_GL1XR_REP_FGCG_OVERRIDE__GL1XA_GL1XR_RET_REP_FGCG_OVERRIDE_MASK 0x00000008L +//GL1XA_GL1XC_CREDITS +#define GL1XA_GL1XC_CREDITS__GL1XC_REQ_CREDITS__SHIFT 0x0 +#define GL1XA_GL1XC_CREDITS__GL1XC_DATA_CREDITS__SHIFT 0x8 +#define GL1XA_GL1XC_CREDITS__GL1XC_REQ_CREDITS_MASK 0x000000FFL +#define GL1XA_GL1XC_CREDITS__GL1XC_DATA_CREDITS_MASK 0x0000FF00L +//GL1XA_CLIENT_FREE_DELAY +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY__SHIFT 0x0 +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY__SHIFT 0x3 +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY__SHIFT 0x6 +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY__SHIFT 0x9 +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY__SHIFT 0xc +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_5_FREE_DELAY__SHIFT 0xf +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_0_FREE_DELAY_MASK 0x00000007L +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_1_FREE_DELAY_MASK 0x00000038L +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_2_FREE_DELAY_MASK 0x000001C0L +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_3_FREE_DELAY_MASK 0x00000E00L +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_4_FREE_DELAY_MASK 0x00007000L +#define GL1XA_CLIENT_FREE_DELAY__CLIENT_TYPE_5_FREE_DELAY_MASK 0x00038000L +//GL1XA_COMPRESSION_MODE +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_OVERRIDE__SHIFT 0x0 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_WRITE_COMPRESSION_DISABLE__SHIFT 0x1 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_BYPASS_COMPRESSION__SHIFT 0x2 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_OVERRIDE__SHIFT 0x3 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_WRITE_COMPRESSION_DISABLE__SHIFT 0x4 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_BYPASS_COMPRESSION__SHIFT 0x5 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_OVERRIDE__SHIFT 0x6 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_WRITE_COMPRESSION_DISABLE__SHIFT 0x7 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_BYPASS_COMPRESSION__SHIFT 0x8 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_OVERRIDE__SHIFT 0x9 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_WRITE_COMPRESSION_DISABLE__SHIFT 0xa +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_BYPASS_COMPRESSION__SHIFT 0xb +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_OVERRIDE__SHIFT 0xc +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_WRITE_COMPRESSION_DISABLE__SHIFT 0xd +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_BYPASS_COMPRESSION__SHIFT 0xe +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_OVERRIDE__SHIFT 0xf +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_WRITE_COMPRESSION_DISABLE__SHIFT 0x10 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_BYPASS_COMPRESSION__SHIFT 0x11 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_OVERRIDE__SHIFT 0x12 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_WRITE_COMPRESSION_DISABLE__SHIFT 0x13 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_BYPASS_COMPRESSION__SHIFT 0x14 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_OVERRIDE__SHIFT 0x15 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_WRITE_COMPRESSION_DISABLE__SHIFT 0x16 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_BYPASS_COMPRESSION__SHIFT 0x17 +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_OVERRIDE_MASK 0x00000001L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_WRITE_COMPRESSION_DISABLE_MASK 0x00000002L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_0_BYPASS_COMPRESSION_MASK 0x00000004L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_OVERRIDE_MASK 0x00000008L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_WRITE_COMPRESSION_DISABLE_MASK 0x00000010L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_1_BYPASS_COMPRESSION_MASK 0x00000020L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_OVERRIDE_MASK 0x00000040L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_WRITE_COMPRESSION_DISABLE_MASK 0x00000080L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_2_BYPASS_COMPRESSION_MASK 0x00000100L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_OVERRIDE_MASK 0x00000200L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_WRITE_COMPRESSION_DISABLE_MASK 0x00000400L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_3_BYPASS_COMPRESSION_MASK 0x00000800L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_OVERRIDE_MASK 0x00001000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_WRITE_COMPRESSION_DISABLE_MASK 0x00002000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_4_BYPASS_COMPRESSION_MASK 0x00004000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_OVERRIDE_MASK 0x00008000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_WRITE_COMPRESSION_DISABLE_MASK 0x00010000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_5_BYPASS_COMPRESSION_MASK 0x00020000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_OVERRIDE_MASK 0x00040000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_WRITE_COMPRESSION_DISABLE_MASK 0x00080000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_6_BYPASS_COMPRESSION_MASK 0x00100000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_OVERRIDE_MASK 0x00200000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_WRITE_COMPRESSION_DISABLE_MASK 0x00400000L +#define GL1XA_COMPRESSION_MODE__CLIENT_TYPE_7_BYPASS_COMPRESSION_MASK 0x00800000L +//GL1XA_COMPRESSOR_OVERRIDE +#define GL1XA_COMPRESSOR_OVERRIDE__DATA_FORMAT__SHIFT 0x0 +#define GL1XA_COMPRESSOR_OVERRIDE__MAX_COMP_BLOCK_SIZE__SHIFT 0x7 +#define GL1XA_COMPRESSOR_OVERRIDE__MAX_UNCOMP_BLOCK_SIZE__SHIFT 0x9 +#define GL1XA_COMPRESSOR_OVERRIDE__MICRO_TILE_MODE__SHIFT 0xa +#define GL1XA_COMPRESSOR_OVERRIDE__NUM_SAMPLES_LOG2__SHIFT 0xc +#define GL1XA_COMPRESSOR_OVERRIDE__NUMBER_TYPE__SHIFT 0xe +#define GL1XA_COMPRESSOR_OVERRIDE__DATA_FORMAT_MASK 0x0000003FL +#define GL1XA_COMPRESSOR_OVERRIDE__MAX_COMP_BLOCK_SIZE_MASK 0x00000180L +#define GL1XA_COMPRESSOR_OVERRIDE__MAX_UNCOMP_BLOCK_SIZE_MASK 0x00000200L +#define GL1XA_COMPRESSOR_OVERRIDE__MICRO_TILE_MODE_MASK 0x00000C00L +#define GL1XA_COMPRESSOR_OVERRIDE__NUM_SAMPLES_LOG2_MASK 0x00003000L +#define GL1XA_COMPRESSOR_OVERRIDE__NUMBER_TYPE_MASK 0x0001C000L +//GL1C_CTRL +#define GL1C_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 +#define GL1C_CTRL__GL2_REQ_CREDITS__SHIFT 0x4 +#define GL1C_CTRL__GL2_DATA_CREDITS__SHIFT 0xb +#define GL1C_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x12 +#define GL1C_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x13 +#define GL1C_CTRL__GL1C_LDBDCST_TIMER__SHIFT 0x14 +#define GL1C_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL +#define GL1C_CTRL__GL2_REQ_CREDITS_MASK 0x000007F0L +#define GL1C_CTRL__GL2_DATA_CREDITS_MASK 0x0003F800L +#define GL1C_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00040000L +#define GL1C_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00080000L +#define GL1C_CTRL__GL1C_LDBDCST_TIMER_MASK 0x1FF00000L +//GL1C_STATUS +#define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 +#define GL1C_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 +#define GL1C_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 +#define GL1C_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 +#define GL1C_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 +#define GL1C_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 +#define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 +#define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 +#define GL1C_STATUS__GL2_RH_BUSY__SHIFT 0x9 +#define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa +#define GL1C_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 +#define GL1C_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 +#define GL1C_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 +#define GL1C_STATUS__BUFFER_FULL__SHIFT 0x17 +#define GL1C_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L +#define GL1C_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L +#define GL1C_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L +#define GL1C_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L +#define GL1C_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L +#define GL1C_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L +#define GL1C_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L +#define GL1C_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L +#define GL1C_STATUS__GL2_RH_BUSY_MASK 0x00000200L +#define GL1C_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L +#define GL1C_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L +#define GL1C_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L +#define GL1C_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L +#define GL1C_STATUS__BUFFER_FULL_MASK 0x00800000L +//GL1C_CTRL2 +#define GL1C_CTRL2__OVERRIDE_READ_BYPASS_TO_DECOMPRESSED__SHIFT 0x8 +#define GL1C_CTRL2__OVERRIDE_WRITE_BYPASS_TO_COMPRESSION_DISABLE__SHIFT 0x9 +#define GL1C_CTRL2__OVERRIDE_READ_BYPASS_TO_DECOMPRESSED_MASK 0x00000100L +#define GL1C_CTRL2__OVERRIDE_WRITE_BYPASS_TO_COMPRESSION_DISABLE_MASK 0x00000200L +//GL1XC_CTRL +#define GL1XC_CTRL__BUFFER_DEPTH_MAX__SHIFT 0x0 +#define GL1XC_CTRL__GL2_REQ_CREDITS__SHIFT 0x4 +#define GL1XC_CTRL__GL2_DATA_CREDITS__SHIFT 0xb +#define GL1XC_CTRL__TO_L1_REPEATER_FGCG_DISABLE__SHIFT 0x12 +#define GL1XC_CTRL__TO_L2_REPEATER_FGCG_DISABLE__SHIFT 0x13 +#define GL1XC_CTRL__GCR_RSP_FGCG_DISABLE__SHIFT 0x14 +#define GL1XC_CTRL__BUFFER_DEPTH_MAX_MASK 0x0000000FL +#define GL1XC_CTRL__GL2_REQ_CREDITS_MASK 0x000007F0L +#define GL1XC_CTRL__GL2_DATA_CREDITS_MASK 0x0003F800L +#define GL1XC_CTRL__TO_L1_REPEATER_FGCG_DISABLE_MASK 0x00040000L +#define GL1XC_CTRL__TO_L2_REPEATER_FGCG_DISABLE_MASK 0x00080000L +#define GL1XC_CTRL__GCR_RSP_FGCG_DISABLE_MASK 0x00100000L +//GL1XC_STATUS +#define GL1XC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL__SHIFT 0x0 +#define GL1XC_STATUS__OUTPUT_FIFOS_BUSY__SHIFT 0x1 +#define GL1XC_STATUS__GL2_REQ_VC0_STALL__SHIFT 0x3 +#define GL1XC_STATUS__GL2_DATA_VC0_STALL__SHIFT 0x4 +#define GL1XC_STATUS__GL2_REQ_VC1_STALL__SHIFT 0x5 +#define GL1XC_STATUS__GL2_DATA_VC1_STALL__SHIFT 0x6 +#define GL1XC_STATUS__INPUT_BUFFER_VC0_BUSY__SHIFT 0x7 +#define GL1XC_STATUS__SRC_DATA_FIFO_VC0_BUSY__SHIFT 0x8 +#define GL1XC_STATUS__GL2_RH_BUSY__SHIFT 0x9 +#define GL1XC_STATUS__NUM_REQ_PENDING_FROM_L2__SHIFT 0xa +#define GL1XC_STATUS__VIRTUAL_FIFO_FULL_STALL__SHIFT 0x14 +#define GL1XC_STATUS__REQUEST_TRACKER_BUFFER_STALL__SHIFT 0x15 +#define GL1XC_STATUS__REQUEST_TRACKER_BUSY__SHIFT 0x16 +#define GL1XC_STATUS__BUFFER_FULL__SHIFT 0x17 +#define GL1XC_STATUS__INPUT_BUFFER_VC0_FIFO_FULL_MASK 0x00000001L +#define GL1XC_STATUS__OUTPUT_FIFOS_BUSY_MASK 0x00000002L +#define GL1XC_STATUS__GL2_REQ_VC0_STALL_MASK 0x00000008L +#define GL1XC_STATUS__GL2_DATA_VC0_STALL_MASK 0x00000010L +#define GL1XC_STATUS__GL2_REQ_VC1_STALL_MASK 0x00000020L +#define GL1XC_STATUS__GL2_DATA_VC1_STALL_MASK 0x00000040L +#define GL1XC_STATUS__INPUT_BUFFER_VC0_BUSY_MASK 0x00000080L +#define GL1XC_STATUS__SRC_DATA_FIFO_VC0_BUSY_MASK 0x00000100L +#define GL1XC_STATUS__GL2_RH_BUSY_MASK 0x00000200L +#define GL1XC_STATUS__NUM_REQ_PENDING_FROM_L2_MASK 0x000FFC00L +#define GL1XC_STATUS__VIRTUAL_FIFO_FULL_STALL_MASK 0x00100000L +#define GL1XC_STATUS__REQUEST_TRACKER_BUFFER_STALL_MASK 0x00200000L +#define GL1XC_STATUS__REQUEST_TRACKER_BUSY_MASK 0x00400000L +#define GL1XC_STATUS__BUFFER_FULL_MASK 0x00800000L +//GL1XC_UTCL0_CNTL1 +#define GL1XC_UTCL0_CNTL1__FORCE_4K_L2_RESP__SHIFT 0x0 +#define GL1XC_UTCL0_CNTL1__GPUVM_64K_DEFAULT__SHIFT 0x1 +#define GL1XC_UTCL0_CNTL1__GPUVM_PERM_MODE__SHIFT 0x2 +#define GL1XC_UTCL0_CNTL1__RESP_MODE__SHIFT 0x3 +#define GL1XC_UTCL0_CNTL1__RESP_FAULT_MODE__SHIFT 0x5 +#define GL1XC_UTCL0_CNTL1__CLIENTID__SHIFT 0x7 +#define GL1XC_UTCL0_CNTL1__REG_INV_VMID__SHIFT 0x13 +#define GL1XC_UTCL0_CNTL1__REG_INV_TOGGLE__SHIFT 0x18 +#define GL1XC_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE__SHIFT 0x19 +#define GL1XC_UTCL0_CNTL1__FORCE_MISS__SHIFT 0x1a +#define GL1XC_UTCL0_CNTL1__FORCE_IN_ORDER__SHIFT 0x1b +#define GL1XC_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define GL1XC_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define GL1XC_UTCL0_CNTL1__FORCE_4K_L2_RESP_MASK 0x00000001L +#define GL1XC_UTCL0_CNTL1__GPUVM_64K_DEFAULT_MASK 0x00000002L +#define GL1XC_UTCL0_CNTL1__GPUVM_PERM_MODE_MASK 0x00000004L +#define GL1XC_UTCL0_CNTL1__RESP_MODE_MASK 0x00000018L +#define GL1XC_UTCL0_CNTL1__RESP_FAULT_MODE_MASK 0x00000060L +#define GL1XC_UTCL0_CNTL1__CLIENTID_MASK 0x0000FF80L +#define GL1XC_UTCL0_CNTL1__REG_INV_VMID_MASK 0x00780000L +#define GL1XC_UTCL0_CNTL1__REG_INV_TOGGLE_MASK 0x01000000L +#define GL1XC_UTCL0_CNTL1__ATOMIC_REQUEST_ENABLE_MASK 0x02000000L +#define GL1XC_UTCL0_CNTL1__FORCE_MISS_MASK 0x04000000L +#define GL1XC_UTCL0_CNTL1__FORCE_IN_ORDER_MASK 0x08000000L +#define GL1XC_UTCL0_CNTL1__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000L +#define GL1XC_UTCL0_CNTL1__REDUCE_CACHE_SIZE_BY_2_MASK 0xC0000000L +//GL1XC_UTCL0_CNTL2 +#define GL1XC_UTCL0_CNTL2__SPARE__SHIFT 0x0 +#define GL1XC_UTCL0_CNTL2__MTYPE_OVRD_DIS__SHIFT 0x9 +#define GL1XC_UTCL0_CNTL2__ANY_LINE_VALID__SHIFT 0xa +#define GL1XC_UTCL0_CNTL2__FORCE_SNOOP__SHIFT 0xe +#define GL1XC_UTCL0_CNTL2__DISABLE_BURST__SHIFT 0x11 +#define GL1XC_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K__SHIFT 0x1a +#define GL1XC_UTCL0_CNTL2__FGCG_DISABLE__SHIFT 0x1e +#define GL1XC_UTCL0_CNTL2__DISABLE_ILLEGAL_PCIE_ATOMIC__SHIFT 0x1f +#define GL1XC_UTCL0_CNTL2__SPARE_MASK 0x000000FFL +#define GL1XC_UTCL0_CNTL2__MTYPE_OVRD_DIS_MASK 0x00000200L +#define GL1XC_UTCL0_CNTL2__ANY_LINE_VALID_MASK 0x00000400L +#define GL1XC_UTCL0_CNTL2__FORCE_SNOOP_MASK 0x00004000L +#define GL1XC_UTCL0_CNTL2__DISABLE_BURST_MASK 0x00020000L +#define GL1XC_UTCL0_CNTL2__FORCE_FRAG_2M_TO_64K_MASK 0x04000000L +#define GL1XC_UTCL0_CNTL2__FGCG_DISABLE_MASK 0x40000000L +#define GL1XC_UTCL0_CNTL2__DISABLE_ILLEGAL_PCIE_ATOMIC_MASK 0x80000000L +//GL1XC_UTCL0_STATUS +#define GL1XC_UTCL0_STATUS__FAULT_DETECTED__SHIFT 0x0 +#define GL1XC_UTCL0_STATUS__RETRY_DETECTED__SHIFT 0x1 +#define GL1XC_UTCL0_STATUS__PRT_DETECTED__SHIFT 0x2 +#define GL1XC_UTCL0_STATUS__FAULT_DETECTED_MASK 0x00000001L +#define GL1XC_UTCL0_STATUS__RETRY_DETECTED_MASK 0x00000002L +#define GL1XC_UTCL0_STATUS__PRT_DETECTED_MASK 0x00000004L +//GL1XC_UTCL0_RETRY +#define GL1XC_UTCL0_RETRY__INCR__SHIFT 0x0 +#define GL1XC_UTCL0_RETRY__COUNT__SHIFT 0x8 +#define GL1XC_UTCL0_RETRY__INCR_MASK 0x000000FFL +#define GL1XC_UTCL0_RETRY__COUNT_MASK 0x00000F00L +//GL1XC_CTRL2 +#define GL1XC_CTRL2__UTCL0_INFLIGHT_MAX__SHIFT 0x0 +#define GL1XC_CTRL2__OVERRIDE_READ_BYPASS_TO_DECOMPRESSED__SHIFT 0x8 +#define GL1XC_CTRL2__OVERRIDE_WRITE_BYPASS_TO_COMPRESSION_DISABLE__SHIFT 0x9 +#define GL1XC_CTRL2__UTCL0_INFLIGHT_MAX_MASK 0x000000FFL +#define GL1XC_CTRL2__OVERRIDE_READ_BYPASS_TO_DECOMPRESSED_MASK 0x00000100L +#define GL1XC_CTRL2__OVERRIDE_WRITE_BYPASS_TO_COMPRESSION_DISABLE_MASK 0x00000200L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pfonly_secacdec +//SE_CAC_CTRL_1 +#define SE_CAC_CTRL_1__CAC_WINDOW__SHIFT 0x0 +#define SE_CAC_CTRL_1__TDP_WINDOW__SHIFT 0x8 +#define SE_CAC_CTRL_1__CAC_WINDOW_MASK 0x000000FFL +#define SE_CAC_CTRL_1__TDP_WINDOW_MASK 0xFFFFFF00L +//SE_CAC_CTRL_2 +#define SE_CAC_CTRL_2__CAC_ENABLE__SHIFT 0x0 +#define SE_CAC_CTRL_2__SE_LCAC_ENABLE__SHIFT 0x1 +#define SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE__SHIFT 0x2 +#define SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN__SHIFT 0x3 +#define SE_CAC_CTRL_2__SE_LCAC_OVR_EN__SHIFT 0x4 +#define SE_CAC_CTRL_2__WGP_LCAC_OVR_EN__SHIFT 0x5 +#define SE_CAC_CTRL_2__WGP_LCAC_MODE__SHIFT 0x6 +#define SE_CAC_CTRL_2__SE_CAC_SOFT_CTRL_ENABLE__SHIFT 0x7 +#define SE_CAC_CTRL_2__CAC_ENABLE_MASK 0x00000001L +#define SE_CAC_CTRL_2__SE_LCAC_ENABLE_MASK 0x00000002L +#define SE_CAC_CTRL_2__WGP_CAC_CLK_OVERRIDE_MASK 0x00000004L +#define SE_CAC_CTRL_2__SE_CAC_INDEX_AUTO_INCR_EN_MASK 0x00000008L +#define SE_CAC_CTRL_2__SE_LCAC_OVR_EN_MASK 0x00000010L +#define SE_CAC_CTRL_2__WGP_LCAC_OVR_EN_MASK 0x00000020L +#define SE_CAC_CTRL_2__WGP_LCAC_MODE_MASK 0x00000040L +#define SE_CAC_CTRL_2__SE_CAC_SOFT_CTRL_ENABLE_MASK 0x00000080L +//SE_CAC_SOFT_CTRL +#define SE_CAC_SOFT_CTRL__SE_CAC_SOFT_SNAP__SHIFT 0x0 +#define SE_CAC_SOFT_CTRL__SE_CAC_SOFT_SNAP_MASK 0x00000001L +//SE_CAC_OVR_VAL_LOWER +#define SE_CAC_OVR_VAL_LOWER__SE_LCAC_OVR_VAL_LOWER__SHIFT 0x0 +#define SE_CAC_OVR_VAL_LOWER__SE_LCAC_OVR_VAL_LOWER_MASK 0xFFFFFFFFL +//SE_CAC_OVR_VAL_UPPER +#define SE_CAC_OVR_VAL_UPPER__SE_LCAC_OVR_VAL_UPPER__SHIFT 0x0 +#define SE_CAC_OVR_VAL_UPPER__SE_LCAC_OVR_VAL_UPPER_MASK 0xFFFFFFFFL +//SE_CAC_WINDOW_AGGR_VALUE_LO +#define SE_CAC_WINDOW_AGGR_VALUE_LO__SE_CAC_WINDOW_AGGR_VALUE_LO__SHIFT 0x0 +#define SE_CAC_WINDOW_AGGR_VALUE_LO__SE_CAC_WINDOW_AGGR_VALUE_LO_MASK 0xFFFFFFFFL +//SE_CAC_WINDOW_AGGR_VALUE_HI +#define SE_CAC_WINDOW_AGGR_VALUE_HI__SE_CAC_WINDOW_AGGR_VALUE_HI__SHIFT 0x0 +#define SE_CAC_WINDOW_AGGR_VALUE_HI__SE_CAC_WINDOW_AGGR_VALUE_HI_MASK 0x000000FFL +//SE_CAC_WINDOW_GFXCLK_CYCLE +#define SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE__SHIFT 0x0 +#define SE_CAC_WINDOW_GFXCLK_CYCLE__SE_CAC_WINDOW_GFXCLK_CYCLE_MASK 0x0000FFFFL +//DIDT_EDC_CTRL +#define DIDT_EDC_CTRL__EDC_EN__SHIFT 0x0 +#define DIDT_EDC_CTRL__EDC_SW_RST__SHIFT 0x1 +#define DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT 0x2 +#define DIDT_EDC_CTRL__EDC_FORCE_STALL__SHIFT 0x3 +#define DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT 0x4 +#define DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT 0xa +#define DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT 0xe +#define DIDT_EDC_CTRL__EDC_ALGORITHM_MODE__SHIFT 0xf +#define DIDT_EDC_CTRL__EDC_AVGDIV__SHIFT 0x10 +#define DIDT_EDC_CTRL__EDC_THRESHOLD_SEL__SHIFT 0x14 +#define DIDT_EDC_CTRL__EDC_PERF_COUNTER_EN__SHIFT 0x15 +#define DIDT_EDC_CTRL__EDC_EN_MASK 0x00000001L +#define DIDT_EDC_CTRL__EDC_SW_RST_MASK 0x00000002L +#define DIDT_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK 0x00000004L +#define DIDT_EDC_CTRL__EDC_FORCE_STALL_MASK 0x00000008L +#define DIDT_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK 0x000003F0L +#define DIDT_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK 0x00003C00L +#define DIDT_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK 0x00004000L +#define DIDT_EDC_CTRL__EDC_ALGORITHM_MODE_MASK 0x00008000L +#define DIDT_EDC_CTRL__EDC_AVGDIV_MASK 0x000F0000L +#define DIDT_EDC_CTRL__EDC_THRESHOLD_SEL_MASK 0x00100000L +#define DIDT_EDC_CTRL__EDC_PERF_COUNTER_EN_MASK 0x00200000L +//DIDT_EDC_THROTTLE_CTRL +#define DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN__SHIFT 0x0 +#define DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN__SHIFT 0x1 +#define DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN__SHIFT 0x2 +#define DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN__SHIFT 0x3 +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN__SHIFT 0x4 +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE__SHIFT 0x5 +#define DIDT_EDC_THROTTLE_CTRL__EDC_STRETCH_EN__SHIFT 0x8 +#define DIDT_EDC_THROTTLE_CTRL__EDC_STRETCH_SRC_SEL__SHIFT 0x9 +#define DIDT_EDC_THROTTLE_CTRL__EDC_MAX_HYSTERESIS__SHIFT 0xa +#define DIDT_EDC_THROTTLE_CTRL__EDC_STALL_CLAMP_EN__SHIFT 0x12 +#define DIDT_EDC_THROTTLE_CTRL__SQ_STALL_EN_MASK 0x00000001L +#define DIDT_EDC_THROTTLE_CTRL__DB_STALL_EN_MASK 0x00000002L +#define DIDT_EDC_THROTTLE_CTRL__TCP_STALL_EN_MASK 0x00000004L +#define DIDT_EDC_THROTTLE_CTRL__TD_STALL_EN_MASK 0x00000008L +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_EN_MASK 0x00000010L +#define DIDT_EDC_THROTTLE_CTRL__PATTERN_EXTEND_MODE_MASK 0x000000E0L +#define DIDT_EDC_THROTTLE_CTRL__EDC_STRETCH_EN_MASK 0x00000100L +#define DIDT_EDC_THROTTLE_CTRL__EDC_STRETCH_SRC_SEL_MASK 0x00000200L +#define DIDT_EDC_THROTTLE_CTRL__EDC_MAX_HYSTERESIS_MASK 0x0003FC00L +#define DIDT_EDC_THROTTLE_CTRL__EDC_STALL_CLAMP_EN_MASK 0x00040000L +//DIDT_EDC_THRESHOLD +#define DIDT_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT 0x0 +#define DIDT_EDC_THRESHOLD__EDC_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_EDC_STRETCH_THRESHOLD +#define DIDT_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD__SHIFT 0x0 +#define DIDT_EDC_STRETCH_THRESHOLD__EDC_STRETCH_THRESHOLD_MASK 0xFFFFFFFFL +//DIDT_EDC_CLK_COUNTER_THRESHOLD +#define DIDT_EDC_CLK_COUNTER_THRESHOLD__EDC_CLK_COUNTER_THRESHOLD__SHIFT 0x0 +#define DIDT_EDC_CLK_COUNTER_THRESHOLD__EDC_CLK_COUNTER_THRESHOLD_MASK 0x0000FFFFL +//DIDT_EDC_STALL_PATTERN_1_2 +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT 0x10 +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK 0x00007FFFL +#define DIDT_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK 0x7FFF0000L +//DIDT_EDC_STALL_PATTERN_3_4 +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT 0x10 +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK 0x00007FFFL +#define DIDT_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK 0x7FFF0000L +//DIDT_EDC_STALL_PATTERN_5_6 +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT 0x10 +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK 0x00007FFFL +#define DIDT_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK 0x7FFF0000L +//DIDT_EDC_STALL_PATTERN_7 +#define DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT 0x0 +#define DIDT_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK 0x00007FFFL +//DIDT_EDC_STATUS +#define DIDT_EDC_STATUS__EDC_FSM_STATE__SHIFT 0x0 +#define DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL__SHIFT 0x1 +#define DIDT_EDC_STATUS__EDC_HYSTERESIS_CNT__SHIFT 0x4 +#define DIDT_EDC_STATUS__EDC_THRESHOLD_STAT__SHIFT 0xc +#define DIDT_EDC_STATUS__EDC_FSM_STATE_MASK 0x00000001L +#define DIDT_EDC_STATUS__EDC_THROTTLE_LEVEL_MASK 0x0000000EL +#define DIDT_EDC_STATUS__EDC_HYSTERESIS_CNT_MASK 0x00000FF0L +#define DIDT_EDC_STATUS__EDC_THRESHOLD_STAT_MASK 0x00001000L +//DIDT_EDC_OVERFLOW +#define DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW__SHIFT 0x0 +#define DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER__SHIFT 0x1 +#define DIDT_EDC_OVERFLOW__EDC_ROLLING_POWER_DELTA_OVERFLOW_MASK 0x00000001L +#define DIDT_EDC_OVERFLOW__EDC_THROTTLE_LEVEL_OVERFLOW_COUNTER_MASK 0x0001FFFEL +//DIDT_EDC_ROLLING_POWER_DELTA +#define DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA__SHIFT 0x0 +#define DIDT_EDC_ROLLING_POWER_DELTA__EDC_ROLLING_POWER_DELTA_MASK 0xFFFFFFFFL +//DIDT_EDC_AVG_POWER_DELTA_HI +#define DIDT_EDC_AVG_POWER_DELTA_HI__EDC_AVG_POWER_DELTA_HI__SHIFT 0x0 +#define DIDT_EDC_AVG_POWER_DELTA_HI__EDC_AVG_POWER_DELTA_HI_MASK 0xFFFFFFFFL +//DIDT_EDC_AVG_POWER_DELTA_LO +#define DIDT_EDC_AVG_POWER_DELTA_LO__EDC_AVG_POWER_DELTA_LO__SHIFT 0x0 +#define DIDT_EDC_AVG_POWER_DELTA_LO__EDC_AVG_POWER_DELTA_LO_MASK 0xFFFFFFFFL +//DIDT_EDC_STALL_PERF_COUNTER +#define DIDT_EDC_STALL_PERF_COUNTER__EDC_STALL_PERF_COUNTER__SHIFT 0x0 +#define DIDT_EDC_STALL_PERF_COUNTER__EDC_STALL_PERF_COUNTER_MASK 0xFFFFFFFFL +//DIDT_THRESHOLD +#define DIDT_THRESHOLD__DIDT_THRESHOLD__SHIFT 0x0 +#define DIDT_THRESHOLD__DIDT_THRESHOLD_MASK 0xFFFFFFFFL +//SE_CAC_WEIGHT_LDS1_0 +#define SE_CAC_WEIGHT_LDS1_0__WEIGHT_LDS1_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS1_0__WEIGHT_LDS1_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS1_0__WEIGHT_LDS1_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS1_0__WEIGHT_LDS1_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS1_1 +#define SE_CAC_WEIGHT_LDS1_1__WEIGHT_LDS1_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS1_1__WEIGHT_LDS1_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS1_1__WEIGHT_LDS1_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS1_1__WEIGHT_LDS1_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS1_2 +#define SE_CAC_WEIGHT_LDS1_2__WEIGHT_LDS1_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS1_2__WEIGHT_LDS1_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS1_2__WEIGHT_LDS1_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS1_2__WEIGHT_LDS1_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS1_3 +#define SE_CAC_WEIGHT_LDS1_3__WEIGHT_LDS1_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS1_3__WEIGHT_LDS1_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS1_3__WEIGHT_LDS1_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS1_3__WEIGHT_LDS1_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_0 +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_0__WEIGHT_TCP_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_1 +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_1__WEIGHT_TCP_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_2 +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_2__WEIGHT_TCP_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_3 +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_3__WEIGHT_TCP_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQ_0 +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SQ_0__WEIGHT_SQ_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQ_1 +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SQ_1__WEIGHT_SQ_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQ_2 +#define SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQ_2__WEIGHT_SQ_SIG4_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_SP_0 +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SP_0__WEIGHT_SP_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SP_1 +#define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SP_1__WEIGHT_SP_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SP_2 +#define SE_CAC_WEIGHT_SP_2__WEIGHT_SP_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_SP_2__WEIGHT_SP_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_SP_2__WEIGHT_SP_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SP_2__WEIGHT_SP_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS0_0 +#define SE_CAC_WEIGHT_LDS0_0__WEIGHT_LDS0_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS0_0__WEIGHT_LDS0_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS0_0__WEIGHT_LDS0_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS0_0__WEIGHT_LDS0_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS0_1 +#define SE_CAC_WEIGHT_LDS0_1__WEIGHT_LDS0_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS0_1__WEIGHT_LDS0_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS0_1__WEIGHT_LDS0_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS0_1__WEIGHT_LDS0_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS0_2 +#define SE_CAC_WEIGHT_LDS0_2__WEIGHT_LDS0_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS0_2__WEIGHT_LDS0_SIG5__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS0_2__WEIGHT_LDS0_SIG4_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS0_2__WEIGHT_LDS0_SIG5_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_LDS0_3 +#define SE_CAC_WEIGHT_LDS0_3__WEIGHT_LDS0_SIG6__SHIFT 0x0 +#define SE_CAC_WEIGHT_LDS0_3__WEIGHT_LDS0_SIG7__SHIFT 0x10 +#define SE_CAC_WEIGHT_LDS0_3__WEIGHT_LDS0_SIG6_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_LDS0_3__WEIGHT_LDS0_SIG7_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQC_0 +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SQC_0__WEIGHT_SQC_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SQC_1 +#define SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SQC_1__WEIGHT_SQC_SIG2_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_CU_0 +#define SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_CU_0__WEIGHT_CU_SIG0_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_UTCL1_0 +#define SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_UTCL1_0__WEIGHT_UTCL1_SIG0_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_GL1C_0 +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_GL1C_0__WEIGHT_GL1C_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_GL1C_1 +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_GL1C_1__WEIGHT_GL1C_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SPI_0 +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0__SHIFT 0x0 +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1__SHIFT 0x10 +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG0_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SPI_0__WEIGHT_SPI_SIG1_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SPI_1 +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2__SHIFT 0x0 +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3__SHIFT 0x10 +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG2_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_SPI_1__WEIGHT_SPI_SIG3_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_SPI_2 +#define SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4__SHIFT 0x0 +#define SE_CAC_WEIGHT_SPI_2__WEIGHT_SPI_SIG4_MASK 0x0000FFFFL +//SE_CAC_WEIGHT_TCP_4 +#define SE_CAC_WEIGHT_TCP_4__WEIGHT_TCP_SIG8__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_4__WEIGHT_TCP_SIG9__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_4__WEIGHT_TCP_SIG8_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_4__WEIGHT_TCP_SIG9_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_5 +#define SE_CAC_WEIGHT_TCP_5__WEIGHT_TCP_SIG10__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_5__WEIGHT_TCP_SIG11__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_5__WEIGHT_TCP_SIG10_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_5__WEIGHT_TCP_SIG11_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_6 +#define SE_CAC_WEIGHT_TCP_6__WEIGHT_TCP_SIG12__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_6__WEIGHT_TCP_SIG13__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_6__WEIGHT_TCP_SIG12_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_6__WEIGHT_TCP_SIG13_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_7 +#define SE_CAC_WEIGHT_TCP_7__WEIGHT_TCP_SIG14__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_7__WEIGHT_TCP_SIG15__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_7__WEIGHT_TCP_SIG14_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_7__WEIGHT_TCP_SIG15_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_8 +#define SE_CAC_WEIGHT_TCP_8__WEIGHT_TCP_SIG16__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_8__WEIGHT_TCP_SIG17__SHIFT 0x10 +#define SE_CAC_WEIGHT_TCP_8__WEIGHT_TCP_SIG16_MASK 0x0000FFFFL +#define SE_CAC_WEIGHT_TCP_8__WEIGHT_TCP_SIG17_MASK 0xFFFF0000L +//SE_CAC_WEIGHT_TCP_9 +#define SE_CAC_WEIGHT_TCP_9__WEIGHT_TCP_SIG18__SHIFT 0x0 +#define SE_CAC_WEIGHT_TCP_9__WEIGHT_TCP_SIG18_MASK 0x0000FFFFL +//SE_CAC_IND_INDEX +#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR__SHIFT 0x0 +#define SE_CAC_IND_INDEX__SE_CAC_IND_ADDR_MASK 0xFFFFFFFFL +//SE_CAC_IND_DATA +#define SE_CAC_IND_DATA__SE_CAC_IND_DATA__SHIFT 0x0 +#define SE_CAC_IND_DATA__SE_CAC_IND_DATA_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_perfddec +//GE2_SE_PERFCOUNTER0_LO +#define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER0_HI +#define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER1_LO +#define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER1_HI +#define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER2_LO +#define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER2_HI +#define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER3_LO +#define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GE2_SE_PERFCOUNTER3_HI +#define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBMH_PERFCOUNTER0_LO +#define GRBMH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBMH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBMH_PERFCOUNTER0_HI +#define GRBMH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBMH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GRBMH_PERFCOUNTER1_LO +#define GRBMH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBMH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GRBMH_PERFCOUNTER1_HI +#define GRBMH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBMH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_LO +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER0_HI +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER1_LO +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER1_HI +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER2_LO +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER2_HI +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER3_LO +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SU_PERFCOUNTER3_HI +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER0_LO +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER0_HI +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_LO +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER1_HI +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_LO +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER2_HI +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_LO +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER3_HI +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_LO +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER4_HI +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_LO +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER5_HI +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_LO +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER6_HI +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_LO +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_SC_PERFCOUNTER7_HI +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_HI +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER0_LO +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_HI +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER1_LO +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_HI +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER2_LO +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_HI +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER3_LO +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_HI +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER4_LO +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_HI +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SPI_PERFCOUNTER5_LO +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER0_HI +#define PC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER0_LO +#define PC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER1_HI +#define PC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER1_LO +#define PC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER2_HI +#define PC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER2_LO +#define PC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER3_HI +#define PC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PC_PERFCOUNTER3_LO +#define PC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER0_LO +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER1_LO +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER2_LO +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER3_LO +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER4_LO +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER5_LO +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER6_LO +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQ_PERFCOUNTER7_LO +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER0_LO +#define SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER0_HI +#define SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER1_LO +#define SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER1_HI +#define SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER2_LO +#define SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER2_HI +#define SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER3_LO +#define SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER3_HI +#define SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER4_LO +#define SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER4_HI +#define SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER5_LO +#define SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER5_HI +#define SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER6_LO +#define SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER6_HI +#define SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER7_LO +#define SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQG_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SQG_PERFCOUNTER7_HI +#define SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQG_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_LO +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER0_HI +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_LO +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER1_HI +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_LO +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER2_HI +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_LO +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//SX_PERFCOUNTER3_HI +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_LO +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER0_HI +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_LO +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TA_PERFCOUNTER1_HI +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_LO +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER0_HI +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_LO +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TD_PERFCOUNTER1_HI +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_LO +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER0_HI +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_LO +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER1_HI +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_LO +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER2_HI +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_LO +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER3_HI +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER4_LO +#define TCP_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER4_HI +#define TCP_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER5_LO +#define TCP_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER5_HI +#define TCP_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER6_LO +#define TCP_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER6_HI +#define TCP_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER7_LO +#define TCP_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER7_HI +#define TCP_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//TCP_PERFCOUNTER_FILTER +#define TCP_PERFCOUNTER_FILTER__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE__SHIFT 0xc +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT__SHIFT 0xd +#define TCP_PERFCOUNTER_FILTER__SW_MODE__SHIFT 0x11 +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES__SHIFT 0x16 +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE__SHIFT 0x18 +#define TCP_PERFCOUNTER_FILTER__TMPRL__SHIFT 0x1b +#define TCP_PERFCOUNTER_FILTER__SCOPE__SHIFT 0x1e +#define TCP_PERFCOUNTER_FILTER__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER__DIM_MASK 0x0000001CL +#define TCP_PERFCOUNTER_FILTER__DATA_FORMAT_MASK 0x00000FE0L +#define TCP_PERFCOUNTER_FILTER__COMPRESSION_ENABLE_MASK 0x00001000L +#define TCP_PERFCOUNTER_FILTER__NUM_FORMAT_MASK 0x0001E000L +#define TCP_PERFCOUNTER_FILTER__SW_MODE_MASK 0x003E0000L +#define TCP_PERFCOUNTER_FILTER__NUM_SAMPLES_MASK 0x00C00000L +#define TCP_PERFCOUNTER_FILTER__OPCODE_TYPE_MASK 0x07000000L +#define TCP_PERFCOUNTER_FILTER__TMPRL_MASK 0x38000000L +#define TCP_PERFCOUNTER_FILTER__SCOPE_MASK 0xC0000000L +//TCP_PERFCOUNTER_FILTER2 +#define TCP_PERFCOUNTER_FILTER2__REQ_MODE__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER2__REQ_MODE_MASK 0x0000000FL +//TCP_PERFCOUNTER_FILTER_EN +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER__SHIFT 0x0 +#define TCP_PERFCOUNTER_FILTER_EN__FLAT__SHIFT 0x1 +#define TCP_PERFCOUNTER_FILTER_EN__DIM__SHIFT 0x2 +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT__SHIFT 0x3 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT__SHIFT 0x4 +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE__SHIFT 0x5 +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES__SHIFT 0x6 +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE__SHIFT 0x7 +#define TCP_PERFCOUNTER_FILTER_EN__TMPRL__SHIFT 0x8 +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE__SHIFT 0xb +#define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE__SHIFT 0xc +#define TCP_PERFCOUNTER_FILTER_EN__SCOPE__SHIFT 0xd +#define TCP_PERFCOUNTER_FILTER_EN__BUFFER_MASK 0x00000001L +#define TCP_PERFCOUNTER_FILTER_EN__FLAT_MASK 0x00000002L +#define TCP_PERFCOUNTER_FILTER_EN__DIM_MASK 0x00000004L +#define TCP_PERFCOUNTER_FILTER_EN__DATA_FORMAT_MASK 0x00000008L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_FORMAT_MASK 0x00000010L +#define TCP_PERFCOUNTER_FILTER_EN__SW_MODE_MASK 0x00000020L +#define TCP_PERFCOUNTER_FILTER_EN__NUM_SAMPLES_MASK 0x00000040L +#define TCP_PERFCOUNTER_FILTER_EN__OPCODE_TYPE_MASK 0x00000080L +#define TCP_PERFCOUNTER_FILTER_EN__TMPRL_MASK 0x00000100L +#define TCP_PERFCOUNTER_FILTER_EN__COMPRESSION_ENABLE_MASK 0x00000800L +#define TCP_PERFCOUNTER_FILTER_EN__REQ_MODE_MASK 0x00001000L +#define TCP_PERFCOUNTER_FILTER_EN__SCOPE_MASK 0x00002000L +//TCP_PERFCOUNTER_SET_DEFINE +#define TCP_PERFCOUNTER_SET_DEFINE__SET_A__SHIFT 0x0 +#define TCP_PERFCOUNTER_SET_DEFINE__SET_B__SHIFT 0x8 +#define TCP_PERFCOUNTER_SET_DEFINE__SET_C__SHIFT 0x10 +#define TCP_PERFCOUNTER_SET_DEFINE__SET_D__SHIFT 0x18 +#define TCP_PERFCOUNTER_SET_DEFINE__SET_A_MASK 0x000000FFL +#define TCP_PERFCOUNTER_SET_DEFINE__SET_B_MASK 0x0000FF00L +#define TCP_PERFCOUNTER_SET_DEFINE__SET_C_MASK 0x00FF0000L +#define TCP_PERFCOUNTER_SET_DEFINE__SET_D_MASK 0xFF000000L +//GL1C_PERFCOUNTER0_LO +#define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER0_HI +#define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER1_LO +#define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER1_HI +#define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER2_LO +#define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER2_HI +#define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER3_LO +#define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1C_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1C_PERFCOUNTER3_HI +#define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1C_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER0_LO +#define GL1XC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER0_HI +#define GL1XC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER1_LO +#define GL1XC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER1_HI +#define GL1XC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER2_LO +#define GL1XC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER2_HI +#define GL1XC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER3_LO +#define GL1XC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XC_PERFCOUNTER3_HI +#define GL1XC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_LO +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER0_HI +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_LO +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER1_HI +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_LO +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER2_HI +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_LO +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//CB_PERFCOUNTER3_HI +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_LO +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER0_HI +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_LO +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER1_HI +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_LO +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER2_HI +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_LO +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//DB_PERFCOUNTER3_HI +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_LO +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER0_HI +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_LO +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER1_HI +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_LO +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER2_HI +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_LO +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RMI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//RMI_PERFCOUNTER3_HI +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RMI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER0_LO +#define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER0_HI +#define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER1_LO +#define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER1_HI +#define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER2_LO +#define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER2_HI +#define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER3_LO +#define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER3_HI +#define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER4_LO +#define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER4_HI +#define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER5_LO +#define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER5_HI +#define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER6_LO +#define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER6_HI +#define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER7_LO +#define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_PH_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//PA_PH_PERFCOUNTER7_HI +#define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_PH_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER0_LO +#define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER0_HI +#define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER1_LO +#define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER1_HI +#define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER2_LO +#define UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER2_HI +#define UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER3_LO +#define UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define UTCL1_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//UTCL1_PERFCOUNTER3_HI +#define UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define UTCL1_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WGS_PERFCOUNTER1_LO +#define WGS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WGS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WGS_PERFCOUNTER1_HI +#define WGS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WGS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WGS_PERFCOUNTER0_LO +#define WGS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WGS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//WGS_PERFCOUNTER0_HI +#define WGS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WGS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//WGS_PERFMON_CNTL +#define WGS_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define WGS_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define WGS_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define WGS_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define WGS_PERFMON_CNTL__PERFMON_STATE_MASK 0x0000000FL +#define WGS_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0x000000F0L +#define WGS_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x00000300L +#define WGS_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x00000400L +//GL1A_PERFCOUNTER0_LO +#define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER0_HI +#define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER1_LO +#define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER1_HI +#define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER2_LO +#define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER2_HI +#define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER3_LO +#define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1A_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1A_PERFCOUNTER3_HI +#define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1A_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER0_LO +#define GL1XA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER0_HI +#define GL1XA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER1_LO +#define GL1XA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER1_HI +#define GL1XA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER2_LO +#define GL1XA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER2_HI +#define GL1XA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER3_LO +#define GL1XA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GL1XA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xFFFFFFFFL +//GL1XA_PERFCOUNTER3_HI +#define GL1XA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GL1XA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_perfsdec +//GE2_SE_PERFCOUNTER0_SELECT +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER0_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER0_SELECT1 +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER1_SELECT +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER1_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER1_SELECT1 +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER2_SELECT +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER2_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER2_SELECT1 +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER3_SELECT +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL0_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER3_SELECT__PERF_MODE0_MASK 0xF0000000L +//GE2_SE_PERFCOUNTER3_SELECT1 +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GE2_SE_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GRBMH_PERFCOUNTER0_SELECT +#define GRBMH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBMH_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBMH_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x7 +#define GRBMH_PERFCOUNTER0_SELECT__SQG_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBMH_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBMH_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xa +#define GRBMH_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBMH_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xc +#define GRBMH_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBMH_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBMH_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBMH_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBMH_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBMH_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBMH_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBMH_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBMH_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBMH_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBMH_PERFCOUNTER0_SELECT__GL1A_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBMH_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBMH_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBMH_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBMH_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBMH_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBMH_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBMH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBMH_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBMH_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000080L +#define GRBMH_PERFCOUNTER0_SELECT__SQG_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBMH_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBMH_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBMH_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBMH_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBMH_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBMH_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBMH_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBMH_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBMH_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBMH_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBMH_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBMH_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBMH_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBMH_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBMH_PERFCOUNTER0_SELECT__GL1A_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBMH_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBMH_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBMH_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBMH_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBMH_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBMH_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//GRBMH_PERFCOUNTER1_SELECT +#define GRBMH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBMH_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT 0x6 +#define GRBMH_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT 0x7 +#define GRBMH_PERFCOUNTER1_SELECT__SQG_BUSY_USER_DEFINED_MASK__SHIFT 0x8 +#define GRBMH_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT 0x9 +#define GRBMH_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT 0xa +#define GRBMH_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBMH_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xc +#define GRBMH_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBMH_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBMH_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBMH_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBMH_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBMH_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBMH_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBMH_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBMH_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBMH_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBMH_PERFCOUNTER1_SELECT__GL1A_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBMH_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBMH_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBMH_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBMH_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBMH_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT 0x1d +#define GRBMH_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT 0x1e +#define GRBMH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x0000003FL +#define GRBMH_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK 0x00000040L +#define GRBMH_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK 0x00000080L +#define GRBMH_PERFCOUNTER1_SELECT__SQG_BUSY_USER_DEFINED_MASK_MASK 0x00000100L +#define GRBMH_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK 0x00000200L +#define GRBMH_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK 0x00000400L +#define GRBMH_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x00000800L +#define GRBMH_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x00001000L +#define GRBMH_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x00002000L +#define GRBMH_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x00004000L +#define GRBMH_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK 0x00008000L +#define GRBMH_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x00010000L +#define GRBMH_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x00020000L +#define GRBMH_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x00040000L +#define GRBMH_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK 0x00080000L +#define GRBMH_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x00100000L +#define GRBMH_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x00200000L +#define GRBMH_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK 0x00800000L +#define GRBMH_PERFCOUNTER1_SELECT__GL1A_BUSY_USER_DEFINED_MASK_MASK 0x01000000L +#define GRBMH_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x02000000L +#define GRBMH_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x04000000L +#define GRBMH_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK 0x08000000L +#define GRBMH_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK 0x10000000L +#define GRBMH_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK 0x20000000L +#define GRBMH_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK 0x40000000L +//PA_SU_PERFCOUNTER0_SELECT +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER0_SELECT1 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER1_SELECT +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER1_SELECT1 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER2_SELECT +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER2_SELECT1 +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SU_PERFCOUNTER3_SELECT +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SU_PERFCOUNTER3_SELECT1 +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SU_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SC_PERFCOUNTER0_SELECT +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_SC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_SC_PERFCOUNTER0_SELECT1 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_SC_PERFCOUNTER1_SELECT +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER2_SELECT +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER3_SELECT +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER4_SELECT +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER5_SELECT +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER6_SELECT +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_SC_PERFCOUNTER7_SELECT +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +//SPI_PERFCOUNTER0_SELECT +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER4_SELECT +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER4_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER4_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER4_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER4_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER5_SELECT +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER5_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER5_SELECT__PERF_MODE1__SHIFT 0x18 +#define SPI_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SPI_PERFCOUNTER5_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SPI_PERFCOUNTER5_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SPI_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//SPI_PERFCOUNTER0_SELECT1 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER1_SELECT1 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER2_SELECT1 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER3_SELECT1 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER4_SELECT1 +#define SPI_PERFCOUNTER4_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER4_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER4_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER4_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER4_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER4_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER4_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER4_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER5_SELECT1 +#define SPI_PERFCOUNTER5_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER5_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER5_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SPI_PERFCOUNTER5_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SPI_PERFCOUNTER5_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SPI_PERFCOUNTER5_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SPI_PERFCOUNTER5_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SPI_PERFCOUNTER5_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SPI_PERFCOUNTER_BINS +#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc +#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c +#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0x0000000FL +#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0x000000F0L +#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0x00000F00L +#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000F000L +#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0x000F0000L +#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0x00F00000L +#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0x0F000000L +#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xF0000000L +//PC_PERFCOUNTER0_SELECT +#define PC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER1_SELECT +#define PC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER2_SELECT +#define PC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER3_SELECT +#define PC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define PC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define PC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define PC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//PC_PERFCOUNTER0_SELECT1 +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PC_PERFCOUNTER1_SELECT1 +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PC_PERFCOUNTER2_SELECT1 +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PC_PERFCOUNTER3_SELECT1 +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SQ_PERFCOUNTER0_SELECT +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER1_SELECT +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER2_SELECT +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER3_SELECT +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER4_SELECT +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER5_SELECT +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER6_SELECT +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER7_SELECT +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER8_SELECT +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER9_SELECT +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER10_SELECT +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER11_SELECT +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER12_SELECT +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER13_SELECT +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER14_SELECT +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xF0000000L +//SQ_PERFCOUNTER15_SELECT +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x000003FFL +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER0_SELECT +#define SQG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER1_SELECT +#define SQG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER2_SELECT +#define SQG_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER3_SELECT +#define SQG_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER4_SELECT +#define SQG_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER5_SELECT +#define SQG_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER6_SELECT +#define SQG_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER7_SELECT +#define SQG_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQG_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQG_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQG_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000001FFL +#define SQG_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0x00F00000L +#define SQG_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L +//SQG_PERFCOUNTER_CTRL +#define SQG_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQG_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQG_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQG_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT 0xe +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT 0xf +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT 0x10 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT 0x11 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT 0x12 +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT 0x13 +#define SQG_PERFCOUNTER_CTRL__POLL_BEFORE_PERF_READ__SHIFT 0x1f +#define SQG_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L +#define SQG_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L +#define SQG_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L +#define SQG_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK 0x00004000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK 0x00008000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK 0x00010000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK 0x00020000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK 0x00040000L +#define SQG_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK 0x00080000L +#define SQG_PERFCOUNTER_CTRL__POLL_BEFORE_PERF_READ_MASK 0x80000000L +//SQG_PERFCOUNTER_CTRL2 +#define SQG_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define SQG_PERFCOUNTER_CTRL2__VMID_EN__SHIFT 0x1 +#define SQG_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L +#define SQG_PERFCOUNTER_CTRL2__VMID_EN_MASK 0x0001FFFEL +//SQG_PERF_SAMPLE_FINISH +#define SQG_PERF_SAMPLE_FINISH__STATUS__SHIFT 0x0 +#define SQG_PERF_SAMPLE_FINISH__STATUS_MASK 0x0000007FL +//SQ_PERFCOUNTER_CTRL +#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF__SHIFT 0xe +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF__SHIFT 0xf +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF__SHIFT 0x10 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF__SHIFT 0x11 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF__SHIFT 0x12 +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF__SHIFT 0x13 +#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x00000004L +#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x00000010L +#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x00000040L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE0_PERF_MASK 0x00004000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME0PIPE1_PERF_MASK 0x00008000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE0_PERF_MASK 0x00010000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE1_PERF_MASK 0x00020000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE2_PERF_MASK 0x00040000L +#define SQ_PERFCOUNTER_CTRL__DISABLE_ME1PIPE3_PERF_MASK 0x00080000L +//SQ_PERFCOUNTER_CTRL2 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL2__VMID_EN__SHIFT 0x1 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x00000001L +#define SQ_PERFCOUNTER_CTRL2__VMID_EN_MASK 0x0001FFFEL +//SQ_THREAD_TRACE_BUF0_SIZE +#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF0_SIZE__SIZE_MASK 0x003FFFFFL +//SQ_THREAD_TRACE_BUF0_BASE_LO +#define SQ_THREAD_TRACE_BUF0_BASE_LO__BASE_LO__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF0_BASE_LO__BASE_LO_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_BUF0_BASE_HI +#define SQ_THREAD_TRACE_BUF0_BASE_HI__BASE_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF0_BASE_HI__BASE_HI_MASK 0x00001FFFL +//SQ_THREAD_TRACE_BUF1_SIZE +#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF1_SIZE__SIZE_MASK 0x003FFFFFL +//SQ_THREAD_TRACE_BUF1_BASE_LO +#define SQ_THREAD_TRACE_BUF1_BASE_LO__BASE_LO__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF1_BASE_LO__BASE_LO_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_BUF1_BASE_HI +#define SQ_THREAD_TRACE_BUF1_BASE_HI__BASE_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_BUF1_BASE_HI__BASE_HI_MASK 0x00001FFFL +//SQ_THREAD_TRACE_CTRL +#define SQ_THREAD_TRACE_CTRL__MODE__SHIFT 0x0 +#define SQ_THREAD_TRACE_CTRL__GL1_PERF_EN__SHIFT 0x3 +#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN__SHIFT 0x4 +#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER__SHIFT 0x5 +#define SQ_THREAD_TRACE_CTRL__HIWATER__SHIFT 0x6 +#define SQ_THREAD_TRACE_CTRL__REG_AT_HWM__SHIFT 0x9 +#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN__SHIFT 0xb +#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN__SHIFT 0xc +#define SQ_THREAD_TRACE_CTRL__STALL_ALL_SIMDS__SHIFT 0xd +#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER__SHIFT 0xe +#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE__SHIFT 0xf +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS__SHIFT 0x12 +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS__SHIFT 0x13 +#define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET__SHIFT 0x14 +#define SQ_THREAD_TRACE_CTRL__GL1X_PREFETCH_PAGE__SHIFT 0x17 +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS__SHIFT 0x1c +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE__SHIFT 0x1d +#define SQ_THREAD_TRACE_CTRL__NCP_REG_TOKEN_EN__SHIFT 0x1e +#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN__SHIFT 0x1f +#define SQ_THREAD_TRACE_CTRL__MODE_MASK 0x00000003L +#define SQ_THREAD_TRACE_CTRL__GL1_PERF_EN_MASK 0x00000008L +#define SQ_THREAD_TRACE_CTRL__INTERRUPT_EN_MASK 0x00000010L +#define SQ_THREAD_TRACE_CTRL__DOUBLE_BUFFER_MASK 0x00000020L +#define SQ_THREAD_TRACE_CTRL__HIWATER_MASK 0x000001C0L +#define SQ_THREAD_TRACE_CTRL__REG_AT_HWM_MASK 0x00000600L +#define SQ_THREAD_TRACE_CTRL__SPI_STALL_EN_MASK 0x00000800L +#define SQ_THREAD_TRACE_CTRL__SQ_STALL_EN_MASK 0x00001000L +#define SQ_THREAD_TRACE_CTRL__STALL_ALL_SIMDS_MASK 0x00002000L +#define SQ_THREAD_TRACE_CTRL__UTIL_TIMER_MASK 0x00004000L +#define SQ_THREAD_TRACE_CTRL__WAVESTART_MODE_MASK 0x00018000L +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_MARKERS_MASK 0x00040000L +#define SQ_THREAD_TRACE_CTRL__SYNC_COUNT_DRAWS_MASK 0x00080000L +#define SQ_THREAD_TRACE_CTRL__LOWATER_OFFSET_MASK 0x00700000L +#define SQ_THREAD_TRACE_CTRL__GL1X_PREFETCH_PAGE_MASK 0x07800000L +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_PADDING_DIS_MASK 0x10000000L +#define SQ_THREAD_TRACE_CTRL__AUTO_FLUSH_MODE_MASK 0x20000000L +#define SQ_THREAD_TRACE_CTRL__NCP_REG_TOKEN_EN_MASK 0x40000000L +#define SQ_THREAD_TRACE_CTRL__DRAW_EVENT_EN_MASK 0x80000000L +//SQ_THREAD_TRACE_MASK +#define SQ_THREAD_TRACE_MASK__SIMD_SEL__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__WGP_SEL__SHIFT 0x4 +#define SQ_THREAD_TRACE_MASK__SA_SEL__SHIFT 0x9 +#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE__SHIFT 0xa +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA__SHIFT 0x11 +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_WAVESTART_EXT__SHIFT 0x12 +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_ALLOC__SHIFT 0x13 +#define SQ_THREAD_TRACE_MASK__SIMD_POWER__SHIFT 0x14 +#define SQ_THREAD_TRACE_MASK__SIMD_POWER_FREQ__SHIFT 0x15 +#define SQ_THREAD_TRACE_MASK__SIMD_SEL_MASK 0x00000003L +#define SQ_THREAD_TRACE_MASK__WGP_SEL_MASK 0x000000F0L +#define SQ_THREAD_TRACE_MASK__SA_SEL_MASK 0x00000200L +#define SQ_THREAD_TRACE_MASK__WTYPE_INCLUDE_MASK 0x0001FC00L +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_SHADERDATA_MASK 0x00020000L +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_WAVESTART_EXT_MASK 0x00040000L +#define SQ_THREAD_TRACE_MASK__EXCLUDE_NONDETAIL_ALLOC_MASK 0x00080000L +#define SQ_THREAD_TRACE_MASK__SIMD_POWER_MASK 0x00100000L +#define SQ_THREAD_TRACE_MASK__SIMD_POWER_FREQ_MASK 0x00200000L +//SQ_THREAD_TRACE_TOKEN_MASK +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC__SHIFT 0xc +#define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE__SHIFT 0xd +#define SQ_THREAD_TRACE_TOKEN_MASK__EXCLUDE_BARRIER_WAIT__SHIFT 0xe +#define SQ_THREAD_TRACE_TOKEN_MASK__EXCLUDE_ALUEXEC5__SHIFT 0xf +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE__SHIFT 0x10 +#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE__SHIFT 0x18 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE__SHIFT 0x1a +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL__SHIFT 0x1f +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_EXCLUDE_MASK 0x00000FFFL +#define SQ_THREAD_TRACE_TOKEN_MASK__TTRACE_EXEC_MASK 0x00001000L +#define SQ_THREAD_TRACE_TOKEN_MASK__BOP_EVENTS_TOKEN_INCLUDE_MASK 0x00002000L +#define SQ_THREAD_TRACE_TOKEN_MASK__EXCLUDE_BARRIER_WAIT_MASK 0x00004000L +#define SQ_THREAD_TRACE_TOKEN_MASK__EXCLUDE_ALUEXEC5_MASK 0x00008000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_INCLUDE_MASK 0x00FF0000L +#define SQ_THREAD_TRACE_TOKEN_MASK__INST_EXCLUDE_MASK 0x03000000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_EXCLUDE_MASK 0x1C000000L +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DETAIL_ALL_MASK 0x80000000L +//SQ_THREAD_TRACE_WPTR +#define SQ_THREAD_TRACE_WPTR__OFFSET__SHIFT 0x0 +#define SQ_THREAD_TRACE_WPTR__BUFFER_ID__SHIFT 0x1f +#define SQ_THREAD_TRACE_WPTR__OFFSET_MASK 0x1FFFFFFFL +#define SQ_THREAD_TRACE_WPTR__BUFFER_ID_MASK 0x80000000L +//SQ_THREAD_TRACE_HALT +#define SQ_THREAD_TRACE_HALT__ENTER_CGCG__SHIFT 0x0 +#define SQ_THREAD_TRACE_HALT__CGCG_READY__SHIFT 0x1 +#define SQ_THREAD_TRACE_HALT__ENTER_POWEROFF__SHIFT 0x2 +#define SQ_THREAD_TRACE_HALT__POWEROFF_READY__SHIFT 0x3 +#define SQ_THREAD_TRACE_HALT__ENTER_CGCG_MASK 0x00000001L +#define SQ_THREAD_TRACE_HALT__CGCG_READY_MASK 0x00000002L +#define SQ_THREAD_TRACE_HALT__ENTER_POWEROFF_MASK 0x00000004L +#define SQ_THREAD_TRACE_HALT__POWEROFF_READY_MASK 0x00000008L +//SQ_THREAD_TRACE_POWEROFF_RESTORE_1 +#define SQ_THREAD_TRACE_POWEROFF_RESTORE_1__STATES__SHIFT 0x0 +#define SQ_THREAD_TRACE_POWEROFF_RESTORE_1__STATES_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_STATUS +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0xc +#define SQ_THREAD_TRACE_STATUS__WRITE_ERROR__SHIFT 0x18 +#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x19 +#define SQ_THREAD_TRACE_STATUS__OWNER_VMID__SHIFT 0x1c +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x00000FFFL +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x00FFF000L +#define SQ_THREAD_TRACE_STATUS__WRITE_ERROR_MASK 0x01000000L +#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x02000000L +#define SQ_THREAD_TRACE_STATUS__OWNER_VMID_MASK 0xF0000000L +//SQ_THREAD_TRACE_STATUS2 +#define SQ_THREAD_TRACE_STATUS2__BUF0_FULL__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS2__BUF1_FULL__SHIFT 0x1 +#define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN__SHIFT 0x4 +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS__SHIFT 0x8 +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE__SHIFT 0xd +#define SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL__SHIFT 0xe +#define SQ_THREAD_TRACE_STATUS2__BUF0_FULL_MASK 0x00000001L +#define SQ_THREAD_TRACE_STATUS2__BUF1_FULL_MASK 0x00000002L +#define SQ_THREAD_TRACE_STATUS2__PACKET_LOST_BUF_NO_LOCKDOWN_MASK 0x00000010L +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_STATUS_MASK 0x00001F00L +#define SQ_THREAD_TRACE_STATUS2__BUF_ISSUE_MASK 0x00002000L +#define SQ_THREAD_TRACE_STATUS2__WRITE_BUF_FULL_MASK 0x00004000L +//SQ_THREAD_TRACE_GFX_DRAW_CNTR +#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_GFX_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_GFX_MARKER_CNTR +#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_GFX_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_HP3D_DRAW_CNTR +#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_HP3D_DRAW_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_HP3D_MARKER_CNTR +#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_HP3D_MARKER_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_DROPPED_CNTR +#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_DROPPED_CNTR__CNTR_MASK 0xFFFFFFFFL +//SQ_THREAD_TRACE_FINISH_DONE_DEBUG +#define SQ_THREAD_TRACE_FINISH_DONE_DEBUG__GFX__SHIFT 0x0 +#define SQ_THREAD_TRACE_FINISH_DONE_DEBUG__EXP__SHIFT 0xa +#define SQ_THREAD_TRACE_FINISH_DONE_DEBUG__GFX_MASK 0x000003FFL +#define SQ_THREAD_TRACE_FINISH_DONE_DEBUG__EXP_MASK 0x0000FC00L +//SX_PERFCOUNTER0_SELECT +#define SX_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER1_SELECT +#define SX_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER2_SELECT +#define SX_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER3_SELECT +#define SX_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SX_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define SX_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SX_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define SX_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define SX_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define SX_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//SX_PERFCOUNTER0_SELECT1 +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SX_PERFCOUNTER1_SELECT1 +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SX_PERFCOUNTER2_SELECT1 +#define SX_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//SX_PERFCOUNTER3_SELECT1 +#define SX_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SX_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SX_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define SX_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define SX_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define SX_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define SX_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define SX_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TA_PERFCOUNTER0_SELECT +#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TA_PERFCOUNTER0_SELECT1 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TA_PERFCOUNTER1_SELECT +#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT +#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TD_PERFCOUNTER0_SELECT1 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TD_PERFCOUNTER1_SELECT +#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER0_SELECT1 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER1_SELECT1 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER2_SELECT +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER2_SELECT1 +#define TCP_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER3_SELECT +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER3_SELECT1 +#define TCP_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define TCP_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define TCP_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define TCP_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//TCP_PERFCOUNTER4_SELECT +#define TCP_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER5_SELECT +#define TCP_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER6_SELECT +#define TCP_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xF0000000L +//TCP_PERFCOUNTER7_SELECT +#define TCP_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +#define TCP_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER0_SELECT +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1C_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER0_SELECT1 +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1C_PERFCOUNTER1_SELECT +#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1C_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER1_SELECT1 +#define GL1C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1C_PERFCOUNTER2_SELECT +#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1C_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER2_SELECT1 +#define GL1C_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1C_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1C_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1C_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1C_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1C_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1C_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1C_PERFCOUNTER3_SELECT +#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1C_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1C_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1C_PERFCOUNTER3_SELECT1 +#define GL1C_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1C_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1C_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1C_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1C_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1C_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1C_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1C_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XC_PERFCOUNTER0_SELECT +#define GL1XC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XC_PERFCOUNTER0_SELECT1 +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XC_PERFCOUNTER1_SELECT +#define GL1XC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XC_PERFCOUNTER1_SELECT1 +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XC_PERFCOUNTER2_SELECT +#define GL1XC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XC_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XC_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XC_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XC_PERFCOUNTER2_SELECT1 +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XC_PERFCOUNTER3_SELECT +#define GL1XC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XC_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XC_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XC_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XC_PERFCOUNTER3_SELECT1 +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XC_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CB_PERFCOUNTER_FILTER +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x00000001L +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0x0000000EL +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x00000010L +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x000003E0L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x00000400L +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x00000800L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x00001000L +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0x0000E000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x00020000L +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x001C0000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x00200000L +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0x00C00000L +//CB_PERFCOUNTER0_SELECT +#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER0_SELECT1 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//CB_PERFCOUNTER1_SELECT +#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER2_SELECT +#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//CB_PERFCOUNTER3_SELECT +#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT +#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER0_SELECT1 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT +#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER1_SELECT1 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER2_SELECT +#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER2_SELECT1 +#define DB_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//DB_PERFCOUNTER3_SELECT +#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//DB_PERFCOUNTER3_SELECT1 +#define DB_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define DB_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define DB_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define DB_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER0_SELECT +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define RMI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER0_SELECT1 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define RMI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER1_SELECT +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define RMI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERFCOUNTER2_SELECT1 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define RMI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define RMI_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//RMI_PERFCOUNTER3_SELECT +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define RMI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define RMI_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//RMI_PERF_COUNTER_CNTL +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL__SHIFT 0x0 +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL__SHIFT 0x2 +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL__SHIFT 0x4 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0__SHIFT 0x6 +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1__SHIFT 0x8 +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID__SHIFT 0xa +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID__SHIFT 0xe +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD__SHIFT 0x13 +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET__SHIFT 0x19 +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL__SHIFT 0x1a +#define RMI_PERF_COUNTER_CNTL__TRANS_BASED_PERF_EN_SEL_MASK 0x00000003L +#define RMI_PERF_COUNTER_CNTL__EVENT_BASED_PERF_EN_SEL_MASK 0x0000000CL +#define RMI_PERF_COUNTER_CNTL__TC_PERF_EN_SEL_MASK 0x00000030L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK0_MASK 0x000000C0L +#define RMI_PERF_COUNTER_CNTL__PERF_EVENT_WINDOW_MASK1_MASK 0x00000300L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_CID_MASK 0x00003C00L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_VMID_MASK 0x0007C000L +#define RMI_PERF_COUNTER_CNTL__PERF_COUNTER_BURST_LENGTH_THRESHOLD_MASK 0x01F80000L +#define RMI_PERF_COUNTER_CNTL__PERF_SOFT_RESET_MASK 0x02000000L +#define RMI_PERF_COUNTER_CNTL__PERF_CNTR_SPM_SEL_MASK 0x04000000L +//PA_PH_PERFCOUNTER0_SELECT +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER0_SELECT1 +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_PH_PERFCOUNTER1_SELECT +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER2_SELECT +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER3_SELECT +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//PA_PH_PERFCOUNTER4_SELECT +#define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER5_SELECT +#define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER6_SELECT +#define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER7_SELECT +#define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_PH_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x000003FFL +//PA_PH_PERFCOUNTER1_SELECT1 +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_PH_PERFCOUNTER2_SELECT1 +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//PA_PH_PERFCOUNTER3_SELECT1 +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define PA_PH_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//UTCL1_PERFCOUNTER0_SELECT +#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define UTCL1_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE1__SHIFT 0x18 +#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define UTCL1_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE1_MASK 0x0F000000L +#define UTCL1_PERFCOUNTER0_SELECT__COUNTER_MODE_MASK 0xF0000000L +//UTCL1_PERFCOUNTER0_SELECT1 +#define UTCL1_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define UTCL1_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define UTCL1_PERFCOUNTER0_SELECT1__COUNTER_MODE3__SHIFT 0x18 +#define UTCL1_PERFCOUNTER0_SELECT1__COUNTER_MODE2__SHIFT 0x1c +#define UTCL1_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define UTCL1_PERFCOUNTER0_SELECT1__COUNTER_MODE3_MASK 0x0F000000L +#define UTCL1_PERFCOUNTER0_SELECT1__COUNTER_MODE2_MASK 0xF0000000L +//UTCL1_PERFCOUNTER1_SELECT +#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define UTCL1_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE1__SHIFT 0x18 +#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define UTCL1_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0x00F00000L +#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE1_MASK 0x0F000000L +#define UTCL1_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK 0xF0000000L +//UTCL1_PERFCOUNTER1_SELECT1 +#define UTCL1_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define UTCL1_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define UTCL1_PERFCOUNTER1_SELECT1__COUNTER_MODE3__SHIFT 0x18 +#define UTCL1_PERFCOUNTER1_SELECT1__COUNTER_MODE2__SHIFT 0x1c +#define UTCL1_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define UTCL1_PERFCOUNTER1_SELECT1__COUNTER_MODE3_MASK 0x0F000000L +#define UTCL1_PERFCOUNTER1_SELECT1__COUNTER_MODE2_MASK 0xF0000000L +//UTCL1_PERFCOUNTER2_SELECT +#define UTCL1_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER2_SELECT__COUNTER_MODE_MASK 0xF0000000L +//UTCL1_PERFCOUNTER3_SELECT +#define UTCL1_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE__SHIFT 0x1c +#define UTCL1_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define UTCL1_PERFCOUNTER3_SELECT__COUNTER_MODE_MASK 0xF0000000L +//WGS_PERFCOUNTER1_SELECT +#define WGS_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define WGS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x1c +#define WGS_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define WGS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xF0000000L +//WGS_PERFCOUNTER0_SELECT1 +#define WGS_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define WGS_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define WGS_PERFCOUNTER0_SELECT1__CNTR_MODE3__SHIFT 0x18 +#define WGS_PERFCOUNTER0_SELECT1__CNTR_MODE2__SHIFT 0x1c +#define WGS_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define WGS_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define WGS_PERFCOUNTER0_SELECT1__CNTR_MODE3_MASK 0x0F000000L +#define WGS_PERFCOUNTER0_SELECT1__CNTR_MODE2_MASK 0xF0000000L +//WGS_PERFCOUNTER0_SELECT +#define WGS_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define WGS_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define WGS_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define WGS_PERFCOUNTER0_SELECT__CNTR_MODE1__SHIFT 0x18 +#define WGS_PERFCOUNTER0_SELECT__CNTR_MODE0__SHIFT 0x1c +#define WGS_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define WGS_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define WGS_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0x00F00000L +#define WGS_PERFCOUNTER0_SELECT__CNTR_MODE1_MASK 0x0F000000L +#define WGS_PERFCOUNTER0_SELECT__CNTR_MODE0_MASK 0xF0000000L +//GL1A_PERFCOUNTER0_SELECT +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1A_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER0_SELECT1 +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1A_PERFCOUNTER1_SELECT +#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1A_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER1_SELECT1 +#define GL1A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1A_PERFCOUNTER2_SELECT +#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1A_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER2_SELECT1 +#define GL1A_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1A_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1A_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1A_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1A_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1A_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1A_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1A_PERFCOUNTER3_SELECT +#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1A_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1A_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1A_PERFCOUNTER3_SELECT1 +#define GL1A_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1A_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1A_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1A_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1A_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1A_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1A_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1A_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XA_PERFCOUNTER0_SELECT +#define GL1XA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XA_PERFCOUNTER0_SELECT1 +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XA_PERFCOUNTER1_SELECT +#define GL1XA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XA_PERFCOUNTER1_SELECT1 +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XA_PERFCOUNTER2_SELECT +#define GL1XA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XA_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XA_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XA_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XA_PERFCOUNTER2_SELECT1 +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK 0xF0000000L +//GL1XA_PERFCOUNTER3_SELECT +#define GL1XA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define GL1XA_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define GL1XA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GL1XA_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define GL1XA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define GL1XA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0x00F00000L +#define GL1XA_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xF0000000L +//GL1XA_PERFCOUNTER3_SELECT1 +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT 0x18 +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT 0x1c +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x000003FFL +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0x000FFC00L +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK 0x0F000000L +#define GL1XA_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK 0xF0000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_pwrdec +//GFX_ICG_SPI_RA0_CLK_CTRL +#define GFX_ICG_SPI_RA0_CLK_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPI_RA0_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SPI_RA0_CLK_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_SPI_RA0_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//GFX_ICG_SPI_RA1_CLK_CTRL +#define GFX_ICG_SPI_RA1_CLK_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPI_RA1_CLK_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +//GFX_ICG_SPI_CS_CTRL +#define GFX_ICG_SPI_CS_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPI_CS_CTRL__OFF_HYSTERESIS__SHIFT 0x10 +#define GFX_ICG_SPI_CS_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_SPI_CS_CTRL__OFF_HYSTERESIS_MASK 0x003F0000L +//GFX_ICG_SPI_PS_CTRL +#define GFX_ICG_SPI_PS_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPI_PS_CTRL__OFF_HYSTERESIS__SHIFT 0x10 +#define GFX_ICG_SPI_PS_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_SPI_PS_CTRL__OFF_HYSTERESIS_MASK 0x003F0000L +//GFX_ICG_SPIS_CTRL +#define GFX_ICG_SPIS_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPIS_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SPIS_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_SPIS_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTX_SPI_DEBUG_CLK_CTRL +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x0 +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x6 +#define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x7 +#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE__SHIFT 0x9 +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0x0000003FL +#define CGTX_SPI_DEBUG_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x00000040L +#define CGTX_SPI_DEBUG_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x00000080L +#define CGTX_SPI_DEBUG_CLK_CTRL__SPI_REPEATER_FGCG_OVERRIDE_MASK 0x00000200L +//GFX_ICG_SPI_CTRL +#define GFX_ICG_SPI_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_SPI_CTRL__OFF_HYSTERESIS__SHIFT 0x10 +#define GFX_ICG_SPI_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SPI_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_SPI_CTRL__OFF_HYSTERESIS_MASK 0x003F0000L +#define GFX_ICG_SPI_CTRL__REG_OVERRIDE_MASK 0x80000000L +//GFX_ICG_PC_CLK_CTRL +#define GFX_ICG_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define GFX_ICG_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GFX_ICG_PC_CLK_CTRL__PC_GLOBAL_MGCG_OVERRIDE__SHIFT 0xc +#define GFX_ICG_PC_CLK_CTRL__PC_SC_INT_MGCG_OVERRIDE__SHIFT 0xd +#define GFX_ICG_PC_CLK_CTRL__MISS_WALKER_MGCG_OVERRIDE__SHIFT 0xe +#define GFX_ICG_PC_CLK_CTRL__PRIM_QUEUE_MGCG_OVERRIDE__SHIFT 0xf +#define GFX_ICG_PC_CLK_CTRL__GL1_IF_MGCG_OVERRIDE__SHIFT 0x10 +#define GFX_ICG_PC_CLK_CTRL__GL1_READ_RETURN_MGCG_OVERRIDE__SHIFT 0x11 +#define GFX_ICG_PC_CLK_CTRL__PC_MEM_MGCG_OVERRIDE__SHIFT 0x12 +#define GFX_ICG_PC_CLK_CTRL__LDS_WRITE_CNTL_MGCG_OVERRIDE__SHIFT 0x13 +#define GFX_ICG_PC_CLK_CTRL__LDS_OUT_MGCG_OVERRIDE__SHIFT 0x14 +#define GFX_ICG_PC_CLK_CTRL__PC_REGS_MGCG_OVERRIDE__SHIFT 0x15 +#define GFX_ICG_PC_CLK_CTRL__PC_PERFMON_MGCG_OVERRIDE__SHIFT 0x16 +#define GFX_ICG_PC_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define GFX_ICG_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GFX_ICG_PC_CLK_CTRL__PC_GLOBAL_MGCG_OVERRIDE_MASK 0x00001000L +#define GFX_ICG_PC_CLK_CTRL__PC_SC_INT_MGCG_OVERRIDE_MASK 0x00002000L +#define GFX_ICG_PC_CLK_CTRL__MISS_WALKER_MGCG_OVERRIDE_MASK 0x00004000L +#define GFX_ICG_PC_CLK_CTRL__PRIM_QUEUE_MGCG_OVERRIDE_MASK 0x00008000L +#define GFX_ICG_PC_CLK_CTRL__GL1_IF_MGCG_OVERRIDE_MASK 0x00010000L +#define GFX_ICG_PC_CLK_CTRL__GL1_READ_RETURN_MGCG_OVERRIDE_MASK 0x00020000L +#define GFX_ICG_PC_CLK_CTRL__PC_MEM_MGCG_OVERRIDE_MASK 0x00040000L +#define GFX_ICG_PC_CLK_CTRL__LDS_WRITE_CNTL_MGCG_OVERRIDE_MASK 0x00080000L +#define GFX_ICG_PC_CLK_CTRL__LDS_OUT_MGCG_OVERRIDE_MASK 0x00100000L +#define GFX_ICG_PC_CLK_CTRL__PC_REGS_MGCG_OVERRIDE_MASK 0x00200000L +#define GFX_ICG_PC_CLK_CTRL__PC_PERFMON_MGCG_OVERRIDE_MASK 0x00400000L +//GFX_ICG_BCI_CTRL +#define GFX_ICG_BCI_CTRL__GRP_OVERRIDES__SHIFT 0x0 +#define GFX_ICG_BCI_CTRL__OFF_HYSTERESIS__SHIFT 0x10 +#define GFX_ICG_BCI_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_BCI_CTRL__GRP_OVERRIDES_MASK 0x0000FFFFL +#define GFX_ICG_BCI_CTRL__OFF_HYSTERESIS_MASK 0x003F0000L +#define GFX_ICG_BCI_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_VGT_CLK_CTRL +#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_VGT_CLK_CTRL__PI1_OVERRIDE__SHIFT 0x17 +#define CGTT_VGT_CLK_CTRL__PI0_OVERRIDE__SHIFT 0x18 +#define CGTT_VGT_CLK_CTRL__HS_OVERRIDE__SHIFT 0x19 +#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d +#define CGTT_VGT_CLK_CTRL__DEPRICATED_RBIU_INPUT_OVERRIDE__SHIFT 0x1e +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_VGT_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_VGT_CLK_CTRL__PI1_OVERRIDE_MASK 0x00800000L +#define CGTT_VGT_CLK_CTRL__PI0_OVERRIDE_MASK 0x01000000L +#define CGTT_VGT_CLK_CTRL__HS_OVERRIDE_MASK 0x02000000L +#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000L +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000L +#define CGTT_VGT_CLK_CTRL__DEPRICATED_RBIU_INPUT_OVERRIDE_MASK 0x40000000L +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_GS_NGG_CLK_CTRL +#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE__SHIFT 0xf +#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE__SHIFT 0x10 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE__SHIFT 0x1b +#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE__SHIFT 0x1c +#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_GS_NGG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_GS_NGG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_GS_NGG_CLK_CTRL__PERF_ENABLE_MASK 0x00008000L +#define CGTT_GS_NGG_CLK_CTRL__DBG_ENABLE_MASK 0x00010000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_GS_NGG_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_GS_NGG_CLK_CTRL__PERF_OVERRIDE_MASK 0x08000000L +#define CGTT_GS_NGG_CLK_CTRL__PRIMGEN_OVERRIDE_MASK 0x10000000L +#define CGTT_GS_NGG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_PA_CLK_CTRL +#define CGTT_PA_CLK_CTRL__PAB_CLIP_SU_PRIM_FIFO_CLK_OVERRIDE__SHIFT 0x0 +#define CGTT_PA_CLK_CTRL__PAB_SXIFCCG_CLK_OVERRIDE__SHIFT 0x1 +#define CGTT_PA_CLK_CTRL__PAB_AG_CLK_OVERRIDE__SHIFT 0x2 +#define CGTT_PA_CLK_CTRL__PAB_VE_VTE_REC_CLK_OVERRIDE__SHIFT 0x3 +#define CGTT_PA_CLK_CTRL__PAB_ENGG_CLK_OVERRIDE__SHIFT 0x4 +#define CGTT_PA_CLK_CTRL__PAB_CL_VTE_CLK_OVERRIDE__SHIFT 0x5 +#define CGTT_PA_CLK_CTRL__PAB_AG_REG_CLK_OVERRIDE__SHIFT 0x6 +#define CGTT_PA_CLK_CTRL__PAB_CL_VTE_REG_CLK_OVERRIDE__SHIFT 0x7 +#define CGTT_PA_CLK_CTRL__PAB_VTE_REG_CLK_OVERRIDE__SHIFT 0x8 +#define CGTT_PA_CLK_CTRL__PAB_NGG_INDEX_CLK_OVERRIDE__SHIFT 0x9 +#define CGTT_PA_CLK_CTRL__PAB_NGG_CSB_CLK_OVERRIDE__SHIFT 0xa +#define CGTT_PA_CLK_CTRL__PAB_SU_CLK_OVERRIDE__SHIFT 0xb +#define CGTT_PA_CLK_CTRL__PAB_CL_CLK_OVERRIDE__SHIFT 0xc +#define CGTT_PA_CLK_CTRL__PAB_SU_CL_REG_CLK_OVERRIDE__SHIFT 0xd +#define CGTT_PA_CLK_CTRL__PAB_GLX_CLIENT_CLK_OVERRIDE__SHIFT 0xe +#define CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE__SHIFT 0xf +#define CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE__SHIFT 0x10 +#define CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE__SHIFT 0x11 +#define CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE__SHIFT 0x12 +#define CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE__SHIFT 0x13 +#define CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE__SHIFT 0x14 +#define CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE__SHIFT 0x15 +#define CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE__SHIFT 0x16 +#define CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE__SHIFT 0x17 +#define CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE__SHIFT 0x18 +#define CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_PA_CLK_CTRL__GLX_CLIENT_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN__SHIFT 0x1f +#define CGTT_PA_CLK_CTRL__PAB_CLIP_SU_PRIM_FIFO_CLK_OVERRIDE_MASK 0x00000001L +#define CGTT_PA_CLK_CTRL__PAB_SXIFCCG_CLK_OVERRIDE_MASK 0x00000002L +#define CGTT_PA_CLK_CTRL__PAB_AG_CLK_OVERRIDE_MASK 0x00000004L +#define CGTT_PA_CLK_CTRL__PAB_VE_VTE_REC_CLK_OVERRIDE_MASK 0x00000008L +#define CGTT_PA_CLK_CTRL__PAB_ENGG_CLK_OVERRIDE_MASK 0x00000010L +#define CGTT_PA_CLK_CTRL__PAB_CL_VTE_CLK_OVERRIDE_MASK 0x00000020L +#define CGTT_PA_CLK_CTRL__PAB_AG_REG_CLK_OVERRIDE_MASK 0x00000040L +#define CGTT_PA_CLK_CTRL__PAB_CL_VTE_REG_CLK_OVERRIDE_MASK 0x00000080L +#define CGTT_PA_CLK_CTRL__PAB_VTE_REG_CLK_OVERRIDE_MASK 0x00000100L +#define CGTT_PA_CLK_CTRL__PAB_NGG_INDEX_CLK_OVERRIDE_MASK 0x00000200L +#define CGTT_PA_CLK_CTRL__PAB_NGG_CSB_CLK_OVERRIDE_MASK 0x00000400L +#define CGTT_PA_CLK_CTRL__PAB_SU_CLK_OVERRIDE_MASK 0x00000800L +#define CGTT_PA_CLK_CTRL__PAB_CL_CLK_OVERRIDE_MASK 0x00001000L +#define CGTT_PA_CLK_CTRL__PAB_SU_CL_REG_CLK_OVERRIDE_MASK 0x00002000L +#define CGTT_PA_CLK_CTRL__PAB_GLX_CLIENT_CLK_OVERRIDE_MASK 0x00004000L +#define CGTT_PA_CLK_CTRL__CLIP_SU_PRIM_FIFO_CLK_OVERRIDE_MASK 0x00008000L +#define CGTT_PA_CLK_CTRL__SXIFCCG_CLK_OVERRIDE_MASK 0x00010000L +#define CGTT_PA_CLK_CTRL__AG_CLK_OVERRIDE_MASK 0x00020000L +#define CGTT_PA_CLK_CTRL__VE_VTE_REC_CLK_OVERRIDE_MASK 0x00040000L +#define CGTT_PA_CLK_CTRL__ENGG_CLK_OVERRIDE_MASK 0x00080000L +#define CGTT_PA_CLK_CTRL__CL_VTE_CLK_OVERRIDE_MASK 0x00100000L +#define CGTT_PA_CLK_CTRL__AG_REG_CLK_OVERRIDE_MASK 0x00200000L +#define CGTT_PA_CLK_CTRL__CL_VTE_REG_CLK_OVERRIDE_MASK 0x00400000L +#define CGTT_PA_CLK_CTRL__VTE_REG_CLK_OVERRIDE_MASK 0x00800000L +#define CGTT_PA_CLK_CTRL__NGG_INDEX_CLK_OVERRIDE_MASK 0x01000000L +#define CGTT_PA_CLK_CTRL__NGG_CSB_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_PA_CLK_CTRL__SU_CL_REG_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_PA_CLK_CTRL__GLX_CLIENT_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_PA_CLK_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_PA_CLK_CTRL__DEBUG_BUS_EN_MASK 0x80000000L +//CGTT_SQ_CLK_CTRL +#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SQ_CLK_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//CGTT_SQG_CLK_CTRL +#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQG_CLK_CTRL__CLUSTER_OVERRIDE__SHIFT 0xc +#define CGTT_SQG_CLK_CTRL__UTCL0_OVERRIDE__SHIFT 0xd +#define CGTT_SQG_CLK_CTRL__PM_OVERRIDE__SHIFT 0xe +#define CGTT_SQG_CLK_CTRL__FORCE_GCR_RSP_FGCG__SHIFT 0xf +#define CGTT_SQG_CLK_CTRL__PM_PIT_PRIME_FGCG_OVERRIDE__SHIFT 0x10 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define CGTT_SQG_CLK_CTRL__FORCE_GL1X_CLKEN__SHIFT 0x17 +#define CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG__SHIFT 0x18 +#define CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG__SHIFT 0x19 +#define CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG__SHIFT 0x1a +#define CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG__SHIFT 0x1b +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0x0000000FL +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SQG_CLK_CTRL__CLUSTER_OVERRIDE_MASK 0x00001000L +#define CGTT_SQG_CLK_CTRL__UTCL0_OVERRIDE_MASK 0x00002000L +#define CGTT_SQG_CLK_CTRL__PM_OVERRIDE_MASK 0x00004000L +#define CGTT_SQG_CLK_CTRL__FORCE_GCR_RSP_FGCG_MASK 0x00008000L +#define CGTT_SQG_CLK_CTRL__PM_PIT_PRIME_FGCG_OVERRIDE_MASK 0x00010000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define CGTT_SQG_CLK_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define CGTT_SQG_CLK_CTRL__FORCE_GL1X_CLKEN_MASK 0x00800000L +#define CGTT_SQG_CLK_CTRL__FORCE_EXPALLOC_FGCG_MASK 0x01000000L +#define CGTT_SQG_CLK_CTRL__FORCE_EXPGRANT_FGCG_MASK 0x02000000L +#define CGTT_SQG_CLK_CTRL__FORCE_EXPREQ_FGCG_MASK 0x04000000L +#define CGTT_SQG_CLK_CTRL__FORCE_CMD_FGCG_MASK 0x08000000L +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000L +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000L +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000L +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000L +//SQ_ALU_CLK_CTRL +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL +#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L +//SQ_TEX_CLK_CTRL +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL +#define SQ_TEX_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L +//SQ_LDS_CLK_CTRL +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0 +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10 +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA0_MASK 0x0000FFFFL +#define SQ_LDS_CLK_CTRL__FORCE_WGP_ON_SA1_MASK 0xFFFF0000L +//SQ_CLK_CTRL +#define SQ_CLK_CTRL__SQ_SPI_MSG_FGCG_OVERRIDE__SHIFT 0x2 +#define SQ_CLK_CTRL__SQ_SPI_EXPREQ_FGCG_OVERRIDE__SHIFT 0x3 +#define SQ_CLK_CTRL__SQ_SX_EXPCMD_FGCG_OVERRIDE__SHIFT 0x4 +#define SQ_CLK_CTRL__SQ_SQC_TTRACE_FGCG_OVERRIDE__SHIFT 0x5 +#define SQ_CLK_CTRL__WCLK_OVERRIDE__SHIFT 0x6 +#define SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x7 +#define SQ_CLK_CTRL__OVERRIDE_LDS_IDX_BUSY__SHIFT 0x8 +#define SQ_CLK_CTRL__OVERRIDE_LDS_DIRECT_BUSY__SHIFT 0x9 +#define SQ_CLK_CTRL__WCLK_SLEEP_VMEM_OVERRIDE__SHIFT 0xa +#define SQ_CLK_CTRL__WCLK_SLEEP_EXPALLOC_OVERRIDE__SHIFT 0xb +#define SQ_CLK_CTRL__SQ_SP_CMD_FGCG_OVERRIDE__SHIFT 0xc +#define SQ_CLK_CTRL__SQ_SP_CONST_FGCG_OVERRIDE__SHIFT 0xd +#define SQ_CLK_CTRL__SQ_SP_EXP_FGCG_OVERRIDE__SHIFT 0xe +#define SQ_CLK_CTRL__SQ_SP_VMEM_FGCG_OVERRIDE__SHIFT 0xf +#define SQ_CLK_CTRL__SQ_LDS_DIRECT_FGCG_OVERRIDE__SHIFT 0x10 +#define SQ_CLK_CTRL__IS_WAVECLK_IB_WCLK_OVERRIDE__SHIFT 0x11 +#define SQ_CLK_CTRL__ISC_SET_FGCG_OVERRIDE__SHIFT 0x12 +#define SQ_CLK_CTRL__ISC_CTRL_FGCG_OVERRIDE__SHIFT 0x13 +#define SQ_CLK_CTRL__ISC_WAVE_CTRL_FGCG_OVERRIDE__SHIFT 0x14 +#define SQ_CLK_CTRL__IB_IBUF_FGCG_OVERRIDE__SHIFT 0x15 +#define SQ_CLK_CTRL__IB_WINFO_FGCG_OVERRIDE__SHIFT 0x16 +#define SQ_CLK_CTRL__IB_MISC_FGCG_OVERRIDE__SHIFT 0x17 +#define SQ_CLK_CTRL__EX_SALU_FGCG_OVERRIDE__SHIFT 0x18 +#define SQ_CLK_CTRL__EX_VALU_FGCG_OVERRIDE__SHIFT 0x19 +#define SQ_CLK_CTRL__EX_BRMSG_FGCG_OVERRIDE__SHIFT 0x1a +#define SQ_CLK_CTRL__SQ_SP_ICG_FGCG_OVERRIDE__SHIFT 0x1b +#define SQ_CLK_CTRL__SQ_MCA_FGCG_OVERRIDE__SHIFT 0x1c +#define SQ_CLK_CTRL__SQ_TA_VMEMCMD_FGCG_OVERRIDE__SHIFT 0x1d +#define SQ_CLK_CTRL__SQ_SPI_MSG_FGCG_OVERRIDE_MASK 0x00000004L +#define SQ_CLK_CTRL__SQ_SPI_EXPREQ_FGCG_OVERRIDE_MASK 0x00000008L +#define SQ_CLK_CTRL__SQ_SX_EXPCMD_FGCG_OVERRIDE_MASK 0x00000010L +#define SQ_CLK_CTRL__SQ_SQC_TTRACE_FGCG_OVERRIDE_MASK 0x00000020L +#define SQ_CLK_CTRL__WCLK_OVERRIDE_MASK 0x00000040L +#define SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x00000080L +#define SQ_CLK_CTRL__OVERRIDE_LDS_IDX_BUSY_MASK 0x00000100L +#define SQ_CLK_CTRL__OVERRIDE_LDS_DIRECT_BUSY_MASK 0x00000200L +#define SQ_CLK_CTRL__WCLK_SLEEP_VMEM_OVERRIDE_MASK 0x00000400L +#define SQ_CLK_CTRL__WCLK_SLEEP_EXPALLOC_OVERRIDE_MASK 0x00000800L +#define SQ_CLK_CTRL__SQ_SP_CMD_FGCG_OVERRIDE_MASK 0x00001000L +#define SQ_CLK_CTRL__SQ_SP_CONST_FGCG_OVERRIDE_MASK 0x00002000L +#define SQ_CLK_CTRL__SQ_SP_EXP_FGCG_OVERRIDE_MASK 0x00004000L +#define SQ_CLK_CTRL__SQ_SP_VMEM_FGCG_OVERRIDE_MASK 0x00008000L +#define SQ_CLK_CTRL__SQ_LDS_DIRECT_FGCG_OVERRIDE_MASK 0x00010000L +#define SQ_CLK_CTRL__IS_WAVECLK_IB_WCLK_OVERRIDE_MASK 0x00020000L +#define SQ_CLK_CTRL__ISC_SET_FGCG_OVERRIDE_MASK 0x00040000L +#define SQ_CLK_CTRL__ISC_CTRL_FGCG_OVERRIDE_MASK 0x00080000L +#define SQ_CLK_CTRL__ISC_WAVE_CTRL_FGCG_OVERRIDE_MASK 0x00100000L +#define SQ_CLK_CTRL__IB_IBUF_FGCG_OVERRIDE_MASK 0x00200000L +#define SQ_CLK_CTRL__IB_WINFO_FGCG_OVERRIDE_MASK 0x00400000L +#define SQ_CLK_CTRL__IB_MISC_FGCG_OVERRIDE_MASK 0x00800000L +#define SQ_CLK_CTRL__EX_SALU_FGCG_OVERRIDE_MASK 0x01000000L +#define SQ_CLK_CTRL__EX_VALU_FGCG_OVERRIDE_MASK 0x02000000L +#define SQ_CLK_CTRL__EX_BRMSG_FGCG_OVERRIDE_MASK 0x04000000L +#define SQ_CLK_CTRL__SQ_SP_ICG_FGCG_OVERRIDE_MASK 0x08000000L +#define SQ_CLK_CTRL__SQ_MCA_FGCG_OVERRIDE_MASK 0x10000000L +#define SQ_CLK_CTRL__SQ_TA_VMEMCMD_FGCG_OVERRIDE_MASK 0x20000000L +//ICG_SQ_CLK_CTRL +#define ICG_SQ_CLK_CTRL__STATIC_OCLK_OVERRIDE__SHIFT 0x0 +#define ICG_SQ_CLK_CTRL__BOUNDARY_DCLK_OVERRIDE__SHIFT 0x1 +#define ICG_SQ_CLK_CTRL__BOUNDARY_CCLK_OVERRIDE__SHIFT 0x2 +#define ICG_SQ_CLK_CTRL__BOUNDARY_RCLK_OVERRIDE__SHIFT 0x3 +#define ICG_SQ_CLK_CTRL__DCLK_OVERRIDE__SHIFT 0x4 +#define ICG_SQ_CLK_CTRL__RCLK_OVERRIDE__SHIFT 0x5 +#define ICG_SQ_CLK_CTRL__PCLK_OVERRIDE__SHIFT 0x6 +#define ICG_SQ_CLK_CTRL__WCLK_OVERRIDE__SHIFT 0x7 +#define ICG_SQ_CLK_CTRL__SALU_CLK_OVERRIDE__SHIFT 0x8 +#define ICG_SQ_CLK_CTRL__VALU_CLK_OVERRIDE__SHIFT 0x9 +#define ICG_SQ_CLK_CTRL__VALU_SGPR_CLK_OVERRIDE__SHIFT 0xa +#define ICG_SQ_CLK_CTRL__VMEM_CLK_OVERRIDE__SHIFT 0xb +#define ICG_SQ_CLK_CTRL__VM_CLK_OVERRIDE__SHIFT 0xc +#define ICG_SQ_CLK_CTRL__TTRACE_CLK_OVERRIDE__SHIFT 0xd +#define ICG_SQ_CLK_CTRL__SQC_RET_CLK_OVERRIDE__SHIFT 0xe +#define ICG_SQ_CLK_CTRL__WAVEUPD_CLK_OVERRIDE__SHIFT 0xf +#define ICG_SQ_CLK_CTRL__WAVE_NEWDONE_CLK_OVERRIDE__SHIFT 0x10 +#define ICG_SQ_CLK_CTRL__WAVE_STATE_CLK_OVERRIDE__SHIFT 0x11 +#define ICG_SQ_CLK_CTRL__SFPU_CLK_OVERRIDE__SHIFT 0x12 +#define ICG_SQ_CLK_CTRL__SQC_SPECIAL_OP_CLK_OVERRIDE__SHIFT 0x13 +#define ICG_SQ_CLK_CTRL__WAVE_INSTBUF_CLK_OVERRIDE__SHIFT 0x14 +#define ICG_SQ_CLK_CTRL__IS_WAVECLK_OVERRIDE__SHIFT 0x15 +#define ICG_SQ_CLK_CTRL__SMEM_CLK_OVERRIDE__SHIFT 0x16 +#define ICG_SQ_CLK_CTRL__SDST_FIFO_CLK_OVERRIDE__SHIFT 0x17 +#define ICG_SQ_CLK_CTRL__SCALAR_BUF_CLK_OVERRIDE__SHIFT 0x18 +#define ICG_SQ_CLK_CTRL__SALU_PIPE_CLK_OVERRIDE__SHIFT 0x19 +#define ICG_SQ_CLK_CTRL__BRMSG_CLK_OVERRIDE__SHIFT 0x1a +#define ICG_SQ_CLK_CTRL__TAG_CLK_OVERRIDE__SHIFT 0x1b +#define ICG_SQ_CLK_CTRL__TAG_STATUS_CLK_OVERRIDE__SHIFT 0x1c +#define ICG_SQ_CLK_CTRL__EXP_CLK_OVERRIDE__SHIFT 0x1d +#define ICG_SQ_CLK_CTRL__VALU2_SGPR_CLK_OVERRIDE__SHIFT 0x1e +#define ICG_SQ_CLK_CTRL__STATIC_OCLK_OVERRIDE_MASK 0x00000001L +#define ICG_SQ_CLK_CTRL__BOUNDARY_DCLK_OVERRIDE_MASK 0x00000002L +#define ICG_SQ_CLK_CTRL__BOUNDARY_CCLK_OVERRIDE_MASK 0x00000004L +#define ICG_SQ_CLK_CTRL__BOUNDARY_RCLK_OVERRIDE_MASK 0x00000008L +#define ICG_SQ_CLK_CTRL__DCLK_OVERRIDE_MASK 0x00000010L +#define ICG_SQ_CLK_CTRL__RCLK_OVERRIDE_MASK 0x00000020L +#define ICG_SQ_CLK_CTRL__PCLK_OVERRIDE_MASK 0x00000040L +#define ICG_SQ_CLK_CTRL__WCLK_OVERRIDE_MASK 0x00000080L +#define ICG_SQ_CLK_CTRL__SALU_CLK_OVERRIDE_MASK 0x00000100L +#define ICG_SQ_CLK_CTRL__VALU_CLK_OVERRIDE_MASK 0x00000200L +#define ICG_SQ_CLK_CTRL__VALU_SGPR_CLK_OVERRIDE_MASK 0x00000400L +#define ICG_SQ_CLK_CTRL__VMEM_CLK_OVERRIDE_MASK 0x00000800L +#define ICG_SQ_CLK_CTRL__VM_CLK_OVERRIDE_MASK 0x00001000L +#define ICG_SQ_CLK_CTRL__TTRACE_CLK_OVERRIDE_MASK 0x00002000L +#define ICG_SQ_CLK_CTRL__SQC_RET_CLK_OVERRIDE_MASK 0x00004000L +#define ICG_SQ_CLK_CTRL__WAVEUPD_CLK_OVERRIDE_MASK 0x00008000L +#define ICG_SQ_CLK_CTRL__WAVE_NEWDONE_CLK_OVERRIDE_MASK 0x00010000L +#define ICG_SQ_CLK_CTRL__WAVE_STATE_CLK_OVERRIDE_MASK 0x00020000L +#define ICG_SQ_CLK_CTRL__SFPU_CLK_OVERRIDE_MASK 0x00040000L +#define ICG_SQ_CLK_CTRL__SQC_SPECIAL_OP_CLK_OVERRIDE_MASK 0x00080000L +#define ICG_SQ_CLK_CTRL__WAVE_INSTBUF_CLK_OVERRIDE_MASK 0x00100000L +#define ICG_SQ_CLK_CTRL__IS_WAVECLK_OVERRIDE_MASK 0x00200000L +#define ICG_SQ_CLK_CTRL__SMEM_CLK_OVERRIDE_MASK 0x00400000L +#define ICG_SQ_CLK_CTRL__SDST_FIFO_CLK_OVERRIDE_MASK 0x00800000L +#define ICG_SQ_CLK_CTRL__SCALAR_BUF_CLK_OVERRIDE_MASK 0x01000000L +#define ICG_SQ_CLK_CTRL__SALU_PIPE_CLK_OVERRIDE_MASK 0x02000000L +#define ICG_SQ_CLK_CTRL__BRMSG_CLK_OVERRIDE_MASK 0x04000000L +#define ICG_SQ_CLK_CTRL__TAG_CLK_OVERRIDE_MASK 0x08000000L +#define ICG_SQ_CLK_CTRL__TAG_STATUS_CLK_OVERRIDE_MASK 0x10000000L +#define ICG_SQ_CLK_CTRL__EXP_CLK_OVERRIDE_MASK 0x20000000L +#define ICG_SQ_CLK_CTRL__VALU2_SGPR_CLK_OVERRIDE_MASK 0x40000000L +//ICG_SP_CLK_CTRL +#define ICG_SP_CLK_CTRL__CLK_OVERRIDE__SHIFT 0x0 +#define ICG_SP_CLK_CTRL__CLK_OVERRIDE_MASK 0xFFFFFFFFL +//GFX_ICG_SX_CLK_CTRL0 +#define GFX_ICG_SX_CLK_CTRL0__RESERVED__SHIFT 0x0 +#define GFX_ICG_SX_CLK_CTRL0__PERF_SOFT_OVERRIDE__SHIFT 0x1e +#define GFX_ICG_SX_CLK_CTRL0__REG_SOFT_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SX_CLK_CTRL0__RESERVED_MASK 0x3FFFFFFFL +#define GFX_ICG_SX_CLK_CTRL0__PERF_SOFT_OVERRIDE_MASK 0x40000000L +#define GFX_ICG_SX_CLK_CTRL0__REG_SOFT_OVERRIDE_MASK 0x80000000L +//GFX_ICG_SX_CLK_CTRL1 +#define GFX_ICG_SX_CLK_CTRL1__RESERVED0__SHIFT 0x0 +#define GFX_ICG_SX_CLK_CTRL1__DBG_EN__SHIFT 0x18 +#define GFX_ICG_SX_CLK_CTRL1__RESERVED1__SHIFT 0x19 +#define GFX_ICG_SX_CLK_CTRL1__SX_SX_IO_SOFT_OVERRIDE__SHIFT 0x1e +#define GFX_ICG_SX_CLK_CTRL1__BDS_SOFT_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SX_CLK_CTRL1__RESERVED0_MASK 0x00FFFFFFL +#define GFX_ICG_SX_CLK_CTRL1__DBG_EN_MASK 0x01000000L +#define GFX_ICG_SX_CLK_CTRL1__RESERVED1_MASK 0x3E000000L +#define GFX_ICG_SX_CLK_CTRL1__SX_SX_IO_SOFT_OVERRIDE_MASK 0x40000000L +#define GFX_ICG_SX_CLK_CTRL1__BDS_SOFT_OVERRIDE_MASK 0x80000000L +//GFX_ICG_SX_CLK_CTRL2 +#define GFX_ICG_SX_CLK_CTRL2__RESERVED0__SHIFT 0x0 +#define GFX_ICG_SX_CLK_CTRL2__COL_WRITE_SOFT_OVERRIDE__SHIFT 0x17 +#define GFX_ICG_SX_CLK_CTRL2__DBG_EN__SHIFT 0x18 +#define GFX_ICG_SX_CLK_CTRL2__COL_REQUESTER_SOFT_OVERRIDE__SHIFT 0x19 +#define GFX_ICG_SX_CLK_CTRL2__COL_EXPORT_SOFT_OVERRIDE__SHIFT 0x1a +#define GFX_ICG_SX_CLK_CTRL2__COL_BLEND_SOFT_OVERRIDE__SHIFT 0x1b +#define GFX_ICG_SX_CLK_CTRL2__COL_DBIF_SOFT_OVERRIDE__SHIFT 0x1c +#define GFX_ICG_SX_CLK_CTRL2__COL_BLEND_DOWNCONVERT_SOFT_OVERRIDE__SHIFT 0x1d +#define GFX_ICG_SX_CLK_CTRL2__COL1_SOFT_OVERRIDE__SHIFT 0x1e +#define GFX_ICG_SX_CLK_CTRL2__COL0_SOFT_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SX_CLK_CTRL2__RESERVED0_MASK 0x007FFFFFL +#define GFX_ICG_SX_CLK_CTRL2__COL_WRITE_SOFT_OVERRIDE_MASK 0x00800000L +#define GFX_ICG_SX_CLK_CTRL2__DBG_EN_MASK 0x01000000L +#define GFX_ICG_SX_CLK_CTRL2__COL_REQUESTER_SOFT_OVERRIDE_MASK 0x02000000L +#define GFX_ICG_SX_CLK_CTRL2__COL_EXPORT_SOFT_OVERRIDE_MASK 0x04000000L +#define GFX_ICG_SX_CLK_CTRL2__COL_BLEND_SOFT_OVERRIDE_MASK 0x08000000L +#define GFX_ICG_SX_CLK_CTRL2__COL_DBIF_SOFT_OVERRIDE_MASK 0x10000000L +#define GFX_ICG_SX_CLK_CTRL2__COL_BLEND_DOWNCONVERT_SOFT_OVERRIDE_MASK 0x20000000L +#define GFX_ICG_SX_CLK_CTRL2__COL1_SOFT_OVERRIDE_MASK 0x40000000L +#define GFX_ICG_SX_CLK_CTRL2__COL0_SOFT_OVERRIDE_MASK 0x80000000L +//GFX_ICG_SX_CLK_CTRL3 +#define GFX_ICG_SX_CLK_CTRL3__RESERVED0__SHIFT 0x0 +#define GFX_ICG_SX_CLK_CTRL3__DBG_EN__SHIFT 0x18 +#define GFX_ICG_SX_CLK_CTRL3__RESERVED1__SHIFT 0x19 +#define GFX_ICG_SX_CLK_CTRL3__POS_WRITE_SOFT_OVERRIDE__SHIFT 0x1c +#define GFX_ICG_SX_CLK_CTRL3__POS_PAIF_SOFT_OVERRIDE__SHIFT 0x1d +#define GFX_ICG_SX_CLK_CTRL3__POS_EXPORT_SOFT_OVERRIDE__SHIFT 0x1e +#define GFX_ICG_SX_CLK_CTRL3__POS_SOFT_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SX_CLK_CTRL3__RESERVED0_MASK 0x00FFFFFFL +#define GFX_ICG_SX_CLK_CTRL3__DBG_EN_MASK 0x01000000L +#define GFX_ICG_SX_CLK_CTRL3__RESERVED1_MASK 0x0E000000L +#define GFX_ICG_SX_CLK_CTRL3__POS_WRITE_SOFT_OVERRIDE_MASK 0x10000000L +#define GFX_ICG_SX_CLK_CTRL3__POS_PAIF_SOFT_OVERRIDE_MASK 0x20000000L +#define GFX_ICG_SX_CLK_CTRL3__POS_EXPORT_SOFT_OVERRIDE_MASK 0x40000000L +#define GFX_ICG_SX_CLK_CTRL3__POS_SOFT_OVERRIDE_MASK 0x80000000L +//GFX_ICG_SX_CLK_CTRL4 +#define GFX_ICG_SX_CLK_CTRL4__RESERVED0__SHIFT 0x0 +#define GFX_ICG_SX_CLK_CTRL4__DBG_EN__SHIFT 0x18 +#define GFX_ICG_SX_CLK_CTRL4__RESERVED1__SHIFT 0x19 +#define GFX_ICG_SX_CLK_CTRL4__IDX_WRITE_SOFT_OVERRIDE__SHIFT 0x1c +#define GFX_ICG_SX_CLK_CTRL4__IDX_PAIF_SOFT_OVERRIDE__SHIFT 0x1d +#define GFX_ICG_SX_CLK_CTRL4__IDX_EXPORT_SOFT_OVERRIDE__SHIFT 0x1e +#define GFX_ICG_SX_CLK_CTRL4__IDX_SOFT_OVERRIDE__SHIFT 0x1f +#define GFX_ICG_SX_CLK_CTRL4__RESERVED0_MASK 0x00FFFFFFL +#define GFX_ICG_SX_CLK_CTRL4__DBG_EN_MASK 0x01000000L +#define GFX_ICG_SX_CLK_CTRL4__RESERVED1_MASK 0x0E000000L +#define GFX_ICG_SX_CLK_CTRL4__IDX_WRITE_SOFT_OVERRIDE_MASK 0x10000000L +#define GFX_ICG_SX_CLK_CTRL4__IDX_PAIF_SOFT_OVERRIDE_MASK 0x20000000L +#define GFX_ICG_SX_CLK_CTRL4__IDX_EXPORT_SOFT_OVERRIDE_MASK 0x40000000L +#define GFX_ICG_SX_CLK_CTRL4__IDX_SOFT_OVERRIDE_MASK 0x80000000L +//GFX_ICG_TA_CTRL +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE0__SHIFT 0x0 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE1__SHIFT 0x1 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE2__SHIFT 0x2 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE3__SHIFT 0x3 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE4__SHIFT 0x4 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE5__SHIFT 0x5 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE6__SHIFT 0x6 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE7__SHIFT 0x7 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE8__SHIFT 0x8 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE9__SHIFT 0x9 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE10__SHIFT 0xa +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE11__SHIFT 0xb +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE12__SHIFT 0xc +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE13__SHIFT 0xd +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE14__SHIFT 0xe +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE15__SHIFT 0xf +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE16__SHIFT 0x10 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE17__SHIFT 0x11 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE18__SHIFT 0x12 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE19__SHIFT 0x13 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE20__SHIFT 0x14 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE21__SHIFT 0x15 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE22__SHIFT 0x16 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE23__SHIFT 0x17 +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE0_MASK 0x00000001L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE1_MASK 0x00000002L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE2_MASK 0x00000004L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE3_MASK 0x00000008L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE4_MASK 0x00000010L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE5_MASK 0x00000020L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE6_MASK 0x00000040L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE7_MASK 0x00000080L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE8_MASK 0x00000100L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE9_MASK 0x00000200L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE10_MASK 0x00000400L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE11_MASK 0x00000800L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE12_MASK 0x00001000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE13_MASK 0x00002000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE14_MASK 0x00004000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE15_MASK 0x00008000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE16_MASK 0x00010000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE17_MASK 0x00020000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE18_MASK 0x00040000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE19_MASK 0x00080000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE20_MASK 0x00100000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE21_MASK 0x00200000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE22_MASK 0x00400000L +#define GFX_ICG_TA_CTRL__SOFT_OVERRIDE23_MASK 0x00800000L +//GFX_ICG_TD_CTRL +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE0__SHIFT 0x0 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE1__SHIFT 0x1 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE2__SHIFT 0x2 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE3__SHIFT 0x3 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE4__SHIFT 0x4 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE5__SHIFT 0x5 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE6__SHIFT 0x6 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE7__SHIFT 0x7 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE8__SHIFT 0x8 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE9__SHIFT 0x9 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE10__SHIFT 0xa +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE11__SHIFT 0xb +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE12__SHIFT 0xc +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE13__SHIFT 0xd +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE14__SHIFT 0xe +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE15__SHIFT 0xf +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE16__SHIFT 0x10 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE17__SHIFT 0x11 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE18__SHIFT 0x12 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE19__SHIFT 0x13 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE20__SHIFT 0x14 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE21__SHIFT 0x15 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE22__SHIFT 0x16 +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE0_MASK 0x00000001L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE1_MASK 0x00000002L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE2_MASK 0x00000004L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE3_MASK 0x00000008L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE4_MASK 0x00000010L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE5_MASK 0x00000020L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE6_MASK 0x00000040L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE7_MASK 0x00000080L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE8_MASK 0x00000100L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE9_MASK 0x00000200L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE10_MASK 0x00000400L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE11_MASK 0x00000800L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE12_MASK 0x00001000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE13_MASK 0x00002000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE14_MASK 0x00004000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE15_MASK 0x00008000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE16_MASK 0x00010000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE17_MASK 0x00020000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE18_MASK 0x00040000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE19_MASK 0x00080000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE20_MASK 0x00100000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE21_MASK 0x00200000L +#define GFX_ICG_TD_CTRL__SOFT_OVERRIDE22_MASK 0x00400000L +//DB_CGTT_CLK_CTRL_0 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x0 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x2 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x3 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x4 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x5 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x6 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8__SHIFT 0x8 +#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0x9 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x00000001L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x00000002L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x00000004L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x00000008L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x00000010L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x00000020L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x00000040L +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE8_MASK 0x00000100L +#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xFFFFFE00L +//GFX_ICG_CB_CTRL +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE31__SHIFT 0x0 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE30__SHIFT 0x1 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE29__SHIFT 0x2 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE28__SHIFT 0x3 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE27__SHIFT 0x4 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE26__SHIFT 0x5 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE25__SHIFT 0x6 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE24__SHIFT 0x7 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE23__SHIFT 0x8 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE22__SHIFT 0x9 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE21__SHIFT 0xa +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE19__SHIFT 0xc +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE18__SHIFT 0xd +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE17__SHIFT 0xe +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE16__SHIFT 0xf +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE15__SHIFT 0x10 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE14__SHIFT 0x11 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE11__SHIFT 0x14 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE10__SHIFT 0x15 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE9__SHIFT 0x16 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE8__SHIFT 0x17 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE31_MASK 0x00000001L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE30_MASK 0x00000002L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE29_MASK 0x00000004L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE28_MASK 0x00000008L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE27_MASK 0x00000010L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE26_MASK 0x00000020L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE25_MASK 0x00000040L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE24_MASK 0x00000080L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE23_MASK 0x00000100L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE22_MASK 0x00000200L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE21_MASK 0x00000400L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE19_MASK 0x00001000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE18_MASK 0x00002000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE17_MASK 0x00004000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE16_MASK 0x00008000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE15_MASK 0x00010000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE14_MASK 0x00020000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE11_MASK 0x00100000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE10_MASK 0x00200000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE9_MASK 0x00400000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE8_MASK 0x00800000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define GFX_ICG_CB_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//GFX_ICG_RMI_CTRL +#define GFX_ICG_RMI_CTRL__ON_DELAY__SHIFT 0x0 +#define GFX_ICG_RMI_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define GFX_ICG_RMI_CTRL__ON_DELAY_MASK 0x0000000FL +#define GFX_ICG_RMI_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L +#define GFX_ICG_RMI_CTRL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L +#define GFX_ICG_RMI_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L +//GFX_ICG_SE_CAC_CLK_CTRL +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_DYNAMIC_ICG_OVERRIDE__SHIFT 0x0 +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_REG_ICG_OVERRIDE__SHIFT 0x1 +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_STATIC_ICG_OVERRIDE__SHIFT 0x2 +#define GFX_ICG_SE_CAC_CLK_CTRL__FGCG_REP_OVERRIDE__SHIFT 0x3 +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_DYNAMIC_ICG_OVERRIDE_MASK 0x00000001L +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_REG_ICG_OVERRIDE_MASK 0x00000002L +#define GFX_ICG_SE_CAC_CLK_CTRL__SE_CAC_STATIC_ICG_OVERRIDE_MASK 0x00000004L +#define GFX_ICG_SE_CAC_CLK_CTRL__FGCG_REP_OVERRIDE_MASK 0x00000008L +//CGTT_PH_CLK_CTRL0 +#define CGTT_PH_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL0__DEBUG_BUS_EN__SHIFT 0x17 +#define CGTT_PH_CLK_CTRL0__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON__SHIFT 0x18 +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_PH_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL0__DEBUG_BUS_EN_MASK 0x00800000L +#define CGTT_PH_CLK_CTRL0__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON_MASK 0x01000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL0__PERFMON_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_PH_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_PH_CLK_CTRL1 +#define CGTT_PH_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL1__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL1__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000L +//CGTT_PH_CLK_CTRL2 +#define CGTT_PH_CLK_CTRL2__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL2__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL2__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000L +//CGTT_PH_CLK_CTRL3 +#define CGTT_PH_CLK_CTRL3__ON_DELAY__SHIFT 0x0 +#define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_PH_CLK_CTRL3__ON_DELAY_MASK 0x0000000FL +#define CGTT_PH_CLK_CTRL3__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x01000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x02000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x04000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x08000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000L +#define CGTT_PH_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000L +//GFX_ICG_TCP_CTRL +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_0__SHIFT 0x0 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_1__SHIFT 0x1 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_2__SHIFT 0x2 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_3__SHIFT 0x3 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_4__SHIFT 0x4 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_5__SHIFT 0x5 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_6__SHIFT 0x6 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_7__SHIFT 0x7 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_8__SHIFT 0x8 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_9__SHIFT 0x9 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_10__SHIFT 0xa +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_11__SHIFT 0xb +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_12__SHIFT 0xc +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_13__SHIFT 0xd +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_14__SHIFT 0xe +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_15__SHIFT 0xf +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_16__SHIFT 0x10 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_17__SHIFT 0x11 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_18__SHIFT 0x12 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_19__SHIFT 0x13 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_20__SHIFT 0x14 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_21__SHIFT 0x15 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_22__SHIFT 0x16 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_23__SHIFT 0x17 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_24__SHIFT 0x18 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_25__SHIFT 0x19 +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_26__SHIFT 0x1a +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_27__SHIFT 0x1b +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_28__SHIFT 0x1c +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_29__SHIFT 0x1d +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_0_MASK 0x00000001L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_1_MASK 0x00000002L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_2_MASK 0x00000004L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_3_MASK 0x00000008L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_4_MASK 0x00000010L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_5_MASK 0x00000020L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_6_MASK 0x00000040L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_7_MASK 0x00000080L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_8_MASK 0x00000100L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_9_MASK 0x00000200L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_10_MASK 0x00000400L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_11_MASK 0x00000800L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_12_MASK 0x00001000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_13_MASK 0x00002000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_14_MASK 0x00004000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_15_MASK 0x00008000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_16_MASK 0x00010000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_17_MASK 0x00020000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_18_MASK 0x00040000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_19_MASK 0x00080000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_20_MASK 0x00100000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_21_MASK 0x00200000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_22_MASK 0x00400000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_23_MASK 0x00800000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_24_MASK 0x01000000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_25_MASK 0x02000000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_26_MASK 0x04000000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_27_MASK 0x08000000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_28_MASK 0x10000000L +#define GFX_ICG_TCP_CTRL__SOFT_OVERRIDE_29_MASK 0x20000000L +//GFX_ICG_TCP_CTRL2 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_0__SHIFT 0x0 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_1__SHIFT 0x1 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_2__SHIFT 0x2 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_3__SHIFT 0x3 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_4__SHIFT 0x4 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_5__SHIFT 0x5 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_6__SHIFT 0x6 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_7__SHIFT 0x7 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_8__SHIFT 0x8 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_9__SHIFT 0x9 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_10__SHIFT 0xa +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_11__SHIFT 0xb +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_12__SHIFT 0xc +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_13__SHIFT 0xd +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_14__SHIFT 0xe +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_15__SHIFT 0xf +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_16__SHIFT 0x10 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_17__SHIFT 0x11 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_18__SHIFT 0x12 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_19__SHIFT 0x13 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_20__SHIFT 0x14 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_21__SHIFT 0x15 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_22__SHIFT 0x16 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_23__SHIFT 0x17 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_24__SHIFT 0x18 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_25__SHIFT 0x19 +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_26__SHIFT 0x1a +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_27__SHIFT 0x1b +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_28__SHIFT 0x1c +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_29__SHIFT 0x1d +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_30__SHIFT 0x1e +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_0_MASK 0x00000001L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_1_MASK 0x00000002L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_2_MASK 0x00000004L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_3_MASK 0x00000008L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_4_MASK 0x00000010L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_5_MASK 0x00000020L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_6_MASK 0x00000040L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_7_MASK 0x00000080L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_8_MASK 0x00000100L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_9_MASK 0x00000200L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_10_MASK 0x00000400L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_11_MASK 0x00000800L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_12_MASK 0x00001000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_13_MASK 0x00002000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_14_MASK 0x00004000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_15_MASK 0x00008000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_16_MASK 0x00010000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_17_MASK 0x00020000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_18_MASK 0x00040000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_19_MASK 0x00080000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_20_MASK 0x00100000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_21_MASK 0x00200000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_22_MASK 0x00400000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_23_MASK 0x00800000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_24_MASK 0x01000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_25_MASK 0x02000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_26_MASK 0x04000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_27_MASK 0x08000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_28_MASK 0x10000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_29_MASK 0x20000000L +#define GFX_ICG_TCP_CTRL2__SOFT_OVERRIDE_30_MASK 0x40000000L +//ICG_LDS_CLK_CTRL +#define ICG_LDS_CLK_CTRL__HARVEST_WGP_OVERRIDE__SHIFT 0x0 +#define ICG_LDS_CLK_CTRL__CONFIG_REG_OVERRIDE__SHIFT 0x1 +#define ICG_LDS_CLK_CTRL__TD_OVERRIDE__SHIFT 0x2 +#define ICG_LDS_CLK_CTRL__ATTR_WR_OVERRIDE__SHIFT 0x3 +#define ICG_LDS_CLK_CTRL__DLOAD0_OVERRIDE__SHIFT 0x4 +#define ICG_LDS_CLK_CTRL__DLOAD1_OVERRIDE__SHIFT 0x5 +#define ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE__SHIFT 0x6 +#define ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE__SHIFT 0x7 +#define ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE__SHIFT 0x8 +#define ICG_LDS_CLK_CTRL__IDX_INPUT_QUEUE_OVERRIDE__SHIFT 0x9 +#define ICG_LDS_CLK_CTRL__IDX_INPUT_QUEUE_BVH_OVERRIDE__SHIFT 0xa +#define ICG_LDS_CLK_CTRL__IDX_SCHED_INPUT_OVERRIDE__SHIFT 0xb +#define ICG_LDS_CLK_CTRL__IDX_BANK_CONFLICT_OVERRIDE__SHIFT 0xc +#define ICG_LDS_CLK_CTRL__IDX_SCHEDULER_OVERRIDE__SHIFT 0xd +#define ICG_LDS_CLK_CTRL__IDX_SCHED_DATA_PIPE_OVERRIDE__SHIFT 0xe +#define ICG_LDS_CLK_CTRL__IDX_SCHED_PIPE_OVERRIDE__SHIFT 0xf +#define ICG_LDS_CLK_CTRL__IDX_SCHED_OUTPUT_OVERRIDE__SHIFT 0x10 +#define ICG_LDS_CLK_CTRL__IDX_PIPE_OVERRIDE__SHIFT 0x11 +#define ICG_LDS_CLK_CTRL__IDX_DIR_OVERRIDE__SHIFT 0x12 +#define ICG_LDS_CLK_CTRL__IDX_WR_OVERRIDE__SHIFT 0x13 +#define ICG_LDS_CLK_CTRL__WGP_ARB_OVERRIDE__SHIFT 0x14 +#define ICG_LDS_CLK_CTRL__MEM_OVERRIDE__SHIFT 0x15 +#define ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE__SHIFT 0x16 +#define ICG_LDS_CLK_CTRL__IDX_WR_ADDR_OVERRIDE__SHIFT 0x17 +#define ICG_LDS_CLK_CTRL__IDX_RDRTN_OVERRIDE__SHIFT 0x18 +#define ICG_LDS_CLK_CTRL__IDX_OUTPUT_ALIGNER_OVERRIDE__SHIFT 0x19 +#define ICG_LDS_CLK_CTRL__DIR_OUTPUT_ALIGNER_OVERRIDE__SHIFT 0x1a +#define ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE__SHIFT 0x1b +#define ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE__SHIFT 0x1c +#define ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE__SHIFT 0x1d +#define ICG_LDS_CLK_CTRL__HARVEST_WGP_OVERRIDE_MASK 0x00000001L +#define ICG_LDS_CLK_CTRL__CONFIG_REG_OVERRIDE_MASK 0x00000002L +#define ICG_LDS_CLK_CTRL__TD_OVERRIDE_MASK 0x00000004L +#define ICG_LDS_CLK_CTRL__ATTR_WR_OVERRIDE_MASK 0x00000008L +#define ICG_LDS_CLK_CTRL__DLOAD0_OVERRIDE_MASK 0x00000010L +#define ICG_LDS_CLK_CTRL__DLOAD1_OVERRIDE_MASK 0x00000020L +#define ICG_LDS_CLK_CTRL__SQ_LDS_VMEMCMD_OVERRIDE_MASK 0x00000040L +#define ICG_LDS_CLK_CTRL__SP_LDS_VMEMREQ_OVERRIDE_MASK 0x00000080L +#define ICG_LDS_CLK_CTRL__SPI_LDS_STALL_OVERRIDE_MASK 0x00000100L +#define ICG_LDS_CLK_CTRL__IDX_INPUT_QUEUE_OVERRIDE_MASK 0x00000200L +#define ICG_LDS_CLK_CTRL__IDX_INPUT_QUEUE_BVH_OVERRIDE_MASK 0x00000400L +#define ICG_LDS_CLK_CTRL__IDX_SCHED_INPUT_OVERRIDE_MASK 0x00000800L +#define ICG_LDS_CLK_CTRL__IDX_BANK_CONFLICT_OVERRIDE_MASK 0x00001000L +#define ICG_LDS_CLK_CTRL__IDX_SCHEDULER_OVERRIDE_MASK 0x00002000L +#define ICG_LDS_CLK_CTRL__IDX_SCHED_DATA_PIPE_OVERRIDE_MASK 0x00004000L +#define ICG_LDS_CLK_CTRL__IDX_SCHED_PIPE_OVERRIDE_MASK 0x00008000L +#define ICG_LDS_CLK_CTRL__IDX_SCHED_OUTPUT_OVERRIDE_MASK 0x00010000L +#define ICG_LDS_CLK_CTRL__IDX_PIPE_OVERRIDE_MASK 0x00020000L +#define ICG_LDS_CLK_CTRL__IDX_DIR_OVERRIDE_MASK 0x00040000L +#define ICG_LDS_CLK_CTRL__IDX_WR_OVERRIDE_MASK 0x00080000L +#define ICG_LDS_CLK_CTRL__WGP_ARB_OVERRIDE_MASK 0x00100000L +#define ICG_LDS_CLK_CTRL__MEM_OVERRIDE_MASK 0x00200000L +#define ICG_LDS_CLK_CTRL__MEM_WR_OVERRIDE_MASK 0x00400000L +#define ICG_LDS_CLK_CTRL__IDX_WR_ADDR_OVERRIDE_MASK 0x00800000L +#define ICG_LDS_CLK_CTRL__IDX_RDRTN_OVERRIDE_MASK 0x01000000L +#define ICG_LDS_CLK_CTRL__IDX_OUTPUT_ALIGNER_OVERRIDE_MASK 0x02000000L +#define ICG_LDS_CLK_CTRL__DIR_OUTPUT_ALIGNER_OVERRIDE_MASK 0x04000000L +#define ICG_LDS_CLK_CTRL__LDS_SP_READ_OVERRIDE_MASK 0x08000000L +#define ICG_LDS_CLK_CTRL__LDS_SP_DONE_OVERRIDE_MASK 0x10000000L +#define ICG_LDS_CLK_CTRL__LDS_SQC_PERF_OVERRIDE_MASK 0x20000000L +//GFX_ICG_UTCL1_CTRL +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE0__SHIFT 0x0 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE1__SHIFT 0x1 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE2__SHIFT 0x2 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE3__SHIFT 0x3 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE4__SHIFT 0x4 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE5__SHIFT 0x5 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE6__SHIFT 0x6 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE7__SHIFT 0x7 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE8__SHIFT 0x8 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE9__SHIFT 0x9 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE10__SHIFT 0xa +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE11__SHIFT 0xb +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE12__SHIFT 0xc +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE13__SHIFT 0xd +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE14__SHIFT 0xe +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE15__SHIFT 0xf +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE16__SHIFT 0x10 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE17__SHIFT 0x11 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE18__SHIFT 0x12 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE19__SHIFT 0x13 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE20__SHIFT 0x14 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE21__SHIFT 0x15 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE22__SHIFT 0x16 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE23__SHIFT 0x17 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE24__SHIFT 0x18 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE25__SHIFT 0x19 +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE26__SHIFT 0x1a +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE26_31__SHIFT 0x1b +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE0_MASK 0x00000001L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE1_MASK 0x00000002L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE2_MASK 0x00000004L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE3_MASK 0x00000008L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE4_MASK 0x00000010L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE5_MASK 0x00000020L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE6_MASK 0x00000040L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE7_MASK 0x00000080L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE8_MASK 0x00000100L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE9_MASK 0x00000200L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE10_MASK 0x00000400L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE11_MASK 0x00000800L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE12_MASK 0x00001000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE13_MASK 0x00002000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE14_MASK 0x00004000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE15_MASK 0x00008000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE16_MASK 0x00010000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE17_MASK 0x00020000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE18_MASK 0x00040000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE19_MASK 0x00080000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE20_MASK 0x00100000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE21_MASK 0x00200000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE22_MASK 0x00400000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE23_MASK 0x00800000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE24_MASK 0x01000000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE25_MASK 0x02000000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE26_MASK 0x04000000L +#define GFX_ICG_UTCL1_CTRL__SOFT_OVERRIDE26_31_MASK 0xF8000000L +//GFX_ICG_GRBMH_CTRL +#define GFX_ICG_GRBMH_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_SE__SHIFT 0x10 +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define GFX_ICG_GRBMH_CTRL__OFF_HYSTERESIS_MASK 0x000003F0L +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_SE_MASK 0x00FF0000L +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000L +#define GFX_ICG_GRBMH_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_sc_pwrdec +//CGTT_SC_CLK_CTRL0 +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL0__VRC_OVERRIDE__SHIFT 0xc +#define CGTT_SC_CLK_CTRL0__HZC_OVERRIDE__SHIFT 0xd +#define CGTT_SC_CLK_CTRL0__HSC_OVERRIDE__SHIFT 0xe +#define CGTT_SC_CLK_CTRL0__HPF_OVERRIDE__SHIFT 0xf +#define CGTT_SC_CLK_CTRL0__G2DYN_STALL_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL0__FEDYN_STALL_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL0__GL1X_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL0__FEDYN_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL0__PERFMON_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +#define CGTT_SC_CLK_CTRL0__VRC_OVERRIDE_MASK 0x00001000L +#define CGTT_SC_CLK_CTRL0__HZC_OVERRIDE_MASK 0x00002000L +#define CGTT_SC_CLK_CTRL0__HSC_OVERRIDE_MASK 0x00004000L +#define CGTT_SC_CLK_CTRL0__HPF_OVERRIDE_MASK 0x00008000L +#define CGTT_SC_CLK_CTRL0__G2DYN_STALL_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL0__FEDYN_STALL_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_STALL_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL0__GL1X_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL0__FEDYN_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL0__PERFMON_OVERRIDE_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL0__REG_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL1 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL1__SC_DB_QP_SAMPLEMASK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_STALL_OVERRIDE_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_STALL_OVERRIDE_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_STALL_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL1__PBB_CLK_STALL_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL1__PBB_BINNING_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL1__PBB_SCISSOR_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL1__SCREEN_EXT_REG_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL1__VPORT_REG_MEM_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL1__SC_DB_QP_SAMPLEMASK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL2 +#define CGTT_SC_CLK_CTRL2__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON__SHIFT 0xf +#define CGTT_SC_CLK_CTRL2__SC_DB_HISZCA_OVERRIDE__SHIFT 0x11 +#define CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL2__DB_SC_WAVE_INTF_CLK_OVERRIDE__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL2__DISABLE_DEBUG_BUS_FLOP_EN_ON_PERFMON_MASK 0x00008000L +#define CGTT_SC_CLK_CTRL2__SC_DB_HISZCA_OVERRIDE_MASK 0x00020000L +#define CGTT_SC_CLK_CTRL2__SC_DB_STAGE_IN_TP_PFFB_WR_OVERRIDE_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUADMASK_Z_OVERRIDE_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_PROC_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL2__SC_DB_QUAD_ACCUM_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL2__SC_DB_PKR_OVERRIDE_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL2__DB_SC_WAVE_INTF_CLK_OVERRIDE_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL2__SC_PKR_INTF_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL2__SC_DB_INTF_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL2__PA_SC_INTF_CLK_OVERRIDE_MASK 0x40000000L +//CGTT_SC_CLK_CTRL3 +#define CGTT_SC_CLK_CTRL3__RESERVED_00__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL3__RESERVED_01__SHIFT 0x1 +#define CGTT_SC_CLK_CTRL3__RESERVED_02__SHIFT 0x2 +#define CGTT_SC_CLK_CTRL3__RESERVED_03__SHIFT 0x3 +#define CGTT_SC_CLK_CTRL3__RESERVED_04__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL3__RESERVED_05__SHIFT 0x5 +#define CGTT_SC_CLK_CTRL3__RESERVED_06__SHIFT 0x6 +#define CGTT_SC_CLK_CTRL3__RESERVED_07__SHIFT 0x7 +#define CGTT_SC_CLK_CTRL3__RESERVED_08__SHIFT 0x8 +#define CGTT_SC_CLK_CTRL3__RESERVED_09__SHIFT 0x9 +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE__SHIFT 0xa +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE__SHIFT 0xb +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE__SHIFT 0xc +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE__SHIFT 0xd +#define CGTT_SC_CLK_CTRL3__RESERVED_18__SHIFT 0x12 +#define CGTT_SC_CLK_CTRL3__RESERVED_19__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL3__RESERVED_20__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL3__RESERVED_21__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL3__RESERVED_22__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL3__RESERVED_23__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL3__RESERVED_24__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL3__RESERVED_25__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL3__RESERVED_26__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL3__RESERVED_27__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL3__RESERVED_00_MASK 0x00000001L +#define CGTT_SC_CLK_CTRL3__RESERVED_01_MASK 0x00000002L +#define CGTT_SC_CLK_CTRL3__RESERVED_02_MASK 0x00000004L +#define CGTT_SC_CLK_CTRL3__RESERVED_03_MASK 0x00000008L +#define CGTT_SC_CLK_CTRL3__RESERVED_04_MASK 0x00000010L +#define CGTT_SC_CLK_CTRL3__RESERVED_05_MASK 0x00000020L +#define CGTT_SC_CLK_CTRL3__RESERVED_06_MASK 0x00000040L +#define CGTT_SC_CLK_CTRL3__RESERVED_07_MASK 0x00000080L +#define CGTT_SC_CLK_CTRL3__RESERVED_08_MASK 0x00000100L +#define CGTT_SC_CLK_CTRL3__RESERVED_09_MASK 0x00000200L +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_STALL_OVERRIDE_MASK 0x00000400L +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_STALL_OVERRIDE_MASK 0x00000800L +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_STALL_OVERRIDE_MASK 0x00001000L +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_STALL_OVERRIDE_MASK 0x00002000L +#define CGTT_SC_CLK_CTRL3__RESERVED_18_MASK 0x00040000L +#define CGTT_SC_CLK_CTRL3__RESERVED_19_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL3__RESERVED_20_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL3__RESERVED_21_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL3__RESERVED_22_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL3__RESERVED_23_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL3__RESERVED_24_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL3__RESERVED_25_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL3__RESERVED_26_MASK 0x04000000L +#define CGTT_SC_CLK_CTRL3__RESERVED_27_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL3__PBB_FRONT_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL3__PBB_BATCHIN_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL3__PBB_VRASTER_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL3__PBB_VGATHER_CLK_OVERRIDE_MASK 0x80000000L +//CGTT_SC_CLK_CTRL4 +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE__SHIFT 0x1 +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE__SHIFT 0x2 +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE__SHIFT 0x3 +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE__SHIFT 0x5 +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE__SHIFT 0x6 +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE__SHIFT 0x8 +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE__SHIFT 0x9 +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE__SHIFT 0xa +#define CGTT_SC_CLK_CTRL4__PBB_BREAKING_CLK_STALL_OVERRIDE__SHIFT 0xb +#define CGTT_SC_CLK_CTRL4__PBB_PASSMEM_CLK_STALL_OVERRIDE__SHIFT 0xc +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE__SHIFT 0x13 +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE__SHIFT 0x14 +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE__SHIFT 0x15 +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE__SHIFT 0x16 +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE__SHIFT 0x17 +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL4__PBB_BREAKING_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL4__PBB_PASSMEM_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_STALL_OVERRIDE_MASK 0x00000001L +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_STALL_OVERRIDE_MASK 0x00000002L +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_STALL_OVERRIDE_MASK 0x00000004L +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_STALL_OVERRIDE_MASK 0x00000008L +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_STALL_OVERRIDE_MASK 0x00000010L +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_STALL_OVERRIDE_MASK 0x00000020L +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_STALL_OVERRIDE_MASK 0x00000040L +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_STALL_OVERRIDE_MASK 0x00000100L +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_STALL_OVERRIDE_MASK 0x00000200L +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_STALL_OVERRIDE_MASK 0x00000400L +#define CGTT_SC_CLK_CTRL4__PBB_BREAKING_CLK_STALL_OVERRIDE_MASK 0x00000800L +#define CGTT_SC_CLK_CTRL4__PBB_PASSMEM_CLK_STALL_OVERRIDE_MASK 0x00001000L +#define CGTT_SC_CLK_CTRL4__PBB_VCOARSE_CLK_OVERRIDE_MASK 0x00080000L +#define CGTT_SC_CLK_CTRL4__PBB_VDETAIL_CLK_OVERRIDE_MASK 0x00100000L +#define CGTT_SC_CLK_CTRL4__PBB_HRASTER_CLK_OVERRIDE_MASK 0x00200000L +#define CGTT_SC_CLK_CTRL4__PBB_HCONFIG_CLK_OVERRIDE_MASK 0x00400000L +#define CGTT_SC_CLK_CTRL4__PBB_HGATHER_CLK_OVERRIDE_MASK 0x00800000L +#define CGTT_SC_CLK_CTRL4__PBB_HCOARSE_CLK_OVERRIDE_MASK 0x01000000L +#define CGTT_SC_CLK_CTRL4__PBB_HDETAIL_CLK_OVERRIDE_MASK 0x02000000L +#define CGTT_SC_CLK_CTRL4__PBB_BATCHOUT_CLK_OVERRIDE_MASK 0x08000000L +#define CGTT_SC_CLK_CTRL4__PBB_OUTPUT_CLK_OVERRIDE_MASK 0x10000000L +#define CGTT_SC_CLK_CTRL4__PBB_OUTMUX_CLK_OVERRIDE_MASK 0x20000000L +#define CGTT_SC_CLK_CTRL4__PBB_BREAKING_CLK_OVERRIDE_MASK 0x40000000L +#define CGTT_SC_CLK_CTRL4__PBB_PASSMEM_CLK_OVERRIDE_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_gl1_pwrdec +//ICG_GL1C_CLK_CTRL +#define ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GL1C_CLK_CTRL__UTCL0_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x7 +#define ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x8 +#define ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x9 +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER0_CLK_OVERRIDE__SHIFT 0xa +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER1_CLK_OVERRIDE__SHIFT 0xb +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER2_CLK_OVERRIDE__SHIFT 0xc +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER3_CLK_OVERRIDE__SHIFT 0xd +#define ICG_GL1C_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GL1C_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GL1C_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GL1C_CLK_CTRL__VM_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GL1C_CLK_CTRL__UTCL0_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GL1C_CLK_CTRL__GCR_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_GL1C_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000040L +#define ICG_GL1C_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000080L +#define ICG_GL1C_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000100L +#define ICG_GL1C_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000200L +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER0_CLK_OVERRIDE_MASK 0x00000400L +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER1_CLK_OVERRIDE_MASK 0x00000800L +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER2_CLK_OVERRIDE_MASK 0x00001000L +#define ICG_GL1C_CLK_CTRL__LDB_TRACKER3_CLK_OVERRIDE_MASK 0x00002000L +//GL1I_GL1R_MGCG_OVERRIDE +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x0 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x2 +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000001L +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L +#define GL1I_GL1R_MGCG_OVERRIDE__GL1A_GL1IW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000004L +//GL1XI_GL1XR_MGCG_OVERRIDE +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIR_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x0 +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIW_MGCG_RET_DCLK_OVERRIDE__SHIFT 0x1 +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIW_MGCG_SRC_DCLK_OVERRIDE__SHIFT 0x2 +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIR_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000001L +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIW_MGCG_RET_DCLK_OVERRIDE_MASK 0x00000002L +#define GL1XI_GL1XR_MGCG_OVERRIDE__GL1XA_GL1XIW_MGCG_SRC_DCLK_OVERRIDE_MASK 0x00000004L +//ICG_GL1XC_CLK_CTRL +#define ICG_GL1XC_CLK_CTRL__GLOBAL_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GL1XC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GL1XC_CLK_CTRL__REQUEST_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GL1XC_CLK_CTRL__VM_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GL1XC_CLK_CTRL__UTCL0_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GL1XC_CLK_CTRL__GCR_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GL1XC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE__SHIFT 0x6 +#define ICG_GL1XC_CLK_CTRL__RETURN_CLK_OVERRIDE__SHIFT 0x7 +#define ICG_GL1XC_CLK_CTRL__GRBM_CLK_OVERRIDE__SHIFT 0x8 +#define ICG_GL1XC_CLK_CTRL__PERF_CLK_OVERRIDE__SHIFT 0x9 +#define ICG_GL1XC_CLK_CTRL__GLOBAL_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GL1XC_CLK_CTRL__GLOBAL_NONHARVESTABLE_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GL1XC_CLK_CTRL__REQUEST_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GL1XC_CLK_CTRL__VM_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GL1XC_CLK_CTRL__UTCL0_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GL1XC_CLK_CTRL__GCR_CLK_OVERRIDE_MASK 0x00000020L +#define ICG_GL1XC_CLK_CTRL__SRC_DATA_CLK_OVERRIDE_MASK 0x00000040L +#define ICG_GL1XC_CLK_CTRL__RETURN_CLK_OVERRIDE_MASK 0x00000080L +#define ICG_GL1XC_CLK_CTRL__GRBM_CLK_OVERRIDE_MASK 0x00000100L +#define ICG_GL1XC_CLK_CTRL__PERF_CLK_OVERRIDE_MASK 0x00000200L +//ICG_GL1A_CTRL +#define ICG_GL1A_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GL1A_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GL1A_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GL1A_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GL1A_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GL1A_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GL1A_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GL1A_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L +//ICG_GL1XA_CTRL +#define ICG_GL1XA_CTRL__REG_CLK_OVERRIDE__SHIFT 0x0 +#define ICG_GL1XA_CTRL__REQ_CLI_CLK_OVERRIDE__SHIFT 0x1 +#define ICG_GL1XA_CTRL__REQ_ARB_CLK_OVERRIDE__SHIFT 0x2 +#define ICG_GL1XA_CTRL__RET_CLK_OVERRIDE__SHIFT 0x3 +#define ICG_GL1XA_CTRL__REQ_CREDIT_CLK_OVERRIDE__SHIFT 0x4 +#define ICG_GL1XA_CTRL__PERFMON_CLK_OVERRIDE__SHIFT 0x5 +#define ICG_GL1XA_CTRL__REG_CLK_OVERRIDE_MASK 0x00000001L +#define ICG_GL1XA_CTRL__REQ_CLI_CLK_OVERRIDE_MASK 0x00000002L +#define ICG_GL1XA_CTRL__REQ_ARB_CLK_OVERRIDE_MASK 0x00000004L +#define ICG_GL1XA_CTRL__RET_CLK_OVERRIDE_MASK 0x00000008L +#define ICG_GL1XA_CTRL__REQ_CREDIT_CLK_OVERRIDE_MASK 0x00000010L +#define ICG_GL1XA_CTRL__PERFMON_CLK_OVERRIDE_MASK 0x00000020L + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_hypdec +//GL1_PIPE_STEER_LSB +#define GL1_PIPE_STEER_LSB__PIPE0__SHIFT 0x0 +#define GL1_PIPE_STEER_LSB__PIPE1__SHIFT 0x4 +#define GL1_PIPE_STEER_LSB__PIPE2__SHIFT 0x8 +#define GL1_PIPE_STEER_LSB__PIPE3__SHIFT 0xc +#define GL1_PIPE_STEER_LSB__PIPE4__SHIFT 0x10 +#define GL1_PIPE_STEER_LSB__PIPE5__SHIFT 0x14 +#define GL1_PIPE_STEER_LSB__PIPE6__SHIFT 0x18 +#define GL1_PIPE_STEER_LSB__PIPE7__SHIFT 0x1c +#define GL1_PIPE_STEER_LSB__PIPE0_MASK 0x0000000FL +#define GL1_PIPE_STEER_LSB__PIPE1_MASK 0x000000F0L +#define GL1_PIPE_STEER_LSB__PIPE2_MASK 0x00000F00L +#define GL1_PIPE_STEER_LSB__PIPE3_MASK 0x0000F000L +#define GL1_PIPE_STEER_LSB__PIPE4_MASK 0x000F0000L +#define GL1_PIPE_STEER_LSB__PIPE5_MASK 0x00F00000L +#define GL1_PIPE_STEER_LSB__PIPE6_MASK 0x0F000000L +#define GL1_PIPE_STEER_LSB__PIPE7_MASK 0xF0000000L +//GL1_PIPE_STEER_MSB +#define GL1_PIPE_STEER_MSB__PIPE8__SHIFT 0x0 +#define GL1_PIPE_STEER_MSB__PIPE9__SHIFT 0x4 +#define GL1_PIPE_STEER_MSB__PIPE10__SHIFT 0x8 +#define GL1_PIPE_STEER_MSB__PIPE11__SHIFT 0xc +#define GL1_PIPE_STEER_MSB__MODE__SHIFT 0x10 +#define GL1_PIPE_STEER_MSB__PIPE8_MASK 0x0000000FL +#define GL1_PIPE_STEER_MSB__PIPE9_MASK 0x000000F0L +#define GL1_PIPE_STEER_MSB__PIPE10_MASK 0x00000F00L +#define GL1_PIPE_STEER_MSB__PIPE11_MASK 0x0000F000L +#define GL1_PIPE_STEER_MSB__MODE_MASK 0x00010000L +//GL1_HASH_CFG +#define GL1_HASH_CFG__HASH_XOR_BIT0__SHIFT 0x0 +#define GL1_HASH_CFG__HASH_XOR_BIT1__SHIFT 0x6 +#define GL1_HASH_CFG__HASH_XOR_BIT2__SHIFT 0xc +#define GL1_HASH_CFG__CHANNEL_FLIP__SHIFT 0x12 +#define GL1_HASH_CFG__CHANNEL_HASH_EN__SHIFT 0x13 +#define GL1_HASH_CFG__RESERVED__SHIFT 0x14 +#define GL1_HASH_CFG__HASH_XOR_BIT0_MASK 0x0000003FL +#define GL1_HASH_CFG__HASH_XOR_BIT1_MASK 0x00000FC0L +#define GL1_HASH_CFG__HASH_XOR_BIT2_MASK 0x0003F000L +#define GL1_HASH_CFG__CHANNEL_FLIP_MASK 0x00040000L +#define GL1_HASH_CFG__CHANNEL_HASH_EN_MASK 0x00080000L +#define GL1_HASH_CFG__RESERVED_MASK 0xFFF00000L +//GC_USER_SHADER_ARRAY_CONFIG +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT 0x10 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK 0xFFFF0000L +//GC_USER_RB_BACKEND_DISABLE +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x4 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x000000F0L +//GC_USER_RMI_REDUNDANCY +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0__SHIFT 0x1 +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1__SHIFT 0x2 +#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE__SHIFT 0x3 +#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP__SHIFT 0x4 +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_0_MASK 0x00000002L +#define GC_USER_RMI_REDUNDANCY__REPAIR_EN_IN_1_MASK 0x00000004L +#define GC_USER_RMI_REDUNDANCY__REPAIR_RMI_OVERRIDE_MASK 0x00000008L +#define GC_USER_RMI_REDUNDANCY__REPAIR_ID_SWAP_MASK 0x00000010L +//GC_USER_SHADER_RATE_CONFIG_1 +#define GC_USER_SHADER_RATE_CONFIG_1__SHADER_RATE__SHIFT 0x1 +#define GC_USER_SHADER_RATE_CONFIG_1__SHADER_RATE_MASK 0x000007FEL + + +// addressBlock: CHIP_XCD_gfxip_xcc_gfx_se_gfx_se_grbmh_hypdec +//GRBMH_WGP_SA0_REMAP_CNTL +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP0_SA0_REMAP_EN__SHIFT 0x0 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP1_SA0_REMAP_EN__SHIFT 0x1 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP2_SA0_REMAP_EN__SHIFT 0x2 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP3_SA0_REMAP_EN__SHIFT 0x3 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP4_SA0_REMAP_EN__SHIFT 0x4 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP5_SA0_REMAP_EN__SHIFT 0x5 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP6_SA0_REMAP_EN__SHIFT 0x6 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP7_SA0_REMAP_EN__SHIFT 0x7 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP8_SA0_REMAP_EN__SHIFT 0x8 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP9_SA0_REMAP_EN__SHIFT 0x9 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP10_SA0_REMAP_EN__SHIFT 0xa +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_SA0_REMAP_TO_SIDE__SHIFT 0xb +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_SA0_REMAP_TO_WGP__SHIFT 0xc +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP0_SA0_REMAP_EN__SHIFT 0x10 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP1_SA0_REMAP_EN__SHIFT 0x11 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP2_SA0_REMAP_EN__SHIFT 0x12 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP3_SA0_REMAP_EN__SHIFT 0x13 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP4_SA0_REMAP_EN__SHIFT 0x14 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP5_SA0_REMAP_EN__SHIFT 0x15 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP6_SA0_REMAP_EN__SHIFT 0x16 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP7_SA0_REMAP_EN__SHIFT 0x17 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP8_SA0_REMAP_EN__SHIFT 0x18 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP9_SA0_REMAP_EN__SHIFT 0x19 +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP10_SA0_REMAP_EN__SHIFT 0x1a +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_SA0_REMAP_TO_SIDE__SHIFT 0x1b +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_SA0_REMAP_TO_WGP__SHIFT 0x1c +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP0_SA0_REMAP_EN_MASK 0x00000001L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP1_SA0_REMAP_EN_MASK 0x00000002L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP2_SA0_REMAP_EN_MASK 0x00000004L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP3_SA0_REMAP_EN_MASK 0x00000008L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP4_SA0_REMAP_EN_MASK 0x00000010L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP5_SA0_REMAP_EN_MASK 0x00000020L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP6_SA0_REMAP_EN_MASK 0x00000040L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP7_SA0_REMAP_EN_MASK 0x00000080L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP8_SA0_REMAP_EN_MASK 0x00000100L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP9_SA0_REMAP_EN_MASK 0x00000200L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_WGP10_SA0_REMAP_EN_MASK 0x00000400L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_SA0_REMAP_TO_SIDE_MASK 0x00000800L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE0_SA0_REMAP_TO_WGP_MASK 0x0000F000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP0_SA0_REMAP_EN_MASK 0x00010000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP1_SA0_REMAP_EN_MASK 0x00020000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP2_SA0_REMAP_EN_MASK 0x00040000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP3_SA0_REMAP_EN_MASK 0x00080000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP4_SA0_REMAP_EN_MASK 0x00100000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP5_SA0_REMAP_EN_MASK 0x00200000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP6_SA0_REMAP_EN_MASK 0x00400000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP7_SA0_REMAP_EN_MASK 0x00800000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP8_SA0_REMAP_EN_MASK 0x01000000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP9_SA0_REMAP_EN_MASK 0x02000000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_WGP10_SA0_REMAP_EN_MASK 0x04000000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_SA0_REMAP_TO_SIDE_MASK 0x08000000L +#define GRBMH_WGP_SA0_REMAP_CNTL__SIDE1_SA0_REMAP_TO_WGP_MASK 0xF0000000L +//GRBMH_WGP_SA1_REMAP_CNTL +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP0_SA1_REMAP_EN__SHIFT 0x0 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP1_SA1_REMAP_EN__SHIFT 0x1 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP2_SA1_REMAP_EN__SHIFT 0x2 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP3_SA1_REMAP_EN__SHIFT 0x3 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP4_SA1_REMAP_EN__SHIFT 0x4 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP5_SA1_REMAP_EN__SHIFT 0x5 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP6_SA1_REMAP_EN__SHIFT 0x6 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP7_SA1_REMAP_EN__SHIFT 0x7 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP8_SA1_REMAP_EN__SHIFT 0x8 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP9_SA1_REMAP_EN__SHIFT 0x9 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP10_SA1_REMAP_EN__SHIFT 0xa +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_SA1_REMAP_TO_SIDE__SHIFT 0xb +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_SA1_REMAP_TO_WGP__SHIFT 0xc +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP0_SA1_REMAP_EN__SHIFT 0x10 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP1_SA1_REMAP_EN__SHIFT 0x11 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP2_SA1_REMAP_EN__SHIFT 0x12 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP3_SA1_REMAP_EN__SHIFT 0x13 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP4_SA1_REMAP_EN__SHIFT 0x14 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP5_SA1_REMAP_EN__SHIFT 0x15 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP6_SA1_REMAP_EN__SHIFT 0x16 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP7_SA1_REMAP_EN__SHIFT 0x17 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP8_SA1_REMAP_EN__SHIFT 0x18 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP9_SA1_REMAP_EN__SHIFT 0x19 +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP10_SA1_REMAP_EN__SHIFT 0x1a +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_SA1_REMAP_TO_SIDE__SHIFT 0x1b +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_SA1_REMAP_TO_WGP__SHIFT 0x1c +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP0_SA1_REMAP_EN_MASK 0x00000001L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP1_SA1_REMAP_EN_MASK 0x00000002L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP2_SA1_REMAP_EN_MASK 0x00000004L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP3_SA1_REMAP_EN_MASK 0x00000008L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP4_SA1_REMAP_EN_MASK 0x00000010L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP5_SA1_REMAP_EN_MASK 0x00000020L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP6_SA1_REMAP_EN_MASK 0x00000040L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP7_SA1_REMAP_EN_MASK 0x00000080L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP8_SA1_REMAP_EN_MASK 0x00000100L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP9_SA1_REMAP_EN_MASK 0x00000200L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_WGP10_SA1_REMAP_EN_MASK 0x00000400L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_SA1_REMAP_TO_SIDE_MASK 0x00000800L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE0_SA1_REMAP_TO_WGP_MASK 0x0000F000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP0_SA1_REMAP_EN_MASK 0x00010000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP1_SA1_REMAP_EN_MASK 0x00020000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP2_SA1_REMAP_EN_MASK 0x00040000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP3_SA1_REMAP_EN_MASK 0x00080000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP4_SA1_REMAP_EN_MASK 0x00100000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP5_SA1_REMAP_EN_MASK 0x00200000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP6_SA1_REMAP_EN_MASK 0x00400000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP7_SA1_REMAP_EN_MASK 0x00800000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP8_SA1_REMAP_EN_MASK 0x01000000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP9_SA1_REMAP_EN_MASK 0x02000000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_WGP10_SA1_REMAP_EN_MASK 0x04000000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_SA1_REMAP_TO_SIDE_MASK 0x08000000L +#define GRBMH_WGP_SA1_REMAP_CNTL__SIDE1_SA1_REMAP_TO_WGP_MASK 0xF0000000L +//GRBMH_RB_SA0_REMAP_CNTL +#define GRBMH_RB_SA0_REMAP_CNTL__RB0_REMAP_EN__SHIFT 0x0 +#define GRBMH_RB_SA0_REMAP_CNTL__RB0_REMAP__SHIFT 0x1 +#define GRBMH_RB_SA0_REMAP_CNTL__RB1_REMAP_EN__SHIFT 0x4 +#define GRBMH_RB_SA0_REMAP_CNTL__RB1_REMAP__SHIFT 0x5 +#define GRBMH_RB_SA0_REMAP_CNTL__RB2_REMAP_EN__SHIFT 0x8 +#define GRBMH_RB_SA0_REMAP_CNTL__RB2_REMAP__SHIFT 0x9 +#define GRBMH_RB_SA0_REMAP_CNTL__RB3_REMAP_EN__SHIFT 0xc +#define GRBMH_RB_SA0_REMAP_CNTL__RB3_REMAP__SHIFT 0xd +#define GRBMH_RB_SA0_REMAP_CNTL__RB0_REMAP_EN_MASK 0x00000001L +#define GRBMH_RB_SA0_REMAP_CNTL__RB0_REMAP_MASK 0x0000000EL +#define GRBMH_RB_SA0_REMAP_CNTL__RB1_REMAP_EN_MASK 0x00000010L +#define GRBMH_RB_SA0_REMAP_CNTL__RB1_REMAP_MASK 0x000000E0L +#define GRBMH_RB_SA0_REMAP_CNTL__RB2_REMAP_EN_MASK 0x00000100L +#define GRBMH_RB_SA0_REMAP_CNTL__RB2_REMAP_MASK 0x00000E00L +#define GRBMH_RB_SA0_REMAP_CNTL__RB3_REMAP_EN_MASK 0x00001000L +#define GRBMH_RB_SA0_REMAP_CNTL__RB3_REMAP_MASK 0x0000E000L +//GRBMH_RB_SA1_REMAP_CNTL +#define GRBMH_RB_SA1_REMAP_CNTL__RB0_REMAP_EN__SHIFT 0x0 +#define GRBMH_RB_SA1_REMAP_CNTL__RB0_REMAP__SHIFT 0x1 +#define GRBMH_RB_SA1_REMAP_CNTL__RB1_REMAP_EN__SHIFT 0x4 +#define GRBMH_RB_SA1_REMAP_CNTL__RB1_REMAP__SHIFT 0x5 +#define GRBMH_RB_SA1_REMAP_CNTL__RB2_REMAP_EN__SHIFT 0x8 +#define GRBMH_RB_SA1_REMAP_CNTL__RB2_REMAP__SHIFT 0x9 +#define GRBMH_RB_SA1_REMAP_CNTL__RB3_REMAP_EN__SHIFT 0xc +#define GRBMH_RB_SA1_REMAP_CNTL__RB3_REMAP__SHIFT 0xd +#define GRBMH_RB_SA1_REMAP_CNTL__RB0_REMAP_EN_MASK 0x00000001L +#define GRBMH_RB_SA1_REMAP_CNTL__RB0_REMAP_MASK 0x0000000EL +#define GRBMH_RB_SA1_REMAP_CNTL__RB1_REMAP_EN_MASK 0x00000010L +#define GRBMH_RB_SA1_REMAP_CNTL__RB1_REMAP_MASK 0x000000E0L +#define GRBMH_RB_SA1_REMAP_CNTL__RB2_REMAP_EN_MASK 0x00000100L +#define GRBMH_RB_SA1_REMAP_CNTL__RB2_REMAP_MASK 0x00000E00L +#define GRBMH_RB_SA1_REMAP_CNTL__RB3_REMAP_EN_MASK 0x00001000L +#define GRBMH_RB_SA1_REMAP_CNTL__RB3_REMAP_MASK 0x0000E000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedpfdec +//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL +//GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x000000FFL +//GCUTCL2_ICG_CTRL +#define GCUTCL2_ICG_CTRL__OFF_HYSTERESIS__SHIFT 0x0 +#define GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT 0x4 +#define GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT 0x5 +#define GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT 0x6 +#define GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT 0x7 +#define GCUTCL2_ICG_CTRL__OFF_HYSTERESIS_MASK 0x0000000FL +#define GCUTCL2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK 0x00000010L +#define GCUTCL2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK 0x00000020L +#define GCUTCL2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK 0x00000040L +#define GCUTCL2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK 0x00000080L +//GCMC_SHARED_ACTIVE_FCN_ID +#define GCMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +#define GCMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f +#define GCMC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000001FL +#define GCMC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L +//GCUTCL2_CGTT_BUSY_CTRL +#define GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define GCUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define GCUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//GCUTCL2_GROUP_RET_FAULT_STATUS +#define GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT 0x0 +#define GCUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pfdec +//GCVM_L2_CNTL +#define GCVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 +#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 +#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 +#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 +#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 +#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 +#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa +#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb +#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc +#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf +#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 +#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 +#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 +#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a +#define GCVM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L +#define GCVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L +#define GCVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL +#define GCVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L +#define GCVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L +#define GCVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L +#define GCVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L +#define GCVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L +#define GCVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L +#define GCVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L +#define GCVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L +#define GCVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L +#define GCVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L +#define GCVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L +//GCVM_L2_CNTL2 +#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 +#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 +#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 +#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 +#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 +#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a +#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c +#define GCVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L +#define GCVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L +#define GCVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L +#define GCVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L +#define GCVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L +#define GCVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L +#define GCVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L +//GCVM_L2_CNTL3 +#define GCVM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 +#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 +#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d +#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e +#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f +#define GCVM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L +#define GCVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L +#define GCVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L +#define GCVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L +#define GCVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L +#define GCVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L +#define GCVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L +//GCVM_L2_STATUS +#define GCVM_L2_STATUS__L2_BUSY__SHIFT 0x0 +#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 +#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 +#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 +#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 +#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 +#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 +#define GCVM_L2_STATUS__FOUND_PDE3_CACHE_PARITY_ERRORS__SHIFT 0x16 +#define GCVM_L2_STATUS__L2_BUSY_MASK 0x00000001L +#define GCVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL +#define GCVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L +#define GCVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L +#define GCVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L +#define GCVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L +#define GCVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L +#define GCVM_L2_STATUS__FOUND_PDE3_CACHE_PARITY_ERRORS_MASK 0x00400000L +//GCVM_DUMMY_PAGE_FAULT_CNTL +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L +#define GCVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL +//GCVM_DUMMY_PAGE_FAULT_ADDR_LO32 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//GCVM_DUMMY_PAGE_FAULT_ADDR_HI32 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI13__SHIFT 0x0 +#define GCVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI13_MASK 0x00001FFFL +//GCVM_INVALIDATE_CNTL +#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT 0x0 +#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT 0x8 +#define GCVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK 0x000000FFL +#define GCVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK 0x0000FF00L +//GCVM_L2_PROTECTION_FAULT_CNTL_LO32 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE3_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xe +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1e +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1f +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__PDE3_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x3FFFC000L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x40000000L +#define GCVM_L2_PROTECTION_FAULT_CNTL_LO32__CRASH_ON_NO_RETRY_FAULT_MASK 0x80000000L +//GCVM_L2_PROTECTION_FAULT_CNTL_HI32 +#define GCVM_L2_PROTECTION_FAULT_CNTL_HI32__CRASH_ON_RETRY_FAULT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_CNTL_HI32__CRASH_ON_RETRY_FAULT_MASK 0x00000001L +//GCVM_L2_PROTECTION_FAULT_CNTL2 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 +#define GCVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL +#define GCVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L +#define GCVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L +//GCVM_L2_PROTECTION_FAULT_MM_CNTL3 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_MM_CNTL4 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_STATUS_LO32 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__MORE_FAULTS__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__WALKER_ERROR__SHIFT 0x1 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__PERMISSION_FAULTS__SHIFT 0x5 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__MAPPING_ERROR__SHIFT 0xa +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__CID__SHIFT 0xb +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__RW__SHIFT 0x14 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__ATOMIC__SHIFT 0x15 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VMID__SHIFT 0x16 +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VF__SHIFT 0x1a +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VFID__SHIFT 0x1b +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__MORE_FAULTS_MASK 0x00000001L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__WALKER_ERROR_MASK 0x0000001EL +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__PERMISSION_FAULTS_MASK 0x000003E0L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__MAPPING_ERROR_MASK 0x00000400L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__CID_MASK 0x000FF800L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__RW_MASK 0x00100000L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__ATOMIC_MASK 0x00200000L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VMID_MASK 0x03C00000L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VF_MASK 0x04000000L +#define GCVM_L2_PROTECTION_FAULT_STATUS_LO32__VFID_MASK 0xF8000000L +//GCVM_L2_PROTECTION_FAULT_STATUS_HI32 +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__PRT__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__UCE__SHIFT 0x1 +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__FED__SHIFT 0x2 +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__PRT_MASK 0x00000001L +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__UCE_MASK 0x00000002L +#define GCVM_L2_PROTECTION_FAULT_STATUS_HI32__FED_MASK 0x00000004L +//GCVM_L2_PROTECTION_FAULT_ADDR_LO32 +#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_ADDR_HI32 +#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI13__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI13_MASK 0x00001FFFL +//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI8__SHIFT 0x0 +#define GCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI8_MASK 0x000000FFL +//GCVM_DEBUG +#define GCVM_DEBUG__FLAGS__SHIFT 0x0 +#define GCVM_DEBUG__FLAGS_MASK 0xFFFFFFFFL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL +//GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI8__SHIFT 0x0 +#define GCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI8_MASK 0x000000FFL +//GCVM_L2_CNTL4 +#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 +#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 +#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 +#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 +#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 +#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c +#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d +#define GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e +#define GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT 0x1f +#define GCVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL +#define GCVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L +#define GCVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L +#define GCVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L +#define GCVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L +#define GCVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L +#define GCVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L +#define GCVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L +#define GCVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK 0x80000000L +//GCVM_L2_MM_GROUP_RT_CLASSES +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L +#define GCVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L +//GCVM_L2_BANK_SELECT_RESERVED_CID +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//GCVM_L2_BANK_SELECT_RESERVED_CID2 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT 0x1a +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L +#define GCVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK 0x7C000000L +//GCVM_L2_CACHE_PARITY_CNTL +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L +#define GCVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L +#define GCVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L +//GCVM_L2_ICG_CTRL +#define GCVM_L2_ICG_CTRL__OFF_HYSTERESIS__SHIFT 0x0 +#define GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT 0x4 +#define GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT 0x5 +#define GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT 0x6 +#define GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT 0x7 +#define GCVM_L2_ICG_CTRL__OFF_HYSTERESIS_MASK 0x0000000FL +#define GCVM_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK 0x00000010L +#define GCVM_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK 0x00000020L +#define GCVM_L2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK 0x00000040L +#define GCVM_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK 0x00000080L +//GCVM_L2_CNTL5 +#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT 0x5 +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT 0xe +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT 0xf +#define GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT 0x10 +#define GCVM_L2_CNTL5__UTCL2_ATC_INVREQ_REPEATER_FGCG_OFF__SHIFT 0x11 +#define GCVM_L2_CNTL5__UTCL2_ONE_OUTSTANDING_ATC_INVREQ__SHIFT 0x12 +#define GCVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK 0x00003FE0L +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK 0x00004000L +#define GCVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK 0x00008000L +#define GCVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK 0x00010000L +#define GCVM_L2_CNTL5__UTCL2_ATC_INVREQ_REPEATER_FGCG_OFF_MASK 0x00020000L +#define GCVM_L2_CNTL5__UTCL2_ONE_OUTSTANDING_ATC_INVREQ_MASK 0x00040000L +//GCVM_L2_GCR_CNTL +#define GCVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT 0x0 +#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT 0x1 +#define GCVM_L2_GCR_CNTL__GCR_ENABLE_MASK 0x00000001L +#define GCVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK 0x000003FEL +//GCVML2_WALKER_MACRO_THROTTLE_TIME +#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME__SHIFT 0x0 +#define GCVML2_WALKER_MACRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL +//GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT +#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 +#define GCVML2_WALKER_MACRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL +//GCVML2_WALKER_MICRO_THROTTLE_TIME +#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME__SHIFT 0x0 +#define GCVML2_WALKER_MICRO_THROTTLE_TIME__TIME_MASK 0x00FFFFFFL +//GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT +#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT__SHIFT 0x1 +#define GCVML2_WALKER_MICRO_THROTTLE_FETCH_LIMIT__LIMIT_MASK 0x0000FFFEL +//GCVM_L2_CGTT_BUSY_CTRL +#define GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 +#define GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x5 +#define GCVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000001FL +#define GCVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000020L +//GCVM_L2_PTE_CACHE_DUMP_CNTL +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT 0x0 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT 0x1 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT 0x4 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT 0x8 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT 0xc +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT 0x10 +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK 0x00000001L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK 0x00000002L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK 0x000000F0L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK 0x00000F00L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK 0x0000F000L +#define GCVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK 0xFFFF0000L +//GCVM_L2_PTE_CACHE_DUMP_READ +#define GCVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT 0x0 +#define GCVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK 0xFFFFFFFFL +//GCVML2_MAIN_DEBUG +#define GCVML2_MAIN_DEBUG__FLAGS__SHIFT 0x0 +#define GCVML2_MAIN_DEBUG__FLAGS_MASK 0xFFFFFFFFL +//GCVML2_WALKER_DEBUG +#define GCVML2_WALKER_DEBUG__FLAGS__SHIFT 0x0 +#define GCVML2_WALKER_DEBUG__FLAGS_MASK 0xFFFFFFFFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32__ADDR_LO32__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_LO32__ADDR_LO32_MASK 0xFFFFFFFFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32__ADDR_HI13__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ADDR_HI32__ADDR_HI13_MASK 0x00001FFFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VMID__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VFID__SHIFT 0x4 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VF__SHIFT 0x9 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__GPA__SHIFT 0xa +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__RD_PERM__SHIFT 0xc +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__WR_PERM__SHIFT 0xd +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__EX_PERM__SHIFT 0xe +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__AT_PERM__SHIFT 0xf +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__CLIENT_ID__SHIFT 0x10 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__REQ__SHIFT 0x1f +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VMID_MASK 0x0000000FL +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VFID_MASK 0x000001F0L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__VF_MASK 0x00000200L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__GPA_MASK 0x00000C00L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__RD_PERM_MASK 0x00001000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__WR_PERM_MASK 0x00002000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__EX_PERM_MASK 0x00004000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__AT_PERM_MASK 0x00008000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__CLIENT_ID_MASK 0x01FF0000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_ATTR__REQ_MASK 0x80000000L +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32__ADDR_LO32__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_LO32__ADDR_LO32_MASK 0xFFFFFFFFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32__ADDR_HI8__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ADDR_HI32__ADDR_HI8_MASK 0x000000FFL +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__PERMS__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__FRAGMENT_SIZE__SHIFT 0x4 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__SNOOP__SHIFT 0xa +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__SPA__SHIFT 0xb +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__IO__SHIFT 0xc +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__PTE_TMZ__SHIFT 0xd +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__NO_PTE__SHIFT 0xe +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__MTYPE__SHIFT 0xf +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__COMP_EN__SHIFT 0x11 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__NACK__SHIFT 0x12 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__HDM__SHIFT 0x14 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__TMPM_RETRY__SHIFT 0x15 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__ACK__SHIFT 0x1f +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__PERMS_MASK 0x0000000FL +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__FRAGMENT_SIZE_MASK 0x000003F0L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__SNOOP_MASK 0x00000400L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__SPA_MASK 0x00000800L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__IO_MASK 0x00001000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__PTE_TMZ_MASK 0x00002000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__NO_PTE_MASK 0x00004000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__MTYPE_MASK 0x00018000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__COMP_EN_MASK 0x00020000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__NACK_MASK 0x000C0000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__HDM_MASK 0x00100000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__TMPM_RETRY_MASK 0x00200000L +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_ATTR__ACK_MASK 0x80000000L +//GCVM_L2_BANK_SELECT_MASKS +#define GCVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 +#define GCVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 +#define GCVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 +#define GCVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT 0xc +#define GCVM_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL +#define GCVM_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L +#define GCVM_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L +#define GCVM_L2_BANK_SELECT_MASKS__MASK3_MASK 0x0000F000L +//GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT 0x0 +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT 0xa +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK 0x000003FFL +#define GCUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK 0x00000400L +//GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT 0x0 +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT 0xa +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK 0x000003FFL +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK 0x00000400L +//GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT 0x0 +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT 0xa +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK 0x000003FFL +#define GCUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK 0x00000400L +//GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT 0x0 +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT 0xa +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK 0x000003FFL +#define GCVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK 0x00000400L +//GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT 0xa +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define GCVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK 0x00000400L +//GCVM_L2_UTCL2_FED_VMID_STS +#define GCVM_L2_UTCL2_FED_VMID_STS__VMIDS__SHIFT 0x0 +#define GCVM_L2_UTCL2_FED_VMID_STS__VMIDS_MASK 0x0000FFFFL +//GCVM_L2_UTCL2_FED_ACK_REG +#define GCVM_L2_UTCL2_FED_ACK_REG__VMIDS__SHIFT 0x0 +#define GCVM_L2_UTCL2_FED_ACK_REG__VMIDS_MASK 0x0000FFFFL +//GCVML2_IH_FAULT_INTERRUPT_CNTL +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_PF_POISON_INTERRUPT__SHIFT 0x0 +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_VF_POISON_INTERRUPT__SHIFT 0x1 +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__POISON_INTERRUPT_TO_PF__SHIFT 0x2 +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_PF_POISON_INTERRUPT_MASK 0x00000001L +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__ENABLE_VF_POISON_INTERRUPT_MASK 0x00000002L +#define GCVML2_IH_FAULT_INTERRUPT_CNTL__POISON_INTERRUPT_TO_PF_MASK 0x00000004L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpfdec +//GC_L2TLB_TLB0_STATUS +#define GC_L2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 +#define GC_L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 +#define GC_L2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L +#define GC_L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L +//GC_L2TLB_TLB0_RETRY_CNTL +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_COUNT__SHIFT 0x0 +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_TIMER__SHIFT 0x10 +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_ENABLE__SHIFT 0x15 +#define GC_L2TLB_TLB0_RETRY_CNTL__NON_TMPM_RETRY_ENABLE__SHIFT 0x16 +#define GC_L2TLB_TLB0_RETRY_CNTL__TMPM_RETRY_ENABLE__SHIFT 0x17 +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_COUNT_MASK 0x0000FFFFL +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_TIMER_MASK 0x001F0000L +#define GC_L2TLB_TLB0_RETRY_CNTL__RETRY_ENABLE_MASK 0x00200000L +#define GC_L2TLB_TLB0_RETRY_CNTL__NON_TMPM_RETRY_ENABLE_MASK 0x00400000L +#define GC_L2TLB_TLB0_RETRY_CNTL__TMPM_RETRY_ENABLE_MASK 0x00800000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedvcdec +//GCMC_VM_FB_LOCATION_BASE_LO32 +#define GCMC_VM_FB_LOCATION_BASE_LO32__FB_BASE_LO32__SHIFT 0x0 +#define GCMC_VM_FB_LOCATION_BASE_LO32__FB_BASE_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_FB_LOCATION_BASE_HI32 +#define GCMC_VM_FB_LOCATION_BASE_HI32__FB_BASE_HI1__SHIFT 0x0 +#define GCMC_VM_FB_LOCATION_BASE_HI32__FB_BASE_HI1_MASK 0x00000001L +//GCMC_VM_FB_LOCATION_TOP_LO32 +#define GCMC_VM_FB_LOCATION_TOP_LO32__FB_TOP_LO32__SHIFT 0x0 +#define GCMC_VM_FB_LOCATION_TOP_LO32__FB_TOP_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_FB_LOCATION_TOP_HI32 +#define GCMC_VM_FB_LOCATION_TOP_HI32__FB_TOP_HI1__SHIFT 0x0 +#define GCMC_VM_FB_LOCATION_TOP_HI32__FB_TOP_HI1_MASK 0x00000001L +//GCMC_VM_AGP_TOP_LO32 +#define GCMC_VM_AGP_TOP_LO32__AGP_TOP_LO32__SHIFT 0x0 +#define GCMC_VM_AGP_TOP_LO32__AGP_TOP_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_AGP_TOP_HI32 +#define GCMC_VM_AGP_TOP_HI32__AGP_TOP_HI1__SHIFT 0x0 +#define GCMC_VM_AGP_TOP_HI32__AGP_TOP_HI1_MASK 0x00000001L +//GCMC_VM_AGP_BOT_LO32 +#define GCMC_VM_AGP_BOT_LO32__AGP_BOT_LO32__SHIFT 0x0 +#define GCMC_VM_AGP_BOT_LO32__AGP_BOT_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_AGP_BOT_HI32 +#define GCMC_VM_AGP_BOT_HI32__AGP_BOT_HI1__SHIFT 0x0 +#define GCMC_VM_AGP_BOT_HI32__AGP_BOT_HI1_MASK 0x00000001L +//GCMC_VM_AGP_BASE_LO32 +#define GCMC_VM_AGP_BASE_LO32__AGP_BASE_LO32__SHIFT 0x0 +#define GCMC_VM_AGP_BASE_LO32__AGP_BASE_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_AGP_BASE_HI32 +#define GCMC_VM_AGP_BASE_HI32__AGP_BASE_HI1__SHIFT 0x0 +#define GCMC_VM_AGP_BASE_HI32__AGP_BASE_HI1_MASK 0x00000001L +//GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32 +#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32__LOGICAL_ADDR_LO32__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32__LOGICAL_ADDR_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32 +#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32__LOGICAL_ADDR_HI7__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32__LOGICAL_ADDR_HI7_MASK 0x0000007FL +//GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32 +#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32__LOGICAL_ADDR_LO32__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32__LOGICAL_ADDR_LO32_MASK 0xFFFFFFFFL +//GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32 +#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32__LOGICAL_ADDR_HI7__SHIFT 0x0 +#define GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32__LOGICAL_ADDR_HI7_MASK 0x0000007FL +//GCMC_VM_MX_L1_TLB_CNTL +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 +#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 +#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L +#define GCMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L +#define GCMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L +#define GCMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L +#define GCMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2vcdec +//GCVM_CONTEXT0_CNTL +#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT1_CNTL +#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT2_CNTL +#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT3_CNTL +#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT4_CNTL +#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT5_CNTL +#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT6_CNTL +#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT7_CNTL +#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT8_CNTL +#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT9_CNTL +#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT10_CNTL +#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT11_CNTL +#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT12_CNTL +#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT13_CNTL +#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT14_CNTL +#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXT15_CNTL +#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x4 +#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x8 +#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x9 +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xa +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xe +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xf +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x10 +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x11 +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x14 +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x15 +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x16 +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x17 +#define GCVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x0000000EL +#define GCVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x000000F0L +#define GCVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000100L +#define GCVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000200L +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000400L +#define GCVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L +#define GCVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00004000L +#define GCVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00008000L +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00010000L +#define GCVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00020000L +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L +#define GCVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00100000L +#define GCVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00200000L +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00400000L +#define GCVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00800000L +//GCVM_CONTEXTS_DISABLE +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L +#define GCVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L +//GCVM_INVALIDATE_ENG0_SEM +#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG1_SEM +#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG2_SEM +#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG3_SEM +#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG4_SEM +#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG5_SEM +#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG6_SEM +#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG7_SEM +#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG8_SEM +#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG9_SEM +#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG10_SEM +#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG11_SEM +#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG12_SEM +#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG13_SEM +#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG14_SEM +#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG15_SEM +#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG16_SEM +#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG17_SEM +#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L +//GCVM_INVALIDATE_ENG0_REQ +#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG1_REQ +#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG2_REQ +#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG3_REQ +#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG4_REQ +#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG5_REQ +#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG6_REQ +#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG7_REQ +#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG8_REQ +#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG9_REQ +#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG10_REQ +#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG11_REQ +#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG12_REQ +#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG13_REQ +#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG14_REQ +#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG15_REQ +#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG16_REQ +#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG17_REQ +#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x13 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x14 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x15 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x16 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x17 +#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x18 +#define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x19 +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT 0x1a +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE3__SHIFT 0x1b +#define GCVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00070000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00080000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00100000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00200000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00400000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00800000L +#define GCVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x01000000L +#define GCVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x02000000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK 0x04000000L +#define GCVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE3_MASK 0x08000000L +//GCVM_INVALIDATE_ENG0_ACK +#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG1_ACK +#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG2_ACK +#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG3_ACK +#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG4_ACK +#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG5_ACK +#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG6_ACK +#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG7_ACK +#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG8_ACK +#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG9_ACK +#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG10_ACK +#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG11_ACK +#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG12_ACK +#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG13_ACK +#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG14_ACK +#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG15_ACK +#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG16_ACK +#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG17_ACK +#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 +#define GCVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL +#define GCVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L +//GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL +//GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14__SHIFT 0x0 +#define GCVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI14_MASK 0x00003FFFL +//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL +//GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13__SHIFT 0x0 +#define GCVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI13_MASK 0x00001FFFL +//GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L +//GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0x5 +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT 0xa +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK 0x0000001FL +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000003E0L +#define GCVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK 0x0000FC00L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedvfdec +//GCMC_VM_PCIE_ATOMIC_SUPPORTED +#define GCMC_VM_PCIE_ATOMIC_SUPPORTED__PCIE_ATOMIC_SUPPORTED__SHIFT 0x0 +#define GCMC_VM_PCIE_ATOMIC_SUPPORTED__PCIE_ATOMIC_SUPPORTED_MASK 0x00000001L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbvfdec +//GC_L2TLB_TLB0_EN_RETRY_ON_ATOMIC +#define GC_L2TLB_TLB0_EN_RETRY_ON_ATOMIC__EN_RETRY_ON_ATOMIC__SHIFT 0x0 +#define GC_L2TLB_TLB0_EN_RETRY_ON_ATOMIC__EN_RETRY_ON_ATOMIC_MASK 0x00000001L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2prdec +//GCMC_VM_L2_PERFCOUNTER_LO +#define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCMC_VM_L2_PERFCOUNTER_HI +#define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L +//GCUTCL2_PERFCOUNTER_LO +#define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GCUTCL2_PERFCOUNTER_HI +#define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GCUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GCUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2prdec +//GC_ATC_L2_PERFCOUNTER_LO +#define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GC_ATC_L2_PERFCOUNTER_HI +#define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GC_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbprdec +//GC_L2TLB_PERFCOUNTER_LO +#define GC_L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL +//GC_L2TLB_PERFCOUNTER_HI +#define GC_L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 +#define GC_L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL +#define GC_L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pldec +//GCMC_VM_L2_PERFCOUNTER0_CFG +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER1_CFG +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER2_CFG +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER3_CFG +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER4_CFG +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER5_CFG +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER6_CFG +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER7_CFG +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER8_CFG +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER8_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER8_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER8_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER8_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER8_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER9_CFG +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER9_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER9_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER9_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER9_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER9_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER10_CFG +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER10_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER10_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER10_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER10_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER10_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER11_CFG +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER11_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER11_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER11_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER11_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER11_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER12_CFG +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER12_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER12_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER12_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER12_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER12_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER13_CFG +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER13_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER13_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER13_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER13_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER13_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER14_CFG +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER14_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER14_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER14_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER14_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER14_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER15_CFG +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_MODE__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER15_CFG__ENABLE__SHIFT 0x1c +#define GCMC_VM_L2_PERFCOUNTER15_CFG__CLEAR__SHIFT 0x1d +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL_MASK 0x000000FFL +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER15_CFG__PERF_MODE_MASK 0x0F000000L +#define GCMC_VM_L2_PERFCOUNTER15_CFG__ENABLE_MASK 0x10000000L +#define GCMC_VM_L2_PERFCOUNTER15_CFG__CLEAR_MASK 0x20000000L +//GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//GCUTCL2_PERFCOUNTER0_CFG +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER1_CFG +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER2_CFG +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER3_CFG +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GCUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GCUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GCUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GCUTCL2_PERFCOUNTER_RSLT_CNTL +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GCUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//GCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT +#define GCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT__SET0_GROUP__SHIFT 0x0 +#define GCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT__SET1_GROUP__SHIFT 0x8 +#define GCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT__SET0_GROUP_MASK 0x000000FFL +#define GCUTCL2_PERFCOUNTER_EVENTS_GROUP_SELECT__SET1_GROUP_MASK 0x0000FF00L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2pldec +//GC_ATC_L2_PERFCOUNTER0_CFG +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER1_CFG +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER2_CFG +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER3_CFG +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER4_CFG +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER5_CFG +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER6_CFG +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER7_CFG +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER8_CFG +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER8_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER8_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER8_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER8_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER8_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER9_CFG +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER9_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER9_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER9_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER9_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER9_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER10_CFG +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER10_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER10_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER10_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER10_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER10_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER11_CFG +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER11_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER11_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER11_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER11_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER11_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER12_CFG +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER12_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER12_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER12_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER12_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER12_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER13_CFG +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER13_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER13_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER13_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER13_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER13_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER14_CFG +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER14_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER14_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER14_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER14_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER14_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER15_CFG +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_SEL__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_MODE__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER15_CFG__ENABLE__SHIFT 0x1c +#define GC_ATC_L2_PERFCOUNTER15_CFG__CLEAR__SHIFT 0x1d +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER15_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_ATC_L2_PERFCOUNTER15_CFG__ENABLE_MASK 0x10000000L +#define GC_ATC_L2_PERFCOUNTER15_CFG__CLEAR_MASK 0x20000000L +//GC_ATC_L2_PERFCOUNTER_RSLT_CNTL +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpldec +//GC_L2TLB_PERFCOUNTER0_CFG +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 +#define GC_L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c +#define GC_L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L +#define GC_L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L +//GC_L2TLB_PERFCOUNTER1_CFG +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 +#define GC_L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c +#define GC_L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L +#define GC_L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L +//GC_L2TLB_PERFCOUNTER2_CFG +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 +#define GC_L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c +#define GC_L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L +#define GC_L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L +//GC_L2TLB_PERFCOUNTER3_CFG +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 +#define GC_L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c +#define GC_L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L +#define GC_L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L +#define GC_L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L +#define GC_L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L +//GC_L2TLB_PERFCOUNTER_RSLT_CNTL +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L +#define GC_L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedhvdec +//GCVM_PCIE_ATS_CNTL +#define GCVM_PCIE_ATS_CNTL__STU__SHIFT 0x10 +#define GCVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f +#define GCVM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L +#define GCVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L +//GCMC_VM_NB_MMIOBASE +#define GCMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 +#define GCMC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL +//GCMC_VM_NB_MMIOLIMIT +#define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 +#define GCMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL +//GCMC_VM_NB_PCI_CTRL +#define GCMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 +#define GCMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L +//GCMC_VM_NB_PCI_ARB +#define GCMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 +#define GCMC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L +//GCMC_VM_NB_TOP_OF_DRAM_SLOT1 +#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 +#define GCMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L +//GCMC_VM_NB_LOWER_TOP_OF_DRAM2 +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L +#define GCMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L +//GCMC_VM_NB_UPPER_TOP_OF_DRAM2 +#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 +#define GCMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x000FFFFFL +//GCMC_VM_STEERING +#define GCMC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 +#define GCMC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L +//GCMC_SHARED_VIRT_RESET_REQ +#define GCMC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 +#define GCMC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x8 +#define GCMC_SHARED_VIRT_RESET_REQ__VF_MASK 0x000000FFL +#define GCMC_SHARED_VIRT_RESET_REQ__PF_MASK 0x00000100L +//GCMC_VM_XGMI_LFB_CNTL +#define GCMC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 +#define GCMC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 +#define GCMC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL +#define GCMC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L +//GCMC_VM_XGMI_LFB_SIZE +#define GCMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 +#define GCMC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL +//GCMC_VM_HOST_MAPPING +#define GCMC_VM_HOST_MAPPING__MODE__SHIFT 0x0 +#define GCMC_VM_HOST_MAPPING__MODE_MASK 0x00000001L +//GCMC_VM_XGMI_GPUIOV_ENABLE +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L +#define GCMC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L +//GCMC_VM_CACHEABLE_DRAM_ADDRESS_START +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_CACHEABLE_DRAM_ADDRESS_END +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define GCMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LOCAL_SYSMEM_ADDRESS_START +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LOCAL_SYSMEM_ADDRESS_END +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LPDDR_ADDRESS_START +#define GCMC_VM_LPDDR_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LPDDR_ADDRESS_START__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LPDDR_ADDRESS_END +#define GCMC_VM_LPDDR_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LPDDR_ADDRESS_END__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_APT_CNTL +#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 +#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 +#define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x2 +#define GCMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x4 +#define GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT 0x5 +#define GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT 0x6 +#define GCMC_VM_APT_CNTL__LPDDR_APERTURE_CNTL__SHIFT 0x8 +#define GCMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L +#define GCMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L +#define GCMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK 0x0000000CL +#define GCMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000010L +#define GCMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK 0x00000020L +#define GCMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK 0x000000C0L +#define GCMC_VM_APT_CNTL__LPDDR_APERTURE_CNTL_MASK 0x00000300L +//GCUTCL2_HARVEST_BYPASS_GROUPS +#define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT 0x0 +#define GCUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK 0xFFFFFFFFL +//GCUTCL2_ROUTER_DEBUG +#define GCUTCL2_ROUTER_DEBUG__FLAGS__SHIFT 0x0 +#define GCUTCL2_ROUTER_DEBUG__FLAGS_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcatcl2dec +//GC_ATC_L2_CNTL +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x2 +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x4 +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x5 +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x6 +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0x8 +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xa +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xb +#define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0xc +#define GC_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0xf +#define GC_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x11 +#define GC_ATC_L2_CNTL__CLI_GVA_REQ_FRAG_SIZE__SHIFT 0x17 +#define GC_ATC_L2_CNTL__FORCE_8T_CAP_ON_AT_RETURN__SHIFT 0x1d +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x0000000CL +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000010L +#define GC_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000020L +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x000000C0L +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00000300L +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000400L +#define GC_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000800L +#define GC_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00007000L +#define GC_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00018000L +#define GC_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x007E0000L +#define GC_ATC_L2_CNTL__CLI_GVA_REQ_FRAG_SIZE_MASK 0x1F800000L +#define GC_ATC_L2_CNTL__FORCE_8T_CAP_ON_AT_RETURN_MASK 0x20000000L +//GC_ATC_L2_CNTL2 +#define GC_ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 +#define GC_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 +#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 +#define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb +#define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc +#define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf +#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 +#define GC_ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL +#define GC_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L +#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L +#define GC_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L +#define GC_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L +#define GC_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L +#define GC_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L +//GC_ATC_L2_CACHE_DATA0 +#define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 +#define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 +#define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 +#define GC_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L +#define GC_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L +#define GC_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x00FFFFFCL +//GC_ATC_L2_CACHE_DATA1 +#define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 +#define GC_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL +//GC_ATC_L2_CACHE_DATA2 +#define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define GC_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//GC_ATC_L2_CACHE_DATA3 +#define GC_ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 +#define GC_ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL +//GC_ATC_L2_CACHE_DATA4 +#define GC_ATC_L2_CACHE_DATA4__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x0 +#define GC_ATC_L2_CACHE_DATA4__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0xFFFFFFFFL +//GC_ATC_L2_CNTL3 +#define GC_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT 0x0 +#define GC_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT 0x6 +#define GC_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT 0xc +#define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 +#define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 +#define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b +#define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e +#define GC_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK 0x0000003FL +#define GC_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK 0x00000FC0L +#define GC_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK 0x0003F000L +#define GC_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L +#define GC_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L +#define GC_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L +#define GC_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L +//GC_ATC_L2_STATUS +#define GC_ATC_L2_STATUS__BUSY__SHIFT 0x0 +#define GC_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT 0x1 +#define GC_ATC_L2_STATUS__BUSY_MASK 0x00000001L +#define GC_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK 0x00000002L +//GC_ATC_L2_MISC_CG +#define GC_ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 +#define GC_ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 +#define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 +#define GC_ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L +#define GC_ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L +#define GC_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L +//GC_ATC_L2_ICG_CTRL +#define GC_ATC_L2_ICG_CTRL__OFF_HYSTERESIS__SHIFT 0x0 +#define GC_ATC_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE__SHIFT 0x4 +#define GC_ATC_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE__SHIFT 0x5 +#define GC_ATC_L2_ICG_CTRL__AON_CLOCK_OVERRIDE__SHIFT 0x6 +#define GC_ATC_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE__SHIFT 0x7 +#define GC_ATC_L2_ICG_CTRL__OFF_HYSTERESIS_MASK 0x0000000FL +#define GC_ATC_L2_ICG_CTRL__DYNAMIC_CLOCK_OVERRIDE_MASK 0x00000010L +#define GC_ATC_L2_ICG_CTRL__STATIC_CLOCK_OVERRIDE_MASK 0x00000020L +#define GC_ATC_L2_ICG_CTRL__AON_CLOCK_OVERRIDE_MASK 0x00000040L +#define GC_ATC_L2_ICG_CTRL__PERFMON_CLOCK_OVERRIDE_MASK 0x00000080L +//GC_ATC_L2_SDPPORT_CTRL +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT 0x0 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT 0x1 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT 0x2 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT 0x3 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT 0x4 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT 0x5 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT 0x6 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT 0x7 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT 0x8 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT 0x9 +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK 0x00000001L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK 0x00000002L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK 0x00000004L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK 0x00000008L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK 0x00000010L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK 0x00000020L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK 0x00000040L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK 0x00000080L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK 0x00000100L +#define GC_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK 0x00000200L +//GC_ATC_L2_MISC_DEBUG +#define GC_ATC_L2_MISC_DEBUG__FLAGS__SHIFT 0x0 +#define GC_ATC_L2_MISC_DEBUG__FLAGS_MASK 0xFFFFFFFFL +//GC_ATC_L2_BANK_SELECT_MASKS +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK0__SHIFT 0x0 +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK1__SHIFT 0x4 +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK2__SHIFT 0x8 +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK0_MASK 0x0000000FL +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK1_MASK 0x000000F0L +#define GC_ATC_L2_BANK_SELECT_MASKS__MASK2_MASK 0x00000F00L +//GC_ATC_L2_FAULT_CNTL +#define GC_ATC_L2_FAULT_CNTL__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x0 +#define GC_ATC_L2_FAULT_CNTL__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 +#define GC_ATC_L2_FAULT_CNTL__LOG_REQUEST_ADDRESS__SHIFT 0x2 +#define GC_ATC_L2_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x3 +#define GC_ATC_L2_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x4 +#define GC_ATC_L2_FAULT_CNTL__CLEAR_FAULT_STATUS_ADDR_MASK 0x00000001L +#define GC_ATC_L2_FAULT_CNTL__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L +#define GC_ATC_L2_FAULT_CNTL__LOG_REQUEST_ADDRESS_MASK 0x00000004L +#define GC_ATC_L2_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x00000008L +#define GC_ATC_L2_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x00000010L +//GC_ATC_L2_FAULT_STATUS +#define GC_ATC_L2_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 +#define GC_ATC_L2_FAULT_STATUS__ERROR_TYPE__SHIFT 0x1 +#define GC_ATC_L2_FAULT_STATUS__CID__SHIFT 0x5 +#define GC_ATC_L2_FAULT_STATUS__RWXA__SHIFT 0xe +#define GC_ATC_L2_FAULT_STATUS__VMID__SHIFT 0x12 +#define GC_ATC_L2_FAULT_STATUS__VF__SHIFT 0x16 +#define GC_ATC_L2_FAULT_STATUS__VFID__SHIFT 0x17 +#define GC_ATC_L2_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L +#define GC_ATC_L2_FAULT_STATUS__ERROR_TYPE_MASK 0x0000001EL +#define GC_ATC_L2_FAULT_STATUS__CID_MASK 0x00003FE0L +#define GC_ATC_L2_FAULT_STATUS__RWXA_MASK 0x0003C000L +#define GC_ATC_L2_FAULT_STATUS__VMID_MASK 0x003C0000L +#define GC_ATC_L2_FAULT_STATUS__VF_MASK 0x00400000L +#define GC_ATC_L2_FAULT_STATUS__VFID_MASK 0x0F800000L +//GC_ATC_L2_FAULT_ADDR_LO +#define GC_ATC_L2_FAULT_ADDR_LO__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define GC_ATC_L2_FAULT_ADDR_LO__LOGICAL_PAGE_ADDR_MASK 0xFFFFFFFFL +//GC_ATC_L2_FAULT_ADDR_HI +#define GC_ATC_L2_FAULT_ADDR_HI__LOGICAL_PAGE_ADDR__SHIFT 0x0 +#define GC_ATC_L2_FAULT_ADDR_HI__LOGICAL_PAGE_ADDR_MASK 0xFFFFFFFFL + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbhvdec +//GC_L2TLB_TMZ_CNTL +#define GC_L2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT 0x0 +#define GC_L2TLB_TMZ_CNTL__TMZ_MODULATION_MASK 0x00000001L +//GC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ +#define GC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT 0x0 +#define GC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT 0xa +#define GC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK 0x000003FFL +#define GC_UTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK 0x00000400L +//GC_L2TLB_GCC_MTYPE_ENCODING_CNTL +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_0__SHIFT 0x0 +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_1__SHIFT 0x1 +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_2__SHIFT 0x2 +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_3__SHIFT 0x3 +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_0_MASK 0x00000001L +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_1_MASK 0x00000002L +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_2_MASK 0x00000004L +#define GC_L2TLB_GCC_MTYPE_ENCODING_CNTL__ENABLE_MTYPE_ENCODING_3_MASK 0x00000008L +//GC_L2TLB_FB_COMP_EN_CNTL +#define GC_L2TLB_FB_COMP_EN_CNTL__COMP_EN__SHIFT 0x0 +#define GC_L2TLB_FB_COMP_EN_CNTL__TLSI_COMP_EN_NO_PTE__SHIFT 0x1 +#define GC_L2TLB_FB_COMP_EN_CNTL__TLSI_COMP_EN_PTE__SHIFT 0x2 +#define GC_L2TLB_FB_COMP_EN_CNTL__COMP_EN_MASK 0x00000001L +#define GC_L2TLB_FB_COMP_EN_CNTL__TLSI_COMP_EN_NO_PTE_MASK 0x00000002L +#define GC_L2TLB_FB_COMP_EN_CNTL__TLSI_COMP_EN_PTE_MASK 0x00000004L +//GC_L2TLB_RETRY_TIMEOUT_STATUS_0 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_0__LOGICAL_ADDR__SHIFT 0x0 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_0__LOGICAL_ADDR_MASK 0xFFFFFFFFL +//GC_L2TLB_RETRY_TIMEOUT_STATUS_1 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__LOGICAL_ADDR__SHIFT 0x0 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VMID__SHIFT 0xd +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VFID__SHIFT 0x11 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VF__SHIFT 0x16 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__GPA__SHIFT 0x17 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__RD_PERM__SHIFT 0x19 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__WR_PERM__SHIFT 0x1a +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__EXE_PERM__SHIFT 0x1b +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__TMZ__SHIFT 0x1c +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__CLIENT_ID__SHIFT 0x1d +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__LOGICAL_ADDR_MASK 0x00001FFFL +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VMID_MASK 0x0001E000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VFID_MASK 0x003E0000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__VF_MASK 0x00400000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__GPA_MASK 0x01800000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__RD_PERM_MASK 0x02000000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__WR_PERM_MASK 0x04000000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__EXE_PERM_MASK 0x08000000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__TMZ_MASK 0x10000000L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_1__CLIENT_ID_MASK 0xE0000000L +//GC_L2TLB_RETRY_TIMEOUT_STATUS_2 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__CLIENT_ID__SHIFT 0x0 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__BUS_ATOMIC_PERM__SHIFT 0x6 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__TLB_ID__SHIFT 0x7 +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__RETRY_TIMEOUT__SHIFT 0xb +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__CLEAR_RETRY_TIMEOUT_STATUS__SHIFT 0x1f +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__CLIENT_ID_MASK 0x0000003FL +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__BUS_ATOMIC_PERM_MASK 0x00000040L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__TLB_ID_MASK 0x00000780L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__RETRY_TIMEOUT_MASK 0x00000800L +#define GC_L2TLB_RETRY_TIMEOUT_STATUS_2__CLEAR_RETRY_TIMEOUT_STATUS_MASK 0x80000000L +//GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__CLIENT_ID__SHIFT 0x0 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__SNOOP__SHIFT 0x9 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__ATOMIC__SHIFT 0xa +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VF__SHIFT 0xb +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__HDM__SHIFT 0xc +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__SPACE__SHIFT 0xd +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VFID__SHIFT 0x10 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__EXE__SHIFT 0x15 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__TMZ__SHIFT 0x16 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VMID__SHIFT 0x18 +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__TEE__SHIFT 0x1c +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__PCIE_ATOMIC__SHIFT 0x1d +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__RESERVED_SPACE_ENCODING_DETECTED__SHIFT 0x1e +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__CLEAR__SHIFT 0x1f +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__CLIENT_ID_MASK 0x000001FFL +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__SNOOP_MASK 0x00000200L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__ATOMIC_MASK 0x00000400L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VF_MASK 0x00000800L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__HDM_MASK 0x00001000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__SPACE_MASK 0x0000E000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VFID_MASK 0x001F0000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__EXE_MASK 0x00200000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__TMZ_MASK 0x00400000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__VMID_MASK 0x0F000000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__TEE_MASK 0x10000000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__PCIE_ATOMIC_MASK 0x20000000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__RESERVED_SPACE_ENCODING_DETECTED_MASK 0x40000000L +#define GC_L2TLB_TLB0_RESERVED_SPACE_ENCODING_STATUS__CLEAR_MASK 0x80000000L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvml2pspdec +//GCUTCL2_TRANSLATION_BYPASS_BY_VMID +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT 0x0 +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT 0x10 +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK 0x0000FFFFL +#define GCUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK 0xFFFF0000L +//GCVML2_SEC_MASTER +#define GCVML2_SEC_MASTER__UNIT_ID__SHIFT 0x0 +#define GCVML2_SEC_MASTER__TRUST_LEVEL__SHIFT 0x6 +#define GCVML2_SEC_MASTER__UNIT_ID_MASK 0x0000003FL +#define GCVML2_SEC_MASTER__TRUST_LEVEL_MASK 0x000003C0L +//GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE +#define GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE__SHIFT 0x0 +#define GCVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE__GPU_HOST_TRANSLATION_ENABLE_MASK 0x00000001L +//GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT 0x0 +#define GCUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK 0x00000001L +//GCVM_IOMMU_CONTROL_REGISTER +#define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 +#define GCVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L +//GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER +#define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd +#define GCVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L +//GCUTC_TRANSLATION_FAULT_CNTL0 +#define GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT 0x0 +#define GCUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK 0xFFFFFFFFL +//GCUTC_TRANSLATION_FAULT_CNTL1 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT 0x0 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT 0x8 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT 0x9 +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT 0xa +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_HDM__SHIFT 0xb +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK 0x000000FFL +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK 0x00000100L +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK 0x00000200L +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK 0x00000400L +#define GCUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_HDM_MASK 0x00000800L +//GCUTCL2_COMP_EN_OVERRIDES +#define GCUTCL2_COMP_EN_OVERRIDES__GPA_MODE3__SHIFT 0x0 +#define GCUTCL2_COMP_EN_OVERRIDES__LOCAL_FB_PTE__SHIFT 0x1 +#define GCUTCL2_COMP_EN_OVERRIDES__REMOTE_FB_PTE__SHIFT 0x2 +#define GCUTCL2_COMP_EN_OVERRIDES__ROUTER_ATCL2__SHIFT 0x3 +#define GCUTCL2_COMP_EN_OVERRIDES__GPA_MODE3_MASK 0x00000001L +#define GCUTCL2_COMP_EN_OVERRIDES__LOCAL_FB_PTE_MASK 0x00000002L +#define GCUTCL2_COMP_EN_OVERRIDES__REMOTE_FB_PTE_MASK 0x00000004L +#define GCUTCL2_COMP_EN_OVERRIDES__ROUTER_ATCL2_MASK 0x00000008L +//GCUTCL2_ROUTER_CNTL +#define GCUTCL2_ROUTER_CNTL__OVERRIDE_GPA2_EXE_AND_ATOMIC_PERMS_GRANTED__SHIFT 0x0 +#define GCUTCL2_ROUTER_CNTL__OVERRIDE_GPA2_EXE_AND_ATOMIC_PERMS_GRANTED_MASK 0x00000001L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcvmsharedpspdec +//GCMC_VM_FB_SIZE_OFFSET_VF0 +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF1 +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF2 +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF3 +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF4 +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF5 +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF6 +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_SIZE_OFFSET_VF7 +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL +#define GCMC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L +//GCMC_VM_FB_OFFSET +#define GCMC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 +#define GCMC_VM_FB_OFFSET__FB_OFFSET_MASK 0x0FFFFFFFL +//GCMC_VM_LOCAL_FB_ADDRESS_START +#define GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LOCAL_FB_ADDRESS_END +#define GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT 0x0 +#define GCMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK 0x0FFFFFFFL +//GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL +#define GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 +#define GCMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L +//GCUTCL2_MISC_CNTL +#define GCUTCL2_MISC_CNTL__MASK_TDISP_RUN_ATC_DIS_IOMMU_DIS_NPA__SHIFT 0x0 +#define GCUTCL2_MISC_CNTL__MASK_TDISP_RUN_ATC_DIS_IOMMU_DIS_NPA_MASK 0x00000001L + + +// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpspdec +//GC_L2TLB_TLB0_CAM_ECC_CNTL +#define GC_L2TLB_TLB0_CAM_ECC_CNTL__FORCE_PARITY_ERROR__SHIFT 0x0 +#define GC_L2TLB_TLB0_CAM_ECC_CNTL__FORCE_PARITY_ERROR_MASK 0x00000001L + + +// addressBlock: gfx_se_sqind +//SQ_DEBUG_STS_LOCAL +#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 +#define SQ_DEBUG_STS_LOCAL__SQ_BUSY__SHIFT 0xc +#define SQ_DEBUG_STS_LOCAL__IS_BUSY__SHIFT 0xd +#define SQ_DEBUG_STS_LOCAL__IB_BUSY__SHIFT 0xe +#define SQ_DEBUG_STS_LOCAL__ARB_BUSY__SHIFT 0xf +#define SQ_DEBUG_STS_LOCAL__EXP_BUSY__SHIFT 0x10 +#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY__SHIFT 0x11 +#define SQ_DEBUG_STS_LOCAL__VM_BUSY__SHIFT 0x12 +#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x00000001L +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x000003F0L +#define SQ_DEBUG_STS_LOCAL__SQ_BUSY_MASK 0x00001000L +#define SQ_DEBUG_STS_LOCAL__IS_BUSY_MASK 0x00002000L +#define SQ_DEBUG_STS_LOCAL__IB_BUSY_MASK 0x00004000L +#define SQ_DEBUG_STS_LOCAL__ARB_BUSY_MASK 0x00008000L +#define SQ_DEBUG_STS_LOCAL__EXP_BUSY_MASK 0x00010000L +#define SQ_DEBUG_STS_LOCAL__BRMSG_BUSY_MASK 0x00020000L +#define SQ_DEBUG_STS_LOCAL__VM_BUSY_MASK 0x00040000L +//SQ_DEBUG_CTRL_LOCAL +#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 +#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0x000000FFL +//SQ_WAVE_ACTIVE +#define SQ_WAVE_ACTIVE__WAVE_SLOT__SHIFT 0x0 +#define SQ_WAVE_ACTIVE__WAVE_SLOT_MASK 0x000FFFFFL +//SQ_WAVE_VALID_AND_IDLE +#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT__SHIFT 0x0 +#define SQ_WAVE_VALID_AND_IDLE__WAVE_SLOT_MASK 0x000FFFFFL +//SQ_WAVE_MODE +#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 +#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 +#define SQ_WAVE_MODE__DST_VGPR_MSB__SHIFT 0xc +#define SQ_WAVE_MODE__SRC0_VGPR_MSB__SHIFT 0xe +#define SQ_WAVE_MODE__SRC1_VGPR_MSB__SHIFT 0x10 +#define SQ_WAVE_MODE__SRC2_VGPR_MSB__SHIFT 0x12 +#define SQ_WAVE_MODE__FP16_OVFL__SHIFT 0x17 +#define SQ_WAVE_MODE__SCALAR_PREFETCH_EN__SHIFT 0x18 +#define SQ_WAVE_MODE__REPLAY_MODE__SHIFT 0x19 +#define SQ_WAVE_MODE__FLAT_SCRATCH_IS_NV__SHIFT 0x1a +#define SQ_WAVE_MODE__DISABLE_PERF__SHIFT 0x1b +#define SQ_WAVE_MODE__FP_ROUND_MASK 0x0000000FL +#define SQ_WAVE_MODE__FP_DENORM_MASK 0x000000F0L +#define SQ_WAVE_MODE__DST_VGPR_MSB_MASK 0x00003000L +#define SQ_WAVE_MODE__SRC0_VGPR_MSB_MASK 0x0000C000L +#define SQ_WAVE_MODE__SRC1_VGPR_MSB_MASK 0x00030000L +#define SQ_WAVE_MODE__SRC2_VGPR_MSB_MASK 0x000C0000L +#define SQ_WAVE_MODE__FP16_OVFL_MASK 0x00800000L +#define SQ_WAVE_MODE__SCALAR_PREFETCH_EN_MASK 0x01000000L +#define SQ_WAVE_MODE__REPLAY_MODE_MASK 0x02000000L +#define SQ_WAVE_MODE__FLAT_SCRATCH_IS_NV_MASK 0x04000000L +#define SQ_WAVE_MODE__DISABLE_PERF_MASK 0x08000000L +//SQ_WAVE_STATUS +#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 +#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 +#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 +#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa +#define SQ_WAVE_STATUS__IN_WG__SHIFT 0xb +#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe +#define SQ_WAVE_STATUS__TRAP_BARRIER_COMPLETE__SHIFT 0xf +#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 +#define SQ_WAVE_STATUS__CLUSTER_TRAP_BARRIER_COMPLETE__SHIFT 0x11 +#define SQ_WAVE_STATUS__FATAL_HALT__SHIFT 0x17 +#define SQ_WAVE_STATUS__NO_VGPRS__SHIFT 0x18 +#define SQ_WAVE_STATUS__IDLE__SHIFT 0x1c +#define SQ_WAVE_STATUS__WAVE64__SHIFT 0x1d +#define SQ_WAVE_STATUS__DVGPR_EN__SHIFT 0x1e +#define SQ_WAVE_STATUS__WGP_TAKEOVER__SHIFT 0x1f +#define SQ_WAVE_STATUS__PRIV_MASK 0x00000020L +#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x00000040L +#define SQ_WAVE_STATUS__EXECZ_MASK 0x00000200L +#define SQ_WAVE_STATUS__VCCZ_MASK 0x00000400L +#define SQ_WAVE_STATUS__IN_WG_MASK 0x00000800L +#define SQ_WAVE_STATUS__TRAP_MASK 0x00004000L +#define SQ_WAVE_STATUS__TRAP_BARRIER_COMPLETE_MASK 0x00008000L +#define SQ_WAVE_STATUS__VALID_MASK 0x00010000L +#define SQ_WAVE_STATUS__CLUSTER_TRAP_BARRIER_COMPLETE_MASK 0x00020000L +#define SQ_WAVE_STATUS__FATAL_HALT_MASK 0x00800000L +#define SQ_WAVE_STATUS__NO_VGPRS_MASK 0x01000000L +#define SQ_WAVE_STATUS__IDLE_MASK 0x10000000L +#define SQ_WAVE_STATUS__WAVE64_MASK 0x20000000L +#define SQ_WAVE_STATUS__DVGPR_EN_MASK 0x40000000L +#define SQ_WAVE_STATUS__WGP_TAKEOVER_MASK 0x80000000L +//SQ_WAVE_STATE_PRIV +#define SQ_WAVE_STATE_PRIV__WG_RR_EN__SHIFT 0x0 +#define SQ_WAVE_STATE_PRIV__SLEEP_WAKEUP__SHIFT 0x1 +#define SQ_WAVE_STATE_PRIV__BARRIER_COMPLETE__SHIFT 0x2 +#define SQ_WAVE_STATE_PRIV__NAMED_BARRIER_COMPLETE__SHIFT 0x3 +#define SQ_WAVE_STATE_PRIV__NAMED_BARRIER_ID__SHIFT 0x4 +#define SQ_WAVE_STATE_PRIV__SCC__SHIFT 0x9 +#define SQ_WAVE_STATE_PRIV__SYS_PRIO__SHIFT 0xa +#define SQ_WAVE_STATE_PRIV__USER_PRIO__SHIFT 0xc +#define SQ_WAVE_STATE_PRIV__HALT__SHIFT 0xe +#define SQ_WAVE_STATE_PRIV__POISON_ERR__SHIFT 0xf +#define SQ_WAVE_STATE_PRIV__CLUSTER_BARRIER_COMPLETE__SHIFT 0x10 +#define SQ_WAVE_STATE_PRIV__COND_DBG_SYS__SHIFT 0x11 +#define SQ_WAVE_STATE_PRIV__SCRATCH_EN__SHIFT 0x12 +#define SQ_WAVE_STATE_PRIV__PERF_EN__SHIFT 0x13 +#define SQ_WAVE_STATE_PRIV__TTRACE_EN__SHIFT 0x14 +#define SQ_WAVE_STATE_PRIV__COND_DBG_USER__SHIFT 0x15 +#define SQ_WAVE_STATE_PRIV__WG_RR_EN_MASK 0x00000001L +#define SQ_WAVE_STATE_PRIV__SLEEP_WAKEUP_MASK 0x00000002L +#define SQ_WAVE_STATE_PRIV__BARRIER_COMPLETE_MASK 0x00000004L +#define SQ_WAVE_STATE_PRIV__NAMED_BARRIER_COMPLETE_MASK 0x00000008L +#define SQ_WAVE_STATE_PRIV__NAMED_BARRIER_ID_MASK 0x000001F0L +#define SQ_WAVE_STATE_PRIV__SCC_MASK 0x00000200L +#define SQ_WAVE_STATE_PRIV__SYS_PRIO_MASK 0x00000C00L +#define SQ_WAVE_STATE_PRIV__USER_PRIO_MASK 0x00003000L +#define SQ_WAVE_STATE_PRIV__HALT_MASK 0x00004000L +#define SQ_WAVE_STATE_PRIV__POISON_ERR_MASK 0x00008000L +#define SQ_WAVE_STATE_PRIV__CLUSTER_BARRIER_COMPLETE_MASK 0x00010000L +#define SQ_WAVE_STATE_PRIV__COND_DBG_SYS_MASK 0x00020000L +#define SQ_WAVE_STATE_PRIV__SCRATCH_EN_MASK 0x00040000L +#define SQ_WAVE_STATE_PRIV__PERF_EN_MASK 0x00080000L +#define SQ_WAVE_STATE_PRIV__TTRACE_EN_MASK 0x00100000L +#define SQ_WAVE_STATE_PRIV__COND_DBG_USER_MASK 0x00200000L +//SQ_WAVE_GPR_ALLOC +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0xc +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x000000FFL +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x000FF000L +//SQ_WAVE_LDS_ALLOC +#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc +#define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE__SHIFT 0x18 +#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0x000001FFL +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x001FF000L +#define SQ_WAVE_LDS_ALLOC__VGPR_SHARED_SIZE_MASK 0x0F000000L +//SQ_WAVE_IB_STS +#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x0 +#define SQ_WAVE_IB_STS__DS_CNT__SHIFT 0x3 +#define SQ_WAVE_IB_STS__LOAD_CNT__SHIFT 0x9 +#define SQ_WAVE_IB_STS__SAMPLE_CNT__SHIFT 0xf +#define SQ_WAVE_IB_STS__BVH_CNT__SHIFT 0x15 +#define SQ_WAVE_IB_STS__STORE_CNT__SHIFT 0x18 +#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x00000007L +#define SQ_WAVE_IB_STS__DS_CNT_MASK 0x000001F8L +#define SQ_WAVE_IB_STS__LOAD_CNT_MASK 0x00007E00L +#define SQ_WAVE_IB_STS__SAMPLE_CNT_MASK 0x001F8000L +#define SQ_WAVE_IB_STS__BVH_CNT_MASK 0x00E00000L +#define SQ_WAVE_IB_STS__STORE_CNT_MASK 0x3F000000L +//SQ_PERF_SNAPSHOT_DATA +#define SQ_PERF_SNAPSHOT_DATA__VALID__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_DATA__WAVE_ISSUE__SHIFT 0x1 +#define SQ_PERF_SNAPSHOT_DATA__INST_TYPE__SHIFT 0x2 +#define SQ_PERF_SNAPSHOT_DATA__NO_ISSUE_REASON__SHIFT 0x6 +#define SQ_PERF_SNAPSHOT_DATA__WAVE_ID__SHIFT 0x9 +#define SQ_PERF_SNAPSHOT_DATA__SAMPLING_LOCK_ERR__SHIFT 0xe +#define SQ_PERF_SNAPSHOT_DATA__ASYNC_CNT__SHIFT 0x14 +#define SQ_PERF_SNAPSHOT_DATA__TENSOR_CNT__SHIFT 0x1a +#define SQ_PERF_SNAPSHOT_DATA__VALID_MASK 0x00000001L +#define SQ_PERF_SNAPSHOT_DATA__WAVE_ISSUE_MASK 0x00000002L +#define SQ_PERF_SNAPSHOT_DATA__INST_TYPE_MASK 0x0000003CL +#define SQ_PERF_SNAPSHOT_DATA__NO_ISSUE_REASON_MASK 0x000001C0L +#define SQ_PERF_SNAPSHOT_DATA__WAVE_ID_MASK 0x00003E00L +#define SQ_PERF_SNAPSHOT_DATA__SAMPLING_LOCK_ERR_MASK 0x00004000L +#define SQ_PERF_SNAPSHOT_DATA__ASYNC_CNT_MASK 0x03F00000L +#define SQ_PERF_SNAPSHOT_DATA__TENSOR_CNT_MASK 0xFC000000L +//SQ_PERF_SNAPSHOT_PC_LO +#define SQ_PERF_SNAPSHOT_PC_LO__PC_LO__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_PC_LO__PC_LO_MASK 0xFFFFFFFFL +//SQ_PERF_SNAPSHOT_PC_HI +#define SQ_PERF_SNAPSHOT_PC_HI__PC_HI__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_PC_HI__PC_HI_MASK 0x01FFFFFFL +//SQ_WAVE_IB_DBG1 +#define SQ_WAVE_IB_DBG1__WAVE_IDLE__SHIFT 0x18 +#define SQ_WAVE_IB_DBG1__MISC_CNT__SHIFT 0x19 +#define SQ_WAVE_IB_DBG1__WAVE_IDLE_MASK 0x01000000L +#define SQ_WAVE_IB_DBG1__MISC_CNT_MASK 0xFE000000L +//SQ_WAVE_FLUSH_IB +#define SQ_WAVE_FLUSH_IB__UNUSED__SHIFT 0x0 +#define SQ_WAVE_FLUSH_IB__UNUSED_MASK 0xFFFFFFFFL +//SQ_PERF_SNAPSHOT_DATA1 +#define SQ_PERF_SNAPSHOT_DATA1__WAVE_CNT__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_BRMSG__SHIFT 0x9 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_EXPORT__SHIFT 0xa +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_LDS_DIRECT__SHIFT 0xb +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_LDS__SHIFT 0xc +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_TEX__SHIFT 0xd +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_SCALAR__SHIFT 0xe +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_VALU__SHIFT 0xf +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_VALU_ARB_B__SHIFT 0x10 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_BRMSG__SHIFT 0x11 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_EXPORT__SHIFT 0x12 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_LDS_DIRECT__SHIFT 0x13 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_LDS__SHIFT 0x14 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_TEX__SHIFT 0x15 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_SCALAR__SHIFT 0x16 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_VALU__SHIFT 0x17 +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_VALU_ARB_B__SHIFT 0x18 +#define SQ_PERF_SNAPSHOT_DATA1__XCNT__SHIFT 0x1a +#define SQ_PERF_SNAPSHOT_DATA1__WAVE_CNT_MASK 0x0000003FL +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_BRMSG_MASK 0x00000200L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_EXPORT_MASK 0x00000400L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_LDS_DIRECT_MASK 0x00000800L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_LDS_MASK 0x00001000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_TEX_MASK 0x00002000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_SCALAR_MASK 0x00004000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_VALU_MASK 0x00008000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_ISSUED_VALU_ARB_B_MASK 0x00010000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_BRMSG_MASK 0x00020000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_EXPORT_MASK 0x00040000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_LDS_DIRECT_MASK 0x00080000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_LDS_MASK 0x00100000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_TEX_MASK 0x00200000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_SCALAR_MASK 0x00400000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_VALU_MASK 0x00800000L +#define SQ_PERF_SNAPSHOT_DATA1__ARB_STATE_STALLED_VALU_ARB_B_MASK 0x01000000L +#define SQ_PERF_SNAPSHOT_DATA1__XCNT_MASK 0xFC000000L +//SQ_PERF_SNAPSHOT_DATA2 +#define SQ_PERF_SNAPSHOT_DATA2__LOAD_CNT__SHIFT 0x0 +#define SQ_PERF_SNAPSHOT_DATA2__STORE_CNT__SHIFT 0x6 +#define SQ_PERF_SNAPSHOT_DATA2__BVH_CNT__SHIFT 0xc +#define SQ_PERF_SNAPSHOT_DATA2__SAMPLE_CNT__SHIFT 0xf +#define SQ_PERF_SNAPSHOT_DATA2__DS_CNT__SHIFT 0x15 +#define SQ_PERF_SNAPSHOT_DATA2__KM_CNT__SHIFT 0x1b +#define SQ_PERF_SNAPSHOT_DATA2__LOAD_CNT_MASK 0x0000003FL +#define SQ_PERF_SNAPSHOT_DATA2__STORE_CNT_MASK 0x00000FC0L +#define SQ_PERF_SNAPSHOT_DATA2__BVH_CNT_MASK 0x00007000L +#define SQ_PERF_SNAPSHOT_DATA2__SAMPLE_CNT_MASK 0x001F8000L +#define SQ_PERF_SNAPSHOT_DATA2__DS_CNT_MASK 0x07E00000L +#define SQ_PERF_SNAPSHOT_DATA2__KM_CNT_MASK 0xF8000000L +//SQ_WAVE_EXCP_FLAG_PRIV +#define SQ_WAVE_EXCP_FLAG_PRIV__ADDR_WATCH__SHIFT 0x0 +#define SQ_WAVE_EXCP_FLAG_PRIV__MEMVIOL__SHIFT 0x4 +#define SQ_WAVE_EXCP_FLAG_PRIV__SAVE_CONTEXT__SHIFT 0x5 +#define SQ_WAVE_EXCP_FLAG_PRIV__ILLEGAL_INST__SHIFT 0x6 +#define SQ_WAVE_EXCP_FLAG_PRIV__HOST_TRAP__SHIFT 0x7 +#define SQ_WAVE_EXCP_FLAG_PRIV__WAVE_START__SHIFT 0x8 +#define SQ_WAVE_EXCP_FLAG_PRIV__WAVE_END__SHIFT 0x9 +#define SQ_WAVE_EXCP_FLAG_PRIV__PERF_SNAPSHOT__SHIFT 0xa +#define SQ_WAVE_EXCP_FLAG_PRIV__TRAP_AFTER_INST__SHIFT 0xb +#define SQ_WAVE_EXCP_FLAG_PRIV__XNACK_ERROR__SHIFT 0xc +#define SQ_WAVE_EXCP_FLAG_PRIV__FIRST_MEMVIOL_SOURCE__SHIFT 0x1e +#define SQ_WAVE_EXCP_FLAG_PRIV__ADDR_WATCH_MASK 0x0000000FL +#define SQ_WAVE_EXCP_FLAG_PRIV__MEMVIOL_MASK 0x00000010L +#define SQ_WAVE_EXCP_FLAG_PRIV__SAVE_CONTEXT_MASK 0x00000020L +#define SQ_WAVE_EXCP_FLAG_PRIV__ILLEGAL_INST_MASK 0x00000040L +#define SQ_WAVE_EXCP_FLAG_PRIV__HOST_TRAP_MASK 0x00000080L +#define SQ_WAVE_EXCP_FLAG_PRIV__WAVE_START_MASK 0x00000100L +#define SQ_WAVE_EXCP_FLAG_PRIV__WAVE_END_MASK 0x00000200L +#define SQ_WAVE_EXCP_FLAG_PRIV__PERF_SNAPSHOT_MASK 0x00000400L +#define SQ_WAVE_EXCP_FLAG_PRIV__TRAP_AFTER_INST_MASK 0x00000800L +#define SQ_WAVE_EXCP_FLAG_PRIV__XNACK_ERROR_MASK 0x00001000L +#define SQ_WAVE_EXCP_FLAG_PRIV__FIRST_MEMVIOL_SOURCE_MASK 0xC0000000L +//SQ_WAVE_EXCP_FLAG_USER +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INVALID__SHIFT 0x0 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INPUT_DENORM__SHIFT 0x1 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_FLOAT_DIV0__SHIFT 0x2 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_OVERFLOW__SHIFT 0x3 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_UNDERFLOW__SHIFT 0x4 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INEXACT__SHIFT 0x5 +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INT_DIV0__SHIFT 0x6 +#define SQ_WAVE_EXCP_FLAG_USER__BUFFER_OOB__SHIFT 0x1e +#define SQ_WAVE_EXCP_FLAG_USER__LOD_CLAMPED__SHIFT 0x1f +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INVALID_MASK 0x00000001L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INPUT_DENORM_MASK 0x00000002L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_FLOAT_DIV0_MASK 0x00000004L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_OVERFLOW_MASK 0x00000008L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_UNDERFLOW_MASK 0x00000010L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INEXACT_MASK 0x00000020L +#define SQ_WAVE_EXCP_FLAG_USER__ALU_INT_DIV0_MASK 0x00000040L +#define SQ_WAVE_EXCP_FLAG_USER__BUFFER_OOB_MASK 0x40000000L +#define SQ_WAVE_EXCP_FLAG_USER__LOD_CLAMPED_MASK 0x80000000L +//SQ_WAVE_TRAP_CTRL +#define SQ_WAVE_TRAP_CTRL__ALU_INVALID__SHIFT 0x0 +#define SQ_WAVE_TRAP_CTRL__ALU_INPUT_DENORM__SHIFT 0x1 +#define SQ_WAVE_TRAP_CTRL__ALU_FLOAT_DIV0__SHIFT 0x2 +#define SQ_WAVE_TRAP_CTRL__ALU_OVERFLOW__SHIFT 0x3 +#define SQ_WAVE_TRAP_CTRL__ALU_UNDERFLOW__SHIFT 0x4 +#define SQ_WAVE_TRAP_CTRL__ALU_INEXACT__SHIFT 0x5 +#define SQ_WAVE_TRAP_CTRL__ALU_INT_DIV0__SHIFT 0x6 +#define SQ_WAVE_TRAP_CTRL__ADDR_WATCH__SHIFT 0x7 +#define SQ_WAVE_TRAP_CTRL__WAVE_END__SHIFT 0x8 +#define SQ_WAVE_TRAP_CTRL__TRAP_AFTER_INST__SHIFT 0x9 +#define SQ_WAVE_TRAP_CTRL__ALU_INVALID_MASK 0x00000001L +#define SQ_WAVE_TRAP_CTRL__ALU_INPUT_DENORM_MASK 0x00000002L +#define SQ_WAVE_TRAP_CTRL__ALU_FLOAT_DIV0_MASK 0x00000004L +#define SQ_WAVE_TRAP_CTRL__ALU_OVERFLOW_MASK 0x00000008L +#define SQ_WAVE_TRAP_CTRL__ALU_UNDERFLOW_MASK 0x00000010L +#define SQ_WAVE_TRAP_CTRL__ALU_INEXACT_MASK 0x00000020L +#define SQ_WAVE_TRAP_CTRL__ALU_INT_DIV0_MASK 0x00000040L +#define SQ_WAVE_TRAP_CTRL__ADDR_WATCH_MASK 0x00000080L +#define SQ_WAVE_TRAP_CTRL__WAVE_END_MASK 0x00000100L +#define SQ_WAVE_TRAP_CTRL__TRAP_AFTER_INST_MASK 0x00000200L +//SQ_WAVE_SCRATCH_BASE_LO +#define SQ_WAVE_SCRATCH_BASE_LO__DATA__SHIFT 0x0 +#define SQ_WAVE_SCRATCH_BASE_LO__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_SCRATCH_BASE_HI +#define SQ_WAVE_SCRATCH_BASE_HI__DATA__SHIFT 0x0 +#define SQ_WAVE_SCRATCH_BASE_HI__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_HW_ID1 +#define SQ_WAVE_HW_ID1__WAVE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID1__SIMD_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID1__WGP_ID__SHIFT 0xa +#define SQ_WAVE_HW_ID1__SA_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID1__DP_RATE__SHIFT 0x1d +#define SQ_WAVE_HW_ID1__WAVE_ID_MASK 0x0000001FL +#define SQ_WAVE_HW_ID1__SIMD_ID_MASK 0x00000300L +#define SQ_WAVE_HW_ID1__WGP_ID_MASK 0x00003C00L +#define SQ_WAVE_HW_ID1__SA_ID_MASK 0x00010000L +#define SQ_WAVE_HW_ID1__DP_RATE_MASK 0xE0000000L +//SQ_WAVE_HW_ID2 +#define SQ_WAVE_HW_ID2__QUEUE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID2__PIPE_ID__SHIFT 0x4 +#define SQ_WAVE_HW_ID2__ME_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID2__STATE_ID__SHIFT 0xc +#define SQ_WAVE_HW_ID2__WG_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID2__VM_ID__SHIFT 0x18 +#define SQ_WAVE_HW_ID2__QUEUE_ID_MASK 0x0000000FL +#define SQ_WAVE_HW_ID2__PIPE_ID_MASK 0x00000030L +#define SQ_WAVE_HW_ID2__ME_ID_MASK 0x00000300L +#define SQ_WAVE_HW_ID2__STATE_ID_MASK 0x00007000L +#define SQ_WAVE_HW_ID2__WG_ID_MASK 0x001F0000L +#define SQ_WAVE_HW_ID2__VM_ID_MASK 0x0F000000L +//SQ_WAVE_SCHED_MODE +#define SQ_WAVE_SCHED_MODE__DEP_MODE__SHIFT 0x0 +#define SQ_WAVE_SCHED_MODE__DISABLE_VALU_ARB_STALL__SHIFT 0x2 +#define SQ_WAVE_SCHED_MODE__DEP_MODE_MASK 0x00000003L +#define SQ_WAVE_SCHED_MODE__DISABLE_VALU_ARB_STALL_MASK 0x00000004L +//SQ_WAVE_IB_STS2 +#define SQ_WAVE_IB_STS2__KM_CNT__SHIFT 0x0 +#define SQ_WAVE_IB_STS2__CLUSTER_ID__SHIFT 0x6 +#define SQ_WAVE_IB_STS2__ASYNC_CNT__SHIFT 0xc +#define SQ_WAVE_IB_STS2__TENSOR_CNT__SHIFT 0x12 +#define SQ_WAVE_IB_STS2__WG_IN_CLUSTER__SHIFT 0x15 +#define SQ_WAVE_IB_STS2__MWAIT__SHIFT 0x19 +#define SQ_WAVE_IB_STS2__INST_PREFETCH__SHIFT 0x1c +#define SQ_WAVE_IB_STS2__FWD_PROGRESS__SHIFT 0x1e +#define SQ_WAVE_IB_STS2__TTRACE_EN_SPI__SHIFT 0x1f +#define SQ_WAVE_IB_STS2__KM_CNT_MASK 0x0000001FL +#define SQ_WAVE_IB_STS2__CLUSTER_ID_MASK 0x000003C0L +#define SQ_WAVE_IB_STS2__ASYNC_CNT_MASK 0x0003F000L +#define SQ_WAVE_IB_STS2__TENSOR_CNT_MASK 0x000C0000L +#define SQ_WAVE_IB_STS2__WG_IN_CLUSTER_MASK 0x01E00000L +#define SQ_WAVE_IB_STS2__MWAIT_MASK 0x02000000L +#define SQ_WAVE_IB_STS2__INST_PREFETCH_MASK 0x30000000L +#define SQ_WAVE_IB_STS2__FWD_PROGRESS_MASK 0x40000000L +#define SQ_WAVE_IB_STS2__TTRACE_EN_SPI_MASK 0x80000000L +//SQ_WAVE_DVGPR_ALLOC_LO +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT0__SHIFT 0x0 +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT1__SHIFT 0x8 +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT2__SHIFT 0x10 +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT3__SHIFT 0x18 +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT0_MASK 0x0000007FL +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT1_MASK 0x00007F00L +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT2_MASK 0x007F0000L +#define SQ_WAVE_DVGPR_ALLOC_LO__SEGMENT3_MASK 0x7F000000L +//SQ_WAVE_DVGPR_ALLOC_HI +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT4__SHIFT 0x0 +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT5__SHIFT 0x8 +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT6__SHIFT 0x10 +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT7__SHIFT 0x18 +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT4_MASK 0x0000007FL +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT5_MASK 0x00007F00L +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT6_MASK 0x007F0000L +#define SQ_WAVE_DVGPR_ALLOC_HI__SEGMENT7_MASK 0x7F000000L +//SQ_WAVE_XNACK_STATE_PRIV +#define SQ_WAVE_XNACK_STATE_PRIV__FXPTR__SHIFT 0x0 +#define SQ_WAVE_XNACK_STATE_PRIV__RPTR__SHIFT 0x8 +#define SQ_WAVE_XNACK_STATE_PRIV__REPLAY_W64H__SHIFT 0x10 +#define SQ_WAVE_XNACK_STATE_PRIV__GOT_XNACK__SHIFT 0x11 +#define SQ_WAVE_XNACK_STATE_PRIV__FIRST_REPLAY__SHIFT 0x12 +#define SQ_WAVE_XNACK_STATE_PRIV__FXPTR_MASK 0x0000007FL +#define SQ_WAVE_XNACK_STATE_PRIV__RPTR_MASK 0x00007F00L +#define SQ_WAVE_XNACK_STATE_PRIV__REPLAY_W64H_MASK 0x00010000L +#define SQ_WAVE_XNACK_STATE_PRIV__GOT_XNACK_MASK 0x00020000L +#define SQ_WAVE_XNACK_STATE_PRIV__FIRST_REPLAY_MASK 0x00040000L +//SQ_WAVE_XNACK_MASK +#define SQ_WAVE_XNACK_MASK__MASK__SHIFT 0x0 +#define SQ_WAVE_XNACK_MASK__MASK_MASK 0xFFFFFFFFL +//SQ_WAVE_PC_LO +#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 +#define SQ_WAVE_PC_LO__PC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_PC_HI +#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 +#define SQ_WAVE_PC_HI__PC_HI_MASK 0x01FFFFFFL +//SQ_WAVE_TTMP0 +#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP0__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP1 +#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP1__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP2 +#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP2__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP3 +#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP3__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP4 +#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP4__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP5 +#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP5__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP6 +#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP6__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP7 +#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP7__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP8 +#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP8__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP9 +#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP9__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP10 +#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP10__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP11 +#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP11__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP12 +#define SQ_WAVE_TTMP12__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP12__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP13 +#define SQ_WAVE_TTMP13__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP13__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP14 +#define SQ_WAVE_TTMP14__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP14__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_TTMP15 +#define SQ_WAVE_TTMP15__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP15__DATA_MASK 0xFFFFFFFFL +//SQ_WAVE_M0 +#define SQ_WAVE_M0__M0__SHIFT 0x0 +#define SQ_WAVE_M0__M0_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_LO +#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 +#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xFFFFFFFFL +//SQ_WAVE_EXEC_HI +#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 +#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xFFFFFFFFL + + +#endif |