diff options
| author | Alistair Popple <apopple@nvidia.com> | 2025-11-10 22:34:23 +0900 |
|---|---|---|
| committer | Alexandre Courbot <acourbot@nvidia.com> | 2025-11-14 20:25:57 +0900 |
| commit | 5949d419c193ce8e285acfbaafad88efe87f9dfa (patch) | |
| tree | b582bec6f02f2526861942c9c9cf5484ddf4a26e /drivers/gpu/nova-core/firmware | |
| parent | 945c1eee7dbeb0dcafc9d151eaa46a4273d386fa (diff) | |
gpu: nova-core: gsp: Boot GSP
Boot the GSP to the RISC-V active state. Completing the boot requires
running the CPU sequencer which will be added in a future commit.
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Alistair Popple <apopple@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Message-ID: <20251110-gsp_boot-v9-15-8ae4058e3c0e@nvidia.com>
Diffstat (limited to 'drivers/gpu/nova-core/firmware')
| -rw-r--r-- | drivers/gpu/nova-core/firmware/riscv.rs | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/gpu/nova-core/firmware/riscv.rs b/drivers/gpu/nova-core/firmware/riscv.rs index 7d82fb9876e8..28dfef63657a 100644 --- a/drivers/gpu/nova-core/firmware/riscv.rs +++ b/drivers/gpu/nova-core/firmware/riscv.rs @@ -57,7 +57,6 @@ impl RmRiscvUCodeDesc { } /// A parsed firmware for a RISC-V core, ready to be loaded and run. -#[expect(unused)] pub(crate) struct RiscvFirmware { /// Offset at which the code starts in the firmware image. pub(crate) code_offset: u32, @@ -66,7 +65,7 @@ pub(crate) struct RiscvFirmware { /// Offset at which the manifest starts in the firmware image. pub(crate) manifest_offset: u32, /// Application version. - app_version: u32, + pub(crate) app_version: u32, /// Device-mapped firmware image. pub(crate) ucode: DmaObject, } |