Merge tag 'iommu-updates-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux

Pull iommu updates from Will Deacon:
 "Core:
   - Remove the 'pgsize_bitmap' member from 'struct iommu_ops'
   - Convert the x86 drivers over to msi_create_parent_irq_domain()

  AMD-Vi:
   - Add support for examining driver/device internals via debugfs
   - Add support for "HATDis" to disable host translation when it is not
     supported
   - Add support for limiting the maximum host translation level based
     on EFR[HATS]

  Apple DART:
   - Don't enable as built-in by default when ARCH_APPLE is selected

  Arm SMMU:
   - Devicetree bindings update for the Qualcomm SMMU in the "Milos" SoC
   - Support for Qualcomm SM6115 MDSS parts
   - Disable PRR on Qualcomm SM8250 as using these bits causes the
     hypervisor to explode

  Intel VT-d:
   - Reorganize Intel VT-d to be ready for iommupt
   - Optimize iotlb_sync_map for non-caching/non-RWBF modes
   - Fix missed PASID in dev TLB invalidation in cache_tag_flush_all()

  Mediatek:
   - Fix build warnings when W=1

  Samsung Exynos:
   - Add support for reserved memory regions specified by the bootloader

  TI OMAP:
   - Use syscon_regmap_lookup_by_phandle_args() instead of parsing the
     node manually

  Misc:
   - Cleanups and minor fixes across the board"

* tag 'iommu-updates-v6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (48 commits)
  iommu/vt-d: Fix UAF on sva unbind with pending IOPFs
  iommu/vt-d: Make iotlb_sync_map a static property of dmar_domain
  dt-bindings: arm-smmu: Remove sdm845-cheza specific entry
  iommu/amd: Fix geometry.aperture_end for V2 tables
  iommu/amd: Wrap debugfs ABI testing symbols snippets in literal code blocks
  iommu/amd: Add documentation for AMD IOMMU debugfs support
  iommu/amd: Add debugfs support to dump IRT Table
  iommu/amd: Add debugfs support to dump device table
  iommu/amd: Add support for device id user input
  iommu/amd: Add debugfs support to dump IOMMU command buffer
  iommu/amd: Add debugfs support to dump IOMMU Capability registers
  iommu/amd: Add debugfs support to dump IOMMU MMIO registers
  iommu/amd: Refactor AMD IOMMU debugfs initial setup
  dt-bindings: arm-smmu: document the support on Milos
  iommu/exynos: add support for reserved regions
  iommu/arm-smmu: disable PRR on SM8250
  iommu/arm-smmu-v3: Revert vmaster in the error path
  iommu/io-pgtable-arm: Remove unused macro iopte_prot
  iommu/arm-smmu-qcom: Add SM6115 MDSS compatible
  iommu/qcom: Fix pgsize_bitmap
  ...

1 files changed, 11 insertions, 44 deletions

diff --git a/drivers/iommu/intel/cache.c b/drivers/iommu/intel/cache.c
index 47692cbfaabd..265e7290256b 100644
--- a/drivers/iommu/intel/cache.c
+++ b/drivers/iommu/intel/cache.c
@@ -370,7 +370,7 @@ static void cache_tag_flush_iotlb(struct dmar_domain *domain, struct cache_tag *
 	struct intel_iommu *iommu = tag->iommu;
 	u64 type = DMA_TLB_PSI_FLUSH;
 
-	if (domain->use_first_level) {
+	if (intel_domain_is_fs_paging(domain)) {
 		qi_batch_add_piotlb(iommu, tag->domain_id, tag->pasid, addr,
 				    pages, ih, domain->qi_batch);
 		return;
@@ -422,22 +422,6 @@ static void cache_tag_flush_devtlb_psi(struct dmar_domain *domain, struct cache_
 					     domain->qi_batch);
 }
 
-static void cache_tag_flush_devtlb_all(struct dmar_domain *domain, struct cache_tag *tag)
-{
-	struct intel_iommu *iommu = tag->iommu;
-	struct device_domain_info *info;
-	u16 sid;
-
-	info = dev_iommu_priv_get(tag->dev);
-	sid = PCI_DEVID(info->bus, info->devfn);
-
-	qi_batch_add_dev_iotlb(iommu, sid, info->pfsid, info->ats_qdep, 0,
-			       MAX_AGAW_PFN_WIDTH, domain->qi_batch);
-	if (info->dtlb_extra_inval)
-		qi_batch_add_dev_iotlb(iommu, sid, info->pfsid, info->ats_qdep, 0,
-				       MAX_AGAW_PFN_WIDTH, domain->qi_batch);
-}
-
 /*
  * Invalidates a range of IOVA from @start (inclusive) to @end (inclusive)
  * when the memory mappings in the target domain have been modified.
@@ -450,7 +434,13 @@ void cache_tag_flush_range(struct dmar_domain *domain, unsigned long start,
 	struct cache_tag *tag;
 	unsigned long flags;
 
-	addr = calculate_psi_aligned_address(start, end, &pages, &mask);
+	if (start == 0 && end == ULONG_MAX) {
+		addr = 0;
+		pages = -1;
+		mask = MAX_AGAW_PFN_WIDTH;
+	} else {
+		addr = calculate_psi_aligned_address(start, end, &pages, &mask);
+	}
 
 	spin_lock_irqsave(&domain->cache_lock, flags);
 	list_for_each_entry(tag, &domain->cache_tags, node) {
@@ -491,31 +481,7 @@ void cache_tag_flush_range(struct dmar_domain *domain, unsigned long start,
  */
 void cache_tag_flush_all(struct dmar_domain *domain)
 {
-	struct intel_iommu *iommu = NULL;
-	struct cache_tag *tag;
-	unsigned long flags;
-
-	spin_lock_irqsave(&domain->cache_lock, flags);
-	list_for_each_entry(tag, &domain->cache_tags, node) {
-		if (iommu && iommu != tag->iommu)
-			qi_batch_flush_descs(iommu, domain->qi_batch);
-		iommu = tag->iommu;
-
-		switch (tag->type) {
-		case CACHE_TAG_IOTLB:
-		case CACHE_TAG_NESTING_IOTLB:
-			cache_tag_flush_iotlb(domain, tag, 0, -1, 0, 0);
-			break;
-		case CACHE_TAG_DEVTLB:
-		case CACHE_TAG_NESTING_DEVTLB:
-			cache_tag_flush_devtlb_all(domain, tag);
-			break;
-		}
-
-		trace_cache_tag_flush_all(tag);
-	}
-	qi_batch_flush_descs(iommu, domain->qi_batch);
-	spin_unlock_irqrestore(&domain->cache_lock, flags);
+	cache_tag_flush_range(domain, 0, ULONG_MAX, 0);
 }
 
 /*
@@ -545,7 +511,8 @@ void cache_tag_flush_range_np(struct dmar_domain *domain, unsigned long start,
 			qi_batch_flush_descs(iommu, domain->qi_batch);
 		iommu = tag->iommu;
 
-		if (!cap_caching_mode(iommu->cap) || domain->use_first_level) {
+		if (!cap_caching_mode(iommu->cap) ||
+		    intel_domain_is_fs_paging(domain)) {
 			iommu_flush_write_buffer(iommu);
 			continue;
 		}