diff options
| author | Tony Lindgren <tony@atomide.com> | 2018-11-08 09:32:24 -0800 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2018-11-08 09:32:24 -0800 |
| commit | 91e43395820baad80248987608216c35da9df65b (patch) | |
| tree | 29d41d1a036eb1abd6a60f16ad37aa578acd8159 /drivers/pci/controller/dwc/pcie-designware.h | |
| parent | eef3dc34a1e0b01d53328b88c25237bcc7323777 (diff) | |
| parent | cec83ff1241ec98113a19385ea9e9cfa9aa4125b (diff) | |
Merge branch 'fixes-dts' into omap-for-v4.20/fixes
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.h')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 96126fd8403c..0989d880ac46 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -26,8 +26,7 @@ /* Parameters for the waiting for iATU enabled routine */ #define LINK_WAIT_MAX_IATU_RETRIES 5 -#define LINK_WAIT_IATU_MIN 9000 -#define LINK_WAIT_IATU_MAX 10000 +#define LINK_WAIT_IATU 9 /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_LINK_CONTROL 0x710 @@ -37,6 +36,10 @@ #define PORT_LINK_MODE_4_LANES (0x7 << 16) #define PORT_LINK_MODE_8_LANES (0xf << 16) +#define PCIE_PORT_DEBUG0 0x728 +#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f +#define PORT_LOGIC_LTSSM_STATE_L0 0x11 + #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) |