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| author | Junhui Liu <junhui.liu@pigmoral.tech> | 2025-10-21 17:41:40 +0800 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2025-11-11 22:17:21 +0100 |
| commit | 579951da64253e9592d21e54b1535e0119df78ab (patch) | |
| tree | 3ef875122f813fd5ac35123efa07df40cf959bc4 /drivers/pci/controller/dwc/pcie-qcom-common.c | |
| parent | b90ac5fe3285aa8bed625375d1df959c4c9a2cdb (diff) | |
dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT MSWI
Add MSWI support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a
TIMER unit compliant with the ACLINT specification.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251021-dr1v90-basic-dt-v3-5-5478db4f664a@pigmoral.tech
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-qcom-common.c')
0 files changed, 0 insertions, 0 deletions