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authorRyan Chen <ryan_chen@aspeedtech.com>2025-10-30 14:01:55 +0800
committerThomas Gleixner <tglx@linutronix.de>2025-11-11 22:20:45 +0100
commit7083e142256f92d079d2749e002f2f2499e5f63c (patch)
tree9f7b4afb9edb88213b495dfe6ded6f42fba6d9bb /drivers/pci/controller/dwc/pcie-qcom-common.c
parent47a4ebbf91d31782113e7def707b53953bae3050 (diff)
dt-bindings: interrupt-controller: aspeed,ast2700: Correct #interrupt-cells and interrupts count
Update the AST2700 interrupt controller binding to match the actual hardware and the irq-aspeed-intc driver behavior. - Interrupts: First-level INTC banks request multiple interrupt lines to the root GIC, with a maximum of 10 per bank. Second-level INTC banks request only one interrupt line to their parent INTC-IC. Therefore, set the interrupts property to allow a minimum of 1 and a maximum of 10 entries. - #interrupt-cells: Set '#interrupt-cells' to <1> since the aspeed intc driver does not support specifying a trigger type; only the interrupt index is used. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251030060155.2342604-2-ryan_chen@aspeedtech.com
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-qcom-common.c')
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