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authorEric Biggers <ebiggers@kernel.org>2025-10-01 19:31:11 -0700
committerEric Biggers <ebiggers@kernel.org>2025-10-26 20:37:40 -0700
commitf65e90860679d39e01c8bf40b8c740d7ca61476c (patch)
tree9add4aa564cdb4ef708b845ecaac0de9e0c59aec /fs/proc/array.c
parentfae3b96ba6015c35a973da09bf313d90e4e4bb94 (diff)
crypto: x86/aes-gcm - remove VAES+AVX10/256 optimized code
Remove the VAES+AVX10/256 optimized implementation of AES-GCM. It's no longer expected to be useful for future CPUs, since Intel changed the AVX10 specification to require 512-bit vectors. In addition, it's no longer very useful to serve as the 256-bit fallback for older Intel CPUs (Ice Lake and Tiger Lake) that downclock too eagerly when 512-bit vectors are used. This is because I ended up writing another 256-bit implementation anyway, using VAES+AVX2. The VAES+AVX2 implementation is almost as fast as the VAES+AVX10/256 one, as shown by the following tables. So, let's just use it instead. Table 1: AES-256-GCM encryption throughput change, CPU vs. message length in bytes: | 16384 | 4096 | 4095 | 1420 | 512 | 500 | ----------------------+-------+-------+-------+-------+-------+-------+ Intel Ice Lake Server | -2% | -1% | 0% | -2% | -2% | 3% | | 300 | 200 | 64 | 63 | 16 | ----------------------+-------+-------+-------+-------+-------+ Intel Ice Lake Server | 1% | 0% | 4% | 2% | -6% | Table 2: AES-256-GCM decryption throughput change, CPU vs. message length in bytes: | 16384 | 4096 | 4095 | 1420 | 512 | 500 | ----------------------+-------+-------+-------+-------+-------+-------+ Intel Ice Lake Server | -1% | -1% | 1% | -2% | 0% | 2% | | 300 | 200 | 64 | 63 | 16 | ----------------------+-------+-------+-------+-------+-------+ Intel Ice Lake Server | -1% | 4% | 1% | 0% | -5% | Acked-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Ard Biesheuvel <ardb@kernel.org> Link: https://lore.kernel.org/r/20251002023117.37504-3-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
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