diff options
| author | Peter Bergner <bergner@brule.rchland.ibm.com> | 2003-03-31 01:44:08 -0600 |
|---|---|---|
| committer | Peter Bergner <bergner@brule.rchland.ibm.com> | 2003-03-31 01:44:08 -0600 |
| commit | a2c584bb26012d197f52ee53a5a3728f08dd283f (patch) | |
| tree | 632f25e64ad030fafbbb85f05ef61c00a53fe52c /include/asm-ppc64/processor.h | |
| parent | c03cd46714957945017a69664f1a1f2f646d74ce (diff) | |
| parent | b9c4e8df932dbf7cb5abf76df3be1e18a0ac2b56 (diff) | |
Merge bk://ppc.bkbits.net/for-linus-ppc64
into brule.rchland.ibm.com:/u3/ppc64/linux-2.5-bergner
Diffstat (limited to 'include/asm-ppc64/processor.h')
| -rw-r--r-- | include/asm-ppc64/processor.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h index 822d15ead564..a2342b779dcc 100644 --- a/include/asm-ppc64/processor.h +++ b/include/asm-ppc64/processor.h @@ -469,8 +469,6 @@ #define IOCR_SPC 0x00000001 -/* Processor Version Register */ - /* Processor Version Register (PVR) field extraction */ #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ @@ -656,8 +654,10 @@ struct thread_struct { struct pt_regs *regs; /* Pointer to saved register state */ mm_segment_t fs; /* for get_fs() validation */ double fpr[32]; /* Complete floating point set */ - unsigned long fpscr; /* Floating point status */ - unsigned int fpexc_mode; /* Floating-point exception mode */ + unsigned long fpscr; /* Floating point status (plus pad) */ + unsigned long fpexc_mode; /* Floating-point exception mode */ + unsigned long saved_msr; /* Save MSR across signal handlers */ + unsigned long saved_softe; /* Ditto for Soft Enable/Disable */ }; #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) @@ -704,7 +704,7 @@ static inline unsigned int __unpack_fe01(unsigned long msr_bits) return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); } -static inline unsigned int __pack_fe01(unsigned int fpmode) +static inline unsigned long __pack_fe01(unsigned int fpmode) { return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); } |