[PPC32] Merge MPC52xx changes with recent CPM changes.

11 files changed, 606 insertions, 17 deletions

diff --git a/include/asm-ppc/highmem.h b/include/asm-ppc/highmem.h
index aa3e74516808..928f8447ae7f 100644
--- a/include/asm-ppc/highmem.h
+++ b/include/asm-ppc/highmem.h
@@ -91,7 +91,7 @@ static inline void *kmap_atomic(struct page *page, enum km_type type)
 	BUG_ON(!pte_none(*(kmap_pte+idx)));
 #endif
 	set_pte(kmap_pte+idx, mk_pte(page, kmap_prot));
-	flush_tlb_page(0, vaddr);
+	flush_tlb_page(NULL, vaddr);
 
 	return (void*) vaddr;
 }
@@ -115,7 +115,7 @@ static inline void kunmap_atomic(void *kvaddr, enum km_type type)
 	 * this pte without first remap it
 	 */
 	pte_clear(kmap_pte+idx);
-	flush_tlb_page(0, vaddr);
+	flush_tlb_page(NULL, vaddr);
 #endif
 	dec_preempt_count();
 	preempt_check_resched();
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 2717a607de27..a893418be84c 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -237,7 +237,7 @@ extern inline void * bus_to_virt(unsigned long address)
 {
 #ifndef CONFIG_APUS
         if (address == 0)
-		return 0;
+		return NULL;
         return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
 #else
 	return (void*) mm_ptov (address);
diff --git a/include/asm-ppc/mpc52xx.h b/include/asm-ppc/mpc52xx.h
new file mode 100644
index 000000000000..4fb6e572b841
--- /dev/null
+++ b/include/asm-ppc/mpc52xx.h
@@ -0,0 +1,380 @@
+/*
+ * include/asm-ppc/mpc52xx.h
+ * 
+ * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
+ * May need to be cleaned as the port goes on ...
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Originally written by Dale Farnsworth <dfarnsworth@mvista.com> 
+ * for the 2.4 kernel.
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_MPC52xx_H__
+#define __ASM_MPC52xx_H__
+
+#ifndef __ASSEMBLY__
+#include <asm/ppcboot.h>
+#include <asm/types.h>
+
+struct pt_regs;
+struct ocp_def;
+#endif /* __ASSEMBLY__ */
+
+
+/* ======================================================================== */
+/* Main registers/struct addresses                                          */
+/* ======================================================================== */
+/* Theses are PHYSICAL addresses !                                          */
+/* TODO : There should be no static mapping, but it's not yet the case, so  */
+/*        we require a 1:1 mapping                                          */
+
+#define MPC52xx_MBAR		0xf0000000	/* Phys address */
+#define MPC52xx_MBAR_SIZE	0x00010000
+#define MPC52xx_MBAR_VIRT	0xf0000000	/* Virt address */
+
+#define MPC52xx_MMAP_CTL	(MPC52xx_MBAR + 0x0000)
+#define MPC52xx_CDM		(MPC52xx_MBAR + 0x0200)
+#define MPC52xx_SFTRST		(MPC52xx_MBAR + 0x0220)
+#define MPC52xx_SFTRST_BIT	0x01000000
+#define MPC52xx_INTR		(MPC52xx_MBAR + 0x0500)
+#define MPC52xx_GPTx(x)		(MPC52xx_MBAR + 0x0600 + ((x)<<4))
+#define MPC52xx_RTC		(MPC52xx_MBAR + 0x0800)
+#define MPC52xx_MSCAN1		(MPC52xx_MBAR + 0x0900)
+#define MPC52xx_MSCAN2		(MPC52xx_MBAR + 0x0980)
+#define MPC52xx_GPIO		(MPC52xx_MBAR + 0x0b00)
+#define MPC52xx_PCI		(MPC52xx_MBAR + 0x0d00)
+#define MPC52xx_USB_OHCI	(MPC52xx_MBAR + 0x1000)
+#define MPC52xx_SDMA		(MPC52xx_MBAR + 0x1200)
+#define MPC52xx_XLB		(MPC52xx_MBAR + 0x1f00)
+#define MPC52xx_PSCx(x)		(MPC52xx_MBAR + 0x2000 + ((x)<<9))
+#define MPC52xx_PSC1		(MPC52xx_MBAR + 0x2000)
+#define MPC52xx_PSC2		(MPC52xx_MBAR + 0x2200)
+#define MPC52xx_PSC3		(MPC52xx_MBAR + 0x2400)
+#define MPC52xx_PSC4		(MPC52xx_MBAR + 0x2600)
+#define MPC52xx_PSC5		(MPC52xx_MBAR + 0x2800)
+#define MPC52xx_PSC6		(MPC52xx_MBAR + 0x2C00)
+#define MPC52xx_FEC		(MPC52xx_MBAR + 0x3000)
+#define MPC52xx_ATA		(MPC52xx_MBAR + 0x3a00)
+#define MPC52xx_I2C1		(MPC52xx_MBAR + 0x3d00)
+#define MPC52xx_I2C_MICR	(MPC52xx_MBAR + 0x3d20)
+#define MPC52xx_I2C2		(MPC52xx_MBAR + 0x3d40)
+
+/* SRAM used for SDMA */
+#define MPC52xx_SRAM		(MPC52xx_MBAR + 0x8000)
+#define MPC52xx_SRAM_SIZE	(16*1024)
+#define MPC52xx_SDMA_MAX_TASKS	16
+
+	/* Memory allocation block size */
+#define MPC52xx_SDRAM_UNIT	0x8000		/* 32K byte */
+
+
+/* ======================================================================== */
+/* IRQ mapping                                                              */
+/* ======================================================================== */
+/* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change
+ * this
+ */
+
+#define MPC52xx_CRIT_IRQ_NUM	4
+#define MPC52xx_MAIN_IRQ_NUM	17
+#define MPC52xx_SDMA_IRQ_NUM	17
+#define MPC52xx_PERP_IRQ_NUM	23
+
+#define MPC52xx_CRIT_IRQ_BASE	0
+#define MPC52xx_MAIN_IRQ_BASE	(MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
+#define MPC52xx_SDMA_IRQ_BASE	(MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
+#define MPC52xx_PERP_IRQ_BASE	(MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
+
+#define MPC52xx_IRQ0			(MPC52xx_CRIT_IRQ_BASE + 0)
+#define MPC52xx_SLICE_TIMER_0_IRQ	(MPC52xx_CRIT_IRQ_BASE + 1)
+#define MPC52xx_HI_INT_IRQ		(MPC52xx_CRIT_IRQ_BASE + 2)
+#define MPC52xx_CCS_IRQ			(MPC52xx_CRIT_IRQ_BASE + 3)
+
+#define MPC52xx_IRQ1			(MPC52xx_MAIN_IRQ_BASE + 1)
+#define MPC52xx_IRQ2			(MPC52xx_MAIN_IRQ_BASE + 2)
+#define MPC52xx_IRQ3			(MPC52xx_MAIN_IRQ_BASE + 3)
+
+#define MPC52xx_SDMA_IRQ		(MPC52xx_PERP_IRQ_BASE + 0)
+#define MPC52xx_PSC1_IRQ		(MPC52xx_PERP_IRQ_BASE + 1)
+#define MPC52xx_PSC2_IRQ		(MPC52xx_PERP_IRQ_BASE + 2)
+#define MPC52xx_PSC3_IRQ		(MPC52xx_PERP_IRQ_BASE + 3)
+#define MPC52xx_PSC6_IRQ		(MPC52xx_PERP_IRQ_BASE + 4)
+#define MPC52xx_IRDA_IRQ		(MPC52xx_PERP_IRQ_BASE + 4)
+#define MPC52xx_FEC_IRQ			(MPC52xx_PERP_IRQ_BASE + 5)
+#define MPC52xx_USB_IRQ			(MPC52xx_PERP_IRQ_BASE + 6)
+#define MPC52xx_ATA_IRQ			(MPC52xx_PERP_IRQ_BASE + 7)
+#define MPC52xx_PCI_CNTRL_IRQ		(MPC52xx_PERP_IRQ_BASE + 8)
+#define MPC52xx_PCI_SCIRX_IRQ		(MPC52xx_PERP_IRQ_BASE + 9)
+#define MPC52xx_PCI_SCITX_IRQ		(MPC52xx_PERP_IRQ_BASE + 10)
+#define MPC52xx_PSC4_IRQ		(MPC52xx_PERP_IRQ_BASE + 11)
+#define MPC52xx_PSC5_IRQ		(MPC52xx_PERP_IRQ_BASE + 12)
+#define MPC52xx_SPI_MODF_IRQ		(MPC52xx_PERP_IRQ_BASE + 13)
+#define MPC52xx_SPI_SPIF_IRQ		(MPC52xx_PERP_IRQ_BASE + 14)
+#define MPC52xx_I2C1_IRQ		(MPC52xx_PERP_IRQ_BASE + 15)
+#define MPC52xx_I2C2_IRQ		(MPC52xx_PERP_IRQ_BASE + 16)
+#define MPC52xx_CAN1_IRQ		(MPC52xx_PERP_IRQ_BASE + 17)
+#define MPC52xx_CAN2_IRQ		(MPC52xx_PERP_IRQ_BASE + 18)
+#define MPC52xx_IR_RX_IRQ		(MPC52xx_PERP_IRQ_BASE + 19)
+#define MPC52xx_IR_TX_IRQ		(MPC52xx_PERP_IRQ_BASE + 20)
+#define MPC52xx_XLB_ARB_IRQ		(MPC52xx_PERP_IRQ_BASE + 21)
+
+
+
+/* ======================================================================== */
+/* Structures mapping of some unit register set                             */
+/* ======================================================================== */
+
+#ifndef __ASSEMBLY__
+
+/* Memory Mapping Control */
+struct mpc52xx_mmap_ctl {
+	volatile u32	mbar;		/* MMAP_CTRL + 0x00 */
+
+	volatile u32	cs0_start;	/* MMAP_CTRL + 0x04 */
+	volatile u32	cs0_stop;	/* MMAP_CTRL + 0x08 */
+	volatile u32	cs1_start;	/* MMAP_CTRL + 0x0c */
+	volatile u32	cs1_stop;	/* MMAP_CTRL + 0x10 */
+	volatile u32	cs2_start;	/* MMAP_CTRL + 0x14 */
+	volatile u32	cs2_stop;	/* MMAP_CTRL + 0x18 */
+	volatile u32	cs3_start;	/* MMAP_CTRL + 0x1c */
+	volatile u32	cs3_stop;	/* MMAP_CTRL + 0x20 */
+	volatile u32	cs4_start;	/* MMAP_CTRL + 0x24 */
+	volatile u32	cs4_stop;	/* MMAP_CTRL + 0x28 */
+	volatile u32	cs5_start;	/* MMAP_CTRL + 0x2c */
+	volatile u32	cs5_stop;	/* MMAP_CTRL + 0x30 */
+
+	volatile u32	sdram0;		/* MMAP_CTRL + 0x34 */
+	volatile u32	sdram1;		/* MMAP_CTRL + 0X38 */
+
+	volatile u32	reserved[4];	/* MMAP_CTRL + 0x3c .. 0x48 */
+
+	volatile u32	boot_start;	/* MMAP_CTRL + 0x4c */
+	volatile u32	boot_stop;	/* MMAP_CTRL + 0x50 */
+	
+	volatile u32	ipbi_ws_ctrl;	/* MMAP_CTRL + 0x54 */
+	
+	volatile u32	cs6_start;	/* MMAP_CTRL + 0x58 */
+	volatile u32	cs6_stop;	/* MMAP_CTRL + 0x5c */
+	volatile u32	cs7_start;	/* MMAP_CTRL + 0x60 */
+	volatile u32	cs7_stop;	/* MMAP_CTRL + 0x60 */
+};
+
+/* Interrupt controller */
+struct mpc52xx_intr {
+	volatile u32	per_mask;	/* INTR + 0x00 */
+	volatile u32	per_pri1;	/* INTR + 0x04 */
+	volatile u32	per_pri2;	/* INTR + 0x08 */
+	volatile u32	per_pri3;	/* INTR + 0x0c */
+	volatile u32	ctrl;		/* INTR + 0x10 */
+	volatile u32	main_mask;	/* INTR + 0x14 */
+	volatile u32	main_pri1;	/* INTR + 0x18 */
+	volatile u32	main_pri2;	/* INTR + 0x1c */
+	volatile u32	reserved1;	/* INTR + 0x20 */
+	volatile u32	enc_status;	/* INTR + 0x24 */
+	volatile u32	crit_status;	/* INTR + 0x28 */
+	volatile u32	main_status;	/* INTR + 0x2c */
+	volatile u32	per_status;	/* INTR + 0x30 */
+	volatile u32	reserved2;	/* INTR + 0x34 */
+	volatile u32	per_error;	/* INTR + 0x38 */
+};
+
+/* SDMA */
+struct mpc52xx_sdma {
+	volatile u32	taskBar;	/* SDMA + 0x00 */
+	volatile u32	currentPointer;	/* SDMA + 0x04 */
+	volatile u32	endPointer;	/* SDMA + 0x08 */
+	volatile u32	variablePointer;/* SDMA + 0x0c */
+
+	volatile u8	IntVect1;	/* SDMA + 0x10 */
+	volatile u8	IntVect2;	/* SDMA + 0x11 */
+	volatile u16	PtdCntrl;	/* SDMA + 0x12 */
+
+	volatile u32	IntPend;	/* SDMA + 0x14 */
+	volatile u32	IntMask;	/* SDMA + 0x18 */
+	
+	volatile u16	tcr[16];	/* SDMA + 0x1c .. 0x3a */
+
+	volatile u8	ipr[31];	/* SDMA + 0x3c .. 5b */
+
+	volatile u32	res1;		/* SDMA + 0x5c */
+	volatile u32	task_size0;	/* SDMA + 0x60 */
+	volatile u32	task_size1;	/* SDMA + 0x64 */
+	volatile u32	MDEDebug;	/* SDMA + 0x68 */
+	volatile u32	ADSDebug;	/* SDMA + 0x6c */
+	volatile u32	Value1;		/* SDMA + 0x70 */
+	volatile u32	Value2;		/* SDMA + 0x74 */
+	volatile u32	Control;	/* SDMA + 0x78 */
+	volatile u32	Status;		/* SDMA + 0x7c */
+};
+
+/* GPT */
+struct mpc52xx_gpt {
+	volatile u32	mode;		/* GPTx + 0x00 */
+	volatile u32	count;		/* GPTx + 0x04 */
+	volatile u32	pwm;		/* GPTx + 0x08 */
+	volatile u32	status;		/* GPTx + 0X0c */
+};
+
+/* RTC */
+struct mpc52xx_rtc {
+	volatile u32	time_set;	/* RTC + 0x00 */
+	volatile u32	date_set;	/* RTC + 0x04 */
+	volatile u32	stopwatch;	/* RTC + 0x08 */
+	volatile u32	int_enable;	/* RTC + 0x0c */
+	volatile u32	time;		/* RTC + 0x10 */
+	volatile u32	date;		/* RTC + 0x14 */
+	volatile u32	stopwatch_intr;	/* RTC + 0x18 */
+	volatile u32	bus_error;	/* RTC + 0x1c */
+	volatile u32	dividers;	/* RTC + 0x20 */
+};
+
+/* GPIO */
+struct mpc52xx_gpio {
+	volatile u32	port_config;	/* GPIO + 0x00 */
+	volatile u32	simple_gpioe;	/* GPIO + 0x04 */
+	volatile u32	simple_ode;	/* GPIO + 0x08 */
+	volatile u32	simple_ddr;	/* GPIO + 0x0c */
+	volatile u32	simple_dvo;	/* GPIO + 0x10 */
+	volatile u32	simple_ival;	/* GPIO + 0x14 */
+	volatile u8	outo_gpioe;	/* GPIO + 0x18 */
+	volatile u8	reserved1[3];	/* GPIO + 0x19 */
+	volatile u8	outo_dvo;	/* GPIO + 0x1c */
+	volatile u8	reserved2[3];	/* GPIO + 0x1d */
+	volatile u8	sint_gpioe;	/* GPIO + 0x20 */
+	volatile u8	reserved3[3];	/* GPIO + 0x21 */
+	volatile u8	sint_ode;	/* GPIO + 0x24 */
+	volatile u8	reserved4[3];	/* GPIO + 0x25 */
+	volatile u8	sint_ddr;	/* GPIO + 0x28 */
+	volatile u8	reserved5[3];	/* GPIO + 0x29 */
+	volatile u8	sint_dvo;	/* GPIO + 0x2c */
+	volatile u8	reserved6[3];	/* GPIO + 0x2d */
+	volatile u8	sint_inten;	/* GPIO + 0x30 */
+	volatile u8	reserved7[3];	/* GPIO + 0x31 */
+	volatile u16	sint_itype;	/* GPIO + 0x34 */
+	volatile u16	reserved8;	/* GPIO + 0x36 */
+	volatile u8	gpio_control;	/* GPIO + 0x38 */
+	volatile u8	reserved9[3];	/* GPIO + 0x39 */
+	volatile u8	sint_istat;	/* GPIO + 0x3c */
+	volatile u8	sint_ival;	/* GPIO + 0x3d */
+	volatile u8	bus_errs;	/* GPIO + 0x3e */
+	volatile u8	reserved10;	/* GPIO + 0x3f */
+};
+
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD	4
+#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD	5
+#define MPC52xx_GPIO_PCI_DIS			(1<<15)
+
+/* XLB Bus control */
+struct mpc52xx_xlb {
+	volatile u8 reserved[0x40];
+	volatile u32 config;		/* XLB + 0x40 */
+	volatile u32 version;		/* XLB + 0x44 */
+	volatile u32 status;		/* XLB + 0x48 */
+	volatile u32 int_enable;	/* XLB + 0x4c */
+	volatile u32 addr_capture;	/* XLB + 0x50 */
+	volatile u32 bus_sig_capture;	/* XLB + 0x54 */
+	volatile u32 addr_timeout;	/* XLB + 0x58 */
+	volatile u32 data_timeout;	/* XLB + 0x5c */
+	volatile u32 bus_act_timeout;	/* XLB + 0x60 */
+	volatile u32 master_pri_enable;	/* XLB + 0x64 */
+	volatile u32 master_priority;	/* XLB + 0x68 */
+	volatile u32 base_address;	/* XLB + 0x6c */
+	volatile u32 snoop_window;	/* XLB + 0x70 */
+};
+
+
+/* Clock Distribution control */
+struct mpc52xx_cdm {
+	volatile u32	jtag_id;	/* MBAR_CDM + 0x00  reg0 read only */
+	volatile u32	rstcfg;		/* MBAR_CDM + 0x04  reg1 read only */
+	volatile u32	breadcrumb;	/* MBAR_CDM + 0x08  reg2 */
+
+	volatile u8	mem_clk_sel;	/* MBAR_CDM + 0x0c  reg3 byte0 */
+	volatile u8	xlb_clk_sel;	/* MBAR_CDM + 0x0d  reg3 byte1 read only */
+	volatile u8	ipb_clk_sel;	/* MBAR_CDM + 0x0e  reg3 byte2 */
+	volatile u8	pci_clk_sel;	/* MBAR_CDM + 0x0f  reg3 byte3 */
+
+	volatile u8	ext_48mhz_en;	/* MBAR_CDM + 0x10  reg4 byte0 */
+	volatile u8	fd_enable;	/* MBAR_CDM + 0x11  reg4 byte1 */
+	volatile u16	fd_counters;	/* MBAR_CDM + 0x12  reg4 byte2,3 */
+
+	volatile u32	clk_enables;	/* MBAR_CDM + 0x14  reg5 */
+
+	volatile u8	osc_disable;	/* MBAR_CDM + 0x18  reg6 byte0 */
+	volatile u8	reserved0[3];	/* MBAR_CDM + 0x19  reg6 byte1,2,3 */
+
+	volatile u8	ccs_sleep_enable;/* MBAR_CDM + 0x1c  reg7 byte0 */
+	volatile u8	osc_sleep_enable;/* MBAR_CDM + 0x1d  reg7 byte1 */
+	volatile u8	reserved1;	/* MBAR_CDM + 0x1e  reg7 byte2 */
+	volatile u8	ccs_qreq_test;	/* MBAR_CDM + 0x1f  reg7 byte3 */
+
+	volatile u8	soft_reset;	/* MBAR_CDM + 0x20  u8 byte0 */
+	volatile u8	no_ckstp;	/* MBAR_CDM + 0x21  u8 byte0 */
+	volatile u8	reserved2[2];	/* MBAR_CDM + 0x22  u8 byte1,2,3 */
+
+	volatile u8	pll_lock;	/* MBAR_CDM + 0x24  reg9 byte0 */
+	volatile u8	pll_looselock;	/* MBAR_CDM + 0x25  reg9 byte1 */
+	volatile u8	pll_sm_lockwin;	/* MBAR_CDM + 0x26  reg9 byte2 */
+	volatile u8	reserved3;	/* MBAR_CDM + 0x27  reg9 byte3 */
+
+	volatile u16	reserved4;	/* MBAR_CDM + 0x28  reg10 byte0,1 */
+	volatile u16	mclken_div_psc1;/* MBAR_CDM + 0x2a  reg10 byte2,3 */
+    
+	volatile u16	reserved5;	/* MBAR_CDM + 0x2c  reg11 byte0,1 */
+	volatile u16	mclken_div_psc2;/* MBAR_CDM + 0x2e  reg11 byte2,3 */
+		
+	volatile u16	reserved6;	/* MBAR_CDM + 0x30  reg12 byte0,1 */
+	volatile u16	mclken_div_psc3;/* MBAR_CDM + 0x32  reg12 byte2,3 */
+    
+	volatile u16	reserved7;	/* MBAR_CDM + 0x34  reg13 byte0,1 */
+	volatile u16	mclken_div_psc6;/* MBAR_CDM + 0x36  reg13 byte2,3 */
+};
+
+#endif /* __ASSEMBLY__ */
+
+
+/* ========================================================================= */
+/* Prototypes for MPC52xx syslib                                             */
+/* ========================================================================= */
+
+#ifndef __ASSEMBLY__
+
+extern void mpc52xx_init_irq(void);
+extern int mpc52xx_get_irq(struct pt_regs *regs);
+
+extern unsigned long mpc52xx_find_end_of_memory(void);
+extern void mpc52xx_set_bat(void);
+extern void mpc52xx_map_io(void);
+extern void mpc52xx_restart(char *cmd);
+extern void mpc52xx_halt(void);
+extern void mpc52xx_power_off(void);
+extern void mpc52xx_progress(char *s, unsigned short hex);
+extern void mpc52xx_calibrate_decr(void);
+extern void mpc52xx_add_board_devices(struct ocp_def board_ocp[]);
+
+#endif /* __ASSEMBLY__ */
+
+
+/* ========================================================================= */
+/* Platform configuration                                                    */
+/* ========================================================================= */
+
+/* The U-Boot platform information struct */
+extern bd_t __res;
+
+/* Platform options */
+#if defined(CONFIG_LITE5200)
+#include <platforms/lite5200.h>
+#endif
+
+
+#endif /* __ASM_MPC52xx_H__ */
diff --git a/include/asm-ppc/mpc52xx_psc.h b/include/asm-ppc/mpc52xx_psc.h
new file mode 100644
index 000000000000..483102ea6aae
--- /dev/null
+++ b/include/asm-ppc/mpc52xx_psc.h
@@ -0,0 +1,191 @@
+/*
+ * include/asm-ppc/mpc52xx_psc.h
+ * 
+ * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
+ * PSCs. Theses are shared between multiple drivers since a PSC can be
+ * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
+ *
+ *
+ * Maintainer : Sylvain Munaut <tnt@246tNt.com>
+ *
+ * Based/Extracted from some header of the 2.4 originally written by 
+ * Dale Farnsworth <dfarnsworth@mvista.com> 
+ *
+ * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
+ * Copyright (C) 2003 MontaVista, Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __MPC52xx_PSC_H__
+#define __MPC52xx_PSC_H__
+
+#include <asm/types.h>
+
+/* Max number of PSCs */
+#define MPC52xx_PSC_MAXNUM	6
+
+/* Programmable Serial Controller (PSC) status register bits */
+#define MPC52xx_PSC_SR_CDE	0x0080
+#define MPC52xx_PSC_SR_RXRDY	0x0100
+#define MPC52xx_PSC_SR_RXFULL	0x0200
+#define MPC52xx_PSC_SR_TXRDY	0x0400
+#define MPC52xx_PSC_SR_TXEMP	0x0800
+#define MPC52xx_PSC_SR_OE	0x1000
+#define MPC52xx_PSC_SR_PE	0x2000
+#define MPC52xx_PSC_SR_FE	0x4000
+#define MPC52xx_PSC_SR_RB	0x8000
+
+/* PSC Command values */
+#define MPC52xx_PSC_RX_ENABLE		0x0001
+#define MPC52xx_PSC_RX_DISABLE		0x0002
+#define MPC52xx_PSC_TX_ENABLE		0x0004
+#define MPC52xx_PSC_TX_DISABLE		0x0008
+#define MPC52xx_PSC_SEL_MODE_REG_1	0x0010
+#define MPC52xx_PSC_RST_RX		0x0020
+#define MPC52xx_PSC_RST_TX		0x0030
+#define MPC52xx_PSC_RST_ERR_STAT	0x0040
+#define MPC52xx_PSC_RST_BRK_CHG_INT	0x0050
+#define MPC52xx_PSC_START_BRK		0x0060
+#define MPC52xx_PSC_STOP_BRK		0x0070
+
+/* PSC TxRx FIFO status bits */
+#define MPC52xx_PSC_RXTX_FIFO_ERR	0x0040
+#define MPC52xx_PSC_RXTX_FIFO_UF	0x0020
+#define MPC52xx_PSC_RXTX_FIFO_OF	0x0010
+#define MPC52xx_PSC_RXTX_FIFO_FR	0x0008
+#define MPC52xx_PSC_RXTX_FIFO_FULL	0x0004
+#define MPC52xx_PSC_RXTX_FIFO_ALARM	0x0002
+#define MPC52xx_PSC_RXTX_FIFO_EMPTY	0x0001
+
+/* PSC interrupt mask bits */
+#define MPC52xx_PSC_IMR_TXRDY		0x0100
+#define MPC52xx_PSC_IMR_RXRDY		0x0200
+#define MPC52xx_PSC_IMR_DB		0x0400
+#define MPC52xx_PSC_IMR_IPC		0x8000
+
+/* PSC input port change bit */
+#define MPC52xx_PSC_CTS			0x01
+#define MPC52xx_PSC_DCD			0x02
+#define MPC52xx_PSC_D_CTS		0x10
+#define MPC52xx_PSC_D_DCD		0x20
+
+/* PSC mode fields */
+#define MPC52xx_PSC_MODE_5_BITS			0x00
+#define MPC52xx_PSC_MODE_6_BITS			0x01
+#define MPC52xx_PSC_MODE_7_BITS			0x02
+#define MPC52xx_PSC_MODE_8_BITS			0x03
+#define MPC52xx_PSC_MODE_BITS_MASK		0x03
+#define MPC52xx_PSC_MODE_PAREVEN		0x00
+#define MPC52xx_PSC_MODE_PARODD			0x04
+#define MPC52xx_PSC_MODE_PARFORCE		0x08
+#define MPC52xx_PSC_MODE_PARNONE		0x10
+#define MPC52xx_PSC_MODE_ERR			0x20
+#define MPC52xx_PSC_MODE_FFULL			0x40
+#define MPC52xx_PSC_MODE_RXRTS			0x80
+
+#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS	0x00
+#define MPC52xx_PSC_MODE_ONE_STOP		0x07
+#define MPC52xx_PSC_MODE_TWO_STOP		0x0f
+
+#define MPC52xx_PSC_RFNUM_MASK	0x01ff
+
+
+/* Structure of the hardware registers */
+struct mpc52xx_psc {
+	volatile u8		mode;		/* PSC + 0x00 */
+	volatile u8		reserved0[3];
+	union {					/* PSC + 0x04 */
+		volatile u16	status;
+		volatile u16	clock_select;
+	} sr_csr;
+#define mpc52xx_psc_status	sr_csr.status
+#define mpc52xx_psc_clock_select	sr_csr.clock_select
+	volatile u16		reserved1;
+	volatile u8		command;	/* PSC + 0x08 */
+volatile u8		reserved2[3];
+	union {					/* PSC + 0x0c */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} buffer;
+#define mpc52xx_psc_buffer_8	buffer.buffer_8
+#define mpc52xx_psc_buffer_16	buffer.buffer_16
+#define mpc52xx_psc_buffer_32	buffer.buffer_32
+	union {					/* PSC + 0x10 */
+		volatile u8	ipcr;
+		volatile u8	acr;
+	} ipcr_acr;
+#define mpc52xx_psc_ipcr	ipcr_acr.ipcr
+#define mpc52xx_psc_acr		ipcr_acr.acr
+	volatile u8		reserved3[3];
+	union {					/* PSC + 0x14 */
+		volatile u16	isr;
+		volatile u16	imr;
+	} isr_imr;
+#define mpc52xx_psc_isr		isr_imr.isr
+#define mpc52xx_psc_imr		isr_imr.imr
+	volatile u16		reserved4;
+	volatile u8		ctur;		/* PSC + 0x18 */
+	volatile u8		reserved5[3];
+	volatile u8		ctlr;		/* PSC + 0x1c */
+	volatile u8		reserved6[3];
+	volatile u16		ccr;		/* PSC + 0x20 */
+	volatile u8		reserved7[14];
+	volatile u8		ivr;		/* PSC + 0x30 */
+	volatile u8		reserved8[3];
+	volatile u8		ip;		/* PSC + 0x34 */
+	volatile u8		reserved9[3];
+	volatile u8		op1;		/* PSC + 0x38 */
+	volatile u8		reserved10[3];
+	volatile u8		op0;		/* PSC + 0x3c */
+	volatile u8		reserved11[3];
+	volatile u32		sicr;		/* PSC + 0x40 */
+	volatile u8		ircr1;		/* PSC + 0x44 */
+	volatile u8		reserved13[3];
+	volatile u8		ircr2;		/* PSC + 0x44 */
+	volatile u8		reserved14[3];
+	volatile u8		irsdr;		/* PSC + 0x4c */
+	volatile u8		reserved15[3];
+	volatile u8		irmdr;		/* PSC + 0x50 */
+	volatile u8		reserved16[3];
+	volatile u8		irfdr;		/* PSC + 0x54 */
+	volatile u8		reserved17[3];
+	volatile u16		rfnum;		/* PSC + 0x58 */
+	volatile u16		reserved18;
+	volatile u16		tfnum;		/* PSC + 0x5c */
+	volatile u16		reserved19;
+	volatile u32		rfdata;		/* PSC + 0x60 */
+	volatile u16		rfstat;		/* PSC + 0x64 */
+	volatile u16		reserved20;
+	volatile u8		rfcntl;		/* PSC + 0x68 */
+	volatile u8		reserved21[5];
+	volatile u16		rfalarm;	/* PSC + 0x6e */
+	volatile u16		reserved22;
+	volatile u16		rfrptr;		/* PSC + 0x72 */
+	volatile u16		reserved23;
+	volatile u16		rfwptr;		/* PSC + 0x76 */
+	volatile u16		reserved24;
+	volatile u16		rflrfptr;	/* PSC + 0x7a */
+	volatile u16		reserved25;
+	volatile u16		rflwfptr;	/* PSC + 0x7e */
+	volatile u32		tfdata;		/* PSC + 0x80 */
+	volatile u16		tfstat;		/* PSC + 0x84 */
+	volatile u16		reserved26;
+	volatile u8		tfcntl;		/* PSC + 0x88 */
+	volatile u8		reserved27[5];
+	volatile u16		tfalarm;	/* PSC + 0x8e */
+	volatile u16		reserved28;
+	volatile u16		tfrptr;		/* PSC + 0x92 */
+	volatile u16		reserved29;
+	volatile u16		tfwptr;		/* PSC + 0x96 */
+	volatile u16		reserved30;
+	volatile u16		tflrfptr;	/* PSC + 0x9a */
+	volatile u16		reserved31;
+	volatile u16		tflwfptr;	/* PSC + 0x9e */
+};
+
+
+#endif  /* __MPC52xx_PSC_H__ */
diff --git a/include/asm-ppc/ocp_ids.h b/include/asm-ppc/ocp_ids.h
index 5d4ad8a22906..91be19d2df7e 100644
--- a/include/asm-ppc/ocp_ids.h
+++ b/include/asm-ppc/ocp_ids.h
@@ -42,6 +42,7 @@
 #define OCP_FUNC_16550		0x0031
 #define OCP_FUNC_IIC		0x0032
 #define OCP_FUNC_USB		0x0033
+#define OCP_FUNC_PSC_UART	0x0034
 
 /* Memory devices 0x0090 - 0x009F */
 #define OCP_FUNC_MAL		0x0090
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
index df14f8650ab0..38d8edb1ba70 100644
--- a/include/asm-ppc/open_pic.h
+++ b/include/asm-ppc/open_pic.h
@@ -50,7 +50,7 @@ extern void do_openpic_setup_cpu(void);
 extern int openpic_get_irq(struct pt_regs *regs);
 extern void openpic_reset_processor_phys(u_int cpumask);
 extern void openpic_setup_ISU(int isu_num, unsigned long addr);
-extern void openpic_cause_IPI(u_int ipi, u_int cpumask);
+extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
 extern void smp_openpic_message_pass(int target, int msg, unsigned long data,
 				     int wait);
 extern void openpic_set_k2_cascade(int irq);
diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h
index b60773a78385..ca2c16b8c347 100644
--- a/include/asm-ppc/ppcboot.h
+++ b/include/asm-ppc/ppcboot.h
@@ -55,6 +55,9 @@ typedef struct bd_info {
 #if defined(CONFIG_8xx) || defined(CONFIG_CPM2) || defined(CONFIG_85xx)
 	unsigned long	bi_immr_base;	/* base of IMMR register */
 #endif
+#if defined(CONFIG_PPC_MPC52xx)
+	unsigned long   bi_mbar_base;   /* base of internal registers */
+#endif
 	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
 	unsigned long	bi_ip_addr;	/* IP Address */
 	unsigned char	bi_enetaddr[6];	/* Ethernet address */
@@ -67,6 +70,10 @@ typedef struct bd_info {
 	unsigned long	bi_sccfreq;	/* SCC_CLK Freq, in MHz */
 	unsigned long	bi_vco;		/* VCO Out from PLL, in MHz */
 #endif
+#if defined(CONFIG_PPC_MPC52xx)
+	unsigned long   bi_ipbfreq;     /* IPB Bus Freq, in MHz */
+	unsigned long   bi_pcifreq;     /* PCI Bus Freq, in MHz */
+#endif
 	unsigned long	bi_baudrate;	/* Console Baudrate */
 #if defined(CONFIG_405GP)
 	unsigned char	bi_s_version[4];	/* Version of this structure */
diff --git a/include/asm-ppc/reg.h b/include/asm-ppc/reg.h
index 15c93af4079a..73eab4528eb9 100644
--- a/include/asm-ppc/reg.h
+++ b/include/asm-ppc/reg.h
@@ -350,7 +350,7 @@
 #define DBAT6U	SPRN_DBAT6U	/* Data BAT 6 Upper Register */
 #define DBAT7L	SPRN_DBAT7L	/* Data BAT 7 Lower Register */
 #define DBAT7U	SPRN_DBAT7U	/* Data BAT 7 Upper Register */
-#define DEC	SPRN_DEC	/* Decrement Register */
+//#define DEC	SPRN_DEC	/* Decrement Register */
 #define DMISS	SPRN_DMISS	/* Data TLB Miss Register */
 #define DSISR	SPRN_DSISR	/* Data Storage Interrupt Status Register */
 #define EAR	SPRN_EAR	/* External Address Register */
@@ -380,9 +380,9 @@
 #define IMMR	SPRN_IMMR	/* PPC 860/821 Internal Memory Map Register */
 #define L2CR	SPRN_L2CR	/* Classic PPC L2 cache control register */
 #define L3CR	SPRN_L3CR	/* PPC 745x L3 cache control register */
-#define LR	SPRN_LR
+//#define LR	SPRN_LR
 #define PVR	SPRN_PVR	/* Processor Version */
-#define RPA	SPRN_RPA	/* Required Physical Address Register */
+//#define RPA	SPRN_RPA	/* Required Physical Address Register */
 #define SDR1	SPRN_SDR1	/* MMU hash base register */
 #define SPR0	SPRN_SPRG0	/* Supervisor Private Registers */
 #define SPR1	SPRN_SPRG1
@@ -489,6 +489,7 @@
 #define SVR_8555E	0x80790000
 #define SVR_8560	0x80700000
 
+#if 0
 /* Segment Registers */
 #define SR0	0
 #define SR1	1
@@ -506,6 +507,7 @@
 #define SR13	13
 #define SR14	14
 #define SR15	15
+#endif
 
 /* Macros for setting and retrieving special purpose registers */
 #ifndef __ASSEMBLY__
diff --git a/include/asm-ppc/signal.h b/include/asm-ppc/signal.h
index 108bec27db9b..580fcc148259 100644
--- a/include/asm-ppc/signal.h
+++ b/include/asm-ppc/signal.h
@@ -118,7 +118,11 @@ typedef struct {
 #define SIG_SETMASK        2	/* for setting the signal mask */
 
 /* Type of a signal handler.  */
-typedef void (*__sighandler_t)(int);
+typedef void __signalfn_t(int);
+typedef __signalfn_t __user *__sighandler_t;
+
+typedef void __restorefn_t(void);
+typedef __restorefn_t __user *__sigrestore_t;
 
 #define SIG_DFL	((__sighandler_t)0)	/* default signal handling */
 #define SIG_IGN	((__sighandler_t)1)	/* ignore signal */
@@ -128,13 +132,13 @@ struct old_sigaction {
 	__sighandler_t sa_handler;
 	old_sigset_t sa_mask;
 	unsigned long sa_flags;
-	void (*sa_restorer)(void);
+	__sigrestore_t sa_restorer;
 };
 
 struct sigaction {
 	__sighandler_t sa_handler;
 	unsigned long sa_flags;
-	void (*sa_restorer)(void);
+	__sigrestore_t sa_restorer;
 	sigset_t sa_mask;		/* mask last for extensibility */
 };
 
@@ -143,7 +147,7 @@ struct k_sigaction {
 };
 
 typedef struct sigaltstack {
-	void *ss_sp;
+	void __user *ss_sp;
 	int ss_flags;
 	size_t ss_size;
 } stack_t;
diff --git a/include/asm-ppc/uaccess.h b/include/asm-ppc/uaccess.h
index 0a1a1a86a1de..b9d763e0d886 100644
--- a/include/asm-ppc/uaccess.h
+++ b/include/asm-ppc/uaccess.h
@@ -34,7 +34,8 @@
 	((addr) <= current->thread.fs.seg				    \
 	 && ((size) == 0 || (size) - 1 <= current->thread.fs.seg - (addr)))
 
-#define access_ok(type, addr, size) __access_ok((unsigned long)(addr),(size))
+#define access_ok(type, addr, size) \
+	(__chk_user_ptr(addr),__access_ok((unsigned long)(addr),(size)))
 
 extern inline int verify_area(int type, const void __user * addr, unsigned long size)
 {
@@ -105,6 +106,7 @@ extern long __put_user_bad(void);
 #define __put_user_nocheck(x,ptr,size)			\
 ({							\
 	long __pu_err;					\
+	__chk_user_ptr(ptr);				\
 	__put_user_size((x),(ptr),(size),__pu_err);	\
 	__pu_err;					\
 })
@@ -112,7 +114,7 @@ extern long __put_user_bad(void);
 #define __put_user_check(x,ptr,size)				\
 ({								\
 	long __pu_err = -EFAULT;				\
-	__typeof__(*(ptr)) *__pu_addr = (ptr);			\
+	__typeof__(*(ptr)) __user *__pu_addr = (ptr);		\
 	if (access_ok(VERIFY_WRITE,__pu_addr,size))		\
 		__put_user_size((x),__pu_addr,(size),__pu_err);	\
 	__pu_err;						\
@@ -179,6 +181,7 @@ do {							\
 #define __get_user_nocheck(x, ptr, size)			\
 ({								\
 	long __gu_err, __gu_val;				\
+	__chk_user_ptr(ptr);					\
 	__get_user_size(__gu_val, (ptr), (size), __gu_err);	\
 	(x) = (__typeof__(*(ptr)))__gu_val;			\
 	__gu_err;						\
@@ -188,6 +191,7 @@ do {							\
 ({								\
 	long __gu_err;						\
 	long long __gu_val;					\
+	__chk_user_ptr(ptr);					\
 	__get_user_size64(__gu_val, (ptr), (size), __gu_err);	\
 	(x) = (__typeof__(*(ptr)))__gu_val;			\
 	__gu_err;						\
@@ -196,7 +200,7 @@ do {							\
 #define __get_user_check(x, ptr, size)					\
 ({									\
 	long __gu_err = -EFAULT, __gu_val = 0;				\
-	const __typeof__(*(ptr)) *__gu_addr = (ptr);			\
+	const __typeof__(*(ptr)) __user *__gu_addr = (ptr);		\
 	if (access_ok(VERIFY_READ, __gu_addr, (size)))			\
 		__get_user_size(__gu_val, __gu_addr, (size), __gu_err);	\
 	(x) = (__typeof__(*(ptr)))__gu_val;				\
@@ -207,7 +211,7 @@ do {							\
 ({									  \
 	long __gu_err = -EFAULT;					  \
 	long long __gu_val = 0;						  \
-	const __typeof__(*(ptr)) *__gu_addr = (ptr);			  \
+	const __typeof__(*(ptr)) __user *__gu_addr = (ptr);		  \
 	if (access_ok(VERIFY_READ, __gu_addr, (size)))			  \
 		__get_user_size64(__gu_val, __gu_addr, (size), __gu_err); \
 	(x) = (__typeof__(*(ptr)))__gu_val;				  \
diff --git a/include/asm-ppc/ucontext.h b/include/asm-ppc/ucontext.h
index 53da26040a0e..664bc984d51f 100644
--- a/include/asm-ppc/ucontext.h
+++ b/include/asm-ppc/ucontext.h
@@ -13,10 +13,10 @@ struct mcontext {
 
 struct ucontext {
 	unsigned long	 uc_flags;
-	struct ucontext *uc_link;
+	struct ucontext __user *uc_link;
 	stack_t		 uc_stack;
 	int		 uc_pad[7];
-	struct mcontext	*uc_regs;	/* points to uc_mcontext field */
+	struct mcontext	__user *uc_regs;/* points to uc_mcontext field */
 	sigset_t	 uc_sigmask;
 	/* glibc has 1024-bit signal masks, ours are 64-bit */
 	int		 uc_maskext[30];