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authorMiquel Raynal <miquel.raynal@bootlin.com>2025-07-31 18:52:16 +0200
committerMiquel Raynal <miquel.raynal@bootlin.com>2025-07-31 18:52:16 +0200
commit9cf9db888f387844e063efc6296e9fa5c042995e (patch)
tree6c0cea7ecc9f06c93194ec80551e98e07871e3d7 /include/linux/atmdev.h
parent3dd8aa0ef78e4941f4b915d317616c03d08e31b2 (diff)
parentfb2fae70e7e985c4acb1ad96110d8b98bb64a87c (diff)
Merge tag 'nand/for-6.17' into mtd/next
* Raw NAND changes: Various controller drivers received minor fixes like DMA mapping checks, better timing derivations or bitflip statistics. It has also been discovered that some Hynix NAND flashes were not supporting read-retries, which is not properly supported. * SPI NAND changes: In order to support high-speed modes, certain chips need extra configuration like adding more dummy cycles. This is now possible, especially on Winbond chips. Aside from that, Gigadevice gets support for a new chip (GD5F1GM9). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Diffstat (limited to 'include/linux/atmdev.h')
-rw-r--r--include/linux/atmdev.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/include/linux/atmdev.h b/include/linux/atmdev.h
index 9b02961d65ee..45f2f278b50a 100644
--- a/include/linux/atmdev.h
+++ b/include/linux/atmdev.h
@@ -249,6 +249,12 @@ static inline void atm_account_tx(struct atm_vcc *vcc, struct sk_buff *skb)
ATM_SKB(skb)->atm_options = vcc->atm_options;
}
+static inline void atm_return_tx(struct atm_vcc *vcc, struct sk_buff *skb)
+{
+ WARN_ON_ONCE(refcount_sub_and_test(ATM_SKB(skb)->acct_truesize,
+ &sk_atm(vcc)->sk_wmem_alloc));
+}
+
static inline void atm_force_charge(struct atm_vcc *vcc,int truesize)
{
atomic_add(truesize, &sk_atm(vcc)->sk_rmem_alloc);