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authorDave Jiang <dave.jiang@intel.com>2026-02-04 10:53:33 -0700
committerDave Jiang <dave.jiang@intel.com>2026-02-04 10:53:33 -0700
commit63fbf275fa9f18f7020fb8acf54fa107e51d0f23 (patch)
tree4e553e1e9e69a72131019667a8682efce3ce210d /include/linux
parent0da3050bdded5f121aaca6b5247ea50681d7129e (diff)
parent208f432406b7ed446c061d68cc73efd85b575d3f (diff)
Merge branch 'for-7.0/cxl-prm-translation' into cxl-for-next
Add support for normalized CXL address translation through ACPI PRM method to support AMD Zen5 platforms. Including a conventions doc that explains how the translation is implemented and for future implementations that need such setup to comply with the current implementation method. cxl: Disable HPA/SPA translation handlers for Normalized Addressing cxl/region: Factor out code into cxl_region_setup_poison() cxl/atl: Lock decoders that need address translation cxl: Enable AMD Zen5 address translation using ACPI PRMT cxl/acpi: Prepare use of EFI runtime services cxl: Introduce callback for HPA address ranges translation cxl/region: Use region data to get the root decoder cxl/region: Add @hpa_range argument to function cxl_calc_interleave_pos() cxl/region: Separate region parameter setup and region construction cxl: Simplify cxl_root_ops allocation and handling cxl/region: Store HPA range in struct cxl_region cxl/region: Store root decoder in struct cxl_region cxl/region: Rename misleading variable name @hpa to @hpa_range Documentation/driver-api/cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement cxl, doc: Moving conventions in separate files cxl, doc: Remove isonum.txt inclusion
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