diff options
| author | Bryan O'Donoghue <pure.logic@nexus-software.ie> | 2014-10-07 01:19:49 +0100 |
|---|---|---|
| committer | Luis Henriques <luis.henriques@canonical.com> | 2014-11-17 14:11:51 +0000 |
| commit | a51906f6c811cadf20b35d60f427b4b3e09dbcc0 (patch) | |
| tree | 6cc45e02dbcdc1ffc0e0f886bfbe77e564e05803 /include/linux | |
| parent | 48c43d231bf6b53961271c50f1347d7bb81f9466 (diff) | |
x86: Add cpu_detect_cache_sizes to init_intel() add Quark legacy_cache()
commit aece118e487a744eafcdd0c77fe32b55ee2092a1 upstream.
Intel processors which don't report cache information via cpuid(2)
or cpuid(4) need quirk code in the legacy_cache_size callback to
report this data. For Intel that callback is is intel_size_cache().
This patch enables calling of cpu_detect_cache_sizes() inside of
init_intel() and hence the calling of the legacy_cache callback in
intel_size_cache(). Adding this call will ensure that PIII Tualatin
currently in intel_size_cache() and Quark SoC X1000 being added to
intel_size_cache() in this patch will report their respective cache
sizes.
This model of calling cpu_detect_cache_sizes() is consistent with
AMD/Via/Cirix/Transmeta and Centaur.
Also added is a string to idenitfy the Quark as Quark SoC X1000
giving better and more descriptive output via /proc/cpuinfo
Adding cpu_detect_cache_sizes to init_intel() will enable calling
of intel_size_cache() on Intel processors which currently no code
can reach. Therefore this patch will also re-enable reporting
of PIII Tualatin cache size information as well as add
Quark SoC X1000 support.
Comment text and cache flow logic suggested by Thomas Gleixner
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: davej@redhat.com
Cc: hmh@hmh.eng.br
Link: http://lkml.kernel.org/r/1412641189-12415-3-git-send-email-pure.logic@nexus-software.ie
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Luis Henriques <luis.henriques@canonical.com>
Diffstat (limited to 'include/linux')
0 files changed, 0 insertions, 0 deletions
