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authorPalmer Dabbelt <palmer@rivosinc.com>2024-03-12 07:10:08 -0700
committerPalmer Dabbelt <palmer@rivosinc.com>2024-03-12 07:10:08 -0700
commitb8e00bdf253e0f0f3a7c351463bdbca513b21900 (patch)
tree61b04e2bea6a195ca259999d6ae5dd47f3c16841 /include/linux
parent886516fae2b73a1578600e95631436785f3e44d6 (diff)
parentf4cc33e78ba8624a79ba8dea98ce5c85aa9ca33c (diff)
Merge tag 'irq-for-riscv-02-23-24' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tip/tip into for-next
INTC changes to consume for RISCV * tag 'irq-for-riscv-02-23-24' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/riscv-intc: Introduce Andes hart-level interrupt controller irqchip/riscv-intc: Allow large non-standard interrupt number
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/soc/andes/irq.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h
new file mode 100644
index 000000000000..edc3182d6e66
--- /dev/null
+++ b/include/linux/soc/andes/irq.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+#ifndef __ANDES_IRQ_H
+#define __ANDES_IRQ_H
+
+/* Andes PMU irq number */
+#define ANDES_RV_IRQ_PMOVI 18
+#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI
+#define ANDES_SLI_CAUSE_BASE 256
+
+/* Andes PMU related registers */
+#define ANDES_CSR_SLIE 0x9c4
+#define ANDES_CSR_SLIP 0x9c5
+#define ANDES_CSR_SCOUNTEROF 0x9d4
+
+#endif /* __ANDES_IRQ_H */