Merge tag 'spi-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi updates from Mark Brown:
 "The highlight here is that David Lechner has added support for
  multi-lane SPI devices. Unlike the existing dual/quad SPI support this
  is for devices (typically ADCs/DACs) which support multiple
  independent data streams over multiple data lanes, instead of sending
  one data stream N times as fast they simultaneously transfer N
  different data streams.

  This is very similar to the case where multiple devices are grouped
  together but in this case it's a single device in a way that's visible
  to software.

  Otherwise there's been quite a bit of work on existing drivers, both
  cleanup and feature improvement, and a reasonable collection of new
  drivers.

   - Support for multi-lane SPI devices

   - Preparatory work for some memory mapped flash improvements that
     will happen in the MTD subsystem

   - Several conversions to fwnode APIs

   - A bunch of cleanup and hardening work on the ST drivers

   - Support for DMA mode on Renesas RZV2H and i.MX target mode

   - Support for ATCSPI200, AXIADO AX300, NXP XPI and Renesas RZ/N1"

* tag 'spi-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (108 commits)
  spi: tools: Add include folder to .gitignore
  spi: cadence-qspi: Add support for the Renesas RZ/N1 controller
  spi: cadence-qspi: Kill cqspi_jh7110_clk_init
  spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list
  spi: geni-qcom: Add target abort support
  spi: geni-qcom: Drop unused msg parameter from timeout handlers
  spi: geni-qcom: Fix abort sequence execution for serial engine errors
  spi: geni-qcom: Improve target mode allocation by using proper allocation functions
  spi: xilinx: use device property accessors.
  dt-bindings: spi: Add binding for Faraday FTSSP010
  spi: axi-spi-engine: support SPI_MULTI_LANE_MODE_STRIPE
  spi: dt-bindings: adi,axi-spi-engine: add multi-lane support
  spi: Documentation: add page on multi-lane support
  spi: add multi_lane_mode field to struct spi_transfer
  spi: support controllers with multiple data lanes
  spi: dt-bindings: add spi-{tx,rx}-lane-map properties
  spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays
  spi: dw: Remove not-going-to-be-supported code for Baikal SoC
  spi: cadence-qspi: Use a default value for cdns,fifo-width
  spi: cadence-qspi: Make sure write protection is disabled
  ...

2 files changed, 41 insertions, 3 deletions

diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index 82390712794c..e4db0924898c 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -20,10 +20,10 @@
 		.opcode = __opcode,				\
 	}
 
-#define SPI_MEM_DTR_OP_CMD(__opcode, __buswidth)		\
+#define SPI_MEM_DTR_OP_RPT_CMD(__opcode, __buswidth)		\
 	{							\
-		.nbytes = 1,					\
-		.opcode = __opcode,				\
+		.nbytes = 2,					\
+		.opcode = __opcode | __opcode << 8,		\
 		.buswidth = __buswidth,				\
 		.dtr = true,					\
 	}
@@ -43,6 +43,14 @@
 		.dtr = true,					\
 	}
 
+#define SPI_MEM_DTR_OP_RPT_ADDR(__val, __buswidth)		\
+	{							\
+		.nbytes = 2,					\
+		.val = __val | __val << 8,			\
+		.buswidth = __buswidth,				\
+		.dtr = true,					\
+	}
+
 #define SPI_MEM_OP_NO_ADDR	{ }
 
 #define SPI_MEM_OP_DUMMY(__nbytes, __buswidth)			\
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index cb2c2df31089..39681f7e063b 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -23,6 +23,9 @@
 /* Max no. of CS supported per spi device */
 #define SPI_DEVICE_CS_CNT_MAX 4
 
+/* Max no. of data lanes supported per spi device */
+#define SPI_DEVICE_DATA_LANE_CNT_MAX 8
+
 struct dma_chan;
 struct software_node;
 struct ptp_system_timestamp;
@@ -174,6 +177,10 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg,
  * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array
  * @cs_gpiod: Array of GPIO descriptors of the corresponding chipselect lines
  *	(optional, NULL when not using a GPIO line)
+ * @tx_lane_map: Map of peripheral lanes (index) to controller lanes (value).
+ * @num_tx_lanes: Number of transmit lanes wired up.
+ * @rx_lane_map: Map of peripheral lanes (index) to controller lanes (value).
+ * @num_rx_lanes: Number of receive lanes wired up.
  *
  * A @spi_device is used to interchange data between an SPI target device
  * (usually a discrete chip) and CPU memory.
@@ -242,6 +249,12 @@ struct spi_device {
 
 	struct gpio_desc	*cs_gpiod[SPI_DEVICE_CS_CNT_MAX];	/* Chip select gpio desc */
 
+	/* Multi-lane SPI controller support. */
+	u8			tx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX];
+	u8			num_tx_lanes;
+	u8			rx_lane_map[SPI_DEVICE_DATA_LANE_CNT_MAX];
+	u8			num_rx_lanes;
+
 	/*
 	 * Likely need more hooks for more protocol options affecting how
 	 * the controller talks to each chip, like:
@@ -401,6 +414,7 @@ extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 ch
  *	SPI targets, and are numbered from zero to num_chipselects.
  *	each target has a chipselect signal, but it's common that not
  *	every chipselect is connected to a target.
+ * @num_data_lanes: Number of data lanes supported by this controller. Default is 1.
  * @dma_alignment: SPI controller constraint on DMA buffers alignment.
  * @mode_bits: flags understood by this controller driver
  * @buswidth_override_bits: flags to override for this controller driver
@@ -576,6 +590,14 @@ struct spi_controller {
 	 */
 	u16			num_chipselect;
 
+	/*
+	 * Some specialized SPI controllers can have more than one physical
+	 * data lane interface per controller (each having it's own serializer).
+	 * This specifies the number of data lanes in that case. Other
+	 * controllers do not need to set this (defaults to 1).
+	 */
+	u16			num_data_lanes;
+
 	/* Some SPI controllers pose alignment requirements on DMAable
 	 * buffers; let protocol drivers know about these requirements.
 	 */
@@ -959,6 +981,8 @@ struct spi_res {
  *      (SPI_NBITS_SINGLE) is used.
  * @rx_nbits: number of bits used for reading. If 0 the default
  *      (SPI_NBITS_SINGLE) is used.
+ * @multi_lane_mode: How to serialize data on multiple lanes. One of the
+ *      SPI_MULTI_LANE_MODE_* values.
  * @len: size of rx and tx buffers (in bytes)
  * @speed_hz: Select a speed other than the device default for this
  *      transfer. If 0 the default (from @spi_device) is used.
@@ -1095,6 +1119,12 @@ struct spi_transfer {
 	unsigned	cs_change:1;
 	unsigned	tx_nbits:4;
 	unsigned	rx_nbits:4;
+
+#define SPI_MULTI_LANE_MODE_SINGLE	0 /* only use single lane */
+#define SPI_MULTI_LANE_MODE_STRIPE	1 /* one data word per lane */
+#define SPI_MULTI_LANE_MODE_MIRROR	2 /* same word sent on all lanes */
+	unsigned	multi_lane_mode: 2;
+
 	unsigned	timestamped:1;
 	bool		dtr_mode;
 #define	SPI_NBITS_SINGLE	0x01 /* 1-bit transfer */