[IRDA]: Move IRDA device headers to more appropriate place.

10 files changed, 0 insertions, 2279 deletions

diff --git a/include/net/irda/ali-ircc.h b/include/net/irda/ali-ircc.h
deleted file mode 100644
index dc5edd12b8f8..000000000000
--- a/include/net/irda/ali-ircc.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*********************************************************************
- *                
- * Filename:      ali-ircc.h
- * Version:       0.5
- * Description:   Driver for the ALI M1535D and M1543C FIR Controller
- * Status:        Experimental.
- * Author:        Benjamin Kong <benjamin_kong@ali.com.tw>
- * Created at:    2000/10/16 03:46PM
- * Modified at:   2001/1/3 02:56PM
- * Modified by:   Benjamin Kong <benjamin_kong@ali.com.tw>
- * 
- *     Copyright (c) 2000 Benjamin Kong <benjamin_kong@ali.com.tw>
- *     All Rights Reserved
- *      
- *     This program is free software; you can redistribute it and/or 
- *     modify it under the terms of the GNU General Public License as 
- *     published by the Free Software Foundation; either version 2 of 
- *     the License, or (at your option) any later version.
- *  
- ********************************************************************/
-
-#ifndef ALI_IRCC_H
-#define ALI_IRCC_H
-
-#include <linux/time.h>
-
-#include <linux/spinlock.h>
-#include <linux/pm.h>
-#include <asm/io.h>
-
-/* SIR Register */
-/* Usr definition of linux/serial_reg.h */
-
-/* FIR Register */
-#define BANK0		0x20
-#define BANK1		0x21
-#define BANK2		0x22
-#define BANK3		0x23
-
-#define FIR_MCR		0x07	/* Master Control Register */
-
-/* Bank 0 */
-#define FIR_DR		0x00	/* Alias 0, FIR Data Register (R/W) */ 
-#define FIR_IER		0x01	/* Alias 1, FIR Interrupt Enable Register (R/W) */
-#define FIR_IIR		0x02	/* Alias 2, FIR Interrupt Identification Register (Read only) */
-#define FIR_LCR_A	0x03	/* Alias 3, FIR Line Control Register A (R/W) */
-#define FIR_LCR_B	0x04	/* Alias 4, FIR Line Control Register B (R/W) */
-#define FIR_LSR		0x05	/* Alias 5, FIR Line Status Register (R/W) */
-#define FIR_BSR		0x06	/* Alias 6, FIR Bus Status Register (Read only) */
-
-
-	/* Alias 1 */
-	#define	IER_FIFO	0x10	/* FIR FIFO Interrupt Enable */	
-	#define	IER_TIMER	0x20 	/* Timer Interrupt Enable */ 
-	#define	IER_EOM		0x40	/* End of Message Interrupt Enable */
-	#define IER_ACT		0x80	/* Active Frame Interrupt Enable */
-	
-	/* Alias 2 */
-	#define IIR_FIFO	0x10	/* FIR FIFO Interrupt */
-	#define IIR_TIMER	0x20	/* Timer Interrupt */
-	#define IIR_EOM		0x40	/* End of Message Interrupt */
-	#define IIR_ACT		0x80	/* Active Frame Interrupt */	
-	
-	/* Alias 3 */
-	#define LCR_A_FIFO_RESET 0x80	/* FIFO Reset */
-
-	/* Alias 4 */
-	#define	LCR_B_BW	0x10	/* Brick Wall */
-	#define LCR_B_SIP	0x20	/* SIP Enable */
-	#define	LCR_B_TX_MODE 	0x40	/* Transmit Mode */
-	#define LCR_B_RX_MODE	0x80	/* Receive Mode */
-	
-	/* Alias 5 */	
-	#define LSR_FIR_LSA	0x00	/* FIR Line Status Address */
-	#define LSR_FRAME_ABORT	0x08	/* Frame Abort */
-	#define LSR_CRC_ERROR	0x10	/* CRC Error */
-	#define LSR_SIZE_ERROR	0x20	/* Size Error */
-	#define LSR_FRAME_ERROR	0x40	/* Frame Error */
-	#define LSR_FIFO_UR	0x80	/* FIFO Underrun */
-	#define LSR_FIFO_OR	0x80	/* FIFO Overrun */
-		
-	/* Alias 6 */
-	#define BSR_FIFO_NOT_EMPTY	0x80	/* FIFO Not Empty */
-	
-/* Bank 1 */
-#define	FIR_CR		0x00 	/* Alias 0, FIR Configuration Register (R/W) */
-#define FIR_FIFO_TR	0x01   	/* Alias 1, FIR FIFO Threshold Register (R/W) */
-#define FIR_DMA_TR	0x02	/* Alias 2, FIR DMA Threshold Register (R/W) */
-#define FIR_TIMER_IIR	0x03	/* Alias 3, FIR Timer interrupt interval register (W/O) */
-#define FIR_FIFO_FR	0x03	/* Alias 3, FIR FIFO Flag register (R/O) */
-#define FIR_FIFO_RAR	0x04 	/* Alias 4, FIR FIFO Read Address register (R/O) */
-#define FIR_FIFO_WAR	0x05	/* Alias 5, FIR FIFO Write Address register (R/O) */
-#define FIR_TR		0x06	/* Alias 6, Test REgister (W/O) */
-
-	/* Alias 0 */
-	#define CR_DMA_EN	0x01	/* DMA Enable */
-	#define CR_DMA_BURST	0x02	/* DMA Burst Mode */
-	#define CR_TIMER_EN 	0x08	/* Timer Enable */
-	
-	/* Alias 3 */
-	#define TIMER_IIR_500	0x00	/* 500 us */
-	#define TIMER_IIR_1ms	0x01	/* 1   ms */
-	#define TIMER_IIR_2ms	0x02	/* 2   ms */
-	#define TIMER_IIR_4ms	0x03	/* 4   ms */
-	
-/* Bank 2 */
-#define FIR_IRDA_CR	0x00	/* Alias 0, IrDA Control Register (R/W) */
-#define FIR_BOF_CR	0x01	/* Alias 1, BOF Count Register (R/W) */
-#define FIR_BW_CR	0x02	/* Alias 2, Brick Wall Count Register (R/W) */
-#define FIR_TX_DSR_HI	0x03	/* Alias 3, TX Data Size Register (high) (R/W) */
-#define FIR_TX_DSR_LO	0x04	/* Alias 4, TX Data Size Register (low) (R/W) */
-#define FIR_RX_DSR_HI	0x05	/* Alias 5, RX Data Size Register (high) (R/W) */
-#define FIR_RX_DSR_LO	0x06	/* Alias 6, RX Data Size Register (low) (R/W) */
-	
-	/* Alias 0 */
-	#define IRDA_CR_HDLC1152 0x80	/* 1.152Mbps HDLC Select */
-	#define IRDA_CR_CRC	0X40	/* CRC Select. */
-	#define IRDA_CR_HDLC	0x20	/* HDLC select. */
-	#define IRDA_CR_HP_MODE 0x10	/* HP mode (read only) */
-	#define IRDA_CR_SD_ST	0x08	/* SD/MODE State.  */
-	#define IRDA_CR_FIR_SIN 0x04	/* FIR SIN Select. */
-	#define IRDA_CR_ITTX_0	0x02	/* SOUT State. IRTX force to 0 */
-	#define IRDA_CR_ITTX_1	0x03	/* SOUT State. IRTX force to 1 */
-	
-/* Bank 3 */
-#define FIR_ID_VR	0x00	/* Alias 0, FIR ID Version Register (R/O) */
-#define FIR_MODULE_CR	0x01	/* Alias 1, FIR Module Control Register (R/W) */
-#define FIR_IO_BASE_HI	0x02	/* Alias 2, FIR Higher I/O Base Address Register (R/O) */
-#define FIR_IO_BASE_LO	0x03	/* Alias 3, FIR Lower I/O Base Address Register (R/O) */
-#define FIR_IRQ_CR	0x04	/* Alias 4, FIR IRQ Channel Register (R/O) */
-#define FIR_DMA_CR	0x05	/* Alias 5, FIR DMA Channel Register (R/O) */
-
-struct ali_chip {
-	char *name;
-	int cfg[2];
-	unsigned char entr1;
-	unsigned char entr2;
-	unsigned char cid_index;
-	unsigned char cid_value;
-	int (*probe)(struct ali_chip *chip, chipio_t *info);
-	int (*init)(struct ali_chip *chip, chipio_t *info); 
-};
-typedef struct ali_chip ali_chip_t;
-
-
-/* DMA modes needed */
-#define DMA_TX_MODE     0x08    /* Mem to I/O, ++, demand. */
-#define DMA_RX_MODE     0x04    /* I/O to mem, ++, demand. */
-
-#define MAX_TX_WINDOW 	7
-#define MAX_RX_WINDOW 	7
-
-#define TX_FIFO_Threshold	8
-#define RX_FIFO_Threshold	1
-#define TX_DMA_Threshold	1
-#define RX_DMA_Threshold	1
-
-/* For storing entries in the status FIFO */
-
-struct st_fifo_entry {
-	int status;
-	int len;
-};
-
-struct st_fifo {
-	struct st_fifo_entry entries[MAX_RX_WINDOW];
-	int pending_bytes;
-	int head;
-	int tail;
-	int len;
-};
-
-struct frame_cb {
-	void *start; /* Start of frame in DMA mem */
-	int len;     /* Lenght of frame in DMA mem */
-};
-
-struct tx_fifo {
-	struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */
-	int             ptr;                  /* Currently being sent */
-	int             len;                  /* Lenght of queue */
-	int             free;                 /* Next free slot */
-	void           *tail;                 /* Next free start in DMA mem */
-};
-
-/* Private data for each instance */
-struct ali_ircc_cb {
-
-	struct st_fifo st_fifo;    /* Info about received frames */
-	struct tx_fifo tx_fifo;    /* Info about frames to be transmitted */
-
-	struct net_device *netdev;     /* Yes! we are some kind of netdevice */
-	struct net_device_stats stats;
-	
-	struct irlap_cb *irlap;    /* The link layer we are binded to */
-	struct qos_info qos;       /* QoS capabilities for this device */
-	
-	chipio_t io;               /* IrDA controller information */
-	iobuff_t tx_buff;          /* Transmit buffer */
-	iobuff_t rx_buff;          /* Receive buffer */
-
-	__u8 ier;                  /* Interrupt enable register */
-	
-	__u8 InterruptID;	   /* Interrupt ID */	
-	__u8 BusStatus;		   /* Bus Status */	
-	__u8 LineStatus;	   /* Line Status */	
-	
-	unsigned char rcvFramesOverflow;
-		
-	struct timeval stamp;
-	struct timeval now;
-
-	spinlock_t lock;           /* For serializing operations */
-	
-	__u32 new_speed;
-	int index;                 /* Instance index */
-	
-	unsigned char fifo_opti_buf;
-
-        struct pm_dev *dev;
-};
-
-static inline void switch_bank(int iobase, int bank)
-{
-		outb(bank, iobase+FIR_MCR);
-}
-
-#endif /* ALI_IRCC_H */
diff --git a/include/net/irda/au1000_ircc.h b/include/net/irda/au1000_ircc.h
deleted file mode 100644
index 7a31d4659ed6..000000000000
--- a/include/net/irda/au1000_ircc.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *	Au1000 IrDA driver.
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: MontaVista Software, Inc.
- *         	ppopov@mvista.com or source@mvista.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef AU1000_IRCC_H
-#define AU1000_IRCC_H
-
-#include <linux/time.h>
-
-#include <linux/spinlock.h>
-#include <linux/pm.h>
-#include <asm/io.h>
-
-#define NUM_IR_IFF          1
-#define NUM_IR_DESC        64
-#define RING_SIZE_4       0x0
-#define RING_SIZE_16      0x3
-#define RING_SIZE_64      0xF
-#define MAX_NUM_IR_DESC    64
-#define MAX_BUF_SIZE     2048
-
-#define BPS_115200          0
-#define BPS_57600           1
-#define BPS_38400           2
-#define BPS_19200           5
-#define BPS_9600           11
-#define BPS_2400           47
-
-/* Ring descriptor flags */
-#define AU_OWN           (1<<7) /* tx,rx */
-
-#define IR_DIS_CRC       (1<<6) /* tx */
-#define IR_BAD_CRC       (1<<5) /* tx */
-#define IR_NEED_PULSE    (1<<4) /* tx */
-#define IR_FORCE_UNDER   (1<<3) /* tx */
-#define IR_DISABLE_TX    (1<<2) /* tx */
-#define IR_HW_UNDER      (1<<0) /* tx */
-#define IR_TX_ERROR      (IR_DIS_CRC|IR_BAD_CRC|IR_HW_UNDER)
-
-#define IR_PHY_ERROR     (1<<6) /* rx */
-#define IR_CRC_ERROR     (1<<5) /* rx */
-#define IR_MAX_LEN       (1<<4) /* rx */
-#define IR_FIFO_OVER     (1<<3) /* rx */
-#define IR_SIR_ERROR     (1<<2) /* rx */
-#define IR_RX_ERROR      (IR_PHY_ERROR|IR_CRC_ERROR| \
-		IR_MAX_LEN|IR_FIFO_OVER|IR_SIR_ERROR)
-
-typedef struct db_dest {
-	struct db_dest *pnext;
-	volatile u32 *vaddr;
-	dma_addr_t dma_addr;
-} db_dest_t;
-
-
-typedef struct ring_desc {
-	u8 count_0;               /* 7:0  */
-	u8 count_1;               /* 12:8 */
-	u8 reserved;
-	u8 flags;
-	u8 addr_0;                /* 7:0   */
-	u8 addr_1;                /* 15:8  */
-	u8 addr_2;                /* 23:16 */
-	u8 addr_3;                /* 31:24 */
-} ring_dest_t;
-
-
-/* Private data for each instance */
-struct au1k_private {
-
-	db_dest_t *pDBfree;
-	db_dest_t db[2*NUM_IR_DESC];
-	volatile ring_dest_t *rx_ring[NUM_IR_DESC];
-	volatile ring_dest_t *tx_ring[NUM_IR_DESC];
-	db_dest_t *rx_db_inuse[NUM_IR_DESC];
-	db_dest_t *tx_db_inuse[NUM_IR_DESC];
-	u32 rx_head;
-	u32 tx_head;
-	u32 tx_tail;
-	u32 tx_full;
-
-	iobuff_t rx_buff;
-
-	struct net_device *netdev;
-	struct net_device_stats stats;
-	
-	struct timeval stamp;
-	struct timeval now;
-	struct qos_info		qos;
-	struct irlap_cb		*irlap;
-	
-	u8 open;
-	u32 speed;
-	u32 newspeed;
-	
-	u32 intr_work_done; /* number of Rx and Tx pkts processed in the isr */
-	struct timer_list timer;
-
-	spinlock_t lock;           /* For serializing operations */
-        struct pm_dev *dev;
-};
-#endif /* AU1000_IRCC_H */
diff --git a/include/net/irda/irda-usb.h b/include/net/irda/irda-usb.h
deleted file mode 100644
index bd8f66542322..000000000000
--- a/include/net/irda/irda-usb.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*****************************************************************************
- *
- * Filename:      irda-usb.h
- * Version:       0.9b
- * Description:   IrDA-USB Driver
- * Status:        Experimental 
- * Author:        Dag Brattli <dag@brattli.net>
- *
- *	Copyright (C) 2001, Roman Weissgaerber <weissg@vienna.at>
- *      Copyright (C) 2000, Dag Brattli <dag@brattli.net>
- *      Copyright (C) 2001, Jean Tourrilhes <jt@hpl.hp.com>
- *          
- *	This program is free software; you can redistribute it and/or modify
- *	it under the terms of the GNU General Public License as published by
- *	the Free Software Foundation; either version 2 of the License, or
- *	(at your option) any later version.
- *
- *	This program is distributed in the hope that it will be useful,
- *	but WITHOUT ANY WARRANTY; without even the implied warranty of
- *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *	GNU General Public License for more details.
- *
- *	You should have received a copy of the GNU General Public License
- *	along with this program; if not, write to the Free Software
- *	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *****************************************************************************/
-
-#include <linux/time.h>
-
-#include <net/irda/irda.h>
-#include <net/irda/irda_device.h>      /* struct irlap_cb */
-
-#define RX_COPY_THRESHOLD 200
-#define IRDA_USB_MAX_MTU 2051
-#define IRDA_USB_SPEED_MTU 64		/* Weird, but work like this */
-
-/* Maximum number of active URB on the Rx path
- * This is the amount of buffers the we keep between the USB harware and the
- * IrDA stack.
- *
- * Note : the network layer does also queue the packets between us and the
- * IrDA stack, and is actually pretty fast and efficient in doing that.
- * Therefore, we don't need to have a large number of URBs, and we can
- * perfectly live happy with only one. We certainly don't need to keep the
- * full IrTTP window around here...
- * I repeat for those who have trouble to understand : 1 URB is plenty
- * good enough to handle back-to-back (brickwalled) frames. I tried it,
- * it works (it's the hardware that has trouble doing it).
- *
- * Having 2 URBs would allow the USB stack to process one URB while we take
- * care of the other and then swap the URBs...
- * On the other hand, increasing the number of URB will have penalities
- * in term of latency and will interact with the link management in IrLAP...
- * Jean II */
-#define IU_MAX_ACTIVE_RX_URBS	1	/* Don't touch !!! */
-
-/* When a Rx URB is passed back to us, we can't reuse it immediately,
- * because it may still be referenced by the USB layer. Therefore we
- * need to keep one extra URB in the Rx path.
- * Jean II */
-#define IU_MAX_RX_URBS	(IU_MAX_ACTIVE_RX_URBS + 1)
-
-/* Various ugly stuff to try to workaround generic problems */
-/* Send speed command in case of timeout, just for trying to get things sane */
-#define IU_BUG_KICK_TIMEOUT
-/* Show the USB class descriptor */
-#undef IU_DUMP_CLASS_DESC 
-/* Assume a minimum round trip latency for USB transfer (in us)...
- * USB transfer are done in the next USB slot if there is no traffic
- * (1/19 msec) and is done at 12 Mb/s :
- * Waiting for slot + tx = (53us + 16us) * 2 = 137us minimum.
- * Rx notification will only be done at the end of the USB frame period :
- * OHCI : frame period = 1ms
- * UHCI : frame period = 1ms, but notification can take 2 or 3 ms :-(
- * EHCI : frame period = 125us */
-#define IU_USB_MIN_RTT		500	/* This should be safe in most cases */
-
-/* Inbound header */
-#define MEDIA_BUSY    0x80
-
-#define SPEED_2400    0x01
-#define SPEED_9600    0x02
-#define SPEED_19200   0x03
-#define SPEED_38400   0x04
-#define SPEED_57600   0x05
-#define SPEED_115200  0x06
-#define SPEED_576000  0x07
-#define SPEED_1152000 0x08
-#define SPEED_4000000 0x09
-
-/* Basic capabilities */
-#define IUC_DEFAULT	0x00	/* Basic device compliant with 1.0 spec */
-/* Main bugs */
-#define IUC_SPEED_BUG	0x01	/* Device doesn't set speed after the frame */
-#define IUC_NO_WINDOW	0x02	/* Device doesn't behave with big Rx window */
-#define IUC_NO_TURN	0x04	/* Device doesn't do turnaround by itself */
-/* Not currently used */
-#define IUC_SIR_ONLY	0x08	/* Device doesn't behave at FIR speeds */
-#define IUC_SMALL_PKT	0x10	/* Device doesn't behave with big Rx packets */
-#define IUC_MAX_WINDOW	0x20	/* Device underestimate the Rx window */
-#define IUC_MAX_XBOFS	0x40	/* Device need more xbofs than advertised */
-
-/* USB class definitions */
-#define USB_IRDA_HEADER   0x01
-#define USB_CLASS_IRDA    0x02 /* USB_CLASS_APP_SPEC subclass */ 
-#define USB_DT_IRDA       0x21
-
-struct irda_class_desc {
-	__u8  bLength;
-	__u8  bDescriptorType;
-	__u16 bcdSpecRevision;
-	__u8  bmDataSize;
-	__u8  bmWindowSize;
-	__u8  bmMinTurnaroundTime;
-	__u16 wBaudRate;
-	__u8  bmAdditionalBOFs;
-	__u8  bIrdaRateSniff;
-	__u8  bMaxUnicastList;
-} __attribute__ ((packed));
-
-/* class specific interface request to get the IrDA-USB class descriptor
- * (6.2.5, USB-IrDA class spec 1.0) */
-
-#define IU_REQ_GET_CLASS_DESC	0x06
-
-struct irda_usb_cb {
-	struct irda_class_desc *irda_desc;
-	struct usb_device *usbdev;	/* init: probe_irda */
-	struct usb_interface *usbintf;	/* init: probe_irda */
-	int netopen;			/* Device is active for network */
-	int present;			/* Device is present on the bus */
-	__u32 capability;		/* Capability of the hardware */
-	__u8  bulk_in_ep;		/* Rx Endpoint assignments */
-	__u8  bulk_out_ep;		/* Tx Endpoint assignments */
-	__u16 bulk_out_mtu;		/* Max Tx packet size in bytes */
-	__u8  bulk_int_ep;		/* Interrupt Endpoint assignments */
-
-	wait_queue_head_t wait_q;	/* for timeouts */
-
-	struct urb *rx_urb[IU_MAX_RX_URBS];	/* URBs used to receive data frames */
-	struct urb *idle_rx_urb;	/* Pointer to idle URB in Rx path */
-	struct urb *tx_urb;		/* URB used to send data frames */
-	struct urb *speed_urb;		/* URB used to send speed commands */
-	
-	struct net_device *netdev;	/* Yes! we are some kind of netdev. */
-	struct net_device_stats stats;
-	struct irlap_cb   *irlap;	/* The link layer we are binded to */
-	struct qos_info qos;
-	hashbin_t *tx_list;		/* Queued transmit skb's */
-	char *speed_buff;		/* Buffer for speed changes */
-
-	struct timeval stamp;
-	struct timeval now;
-
-	spinlock_t lock;		/* For serializing operations */
-
-	__u16 xbofs;			/* Current xbofs setting */
-	__s16 new_xbofs;		/* xbofs we need to set */
-	__u32 speed;			/* Current speed */
-	__s32 new_speed;		/* speed we need to set */
-};
-
diff --git a/include/net/irda/irport.h b/include/net/irda/irport.h
deleted file mode 100644
index 991f956c096c..000000000000
--- a/include/net/irda/irport.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*********************************************************************
- *                
- * Filename:      irport.h
- * Version:       0.1
- * Description:   Serial driver for IrDA
- * Status:        Experimental.
- * Author:        Dag Brattli <dagb@cs.uit.no>
- * Created at:    Sun Aug  3 13:49:59 1997
- * Modified at:   Fri Jan 14 10:21:10 2000
- * Modified by:   Dag Brattli <dagb@cs.uit.no>
- * 
- *     Copyright (c) 1997, 1998-2000 Dag Brattli <dagb@cs.uit.no>
- *     All Rights Reserved.
- *     
- *     This program is free software; you can redistribute it and/or 
- *     modify it under the terms of the GNU General Public License as 
- *     published by the Free Software Foundation; either version 2 of 
- *     the License, or (at your option) any later version.
- *
- *     Neither Dag Brattli nor University of Tromsų admit liability nor
- *     provide warranty for any of this software. This material is 
- *     provided "AS-IS" and at no charge.
- *
- ********************************************************************/
-
-#ifndef IRPORT_H
-#define IRPORT_H
-
-#include <linux/netdevice.h>
-#include <linux/skbuff.h>
-#include <linux/types.h>
-#include <linux/spinlock.h>
-
-#include <net/irda/irda_device.h>
-
-#define SPEED_DEFAULT 9600
-#define SPEED_MAX     115200
-
-/*
- * These are the supported serial types.
- */
-#define PORT_UNKNOWN    0
-#define PORT_8250       1
-#define PORT_16450      2
-#define PORT_16550      3
-#define PORT_16550A     4
-#define PORT_CIRRUS     5
-#define PORT_16650      6
-#define PORT_MAX        6  
-
-#define FRAME_MAX_SIZE 2048
-
-struct irport_cb {
-	struct net_device *netdev; /* Yes! we are some kind of netdevice */
-	struct net_device_stats stats;
-
-	struct irlap_cb *irlap;    /* The link layer we are attached to */
-
-	chipio_t io;               /* IrDA controller information */
-	iobuff_t tx_buff;          /* Transmit buffer */
-	iobuff_t rx_buff;          /* Receive buffer */
-
-	struct qos_info qos;       /* QoS capabilities for this device */
-	dongle_t *dongle;          /* Dongle driver */
-
- 	__u32 flags;               /* Interface flags */
-	__u32 new_speed;
-	int mode;
-	int index;                 /* Instance index */
-	int transmitting;	   /* Are we transmitting ? */
-
-	spinlock_t lock;           /* For serializing operations */
-
-	/* For piggyback drivers */
-	void *priv;                
-	void (*change_speed)(void *priv, __u32 speed);
-	int (*interrupt)(int irq, void *dev_id, struct pt_regs *regs);
-};
-
-struct irport_cb *irport_open(int i, unsigned int iobase, unsigned int irq);
-int  irport_close(struct irport_cb *self);
-void irport_start(struct irport_cb *self);
-void irport_stop(struct irport_cb *self);
-void irport_change_speed(void *priv, __u32 speed);
-irqreturn_t irport_interrupt(int irq, void *dev_id, struct pt_regs *regs);
-int  irport_hard_xmit(struct sk_buff *skb, struct net_device *dev);
-int  irport_net_open(struct net_device *dev);
-int  irport_net_close(struct net_device *dev);
-
-#endif /* IRPORT_H */
diff --git a/include/net/irda/nsc-ircc.h b/include/net/irda/nsc-ircc.h
deleted file mode 100644
index 0f541aa71935..000000000000
--- a/include/net/irda/nsc-ircc.h
+++ /dev/null
@@ -1,277 +0,0 @@
-/*********************************************************************
- *                
- * Filename:      nsc-ircc.h
- * Version:       
- * Description:   
- * Status:        Experimental.
- * Author:        Dag Brattli <dagb@cs.uit.no>
- * Created at:    Fri Nov 13 14:37:40 1998
- * Modified at:   Sun Jan 23 17:47:00 2000
- * Modified by:   Dag Brattli <dagb@cs.uit.no>
- * 
- *     Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
- *     Copyright (c) 1998 Lichen Wang, <lwang@actisys.com>
- *     Copyright (c) 1998 Actisys Corp., www.actisys.com
- *     All Rights Reserved
- *      
- *     This program is free software; you can redistribute it and/or 
- *     modify it under the terms of the GNU General Public License as 
- *     published by the Free Software Foundation; either version 2 of 
- *     the License, or (at your option) any later version.
- *  
- *     Neither Dag Brattli nor University of Tromsų admit liability nor
- *     provide warranty for any of this software. This material is 
- *     provided "AS-IS" and at no charge.
- *     
- ********************************************************************/
-
-#ifndef NSC_IRCC_H
-#define NSC_IRCC_H
-
-#include <linux/time.h>
-
-#include <linux/spinlock.h>
-#include <linux/pm.h>
-#include <asm/io.h>
-
-/* DMA modes needed */
-#define DMA_TX_MODE     0x08    /* Mem to I/O, ++, demand. */
-#define DMA_RX_MODE     0x04    /* I/O to mem, ++, demand. */
-
-/* Config registers for the '108 */
-#define CFG_108_BAIC 0x00
-#define CFG_108_CSRT 0x01
-#define CFG_108_MCTL 0x02
-
-/* Config registers for the '338 */
-#define CFG_338_FER  0x00
-#define CFG_338_FAR  0x01
-#define CFG_338_PTR  0x02
-#define CFG_338_PNP0 0x1b
-#define CFG_338_PNP1 0x1c
-#define CFG_338_PNP3 0x4f
-
-/* Config registers for the '39x (in the logical device bank) */
-#define CFG_39X_LDN	0x07	/* Logical device number (Super I/O bank) */
-#define CFG_39X_SIOCF1	0x21	/* SuperI/O Config */
-#define CFG_39X_ACT	0x30	/* Device activation */
-#define CFG_39X_BASEH	0x60	/* Device base address (high bits) */
-#define CFG_39X_BASEL	0x61	/* Device base address (low bits) */
-#define CFG_39X_IRQNUM	0x70	/* Interrupt number & wake up enable */
-#define CFG_39X_IRQSEL	0x71	/* Interrupt select (edge/level + polarity) */
-#define CFG_39X_DMA0	0x74	/* DMA 0 configuration */
-#define CFG_39X_DMA1	0x75	/* DMA 1 configuration */
-#define CFG_39X_SPC	0xF0	/* Serial port configuration register */
-
-/* Flags for configuration register CRF0 */
-#define APEDCRC		0x02
-#define ENBNKSEL	0x01
-
-/* Set 0 */
-#define TXD             0x00 /* Transmit data port */
-#define RXD             0x00 /* Receive data port */
-
-/* Register 1 */
-#define IER		0x01 /* Interrupt Enable Register*/
-#define IER_RXHDL_IE    0x01 /* Receiver high data level interrupt */
-#define IER_TXLDL_IE    0x02 /* Transeiver low data level interrupt */
-#define IER_LS_IE	0x04//* Link Status Interrupt */
-#define IER_ETXURI      0x04 /* Tx underrun */
-#define IER_DMA_IE	0x10 /* DMA finished interrupt */
-#define IER_TXEMP_IE    0x20
-#define IER_SFIF_IE     0x40 /* Frame status FIFO intr */
-#define IER_TMR_IE      0x80 /* Timer event */
-
-#define FCR		0x02 /* (write only) */
-#define FCR_FIFO_EN     0x01 /* Enable FIFO's */
-#define FCR_RXSR        0x02 /* Rx FIFO soft reset */
-#define FCR_TXSR        0x04 /* Tx FIFO soft reset */
-#define FCR_RXTH	0x40 /* Rx FIFO threshold (set to 16) */
-#define FCR_TXTH	0x20 /* Tx FIFO threshold (set to 17) */
-
-#define EIR		0x02 /* (read only) */
-#define EIR_RXHDL_EV	0x01
-#define EIR_TXLDL_EV    0x02
-#define EIR_LS_EV	0x04
-#define EIR_DMA_EV	0x10
-#define EIR_TXEMP_EV	0x20
-#define EIR_SFIF_EV     0x40
-#define EIR_TMR_EV      0x80
-
-#define LCR             0x03 /* Link control register */
-#define LCR_WLS_8       0x03 /* 8 bits */
-
-#define BSR 	        0x03 /* Bank select register */
-#define BSR_BKSE        0x80
-#define BANK0 	        LCR_WLS_8 /* Must make sure that we set 8N1 */
-#define BANK1	        0x80
-#define BANK2	        0xe0
-#define BANK3	        0xe4
-#define BANK4	        0xe8
-#define BANK5	        0xec
-#define BANK6	        0xf0
-#define BANK7     	0xf4
-
-#define MCR		0x04 /* Mode Control Register */
-#define MCR_MODE_MASK	~(0xd0)
-#define MCR_UART        0x00
-#define MCR_RESERVED  	0x20	
-#define MCR_SHARP_IR    0x40
-#define MCR_SIR         0x60
-#define MCR_MIR  	0x80
-#define MCR_FIR		0xa0
-#define MCR_CEIR        0xb0
-#define MCR_IR_PLS      0x10
-#define MCR_DMA_EN	0x04
-#define MCR_EN_IRQ	0x08
-#define MCR_TX_DFR	0x08
-
-#define LSR             0x05 /* Link status register */
-#define LSR_RXDA        0x01 /* Receiver data available */
-#define LSR_TXRDY       0x20 /* Transmitter ready */
-#define LSR_TXEMP       0x40 /* Transmitter empty */
-
-#define ASCR            0x07 /* Auxillary Status and Control Register */
-#define ASCR_RXF_TOUT   0x01 /* Rx FIFO timeout */
-#define ASCR_FEND_INF   0x02 /* Frame end bytes in rx FIFO */
-#define ASCR_S_EOT      0x04 /* Set end of transmission */
-#define ASCT_RXBSY      0x20 /* Rx busy */
-#define ASCR_TXUR       0x40 /* Transeiver underrun */
-#define ASCR_CTE        0x80 /* Clear timer event */
-
-/* Bank 2 */
-#define BGDL            0x00 /* Baud Generator Divisor Port (Low Byte) */
-#define BGDH            0x01 /* Baud Generator Divisor Port (High Byte) */
-
-#define ECR1		0x02 /* Extended Control Register 1 */
-#define ECR1_EXT_SL	0x01 /* Extended Mode Select */
-#define ECR1_DMANF	0x02 /* DMA Fairness */
-#define ECR1_DMATH      0x04 /* DMA Threshold */
-#define ECR1_DMASWP	0x08 /* DMA Swap */
-
-#define EXCR2		0x04
-#define EXCR2_TFSIZ	0x01 /* Rx FIFO size = 32 */
-#define EXCR2_RFSIZ	0x04 /* Tx FIFO size = 32 */
-
-#define TXFLV           0x06 /* Tx FIFO level */
-#define RXFLV           0x07 /* Rx FIFO level */
-
-/* Bank 3 */
-#define MID		0x00
-
-/* Bank 4 */
-#define TMRL            0x00 /* Timer low byte */
-#define TMRH            0x01 /* Timer high byte */
-#define IRCR1           0x02 /* Infrared control register 1 */
-#define IRCR1_TMR_EN    0x01 /* Timer enable */
-
-#define TFRLL		0x04
-#define TFRLH		0x05
-#define RFRLL		0x06
-#define RFRLH		0x07
-
-/* Bank 5 */
-#define IRCR2           0x04 /* Infrared control register 2 */
-#define IRCR2_MDRS      0x04 /* MIR data rate select */
-#define IRCR2_FEND_MD   0x20 /* */
-
-#define FRM_ST          0x05 /* Frame status FIFO */
-#define FRM_ST_VLD      0x80 /* Frame status FIFO data valid */
-#define FRM_ST_ERR_MSK  0x5f
-#define FRM_ST_LOST_FR  0x40 /* Frame lost */
-#define FRM_ST_MAX_LEN  0x10 /* Max frame len exceeded */
-#define FRM_ST_PHY_ERR  0x08 /* Physical layer error */
-#define FRM_ST_BAD_CRC  0x04 
-#define FRM_ST_OVR1     0x02 /* Rx FIFO overrun */
-#define FRM_ST_OVR2     0x01 /* Frame status FIFO overrun */
-
-#define RFLFL           0x06
-#define RFLFH           0x07
-
-/* Bank 6 */
-#define IR_CFG2		0x00
-#define IR_CFG2_DIS_CRC	0x02
-
-/* Bank 7 */
-#define IRM_CR		0x07 /* Infrared module control register */
-#define IRM_CR_IRX_MSL	0x40
-#define IRM_CR_AF_MNT   0x80 /* Automatic format */
-
-/* NSC chip information */
-struct nsc_chip {
-	char *name;          /* Name of chipset */
-	int cfg[3];          /* Config registers */
-	u_int8_t cid_index;  /* Chip identification index reg */
-	u_int8_t cid_value;  /* Chip identification expected value */
-	u_int8_t cid_mask;   /* Chip identification revision mask */
-
-	/* Functions for probing and initializing the specific chip */
-	int (*probe)(struct nsc_chip *chip, chipio_t *info);
-	int (*init)(struct nsc_chip *chip, chipio_t *info);
-};
-typedef struct nsc_chip nsc_chip_t;
-
-/* For storing entries in the status FIFO */
-struct st_fifo_entry {
-	int status;
-	int len;
-};
-
-#define MAX_TX_WINDOW 7
-#define MAX_RX_WINDOW 7
-
-struct st_fifo {
-	struct st_fifo_entry entries[MAX_RX_WINDOW];
-	int pending_bytes;
-	int head;
-	int tail;
-	int len;
-};
-
-struct frame_cb {
-	void *start; /* Start of frame in DMA mem */
-	int len;     /* Lenght of frame in DMA mem */
-};
-
-struct tx_fifo {
-	struct frame_cb queue[MAX_TX_WINDOW]; /* Info about frames in queue */
-	int             ptr;                  /* Currently being sent */
-	int             len;                  /* Lenght of queue */
-	int             free;                 /* Next free slot */
-	void           *tail;                 /* Next free start in DMA mem */
-};
-
-/* Private data for each instance */
-struct nsc_ircc_cb {
-	struct st_fifo st_fifo;    /* Info about received frames */
-	struct tx_fifo tx_fifo;    /* Info about frames to be transmitted */
-
-	struct net_device *netdev;     /* Yes! we are some kind of netdevice */
-	struct net_device_stats stats;
-	
-	struct irlap_cb *irlap;    /* The link layer we are binded to */
-	struct qos_info qos;       /* QoS capabilities for this device */
-	
-	chipio_t io;               /* IrDA controller information */
-	iobuff_t tx_buff;          /* Transmit buffer */
-	iobuff_t rx_buff;          /* Receive buffer */
-
-	__u8 ier;                  /* Interrupt enable register */
-
-	struct timeval stamp;
-	struct timeval now;
-
-	spinlock_t lock;           /* For serializing operations */
-	
-	__u32 new_speed;
-	int index;                 /* Instance index */
-
-        struct pm_dev *dev;
-};
-
-static inline void switch_bank(int iobase, int bank)
-{
-		outb(bank, iobase+BSR);
-}
-
-#endif /* NSC_IRCC_H */
diff --git a/include/net/irda/smc-ircc.h b/include/net/irda/smc-ircc.h
deleted file mode 100644
index 6ef49e7e5aba..000000000000
--- a/include/net/irda/smc-ircc.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*********************************************************************
- *                
- * Filename:      smc-ircc.h
- * Version:       0.3
- * Description:   Definitions for the SMC IrCC chipset
- * Status:        Experimental.
- * Author:        Thomas Davis (tadavis@jps.net)
- *
- *     Copyright (c) 1999-2000, Dag Brattli <dagb@cs.uit.no>
- *     Copyright (c) 1998-1999, Thomas Davis (tadavis@jps.net>
- *     All Rights Reserved
- *      
- *     This program is free software; you can redistribute it and/or 
- *     modify it under the terms of the GNU General Public License as 
- *     published by the Free Software Foundation; either version 2 of 
- *     the License, or (at your option) any later version.
- * 
- *     This program is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *     GNU General Public License for more details.
- * 
- *     You should have received a copy of the GNU General Public License 
- *     along with this program; if not, write to the Free Software 
- *     Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
- *     MA 02111-1307 USA
- *
- ********************************************************************/
-
-#ifndef SMC_IRCC_H
-#define SMC_IRCC_H
-
-#include <linux/spinlock.h>
-#include <linux/pm.h>
-
-#include <net/irda/irport.h>
-
-/* DMA modes needed */
-#define DMA_TX_MODE                0x08    /* Mem to I/O, ++, demand. */
-#define DMA_RX_MODE                0x04    /* I/O to mem, ++, demand. */
-
-/* Master Control Register */
-#define IRCC_MASTER                0x07
-#define   IRCC_MASTER_POWERDOWN	   0x80
-#define   IRCC_MASTER_RESET        0x40
-#define   IRCC_MASTER_INT_EN       0x20
-#define   IRCC_MASTER_ERROR_RESET  0x10
-
-/* Register block 0 */
-
-/* Interrupt Identification */
-#define IRCC_IIR                   0x01
-#define   IRCC_IIR_ACTIVE_FRAME    0x80
-#define   IRCC_IIR_EOM             0x40
-#define   IRCC_IIR_RAW_MODE        0x20
-#define   IRCC_IIR_FIFO		   0x10
-
-/* Interrupt Enable */
-#define IRCC_IER                   0x02
-#define   IRCC_IER_ACTIVE_FRAME	   0x80
-#define   IRCC_IER_EOM 		   0x40
-#define   IRCC_IER_RAW_MODE        0x20
-#define   IRCC_IER_FIFO		   0x10
-
-/* Line Status Register */
-#define IRCC_LSR                   0x03
-#define   IRCC_LSR_UNDERRUN        0x80
-#define   IRCC_LSR_OVERRUN         0x40
-#define   IRCC_LSR_FRAME_ERROR     0x20
-#define   IRCC_LSR_SIZE_ERROR      0x10
-#define   IRCC_LSR_CRC_ERROR       0x80
-#define   IRCC_LSR_FRAME_ABORT 	   0x40
-
-/* Line Control Register A */
-#define IRCC_LCR_A                 0x04
-#define   IRCC_LCR_A_FIFO_RESET    0x80
-#define   IRCC_LCR_A_FAST          0x40
-#define   IRCC_LCR_A_GP_DATA       0x20
-#define   IRCC_LCR_A_RAW_TX        0x10
-#define   IRCC_LCR_A_RAW_RX        0x08
-#define   IRCC_LCR_A_ABORT         0x04
-#define   IRCC_LCR_A_DATA_DONE     0x02
-
-/* Line Control Register B */
-#define IRCC_LCR_B                 0x05
-#define   IRCC_LCR_B_SCE_DISABLED  0x00
-#define   IRCC_LCR_B_SCE_TRANSMIT  0x40
-#define   IRCC_LCR_B_SCE_RECEIVE   0x80
-#define   IRCC_LCR_B_SCE_UNDEFINED 0xc0
-#define   IRCC_LCR_B_SIP_ENABLE	   0x20
-#define   IRCC_LCR_B_BRICK_WALL    0x10
-
-/* Bus Status Register */
-#define IRCC_BSR                   0x06
-#define   IRCC_BSR_NOT_EMPTY	   0x80
-#define   IRCC_BSR_FIFO_FULL	   0x40
-#define   IRCC_BSR_TIMEOUT	   0x20
-
-/* Register block 1 */
-
-#define IRCC_FIFO_THRESHOLD	   0x02
-
-#define IRCC_SCE_CFGA	           0x00
-#define   IRCC_CFGA_AUX_IR	   0x80
-#define   IRCC_CFGA_HALF_DUPLEX	   0x04
-#define   IRCC_CFGA_TX_POLARITY	   0x02
-#define   IRCC_CFGA_RX_POLARITY	   0x01
-
-#define   IRCC_CFGA_COM		   0x00
-#define   IRCC_CFGA_IRDA_SIR_A	   0x08
-#define   IRCC_CFGA_ASK_SIR	   0x10
-#define   IRCC_CFGA_IRDA_SIR_B	   0x18
-#define   IRCC_CFGA_IRDA_HDLC 	   0x20
-#define   IRCC_CFGA_IRDA_4PPM 	   0x28
-#define   IRCC_CFGA_CONSUMER	   0x30
-#define   IRCC_CFGA_RAW_IR	   0x38
-#define   IRCC_CFGA_OTHER          0x40
-
-#define IRCC_IR_HDLC               0x04
-#define IRCC_IR_4PPM               0x01
-#define IRCC_IR_CONSUMER           0x02
-
-#define IRCC_SCE_CFGB	           0x01
-#define IRCC_CFGB_LOOPBACK         0x20
-#define IRCC_CFGB_LPBCK_TX_CRC	   0x10
-#define IRCC_CFGB_NOWAIT	   0x08
-#define IRCC_CFGB_STRING_MOVE	   0x04
-#define IRCC_CFGB_DMA_BURST 	   0x02
-#define IRCC_CFGB_DMA_ENABLE	   0x01
-
-#define IRCC_CFGB_MUX_COM          0x00
-#define IRCC_CFGB_MUX_IR           0x40
-#define IRCC_CFGB_MUX_AUX          0x80
-#define IRCC_CFGB_MUX_INACTIVE	   0xc0
-
-/* Register block 3 - Identification Registers! */
-#define IRCC_ID_HIGH	           0x00   /* 0x10 */
-#define IRCC_ID_LOW	           0x01   /* 0xB8 */
-#define IRCC_CHIP_ID 	           0x02   /* 0xF1 */
-#define IRCC_VERSION	           0x03   /* 0x01 */
-#define IRCC_INTERFACE	           0x04   /* low 4 = DMA, high 4 = IRQ */
-
-/* Register block 4 - IrDA */
-#define IRCC_CONTROL               0x00
-#define IRCC_BOF_COUNT_LO          0x01 /* Low byte */
-#define IRCC_BOF_COUNT_HI          0x00 /* High nibble (bit 0-3) */
-#define IRCC_BRICKWALL_CNT_LO      0x02 /* Low byte */
-#define IRCC_BRICKWALL_CNT_HI      0x03 /* High nibble (bit 4-7) */
-#define IRCC_TX_SIZE_LO            0x04 /* Low byte */
-#define IRCC_TX_SIZE_HI            0x03 /* High nibble (bit 0-3) */
-#define IRCC_RX_SIZE_HI            0x05 /* High nibble (bit 0-3) */
-#define IRCC_RX_SIZE_LO            0x06 /* Low byte */
-
-#define IRCC_1152                  0x80
-#define IRCC_CRC                   0x40
-
-/* Private data for each instance */
-struct ircc_cb {
-	struct net_device *netdev;     /* Yes! we are some kind of netdevice */
-	struct irlap_cb    *irlap; /* The link layer we are binded to */
-	
-	chipio_t *io;               /* IrDA controller information */
-	iobuff_t tx_buff;          /* Transmit buffer */
-	iobuff_t rx_buff;          /* Receive buffer */
-
-	struct irport_cb *irport;
-
-	/* Locking : half of our operations are done with irport, so we
-	 * use the irport spinlock to make sure *everything* is properly
-	 * synchronised - Jean II */
-	
-	__u32 new_speed;
-
-	int tx_buff_offsets[10];   /* Offsets between frames in tx_buff */
-	int tx_len;                /* Number of frames in tx_buff */
-
-	struct pm_dev *pmdev;
-};
-
-#endif /* SMC_IRCC_H */
diff --git a/include/net/irda/toshoboe.h b/include/net/irda/toshoboe.h
deleted file mode 100644
index 7d7a227d1d35..000000000000
--- a/include/net/irda/toshoboe.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*********************************************************************
- *                
- * Filename:      toshoboe.h
- * Version:       0.1
- * Description:   Driver for the Toshiba OBOE (or type-O)
- *                FIR Chipset. 
- * Status:        Experimental.
- * Author:        James McKenzie <james@fishsoup.dhs.org>
- * Created at:    Sat May 8  12:35:27 1999
- * 
- *     Copyright (c) 1999-2000 James McKenzie, All Rights Reserved.
- *      
- *     This program is free software; you can redistribute it and/or 
- *     modify it under the terms of the GNU General Public License as 
- *     published by the Free Software Foundation; either version 2 of 
- *     the License, or (at your option) any later version.
- *  
- *     Neither James McKenzie nor Cambridge University admit liability nor
- *     provide warranty for any of this software. This material is 
- *     provided "AS-IS" and at no charge.
- *
- *     Applicable Models : Libretto 100CT. and many more
- *
- ********************************************************************/
-
-#ifndef TOSHOBOE_H
-#define TOSHOBOE_H
-
-/* Registers */
-/*Receive and transmit task registers (read only) */
-#define OBOE_RCVT	(0x00+(self->base))
-#define OBOE_XMTT	(0x01+(self->base))
-#define OBOE_XMTT_OFFSET	0x40
-
-/*Page pointers to the TaskFile structure */
-#define OBOE_TFP2	(0x02+(self->base))
-#define OBOE_TFP0	(0x04+(self->base))
-#define OBOE_TFP1	(0x05+(self->base))
-
-/*Dunno */
-#define OBOE_REG_3	(0x03+(self->base))
-
-/*Number of tasks to use in Xmit and Recv queues */
-#define OBOE_NTR	(0x07+(self->base))
-#define OBOE_NTR_XMIT4	0x00
-#define OBOE_NTR_XMIT8	0x10
-#define OBOE_NTR_XMIT16	0x30
-#define OBOE_NTR_XMIT32	0x70
-#define OBOE_NTR_XMIT64	0xf0
-#define OBOE_NTR_RECV4	0x00
-#define OBOE_NTR_RECV8	0x01
-#define OBOE_NTR_RECV6	0x03
-#define OBOE_NTR_RECV32	0x07
-#define OBOE_NTR_RECV64	0x0f
-
-/* Dunno */
-#define OBOE_REG_9	(0x09+(self->base))
-
-/* Interrupt Status Register */
-#define OBOE_ISR	(0x0c+(self->base))
-#define OBOE_ISR_TXDONE	0x80
-#define OBOE_ISR_RXDONE	0x40
-#define OBOE_ISR_20	0x20
-#define OBOE_ISR_10	0x10
-#define OBOE_ISR_8	0x08         /*This is collision or parity or something */
-#define OBOE_ISR_4	0x08
-#define OBOE_ISR_2	0x08
-#define OBOE_ISR_1	0x08
-
-/*Dunno */
-#define OBOE_REG_D	(0x0d+(self->base))
-
-/*Register Lock Register */
-#define OBOE_LOCK	((self->base)+0x0e)
-
-
-
-/*Speed control registers */
-#define OBOE_PMDL	(0x10+(self->base))
-#define OBOE_PMDL_SIR	0x18
-#define OBOE_PMDL_MIR	0xa0
-#define OBOE_PMDL_FIR	0x40
-
-#define OBOE_SMDL	(0x18+(self->base))
-#define OBOE_SMDL_SIR	0x20
-#define OBOE_SMDL_MIR	0x01
-#define OBOE_SMDL_FIR	0x0f
-
-#define OBOE_UDIV	(0x19+(self->base))
-
-/*Dunno */
-#define OBOE_REG_11	(0x11+(self->base))
-
-/*Chip Reset Register */
-#define OBOE_RST	(0x15+(self->base))
-#define OBOE_RST_WRAP	0x8
-
-/*Dunno */
-#define OBOE_REG_1A	(0x1a+(self->base))
-#define OBOE_REG_1B	(0x1b+(self->base))
-
-/* The PCI ID of the OBOE chip */
-#ifndef PCI_DEVICE_ID_FIR701
-#define PCI_DEVICE_ID_FIR701 	0x0701
-#endif
-
-typedef unsigned int dword;
-typedef unsigned short int word;
-typedef unsigned char byte;
-typedef dword Paddr;
-
-struct OboeTask
-  {
-    __u16 len;
-    __u8 unused;
-    __u8 control;
-    __u32 buffer;
-  };
-
-#define OBOE_NTASKS 64
-
-struct OboeTaskFile
-  {
-    struct OboeTask recv[OBOE_NTASKS];
-    struct OboeTask xmit[OBOE_NTASKS];
-  };
-
-#define OBOE_TASK_BUF_LEN (sizeof(struct OboeTaskFile) << 1)
-
-/*These set the number of slots in use */
-#define TX_SLOTS	4
-#define RX_SLOTS	4
-
-/* You need also to change this, toshiba uses 4,8 and 4,4 */
-/* It makes no difference if you are only going to use ONETASK mode */
-/* remember each buffer use XX_BUF_SZ more _PHYSICAL_ memory */
-#define OBOE_NTR_VAL 	(OBOE_NTR_XMIT4 | OBOE_NTR_RECV4)
-
-struct toshoboe_cb
-  {
-    struct net_device *netdev;      /* Yes! we are some kind of netdevice */
-    struct net_device_stats stats;
-
-    struct irlap_cb    *irlap;  /* The link layer we are binded to */
-    struct qos_info     qos;    /* QoS capabilities for this device */
-
-    chipio_t io;                /* IrDA controller information */
-
-    __u32 new_speed;
-
-    struct pci_dev *pdev;       /*PCI device */
-    int base;                   /*IO base */
-    int txpending;              /*how many tx's are pending */
-    int txs, rxs;               /*Which slots are we at  */
-    void *taskfilebuf;          /*The unaligned taskfile buffer */
-    struct OboeTaskFile *taskfile;  /*The taskfile   */
-    void *xmit_bufs[TX_SLOTS];  /*The buffers   */
-    void *recv_bufs[RX_SLOTS];
-    int open;
-    int stopped;		/*Stopped by some or other APM stuff*/
-  };
-
-
-#endif
-
-
diff --git a/include/net/irda/vlsi_ir.h b/include/net/irda/vlsi_ir.h
deleted file mode 100644
index 55e4a7f34fb1..000000000000
--- a/include/net/irda/vlsi_ir.h
+++ /dev/null
@@ -1,799 +0,0 @@
-
-/*********************************************************************
- *
- *	vlsi_ir.h:	VLSI82C147 PCI IrDA controller driver for Linux
- *
- *	Version:	0.5
- *
- *	Copyright (c) 2001-2003 Martin Diehl
- *
- *	This program is free software; you can redistribute it and/or 
- *	modify it under the terms of the GNU General Public License as 
- *	published by the Free Software Foundation; either version 2 of 
- *	the License, or (at your option) any later version.
- *
- *	This program is distributed in the hope that it will be useful,
- *	but WITHOUT ANY WARRANTY; without even the implied warranty of
- *	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *	GNU General Public License for more details.
- *
- *	You should have received a copy of the GNU General Public License 
- *	along with this program; if not, write to the Free Software 
- *	Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
- *	MA 02111-1307 USA
- *
- ********************************************************************/
-
-#ifndef IRDA_VLSI_FIR_H
-#define IRDA_VLSI_FIR_H
-
-/* ================================================================
- * compatibility stuff
- */
-
-/* definitions not present in pci_ids.h */
-
-#ifndef PCI_CLASS_WIRELESS_IRDA
-#define PCI_CLASS_WIRELESS_IRDA		0x0d00
-#endif
-
-#ifndef PCI_CLASS_SUBCLASS_MASK
-#define PCI_CLASS_SUBCLASS_MASK		0xffff
-#endif
-
-/* in recent 2.5 interrupt handlers have non-void return value */
-#ifndef IRQ_RETVAL
-typedef void irqreturn_t;
-#define IRQ_NONE
-#define IRQ_HANDLED
-#define IRQ_RETVAL(x)
-#endif
-
-/* some stuff need to check kernelversion. Not all 2.5 stuff was present
- * in early 2.5.x - the test is merely to separate 2.4 from 2.5
- */
-#include <linux/version.h>
-
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
-
-/* PDE() introduced in 2.5.4 */
-#ifdef CONFIG_PROC_FS
-#define PDE(inode) ((inode)->u.generic_ip)
-#endif
-
-/* irda crc16 calculation exported in 2.5.42 */
-#define irda_calc_crc16(fcs,buf,len)	(GOOD_FCS)
-
-/* we use this for unified pci device name access */
-#define PCIDEV_NAME(pdev)	((pdev)->name)
-
-#else /* 2.5 or later */
-
-/* recent 2.5/2.6 stores pci device names at varying places ;-) */
-#ifdef CONFIG_PCI_NAMES
-/* human readable name */
-#define PCIDEV_NAME(pdev)	((pdev)->pretty_name)
-#else
-/* whatever we get from the associated struct device - bus:slot:dev.fn id */
-#define PCIDEV_NAME(pdev)	(pci_name(pdev))
-#endif
-
-#endif
-
-/* ================================================================ */
-
-/* non-standard PCI registers */
-
-enum vlsi_pci_regs {
-	VLSI_PCI_CLKCTL		= 0x40,		/* chip clock input control */
-	VLSI_PCI_MSTRPAGE	= 0x41,		/* addr [31:24] for all busmaster cycles */
-	VLSI_PCI_IRMISC		= 0x42		/* mainly legacy UART related */
-};
-
-/* ------------------------------------------ */
-
-/* VLSI_PCI_CLKCTL: Clock Control Register (u8, rw) */
-
-/* Three possible clock sources: either on-chip 48MHz PLL or
- * external clock applied to EXTCLK pin. External clock may
- * be either 48MHz or 40MHz, which is indicated by XCKSEL.
- * CLKSTP controls whether the selected clock source gets
- * connected to the IrDA block.
- *
- * On my HP OB-800 the BIOS sets external 40MHz clock as source
- * when IrDA enabled and I've never detected any PLL lock success.
- * Apparently the 14.3...MHz OSC input required for the PLL to work
- * is not connected and the 40MHz EXTCLK is provided externally.
- * At least this is what makes the driver working for me.
- */
-
-enum vlsi_pci_clkctl {
-
-	/* PLL control */
-
-	CLKCTL_PD_INV		= 0x04,		/* PD#: inverted power down signal,
-						 * i.e. PLL is powered, if PD_INV set */
-	CLKCTL_LOCK		= 0x40,		/* (ro) set, if PLL is locked */
-
-	/* clock source selection */
-
-	CLKCTL_EXTCLK		= 0x20,		/* set to select external clock input, not PLL */
-	CLKCTL_XCKSEL		= 0x10,		/* set to indicate EXTCLK is 40MHz, not 48MHz */
-
-	/* IrDA block control */
-
-	CLKCTL_CLKSTP		= 0x80,		/* set to disconnect from selected clock source */
-	CLKCTL_WAKE		= 0x08		/* set to enable wakeup feature: whenever IR activity
-						 * is detected, PD_INV gets set(?) and CLKSTP cleared */
-};
-
-/* ------------------------------------------ */
-
-/* VLSI_PCI_MSTRPAGE: Master Page Register (u8, rw) and busmastering stuff */
-
-#define DMA_MASK_USED_BY_HW	0xffffffff
-#define DMA_MASK_MSTRPAGE	0x00ffffff
-#define MSTRPAGE_VALUE		(DMA_MASK_MSTRPAGE >> 24)
-
-	/* PCI busmastering is somewhat special for this guy - in short:
-	 *
-	 * We select to operate using fixed MSTRPAGE=0, use ISA DMA
-	 * address restrictions to make the PCI BM api aware of this,
-	 * but ensure the hardware is dealing with real 32bit access.
-	 *
-	 * In detail:
-	 * The chip executes normal 32bit busmaster cycles, i.e.
-	 * drives all 32 address lines. These addresses however are
-	 * composed of [0:23] taken from various busaddr-pointers
-	 * and [24:31] taken from the MSTRPAGE register in the VLSI82C147
-	 * config space. Therefore _all_ busmastering must be
-	 * targeted to/from one single 16MB (busaddr-) superpage!
-	 * The point is to make sure all the allocations for memory
-	 * locations with busmaster access (ring descriptors, buffers)
-	 * are indeed bus-mappable to the same 16MB range (for x86 this
-	 * means they must reside in the same 16MB physical memory address
-	 * range). The only constraint we have which supports "several objects
-	 * mappable to common 16MB range" paradigma, is the old ISA DMA
-	 * restriction to the first 16MB of physical address range.
-	 * Hence the approach here is to enable PCI busmaster support using
-	 * the correct 32bit dma-mask used by the chip. Afterwards the device's
-	 * dma-mask gets restricted to 24bit, which must be honoured somehow by
-	 * all allocations for memory areas to be exposed to the chip ...
-	 *
-	 * Note:
-	 * Don't be surprised to get "Setting latency timer..." messages every
-	 * time when PCI busmastering is enabled for the chip.
-	 * The chip has its PCI latency timer RO fixed at 0 - which is not a
-	 * problem here, because it is never requesting _burst_ transactions.
-	 */
-
-/* ------------------------------------------ */
-
-/* VLSI_PCIIRMISC: IR Miscellaneous Register (u8, rw) */
-
-/* legacy UART emulation - not used by this driver - would require:
- * (see below for some register-value definitions)
- *
- *	- IRMISC_UARTEN must be set to enable UART address decoding
- *	- IRMISC_UARTSEL configured
- *	- IRCFG_MASTER must be cleared
- *	- IRCFG_SIR must be set
- *	- IRENABLE_PHYANDCLOCK must be asserted 0->1 (and hence IRENABLE_SIR_ON)
- */
-
-enum vlsi_pci_irmisc {
-
-	/* IR transceiver control */
-
-	IRMISC_IRRAIL		= 0x40,		/* (ro?) IR rail power indication (and control?)
-						 * 0=3.3V / 1=5V. Probably set during power-on?
-						 * unclear - not touched by driver */
-	IRMISC_IRPD		= 0x08,		/* transceiver power down, if set */
-
-	/* legacy UART control */
-
-	IRMISC_UARTTST		= 0x80,		/* UART test mode - "always write 0" */
-	IRMISC_UARTEN		= 0x04,		/* enable UART address decoding */
-
-	/* bits [1:0] IRMISC_UARTSEL to select legacy UART address */
-
-	IRMISC_UARTSEL_3f8	= 0x00,
-	IRMISC_UARTSEL_2f8	= 0x01,
-	IRMISC_UARTSEL_3e8	= 0x02,
-	IRMISC_UARTSEL_2e8	= 0x03
-};
-
-/* ================================================================ */
-
-/* registers mapped to 32 byte PCI IO space */
-
-/* note: better access all registers at the indicated u8/u16 size
- *	 although some of them contain only 1 byte of information.
- *	 some of them (particaluarly PROMPT and IRCFG) ignore
- *	 access when using the wrong addressing mode!
- */
-
-enum vlsi_pio_regs {
-	VLSI_PIO_IRINTR		= 0x00,		/* interrupt enable/request (u8, rw) */
-	VLSI_PIO_RINGPTR	= 0x02,		/* rx/tx ring pointer (u16, ro) */
-	VLSI_PIO_RINGBASE	= 0x04,		/* [23:10] of ring address (u16, rw) */
-	VLSI_PIO_RINGSIZE	= 0x06,		/* rx/tx ring size (u16, rw) */
-	VLSI_PIO_PROMPT		= 0x08, 	/* triggers ring processing (u16, wo) */
-	/* 0x0a-0x0f: reserved / duplicated UART regs */
-	VLSI_PIO_IRCFG		= 0x10,		/* configuration select (u16, rw) */
-	VLSI_PIO_SIRFLAG	= 0x12,		/* BOF/EOF for filtered SIR (u16, ro) */
-	VLSI_PIO_IRENABLE	= 0x14,		/* enable and status register (u16, rw/ro) */
-	VLSI_PIO_PHYCTL		= 0x16,		/* physical layer current status (u16, ro) */
-	VLSI_PIO_NPHYCTL	= 0x18,		/* next physical layer select (u16, rw) */
-	VLSI_PIO_MAXPKT		= 0x1a,		/* [11:0] max len for packet receive (u16, rw) */
-	VLSI_PIO_RCVBCNT	= 0x1c		/* current receive-FIFO byte count (u16, ro) */
-	/* 0x1e-0x1f: reserved / duplicated UART regs */
-};
-
-/* ------------------------------------------ */
-
-/* VLSI_PIO_IRINTR: Interrupt Register (u8, rw) */
-
-/* enable-bits:
- *		1 = enable / 0 = disable
- * interrupt condition bits:
- * 		set according to corresponding interrupt source
- *		(regardless of the state of the enable bits)
- *		enable bit status indicates whether interrupt gets raised
- *		write-to-clear
- * note: RPKTINT and TPKTINT behave different in legacy UART mode (which we don't use :-)
- */
-
-enum vlsi_pio_irintr {
-	IRINTR_ACTEN	= 0x80,	/* activity interrupt enable */
-	IRINTR_ACTIVITY	= 0x40,	/* activity monitor (traffic detected) */
-	IRINTR_RPKTEN	= 0x20,	/* receive packet interrupt enable*/
-	IRINTR_RPKTINT	= 0x10,	/* rx-packet transfered from fifo to memory finished */
-	IRINTR_TPKTEN	= 0x08,	/* transmit packet interrupt enable */
-	IRINTR_TPKTINT	= 0x04,	/* last bit of tx-packet+crc shifted to ir-pulser */
-	IRINTR_OE_EN	= 0x02,	/* UART rx fifo overrun error interrupt enable */
-	IRINTR_OE_INT	= 0x01	/* UART rx fifo overrun error (read LSR to clear) */
-};
-
-/* we use this mask to check whether the (shared PCI) interrupt is ours */
-
-#define IRINTR_INT_MASK		(IRINTR_ACTIVITY|IRINTR_RPKTINT|IRINTR_TPKTINT)
-
-/* ------------------------------------------ */
-
-/* VLSI_PIO_RINGPTR: Ring Pointer Read-Back Register (u16, ro) */
-
-/* _both_ ring pointers are indices relative to the _entire_ rx,tx-ring!
- * i.e. the referenced descriptor is located
- * at RINGBASE + PTR * sizeof(descr) for rx and tx
- * therefore, the tx-pointer has offset MAX_RING_DESCR
- */
-
-#define MAX_RING_DESCR		64	/* tx, rx rings may contain up to 64 descr each */
-
-#define RINGPTR_RX_MASK		(MAX_RING_DESCR-1)
-#define RINGPTR_TX_MASK		((MAX_RING_DESCR-1)<<8)
-
-#define RINGPTR_GET_RX(p)	((p)&RINGPTR_RX_MASK)
-#define RINGPTR_GET_TX(p)	(((p)&RINGPTR_TX_MASK)>>8)
-
-/* ------------------------------------------ */
-
-/* VLSI_PIO_RINGBASE: Ring Pointer Base Address Register (u16, ro) */
-
-/* Contains [23:10] part of the ring base (bus-) address
- * which must be 1k-alinged. [31:24] is taken from
- * VLSI_PCI_MSTRPAGE above.
- * The controller initiates non-burst PCI BM cycles to
- * fetch and update the descriptors in the ring.
- * Once fetched, the descriptor remains cached onchip
- * until it gets closed and updated due to the ring
- * processing state machine.
- * The entire ring area is split in rx and tx areas with each
- * area consisting of 64 descriptors of 8 bytes each.
- * The rx(tx) ring is located at ringbase+0 (ringbase+64*8).
- */
-
-#define BUS_TO_RINGBASE(p)	(((p)>>10)&0x3fff)
-
-/* ------------------------------------------ */
-
-/* VLSI_PIO_RINGSIZE: Ring Size Register (u16, rw) */
-
-/* bit mask to indicate the ring size to be used for rx and tx.
- * 	possible values		encoded bits
- *		 4		   0000
- *		 8		   0001
- *		16		   0011
- *		32		   0111
- *		64		   1111
- * located at [15:12] for tx and [11:8] for rx ([7:0] unused)
- *
- * note: probably a good idea to have IRCFG_MSTR cleared when writing
- *	 this so the state machines are stopped and the RINGPTR is reset!
- */
-
-#define SIZE_TO_BITS(num)		((((num)-1)>>2)&0x0f)
-#define TX_RX_TO_RINGSIZE(tx,rx)	((SIZE_TO_BITS(tx)<<12)|(SIZE_TO_BITS(rx)<<8))
-#define RINGSIZE_TO_RXSIZE(rs)		((((rs)&0x0f00)>>6)+4)
-#define RINGSIZE_TO_TXSIZE(rs)		((((rs)&0xf000)>>10)+4)
-
-
-/* ------------------------------------------ */
-
-/* VLSI_PIO_PROMPT: Ring Prompting Register (u16, write-to-start) */
-
-/* writing any value kicks the ring processing state machines
- * for both tx, rx rings as follows:
- * 	- active rings (currently owning an active descriptor)
- *	  ignore the prompt and continue
- *	- idle rings fetch the next descr from the ring and start
- *	  their processing
- */
-
-/* ------------------------------------------ */
-
-/* VLSI_PIO_IRCFG: IR Config Register (u16, rw) */
-
-/* notes:
- *	- not more than one SIR/MIR/FIR bit must be set at any time
- *	- SIR, MIR, FIR and CRC16 select the configuration which will
- *	  be applied on next 0->1 transition of IRENABLE_PHYANDCLOCK (see below).
- *	- besides allowing the PCI interface to execute busmaster cycles
- *	  and therefore the ring SM to operate, the MSTR bit has side-effects:
- *	  when MSTR is cleared, the RINGPTR's get reset and the legacy UART mode
- *	  (in contrast to busmaster access mode) gets enabled.
- *	- clearing ENRX or setting ENTX while data is received may stall the
- *	  receive fifo until ENRX reenabled _and_ another packet arrives
- *	- SIRFILT means the chip performs the required unwrapping of hardware
- *	  headers (XBOF's, BOF/EOF) and un-escaping in the _receive_ direction.
- *	  Only the resulting IrLAP payload is copied to the receive buffers -
- *	  but with the 16bit FCS still encluded. Question remains, whether it
- *	  was already checked or we should do it before passing the packet to IrLAP?
- */
-
-enum vlsi_pio_ircfg {
-	IRCFG_LOOP	= 0x4000,	/* enable loopback test mode */
-	IRCFG_ENTX	= 0x1000,	/* transmit enable */
-	IRCFG_ENRX	= 0x0800,	/* receive enable */
-	IRCFG_MSTR	= 0x0400,	/* master enable */
-	IRCFG_RXANY	= 0x0200,	/* receive any packet */
-	IRCFG_CRC16	= 0x0080,	/* 16bit (not 32bit) CRC select for MIR/FIR */
-	IRCFG_FIR	= 0x0040,	/* FIR 4PPM encoding mode enable */
-	IRCFG_MIR	= 0x0020,	/* MIR HDLC encoding mode enable */
-	IRCFG_SIR	= 0x0010,	/* SIR encoding mode enable */
-	IRCFG_SIRFILT	= 0x0008,	/* enable SIR decode filter (receiver unwrapping) */
-	IRCFG_SIRTEST	= 0x0004,	/* allow SIR decode filter when not in SIR mode */
-	IRCFG_TXPOL	= 0x0002,	/* invert tx polarity when set */
-	IRCFG_RXPOL	= 0x0001	/* invert rx polarity when set */
-};
-
-/* ------------------------------------------ */
-
-/* VLSI_PIO_SIRFLAG: SIR Flag Register (u16, ro) */
-
-/* register contains hardcoded BOF=0xc0 at [7:0] and EOF=0xc1 at [15:8]
- * which is used for unwrapping received frames in SIR decode-filter mode
- */
-
-/* ------------------------------------------ */
-
-/* VLSI_PIO_IRENABLE: IR Enable Register (u16, rw/ro) */
-
-/* notes:
- *	- IREN acts as gate for latching the configured IR mode information
- *	  from IRCFG and IRPHYCTL when IREN=reset and applying them when
- *	  IREN gets set afterwards.
- *	- ENTXST reflects IRCFG_ENTX
- *	- ENRXST = IRCFG_ENRX && (!IRCFG_ENTX || IRCFG_LOOP)
- */
-
-enum vlsi_pio_irenable {
-	IRENABLE_PHYANDCLOCK	= 0x8000,  /* enable IR phy and gate the mode config (rw) */
-	IRENABLE_CFGER		= 0x4000,  /* mode configuration error (ro) */
-	IRENABLE_FIR_ON		= 0x2000,  /* FIR on status (ro) */
-	IRENABLE_MIR_ON		= 0x1000,  /* MIR on status (ro) */
-	IRENABLE_SIR_ON		= 0x0800,  /* SIR on status (ro) */
-	IRENABLE_ENTXST		= 0x0400,  /* transmit enable status (ro) */
-	IRENABLE_ENRXST		= 0x0200,  /* Receive enable status (ro) */
-	IRENABLE_CRC16_ON	= 0x0100   /* 16bit (not 32bit) CRC enabled status (ro) */
-};
-
-#define	  IRENABLE_MASK	    0xff00  /* Read mask */
-
-/* ------------------------------------------ */
-
-/* VLSI_PIO_PHYCTL: IR Physical Layer Current Control Register (u16, ro) */
-
-/* read-back of the currently applied physical layer status.
- * applied from VLSI_PIO_NPHYCTL at rising edge of IRENABLE_PHYANDCLOCK
- * contents identical to VLSI_PIO_NPHYCTL (see below)
- */
-
-/* ------------------------------------------ */
-
-/* VLSI_PIO_NPHYCTL: IR Physical Layer Next Control Register (u16, rw) */
-
-/* latched during IRENABLE_PHYANDCLOCK=0 and applied at 0-1 transition
- *
- * consists of BAUD[15:10], PLSWID[9:5] and PREAMB[4:0] bits defined as follows:
- *
- * SIR-mode:	BAUD = (115.2kHz / baudrate) - 1
- *		PLSWID = (pulsetime * freq / (BAUD+1)) - 1
- *			where pulsetime is the requested IrPHY pulse width
- *			and freq is 8(16)MHz for 40(48)MHz primary input clock
- *		PREAMB: don't care for SIR
- *
- *		The nominal SIR pulse width is 3/16 bit time so we have PLSWID=12
- *		fixed for all SIR speeds at 40MHz input clock (PLSWID=24 at 48MHz).
- *		IrPHY also allows shorter pulses down to the nominal pulse duration
- *		at 115.2kbaud (minus some tolerance) which is 1.41 usec.
- *		Using the expression PLSWID = 12/(BAUD+1)-1 (multiplied by two for 48MHz)
- *		we get the minimum acceptable PLSWID values according to the VLSI
- *		specification, which provides 1.5 usec pulse width for all speeds (except
- *		for 2.4kbaud getting 6usec). This is fine with IrPHY v1.3 specs and
- *		reduces the transceiver power which drains the battery. At 9.6kbaud for
- *		example this amounts to more than 90% battery power saving!
- *
- * MIR-mode:	BAUD = 0
- *		PLSWID = 9(10) for 40(48) MHz input clock
- *			to get nominal MIR pulse width
- *		PREAMB = 1
- *
- * FIR-mode:	BAUD = 0
- *		PLSWID: don't care
- *		PREAMB = 15
- */
-
-#define PHYCTL_BAUD_SHIFT	10
-#define PHYCTL_BAUD_MASK	0xfc00
-#define PHYCTL_PLSWID_SHIFT	5
-#define PHYCTL_PLSWID_MASK	0x03e0
-#define PHYCTL_PREAMB_SHIFT	0
-#define PHYCTL_PREAMB_MASK	0x001f
-
-#define PHYCTL_TO_BAUD(bwp)	(((bwp)&PHYCTL_BAUD_MASK)>>PHYCTL_BAUD_SHIFT)
-#define PHYCTL_TO_PLSWID(bwp)	(((bwp)&PHYCTL_PLSWID_MASK)>>PHYCTL_PLSWID_SHIFT)
-#define PHYCTL_TO_PREAMB(bwp)	(((bwp)&PHYCTL_PREAMB_MASK)>>PHYCTL_PREAMB_SHIFT)
-
-#define BWP_TO_PHYCTL(b,w,p)	((((b)<<PHYCTL_BAUD_SHIFT)&PHYCTL_BAUD_MASK) \
-				 | (((w)<<PHYCTL_PLSWID_SHIFT)&PHYCTL_PLSWID_MASK) \
-				 | (((p)<<PHYCTL_PREAMB_SHIFT)&PHYCTL_PREAMB_MASK))
-
-#define BAUD_BITS(br)		((115200/(br))-1)
-
-static inline unsigned
-calc_width_bits(unsigned baudrate, unsigned widthselect, unsigned clockselect)
-{
-	unsigned	tmp;
-
-	if (widthselect)	/* nominal 3/16 puls width */
-		return (clockselect) ? 12 : 24;
-
-	tmp = ((clockselect) ? 12 : 24) / (BAUD_BITS(baudrate)+1);
-
-	/* intermediate result of integer division needed here */
-
-	return (tmp>0) ? (tmp-1) : 0;
-}
-
-#define PHYCTL_SIR(br,ws,cs)	BWP_TO_PHYCTL(BAUD_BITS(br),calc_width_bits((br),(ws),(cs)),0)
-#define PHYCTL_MIR(cs)		BWP_TO_PHYCTL(0,((cs)?9:10),1)
-#define PHYCTL_FIR		BWP_TO_PHYCTL(0,0,15)
-
-/* quite ugly, I know. But implementing these calculations here avoids
- * having magic numbers in the code and allows some playing with pulsewidths
- * without risk to violate the standards.
- * FWIW, here is the table for reference:
- *
- * baudrate	BAUD	min-PLSWID	nom-PLSWID	PREAMB
- *     2400	  47	   0(0)		   12(24)	   0
- *     9600	  11	   0(0)		   12(24)	   0
- *    19200	   5	   1(2)		   12(24)	   0
- *    38400	   2	   3(6)	           12(24)	   0
- *    57600	   1	   5(10)	   12(24)	   0
- *   115200	   0	  11(22)	   12(24)	   0
- *	MIR	   0	    -		    9(10)	   1
- *	FIR	   0        -               0		  15
- *
- * note: x(y) means x-value for 40MHz / y-value for 48MHz primary input clock
- */
-
-/* ------------------------------------------ */
-
-
-/* VLSI_PIO_MAXPKT: Maximum Packet Length register (u16, rw) */
-
-/* maximum acceptable length for received packets */
-
-/* hw imposed limitation - register uses only [11:0] */
-#define MAX_PACKET_LENGTH	0x0fff
-
-/* IrLAP I-field (apparently not defined elsewhere) */
-#define IRDA_MTU		2048
-
-/* complete packet consists of A(1)+C(1)+I(<=IRDA_MTU) */
-#define IRLAP_SKB_ALLOCSIZE	(1+1+IRDA_MTU)
-
-/* the buffers we use to exchange frames with the hardware need to be
- * larger than IRLAP_SKB_ALLOCSIZE because we may have up to 4 bytes FCS
- * appended and, in SIR mode, a lot of frame wrapping bytes. The worst
- * case appears to be a SIR packet with I-size==IRDA_MTU and all bytes
- * requiring to be escaped to provide transparency. Furthermore, the peer
- * might ask for quite a number of additional XBOFs:
- *	up to 115+48 XBOFS		 163
- *	regular BOF			   1
- *	A-field				   1
- *	C-field				   1
- *	I-field, IRDA_MTU, all escaped	4096
- *	FCS (16 bit at SIR, escaped)	   4
- *	EOF				   1
- * AFAICS nothing in IrLAP guarantees A/C field not to need escaping
- * (f.e. 0xc0/0xc1 - i.e. BOF/EOF - are legal values there) so in the
- * worst case we have 4269 bytes total frame size.
- * However, the VLSI uses 12 bits only for all buffer length values,
- * which limits the maximum useable buffer size <= 4095.
- * Note this is not a limitation in the receive case because we use
- * the SIR filtering mode where the hw unwraps the frame and only the
- * bare packet+fcs is stored into the buffer - in contrast to the SIR
- * tx case where we have to pass frame-wrapped packets to the hw.
- * If this would ever become an issue in real life, the only workaround
- * I see would be using the legacy UART emulation in SIR mode.
- */
-
-#define XFER_BUF_SIZE		MAX_PACKET_LENGTH
-
-/* ------------------------------------------ */
-
-/* VLSI_PIO_RCVBCNT: Receive Byte Count Register (u16, ro) */
-
-/* receive packet counter gets incremented on every non-filtered
- * byte which was put in the receive fifo and reset for each
- * new packet. Used to decide whether we are just in the middle
- * of receiving
- */
-
-/* better apply the [11:0] mask when reading, as some docs say the
- * reserved [15:12] would return 1 when reading - which is wrong AFAICS
- */
-#define RCVBCNT_MASK	0x0fff
-
-/******************************************************************/
-
-/* descriptors for rx/tx ring
- *
- * accessed by hardware - don't change!
- *
- * the descriptor is owned by hardware, when the ACTIVE status bit
- * is set and nothing (besides reading status to test the bit)
- * shall be done. The bit gets cleared by hw, when the descriptor
- * gets closed. Premature reaping of descriptors owned be the chip
- * can be achieved by disabling IRCFG_MSTR
- *
- * Attention: Writing addr overwrites status!
- *
- * ### FIXME: depends on endianess (but there ain't no non-i586 ob800 ;-)
- */
-
-struct ring_descr_hw {
-	volatile u16	rd_count;	/* tx/rx count [11:0] */
-	u16		reserved;
-	union {
-		u32	addr;		/* [23:0] of the buffer's busaddress */
-		struct {
-			u8		addr_res[3];
-			volatile u8	status;		/* descriptor status */
-		} rd_s __attribute__((packed));
-	} rd_u __attribute((packed));
-} __attribute__ ((packed));
-
-#define rd_addr		rd_u.addr
-#define rd_status	rd_u.rd_s.status
-
-/* ring descriptor status bits */
-
-#define RD_ACTIVE		0x80	/* descriptor owned by hw (both TX,RX) */
-
-/* TX ring descriptor status */
-
-#define	RD_TX_DISCRC		0x40	/* do not send CRC (for SIR) */
-#define	RD_TX_BADCRC		0x20	/* force a bad CRC */
-#define	RD_TX_PULSE		0x10	/* send indication pulse after this frame (MIR/FIR) */
-#define	RD_TX_FRCEUND		0x08	/* force underrun */
-#define	RD_TX_CLRENTX		0x04	/* clear ENTX after this frame */
-#define	RD_TX_UNDRN		0x01	/* TX fifo underrun (probably PCI problem) */
-
-/* RX ring descriptor status */
-
-#define RD_RX_PHYERR		0x40	/* physical encoding error */
-#define RD_RX_CRCERR		0x20	/* CRC error (MIR/FIR) */
-#define RD_RX_LENGTH		0x10	/* frame exceeds buffer length */
-#define RD_RX_OVER		0x08	/* RX fifo overrun (probably PCI problem) */
-#define RD_RX_SIRBAD		0x04	/* EOF missing: BOF follows BOF (SIR, filtered) */
-
-#define RD_RX_ERROR		0x7c	/* any error in received frame */
-
-/* the memory required to hold the 2 descriptor rings */
-#define HW_RING_AREA_SIZE	(2 * MAX_RING_DESCR * sizeof(struct ring_descr_hw))
-
-/******************************************************************/
-
-/* sw-ring descriptors consists of a bus-mapped transfer buffer with
- * associated skb and a pointer to the hw entry descriptor
- */
-
-struct ring_descr {
-	struct ring_descr_hw	*hw;
-	struct sk_buff		*skb;
-	void			*buf;
-};
-
-/* wrappers for operations on hw-exposed ring descriptors
- * access to the hw-part of the descriptors must use these.
- */
-
-static inline int rd_is_active(struct ring_descr *rd)
-{
-	return ((rd->hw->rd_status & RD_ACTIVE) != 0);
-}
-
-static inline void rd_activate(struct ring_descr *rd)
-{
-	rd->hw->rd_status |= RD_ACTIVE;
-}
-
-static inline void rd_set_status(struct ring_descr *rd, u8 s)
-{
-	rd->hw->rd_status = s;	 /* may pass ownership to the hardware */
-}
-
-static inline void rd_set_addr_status(struct ring_descr *rd, dma_addr_t a, u8 s)
-{
-	/* order is important for two reasons:
-	 *  - overlayed: writing addr overwrites status
-	 *  - we want to write status last so we have valid address in
-	 *    case status has RD_ACTIVE set
-	 */
-
-	if ((a & ~DMA_MASK_MSTRPAGE)>>24 != MSTRPAGE_VALUE) {
-		ERROR("%s: pci busaddr inconsistency!\n", __FUNCTION__);
-		dump_stack();
-		return;
-	}
-
-	a &= DMA_MASK_MSTRPAGE;  /* clear highbyte to make sure we won't write
-				  * to status - just in case MSTRPAGE_VALUE!=0
-				  */
-	rd->hw->rd_addr = cpu_to_le32(a);
-	wmb();
-	rd_set_status(rd, s);	 /* may pass ownership to the hardware */
-}
-
-static inline void rd_set_count(struct ring_descr *rd, u16 c)
-{
-	rd->hw->rd_count = cpu_to_le16(c);
-}
-
-static inline u8 rd_get_status(struct ring_descr *rd)
-{
-	return rd->hw->rd_status;
-}
-
-static inline dma_addr_t rd_get_addr(struct ring_descr *rd)
-{
-	dma_addr_t	a;
-
-	a = le32_to_cpu(rd->hw->rd_addr);
-	return (a & DMA_MASK_MSTRPAGE) | (MSTRPAGE_VALUE << 24);
-}
-
-static inline u16 rd_get_count(struct ring_descr *rd)
-{
-	return le16_to_cpu(rd->hw->rd_count);
-}
-
-/******************************************************************/
-
-/* sw descriptor rings for rx, tx:
- *
- * operations follow producer-consumer paradigm, with the hw
- * in the middle doing the processing.
- * ring size must be power of two.
- *
- * producer advances r->tail after inserting for processing
- * consumer advances r->head after removing processed rd
- * ring is empty if head==tail / full if (tail+1)==head
- */
-
-struct vlsi_ring {
-	struct pci_dev		*pdev;
-	int			dir;
-	unsigned		len;
-	unsigned		size;
-	unsigned		mask;
-	atomic_t		head, tail;
-	struct ring_descr	*rd;
-};
-
-/* ring processing helpers */
-
-static inline struct ring_descr *ring_last(struct vlsi_ring *r)
-{
-	int t;
-
-	t = atomic_read(&r->tail) & r->mask;
-	return (((t+1) & r->mask) == (atomic_read(&r->head) & r->mask)) ? NULL : &r->rd[t];
-}
-
-static inline struct ring_descr *ring_put(struct vlsi_ring *r)
-{
-	atomic_inc(&r->tail);
-	return ring_last(r);
-}
-
-static inline struct ring_descr *ring_first(struct vlsi_ring *r)
-{
-	int h;
-
-	h = atomic_read(&r->head) & r->mask;
-	return (h == (atomic_read(&r->tail) & r->mask)) ? NULL : &r->rd[h];
-}
-
-static inline struct ring_descr *ring_get(struct vlsi_ring *r)
-{
-	atomic_inc(&r->head);
-	return ring_first(r);
-}
-
-/******************************************************************/
-
-/* our private compound VLSI-PCI-IRDA device information */
-
-typedef struct vlsi_irda_dev {
-	struct pci_dev		*pdev;
-	struct net_device_stats	stats;
-
-	struct irlap_cb		*irlap;
-
-	struct qos_info		qos;
-
-	unsigned		mode;
-	int			baud, new_baud;
-
-	dma_addr_t		busaddr;
-	void			*virtaddr;
-	struct vlsi_ring	*tx_ring, *rx_ring;
-
-	struct timeval		last_rx;
-
-	spinlock_t		lock;
-	struct semaphore	sem;
-
-	u32			cfg_space[64/sizeof(u32)];
-	u8			resume_ok;	
-	struct proc_dir_entry	*proc_entry;
-
-} vlsi_irda_dev_t;
-
-/********************************************************/
-
-/* the remapped error flags we use for returning from frame
- * post-processing in vlsi_process_tx/rx() after it was completed
- * by the hardware. These functions either return the >=0 number
- * of transfered bytes in case of success or the negative (-)
- * of the or'ed error flags.
- */
-
-#define VLSI_TX_DROP		0x0001
-#define VLSI_TX_FIFO		0x0002
-
-#define VLSI_RX_DROP		0x0100
-#define VLSI_RX_OVER		0x0200
-#define VLSI_RX_LENGTH  	0x0400
-#define VLSI_RX_FRAME		0x0800
-#define VLSI_RX_CRC		0x1000
-
-/********************************************************/
-
-#endif /* IRDA_VLSI_FIR_H */
-
diff --git a/include/net/irda/w83977af.h b/include/net/irda/w83977af.h
deleted file mode 100644
index 04476c2e9121..000000000000
--- a/include/net/irda/w83977af.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef W83977AF_H
-#define W83977AF_H
-
-#define W977_EFIO_BASE 0x370
-#define W977_EFIO2_BASE 0x3f0
-#define W977_DEVICE_IR 0x06
-
-
-/*
- * Enter extended function mode
- */
-static inline void w977_efm_enter(unsigned int efio)
-{
-        outb(0x87, efio);
-        outb(0x87, efio);
-}
-
-/*
- * Select a device to configure 
- */
-
-static inline void w977_select_device(__u8 devnum, unsigned int efio)
-{
-	outb(0x07, efio);
-	outb(devnum, efio+1);
-} 
-
-/* 
- * Write a byte to a register
- */
-static inline void w977_write_reg(__u8 reg, __u8 value, unsigned int efio)
-{
-	outb(reg, efio);
-	outb(value, efio+1);
-}
-
-/*
- * read a byte from a register
- */
-static inline __u8 w977_read_reg(__u8 reg, unsigned int efio)
-{
-	outb(reg, efio);
-	return inb(efio+1);
-}
-
-/*
- * Exit extended function mode
- */
-static inline void w977_efm_exit(unsigned int efio)
-{
-	outb(0xAA, efio);
-}
-#endif
diff --git a/include/net/irda/w83977af_ir.h b/include/net/irda/w83977af_ir.h
deleted file mode 100644
index c578ddc1a0eb..000000000000
--- a/include/net/irda/w83977af_ir.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*********************************************************************
- *                
- * Filename:      w83977af_ir.h
- * Version:       
- * Description:   
- * Status:        Experimental.
- * Author:        Paul VanderSpek
- * Created at:    Thu Nov 19 13:55:34 1998
- * Modified at:   Tue Jan 11 13:08:19 2000
- * Modified by:   Dag Brattli <dagb@cs.uit.no>
- * 
- *     Copyright (c) 1998-2000 Dag Brattli, All Rights Reserved.
- *      
- *     This program is free software; you can redistribute it and/or 
- *     modify it under the terms of the GNU General Public License as 
- *     published by the Free Software Foundation; either version 2 of 
- *     the License, or (at your option) any later version.
- *  
- *     Neither Dag Brattli nor University of Tromsų admit liability nor
- *     provide warranty for any of this software. This material is 
- *     provided "AS-IS" and at no charge.
- *     
- ********************************************************************/
-
-#ifndef W83977AF_IR_H
-#define W83977AF_IR_H
-
-#include <asm/io.h>
-
-/* Flags for configuration register CRF0 */
-#define ENBNKSEL	0x01
-#define APEDCRC		0x02
-#define TXW4C           0x04
-#define RXW4C           0x08
-
-/* Bank 0 */
-#define RBR             0x00 /* Receiver buffer register */
-#define TBR             0x00 /* Transmitter buffer register */
-
-#define ICR		0x01 /* Interrupt configuration register */
-#define ICR_ERBRI       0x01 /* Receiver buffer register interrupt */
-#define ICR_ETBREI      0x02 /* Transeiver empty interrupt */
-#define ICR_EUSRI	0x04//* IR status interrupt */
-#define ICR_EHSRI       0x04
-#define ICR_ETXURI      0x04 /* Tx underrun */
-#define ICR_EDMAI	0x10 /* DMA interrupt */
-#define ICR_ETXTHI      0x20 /* Transmitter threshold interrupt */
-#define ICR_EFSFI       0x40 /* Frame status FIFO interrupt */
-#define ICR_ETMRI       0x80 /* Timer interrupt */
-
-#define UFR		0x02 /* FIFO control register */
-#define UFR_EN_FIFO     0x01 /* Enable FIFO's */
-#define UFR_RXF_RST     0x02 /* Reset Rx FIFO */
-#define UFR_TXF_RST     0x04 /* Reset Tx FIFO */
-#define UFR_RXTL	0x80 /* Rx FIFO threshold (set to 16) */
-#define UFR_TXTL	0x20 /* Tx FIFO threshold (set to 17) */
-
-#define ISR		0x02 /* Interrupt status register */
-#define ISR_RXTH_I	0x01 /* Receive threshold interrupt */
-#define ISR_TXEMP_I     0x02 /* Transmitter empty interrupt */
-#define ISR_FEND_I	0x04
-#define ISR_DMA_I	0x10
-#define ISR_TXTH_I	0x20 /* Transmitter threshold interrupt */
-#define ISR_FSF_I       0x40
-#define ISR_TMR_I       0x80 /* Timer interrupt */
-
-#define UCR             0x03 /* Uart control register */
-#define UCR_DLS8        0x03 /* 8N1 */
-
-#define SSR 	        0x03 /* Sets select register */
-#define SET0 	        UCR_DLS8        /* Make sure we keep 8N1 */
-#define SET1	        (0x80|UCR_DLS8) /* Make sure we keep 8N1 */
-#define SET2	        0xE0
-#define SET3	        0xE4
-#define SET4	        0xE8
-#define SET5	        0xEC
-#define SET6	        0xF0
-#define SET7	        0xF4
-
-#define HCR		0x04
-#define HCR_MODE_MASK	~(0xD0)
-#define HCR_SIR         0x60
-#define HCR_MIR_576  	0x20	
-#define HCR_MIR_1152	0x80
-#define HCR_FIR		0xA0
-#define HCR_EN_DMA	0x04
-#define HCR_EN_IRQ	0x08
-#define HCR_TX_WT	0x08
-
-#define USR             0x05 /* IR status register */
-#define USR_RDR         0x01 /* Receive data ready */
-#define USR_TSRE        0x40 /* Transmitter empty? */
-
-#define AUDR            0x07
-#define AUDR_SFEND      0x08 /* Set a frame end */
-#define AUDR_RXBSY      0x20 /* Rx busy */
-#define AUDR_UNDR       0x40 /* Transeiver underrun */
-
-/* Set 2 */
-#define ABLL            0x00 /* Advanced baud rate divisor latch (low byte) */
-#define ABHL            0x01 /* Advanced baud rate divisor latch (high byte) */
-
-#define ADCR1		0x02
-#define ADCR1_ADV_SL	0x01	
-#define ADCR1_D_CHSW	0x08	/* the specs are wrong. its bit 3, not 4 */
-#define ADCR1_DMA_F	0x02
-
-#define ADCR2		0x04
-#define ADCR2_TXFS32	0x01
-#define ADCR2_RXFS32	0x04
-
-#define RXFDTH          0x07
-
-/* Set 3 */
-#define AUID		0x00
-
-/* Set 4 */
-#define TMRL            0x00 /* Timer value register (low byte) */
-#define TMRH            0x01 /* Timer value register (high byte) */
-
-#define IR_MSL          0x02 /* Infrared mode select */
-#define IR_MSL_EN_TMR   0x01 /* Enable timer */
-
-#define TFRLL		0x04 /* Transmitter frame length (low byte) */
-#define TFRLH		0x05 /* Transmitter frame length (high byte) */
-#define RFRLL		0x06 /* Receiver frame length (low byte) */
-#define RFRLH		0x07 /* Receiver frame length (high byte) */
-
-/* Set 5 */
-
-#define FS_FO           0x05 /* Frame status FIFO */
-#define FS_FO_FSFDR     0x80 /* Frame status FIFO data ready */
-#define FS_FO_LST_FR    0x40 /* Frame lost */
-#define FS_FO_MX_LEX    0x10 /* Max frame len exceeded */
-#define FS_FO_PHY_ERR   0x08 /* Physical layer error */
-#define FS_FO_CRC_ERR   0x04 
-#define FS_FO_RX_OV     0x02 /* Receive overrun */
-#define FS_FO_FSF_OV    0x01 /* Frame status FIFO overrun */
-#define FS_FO_ERR_MSK   0x5f /* Error mask */
-
-#define RFLFL           0x06
-#define RFLFH           0x07
-
-/* Set 6 */
-#define IR_CFG2		0x00
-#define IR_CFG2_DIS_CRC	0x02
-
-/* Set 7 */
-#define IRM_CR		0x07 /* Infrared module control register */
-#define IRM_CR_IRX_MSL	0x40
-#define IRM_CR_AF_MNT   0x80 /* Automatic format */
-
-/* For storing entries in the status FIFO */
-struct st_fifo_entry {
-	int status;
-	int len;
-};
-
-struct st_fifo {
-	struct st_fifo_entry entries[10];
-	int head;
-	int tail;
-	int len;
-};
-
-/* Private data for each instance */
-struct w83977af_ir {
-	struct st_fifo st_fifo;
-
-	int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
-	int tx_len;          /* Number of frames in tx_buff */
-
-	struct net_device *netdev; /* Yes! we are some kind of netdevice */
-	struct net_device_stats stats;
-	
-	struct irlap_cb    *irlap; /* The link layer we are binded to */
-	struct qos_info     qos;   /* QoS capabilities for this device */
-	
-	chipio_t io;               /* IrDA controller information */
-	iobuff_t tx_buff;          /* Transmit buffer */
-	iobuff_t rx_buff;          /* Receive buffer */
-
-	/* Note : currently locking is *very* incomplete, but this
-	 * will get you started. Check in nsc-ircc.c for a proper
-	 * locking strategy. - Jean II */
-	spinlock_t lock;           /* For serializing operations */
-	
-	__u32 new_speed;
-};
-
-static inline void switch_bank( int iobase, int set)
-{
-	outb(set, iobase+SSR);
-}
-
-#endif