diff options
| author | Miles Bader <miles@lsi.nec.co.jp> | 2003-04-07 22:25:26 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@home.transmeta.com> | 2003-04-07 22:25:26 -0700 |
| commit | 050e6ae52a235525ce15452d66ee80d24e00be74 (patch) | |
| tree | 1da16d46db8816eb3f9a947bb2e2540f2ce0143b /include | |
| parent | 47ebae0827768cf161cfe61d5202369ed0f6c991 (diff) | |
[PATCH] On the v850/nb85e, acknowledge interrupts immediately after handling them
Previously, it was done automatically by the `reti' isntruction upon
returning from the kernel, but that doesn't do the correct thing in
various cases, for instance if there's a context switch, or a softirq.
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-v850/nb85e_intc.h | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/include/asm-v850/nb85e_intc.h b/include/asm-v850/nb85e_intc.h index a093ae3a17c9..d81b777363cc 100644 --- a/include/asm-v850/nb85e_intc.h +++ b/include/asm-v850/nb85e_intc.h @@ -1,8 +1,8 @@ /* * include/asm-v850/nb85e_intc.h -- NB85E cpu core interrupt controller (INTC) * - * Copyright (C) 2001,02 NEC Corporation - * Copyright (C) 2001,02 Miles Bader <miles@gnu.org> + * Copyright (C) 2001,02,03 NEC Electronics Corporation + * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org> * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this @@ -26,7 +26,7 @@ address. */ #define NB85E_INTC_IC_BASE_ADDR 0xFFFFF110 #define NB85E_INTC_IC_ADDR(irq) (NB85E_INTC_IC_BASE_ADDR + ((irq) << 1)) -#define NB85E_INTC_IC(irq) (*(char *)NB85E_INTC_IC_ADDR(irq)) +#define NB85E_INTC_IC(irq) (*(volatile u8 *)NB85E_INTC_IC_ADDR(irq)) /* Encode priority PR for storing in an interrupt control register. */ #define NB85E_INTC_IC_PR(pr) (pr) /* Interrupt disable bit in an interrupt control register. */ @@ -36,6 +36,13 @@ #define NB85E_INTC_IC_IF_BIT 7 #define NB85E_INTC_IC_IF (1 << NB85E_INTC_IC_IF_BIT) +/* The ISPR (In-service priority register) contains one bit for each interrupt + priority level, which is set to one when that level is currently being + serviced (and thus blocking any interrupts of equal or lesser level). */ +#define NB85E_INTC_ISPR_ADDR 0xFFFFF1FA +#define NB85E_INTC_ISPR (*(volatile u8 *)NB85E_INTC_ISPR_ADDR) + + #ifndef __ASSEMBLY__ /* Enable interrupt handling for interrupt IRQ. */ |