[PATCH] sh: SH7705/SH7300 subtype support, ST40 updates.

From: Paul Mundt <lethal@Linux-SH.ORG>

This adds support for the SH7705 and SH7300 subtypes and also updates some
ST40-specific FRQCR handling code.

Signed-off-by: Alex Bennee <kernel-hacker@bennee.com>
Signed-off-by: Hiroshi DOYU <Hiroshi_DOYU@montavista.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

4 files changed, 274 insertions, 23 deletions

diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h
index 9ceca407fe60..154d774f982f 100644
--- a/include/asm-sh/bugs.h
+++ b/include/asm-sh/bugs.h
@@ -26,7 +26,7 @@ static void __init check_bugs(void)
 	case CPU_SH7604:
 		*p++ = '2';
 		break;
-	case CPU_SH7708 ... CPU_SH7729:
+	case CPU_SH7705 ... CPU_SH7300:
 		*p++ = '3';
 		break;
 	case CPU_SH7750 ... CPU_ST40GX1:
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 7dd2a5ae10b5..58bd8df7a53d 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -15,9 +15,15 @@
 #include <asm/machvec.h>
 #include <asm/ptrace.h>		/* for pt_regs */
 
+#if defined(CONFIG_SH_HP600) || \
+    defined(CONFIG_SH_RTS7751R2D) || \
+    defined(CONFIG_SH_HS7751RVOIP)
+#include <asm/mach/ide.h>
+#endif
+
 #if defined(CONFIG_CPU_SH3)
-#define INTC_IPRA  	0xfffffee2UL
-#define INTC_IPRB  	0xfffffee4UL
+#define INTC_IPRA	0xfffffee2UL
+#define INTC_IPRB	0xfffffee4UL
 #elif defined(CONFIG_CPU_SH4)
 #define INTC_IPRA	0xffd00004UL
 #define INTC_IPRB	0xffd00008UL
@@ -25,6 +31,15 @@
 #define INTC_IPRD	0xffd00010UL
 #endif
 
+#ifdef CONFIG_IDE
+# ifndef IRQ_CFCARD
+#  define IRQ_CFCARD	14
+# endif
+# ifndef IRQ_PCMCIA
+#  define IRQ_PCMCIA	15
+# endif
+#endif
+
 #define TIMER_IRQ	16
 #define TIMER_IPR_ADDR	INTC_IPRA
 #define TIMER_IPR_POS	 3
@@ -48,6 +63,111 @@
 #define DMA_IPR_ADDR	INTC_IPRE
 #define DMA_IPR_POS	3
 #define DMA_PRIORITY	7
+#if defined(CONFIG_CPU_SUBTYPE_SH7300)
+/* TMU2 */
+#define TIMER2_IRQ      18
+#define TIMER2_IPR_ADDR INTC_IPRA
+#define TIMER2_IPR_POS   1
+#define TIMER2_PRIORITY  2
+
+/* WDT */
+#define WDT_IRQ		27
+#define WDT_IPR_ADDR	INTC_IPRB
+#define WDT_IPR_POS	 3
+#define WDT_PRIORITY	 2
+
+/* SIM (SIM Card Module) */
+#define SIM_ERI_IRQ	23
+#define SIM_RXI_IRQ	24
+#define SIM_TXI_IRQ	25
+#define SIM_TEND_IRQ	26
+#define SIM_IPR_ADDR	INTC_IPRB
+#define SIM_IPR_POS	 1
+#define SIM_PRIORITY	 2
+
+/* VIO (Video I/O) */
+#define VIO_IRQ		52
+#define VIO_IPR_ADDR	INTC_IPRE
+#define VIO_IPR_POS	 2
+#define VIO_PRIORITY	 2
+
+/* MFI (Multi Functional Interface) */
+#define MFI_IRQ		56
+#define MFI_IPR_ADDR	INTC_IPRE
+#define MFI_IPR_POS	 1
+#define MFI_PRIORITY	 2
+
+/* VPU (Video Processing Unit) */
+#define VPU_IRQ		60
+#define VPU_IPR_ADDR	INTC_IPRE
+#define VPU_IPR_POS	 0
+#define VPU_PRIORITY	 2
+
+/* KEY (Key Scan Interface) */
+#define KEY_IRQ		79
+#define KEY_IPR_ADDR	INTC_IPRF
+#define KEY_IPR_POS	 3
+#define KEY_PRIORITY	 2
+
+/* CMT (Compare Match Timer) */
+#define CMT_IRQ		104
+#define CMT_IPR_ADDR	INTC_IPRF
+#define CMT_IPR_POS	 0
+#define CMT_PRIORITY	 2
+
+/* DMAC(1) */
+#define DMTE0_IRQ	48
+#define DMTE1_IRQ	49
+#define DMTE2_IRQ	50
+#define DMTE3_IRQ	51
+#define DMA1_IPR_ADDR	INTC_IPRE
+#define DMA1_IPR_POS	3
+#define DMA1_PRIORITY	7
+
+/* DMAC(2) */
+#define DMTE4_IRQ	76
+#define DMTE5_IRQ	77
+#define DMA2_IPR_ADDR	INTC_IPRF
+#define DMA2_IPR_POS	2
+#define DMA2_PRIORITY	7
+
+/* SIOF0 */
+#define SIOF0_IRQ	84
+#define SIOF0_IPR_ADDR	INTC_IPRH
+#define SIOF0_IPR_POS	3
+#define SIOF0_PRIORITY	3
+
+/* FLCTL (Flash Memory Controller) */
+#define FLSTE_IRQ	92
+#define FLTEND_IRQ	93
+#define FLTRQ0_IRQ	94
+#define FLTRQ1_IRQ	95
+#define FLCTL_IPR_ADDR	INTC_IPRH
+#define FLCTL_IPR_POS	1
+#define FLCTL_PRIORITY	3
+
+/* IIC (IIC Bus Interface) */
+#define IIC_ALI_IRQ	96
+#define IIC_TACKI_IRQ	97
+#define IIC_WAITI_IRQ	98
+#define IIC_DTEI_IRQ	99
+#define IIC_IPR_ADDR	INTC_IPRH
+#define IIC_IPR_POS	0
+#define IIC_PRIORITY	3
+
+/* SIO0 */
+#define SIO0_IRQ	88
+#define SIO0_IPR_ADDR	INTC_IPRI
+#define SIO0_IPR_POS	3
+#define SIO0_PRIORITY	3
+
+/* SIU (Sound Interface Unit) */
+#define SIU_IRQ		108
+#define SIU_IPR_ADDR	INTC_IPRJ
+#define SIU_IPR_POS	1
+#define SIU_PRIORITY	3
+
+#endif
 #elif defined(CONFIG_CPU_SH4)
 #define DMTE0_IRQ	34
 #define DMTE1_IRQ	35
@@ -74,7 +194,14 @@
 #define SCI_PRIORITY	3
 #endif
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
+#if defined(CONFIG_CPU_SUBTYPE_SH7300)
+#define SCIF0_IRQ	80
+#define SCIF0_IPR_ADDR	INTC_IPRG
+#define SCIF0_IPR_POS	3
+#define SCIF0_PRIORITY	3
+#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7709)
 #define SCIF_ERI_IRQ	56
 #define SCIF_RXI_IRQ	57
 #define SCIF_BRI_IRQ	58
@@ -127,7 +254,8 @@
 #  define PINT_NR_IRQS   16
 # elif defined(CONFIG_CPU_SUBTYPE_SH7708)
 #  define ONCHIP_NR_IRQS 32
-# elif defined(CONFIG_CPU_SUBTYPE_SH7709)
+# elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
+       defined(CONFIG_CPU_SUBTYPE_SH7705)
 #  define ONCHIP_NR_IRQS 64	// Actually 61
 #  define PINT_NR_IRQS   16
 # elif defined(CONFIG_CPU_SUBTYPE_SH7750)
@@ -138,6 +266,8 @@
 #  define ONCHIP_NR_IRQS 110
 # elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 #  define ONCHIP_NR_IRQS 144
+# elif defined(CONFIG_CPU_SUBTYPE_SH7300)
+#  define ONCHIP_NR_IRQS 109
 # endif
 #endif
 
@@ -207,7 +337,121 @@ extern void make_ipr_irq(unsigned int irq, unsigned int addr,
 			 int pos,  int priority);
 extern void make_imask_irq(unsigned int irq);
 
-#if defined(CONFIG_CPU_SUBTYPE_SH7604)
+#if defined(CONFIG_CPU_SUBTYPE_SH7300)
+#undef INTC_IPRA
+#undef INTC_IPRB
+#define INTC_IPRA  	0xA414FEE2UL
+#define INTC_IPRB  	0xA414FEE4UL
+#define INTC_IPRC  	0xA4140016UL
+#define INTC_IPRD  	0xA4140018UL
+#define INTC_IPRE  	0xA414001AUL
+#define INTC_IPRF  	0xA4080000UL
+#define INTC_IPRG  	0xA4080002UL
+#define INTC_IPRH  	0xA4080004UL
+#define INTC_IPRI  	0xA4080006UL
+#define INTC_IPRJ  	0xA4080008UL
+
+#define INTC_IMR0	0xA4080040UL
+#define INTC_IMR1	0xA4080042UL
+#define INTC_IMR2	0xA4080044UL
+#define INTC_IMR3	0xA4080046UL
+#define INTC_IMR4	0xA4080048UL
+#define INTC_IMR5	0xA408004AUL
+#define INTC_IMR6	0xA408004CUL
+#define INTC_IMR7	0xA408004EUL
+#define INTC_IMR8	0xA4080050UL
+#define INTC_IMR9	0xA4080052UL
+#define INTC_IMR10	0xA4080054UL
+
+#define INTC_IMCR0	0xA4080060UL
+#define INTC_IMCR1	0xA4080062UL
+#define INTC_IMCR2	0xA4080064UL
+#define INTC_IMCR3	0xA4080066UL
+#define INTC_IMCR4	0xA4080068UL
+#define INTC_IMCR5	0xA408006AUL
+#define INTC_IMCR6	0xA408006CUL
+#define INTC_IMCR7	0xA408006EUL
+#define INTC_IMCR8	0xA4080070UL
+#define INTC_IMCR9	0xA4080072UL
+#define INTC_IMCR10	0xA4080074UL
+
+#define INTC_ICR0	0xA414FEE0UL
+#define INTC_ICR1	0xA4140010UL
+
+#define INTC_IRR0	0xA4140004UL
+
+#define PORT_PACR	0xA4050100UL
+#define PORT_PBCR	0xA4050102UL
+#define PORT_PCCR	0xA4050104UL
+#define PORT_PDCR	0xA4050106UL
+#define PORT_PECR	0xA4050108UL
+#define PORT_PFCR	0xA405010AUL
+#define PORT_PGCR	0xA405010CUL
+#define PORT_PHCR	0xA405010EUL
+#define PORT_PJCR	0xA4050110UL
+#define PORT_PKCR	0xA4050112UL
+#define PORT_PLCR	0xA4050114UL
+#define PORT_SCPCR	0xA4050116UL
+#define PORT_PMCR	0xA4050118UL
+#define PORT_PNCR	0xA405011AUL
+#define PORT_PQCR	0xA405011CUL
+
+#define PORT_PSELA	0xA4050140UL
+#define PORT_PSELB	0xA4050142UL
+#define PORT_PSELC	0xA4050144UL
+
+#define PORT_HIZCRA	0xA4050146UL
+#define PORT_HIZCRB	0xA4050148UL
+#define PORT_DRVCR	0xA4050150UL
+
+#define PORT_PADR  	0xA4050120UL
+#define PORT_PBDR  	0xA4050122UL
+#define PORT_PCDR  	0xA4050124UL
+#define PORT_PDDR  	0xA4050126UL
+#define PORT_PEDR  	0xA4050128UL
+#define PORT_PFDR  	0xA405012AUL
+#define PORT_PGDR  	0xA405012CUL
+#define PORT_PHDR  	0xA405012EUL
+#define PORT_PJDR  	0xA4050130UL
+#define PORT_PKDR  	0xA4050132UL
+#define PORT_PLDR  	0xA4050134UL
+#define PORT_SCPDR  	0xA4050136UL
+#define PORT_PMDR  	0xA4050138UL
+#define PORT_PNDR  	0xA405013AUL
+#define PORT_PQDR  	0xA405013CUL
+
+#define IRQ0_IRQ	32
+#define IRQ1_IRQ	33
+#define IRQ2_IRQ	34
+#define IRQ3_IRQ	35
+#define IRQ4_IRQ	36
+#define IRQ5_IRQ	37
+
+#define IRQ0_IPR_ADDR	INTC_IPRC
+#define IRQ1_IPR_ADDR	INTC_IPRC
+#define IRQ2_IPR_ADDR	INTC_IPRC
+#define IRQ3_IPR_ADDR	INTC_IPRC
+#define IRQ4_IPR_ADDR	INTC_IPRD
+#define IRQ5_IPR_ADDR	INTC_IPRD
+
+#define IRQ0_IPR_POS	0
+#define IRQ1_IPR_POS	1
+#define IRQ2_IPR_POS	2
+#define IRQ3_IPR_POS	3
+#define IRQ4_IPR_POS	0
+#define IRQ5_IPR_POS	1
+
+#define IRQ0_PRIORITY	1
+#define IRQ1_PRIORITY	1
+#define IRQ2_PRIORITY	1
+#define IRQ3_PRIORITY	1
+#define IRQ4_PRIORITY	1
+#define IRQ5_PRIORITY	1
+
+extern int ipr_irq_demux(int irq);
+#define __irq_demux(irq) ipr_irq_demux(irq)
+
+#elif defined(CONFIG_CPU_SUBTYPE_SH7604)
 #define INTC_IPRA	0xfffffee2UL
 #define INTC_IPRB	0xfffffe60UL
 
@@ -222,21 +466,27 @@ extern void make_imask_irq(unsigned int irq);
 #define INTC_VCRDMA1	0xffffffa8UL
 
 #define INTC_ICR	0xfffffee0UL
-#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7709)
 #define INTC_IRR0	0xa4000004UL
 #define INTC_IRR1	0xa4000006UL
 #define INTC_IRR2	0xa4000008UL
 
-#define INTC_ICR0  	0xfffffee0UL
-#define INTC_ICR1  	0xa4000010UL
-#define INTC_ICR2  	0xa4000012UL
-#define INTC_INTER 	0xa4000014UL
+#define INTC_ICR0	0xfffffee0UL
+#define INTC_ICR1	0xa4000010UL
+#define INTC_ICR2	0xa4000012UL
+#define INTC_INTER	0xa4000014UL
 
-#define INTC_IPRC  	0xa4000016UL
-#define INTC_IPRD  	0xa4000018UL
-#define INTC_IPRE  	0xa400001aUL
+#define INTC_IPRC	0xa4000016UL
+#define INTC_IPRD	0xa4000018UL
+#define INTC_IPRE	0xa400001aUL
 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
 #define INTC_IPRF	0xa400001cUL
+#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
+#define INTC_IPRF	0xa4080000UL
+#define INTC_IPRG	0xa4080002UL
+#define INTC_IPRH	0xa4080004UL
 #endif
 
 #define PORT_PACR	0xa4000100UL
@@ -307,20 +557,20 @@ extern int ipr_irq_demux(int irq);
 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
 #define INTC2_FIRST_IRQ 64
 #define NR_INTC2_IRQS 25
- 
+
 #define INTC2_BASE0 0xfe080000
 #define INTC2_INTC2MODE  (INTC2_BASE0+0x80)
- 
+
 #define INTC2_INTPRI_OFFSET	0x00
 #define INTC2_INTREQ_OFFSET	0x20
 #define INTC2_INTMSK_OFFSET	0x40
 #define INTC2_INTMSKCLR_OFFSET	0x60
- 
+
 extern void make_intc2_irq(unsigned int irq,unsigned int addr,
                            unsigned int group,int pos,int priority);
- 
-#endif                                                                        
-       
+
+#endif
+
 static inline int generic_irq_demux(int irq)
 {
 	return irq;
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 786d41c3663c..0eaf9d91b54d 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -37,8 +37,8 @@ enum cpu_type {
 	CPU_SH7604,
 
 	/* SH-3 types */
-	CPU_SH7707,  CPU_SH7708, CPU_SH7708S, CPU_SH7708R, CPU_SH7709,
-	CPU_SH7709A, CPU_SH7729, CPU_SH7300,
+	CPU_SH7705, CPU_SH7707,  CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
+	CPU_SH7709, CPU_SH7709A, CPU_SH7729, CPU_SH7300,
 
 	/* SH-4 types */
 	CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
diff --git a/include/asm-sh/ubc.h b/include/asm-sh/ubc.h
index 412a6496ce95..a42dd7adfb4c 100644
--- a/include/asm-sh/ubc.h
+++ b/include/asm-sh/ubc.h
@@ -14,7 +14,8 @@
 #include <asm/cpu/ubc.h>
 
 /* User Break Controller */
-#if defined(CONFIG_CPU_SUBTYPE_SH7709)
+#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7300)
 #define UBC_TYPE_SH7729	(cpu_data->type == CPU_SH7729)
 #else
 #define UBC_TYPE_SH7729	0