merge

104 files changed, 3016 insertions, 2438 deletions

diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h
index 1b6eff5c3113..829c4e2bfd36 100644
--- a/include/acpi/acpixf.h
+++ b/include/acpi/acpixf.h
@@ -345,11 +345,11 @@ acpi_disable_event (
 	u32                             event,
 	u32                             flags);
 
-#ifdef ACPI_FUTURE_USAGE
 acpi_status
 acpi_clear_event (
 	u32                             event);
 
+#ifdef ACPI_FUTURE_USAGE
 acpi_status
 acpi_get_event_status (
 	u32                             event,
diff --git a/include/acpi/processor.h b/include/acpi/processor.h
index 055e97ca13e9..3982834e96ad 100644
--- a/include/acpi/processor.h
+++ b/include/acpi/processor.h
@@ -17,7 +17,7 @@
 
 struct acpi_processor_cx_policy {
 	u32			count;
-	int			state;
+	u32			state;
 	struct {
 		u32			time;
 		u32			ticks;
@@ -38,8 +38,8 @@ struct acpi_processor_cx {
 };
 
 struct acpi_processor_power {
-	int			state;
-	int			default_state;
+	u32			state;
+	u32			default_state;
 	u32			bm_activity;
 	struct acpi_processor_cx states[ACPI_PROCESSOR_MAX_POWER];
 };
diff --git a/include/asm-arm/uaccess.h b/include/asm-arm/uaccess.h
index f36715246407..abda6082b5cb 100644
--- a/include/asm-arm/uaccess.h
+++ b/include/asm-arm/uaccess.h
@@ -108,35 +108,35 @@ extern int __get_user_4(void *);
 extern int __get_user_8(void *);
 extern int __get_user_bad(void);
 
-#define __get_user_x(__r1,__p,__e,__s,__i...)				\
+#define __get_user_x(__r2,__p,__e,__s,__i...)				\
 	   __asm__ __volatile__ (					\
-		__asmeq("%0", "r0") __asmeq("%1", "r1")			\
+		__asmeq("%0", "r0") __asmeq("%1", "r2")			\
 		"bl	__get_user_" #__s				\
-		: "=&r" (__e), "=r" (__r1)				\
+		: "=&r" (__e), "=r" (__r2)				\
 		: "0" (__p)						\
 		: __i, "cc")
 
 #define get_user(x,p)							\
 	({								\
 		const register typeof(*(p)) __user *__p asm("r0") = (p);\
-		register typeof(*(p)) __r1 asm("r1");			\
+		register typeof(*(p)) __r2 asm("r2");			\
 		register int __e asm("r0");				\
 		switch (sizeof(*(__p))) {				\
 		case 1:							\
-			__get_user_x(__r1, __p, __e, 1, "lr");		\
+			__get_user_x(__r2, __p, __e, 1, "lr");		\
 	       		break;						\
 		case 2:							\
-			__get_user_x(__r1, __p, __e, 2, "r2", "lr");	\
+			__get_user_x(__r2, __p, __e, 2, "r3", "lr");	\
 			break;						\
 		case 4:							\
-	       		__get_user_x(__r1, __p, __e, 4, "lr");		\
+	       		__get_user_x(__r2, __p, __e, 4, "lr");		\
 			break;						\
 		case 8:							\
-			__get_user_x(__r1, __p, __e, 8, "lr");		\
+			__get_user_x(__r2, __p, __e, 8, "lr");		\
 	       		break;						\
 		default: __e = __get_user_bad(); break;			\
 		}							\
-		x = __r1;						\
+		x = __r2;						\
 		__e;							\
 	})
 
@@ -227,31 +227,31 @@ extern int __put_user_4(void *, unsigned int);
 extern int __put_user_8(void *, unsigned long long);
 extern int __put_user_bad(void);
 
-#define __put_user_x(__r1,__p,__e,__s)					\
+#define __put_user_x(__r2,__p,__e,__s)					\
 	   __asm__ __volatile__ (					\
-		__asmeq("%0", "r0") __asmeq("%2", "r1")			\
+		__asmeq("%0", "r0") __asmeq("%2", "r2")			\
 		"bl	__put_user_" #__s				\
 		: "=&r" (__e)						\
-		: "0" (__p), "r" (__r1)					\
+		: "0" (__p), "r" (__r2)					\
 		: "ip", "lr", "cc")
 
 #define put_user(x,p)							\
 	({								\
-		const register typeof(*(p)) __r1 asm("r1") = (x);	\
+		const register typeof(*(p)) __r2 asm("r2") = (x);	\
 		const register typeof(*(p)) __user *__p asm("r0") = (p);\
 		register int __e asm("r0");				\
 		switch (sizeof(*(__p))) {				\
 		case 1:							\
-			__put_user_x(__r1, __p, __e, 1);		\
+			__put_user_x(__r2, __p, __e, 1);		\
 			break;						\
 		case 2:							\
-			__put_user_x(__r1, __p, __e, 2);		\
+			__put_user_x(__r2, __p, __e, 2);		\
 			break;						\
 		case 4:							\
-			__put_user_x(__r1, __p, __e, 4);		\
+			__put_user_x(__r2, __p, __e, 4);		\
 			break;						\
 		case 8:							\
-			__put_user_x(__r1, __p, __e, 8);		\
+			__put_user_x(__r2, __p, __e, 8);		\
 			break;						\
 		default: __e = __put_user_bad(); break;			\
 		}							\
diff --git a/include/asm-i386/acpi.h b/include/asm-i386/acpi.h
index 60f2942f4588..9e5d4c8a21fa 100644
--- a/include/asm-i386/acpi.h
+++ b/include/asm-i386/acpi.h
@@ -162,8 +162,6 @@ static inline void check_acpi_pci(void) { }
 
 #endif
 
-extern int (*platform_rename_gsi)(int ioapic, int gsi);
-
 #ifdef CONFIG_ACPI_PCI
 static inline void acpi_noirq_set(void) { acpi_noirq = 1; }
 static inline void acpi_disable_pci(void) 
diff --git a/include/asm-i386/apic.h b/include/asm-i386/apic.h
index ed794d04c118..e1de67483f38 100644
--- a/include/asm-i386/apic.h
+++ b/include/asm-i386/apic.h
@@ -89,6 +89,7 @@ extern void clear_local_APIC(void);
 extern void connect_bsp_APIC (void);
 extern void disconnect_bsp_APIC (void);
 extern void disable_local_APIC (void);
+extern void lapic_shutdown (void);
 extern int verify_local_APIC (void);
 extern void cache_APIC_registers (void);
 extern void sync_Arb_IDs (void);
@@ -117,6 +118,9 @@ extern unsigned int nmi_watchdog;
 #define NMI_LOCAL_APIC	2
 #define NMI_INVALID	3
 
-#endif /* CONFIG_X86_LOCAL_APIC */
+#else /* !CONFIG_X86_LOCAL_APIC */
+static inline void lapic_shutdown(void) { }
+
+#endif /* !CONFIG_X86_LOCAL_APIC */
 
 #endif /* __ASM_APIC_H */
diff --git a/include/asm-i386/io_apic.h b/include/asm-i386/io_apic.h
index 1a9ba4fd0532..002c203ccd6a 100644
--- a/include/asm-i386/io_apic.h
+++ b/include/asm-i386/io_apic.h
@@ -202,6 +202,8 @@ extern int io_apic_get_redir_entries (int ioapic);
 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
 #endif /*CONFIG_ACPI_BOOT*/
 
+extern int (*ioapic_renumber_irq)(int ioapic, int irq);
+
 #else  /* !CONFIG_X86_IO_APIC */
 #define io_apic_assign_pci_irqs 0
 #endif
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 8e816364aec1..f3eda9d9b74f 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -38,16 +38,6 @@
 #endif
 
 /*
- * Memory segments (32bit kernel mode addresses)
- * These are the traditional names used in the 32-bit universe.
- */
-#define KUSEG			0x00000000
-#define KSEG0			0x80000000
-#define KSEG1			0xa0000000
-#define KSEG2			0xc0000000
-#define KSEG3			0xe0000000
-
-/*
  * Returns the kernel segment base of a given address
  */
 #define KSEGX(a)		((_ACAST32_ (a)) & 0xe0000000)
@@ -58,18 +48,7 @@
 #define CPHYSADDR(a)		((_ACAST32_ (a)) & 0x1fffffff)
 #define XPHYSADDR(a)            ((_ACAST64_ (a)) & 0x000000ffffffffff)
 
-/*
- * Map an address to a certain kernel segment
- */
-#define KSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
-#define KSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
-#define KSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2)
-#define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
-
-#define CKSEG0ADDR(a)		(CPHYSADDR(a) | CKSEG0)
-#define CKSEG1ADDR(a)		(CPHYSADDR(a) | CKSEG1)
-#define CKSEG2ADDR(a)		(CPHYSADDR(a) | CKSEG2)
-#define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
+#ifdef CONFIG_MIPS64
 
 /*
  * Memory segments (64bit kernel mode addresses)
@@ -85,6 +64,44 @@
 #define CKSSEG			0xffffffffc0000000
 #define CKSEG3			0xffffffffe0000000
 
+#define CKSEG0ADDR(a)		(CPHYSADDR(a) | CKSEG0)
+#define CKSEG1ADDR(a)		(CPHYSADDR(a) | CKSEG1)
+#define CKSEG2ADDR(a)		(CPHYSADDR(a) | CKSEG2)
+#define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
+
+#else
+
+#define CKSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
+#define CKSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
+#define CKSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2)
+#define CKSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
+
+/*
+ * Map an address to a certain kernel segment
+ */
+#define KSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
+#define KSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1)
+#define KSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2)
+#define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3)
+
+/*
+ * Memory segments (32bit kernel mode addresses)
+ * These are the traditional names used in the 32-bit universe.
+ */
+#define KUSEG			0x00000000
+#define KSEG0			0x80000000
+#define KSEG1			0xa0000000
+#define KSEG2			0xc0000000
+#define KSEG3			0xe0000000
+
+#define CKUSEG			0x00000000
+#define CKSEG0			0x80000000
+#define CKSEG1			0xa0000000
+#define CKSEG2			0xc0000000
+#define CKSEG3			0xe0000000
+
+#endif
+
 /*
  * Cache modes for XKPHYS address conversion macros
  */
diff --git a/include/asm-mips/asmmacro-32.h b/include/asm-mips/asmmacro-32.h
index 1d927d07cf14..ac8823df2554 100644
--- a/include/asm-mips/asmmacro-32.h
+++ b/include/asm-mips/asmmacro-32.h
@@ -12,8 +12,8 @@
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 
-	.macro	fpu_save_double thread tmp=t0
-	cfc1	\tmp,  fcr31
+	.macro	fpu_save_double thread status tmp1=t0 tmp2
+	cfc1	\tmp1,  fcr31
 	sdc1	$f0,  THREAD_FPR0(\thread)
 	sdc1	$f2,  THREAD_FPR2(\thread)
 	sdc1	$f4,  THREAD_FPR4(\thread)
@@ -30,7 +30,7 @@
 	sdc1	$f26, THREAD_FPR26(\thread)
 	sdc1	$f28, THREAD_FPR28(\thread)
 	sdc1	$f30, THREAD_FPR30(\thread)
-	sw	\tmp, THREAD_FCR31(\thread)
+	sw	\tmp1, THREAD_FCR31(\thread)
 	.endm
 
 	.macro	fpu_save_single thread tmp=t0
diff --git a/include/asm-mips/asmmacro-64.h b/include/asm-mips/asmmacro-64.h
index 10b71cc877bc..bbed35511f5a 100644
--- a/include/asm-mips/asmmacro-64.h
+++ b/include/asm-mips/asmmacro-64.h
@@ -15,6 +15,7 @@
 
 	.macro	fpu_save_16even thread tmp=t0
 	cfc1	\tmp, fcr31
+	sdc1	$f0,  THREAD_FPR0(\thread)
 	sdc1	$f2,  THREAD_FPR2(\thread)
 	sdc1	$f4,  THREAD_FPR4(\thread)
 	sdc1	$f6,  THREAD_FPR6(\thread)
@@ -52,6 +53,14 @@
 	sdc1	$f31, THREAD_FPR31(\thread)
 	.endm
 
+	.macro	fpu_save_double thread status tmp1 tmp2
+	sll	\tmp2, \tmp1, 5
+	bgez	\tmp2, 2f
+	fpu_save_16odd \thread
+2:
+	fpu_save_16even \thread \tmp1			# clobbers t1
+	.endm
+
 	.macro	fpu_restore_16even thread tmp=t0
 	lw	\tmp, THREAD_FCR31(\thread)
 	ldc1	$f0,  THREAD_FPR0(\thread)
@@ -92,6 +101,15 @@
 	ldc1	$f31, THREAD_FPR31(\thread)
 	.endm
 
+	.macro	fpu_restore_double thread tmp
+	mfc0	t0, CP0_STATUS
+	sll	t1, t0, 5
+	bgez	t1, 1f				# 16 register mode?
+
+	fpu_restore_16odd a0
+1:	fpu_restore_16even a0, t0		# clobbers t0
+	.endm
+
 	.macro	cpu_save_nonscratch thread
 	LONG_S	s0, THREAD_REG16(\thread)
 	LONG_S	s1, THREAD_REG17(\thread)
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index c8c6a5a8c5aa..7d89e87bc8c6 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -23,6 +23,9 @@
 #ifndef _ASM_ATOMIC_H
 #define _ASM_ATOMIC_H
 
+#include <asm/cpu-features.h>
+#include <asm/war.h>
+
 extern spinlock_t atomic_lock;
 
 typedef struct { volatile int counter; } atomic_t;
@@ -46,8 +49,6 @@ typedef struct { volatile int counter; } atomic_t;
  */
 #define atomic_set(v,i)		((v)->counter = (i))
 
-#ifdef CONFIG_CPU_HAS_LLSC
-
 /*
  * atomic_add - add integer to atomic variable
  * @i: integer value to add
@@ -57,15 +58,33 @@ typedef struct { volatile int counter; } atomic_t;
  */
 static __inline__ void atomic_add(int i, atomic_t * v)
 {
-	unsigned long temp;
-
-	__asm__ __volatile__(
-	"1:	ll	%0, %1		# atomic_add		\n"
-	"	addu	%0, %2					\n"
-	"	sc	%0, %1					\n"
-	"	beqz	%0, 1b					\n"
-	: "=&r" (temp), "=m" (v->counter)
-	: "Ir" (i), "m" (v->counter));
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	ll	%0, %1		# atomic_add		\n"
+		"	addu	%0, %2					\n"
+		"	sc	%0, %1					\n"
+		"	beqzl	%0, 1b					\n"
+		: "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter));
+	} else if (cpu_has_llsc) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	ll	%0, %1		# atomic_add		\n"
+		"	addu	%0, %2					\n"
+		"	sc	%0, %1					\n"
+		"	beqz	%0, 1b					\n"
+		: "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter));
+	} else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&atomic_lock, flags);
+		v->counter += i;
+		spin_unlock_irqrestore(&atomic_lock, flags);
+	}
 }
 
 /*
@@ -77,15 +96,33 @@ static __inline__ void atomic_add(int i, atomic_t * v)
  */
 static __inline__ void atomic_sub(int i, atomic_t * v)
 {
-	unsigned long temp;
-
-	__asm__ __volatile__(
-	"1:	ll	%0, %1		# atomic_sub		\n"
-	"	subu	%0, %2					\n"
-	"	sc	%0, %1					\n"
-	"	beqz	%0, 1b					\n"
-	: "=&r" (temp), "=m" (v->counter)
-	: "Ir" (i), "m" (v->counter));
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	ll	%0, %1		# atomic_sub		\n"
+		"	subu	%0, %2					\n"
+		"	sc	%0, %1					\n"
+		"	beqzl	%0, 1b					\n"
+		: "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter));
+	} else if (cpu_has_llsc) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	ll	%0, %1		# atomic_sub		\n"
+		"	subu	%0, %2					\n"
+		"	sc	%0, %1					\n"
+		"	beqz	%0, 1b					\n"
+		: "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter));
+	} else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&atomic_lock, flags);
+		v->counter -= i;
+		spin_unlock_irqrestore(&atomic_lock, flags);
+	}
 }
 
 /*
@@ -93,36 +130,86 @@ static __inline__ void atomic_sub(int i, atomic_t * v)
  */
 static __inline__ int atomic_add_return(int i, atomic_t * v)
 {
-	unsigned long temp, result;
-
-	__asm__ __volatile__(
-	"1:	ll	%1, %2		# atomic_add_return	\n"
-	"	addu	%0, %1, %3				\n"
-	"	sc	%0, %2					\n"
-	"	beqz	%0, 1b					\n"
-	"	addu	%0, %1, %3				\n"
-	"	sync						\n"
-	: "=&r" (result), "=&r" (temp), "=m" (v->counter)
-	: "Ir" (i), "m" (v->counter)
-	: "memory");
+	unsigned long result;
+
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	ll	%1, %2		# atomic_add_return	\n"
+		"	addu	%0, %1, %3				\n"
+		"	sc	%0, %2					\n"
+		"	beqzl	%0, 1b					\n"
+		"	addu	%0, %1, %3				\n"
+		"	sync						\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else if (cpu_has_llsc) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	ll	%1, %2		# atomic_add_return	\n"
+		"	addu	%0, %1, %3				\n"
+		"	sc	%0, %2					\n"
+		"	beqz	%0, 1b					\n"
+		"	addu	%0, %1, %3				\n"
+		"	sync						\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&atomic_lock, flags);
+		result = v->counter;
+		result += i;
+		v->counter = result;
+		spin_unlock_irqrestore(&atomic_lock, flags);
+	}
 
 	return result;
 }
 
 static __inline__ int atomic_sub_return(int i, atomic_t * v)
 {
-	unsigned long temp, result;
-
-	__asm__ __volatile__(
-	"1:	ll	%1, %2		# atomic_sub_return	\n"
-	"	subu	%0, %1, %3				\n"
-	"	sc	%0, %2					\n"
-	"	beqz	%0, 1b					\n"
-	"	subu	%0, %1, %3				\n"
-	"	sync						\n"
-	: "=&r" (result), "=&r" (temp), "=m" (v->counter)
-	: "Ir" (i), "m" (v->counter)
-	: "memory");
+	unsigned long result;
+
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	ll	%1, %2		# atomic_sub_return	\n"
+		"	subu	%0, %1, %3				\n"
+		"	sc	%0, %2					\n"
+		"	beqzl	%0, 1b					\n"
+		"	subu	%0, %1, %3				\n"
+		"	sync						\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else if (cpu_has_llsc) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	ll	%1, %2		# atomic_sub_return	\n"
+		"	subu	%0, %1, %3				\n"
+		"	sc	%0, %2					\n"
+		"	beqz	%0, 1b					\n"
+		"	subu	%0, %1, %3				\n"
+		"	sync						\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&atomic_lock, flags);
+		result = v->counter;
+		result -= i;
+		v->counter = result;
+		spin_unlock_irqrestore(&atomic_lock, flags);
+	}
 
 	return result;
 }
@@ -136,112 +223,50 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
  */
 static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
 {
-	unsigned long temp, result;
-
-	__asm__ __volatile__(
-	"1:	ll	%1, %2		# atomic_sub_if_positive\n"
-	"	subu	%0, %1, %3				\n"
-	"	bltz	%0, 1f					\n"
-	"	sc	%0, %2					\n"
-	"	beqz	%0, 1b					\n"
-	"	sync						\n"
-	"1:							\n"
-	: "=&r" (result), "=&r" (temp), "=m" (v->counter)
-	: "Ir" (i), "m" (v->counter)
-	: "memory");
+	unsigned long result;
+
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	ll	%1, %2		# atomic_sub_if_positive\n"
+		"	subu	%0, %1, %3				\n"
+		"	bltz	%0, 1f					\n"
+		"	sc	%0, %2					\n"
+		"	beqzl	%0, 1b					\n"
+		"	sync						\n"
+		"1:							\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else if (cpu_has_llsc) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	ll	%1, %2		# atomic_sub_if_positive\n"
+		"	subu	%0, %1, %3				\n"
+		"	bltz	%0, 1f					\n"
+		"	sc	%0, %2					\n"
+		"	beqz	%0, 1b					\n"
+		"	sync						\n"
+		"1:							\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&atomic_lock, flags);
+		result = v->counter;
+		result -= i;
+		if (result >= 0)
+			v->counter = result;
+		spin_unlock_irqrestore(&atomic_lock, flags);
+	}
 
 	return result;
 }
 
-#else
-
-/*
- * The MIPS I implementation is only atomic with respect to
- * interrupts.  R3000 based multiprocessor machines are rare anyway ...
- *
- * atomic_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v.
- */
-static __inline__ void atomic_add(int i, atomic_t * v)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&atomic_lock, flags);
-	v->counter += i;
-	spin_unlock_irqrestore(&atomic_lock, flags);
-}
-
-/*
- * atomic_sub - subtract the atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v.
- */
-static __inline__ void atomic_sub(int i, atomic_t * v)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&atomic_lock, flags);
-	v->counter -= i;
-	spin_unlock_irqrestore(&atomic_lock, flags);
-}
-
-static __inline__ int atomic_add_return(int i, atomic_t * v)
-{
-	unsigned long flags;
-	int temp;
-
-	spin_lock_irqsave(&atomic_lock, flags);
-	temp = v->counter;
-	temp += i;
-	v->counter = temp;
-	spin_unlock_irqrestore(&atomic_lock, flags);
-
-	return temp;
-}
-
-static __inline__ int atomic_sub_return(int i, atomic_t * v)
-{
-	unsigned long flags;
-	int temp;
-
-	spin_lock_irqsave(&atomic_lock, flags);
-	temp = v->counter;
-	temp -= i;
-	v->counter = temp;
-	spin_unlock_irqrestore(&atomic_lock, flags);
-
-	return temp;
-}
-
-/*
- * atomic_sub_if_positive - add integer to atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically test @v and decrement if it is greater than 0.
- * The function returns the old value of @v minus 1.
- */
-static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
-{
-	unsigned long flags;
-	int temp;
-
-	spin_lock_irqsave(&atomic_lock, flags);
-	temp = v->counter;
-	temp -= i;
-	if (temp >= 0)
-		v->counter = temp;
-	spin_unlock_irqrestore(&atomic_lock, flags);
-
-	return temp;
-}
-
-#endif /* CONFIG_CPU_HAS_LLSC */
-
 #define atomic_dec_return(v) atomic_sub_return(1,(v))
 #define atomic_inc_return(v) atomic_add_return(1,(v))
 
@@ -329,8 +354,6 @@ typedef struct { volatile __s64 counter; } atomic64_t;
  */
 #define atomic64_set(v,i)	((v)->counter = (i))
 
-#ifdef CONFIG_CPU_HAS_LLDSCD
-
 /*
  * atomic64_add - add integer to atomic variable
  * @i: integer value to add
@@ -340,15 +363,33 @@ typedef struct { volatile __s64 counter; } atomic64_t;
  */
 static __inline__ void atomic64_add(long i, atomic64_t * v)
 {
-	unsigned long temp;
-
-	__asm__ __volatile__(
-	"1:	lld	%0, %1		# atomic64_add		\n"
-	"	addu	%0, %2					\n"
-	"	scd	%0, %1					\n"
-	"	beqz	%0, 1b					\n"
-	: "=&r" (temp), "=m" (v->counter)
-	: "Ir" (i), "m" (v->counter));
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	lld	%0, %1		# atomic64_add		\n"
+		"	addu	%0, %2					\n"
+		"	scd	%0, %1					\n"
+		"	beqzl	%0, 1b					\n"
+		: "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter));
+	} else if (cpu_has_llsc) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	lld	%0, %1		# atomic64_add		\n"
+		"	addu	%0, %2					\n"
+		"	scd	%0, %1					\n"
+		"	beqz	%0, 1b					\n"
+		: "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter));
+	} else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&atomic_lock, flags);
+		v->counter += i;
+		spin_unlock_irqrestore(&atomic_lock, flags);
+	}
 }
 
 /*
@@ -360,15 +401,33 @@ static __inline__ void atomic64_add(long i, atomic64_t * v)
  */
 static __inline__ void atomic64_sub(long i, atomic64_t * v)
 {
-	unsigned long temp;
-
-	__asm__ __volatile__(
-	"1:	lld	%0, %1		# atomic64_sub		\n"
-	"	subu	%0, %2					\n"
-	"	scd	%0, %1					\n"
-	"	beqz	%0, 1b					\n"
-	: "=&r" (temp), "=m" (v->counter)
-	: "Ir" (i), "m" (v->counter));
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	lld	%0, %1		# atomic64_sub		\n"
+		"	subu	%0, %2					\n"
+		"	scd	%0, %1					\n"
+		"	beqzl	%0, 1b					\n"
+		: "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter));
+	} else if (cpu_has_llsc) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	lld	%0, %1		# atomic64_sub		\n"
+		"	subu	%0, %2					\n"
+		"	scd	%0, %1					\n"
+		"	beqz	%0, 1b					\n"
+		: "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter));
+	} else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&atomic_lock, flags);
+		v->counter -= i;
+		spin_unlock_irqrestore(&atomic_lock, flags);
+	}
 }
 
 /*
@@ -376,36 +435,86 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v)
  */
 static __inline__ long atomic64_add_return(long i, atomic64_t * v)
 {
-	unsigned long temp, result;
-
-	__asm__ __volatile__(
-	"1:	lld	%1, %2		# atomic64_add_return	\n"
-	"	addu	%0, %1, %3				\n"
-	"	scd	%0, %2					\n"
-	"	beqz	%0, 1b					\n"
-	"	addu	%0, %1, %3				\n"
-	"	sync						\n"
-	: "=&r" (result), "=&r" (temp), "=m" (v->counter)
-	: "Ir" (i), "m" (v->counter)
-	: "memory");
+	unsigned long result;
+
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	lld	%1, %2		# atomic64_add_return	\n"
+		"	addu	%0, %1, %3				\n"
+		"	scd	%0, %2					\n"
+		"	beqzl	%0, 1b					\n"
+		"	addu	%0, %1, %3				\n"
+		"	sync						\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else if (cpu_has_llsc) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	lld	%1, %2		# atomic64_add_return	\n"
+		"	addu	%0, %1, %3				\n"
+		"	scd	%0, %2					\n"
+		"	beqz	%0, 1b					\n"
+		"	addu	%0, %1, %3				\n"
+		"	sync						\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&atomic_lock, flags);
+		result = v->counter;
+		result += i;
+		v->counter = result;
+		spin_unlock_irqrestore(&atomic_lock, flags);
+	}
 
 	return result;
 }
 
 static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
 {
-	unsigned long temp, result;
-
-	__asm__ __volatile__(
-	"1:	lld	%1, %2		# atomic64_sub_return	\n"
-	"	subu	%0, %1, %3				\n"
-	"	scd	%0, %2					\n"
-	"	beqz	%0, 1b					\n"
-	"	subu	%0, %1, %3				\n"
-	"	sync						\n"
-	: "=&r" (result), "=&r" (temp), "=m" (v->counter)
-	: "Ir" (i), "m" (v->counter)
-	: "memory");
+	unsigned long result;
+
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	lld	%1, %2		# atomic64_sub_return	\n"
+		"	subu	%0, %1, %3				\n"
+		"	scd	%0, %2					\n"
+		"	beqzl	%0, 1b					\n"
+		"	subu	%0, %1, %3				\n"
+		"	sync						\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else if (cpu_has_llsc) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	lld	%1, %2		# atomic64_sub_return	\n"
+		"	subu	%0, %1, %3				\n"
+		"	scd	%0, %2					\n"
+		"	beqz	%0, 1b					\n"
+		"	subu	%0, %1, %3				\n"
+		"	sync						\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&atomic_lock, flags);
+		result = v->counter;
+		result -= i;
+		v->counter = result;
+		spin_unlock_irqrestore(&atomic_lock, flags);
+	}
 
 	return result;
 }
@@ -419,112 +528,50 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
  */
 static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
 {
-	unsigned long temp, result;
-
-	__asm__ __volatile__(
-	"1:	lld	%1, %2		# atomic64_sub_if_positive\n"
-	"	dsubu	%0, %1, %3				\n"
-	"	bltz	%0, 1f					\n"
-	"	scd	%0, %2					\n"
-	"	beqz	%0, 1b					\n"
-	"	sync						\n"
-	"1:							\n"
-	: "=&r" (result), "=&r" (temp), "=m" (v->counter)
-	: "Ir" (i), "m" (v->counter)
-	: "memory");
+	unsigned long result;
+
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	lld	%1, %2		# atomic64_sub_if_positive\n"
+		"	dsubu	%0, %1, %3				\n"
+		"	bltz	%0, 1f					\n"
+		"	scd	%0, %2					\n"
+		"	beqzl	%0, 1b					\n"
+		"	sync						\n"
+		"1:							\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else if (cpu_has_llsc) {
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	lld	%1, %2		# atomic64_sub_if_positive\n"
+		"	dsubu	%0, %1, %3				\n"
+		"	bltz	%0, 1f					\n"
+		"	scd	%0, %2					\n"
+		"	beqz	%0, 1b					\n"
+		"	sync						\n"
+		"1:							\n"
+		: "=&r" (result), "=&r" (temp), "=m" (v->counter)
+		: "Ir" (i), "m" (v->counter)
+		: "memory");
+	} else {
+		unsigned long flags;
+
+		spin_lock_irqsave(&atomic_lock, flags);
+		result = v->counter;
+		result -= i;
+		if (result >= 0)
+			v->counter = result;
+		spin_unlock_irqrestore(&atomic_lock, flags);
+	}
 
 	return result;
 }
 
-#else
-
-/*
- * This implementation is only atomic with respect to interrupts.  It can't
- * be used on SMP
- *
- * atomic64_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic64_t
- *
- * Atomically adds @i to @v.
- */
-static __inline__ void atomic64_add(long i, atomic64_t * v)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&atomic_lock, flags);
-	v->counter += i;
-	spin_unlock_irqrestore(&atomic_lock, flags);
-}
-
-/*
- * atomic64_sub - subtract the atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic64_t
- *
- * Atomically subtracts @i from @v.
- */
-static __inline__ void atomic64_sub(long i, atomic64_t * v)
-{
-	unsigned long flags;
-
-	spin_lock_irqsave(&atomic_lock, flags);
-	v->counter -= i;
-	spin_unlock_irqrestore(&atomic_lock, flags);
-}
-
-static __inline__ long atomic64_add_return(long i, atomic64_t * v)
-{
-	unsigned long flags;
-	long temp;
-
-	spin_lock_irqsave(&atomic_lock, flags);
-	temp = v->counter;
-	temp += i;
-	v->counter = temp;
-	spin_unlock_irqrestore(&atomic_lock, flags);
-
-	return temp;
-}
-
-static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
-{
-	unsigned long flags;
-	long temp;
-
-	spin_lock_irqsave(&atomic_lock, flags);
-	temp = v->counter;
-	temp -= i;
-	v->counter = temp;
-	spin_unlock_irqrestore(&atomic_lock, flags);
-
-	return temp;
-}
-
-/*
- * atomic64_sub_if_positive - add integer to atomic variable
- * @v: pointer of type atomic64_t
- *
- * Atomically test @v and decrement if it is greater than 0.
- * The function returns the old value of @v minus 1.
- */
-static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
-{
-	unsigned long flags;
-	long temp;
-
-	spin_lock_irqsave(&atomic_lock, flags);
-	temp = v->counter;
-	temp -= i;
-	if (temp >= 0)
-		v->counter = temp;
-	spin_unlock_irqrestore(&atomic_lock, flags);
-
-	return temp;
-}
-
-#endif /* CONFIG_CPU_HAS_LLDSCD */
-
 #define atomic64_dec_return(v) atomic64_sub_return(1,(v))
 #define atomic64_inc_return(v) atomic64_add_return(1,(v))
 
diff --git a/include/asm-mips/baget/baget.h b/include/asm-mips/baget/baget.h
deleted file mode 100644
index d3f0256f7616..000000000000
--- a/include/asm-mips/baget/baget.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * baget.h: Definitions specific to Baget/MIPS machines.
- *
- * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
- */
-#ifndef _MIPS_BAGET_H
-#define _MIPS_BAGET_H
-
-#include "vic.h"
-#include "vac.h"
-
-#define VIC_BASE         0xBFFC0000
-#define VAC_BASE         0xBFFD0000
-
-
-/* Baget interrupt registers and their sizes */
-
-struct  baget_int_reg {
-	unsigned long address;
-	int size;  /* in bytes */
-};
-#define BAGET_INT_NONE   {0,0}
-
-#define BAGET_INT0_ACK   {0xbffa0003,1}
-#define BAGET_INT1_ACK   {0xbffa0008,4}
-#define BAGET_INT5_ACK   {0xbff00000,1}
-
-#define BAGET_WRERR_ACK  ((volatile char*)0xbff00000)
-
-
-/* Baget address spaces */
-
-#define BAGET_A24M_BASE       0xFC000000      /* VME-master A24 base address  */
-#define BAGET_A24S_BASE       0x00000000      /* VME-slave A24 base address   */
-#define BAGET_A24S_MASK       0x00c00000      /* VME-slave A24 address mask   */
-#define BAGET_GSW_BASE        0xf000          /* global switches address base */
-#define BAGET_MSW_BASE(P) (0xe000+(P)*0x100)  /* module switches address base */
-
-#define BAGET_LED_BASE  ((volatile short *)(0xbffd0000 + 0x00001800))
-
-#define BAGET_PIL_NR            8
-#define BAGET_IRQ_NR            NR_IRQS /* 64 */
-#define BAGET_IRQ_MASK(x)       ((NR_IRQS-1) & (x))
-
-#define BAGET_FPU_IRQ           0x26
-#define BAGET_VIC_TIMER_IRQ     0x32
-#define BAGET_VAC_TIMER_IRQ     0x36
-#define BAGET_BSM_IRQ           0x3C
-
-#define BAGET_LANCE_MEM_BASE    0xfcf10000
-#define BAGET_LANCE_MEM_SIZE    0x10000
-#define BAGET_LANCE_IO_BASE     0xbffeff00
-
-#define BALO_OFFSET     0x400000 /* sync with ld.script.balo  */
-#define BALO_SIZE       0x200000 /* sync with image segs size */
-
-/* move it to the right place, somehere in include/asm */
-#define CAUSE_DBE       0x1C
-#define CAUSE_MASK      0x7C
-
-/* Simple debug fascilities */
-extern void outc(char);
-extern void outs(char *);
-extern void baget_write(char *s, int l);
-extern int  baget_printk(const char *, ...);
-extern void balo_printf( char *f, ... );
-extern void balo_hungup(void);
-
-#endif /* !(_MIPS_BAGET_H) */
diff --git a/include/asm-mips/baget/vac.h b/include/asm-mips/baget/vac.h
deleted file mode 100644
index 5ca62dc540d1..000000000000
--- a/include/asm-mips/baget/vac.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * vac.h: Various VIC controller defines.  The VIC is a VME controller
- *        used in Baget/MIPS series.
- *
- * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
- */
-#ifndef _ASM_VAC_H
-#define _ASM_VAC_H
-
-#define VAC_SLSEL1_MASK      0x000
-#define VAC_SLSEL1_BASE      0x100
-#define VAC_SLSEL0_MASK      0x200
-#define VAC_SLSEL0_BASE      0x300
-#define VAC_ICFSEL_BASE      0x400
-#define VAC_ICFSEL_GLOBAL_VAL(x) (((x)>>8)&0xff)
-#define VAC_ICFSEL_MODULE_VAL(x) ((x)&0xff)
-#define VAC_DRAM_MASK        0x500
-#define VAC_BNDR2            0x600
-#define VAC_BNDR3            0x700
-#define VAC_A24_BASE         0x800
-#define    VAC_A24_MASK          (0x3f<<9)
-#define    VAC_A24_D32_ENABLE    (1<<8)
-#define    VAC_A24_A24_CACHINH   (1<<7)
-#define    VAC_A24_A16D32_ENABLE (1<<6)
-#define    VAC_A24_A16D32        (1<<5)
-#define    VAC_A24_DATAPATH      (1<<4)
-#define    VAC_A24_IO_CACHINH    (1<<3)
-#define VAC_REG1             0x900
-#define VAC_REG2             0xA00
-#define VAC_REG3             0xB00
-#define    VAC_REG_WORD      (1<<15)
-#define    VAC_REG_ASIZ1     (1<<14)
-#define    VAC_REG_ASIZ0     (1<<13)
-#define    VAC_REG_ASIZ_VAL(x) (((x)>>13)&3)
-#define    VAC_REG_CACHINH   (1<<12)
-#define    VAC_REG_INACTIVE  (0<<10)
-#define    VAC_REG_SHARED    (1<<10)
-#define    VAC_REG_VSB       (2<<10)
-#define    VAC_REG_MWB       (3<<10)
-#define    VAC_REG_MASK      (3<<10)
-#define    VAC_REG_MODE(x)   (((x)>>10)&3)
-#define VAC_IOSEL4_CTRL      0xC00
-#define VAC_IOSEL5_CTRL      0xD00
-#define VAC_SHRCS_CTRL       0xE00
-#define VAC_EPROMCS_CTRL     0xF00
-#define VAC_IOSEL0_CTRL      0x1000
-#define VAC_IOSEL1_CTRL      0x1100
-#define VAC_IOSEL2_CTRL      0x1200
-#define VAC_IOSEL3_CTRL      0x1300
-#define    VAC_CTRL_IOWR               (1<<0)
-#define    VAC_CTRL_IORD               (1<<1)
-#define    VAC_CTRL_DELAY_IOSELI(x)    (((x)&3)<<2)
-#define    VAC_CTRL_DELAY_IOSELI_VAL(x) (((x)>>2)&3)
-#define    VAC_CTRL_DELAY_IOWR(x)      (((x)&3)<<4)
-#define    VAC_CTRL_DELAY_IOWR_VAL(x)  (((x)>>4)&3)
-#define    VAC_CTRL_DELAY_IORD(x)      (((x)&3)<<6)
-#define    VAC_CTRL_DELAY_IORD_VAL(x)  (((x)>>6)&3)
-#define    VAC_CTRL_RECOVERY_IOSELI(x) ((((x)-1)&7)<<8)
-#define    VAC_CTRL_RECOVERY_IOSELI_VAL(x) ((((x)>>8)&7)+1)
-#define    VAC_CTRL_DSACK0             (1<<11)
-#define    VAC_CTRL_DSACK1             (1<<12)
-#define    VAC_CTRL_DELAY_DSACKI(x)    ((((x)-1)&7)<<13)
-#define    VAC_CTRL_DELAY_DSACKI_VAL(x) ((((x)>>13)&7)+1)
-#define VAC_DECODE_CTRL      0x1400
-#define    VAC_DECODE_FPUCS   (1<<0)
-#define    VAC_DECODE_CPUCLK(x)  (((x)&3)<<1)
-#define    VAC_DECODE_CPUCLK_VAL(x) (((x)>>1)&3)
-#define    VAC_DECODE_RDR_SLSEL0 (1<<3)
-#define    VAC_DECODE_RDR_SLSEL1 (1<<4)
-#define    VAC_DECODE_DSACK   (1<<5)
-#define    VAC_DECODE_QFY_BNDR    (1<<6)
-#define    VAC_DECODE_QFY_ICFSEL  (1<<7)
-#define    VAC_DECODE_QFY_SLSEL1  (1<<8)
-#define    VAC_DECODE_QFY_SLSEL0  (1<<9)
-#define    VAC_DECODE_CMP_SLSEL1_LO  (1<<10)
-#define    VAC_DECODE_CMP_SLSEL1_HI  (1<<11)
-#define    VAC_DECODE_CMP_SLSEL1_VAL(x) (((x)>>10)&3)
-#define    VAC_DECODE_DRAMCS  (3<<12)
-#define    VAC_DECODE_SHRCS   (2<<12)
-#define    VAC_DECODE_VSBSEL  (1<<12)
-#define    VAC_DECODE_EPROMCS (0<<12)
-#define    VAC_DECODE_MODE_VAL(x) (((x)>>12)&3)
-#define    VAC_DECODE_QFY_DRAMCS  (1<<14)
-#define    VAC_DECODE_DSACKI  (1<<15)
-#define VAC_INT_STATUS       0x1500
-#define VAC_INT_CTRL         0x1600
-#define    VAC_INT_CTRL_TIMER_PIO11    (3<<0)
-#define    VAC_INT_CTRL_TIMER_PIO10    (2<<0)
-#define    VAC_INT_CTRL_TIMER_PIO7     (1<<0)
-#define    VAC_INT_CTRL_TIMER_DISABLE  (0<<0)
-#define    VAC_INT_CTRL_TIMER_MASK     (3<<0)
-#define    VAC_INT_CTRL_UART_B_PIO11   (3<<2)
-#define    VAC_INT_CTRL_UART_B_PIO10   (2<<2)
-#define    VAC_INT_CTRL_UART_B_PIO7    (1<<2)
-#define    VAC_INT_CTRL_UART_B_DISABLE (0<<2)
-#define    VAC_INT_CTRL_UART_A_PIO11   (3<<4)
-#define    VAC_INT_CTRL_UART_A_PIO10   (2<<4)
-#define    VAC_INT_CTRL_UART_A_PIO7    (1<<4)
-#define    VAC_INT_CTRL_UART_A_DISABLE (0<<4)
-#define    VAC_INT_CTRL_MBOX_PIO11     (3<<6)
-#define    VAC_INT_CTRL_MBOX_PIO10     (2<<6)
-#define    VAC_INT_CTRL_MBOX_PIO7      (1<<6)
-#define    VAC_INT_CTRL_MBOX_DISABLE   (0<<6)
-#define    VAC_INT_CTRL_PIO4_PIO11     (3<<8)
-#define    VAC_INT_CTRL_PIO4_PIO10     (2<<8)
-#define    VAC_INT_CTRL_PIO4_PIO7      (1<<8)
-#define    VAC_INT_CTRL_PIO4_DISABLE   (0<<8)
-#define    VAC_INT_CTRL_PIO7_PIO11     (3<<10)
-#define    VAC_INT_CTRL_PIO7_PIO10     (2<<10)
-#define    VAC_INT_CTRL_PIO7_PIO7      (1<<10)
-#define    VAC_INT_CTRL_PIO7_DISABLE   (0<<10)
-#define    VAC_INT_CTRL_PIO8_PIO11     (3<<12)
-#define    VAC_INT_CTRL_PIO8_PIO10     (2<<12)
-#define    VAC_INT_CTRL_PIO8_PIO7      (1<<12)
-#define    VAC_INT_CTRL_PIO8_DISABLE   (0<<12)
-#define    VAC_INT_CTRL_PIO9_PIO11     (3<<14)
-#define    VAC_INT_CTRL_PIO9_PIO10     (2<<14)
-#define    VAC_INT_CTRL_PIO9_PIO7      (1<<14)
-#define    VAC_INT_CTRL_PIO9_DISABLE   (0<<14)
-#define VAC_DEV_LOC          0x1700
-#define    VAC_DEV_LOC_IOSEL(x)   (1<<(x))
-#define VAC_PIO_DATA_OUT     0x1800
-#define VAC_PIO_PIN          0x1900
-#define VAC_PIO_DIRECTION    0x1A00
-#define    VAC_PIO_DIR_OUT(x)     (1<<(x))
-#define    VAC_PIO_DIR_IN(x)      (0<<(x))
-#define    VAC_PIO_DIR_FCIACK     (1<<14)
-#define VAC_PIO_FUNC         0x1B00
-#define    VAC_PIO_FUNC_UART_A_TX (1<<0)
-#define    VAC_PIO_FUNC_UART_A_RX (1<<1)
-#define    VAC_PIO_FUNC_UART_B_TX (1<<2)
-#define    VAC_PIO_FUNC_UART_B_RX (1<<3)
-#define    VAC_PIO_FUNC_IORD      (1<<4)
-#define    VAC_PIO_FUNC_IOWR      (1<<5)
-#define    VAC_PIO_FUNC_IOSEL3    (1<<6)
-#define    VAC_PIO_FUNC_IRQ7      (1<<7)
-#define    VAC_PIO_FUNC_IOSEL4    (1<<8)
-#define    VAC_PIO_FUNC_IOSEL5    (1<<9)
-#define    VAC_PIO_FUNC_IRQ10     (1<<10)
-#define    VAC_PIO_FUNC_IRQ11     (1<<11)
-#define    VAC_PIO_FUNC_OUT       (1<<12)
-#define    VAC_PIO_FUNC_IOSEL2    (1<<13)
-#define    VAC_PIO_FUNC_DELAY     (1<<14)
-#define    VAC_PIO_FUNC_FCIACK    (1<<15)
-#define VAC_CPU_CLK_DIV      0x1C00
-#define VAC_UART_A_MODE      0x1D00
-#define    VAC_UART_MODE_PARITY_ENABLE  (1<<15) /* Inversed in manual ? */
-#define    VAC_UART_MODE_PARITY_ODD     (1<<14) /* Inversed in manual ? */
-#define    VAC_UART_MODE_8BIT_CHAR      (1<<13)
-#define    VAC_UART_MODE_BAUD(x)        (((x)&7)<<10)
-#define    VAC_UART_MODE_CHAR_RX_ENABLE (1<<9)
-#define    VAC_UART_MODE_CHAR_TX_ENABLE (1<<8)
-#define    VAC_UART_MODE_TX_ENABLE      (1<<7)
-#define    VAC_UART_MODE_RX_ENABLE      (1<<6)
-#define    VAC_UART_MODE_SEND_BREAK     (1<<5)
-#define    VAC_UART_MODE_LOOPBACK       (1<<4)
-#define    VAC_UART_MODE_INITIAL        (VAC_UART_MODE_8BIT_CHAR | \
-                                         VAC_UART_MODE_TX_ENABLE | \
-                                         VAC_UART_MODE_RX_ENABLE | \
-                                         VAC_UART_MODE_CHAR_TX_ENABLE | \
-                                         VAC_UART_MODE_CHAR_RX_ENABLE | \
-                                         VAC_UART_MODE_BAUD(5)) /* 9600/4 */
-#define VAC_UART_A_TX        0x1E00
-#define VAC_UART_B_MODE      0x1F00
-#define VAC_UART_A_RX        0x2000
-#define    VAC_UART_RX_ERR_BREAK        (1<<10)
-#define    VAC_UART_RX_ERR_FRAME        (1<<9)
-#define    VAC_UART_RX_ERR_PARITY       (1<<8)
-#define    VAC_UART_RX_DATA_MASK        (0xff)
-#define VAC_UART_B_RX        0x2100
-#define VAC_UART_B_TX        0x2200
-#define VAC_UART_A_INT_MASK  0x2300
-#define    VAC_UART_INT_RX_READY        (1<<15)
-#define    VAC_UART_INT_RX_FULL         (1<<14)
-#define    VAC_UART_INT_RX_BREAK_CHANGE (1<<13)
-#define    VAC_UART_INT_RX_ERRS         (1<<12)
-#define    VAC_UART_INT_TX_READY        (1<<11)
-#define    VAC_UART_INT_TX_EMPTY        (1<<10)
-#define VAC_UART_B_INT_MASK  0x2400
-#define VAC_UART_A_INT_STATUS  0x2500
-#define    VAC_UART_STATUS_RX_READY        (1<<15)
-#define    VAC_UART_STATUS_RX_FULL         (1<<14)
-#define    VAC_UART_STATUS_RX_BREAK_CHANGE (1<<13)
-#define    VAC_UART_STATUS_RX_ERR_PARITY   (1<<12)
-#define    VAC_UART_STATUS_RX_ERR_FRAME    (1<<11)
-#define    VAC_UART_STATUS_RX_ERR_OVERRUN  (1<<10)
-#define    VAC_UART_STATUS_TX_READY        (1<<9)
-#define    VAC_UART_STATUS_TX_EMPTY        (1<<8)
-#define    VAC_UART_STATUS_INTS            (0xff<<8)
-#define VAC_UART_B_INT_STATUS  0x2600
-#define VAC_TIMER_DATA       0x2700
-#define VAC_TIMER_CTRL       0x2800
-#define    VAC_TIMER_ONCE      (1<<15)
-#define    VAC_TIMER_ENABLE    (1<<14)
-#define    VAC_TIMER_PRESCALE(x) (((x)&0x3F)<<8)
-#define VAC_ID               0x2900
-
-
-#ifndef __ASSEMBLY__
-
-#define vac_inb(p)    (*(volatile unsigned char *)(VAC_BASE + (p)))
-#define vac_outb(v,p) (*((volatile unsigned char *)(VAC_BASE + (p))) = v)
-#define vac_inw(p)    (*(volatile unsigned short*)(VAC_BASE + (p)))
-#define vac_outw(v,p) (*((volatile unsigned short*)(VAC_BASE + (p))) = v)
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_VAC_H */
diff --git a/include/asm-mips/baget/vic.h b/include/asm-mips/baget/vic.h
deleted file mode 100644
index c70f303e6f47..000000000000
--- a/include/asm-mips/baget/vic.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- * vic.h: Various VIC controller defines.  The VIC is an interrupt controller
- *        used in Baget/MIPS series.
- *
- * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
- */
-#ifndef _ASM_BAGET_VIC_H
-#define _ASM_BAGET_VIC_H
-
-#define VIC_VME_II       0x3
-#define VIC_VME_INT1     0x7
-#define VIC_VME_INT2     0xB
-#define VIC_VME_INT3     0xF
-#define VIC_VME_INT4     0x13
-#define VIC_VME_INT5     0x17
-#define VIC_VME_INT6     0x1B
-#define VIC_VME_INT7     0x1F
-#define VIC_DMA_INT      0x23
-#define VIC_LINT1        0x27
-#define VIC_LINT2        0x2B
-#define VIC_LINT3        0x2F
-#define VIC_LINT4        0x33
-#define VIC_LINT5        0x37
-#define VIC_LINT6        0x3B
-#define VIC_LINT7        0x3F
-#define VIC_ICGS_INT     0x43
-#define VIC_ICMS_INT     0x47
-#define    VIC_INT_IPL(lev)  ((~(lev))&0x7)
-#define    VIC_INT_ACTIVE    (1<<3)
-#define    VIC_INT_AUTO      (0<<4)
-#define    VIC_INT_NOAUTO    (1<<4)
-#define    VIC_INT_LEVEL     (0<<5)
-#define    VIC_INT_EDGE      (1<<5)
-#define    VIC_INT_LOW       (0<<6)
-#define    VIC_INT_HIGH      (1<<6)
-#define    VIC_INT_ENABLE    (0<<7)
-#define    VIC_INT_DISABLE   (1<<7)
-#define    VIC_INT_SWITCH(x) (1<<(((x)&0x3)+4))
-#define VIC_ERR_INT      0x4B
-#define    VIC_ERR_INT_SYSFAIL_ACTIVE  (1<<3)
-#define    VIC_ERR_INT_SYSFAIL  (1<<4)
-#define    VIC_ERR_INT_TIMO     (1<<5)
-#define    VIC_ERR_INT_WRPOST   (1<<6)
-#define    VIC_ERR_INT_ACFAIL   (1<<7)
-#define VIC_ICGS_BASE    0x4F
-#define VIC_ICMS_BASE    0x53
-#define    VIC_ICxS_BASE_GSWITCH_MASK 0x3
-#define    VIC_ICxS_BASE_ID(x)  (((x)&0x3f)<<2)
-#define VIC_LOCAL_BASE   0x57
-#define    VIC_LOCAL_BASE_LINT_MASK 0x7
-#define    VIC_LOCAL_BASE_ID(x)  (((x)&0x1f)<<3)
-#define VIC_ERR_BASE     0x5B
-#define    VIC_ERR_BASE_ACFAIL   0
-#define    VIC_ERR_BASE_WRPOST   1
-#define    VIC_ERR_BASE_TIMO     2
-#define    VIC_ERR_BASE_SYSFAIL  3
-#define    VIC_ERR_BASE_VMEACK   4
-#define    VIC_ERR_BASE_DMA      5
-#define    VIC_ERR_BASE_ID(x)  (((x)&0x1f)<<3)
-#define VIC_ICS          0x5F
-#define VIC_IC0          0x63
-#define VIC_IC1          0x67
-#define VIC_IC2          0x6B
-#define VIC_IC3          0x6F
-#define VIC_IC4          0x73
-#define VIC_ID           0x77
-#define VIC_IC6          0x7B
-#define    VIC_IC6_IRESET_STATUS (1<<7)
-#define    VIC_IC6_HALT_STATUS   (1<<6)
-#define    VIC_IC6_SYSRESET   (3<<0)
-#define    VIC_IC6_RESET      (2<<0)
-#define    VIC_IC6_HALT       (1<<0)
-#define    VIC_IC6_RUN        (0<<0)
-#define VIC_IC7          0x7F
-#define    VIC_IC7_SYSFAIL     (1<<7)
-#define    VIC_IC7_RESET       (1<<6)
-#define    VIC_IC7_VME_MASTER  (1<<5)
-#define    VIC_IC7_SEMSET(x)   ((1<<(x))&0x1f)
-#define VIC_VME_REQ      0x83
-#define VIC_VME_BASE1    0x87
-#define VIC_VME_BASE2    0x8B
-#define VIC_VME_BASE3    0x8F
-#define VIC_VME_BASE4    0x93
-#define VIC_VME_BASE5    0x97
-#define VIC_VME_BASE6    0x9B
-#define VIC_VME_BASE7    0x9F
-#define VIC_XFER_TIMO    0xA3
-#define    VIC_XFER_TIMO_VME_PERIOD_INF (7<<5)
-#define    VIC_XFER_TIMO_VME_PERIOD_512 (6<<5)
-#define    VIC_XFER_TIMO_VME_PERIOD_256 (5<<5)
-#define    VIC_XFER_TIMO_VME_PERIOD_128 (4<<5)
-#define    VIC_XFER_TIMO_VME_PERIOD_64 (3<<5)
-#define    VIC_XFER_TIMO_VME_PERIOD_32 (2<<5)
-#define    VIC_XFER_TIMO_VME_PERIOD_16 (1<<5)
-#define    VIC_XFER_TIMO_VME_PERIOD_4  (0<<5)
-#define    VIC_XFER_TIMO_VME_PERIOD_VAL(x) (((x)>>5)&7)
-#define    VIC_XFER_TIMO_LOCAL_PERIOD_INF (7<<2)
-#define    VIC_XFER_TIMO_LOCAL_PERIOD_512 (6<<2)
-#define    VIC_XFER_TIMO_LOCAL_PERIOD_256 (5<<2)
-#define    VIC_XFER_TIMO_LOCAL_PERIOD_128 (4<<2)
-#define    VIC_XFER_TIMO_LOCAL_PERIOD_64 (3<<2)
-#define    VIC_XFER_TIMO_LOCAL_PERIOD_32 (2<<2)
-#define    VIC_XFER_TIMO_LOCAL_PERIOD_16 (1<<2)
-#define    VIC_XFER_TIMO_LOCAL_PERIOD_4  (0<<2)
-#define    VIC_XFER_TIMO_LOCAL_PERIOD_VAL(x) (((x)>>2)&7)
-#define    VIC_XFER_TIMO_ARB  (1<<1)
-#define    VIC_XFER_TIMO_VME  (1<<0)
-#define VIC_LOCAL_TIM    0xA7
-#define    VIC_LOCAL_TIM_PAS_ASSERT(x)   (((x)-2)&0xf)
-#define    VIC_LOCAL_TIM_PAS_ASSERT_VAL(x) (((x)&0xf)+2)
-#define    VIC_LOCAT_TIM_DS_DEASSERT(x)  ((((x)-1)&1)<<4)
-#define    VIC_LOCAT_TIM_DS_DEASSERT_VAL(x)  ((((x)>>4)&1)+1)
-#define    VIC_LOCAL_TIM_PAS_DEASSERT(x) ((((x)-1)&0x7)<<5)
-#define    VIC_LOCAL_TIM_PAS_DEASSERT_VAL(x) ((((x)>>5)&0x7)+1)
-#define VIC_BXFER_DEF    0xAB
-#define    VIC_BXFER_DEF_VME_CROSS    (1<<3)
-#define    VIC_BXFER_DEF_LOCAL_CROSS  (1<<2)
-#define    VIC_BXFER_DEF_AMSR   (1<<1)
-#define    VIC_BXFER_DEF_DUAL   (1<<0)
-#define VIC_IFACE_CFG    0xAF
-#define    VIC_IFACE_CFG_RMC3    (1<<7)
-#define    VIC_IFACE_CFG_RMC2    (1<<6)
-#define    VIC_IFACE_CFG_RMC1    (1<<5)
-#define    VIC_IFACE_CFG_HALT    (1<<4)
-#define    VIC_IFACE_CFG_NOHALT  (0<<4)
-#define    VIC_IFACE_CFG_NORMC   (1<<3)
-#define    VIC_IFACE_CFG_DEADLOCK_VAL(x) (((x)>>3)&3)
-#define    VIC_IFACE_CFG_MSTAB   (1<<2)
-#define    VIC_IFACE_CFG_TURBO   (1<<1)
-#define    VIC_IFACE_CFG_NOTURBO (0<<1)
-#define    VIC_IFACE_CFG_VME     (1<<0)
-#define VIC_REQ_CFG      0xB3
-#define    VIC_REQ_CFG_FAIRNESS_DISABLED  0
-#define    VIC_REQ_CFG_FAIRNESS_ENABLED   1
-#define    VIC_REQ_CFG_TIMO_DISABLED      0xf
-#define    VIC_REQ_CFG_DRAM_REFRESH       (1<<4)
-#define    VIC_REQ_CFG_LEVEL(x)           (((x)&3)<<5)
-#define    VIC_REQ_CFG_PRIO_ARBITRATION   (1<<7)
-#define    VIC_REQ_CFG_RR_ARBITRATION     (0<<7)
-#define VIC_AMS          0xB7
-#define    VIC_AMS_AM_2_0   (1<<7)
-#define    VIC_AMS_AM_5_3   (1<<6)
-#define    VIC_AMS_CODE(x)  ((x)&0x1f)
-#define VIC_BERR_STATUS  0xBB
-#define VIC_DMA_STATUS   0xBF
-#define VIC_SS0CR0       0xC3
-#define VIC_SS1CR0       0xCB
-#define    VIC_SSxCR0_LOCAL_XFER_ACCEL  (2)
-#define    VIC_SSxCR0_LOCAL_XFER_SINGLE (1)
-#define    VIC_SSxCR0_LOCAL_XFER_NONE   (0)
-#define    VIC_SSxCR0_A32       (0<<2)
-#define    VIC_SSxCR0_A24       (1<<2)
-#define    VIC_SSxCR0_A16       (2<<2)
-#define    VIC_SSxCR0_USER      (3<<2)
-#define    VIC_SSxCR0_D32       (1<<4)
-#define    VIC_SSxCR0_SUPER     (1<<5)
-#define    VIC_SS0CR0_TIMER_FREQ_MASK   (3<<6)
-#define    VIC_SS0CR0_TIMER_FREQ_NONE   (0<<6)
-#define    VIC_SS0CR0_TIMER_FREQ_50HZ   (1<<6)
-#define    VIC_SS0CR0_TIMER_FREQ_1000HZ (2<<6)
-#define    VIC_SS0CR0_TIMER_FREQ_100HZ  (3<<6)
-#define    VIC_SS1CR0_MASTER_WRPOST (1<<6)
-#define    VIC_SS1CR0_SLAVE_WRPOST  (1<<7)
-#define VIC_SS0CR1       0xC7
-#define VIC_SS1CR1       0xCF
-#define    VIC_SSxCR1_TF2(x)  (((x)&0xf)<<4)
-#define    VIC_SSxCR1_TF1(x)  ((x)&0xf)
-#define VIC_RELEASE      0xD3
-#define    VIC_RELEASE_BLKXFER_BLEN(x) ((x)&0x1f)
-#define    VIC_RELEASE_ROR             (0<<6)
-#define    VIC_RELEASE_RWD             (1<<6)
-#define    VIC_RELEASE_ROC             (2<<6)
-#define    VIC_RELEASE_BCAP            (3<<6)
-#define VIC_BXFER_CTRL   0xD7
-#define    VIC_BXFER_CTRL_MODULE     (1<<7)
-#define    VIC_BXFER_CTRL_LOCAL      (1<<6)
-#define    VIC_BXFER_CTRL_MOVEM      (1<<5)
-#define    VIC_BXFER_CTRL_READ       (1<<4)
-#define    VIC_BXFER_CTRL_WRITE      (0<<4)
-#define    VIC_BXFER_CTRL_INTERLEAVE(x)  ((x)&0xf)
-#define VIC_BXFER_LEN_LO    0xDB
-#define VIC_BXFER_LEN_HI    0xDF
-#define VIC_SYS_RESET    0xE3
-
-#ifndef __ASSEMBLY__
-
-#define vic_inb(p)    (*(volatile unsigned char *)(VIC_BASE + (p)))
-#define vic_outb(v,p) (*((volatile unsigned char *)(VIC_BASE + (p))) = v)
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_BAGET_VIC_H */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index cb06e891d0aa..3f41f32433b1 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -13,25 +13,27 @@
 #include <linux/compiler.h>
 #include <linux/types.h>
 #include <asm/byteorder.h>		/* sigh ... */
+#include <asm/cpu-features.h>
 
 #if (_MIPS_SZLONG == 32)
 #define SZLONG_LOG 5
 #define SZLONG_MASK 31UL
-#define __LL	"ll"
-#define __SC	"sc"
+#define __LL	"ll	"
+#define __SC	"sc	"
 #define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) 
 #elif (_MIPS_SZLONG == 64)
 #define SZLONG_LOG 6
 #define SZLONG_MASK 63UL
-#define __LL	"lld"
-#define __SC	"scd"
+#define __LL	"lld	"
+#define __SC	"scd	"
 #define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) 
 #endif
 
 #ifdef __KERNEL__
 
+#include <asm/interrupt.h>
 #include <asm/sgidefs.h>
-#include <asm/system.h>
+#include <asm/war.h>
 
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
@@ -43,26 +45,16 @@
  * Only disable interrupt for kernel mode stuff to keep usermode stuff
  * that dares to use kernel include files alive.
  */
+
 #define __bi_flags			unsigned long flags
-#define __bi_cli()			local_irq_disable()
-#define __bi_save_flags(x)		local_save_flags(x)
 #define __bi_local_irq_save(x)		local_irq_save(x)
 #define __bi_local_irq_restore(x)	local_irq_restore(x)
 #else
 #define __bi_flags
-#define __bi_cli()
-#define __bi_save_flags(x)
 #define __bi_local_irq_save(x)
 #define __bi_local_irq_restore(x)
 #endif /* __KERNEL__ */
 
-#ifdef CONFIG_CPU_HAS_LLSC
-
-/*
- * These functions for MIPS ISA > 1 are interrupt and SMP proof and
- * interrupt friendly
- */
-
 /*
  * set_bit - Atomically set a bit in memory
  * @nr: the bit to set
@@ -78,13 +70,33 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
 	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 	unsigned long temp;
 
-	__asm__ __volatile__(
-		"1:\t" __LL "\t%0, %1\t\t# set_bit\n\t"
-		"or\t%0, %2\n\t"
-		__SC "\t%0, %1\n\t"
-		"beqz\t%0, 1b"
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		__asm__ __volatile__(
+		"1:	" __LL "%0, %1			# set_bit	\n"
+		"	or	%0, %2					\n"
+		"	"__SC	"%0, %1					\n"
+		"	beqzl	%0, 1b					\n"
 		: "=&r" (temp), "=m" (*m)
 		: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+	} else if (cpu_has_llsc) {
+		__asm__ __volatile__(
+		"1:	" __LL "%0, %1			# set_bit	\n"
+		"	or	%0, %2					\n"
+		"	"__SC	"%0, %1					\n"
+		"	beqz	%0, 1b					\n"
+		: "=&r" (temp), "=m" (*m)
+		: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+	} else {
+		volatile unsigned long *a = addr;
+		unsigned long mask;
+		__bi_flags;
+
+		a += nr >> SZLONG_LOG;
+		mask = 1 << (nr & SZLONG_MASK);
+		__bi_local_irq_save(flags);
+		*a |= mask;
+		__bi_local_irq_restore(flags);
+	}
 }
 
 /*
@@ -118,13 +130,33 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
 	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
 	unsigned long temp;
 
-	__asm__ __volatile__(
-		"1:\t" __LL "\t%0, %1\t\t# clear_bit\n\t"
-		"and\t%0, %2\n\t"
-		__SC "\t%0, %1\n\t"
-		"beqz\t%0, 1b\n\t"
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		__asm__ __volatile__(
+		"1:	" __LL "%0, %1			# clear_bit	\n"
+		"	and	%0, %2					\n"
+		"	" __SC "%0, %1					\n"
+		"	beqzl	%0, 1b					\n"
+		: "=&r" (temp), "=m" (*m)
+		: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
+	} else if (cpu_has_llsc) {
+		__asm__ __volatile__(
+		"1:	" __LL "%0, %1			# clear_bit	\n"
+		"	and	%0, %2					\n"
+		"	" __SC "%0, %1					\n"
+		"	beqz	%0, 1b					\n"
 		: "=&r" (temp), "=m" (*m)
 		: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
+	} else {
+		volatile unsigned long *a = addr;
+		unsigned long mask;
+		__bi_flags;
+
+		a += nr >> SZLONG_LOG;
+		mask = 1 << (nr & SZLONG_MASK);
+		__bi_local_irq_save(flags);
+		*a &= ~mask;
+		__bi_local_irq_restore(flags);
+	}
 }
 
 /*
@@ -154,16 +186,39 @@ static inline void __clear_bit(unsigned long nr, volatile unsigned long * addr)
  */
 static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
 {
-	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-	unsigned long temp;
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+		unsigned long temp;
 
-	__asm__ __volatile__(
-		"1:\t" __LL "\t%0, %1\t\t# change_bit\n\t"
-		"xor\t%0, %2\n\t"
-		__SC "\t%0, %1\n\t"
-		"beqz\t%0, 1b"
+		__asm__ __volatile__(
+		"1:	" __LL "%0, %1		# change_bit	\n"
+		"	xor	%0, %2				\n"
+		"	"__SC	"%0, %1				\n"
+		"	beqzl	%0, 1b				\n"
 		: "=&r" (temp), "=m" (*m)
 		: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+	} else if (cpu_has_llsc) {
+		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+		unsigned long temp;
+
+		__asm__ __volatile__(
+		"1:	" __LL "%0, %1		# change_bit	\n"
+		"	xor	%0, %2				\n"
+		"	"__SC	"%0, %1				\n"
+		"	beqz	%0, 1b				\n"
+		: "=&r" (temp), "=m" (*m)
+		: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
+	} else {
+		volatile unsigned long *a = addr;
+		unsigned long mask;
+		__bi_flags;
+
+		a += nr >> SZLONG_LOG;
+		mask = 1 << (nr & SZLONG_MASK);
+		__bi_local_irq_save(flags);
+		*a ^= mask;
+		__bi_local_irq_restore(flags);
+	}
 }
 
 /*
@@ -193,25 +248,59 @@ static inline void __change_bit(unsigned long nr, volatile unsigned long * addr)
 static inline int test_and_set_bit(unsigned long nr,
 	volatile unsigned long *addr)
 {
-	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-	unsigned long temp, res;
-
-	__asm__ __volatile__(
-		".set\tnoreorder\t\t# test_and_set_bit\n"
-		"1:\t" __LL "\t%0, %1\n\t"
-		"or\t%2, %0, %3\n\t"
-		__SC "\t%2, %1\n\t"
-		"beqz\t%2, 1b\n\t"
-		" and\t%2, %0, %3\n\t"
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+		unsigned long temp, res;
+
+		__asm__ __volatile__(
+		"1:	" __LL "%0, %1		# test_and_set_bit	\n"
+		"	or	%2, %0, %3				\n"
+		"	" __SC	"%2, %1					\n"
+		"	beqzl	%2, 1b					\n"
+		"	and	%2, %0, %3				\n"
 #ifdef CONFIG_SMP
-		"sync\n\t"
+		"sync							\n"
+#endif
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+		: "memory");
+
+		return res != 0;
+	} else if (cpu_has_llsc) {
+		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+		unsigned long temp, res;
+
+		__asm__ __volatile__(
+		"	.set	noreorder	# test_and_set_bit	\n"
+		"1:	" __LL "%0, %1					\n"
+		"	or	%2, %0, %3				\n"
+		"	" __SC	"%2, %1					\n"
+		"	beqz	%2, 1b					\n"
+		"	 and	%2, %0, %3				\n"
+#ifdef CONFIG_SMP
+		"sync							\n"
 #endif
 		".set\treorder"
 		: "=&r" (temp), "=m" (*m), "=&r" (res)
 		: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
 		: "memory");
 
-	return res != 0;
+		return res != 0;
+	} else {
+		volatile unsigned long *a = addr;
+		unsigned long mask;
+		int retval;
+		__bi_flags;
+
+		a += nr >> SZLONG_LOG;
+		mask = 1 << (nr & SZLONG_MASK);
+		__bi_local_irq_save(flags);
+		retval = (mask & *a) != 0;
+		*a |= mask;
+		__bi_local_irq_restore(flags);
+
+		return retval;
+	}
 }
 
 /*
@@ -249,26 +338,61 @@ static inline int __test_and_set_bit(unsigned long nr,
 static inline int test_and_clear_bit(unsigned long nr,
 	volatile unsigned long *addr)
 {
-	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-	unsigned long temp, res;
-
-	__asm__ __volatile__(
-		".set\tnoreorder\t\t# test_and_clear_bit\n"
-		"1:\t" __LL "\t%0, %1\n\t"
-		"or\t%2, %0, %3\n\t"
-		"xor\t%2, %3\n\t"
-		__SC "\t%2, %1\n\t"
-		"beqz\t%2, 1b\n\t"
-		" and\t%2, %0, %3\n\t"
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+		unsigned long temp, res;
+
+		__asm__ __volatile__(
+		"1:	" __LL	"%0, %1		# test_and_clear_bit	\n"
+		"	or	%2, %0, %3				\n"
+		"	xor	%2, %3					\n"
+			__SC 	"%2, %1					\n"
+		"	beqzl	%2, 1b					\n"
+		"	and	%2, %0, %3				\n"
 #ifdef CONFIG_SMP
-		"sync\n\t"
+		"	sync						\n"
 #endif
-		".set\treorder"
 		: "=&r" (temp), "=m" (*m), "=&r" (res)
 		: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
 		: "memory");
 
-	return res != 0;
+		return res != 0;
+	} else if (cpu_has_llsc) {
+		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+		unsigned long temp, res;
+
+		__asm__ __volatile__(
+		"	.set	noreorder	# test_and_clear_bit	\n"
+		"1:	" __LL	"%0, %1					\n"
+		"	or	%2, %0, %3				\n"
+		"	xor	%2, %3					\n"
+			__SC 	"%2, %1					\n"
+		"	beqz	%2, 1b					\n"
+		"	 and	%2, %0, %3				\n"
+#ifdef CONFIG_SMP
+		"	sync						\n"
+#endif
+		"	.set	reorder					\n"
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+		: "memory");
+
+		return res != 0;
+	} else {
+		volatile unsigned long *a = addr;
+		unsigned long mask;
+		int retval;
+		__bi_flags;
+
+		a += nr >> SZLONG_LOG;
+		mask = 1 << (nr & SZLONG_MASK);
+		__bi_local_irq_save(flags);
+		retval = (mask & *a) != 0;
+		*a &= ~mask;
+		__bi_local_irq_restore(flags);
+
+		return retval;
+	}
 }
 
 /*
@@ -306,322 +430,88 @@ static inline int __test_and_clear_bit(unsigned long nr,
 static inline int test_and_change_bit(unsigned long nr,
 	volatile unsigned long *addr)
 {
-	unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-	unsigned long temp, res;
-
-	__asm__ __volatile__(
-		".set\tnoreorder\t\t# test_and_change_bit\n"
-		"1:\t" __LL "\t%0, %1\n\t"
-		"xor\t%2, %0, %3\n\t"
-		__SC "\t%2, %1\n\t"
-		"beqz\t%2, 1b\n\t"
-		" and\t%2, %0, %3\n\t"
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+		unsigned long temp, res;
+
+		__asm__ __volatile__(
+		"1:	" __LL	" %0, %1	# test_and_change_bit	\n"
+		"	xor	%2, %0, %3				\n"
+		"	"__SC	"%2, %1					\n"
+		"	beqzl	%2, 1b					\n"
+		"	and	%2, %0, %3				\n"
 #ifdef CONFIG_SMP
-		"sync\n\t"
+		"	sync						\n"
 #endif
-		".set\treorder"
 		: "=&r" (temp), "=m" (*m), "=&r" (res)
 		: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
 		: "memory");
 
-	return res != 0;
-}
-
-/*
- * __test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to change
- * @addr: Address to count from
- *
- * This operation is non-atomic and can be reordered.
- * If two examples of this operation race, one can appear to succeed
- * but actually fail.  You must protect multiple accesses with a lock.
- */
-static inline int __test_and_change_bit(unsigned long nr,
-	volatile unsigned long *addr)
-{
-	volatile unsigned long *a = addr;
-	unsigned long mask;
-	int retval;
-
-	a += (nr >> SZLONG_LOG);
-	mask = 1UL << (nr & SZLONG_MASK);
-	retval = ((mask & *a) != 0);
-	*a ^= mask;
-
-	return retval;
-}
-
-#else /* MIPS I */
-
-/*
- * set_bit - Atomically set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * This function is atomic and may not be reordered.  See __set_bit()
- * if you do not require the atomic guarantees.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void set_bit(unsigned long nr, volatile unsigned long * addr)
-{
-	volatile unsigned long *a = addr;
-	unsigned long mask;
-	__bi_flags;
-
-	a += nr >> SZLONG_LOG;
-	mask = 1 << (nr & SZLONG_MASK);
-	__bi_local_irq_save(flags);
-	*a |= mask;
-	__bi_local_irq_restore(flags);
-}
-
-/*
- * __set_bit - Set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * Unlike set_bit(), this function is non-atomic and may be reordered.
- * If it's called on the same region of memory simultaneously, the effect
- * may be that only one operation succeeds.
- */
-static inline void __set_bit(unsigned long nr, volatile unsigned long * addr)
-{
-	volatile unsigned long *a = addr;
-	unsigned long mask;
-
-	a += nr >> SZLONG_LOG;
-	mask = 1 << (nr & SZLONG_MASK);
-	*a |= mask;
-}
-
-/*
- * clear_bit - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and may not be reordered.  However, it does
- * not contain a memory barrier, so if it is used for locking purposes,
- * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
- * in order to ensure changes are visible on other processors.
- */
-static inline void clear_bit(unsigned long nr, volatile unsigned long * addr)
-{
-	volatile unsigned long *a = addr;
-	unsigned long mask;
-	__bi_flags;
+		return res != 0;
+	} else if (cpu_has_llsc) {
+		unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
+		unsigned long temp, res;
+
+		__asm__ __volatile__(
+		"	.set	noreorder	# test_and_change_bit	\n"
+		"1:	" __LL	" %0, %1				\n"
+		"	xor	%2, %0, %3				\n"
+		"	"__SC	"\t%2, %1				\n"
+		"	beqz	%2, 1b					\n"
+		"	 and	%2, %0, %3				\n"
+#ifdef CONFIG_SMP
+		"	sync						\n"
+#endif
+		"	.set	reorder					\n"
+		: "=&r" (temp), "=m" (*m), "=&r" (res)
+		: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
+		: "memory");
 
-	a += nr >> SZLONG_LOG;
-	mask = 1 << (nr & SZLONG_MASK);
-	__bi_local_irq_save(flags);
-	*a &= ~mask;
-	__bi_local_irq_restore(flags);
-}
+		return res != 0;
+	} else {
+		volatile unsigned long *a = addr;
+		unsigned long mask, retval;
+		__bi_flags;
 
-static inline void __clear_bit(unsigned long nr, volatile unsigned long * addr)
-{
-	volatile unsigned long *a = addr;
-	unsigned long mask;
+		a += nr >> SZLONG_LOG;
+		mask = 1 << (nr & SZLONG_MASK);
+		__bi_local_irq_save(flags);
+		retval = (mask & *a) != 0;
+		*a ^= mask;
+		__bi_local_irq_restore(flags);
 
-	a += nr >> SZLONG_LOG;
-	mask = 1 << (nr & SZLONG_MASK);
-	*a &= ~mask;
+		return retval;
+	}
 }
 
 /*
- * change_bit - Toggle a bit in memory
+ * __test_and_change_bit - Change a bit and return its old value
  * @nr: Bit to change
- * @addr: Address to start counting from
- *
- * change_bit() is atomic and may not be reordered.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void change_bit(unsigned long nr, volatile unsigned long * addr)
-{
-	volatile unsigned long *a = addr;
-	unsigned long mask;
-	__bi_flags;
-
-	a += nr >> SZLONG_LOG;
-	mask = 1 << (nr & SZLONG_MASK);
-	__bi_local_irq_save(flags);
-	*a ^= mask;
-	__bi_local_irq_restore(flags);
-}
-
-/*
- * __change_bit - Toggle a bit in memory
- * @nr: the bit to change
- * @addr: the address to start counting from
- *
- * Unlike change_bit(), this function is non-atomic and may be reordered.
- * If it's called on the same region of memory simultaneously, the effect
- * may be that only one operation succeeds.
- */
-static inline void __change_bit(unsigned long nr, volatile unsigned long * addr)
-{
-	unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-
-	*m ^= 1UL << (nr & SZLONG_MASK);
-}
-
-/*
- * test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_set_bit(unsigned long nr,
-	volatile unsigned long * addr)
-{
-	volatile unsigned long *a = addr;
-	unsigned long mask;
-	int retval;
-	__bi_flags;
-
-	a += nr >> SZLONG_LOG;
-	mask = 1 << (nr & SZLONG_MASK);
-	__bi_local_irq_save(flags);
-	retval = (mask & *a) != 0;
-	*a |= mask;
-	__bi_local_irq_restore(flags);
-
-	return retval;
-}
-
-/*
- * __test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
  * @addr: Address to count from
  *
  * This operation is non-atomic and can be reordered.
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
  */
-static inline int __test_and_set_bit(unsigned long nr,
+static inline int __test_and_change_bit(unsigned long nr,
 	volatile unsigned long *addr)
 {
 	volatile unsigned long *a = addr;
 	unsigned long mask;
 	int retval;
 
-	a += nr >> SZLONG_LOG;
-	mask = 1 << (nr & SZLONG_MASK);
-	retval = (mask & *a) != 0;
-	*a |= mask;
-
-	return retval;
-}
-
-/*
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to clear
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_clear_bit(unsigned long nr,
-	volatile unsigned long * addr)
-{
-	volatile unsigned long *a = addr;
-	unsigned long mask;
-	int retval;
-	__bi_flags;
-
-	a += nr >> SZLONG_LOG;
-	mask = 1 << (nr & SZLONG_MASK);
-	__bi_local_irq_save(flags);
-	retval = (mask & *a) != 0;
-	*a &= ~mask;
-	__bi_local_irq_restore(flags);
-
-	return retval;
-}
-
-/*
- * __test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to clear
- * @addr: Address to count from
- *
- * This operation is non-atomic and can be reordered.
- * If two examples of this operation race, one can appear to succeed
- * but actually fail.  You must protect multiple accesses with a lock.
- */
-static inline int __test_and_clear_bit(unsigned long nr,
-	volatile unsigned long * addr)
-{
-	volatile unsigned long *a = addr;
-	unsigned long mask;
-	int retval;
-
 	a += (nr >> SZLONG_LOG);
 	mask = 1UL << (nr & SZLONG_MASK);
 	retval = ((mask & *a) != 0);
-	*a &= ~mask;
-
-	return retval;
-}
-
-/*
- * test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to change
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_change_bit(unsigned long nr,
-	volatile unsigned long * addr)
-{
-	volatile unsigned long *a = addr;
-	unsigned long mask, retval;
-	__bi_flags;
-
-	a += nr >> SZLONG_LOG;
-	mask = 1 << (nr & SZLONG_MASK);
-	__bi_local_irq_save(flags);
-	retval = (mask & *a) != 0;
-	*a ^= mask;
-	__bi_local_irq_restore(flags);
-
-	return retval;
-}
-
-/*
- * __test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to change
- * @addr: Address to count from
- *
- * This operation is non-atomic and can be reordered.
- * If two examples of this operation race, one can appear to succeed
- * but actually fail.  You must protect multiple accesses with a lock.
- */
-static inline int __test_and_change_bit(unsigned long nr,
-	volatile unsigned long * addr)
-{
-	volatile unsigned long *a = addr;
-	unsigned long mask;
-	int retval;
-
-	a += (nr >> SZLONG_LOG);
-	mask = 1 << (nr & SZLONG_MASK);
-	retval = (mask & *a) != 0;
 	*a ^= mask;
 
 	return retval;
 }
 
 #undef __bi_flags
-#undef __bi_cli
-#undef __bi_save_flags
+#undef __bi_local_irq_save
 #undef __bi_local_irq_restore
 
-#endif /* MIPS I */
-
 /*
  * test_bit - Determine whether a bit is set
  * @nr: bit number to test
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index c9c257c201eb..9e49d9c71263 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -122,6 +122,7 @@
 #define  MACH_MOMENCO_OCELOT_G	1
 #define  MACH_MOMENCO_OCELOT_C	2
 #define  MACH_MOMENCO_JAGUAR_ATX 3
+#define  MACH_MOMENCO_OCELOT_3	4
 
 /*
  * Valid machtype for group ITE
@@ -175,6 +176,7 @@
 #define  MACH_XXS1500		6       /* Au1500-based eval board */
 #define  MACH_MTX1		7       /* 4G MTX-1 Au1500-based board */
 #define  MACH_PB1550		8       /* Au1550-based eval board */
+#define  MACH_DB1550		9       /* Au1550-based eval board */
 
 /*
  * Valid machtype for group NEC_VR41XX
diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h
index 065426468272..799beca4e8da 100644
--- a/include/asm-mips/checksum.h
+++ b/include/asm-mips/checksum.h
@@ -46,6 +46,7 @@ static inline unsigned int csum_and_copy_to_user (const char *src,
 						  int len, int sum,
 						  int *err_ptr)
 {
+	might_sleep();
 	sum = csum_partial(src, len, sum);
 
 	if (copy_to_user(dst, src, len)) {
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h
index 88ca4d50d42a..38b2116c78d2 100644
--- a/include/asm-mips/compat.h
+++ b/include/asm-mips/compat.h
@@ -132,10 +132,10 @@ static inline void *compat_ptr(compat_uptr_t uptr)
 
 static inline void *compat_alloc_user_space(long len)
 {
-	unsigned long sp = (unsigned long) current_thread_info() +
-	                    THREAD_SIZE - 32;
+	struct pt_regs *regs = (struct pt_regs *)
+		((unsigned long) current_thread_info() + THREAD_SIZE - 32) - 1;
 
-	return (void *) (sp - len);
+	return (void *) (regs->regs[29] - len);
 }
 
 #endif /* _ASM_COMPAT_H */
diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h
new file mode 100644
index 000000000000..169ae26105e9
--- /dev/null
+++ b/include/asm-mips/compiler.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2004  Maciej W. Rozycki
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef _ASM_COMPILER_H
+#define _ASM_COMPILER_H
+
+#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
+#define GCC_REG_ACCUM "$0"
+#else
+#define GCC_REG_ACCUM "accum"
+#endif
+
+#endif /* _ASM_COMPILER_H */
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 1bc8758b39cc..ea559a3ba033 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -8,6 +8,8 @@
 #ifndef __ASM_CPU_FEATURES_H
 #define __ASM_CPU_FEATURES_H
 
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
 #include <cpu-feature-overrides.h>
 
 /*
@@ -69,7 +71,18 @@
 #define cpu_has_dc_aliases	(cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
 #endif
 #ifndef cpu_has_ic_fills_f_dc
-#define cpu_has_ic_fills_f_dc	(cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC)
+#define cpu_has_ic_fills_f_dc	(cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
+#endif
+
+/*
+ * Certain CPUs may throw bizarre exceptions if not the whole cacheline
+ * contains valid instructions.  For these we ensure proper alignment of
+ * signal trampolines and pad them to the size of a full cache lines with
+ * nops.  This is also used in structure definitions so can't be a test macro
+ * like the others.
+ */
+#ifndef PLAT_TRAMPOLINE_STUFF_LINE
+#define PLAT_TRAMPOLINE_STUFF_LINE	0UL
 #endif
 
 #ifdef CONFIG_MIPS32
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
new file mode 100644
index 000000000000..984277a8a7d8
--- /dev/null
+++ b/include/asm-mips/cpu-info.h
@@ -0,0 +1,81 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 Waldorf GMBH
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
+ * Copyright (C) 1996 Paul M. Antoine
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef __ASM_CPU_INFO_H
+#define __ASM_CPU_INFO_H
+
+#include <linux/config.h>
+#include <asm/cache.h>
+
+#ifdef CONFIG_SGI_IP27
+#include <asm/sn/types.h>
+#endif
+
+/*
+ * Descriptor for a cache
+ */
+struct cache_desc {
+	unsigned short linesz;	/* Size of line in bytes */
+	unsigned short ways;	/* Number of ways */
+	unsigned short sets;	/* Number of lines per set */
+	unsigned int waysize;	/* Bytes per way */
+	unsigned int waybit;	/* Bits to select in a cache set */
+	unsigned int flags;	/* Flags describing cache properties */
+};
+
+/*
+ * Flag definitions
+ */
+#define MIPS_CACHE_NOT_PRESENT	0x00000001
+#define MIPS_CACHE_VTAG		0x00000002	/* Virtually tagged cache */
+#define MIPS_CACHE_ALIASES	0x00000004	/* Cache could have aliases */
+#define MIPS_CACHE_IC_F_DC	0x00000008	/* Ic can refill from D-cache */
+
+struct cpuinfo_mips {
+	unsigned long		udelay_val;
+	unsigned long		asid_cache;
+#if defined(CONFIG_SGI_IP27)
+//	cpuid_t		p_cpuid;	/* PROM assigned cpuid */
+	cnodeid_t	p_nodeid;	/* my node ID in compact-id-space */
+	nasid_t		p_nasid;	/* my node ID in numa-as-id-space */
+	unsigned char	p_slice;	/* Physical position on node board */
+#endif
+#if 0
+	unsigned long		loops_per_sec;
+	unsigned long		ipi_count;
+	unsigned long		irq_attempt[NR_IRQS];
+	unsigned long		smp_local_irq_count;
+	unsigned long		prof_multiplier;
+	unsigned long		prof_counter;
+#endif
+
+	/*
+	 * Capability and feature descriptor structure for MIPS CPU
+	 */
+	unsigned long		options;
+	unsigned int		processor_id;
+	unsigned int		fpu_id;
+	unsigned int		cputype;
+	int			isa_level;
+	int			tlbsize;
+	struct cache_desc	icache;	/* Primary I-cache */
+	struct cache_desc	dcache;	/* Primary D or combined I/D cache */
+	struct cache_desc	scache;	/* Secondary cache */
+	struct cache_desc	tcache;	/* Tertiary/split secondary cache */
+	void 			*data;	/* Additional data */
+} __attribute__((aligned(SMP_CACHE_BYTES)));
+
+extern struct cpuinfo_mips cpu_data[];
+#define current_cpu_data cpu_data[smp_processor_id()]
+
+extern void cpu_probe(void);
+extern void cpu_report(void);
+
+#endif /* __ASM_CPU_INFO_H */
diff --git a/include/asm-mips/debug.h b/include/asm-mips/debug.h
index e5466194cade..d71370708cc8 100644
--- a/include/asm-mips/debug.h
+++ b/include/asm-mips/debug.h
@@ -1,5 +1,6 @@
 /*
- * Debug macros for run-time debugging.  Turned on/off with CONFIG_RUNTIME_DEBUG option.
+ * Debug macros for run-time debugging.
+ * Turned on/off with CONFIG_RUNTIME_DEBUG option.
  *
  * Copyright (C) 2001 MontaVista Software Inc.
  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
diff --git a/include/asm-mips/dec/serial.h b/include/asm-mips/dec/serial.h
new file mode 100644
index 000000000000..acad75890a05
--- /dev/null
+++ b/include/asm-mips/dec/serial.h
@@ -0,0 +1,36 @@
+/*
+ *	include/asm-mips/dec/serial.h
+ *
+ *	Definitions common to all DECstation serial devices.
+ *
+ *	Copyright (C) 2004  Maciej W. Rozycki
+ *
+ *	Based on bits extracted from drivers/tc/zs.h for which
+ *	the following copyrights apply:
+ *
+ *	Copyright (C) 1995  David S. Miller (davem@caip.rutgers.edu)
+ *	Copyright (C) 1996  Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
+ *	Copyright (C)       Harald Koerfgen
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MIPS_DEC_SERIAL_H
+#define __ASM_MIPS_DEC_SERIAL_H
+
+struct dec_serial_hook {
+	int (*init_channel)(void *handle);
+	void (*init_info)(void *handle);
+	void (*rx_char)(unsigned char ch, unsigned char fl);
+	int (*poll_rx_char)(void *handle);
+	int (*poll_tx_char)(void *handle, unsigned char ch);
+	unsigned int cflags;
+};
+
+extern int register_dec_serial_hook(unsigned int channel,
+				    struct dec_serial_hook *hook);
+extern int unregister_dec_serial_hook(unsigned int channel);
+
+#endif /* __ASM_MIPS_DEC_SERIAL_H */
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index 91fdf79fd687..d0f68447e5a7 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -13,6 +13,8 @@
 #include <linux/config.h>
 #include <linux/param.h>
 
+#include <asm/compiler.h>
+
 extern unsigned long loops_per_jiffy;
 
 static inline void __delay(unsigned long loops)
@@ -69,11 +71,13 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
 	if (sizeof(long) == 4)
 		__asm__("multu\t%2, %3"
 		: "=h" (usecs), "=l" (lo)
-		: "r" (usecs),"r" (lpj));
+		: "r" (usecs), "r" (lpj)
+		: GCC_REG_ACCUM);
 	else if (sizeof(long) == 8)
 		__asm__("dmultu\t%2, %3"
 		: "=h" (usecs), "=l" (lo)
-		: "r" (usecs),"r" (lpj));
+		: "r" (usecs), "r" (lpj)
+		: GCC_REG_ACCUM);
 
 	__delay(usecs);
 }
diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h
index 7e7e2ea0d6cf..5f7dcf5452e7 100644
--- a/include/asm-mips/div64.h
+++ b/include/asm-mips/div64.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2000 Maciej W. Rozycki
+ * Copyright (C) 2000, 2004  Maciej W. Rozycki
  * Copyright (C) 2003 Ralf Baechle
  *
  * This file is subject to the terms and conditions of the GNU General Public
@@ -11,6 +11,8 @@
 
 #if (_MIPS_SZLONG == 32)
 
+#include <asm/compiler.h>
+
 /*
  * No traps on overflows for any of these...
  */
@@ -67,7 +69,8 @@
 	if (__high) \
 		__asm__("divu	$0, %z2, %z3" \
 			: "=h" (__upper), "=l" (__high) \
-			: "Jr" (__high), "Jr" (__base)); \
+			: "Jr" (__high), "Jr" (__base) \
+			: GCC_REG_ACCUM); \
 	\
 	__mod = do_div64_32(__low, __upper, __low, __base); \
 	\
diff --git a/include/asm-mips/dma-mapping.h b/include/asm-mips/dma-mapping.h
index 716951187bf0..af28dc88930b 100644
--- a/include/asm-mips/dma-mapping.h
+++ b/include/asm-mips/dma-mapping.h
@@ -68,4 +68,12 @@ extern int dma_is_consistent(dma_addr_t dma_addr);
 extern void dma_cache_sync(void *vaddr, size_t size,
 	       enum dma_data_direction direction);
 
+#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
+
+extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
+	dma_addr_t device_addr, size_t size, int flags);
+extern void dma_release_declared_memory(struct device *dev);
+extern void * dma_mark_declared_memory_occupied(struct device *dev,
+	dma_addr_t device_addr, size_t size);
+
 #endif /* _ASM_DMA_MAPPING_H */
diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
index b86291d8ae80..26b6a90a690b 100644
--- a/include/asm-mips/fixmap.h
+++ b/include/asm-mips/fixmap.h
@@ -14,7 +14,6 @@
 #define _ASM_FIXMAP_H
 
 #include <linux/config.h>
-#include <linux/kernel.h>
 #include <asm/page.h>
 #ifdef CONFIG_HIGHMEM
 #include <linux/threads.h>
diff --git a/include/asm-mips/gdb-stub.h b/include/asm-mips/gdb-stub.h
index bbc328f248a1..22f67d4a71ab 100644
--- a/include/asm-mips/gdb-stub.h
+++ b/include/asm-mips/gdb-stub.h
@@ -207,6 +207,7 @@ struct gdb_regs {
  * Prototypes
  */
 
+extern int kgdb_enabled;
 void set_debug_traps(void);
 void set_async_breakpoint(unsigned long *epc);
 
diff --git a/include/asm-mips/hardirq.h b/include/asm-mips/hardirq.h
index 47a0237ac136..8f535d02de1c 100644
--- a/include/asm-mips/hardirq.h
+++ b/include/asm-mips/hardirq.h
@@ -20,24 +20,6 @@ typedef struct {
 
 #include <linux/irq_cpustat.h>	/* Standard mappings for irq_cpustat_t above */
 
-#define HARDIRQ_BITS	8
-
-/*
- * The hardirq mask has to be large enough to have
- * space for potentially all IRQ sources in the system
- * nesting on a single CPU:
- */
-#if (1 << HARDIRQ_BITS) < NR_IRQS
-# error HARDIRQ_BITS is too low!
-#endif
-
-#define irq_enter()		(preempt_count() += HARDIRQ_OFFSET)
-#define irq_exit()                                                     \
-do {                                                                   \
-	preempt_count() -= IRQ_EXIT_OFFSET;                     \
-	if (!in_interrupt() && softirq_pending(smp_processor_id())) \
-		do_softirq();                                   \
-	preempt_enable_no_resched();                            \
-} while (0)
+extern void ack_bad_irq(unsigned int irq);
 
 #endif /* _ASM_HARDIRQ_H */
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index f70b9362aa9f..4b5f12de5594 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -13,7 +13,7 @@
 #ifdef __ASSEMBLY__
 
 	.macro	_ssnop
-	sll	$0, $2, 1
+	sll	$0, $0, 1
 	.endm
 
 /*
diff --git a/include/asm-mips/hw_irq.h b/include/asm-mips/hw_irq.h
index 8be338b9ac10..c854d017c0e5 100644
--- a/include/asm-mips/hw_irq.h
+++ b/include/asm-mips/hw_irq.h
@@ -11,8 +11,6 @@
 #include <linux/profile.h>
 #include <asm/atomic.h>
 
-extern void mask_irq(unsigned int irq);
-extern void unmask_irq(unsigned int irq);
 extern void disable_8259A_irq(unsigned int irq);
 extern void enable_8259A_irq(unsigned int irq);
 extern int i8259A_irq_pending(unsigned int irq);
diff --git a/include/asm-mips/ide.h b/include/asm-mips/ide.h
index 1992aac41a8e..bb674c3b0303 100644
--- a/include/asm-mips/ide.h
+++ b/include/asm-mips/ide.h
@@ -4,22 +4,10 @@
  * for more details.
  *
  * This file contains the MIPS architecture specific IDE code.
- *
- * Copyright (C) 1994-1996  Linus Torvalds & authors
  */
-
 #ifndef __ASM_IDE_H
 #define __ASM_IDE_H
 
-#ifdef __KERNEL__
-
 #include <ide.h>
 
-#define __ide_mm_insw   ide_insw
-#define __ide_mm_insl   ide_insl
-#define __ide_mm_outsw  ide_outsw
-#define __ide_mm_outsl  ide_outsl
-
-#endif /* __KERNEL__ */
-
 #endif /* __ASM_IDE_H */
diff --git a/include/asm-mips/interrupt.h b/include/asm-mips/interrupt.h
new file mode 100644
index 000000000000..e8357f5379fa
--- /dev/null
+++ b/include/asm-mips/interrupt.h
@@ -0,0 +1,134 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_INTERRUPT_H
+#define _ASM_INTERRUPT_H
+
+#include <asm/hazards.h>
+
+__asm__ (
+	".macro\tlocal_irq_enable\n\t"
+	".set\tpush\n\t"
+	".set\treorder\n\t"
+	".set\tnoat\n\t"
+	"mfc0\t$1,$12\n\t"
+	"ori\t$1,0x1f\n\t"
+	"xori\t$1,0x1e\n\t"
+	"mtc0\t$1,$12\n\t"
+	"irq_enable_hazard\n\t"
+	".set\tpop\n\t"
+	".endm");
+
+static inline void local_irq_enable(void)
+{
+	__asm__ __volatile__(
+		"local_irq_enable"
+		: /* no outputs */
+		: /* no inputs */
+		: "memory");
+}
+
+/*
+ * For cli() we have to insert nops to make sure that the new value
+ * has actually arrived in the status register before the end of this
+ * macro.
+ * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
+ * no nops at all.
+ */
+__asm__ (
+	".macro\tlocal_irq_disable\n\t"
+	".set\tpush\n\t"
+	".set\tnoat\n\t"
+	"mfc0\t$1,$12\n\t"
+	"ori\t$1,1\n\t"
+	"xori\t$1,1\n\t"
+	".set\tnoreorder\n\t"
+	"mtc0\t$1,$12\n\t"
+	"irq_disable_hazard\n\t"
+	".set\tpop\n\t"
+	".endm");
+
+static inline void local_irq_disable(void)
+{
+	__asm__ __volatile__(
+		"local_irq_disable"
+		: /* no outputs */
+		: /* no inputs */
+		: "memory");
+}
+
+__asm__ (
+	".macro\tlocal_save_flags flags\n\t"
+	".set\tpush\n\t"
+	".set\treorder\n\t"
+	"mfc0\t\\flags, $12\n\t"
+	".set\tpop\n\t"
+	".endm");
+
+#define local_save_flags(x)						\
+__asm__ __volatile__(							\
+	"local_save_flags %0"						\
+	: "=r" (x))
+
+__asm__ (
+	".macro\tlocal_irq_save result\n\t"
+	".set\tpush\n\t"
+	".set\treorder\n\t"
+	".set\tnoat\n\t"
+	"mfc0\t\\result, $12\n\t"
+	"ori\t$1, \\result, 1\n\t"
+	"xori\t$1, 1\n\t"
+	".set\tnoreorder\n\t"
+	"mtc0\t$1, $12\n\t"
+	"irq_disable_hazard\n\t"
+	".set\tpop\n\t"
+	".endm");
+
+#define local_irq_save(x)						\
+__asm__ __volatile__(							\
+	"local_irq_save\t%0"						\
+	: "=r" (x)							\
+	: /* no inputs */						\
+	: "memory")
+
+__asm__ (
+	".macro\tlocal_irq_restore flags\n\t"
+	".set\tnoreorder\n\t"
+	".set\tnoat\n\t"
+	"mfc0\t$1, $12\n\t"
+	"andi\t\\flags, 1\n\t"
+	"ori\t$1, 1\n\t"
+	"xori\t$1, 1\n\t"
+	"or\t\\flags, $1\n\t"
+	"mtc0\t\\flags, $12\n\t"
+	"irq_disable_hazard\n\t"
+	".set\tat\n\t"
+	".set\treorder\n\t"
+	".endm");
+
+#define local_irq_restore(flags)					\
+do {									\
+	unsigned long __tmp1;						\
+									\
+	__asm__ __volatile__(						\
+		"local_irq_restore\t%0"					\
+		: "=r" (__tmp1)						\
+		: "0" (flags)						\
+		: "memory");						\
+} while(0)
+
+#define irqs_disabled()							\
+({									\
+	unsigned long flags;						\
+	local_save_flags(flags);					\
+	!(flags & 1);							\
+})
+
+#endif /* _ASM_INTERRUPT_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index c6bd278c5ea0..6f7142059080 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -11,6 +11,7 @@
 #define _ASM_IO_H
 
 #include <linux/config.h>
+#include <linux/compiler.h>
 #include <linux/types.h>
 
 #include <asm/addrspace.h>
@@ -169,9 +170,9 @@ extern unsigned long isa_slot_offset;
 #define page_to_phys(page)	((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 
 extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags);
-extern void __iounmap(void *addr);
+extern void __iounmap(volatile void __iomem *addr);
 
-static inline void * __ioremap_mode(unsigned long offset, unsigned long size,
+static inline void * __ioremap_mode(phys_t offset, unsigned long size,
 	unsigned long flags)
 {
 	if (cpu_has_64bit_addresses) {
@@ -236,7 +237,7 @@ static inline void * __ioremap_mode(unsigned long offset, unsigned long size,
 #define ioremap_uncached_accelerated(offset, size)			\
 	__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
 
-static inline void iounmap(void *addr)
+static inline void iounmap(volatile void __iomem *addr)
 {
 	if (cpu_has_64bits)
 		return;
@@ -244,9 +245,12 @@ static inline void iounmap(void *addr)
 	__iounmap(addr);
 }
 
-#define __raw_readb(addr)	(*(volatile unsigned char *)(addr))
-#define __raw_readw(addr)	(*(volatile unsigned short *)(addr))
-#define __raw_readl(addr)	(*(volatile unsigned int *)(addr))
+#define __raw_readb(addr)						\
+	(*(volatile unsigned char *) __swizzle_addr_b((unsigned long)(addr)))
+#define __raw_readw(addr)						\
+	(*(volatile unsigned short *) __swizzle_addr_w((unsigned long)(addr)))
+#define __raw_readl(addr)						\
+	(*(volatile unsigned int *) __swizzle_addr_l((unsigned long)(addr)))
 #ifdef CONFIG_MIPS32
 #define ____raw_readq(addr)						\
 ({									\
@@ -259,7 +263,7 @@ static inline void iounmap(void *addr)
 		"	sll	%L0, %L0, 0			\n"	\
 		"	.set	mips0				\n"	\
 		: "=r" (__res)						\
-		: "r" (addr));						\
+		: "r" (__swizzle_addr_q((unsigned long)(addr))));	\
 	__res;								\
 })
 #define __raw_readq(addr)						\
@@ -274,7 +278,8 @@ static inline void iounmap(void *addr)
 })
 #endif
 #ifdef CONFIG_MIPS64
-#define ____raw_readq(addr)	(*(volatile unsigned long *)(addr))
+#define ____raw_readq(addr)						\
+	(*(volatile unsigned long *)__swizzle_addr_q((unsigned long)(addr)))
 #define __raw_readq(addr)	____raw_readq(addr)
 #endif
 
@@ -287,16 +292,24 @@ static inline void iounmap(void *addr)
 #define readl_relaxed(addr)	readl(addr)
 #define readq_relaxed(addr)	readq(addr)
 
-#define __raw_writeb(b,addr)	((*(volatile unsigned char *)(addr)) = (b))
-#define __raw_writew(w,addr)	((*(volatile unsigned short *)(addr)) = (w))
-#define __raw_writel(l,addr)	((*(volatile unsigned int *)(addr)) = (l))
+#define __raw_writeb(b,addr)						\
+do {									\
+	((*(volatile unsigned char *)__swizzle_addr_b((unsigned long)(addr))) = (b));	\
+} while (0)
 
-/* Depends on MIPS III instruction set */
-#define mmiowb() asm volatile ("sync" ::: "memory")
+#define __raw_writew(w,addr)						\
+do {									\
+	((*(volatile unsigned short *)__swizzle_addr_w((unsigned long)(addr))) = (w));	\
+} while (0)
+
+#define __raw_writel(l,addr)						\
+do {									\
+	((*(volatile unsigned int *)__swizzle_addr_l((unsigned long)(addr))) = (l));	\
+} while (0)
 
 #ifdef CONFIG_MIPS32
-#define ____raw_writeq(val,addr)						\
-({									\
+#define ____raw_writeq(val,addr)					\
+do {									\
 	u64 __tmp;							\
 									\
 	__asm__ __volatile__ (						\
@@ -308,19 +321,25 @@ static inline void iounmap(void *addr)
 		"	sd	%L0, (%2)			\n"	\
 		"	.set	mips0				\n"	\
 		: "=r" (__tmp)						\
-		: "0" ((unsigned long long)val), "r" (addr));		\
-})
+		: "0" ((unsigned long long)val),			\
+		  "r" (__swizzle_addr_q((unsigned long)(addr))));	\
+} while (0)
+
 #define __raw_writeq(val,addr)						\
-({									\
+do {									\
 	unsigned long __flags;						\
 									\
 	local_irq_save(__flags);					\
 	____raw_writeq(val, addr);					\
 	local_irq_restore(__flags);					\
-})
+} while (0)
 #endif
 #ifdef CONFIG_MIPS64
-#define ____raw_writeq(q,addr)	((*(volatile unsigned long *)(addr)) = (q))
+#define ____raw_writeq(q,addr)						\
+do {									\
+	*(volatile unsigned long *)__swizzle_addr_q((unsigned long)(addr)) = (q);	\
+} while (0)
+
 #define __raw_writeq(q,addr)	____raw_writeq(q, addr)
 #endif
 
@@ -329,6 +348,9 @@ static inline void iounmap(void *addr)
 #define writel(l,addr)		__raw_writel(__ioswab32(l),(addr))
 #define writeq(q,addr)		__raw_writeq(__ioswab64(q),(addr))
 
+/* Depends on MIPS II instruction set */
+#define mmiowb() asm volatile ("sync" ::: "memory")
+
 #define memset_io(a,b,c)	memset((void *)(a),(b),(c))
 #define memcpy_fromio(a,b,c)	memcpy((a),(void *)(b),(c))
 #define memcpy_toio(a,b,c)	memcpy((void *)(a),(b),(c))
diff --git a/include/asm-mips/ip32/crime.h b/include/asm-mips/ip32/crime.h
index 8caae23e183d..556843a9910b 100644
--- a/include/asm-mips/ip32/crime.h
+++ b/include/asm-mips/ip32/crime.h
@@ -1,5 +1,6 @@
 /*
- * Definitions for the SGI O2 Crime chip.
+ * Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory
+ * Engine)
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -11,178 +12,116 @@
 #ifndef __ASM_CRIME_H__
 #define __ASM_CRIME_H__
 
-#include <asm/addrspace.h>
-#include <asm/io.h>
-
 /*
  * Address map
  */
 #define CRIME_BASE	0x14000000	/* physical */
 
-extern void *sgi_crime;
-
-static inline uint64_t crime_read(unsigned long offset)
-{
-        return readq(sgi_crime + offset);
-}
-static inline void crime_write(uint64_t val, unsigned long offset)
-{
-	writeq(val, sgi_crime + offset);
-}
-
 #undef BIT
-#define BIT(x) (1UL << (x))
-
-/* All CRIME registers are 64 bits */
-#define CRIME_ID		0x000
-
-#define CRIME_ID_MASK		0xff
-#define CRIME_ID_IDBITS		0xf0
-#define CRIME_ID_IDVALUE	0xa0
-#define CRIME_ID_REV		0x0f
-
-#define CRIME_REV_PETTY		0x00
-#define CRIME_REV_11		0x11
-#define CRIME_REV_13		0x13
-#define CRIME_REV_14		0x14
-
-#define CRIME_CONTROL		0x008
-#define CRIME_CONTROL_MASK	0x3fff
-
-/* CRIME_CONTROL register bits */
+#define BIT(x)	(1UL << (x))
+
+struct sgi_crime {
+	volatile unsigned long id;
+#define CRIME_ID_MASK			0xff
+#define CRIME_ID_IDBITS			0xf0
+#define CRIME_ID_IDVALUE		0xa0
+#define CRIME_ID_REV			0x0f
+#define CRIME_REV_PETTY			0x00
+#define CRIME_REV_11			0x11
+#define CRIME_REV_13			0x13
+#define CRIME_REV_14			0x14
+
+	volatile unsigned long control;
+#define CRIME_CONTROL_MASK		0x3fff
 #define CRIME_CONTROL_TRITON_SYSADC	0x2000
 #define CRIME_CONTROL_CRIME_SYSADC	0x1000
 #define CRIME_CONTROL_HARD_RESET	0x0800
 #define CRIME_CONTROL_SOFT_RESET	0x0400
 #define CRIME_CONTROL_DOG_ENA		0x0200
 #define CRIME_CONTROL_ENDIANESS		0x0100
-
 #define CRIME_CONTROL_ENDIAN_BIG	0x0100
 #define CRIME_CONTROL_ENDIAN_LITTLE	0x0000
-
 #define CRIME_CONTROL_CQUEUE_HWM	0x000f
 #define CRIME_CONTROL_CQUEUE_SHFT	0
 #define CRIME_CONTROL_WBUF_HWM		0x00f0
 #define CRIME_CONTROL_WBUF_SHFT		8
 
-#define CRIME_INT_STAT			0x010
-#define CRIME_INT_MASK			0x018
-#define CRIME_SOFT_INT			0x020
-#define CRIME_HARD_INT			0x028
-
-/* Bits in CRIME_INT_XXX and CRIME_HARD_INT */
-#define MACE_VID_IN1_INT		BIT (0)
-#define MACE_VID_IN2_INT		BIT (1)
-#define MACE_VID_OUT_INT		BIT (2)
-#define MACE_ETHERNET_INT		BIT (3)
-#define MACE_SUPERIO_INT		BIT (4)
-#define MACE_MISC_INT			BIT (5)
-#define MACE_AUDIO_INT			BIT (6)
-#define MACE_PCI_BRIDGE_INT		BIT (7)
-#define MACEPCI_SCSI0_INT		BIT (8)
-#define MACEPCI_SCSI1_INT		BIT (9)
-#define MACEPCI_SLOT0_INT		BIT (10)
-#define MACEPCI_SLOT1_INT		BIT (11)
-#define MACEPCI_SLOT2_INT		BIT (12)
-#define MACEPCI_SHARED0_INT		BIT (13)
-#define MACEPCI_SHARED1_INT		BIT (14)
-#define MACEPCI_SHARED2_INT		BIT (15)
-#define CRIME_GBE0_INT			BIT (16)
-#define CRIME_GBE1_INT			BIT (17)
-#define CRIME_GBE2_INT			BIT (18)
-#define CRIME_GBE3_INT			BIT (19)
-#define CRIME_CPUERR_INT		BIT (20)
-#define CRIME_MEMERR_INT		BIT (21)
-#define CRIME_RE_EMPTY_E_INT		BIT (22)
-#define CRIME_RE_FULL_E_INT		BIT (23)
-#define CRIME_RE_IDLE_E_INT		BIT (24)
-#define CRIME_RE_EMPTY_L_INT		BIT (25)
-#define CRIME_RE_FULL_L_INT		BIT (26)
-#define CRIME_RE_IDLE_L_INT    		BIT (27)
-#define CRIME_SOFT0_INT			BIT (28)
-#define CRIME_SOFT1_INT			BIT (29)
-#define CRIME_SOFT2_INT			BIT (30)
+	volatile unsigned long istat;
+	volatile unsigned long imask;
+	volatile unsigned long soft_int;
+	volatile unsigned long hard_int;
+#define MACE_VID_IN1_INT		BIT(0)
+#define MACE_VID_IN2_INT		BIT(1)
+#define MACE_VID_OUT_INT		BIT(2)
+#define MACE_ETHERNET_INT		BIT(3)
+#define MACE_SUPERIO_INT		BIT(4)
+#define MACE_MISC_INT			BIT(5)
+#define MACE_AUDIO_INT			BIT(6)
+#define MACE_PCI_BRIDGE_INT		BIT(7)
+#define MACEPCI_SCSI0_INT		BIT(8)
+#define MACEPCI_SCSI1_INT		BIT(9)
+#define MACEPCI_SLOT0_INT		BIT(10)
+#define MACEPCI_SLOT1_INT		BIT(11)
+#define MACEPCI_SLOT2_INT		BIT(12)
+#define MACEPCI_SHARED0_INT		BIT(13)
+#define MACEPCI_SHARED1_INT		BIT(14)
+#define MACEPCI_SHARED2_INT		BIT(15)
+#define CRIME_GBE0_INT			BIT(16)
+#define CRIME_GBE1_INT			BIT(17)
+#define CRIME_GBE2_INT			BIT(18)
+#define CRIME_GBE3_INT			BIT(19)
+#define CRIME_CPUERR_INT		BIT(20)
+#define CRIME_MEMERR_INT		BIT(21)
+#define CRIME_RE_EMPTY_E_INT		BIT(22)
+#define CRIME_RE_FULL_E_INT		BIT(23)
+#define CRIME_RE_IDLE_E_INT		BIT(24)
+#define CRIME_RE_EMPTY_L_INT		BIT(25)
+#define CRIME_RE_FULL_L_INT		BIT(26)
+#define CRIME_RE_IDLE_L_INT    		BIT(27)
+#define CRIME_SOFT0_INT			BIT(28)
+#define CRIME_SOFT1_INT			BIT(29)
+#define CRIME_SOFT2_INT			BIT(30)
 #define CRIME_SYSCORERR_INT		CRIME_SOFT2_INT
-#define CRIME_VICE_INT			BIT (31)
-
+#define CRIME_VICE_INT			BIT(31)
 /* Masks for deciding who handles the interrupt */
 #define CRIME_MACE_INT_MASK		0x8f
 #define CRIME_MACEISA_INT_MASK		0x70
 #define CRIME_MACEPCI_INT_MASK		0xff00
 #define CRIME_CRIME_INT_MASK		0xffff0000
 
-#define CRIME_DOG			0x030
-#define CRIME_DOG_MASK			0x001fffff
-
-/* CRIME_DOG register bits */
+	volatile unsigned long watchdog;
 #define CRIME_DOG_POWER_ON_RESET	0x00010000
 #define CRIME_DOG_WARM_RESET		0x00080000
 #define CRIME_DOG_TIMEOUT		(CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
 #define CRIME_DOG_VALUE			0x00007fff
 
-#define CRIME_TIMER			0x038
-#define CRIME_TIMER_MASK		0x0000ffffffffffff
-
+	volatile unsigned long timer;
 #define CRIME_MASTER_FREQ		66666500	/* Crime upcounter frequency */
 #define CRIME_NS_PER_TICK		15		/* for delay_calibrate */
 
-#define CRIME_CPU_ERROR_ADDR		0x040
+	volatile unsigned long cpu_error_addr;
 #define CRIME_CPU_ERROR_ADDR_MASK	0x3ffffffff
 
-#define CRIME_CPU_ERROR_STAT		0x048
-/* REV_PETTY only! */
-#define CRIME_CPU_ERROR_ENA		0x050
-
-/*
- * bit definitions for CRIME/VICE error status and enable registers
- */
-#define CRIME_CPU_ERROR_MASK           0x7	/* cpu error stat is 3 bits */
-#define CRIME_CPU_ERROR_CPU_ILL_ADDR   0x4
-#define CRIME_CPU_ERROR_VICE_WRT_PRTY  0x2
-#define CRIME_CPU_ERROR_CPU_WRT_PRTY   0x1
+	volatile unsigned long cpu_error_stat;
+#define CRIME_CPU_ERROR_MASK		0x7		/* cpu error stat is 3 bits */
+#define CRIME_CPU_ERROR_CPU_ILL_ADDR	0x4
+#define CRIME_CPU_ERROR_VICE_WRT_PRTY	0x2
+#define CRIME_CPU_ERROR_CPU_WRT_PRTY	0x1
 
-/*
- * these are the definitions for the error status/enable  register in
- * petty crime.  Note that the enable register does not exist in crime
- * rev 1 and above.
- */
-#define CRIME_CPU_ERROR_MASK_REV0		0x3ff	/* cpu error stat is 9 bits */
-#define CRIME_CPU_ERROR_CPU_INV_ADDR_RD		0x200
-#define CRIME_CPU_ERROR_VICE_II			0x100
-#define CRIME_CPU_ERROR_VICE_SYSAD		0x80
-#define CRIME_CPU_ERROR_VICE_SYSCMD		0x40
-#define CRIME_CPU_ERROR_VICE_INV_ADDR		0x20
-#define CRIME_CPU_ERROR_CPU_II			0x10
-#define CRIME_CPU_ERROR_CPU_SYSAD		0x8
-#define CRIME_CPU_ERROR_CPU_SYSCMD		0x4
-#define CRIME_CPU_ERROR_CPU_INV_ADDR_WR		0x2
-#define CRIME_CPU_ERROR_CPU_INV_REG_ADDR	0x1
-
-#define CRIME_VICE_ERROR_ADDR		0x058
-#define CRIME_VICE_ERROR_ADDR_MASK	0x3fffffff
-
-#define CRIME_MEM_CONTROL		0x200
-#define CRIME_MEM_CONTROL_MASK		0x3	/* 25 cent register */
-#define CRIME_MEM_CONTROL_ECC_ENA	0x1
-#define CRIME_MEM_CONTROL_USE_ECC_REPL	0x2
+	unsigned long _pad0[54];
 
-/*
- * macros for CRIME memory bank control registers.
- */
-#define CRIME_MEM_BANK_CONTROL(__bank)		(0x208 + ((__bank) << 3))
-#define CRIME_MEM_BANK_CONTROL_MASK		0x11f /* 9 bits 7:5 reserved */
+	volatile unsigned long mc_ctrl;
+	volatile unsigned long bank_ctrl[8];
+#define CRIME_MEM_BANK_CONTROL_MASK		0x11f	/* 9 bits 7:5 reserved */
 #define CRIME_MEM_BANK_CONTROL_ADDR		0x01f
 #define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE	0x100
 #define CRIME_MAXBANKS				8
 
-#define CRIME_MEM_REFRESH_COUNTER	0x248
-#define CRIME_MEM_REFRESH_COUNTER_MASK	0x7ff	
+	volatile unsigned long mem_ref_counter;
+#define CRIME_MEM_REF_COUNTER_MASK	0x3ff		/* 10bit */
 
-/*
- * CRIME Memory error status register bit definitions
- */
-#define CRIME_MEM_ERROR_STAT		0x250
-#define CRIME_MEM_ERROR_STAT_MASK       0x0ff7ffff    /* 28-bit register */
+	volatile unsigned long mem_error_stat;
+#define CRIME_MEM_ERROR_STAT_MASK       0x0ff7ffff	/* 28-bit register */
 #define CRIME_MEM_ERROR_MACE_ID		0x0000007f
 #define CRIME_MEM_ERROR_MACE_ACCESS	0x00000080
 #define CRIME_MEM_ERROR_RE_ID		0x00007f00
@@ -200,18 +139,21 @@ static inline void crime_write(uint64_t val, unsigned long offset)
 #define CRIME_MEM_ERROR_INV		0x0e000000
 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RD	0x02000000
 #define CRIME_MEM_ERROR_INV_MEM_ADDR_WR	0x04000000
-#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW	0x08000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
 
-#define CRIME_MEM_ERROR_ADDR		0x258
+	volatile unsigned long mem_error_addr;
 #define CRIME_MEM_ERROR_ADDR_MASK	0x3fffffff
 
-#define CRIME_MEM_ERROR_ECC_SYN		0x260
+	volatile unsigned long mem_ecc_syn;
 #define CRIME_MEM_ERROR_ECC_SYN_MASK	0xffffffff
 
-#define CRIME_MEM_ERROR_ECC_CHK		0x268
-#define CRIME_MEM_ERROR_ECC_CHK_MASK    0xffffffff
+	volatile unsigned long mem_ecc_chk;
+#define CRIME_MEM_ERROR_ECC_CHK_MASK	0xffffffff
 
-#define CRIME_MEM_ERROR_ECC_REPL	0x270
+	volatile unsigned long mem_ecc_repl;
 #define CRIME_MEM_ERROR_ECC_REPL_MASK	0xffffffff
+};
+
+extern struct sgi_crime *crime;
 
 #endif /* __ASM_CRIME_H__ */
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
index 255e9b2b87f5..2b7b0fdeac19 100644
--- a/include/asm-mips/ip32/mace.h
+++ b/include/asm-mips/ip32/mace.h
@@ -12,41 +12,13 @@
 #ifndef __ASM_MACE_H__
 #define __ASM_MACE_H__
 
-#include <linux/config.h>
-#include <asm/io.h>
-
 /*
  * Address map
  */
 #define MACE_BASE	0x1f000000	/* physical */
 
 #undef BIT
-#define BIT(x) (1ULL << (x))
-
-#ifdef CONFIG_MIPS32
-typedef struct {
-	volatile unsigned long long reg;
-} mace64_t;
-
-typedef struct {
-	unsigned long pad;
-	volatile unsigned long reg;
-} mace32_t;
-#endif
-#ifdef CONFIG_MIPS64
-typedef struct {
-	volatile unsigned long reg;
-} mace64_t;
-
-typedef struct {
-	volatile unsigned long reg;
-} mace32_t;
-#endif
-
-#define mace_read(r)	\
-	(sizeof(r.reg) == 4 ? readl(&r.reg) : readq(&r.reg))
-#define mace_write(v,r)	\
-	(sizeof(r.reg) == 4 ? writel(v,&r.reg) : writeq(v,&r.reg))
+#define BIT(x) (1UL << (x))
 
 /*
  * PCI interface
@@ -119,48 +91,43 @@ struct mace_pci {
  * Video interface
  */
 struct mace_video {
-	mace32_t xxx;	/* later... */
+	unsigned long xxx;	/* later... */
 };
 
 /* 
  * Ethernet interface
  */
 struct mace_ethernet {
-	mace32_t mac_ctrl;
-	mace32_t int_stat;
-	mace32_t dma_ctrl;
-	mace32_t timer;
-	mace32_t tx_int_al;
-	mace32_t rx_int_al;
-	mace32_t tx_info;
-	mace32_t tx_info_al;
-	mace32_t rx_buff;
-	mace32_t rx_buff_al1;
-	mace32_t rx_buff_al2;
-	mace64_t diag;
-	mace32_t phy_data;
-	mace32_t phy_regs;
-	mace32_t phy_trans_go;
-	mace32_t backoff_seed;
+	volatile unsigned long mac_ctrl;
+	volatile unsigned long int_stat;
+	volatile unsigned long dma_ctrl;
+	volatile unsigned long timer;
+	volatile unsigned long tx_int_al;
+	volatile unsigned long rx_int_al;
+	volatile unsigned long tx_info;
+	volatile unsigned long tx_info_al;
+	volatile unsigned long rx_buff;
+	volatile unsigned long rx_buff_al1;
+	volatile unsigned long rx_buff_al2;
+	volatile unsigned long diag;
+	volatile unsigned long phy_data;
+	volatile unsigned long phy_regs;
+	volatile unsigned long phy_trans_go;
+	volatile unsigned long backoff_seed;
 	/*===================================*/
-	mace64_t imq_reserved[4];
-	mace64_t mac_addr;
-	mace64_t mac_addr2;
-	mace64_t mcast_filter;
-	mace32_t tx_ring_base;
+	volatile unsigned long imq_reserved[4];
+	volatile unsigned long mac_addr;
+	volatile unsigned long mac_addr2;
+	volatile unsigned long mcast_filter;
+	volatile unsigned long tx_ring_base;
 	/* Following are read-only registers for debugging */
-	mace64_t tx_pkt1_hdr;
-	mace64_t tx_pkt1_ptr[3];
-	mace64_t tx_pkt2_hdr;
-	mace64_t tx_pkt2_ptr[3];
+	volatile unsigned long tx_pkt1_hdr;
+	volatile unsigned long tx_pkt1_ptr[3];
+	volatile unsigned long tx_pkt2_hdr;
+	volatile unsigned long tx_pkt2_ptr[3];
 	/*===================================*/
-	mace32_t rx_fifo;
+	volatile unsigned long rx_fifo;
 };
-#define mace_eth_read(r)	\
-	mace_read(mace->eth.r)
-#define mace_eth_write(v,r)	\
-	mace_write(v,mace->eth.r)
-
 
 /* 
  * Peripherals
@@ -168,28 +135,24 @@ struct mace_ethernet {
 
 /* Audio registers */
 struct mace_audio {
-	mace32_t control;
-	mace32_t codec_control;		/* codec status control */
-	mace32_t codec_mask;		/* codec status input mask */
-	mace32_t codec_read;		/* codec status read data */
+	volatile unsigned long control;
+	volatile unsigned long codec_control;		/* codec status control */
+	volatile unsigned long codec_mask;		/* codec status input mask */
+	volatile unsigned long codec_read;		/* codec status read data */
 	struct {
-		mace32_t control;	/* channel control */
-		mace32_t read_ptr;	/* channel read pointer */
-		mace32_t write_ptr;	/* channel write pointer */
-		mace32_t depth;		/* channel depth */
-	} channel[3];
+		volatile unsigned long control;		/* channel control */
+		volatile unsigned long read_ptr;	/* channel read pointer */
+		volatile unsigned long write_ptr;	/* channel write pointer */
+		volatile unsigned long depth;		/* channel depth */
+	} chan[3];
 };
-#define mace_perif_audio_read(r)	\
-	mace_read(mace->perif.audio.r)
-#define mace_perif_audio_write(v,r)	\
-	mace_write(v,mace->perif.audio.r)
 
 /* ISA Control and DMA registers */
 struct mace_isactrl {
-	mace32_t ringbase;
+	volatile unsigned long ringbase;
 #define MACEISA_RINGBUFFERS_SIZE	(8 * 4096)
 
-	mace32_t misc;
+	volatile unsigned long misc;
 #define MACEISA_FLASH_WE		BIT(0)	/* 1=> Enable FLASH writes */
 #define MACEISA_PWD_CLEAR		BIT(1)	/* 1=> PWD CLEAR jumper detected */
 #define MACEISA_NIC_DEASSERT		BIT(2)
@@ -198,8 +161,8 @@ struct mace_isactrl {
 #define MACEISA_LED_GREEN		BIT(5)	/* 0=> Illuminate green LED */
 #define MACEISA_DP_RAM_ENABLE		BIT(6)
 
-	mace32_t istat;
-	mace32_t imask;
+	volatile unsigned long istat;
+	volatile unsigned long imask;
 #define MACEISA_AUDIO_SW_INT		BIT(0)
 #define MACEISA_AUDIO_SC_INT		BIT(1)
 #define MACEISA_AUDIO1_DMAT_INT		BIT(2)
@@ -233,22 +196,18 @@ struct mace_isactrl {
 #define MACEISA_SERIAL2_RDMAT_INT	BIT(30)
 #define MACEISA_SERIAL2_RDMAOR_INT	BIT(31)
 
-	mace64_t _pad[0x2000/8 - 4];
+	volatile unsigned long _pad[0x2000/8 - 4];
 
-	mace64_t dp_ram[0x400];
+	volatile unsigned long dp_ram[0x400];
 };
-#define mace_perif_ctrl_read(r)		\
-	mace_read(mace->perif.ctrl.r)
-#define mace_perif_ctrl_write(v,r)	\
-	mace_write(v,mace->perif.ctrl.r)
 
 /* Keyboard & Mouse registers
  * -> drivers/input/serio/maceps2.c */
 struct mace_ps2port {
-	mace32_t tx;
-	mace32_t rx;
-	mace32_t control;
-	mace32_t status;
+	volatile unsigned long tx;
+	volatile unsigned long rx;
+	volatile unsigned long control;
+	volatile unsigned long status;
 };
 
 struct mace_ps2 {
@@ -259,20 +218,20 @@ struct mace_ps2 {
 /* I2C registers
  * -> drivers/i2c/algos/i2c-algo-sgi.c */
 struct mace_i2c {
-	mace32_t config;
+	volatile unsigned long config;
 #define MACEI2C_RESET           BIT(0)
 #define MACEI2C_FAST            BIT(1)
 #define MACEI2C_DATA_OVERRIDE   BIT(2)
 #define MACEI2C_CLOCK_OVERRIDE  BIT(3)
 #define MACEI2C_DATA_STATUS     BIT(4)
 #define MACEI2C_CLOCK_STATUS    BIT(5)
-	mace32_t control;
-	mace32_t data;
+	volatile unsigned long control;
+	volatile unsigned long data;
 };
 
 /* Timer registers */
 typedef union {
-	mace64_t ust_msc;
+	volatile unsigned long ust_msc;
 	struct reg {
 		volatile unsigned int ust;
 		volatile unsigned int msc;
@@ -280,12 +239,12 @@ typedef union {
 } timer_reg;
 
 struct mace_timers {
-	mace32_t ust;
+	volatile unsigned long ust;
 #define MACE_UST_PERIOD_NS	960
 
-	mace32_t compare1;
-	mace32_t compare2;
-	mace32_t compare3;
+	volatile unsigned long compare1;
+	volatile unsigned long compare2;
+	volatile unsigned long compare3;
 
 	timer_reg audio_in;
 	timer_reg audio_out1;
@@ -326,7 +285,7 @@ struct mace_ecp1284 {	/* later... */
 
 /* Serial port */
 struct mace_serial {
-	mace64_t xxx;	/* later... */
+	volatile unsigned long xxx;	/* later... */
 };
 
 struct mace_isa {
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
index d9667a8fbbfb..b90b11d0b886 100644
--- a/include/asm-mips/irq.h
+++ b/include/asm-mips/irq.h
@@ -22,14 +22,32 @@ static inline int irq_canonicalize(int irq)
 #define irq_canonicalize(irq) (irq)	/* Sane hardware, sane code ... */
 #endif
 
-extern void disable_irq(unsigned int);
-extern void disable_irq_nosync(unsigned int);
-extern void enable_irq(unsigned int);
-
 struct pt_regs;
-extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
 
-extern void init_generic_irq(void);
+#ifdef CONFIG_PREEMPT
+
+extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs);
+
+#else
+
+/*
+ * do_IRQ handles all normal device IRQ's (the special
+ * SMP cross-CPU interrupts have their own specific
+ * handlers).
+ *
+ * Ideally there should be away to get this into kernel/irq/handle.c to
+ * avoid the overhead of a call for just a tiny function ...
+ */
+#define do_IRQ(irq, regs)						\
+do {									\
+	irq_enter();							\
+	__do_IRQ((irq), (regs));					\
+	irq_exit();							\
+} while (0)
+
+#endif
+
+extern void arch_init_irq(void);
 
 struct irqaction;
 int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
diff --git a/include/asm-mips/jazz.h b/include/asm-mips/jazz.h
index 4e62ee69e219..81cbf004fd13 100644
--- a/include/asm-mips/jazz.h
+++ b/include/asm-mips/jazz.h
@@ -107,6 +107,8 @@ typedef struct {
 	unsigned char command;
 } jazz_keyboard_hardware;
 
+#define jazz_kh ((keyboard_hardware *) JAZZ_KEYBOARD_ADDRESS)
+
 typedef struct {
 	unsigned char pad0[3];
 	unsigned char data;
diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h
index 8799f921af96..64f3b1aa79e4 100644
--- a/include/asm-mips/mach-atlas/mc146818rtc.h
+++ b/include/asm-mips/mach-atlas/mc146818rtc.h
@@ -29,7 +29,7 @@
 #define RTC_EXTENT	16
 #define RTC_IRQ		ATLASINT_RTC
 
-#if CONFIG_CPU_LITTLE_ENDIAN
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define ATLAS_RTC_PORT(x) (RTC_PORT(x) + 0)
 #else
 #define ATLAS_RTC_PORT(x) (RTC_PORT(x) + 3)
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 326f266968ab..51870bec13a4 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -161,6 +161,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #endif
 
 /* SDRAM Controller */
+#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
 #define MEM_SDMODE0                0xB4000000
 #define MEM_SDMODE1                0xB4000004
 #define MEM_SDMODE2                0xB4000008
@@ -179,6 +180,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 
 #define MEM_SDSLEEP                0xB4000030
 #define MEM_SDSMCKE                0xB4000034
+#endif
 
 /* Static Bus Controller */
 #define MEM_STCFG0                 0xB4001000
@@ -197,7 +199,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define MEM_STTIME3                0xB4001034
 #define MEM_STADDR3                0xB4001038
 
-#ifdef CONFIG_SOC_AU1550
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
 #define MEM_STNDCTL                0xB4001100
 #define MEM_STSTAT                 0xB4001104
 
@@ -292,21 +294,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define INTC_INT_HIGH_AND_LOW_LEVEL    0x7
 
 /* Interrupt Numbers */
+/* Au1000 */
+#ifdef CONFIG_SOC_AU1000
 #define AU1000_UART0_INT          0
 #define AU1000_UART1_INT          1 /* au1000 */
 #define AU1000_UART2_INT          2 /* au1000 */
-
-#define AU1000_PCI_INTA           1 /* au1500 */
-#define AU1000_PCI_INTB           2 /* au1500 */
-
 #define AU1000_UART3_INT          3
-
 #define AU1000_SSI0_INT           4 /* au1000 */
 #define AU1000_SSI1_INT           5 /* au1000 */
-
-#define AU1000_PCI_INTC           4 /* au1500 */
-#define AU1000_PCI_INTD           5 /* au1500 */
-
 #define AU1000_DMA_INT_BASE       6
 #define AU1000_TOY_INT            14
 #define AU1000_TOY_MATCH0_INT     15
@@ -324,11 +319,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1000_ACSYNC_INT         27
 #define AU1000_MAC0_DMA_INT       28
 #define AU1000_MAC1_DMA_INT       29
-#define AU1000_ETH0_IRQ           AU1000_MAC0_DMA_INT
-#define AU1000_ETH1_IRQ           AU1000_MAC1_DMA_INT
 #define AU1000_I2S_UO_INT         30 /* au1000 */
 #define AU1000_AC97C_INT          31
-#define AU1000_LAST_INTC0_INT     AU1000_AC97C_INT
 #define AU1000_GPIO_0             32
 #define AU1000_GPIO_1             33
 #define AU1000_GPIO_2             34
@@ -345,8 +337,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1000_GPIO_13            45
 #define AU1000_GPIO_14            46
 #define AU1000_GPIO_15            47
-
-/* Au1000 only */
 #define AU1000_GPIO_16            48
 #define AU1000_GPIO_17            49
 #define AU1000_GPIO_18            50
@@ -364,7 +354,62 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1000_GPIO_30            62
 #define AU1000_GPIO_31            63
 
-/* Au1500 only */
+#define UART0_ADDR                0xB1100000
+#define UART1_ADDR                0xB1200000
+#define UART2_ADDR                0xB1300000
+#define UART3_ADDR                0xB1400000
+
+#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
+#define USB_HOST_CONFIG           0xB017fffc
+
+#define AU1000_ETH0_BASE      0xB0500000
+#define AU1000_ETH1_BASE      0xB0510000
+#define AU1000_MAC0_ENABLE       0xB0520000
+#define AU1000_MAC1_ENABLE       0xB0520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1000
+
+/* Au1500 */
+#ifdef CONFIG_SOC_AU1500
+#define AU1500_UART0_INT          0
+#define AU1000_PCI_INTA           1 /* au1500 */
+#define AU1000_PCI_INTB           2 /* au1500 */
+#define AU1500_UART3_INT          3
+#define AU1000_PCI_INTC           4 /* au1500 */
+#define AU1000_PCI_INTD           5 /* au1500 */
+#define AU1000_DMA_INT_BASE       6
+#define AU1000_TOY_INT            14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
+#define AU1500_PCI_ERR_INT        22
+#define AU1000_USB_DEV_REQ_INT    24
+#define AU1000_USB_DEV_SUS_INT    25
+#define AU1000_USB_HOST_INT       26
+#define AU1000_ACSYNC_INT         27
+#define AU1500_MAC0_DMA_INT       28
+#define AU1500_MAC1_DMA_INT       29
+#define AU1000_AC97C_INT          31
+#define AU1000_GPIO_0             32
+#define AU1000_GPIO_1             33
+#define AU1000_GPIO_2             34
+#define AU1000_GPIO_3             35
+#define AU1000_GPIO_4             36
+#define AU1000_GPIO_5             37
+#define AU1000_GPIO_6             38
+#define AU1000_GPIO_7             39
+#define AU1000_GPIO_8             40
+#define AU1000_GPIO_9             41
+#define AU1000_GPIO_10            42
+#define AU1000_GPIO_11            43
+#define AU1000_GPIO_12            44
+#define AU1000_GPIO_13            45
+#define AU1000_GPIO_14            46
+#define AU1000_GPIO_15            47
 #define AU1500_GPIO_200           48
 #define AU1500_GPIO_201           49
 #define AU1500_GPIO_202           50
@@ -382,14 +427,79 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1500_GPIO_207           62
 #define AU1500_GPIO_208_215       63
 
-#define AU1000_MAX_INTR           63
+#define UART0_ADDR                0xB1100000
+#define UART3_ADDR                0xB1400000
 
-#define AU1100_SD		2
+#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
+#define USB_HOST_CONFIG           0xB017fffc
+
+#define AU1500_ETH0_BASE	  0xB1500000
+#define AU1500_ETH1_BASE	  0xB1510000
+#define AU1500_MAC0_ENABLE       0xB1520000
+#define AU1500_MAC1_ENABLE       0xB1520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1500
+
+/* Au1100 */
+#ifdef CONFIG_SOC_AU1100
+#define AU1100_UART0_INT          0
+#define AU1100_UART1_INT          1
+#define AU1100_SD_INT             2
+#define AU1100_UART3_INT          3
+#define AU1000_SSI0_INT           4
+#define AU1000_SSI1_INT           5
+#define AU1000_DMA_INT_BASE       6
+#define AU1000_TOY_INT            14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
+#define AU1000_IRDA_TX_INT        22
+#define AU1000_IRDA_RX_INT        23
+#define AU1000_USB_DEV_REQ_INT    24
+#define AU1000_USB_DEV_SUS_INT    25
+#define AU1000_USB_HOST_INT       26
+#define AU1000_ACSYNC_INT         27
+#define AU1100_MAC0_DMA_INT       28
 #define	AU1100_GPIO_208_215	29
-// Seperate defines for AU1550 SOC
-#define AU1550_UART0_INT          AU1000_UART0_INT
-#define AU1550_PCI_INTA           AU1000_PCI_INTA
-#define AU1550_PCI_INTB           AU1000_PCI_INTB
+#define	AU1100_LCD_INT            30
+#define AU1000_AC97C_INT          31
+#define AU1000_GPIO_0             32
+#define AU1000_GPIO_1             33
+#define AU1000_GPIO_2             34
+#define AU1000_GPIO_3             35
+#define AU1000_GPIO_4             36
+#define AU1000_GPIO_5             37
+#define AU1000_GPIO_6             38
+#define AU1000_GPIO_7             39
+#define AU1000_GPIO_8             40
+#define AU1000_GPIO_9             41
+#define AU1000_GPIO_10            42
+#define AU1000_GPIO_11            43
+#define AU1000_GPIO_12            44
+#define AU1000_GPIO_13            45
+#define AU1000_GPIO_14            46
+#define AU1000_GPIO_15            47
+
+#define UART0_ADDR                0xB1100000
+#define UART1_ADDR                0xB1200000
+#define UART3_ADDR                0xB1400000
+
+#define USB_OHCI_BASE             0x10100000 // phys addr for ioremap
+#define USB_HOST_CONFIG           0xB017fffc
+
+#define AU1100_ETH0_BASE	  0xB0500000
+#define AU1100_MAC0_ENABLE       0xB0520000
+#define NUM_ETH_INTERFACES 1
+#endif // CONFIG_SOC_AU1100
+
+#ifdef CONFIG_SOC_AU1550
+#define AU1550_UART0_INT          0
+#define AU1550_PCI_INTA           1
+#define AU1550_PCI_INTB           2
 #define AU1550_DDMA_INT           3
 #define AU1550_CRYPTO_INT         4
 #define AU1550_PCI_INTC           5
@@ -413,11 +523,27 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1550_USB_DEV_REQ_INT    24
 #define AU1550_USB_DEV_SUS_INT    25
 #define AU1550_USB_HOST_INT       26
+#define AU1000_USB_DEV_REQ_INT    AU1550_USB_DEV_REQ_INT
+#define AU1000_USB_DEV_SUS_INT    AU1550_USB_DEV_SUS_INT
+#define AU1000_USB_HOST_INT       AU1550_USB_HOST_INT
 #define AU1550_MAC0_DMA_INT       27
 #define AU1550_MAC1_DMA_INT       28
-#define AU1550_ETH0_IRQ           AU1550_MAC0_DMA_INT
-#define AU1550_ETH1_IRQ           AU1550_MAC1_DMA_INT
-
+#define AU1000_GPIO_0             32
+#define AU1000_GPIO_1             33
+#define AU1000_GPIO_2             34
+#define AU1000_GPIO_3             35
+#define AU1000_GPIO_4             36
+#define AU1000_GPIO_5             37
+#define AU1000_GPIO_6             38
+#define AU1000_GPIO_7             39
+#define AU1000_GPIO_8             40
+#define AU1000_GPIO_9             41
+#define AU1000_GPIO_10            42
+#define AU1000_GPIO_11            43
+#define AU1000_GPIO_12            44
+#define AU1000_GPIO_13            45
+#define AU1000_GPIO_14            46
+#define AU1000_GPIO_15            47
 #define AU1550_GPIO_200           48
 #define AU1500_GPIO_201_205       49	// Logical or of GPIO201:205
 #define AU1500_GPIO_16            50
@@ -435,7 +561,101 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1500_GPIO_207           62
 #define AU1500_GPIO_208_218       63	// Logical or of GPIO208:218
 
-// REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE
+#define UART0_ADDR                0xB1100000
+#define UART1_ADDR                0xB1200000
+#define UART3_ADDR                0xB1400000
+
+#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap
+#define USB_HOST_CONFIG           0xB4027ffc
+
+#define AU1550_ETH0_BASE      0xB0500000
+#define AU1550_ETH1_BASE      0xB0510000
+#define AU1550_MAC0_ENABLE       0xB0520000
+#define AU1550_MAC1_ENABLE       0xB0520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1550
+
+#ifdef CONFIG_SOC_AU1200
+#define AU1200_UART0_INT          0
+#define AU1200_SWT_INT            1
+#define AU1200_SD_INT             2
+#define AU1200_DDMA_INT           3
+#define AU1200_MAE_BE_INT         4
+#define AU1200_GPIO_200           5
+#define AU1200_GPIO_201           6
+#define AU1200_GPIO_202           7
+#define AU1200_UART1_INT          8
+#define AU1200_MAE_FE_INT         9
+#define AU1200_PSC0_INT           10
+#define AU1200_PSC1_INT           11
+#define AU1200_AES_INT            12
+#define AU1200_CAMERA_INT         13
+#define AU1200_TOY_INT			  14
+#define AU1200_TOY_MATCH0_INT     15
+#define AU1200_TOY_MATCH1_INT     16
+#define AU1200_TOY_MATCH2_INT     17
+#define AU1200_RTC_INT            18
+#define AU1200_RTC_MATCH0_INT     19
+#define AU1200_RTC_MATCH1_INT     20
+#define AU1200_RTC_MATCH2_INT     21
+#define AU1200_NAND_INT           23
+#define AU1200_GPIO_204           24
+#define AU1200_GPIO_205           25
+#define AU1200_GPIO_206           26
+#define AU1200_GPIO_207           27
+#define AU1200_GPIO_208_215       28 // Logical OR of 208:215
+#define AU1200_USB_INT            29
+#define AU1200_LCD_INT            30
+#define AU1200_MAE_BOTH_INT       31
+#define AU1000_GPIO_0             32
+#define AU1000_GPIO_1             33
+#define AU1000_GPIO_2             34
+#define AU1000_GPIO_3             35
+#define AU1000_GPIO_4             36
+#define AU1000_GPIO_5             37
+#define AU1000_GPIO_6             38
+#define AU1000_GPIO_7             39
+#define AU1000_GPIO_8             40
+#define AU1000_GPIO_9             41
+#define AU1000_GPIO_10            42
+#define AU1000_GPIO_11            43
+#define AU1000_GPIO_12            44
+#define AU1000_GPIO_13            45
+#define AU1000_GPIO_14            46
+#define AU1000_GPIO_15            47
+#define AU1000_GPIO_16            48
+#define AU1000_GPIO_17            49
+#define AU1000_GPIO_18            50
+#define AU1000_GPIO_19            51
+#define AU1000_GPIO_20            52
+#define AU1000_GPIO_21            53
+#define AU1000_GPIO_22            54
+#define AU1000_GPIO_23            55
+#define AU1000_GPIO_24            56
+#define AU1000_GPIO_25            57
+#define AU1000_GPIO_26            58
+#define AU1000_GPIO_27            59
+#define AU1000_GPIO_28            60
+#define AU1000_GPIO_29            61
+#define AU1000_GPIO_30            62
+#define AU1000_GPIO_31            63
+
+#define UART0_ADDR                0xB1100000
+#define UART1_ADDR                0xB1200000
+
+#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap
+#define USB_HOST_CONFIG           0xB4027ffc
+
+// these are here for prototyping on au1550 (do not exist on au1200)
+#define AU1200_ETH0_BASE      0xB0500000
+#define AU1200_ETH1_BASE      0xB0510000
+#define AU1200_MAC0_ENABLE       0xB0520000
+#define AU1200_MAC1_ENABLE       0xB0520004
+#define NUM_ETH_INTERFACES 2
+#endif // CONFIG_SOC_AU1200
+
+#define AU1000_LAST_INTC0_INT     31
+#define AU1000_MAX_INTR           63
 
 
 /* Programmable Counters 0 and 1 */
@@ -509,16 +729,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
   #define I2S_CONTROL_CE        (1<<0)
 
 /* USB Host Controller */
-// We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address
-#if defined( CONFIG_SOC_AU1550 )
-#define USB_OHCI_BASE             0x14020000
-#define USB_OHCI_LEN              0x00100000
-#define USB_HOST_CONFIG           0xB4027ffc
-#else
-#define USB_OHCI_BASE             0x10100000
 #define USB_OHCI_LEN              0x00100000
-#define USB_HOST_CONFIG           0xB017fffc
-#endif
 
 /* USB Device Controller */
 #define USBD_EP0RD                0xB0200000
@@ -563,13 +774,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
   #define USBDEV_CE     (1<<0)
 
 /* Ethernet Controllers  */
-#define AU1000_ETH0_BASE          0xB0500000
-#define AU1000_ETH1_BASE          0xB0510000
-#define AU1500_ETH0_BASE	  0xB1500000
-#define AU1500_ETH1_BASE	  0xB1510000
-#define AU1100_ETH0_BASE	  0xB0500000
-#define AU1550_ETH0_BASE      0xB0500000
-#define AU1550_ETH1_BASE      0xB0510000
 
 /* 4 byte offsets from AU1000_ETH_BASE */
 #define MAC_CONTROL                     0x0
@@ -614,11 +818,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define MAC_VLAN2_TAG                  0x24
 
 /* Ethernet Controller Enable */
-#define AU1000_MAC0_ENABLE       0xB0520000
-#define AU1000_MAC1_ENABLE       0xB0520004
-#define AU1500_MAC0_ENABLE       0xB1520000
-#define AU1500_MAC1_ENABLE       0xB1520004
-#define AU1100_MAC0_ENABLE       0xB0520000
 
   #define MAC_EN_CLOCK_ENABLE         (1<<0)
   #define MAC_EN_RESET0               (1<<1)
@@ -702,10 +901,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 
 
 /* UARTS 0-3 */
-#define UART0_ADDR                0xB1100000
-#define UART1_ADDR                0xB1200000
-#define UART2_ADDR                0xB1300000
-#define UART3_ADDR                0xB1400000
 #define UART_BASE                 UART0_ADDR
 #define UART_DEBUG_BASE           UART3_ADDR
 
@@ -976,7 +1171,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
   #define SYS_PF_PSC1_S1		(1 << 1)
   #define SYS_PF_MUST_BE_SET		((1 << 5) | (1 << 2))
 
-
 #define SYS_TRIOUTRD              0xB1900100
 #define SYS_TRIOUTCLR             0xB1900100
 #define SYS_OUTPUTRD              0xB1900108
@@ -1134,12 +1328,12 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
  * addresses.  For PCI IO, it's simpler because we get to do the ioremap
  * ourselves and then adjust the device's resources.
  */
-#define Au1500_EXT_CFG            0x600000000
-#define Au1500_EXT_CFG_TYPE1      0x680000000
-#define Au1500_PCI_IO_START       0x500000000
-#define Au1500_PCI_IO_END         0x5000FFFFF
-#define Au1500_PCI_MEM_START      0x440000000
-#define Au1500_PCI_MEM_END        0x44FFFFFFF
+#define Au1500_EXT_CFG            0x600000000ULL
+#define Au1500_EXT_CFG_TYPE1      0x680000000ULL
+#define Au1500_PCI_IO_START       0x500000000ULL
+#define Au1500_PCI_IO_END         0x5000FFFFFULL
+#define Au1500_PCI_MEM_START      0x440000000ULL
+#define Au1500_PCI_MEM_END        0x44FFFFFFFULL
 
 #define PCI_IO_START    (Au1500_PCI_IO_START + 0x1000)
 #define PCI_IO_END      (Au1500_PCI_IO_END)
@@ -1148,7 +1342,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define PCI_FIRST_DEVFN (0<<3)
 #define PCI_LAST_DEVFN  (19<<3)
 
-#define IOPORT_RESOURCE_START 0x00001000 /* skip the legacy ide probing */
+#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
 #define IOPORT_RESOURCE_END   0xffffffff
 #define IOMEM_RESOURCE_START  0x10000000
 #define IOMEM_RESOURCE_END    0xffffffff
@@ -1194,11 +1388,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 
 #endif
 
-#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
-#define NUM_ETH_INTERFACES 2
-#elif defined(CONFIG_SOC_AU1100)
-#define NUM_ETH_INTERFACES 1
-#endif
 /* Processor information base on prid.
  * Copied from PowerPC.
  */
@@ -1208,11 +1397,10 @@ struct cpu_spec {
 	unsigned int	prid_value;
 
 	char		*cpu_name;
-	unsigned int	cpu_od;		/* Set Config[OD] */
-	unsigned int	cpu_bclk;	/* Enable BCLK switching */
+	unsigned char	cpu_od;		/* Set Config[OD] */
+	unsigned char	cpu_bclk;	/* Enable BCLK switching */
 };
 
 extern struct cpu_spec		cpu_specs[];
 extern struct cpu_spec		*cur_cpu_spec[];
-
 #endif
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
index 3b03b0b0a7e9..0812ea6b028c 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -29,6 +29,7 @@
 
 #ifdef CONFIG_MIPS_DB1550
 #define BCSR_KSEG1_ADDR 0xAF000000
+#define NAND_PHYS_ADDR  0x20000000
 #else
 #define BCSR_KSEG1_ADDR 0xAE000000
 #endif
@@ -130,15 +131,6 @@ typedef volatile struct
 #define SET_VCC_VPP(VCC, VPP, SLOT)\
 	((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
 
-/* MTD CONFIG OPTIONS */
-#if defined(CONFIG_MTD_DB1X00_BOOT) && defined(CONFIG_MTD_DB1X00_USER)
-#define DB1X00_BOTH_BANKS
-#elif defined(CONFIG_MTD_DB1X00_BOOT) && !defined(CONFIG_MTD_DB1X00_USER)
-#define DB1X00_BOOT_ONLY
-#elif !defined(CONFIG_MTD_DB1X00_BOOT) && defined(CONFIG_MTD_DB1X00_USER)
-#define DB1X00_USER_ONLY
-#endif
-
 /* SD controller macros */
 /*
  * Detect card.
@@ -182,5 +174,29 @@ typedef volatile struct
 		} \
 	} while (0)
 
+
+/* NAND defines */
+/* Timing values as described in databook, * ns value stripped of
+ * lower 2 bits.
+ * These defines are here rather than an SOC1550 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H			(18 >> 2)
+#define NAND_T_PUL			(30 >> 2)
+#define NAND_T_SU			(30 >> 2)
+#define NAND_T_WH			(30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT		0
+#define NAND_T_PUL_SHIFT	4
+#define NAND_T_SU_SHIFT		8
+#define NAND_T_WH_SHIFT		12
+
+#define NAND_TIMING	((NAND_T_H   & 0xF)	<< NAND_T_H_SHIFT)   | \
+			((NAND_T_PUL & 0xF)	<< NAND_T_PUL_SHIFT) | \
+			((NAND_T_SU  & 0xF)	<< NAND_T_SU_SHIFT)  | \
+			((NAND_T_WH  & 0xF)	<< NAND_T_WH_SHIFT)
+
 #endif /* __ASM_DB1X00_H */
 
diff --git a/include/asm-mips/mach-generic/floppy.h b/include/asm-mips/mach-generic/floppy.h
index d47601392f0f..682a5858f8d7 100644
--- a/include/asm-mips/mach-generic/floppy.h
+++ b/include/asm-mips/mach-generic/floppy.h
@@ -12,7 +12,6 @@
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/sched.h>
-#include <linux/kernel.h>
 #include <linux/linkage.h>
 #include <linux/types.h>
 #include <linux/mm.h>
diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
index fa2760afa51c..7cdd4649fff8 100644
--- a/include/asm-mips/mach-generic/ide.h
+++ b/include/asm-mips/mach-generic/ide.h
@@ -3,13 +3,18 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * IDE routines for typical pc-like legacy IDE configurations.
+ * Copyright (C) 1994-1996  Linus Torvalds & authors
  *
- * Copyright (C) 1998, 1999, 2001, 2003 by Ralf Baechle
+ * Copied from i386; many of the especially older MIPS or ISA-based platforms
+ * are basically identical.  Using this file probably implies i8259 PIC
+ * support in a system but the very least interrupt numbers 0 - 15 need to
+ * be put aside for legacy devices.
  */
 #ifndef __ASM_MACH_GENERIC_IDE_H
 #define __ASM_MACH_GENERIC_IDE_H
 
+#ifdef __KERNEL__
+
 #include <linux/config.h>
 
 #ifndef MAX_HWIFS
@@ -22,7 +27,7 @@
 
 #define IDE_ARCH_OBSOLETE_DEFAULTS
 
-static inline int ide_default_irq(unsigned long base)
+static __inline__ int ide_default_irq(unsigned long base)
 {
 	switch (base) {
 		case 0x1f0: return 14;
@@ -36,11 +41,11 @@ static inline int ide_default_irq(unsigned long base)
 	}
 }
 
-static inline unsigned long ide_default_io_base(int index)
+static __inline__ unsigned long ide_default_io_base(int index)
 {
 	switch (index) {
-		case 0: return 0x1f0;
-		case 1: return 0x170;
+		case 0:	return 0x1f0;
+		case 1:	return 0x170;
 		case 2: return 0x1e8;
 		case 3: return 0x168;
 		case 4: return 0x1e0;
@@ -59,4 +64,8 @@ static inline unsigned long ide_default_io_base(int index)
 #define ide_init_default_irq(base)	ide_default_irq(base)
 #endif
 
+#include <asm-generic/ide_iops.h>
+
+#endif /* __KERNEL__ */
+
 #endif /* __ASM_MACH_GENERIC_IDE_H */
diff --git a/include/asm-mips/mach-generic/mangle-port.h b/include/asm-mips/mach-generic/mangle-port.h
index ba82007a57a1..4a98d83b8ec7 100644
--- a/include/asm-mips/mach-generic/mangle-port.h
+++ b/include/asm-mips/mach-generic/mangle-port.h
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2003 Ralf Baechle
+ * Copyright (C) 2003, 2004 Ralf Baechle
  */
 #ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
 #define __ASM_MACH_GENERIC_MANGLE_PORT_H
@@ -11,5 +11,6 @@
 #define __swizzle_addr_b(port)	(port)
 #define __swizzle_addr_w(port)	(port)
 #define __swizzle_addr_l(port)	(port)
+#define __swizzle_addr_q(port)	(port)
 
 #endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h
index 4b565cfb7976..63c0a81c7832 100644
--- a/include/asm-mips/mach-generic/spaces.h
+++ b/include/asm-mips/mach-generic/spaces.h
@@ -7,8 +7,8 @@
  * Copyright (C) 2000, 2002  Maciej W. Rozycki
  * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
  */
-#ifndef _ASM_MACH_SPACES_H
-#define _ASM_MACH_SPACES_H
+#ifndef _ASM_MACH_GENERIC_SPACES_H
+#define _ASM_MACH_GENERIC_SPACES_H
 
 #include <linux/config.h>
 
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h
new file mode 100644
index 000000000000..30d42fcafe3d
--- /dev/null
+++ b/include/asm-mips/mach-ip22/spaces.h
@@ -0,0 +1,55 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_IP22_SPACES_H
+#define _ASM_MACH_IP22_SPACES_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_MIPS32
+
+#define CAC_BASE		0x80000000
+#define IO_BASE			0xa0000000
+#define UNCAC_BASE		0xa0000000
+#define MAP_BASE		0xc0000000
+
+/*
+ * This handles the memory map.
+ * We handle pages at KSEG0 for kernels with 32 bit address space.
+ */
+#define PAGE_OFFSET		0x80000000UL
+
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START		0x20000000UL
+#endif
+
+#endif /* CONFIG_MIPS32 */
+
+#ifdef CONFIG_MIPS64
+#define PAGE_OFFSET		0xffffffff80000000UL
+
+#ifndef HIGHMEM_START
+#define HIGHMEM_START		(1UL << 59UL)
+#endif
+
+#define CAC_BASE		0xffffffff80000000
+#define IO_BASE			0xffffffffa0000000
+#define UNCAC_BASE		0xffffffffa0000000
+#define MAP_BASE		0xffffffffc0000000
+
+#define TO_PHYS(x)		(             ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)		(CAC_BASE   | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)		(UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
+#endif /* CONFIG_MIPS64 */
+
+#endif /* __ASM_MACH_IP22_SPACES_H */
diff --git a/include/asm-mips/mach-ip27/mangle-port.h b/include/asm-mips/mach-ip27/mangle-port.h
index 661995e769a5..f76c44880451 100644
--- a/include/asm-mips/mach-ip27/mangle-port.h
+++ b/include/asm-mips/mach-ip27/mangle-port.h
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2003 Ralf Baechle
+ * Copyright (C) 2003, 2004 Ralf Baechle
  */
 #ifndef __ASM_MACH_IP27_MANGLE_PORT_H
 #define __ASM_MACH_IP27_MANGLE_PORT_H
@@ -11,5 +11,6 @@
 #define __swizzle_addr_b(port)	(port)
 #define __swizzle_addr_w(port)	((port) ^ 2)
 #define __swizzle_addr_l(port)	(port)
+#define __swizzle_addr_q(port)	(port)
 
 #endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-ip27/mmzone.h b/include/asm-mips/mach-ip27/mmzone.h
index 4d95609b1c72..d3f566362e9d 100644
--- a/include/asm-mips/mach-ip27/mmzone.h
+++ b/include/asm-mips/mach-ip27/mmzone.h
@@ -3,7 +3,34 @@
 
 #include <asm/sn/addrs.h>
 #include <asm/sn/arch.h>
+#include <asm/sn/hub.h>
 
 #define pa_to_nid(addr)		NASID_TO_COMPACT_NODEID(NASID_GET(addr))
 
+#define LEVELS_PER_SLICE        128
+
+struct slice_data {
+	unsigned long irq_alloc_mask[2];
+	unsigned long irq_enable_mask[2];
+	int level_to_irq[LEVELS_PER_SLICE];
+};
+
+struct hub_data {
+	kern_vars_t	kern_vars;
+	DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
+	cpumask_t	h_cpus;
+	unsigned long slice_map;
+	struct slice_data slice[2];
+};
+
+struct node_data {
+	struct pglist_data pglist;
+	struct hub_data hub;
+};
+
+extern struct node_data *__node_data[];
+
+#define NODE_DATA(n)		(&__node_data[(n)]->pglist)
+#define hub_data(n)		(&__node_data[(n)]->hub)
+
 #endif /* _ASM_MACH_MMZONE_H */
diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h
index e0cf74d32937..e3b3fe32eeb1 100644
--- a/include/asm-mips/mach-ip27/spaces.h
+++ b/include/asm-mips/mach-ip27/spaces.h
@@ -7,8 +7,8 @@
  * Copyright (C) 2000, 2002  Maciej W. Rozycki
  * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
  */
-#ifndef _ASM_MACH_SPACES_H
-#define _ASM_MACH_SPACES_H
+#ifndef _ASM_MACH_IP27_SPACES_H
+#define _ASM_MACH_IP27_SPACES_H
 
 /*
  * IP27 uses the R10000's uncached attribute feature.  Attribute 3 selects
@@ -31,4 +31,4 @@
 
 #define HIGHMEM_START		(~0UL)
 
-#endif /* _ASM_MACH_SPACES_H */
+#endif /* _ASM_MACH_IP27_SPACES_H */
diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h
index de8eb53eb930..a70a81257c3d 100644
--- a/include/asm-mips/mach-ip27/topology.h
+++ b/include/asm-mips/mach-ip27/topology.h
@@ -1,15 +1,38 @@
 #ifndef _ASM_MACH_TOPOLOGY_H
 #define _ASM_MACH_TOPOLOGY_H	1
 
+#include <asm/sn/arch.h>
 #include <asm/sn/hub.h>
+#include <asm/mmzone.h>
 
 #define cpu_to_node(cpu)	(cpu_data[(cpu)].p_nodeid)
 #define parent_node(node)	(node)
-#define node_to_cpumask(node)	(HUB_DATA(node)->h_cpus)
+#define node_to_cpumask(node)	(hub_data(node)->h_cpus)
 #define node_to_first_cpu(node)	(first_cpu(node_to_cpumask(node)))
 #define pcibus_to_cpumask(bus)	(cpu_online_map)
 
-extern int node_distance(nasid_t nasid_a, nasid_t nasid_b);
-#define node_distance(from, to)	node_distance(from, to)
+extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
+
+#define node_distance(from, to)	(__node_distances[(from)][(to)])
+
+/* sched_domains SD_NODE_INIT for SGI IP27 machines */
+#define SD_NODE_INIT (struct sched_domain) {		\
+	.span			= CPU_MASK_NONE,	\
+	.parent			= NULL,			\
+	.groups			= NULL,			\
+	.min_interval		= 8,			\
+	.max_interval		= 32,			\
+	.busy_factor		= 32,			\
+	.imbalance_pct		= 125,			\
+	.cache_hot_time		= (10*1000),		\
+	.cache_nice_tries	= 1,			\
+	.per_cpu_gain		= 100,			\
+	.flags			= SD_LOAD_BALANCE	\
+				| SD_BALANCE_EXEC	\
+				| SD_WAKE_BALANCE,	\
+	.last_balance		= jiffies,		\
+	.balance_interval	= 1,			\
+	.nr_balance_failed	= 0,			\
+}
 
 #endif /* _ASM_MACH_TOPOLOGY_H */
diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/include/asm-mips/mach-ip32/mangle-port.h
index 6842af46eeff..6e25b52ed8f2 100644
--- a/include/asm-mips/mach-ip32/mangle-port.h
+++ b/include/asm-mips/mach-ip32/mangle-port.h
@@ -4,6 +4,7 @@
  * for more details.
  *
  * Copyright (C) 2003 Ladislav Michl
+ * Copyright (C) 2004 Ralf Baechle
  */
 #ifndef __ASM_MACH_IP32_MANGLE_PORT_H
 #define __ASM_MACH_IP32_MANGLE_PORT_H
@@ -11,5 +12,6 @@
 #define __swizzle_addr_b(port)	((port) ^ 3)
 #define __swizzle_addr_w(port)	((port) ^ 2)
 #define __swizzle_addr_l(port)	(port)
+#define __swizzle_addr_q(port)	(port)
 
 #endif /* __ASM_MACH_IP32_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-ip32/spaces.h b/include/asm-mips/mach-ip32/spaces.h
new file mode 100644
index 000000000000..649864c5ba32
--- /dev/null
+++ b/include/asm-mips/mach-ip32/spaces.h
@@ -0,0 +1,42 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
+ * Copyright (C) 2000, 2002  Maciej W. Rozycki
+ * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_MACH_IP32_SPACES_H
+#define _ASM_MACH_IP32_SPACES_H
+
+#include <linux/config.h>
+
+/*
+ * This handles the memory map.
+ */
+#define PAGE_OFFSET		0xffffffff80000000
+
+/*
+ * Memory above this physical address will be considered highmem.
+ * Fixme: 59 bits is a fictive number and makes assumptions about processors
+ * in the distant future.  Nobody will care for a few years :-)
+ */
+#ifndef HIGHMEM_START
+#define HIGHMEM_START		(1UL << 59UL)
+#endif
+
+#ifdef CONFIG_DMA_NONCOHERENT
+#define CAC_BASE		0x9800000000000000
+#else
+#define CAC_BASE		0xa800000000000000
+#endif
+#define IO_BASE			0x9000000000000000
+#define UNCAC_BASE		0x9000000000000000
+#define MAP_BASE		0xc000000000000000
+
+#define TO_PHYS(x)		(             ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)		(CAC_BASE   | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)		(UNCAC_BASE | ((x) & TO_PHYS_MASK))
+
+#endif /* __ASM_MACH_IP32_SPACES_H */
diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h
index 2dce66f287ef..d2018ebfe33e 100644
--- a/include/asm-mips/mach-ja/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h
@@ -35,4 +35,10 @@
 #define cpu_icache_line_size()	32
 #define cpu_scache_line_size()	32
 
+/*
+ * On the RM9000 we need to ensure that I-cache lines being fetches only
+ * contain valid instructions are funny things will happen.
+ */
+#define PLAT_TRAMPOLINE_STUFF_LINE	32UL
+
 #endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-mips/cpu-feature-overrides.h
new file mode 100644
index 000000000000..2aba6542c8e3
--- /dev/null
+++ b/include/asm-mips/mach-mips/cpu-feature-overrides.h
@@ -0,0 +1,64 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Chris Dearman
+ */
+#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * CPU feature overrides for MIPS boards
+ */
+#ifdef CONFIG_CPU_MIPS32
+#define cpu_has_tlb		1
+#define cpu_has_4kex		1
+#define cpu_has_4ktlb		1
+/* #define cpu_has_fpu		? */
+/* #define cpu_has_32fpr	? */
+#define cpu_has_counter		1
+/* #define cpu_has_watch	? */
+#define cpu_has_divec		1
+#define cpu_has_vce		0
+/* #define cpu_has_cache_cdex_p	? */
+/* #define cpu_has_cache_cdex_s	? */
+/* #define cpu_has_prefetch	? */
+#define cpu_has_mcheck		1
+/* #define cpu_has_ejtag	? */
+#define cpu_has_llsc		1
+/* #define cpu_has_vtag_icache	? */
+/* #define cpu_has_dc_aliases	? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex		0
+/* #define cpu_has_64bits	? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_subset_pcaches ? */
+#endif
+
+#ifdef CONFIG_CPU_MIPS64
+#define cpu_has_tlb		1
+#define cpu_has_4kex		1
+#define cpu_has_4ktlb		1
+/* #define cpu_has_fpu		? */
+/* #define cpu_has_32fpr	? */
+#define cpu_has_counter		1
+/* #define cpu_has_watch	? */
+#define cpu_has_divec		1
+#define cpu_has_vce		0
+/* #define cpu_has_cache_cdex_p	? */
+/* #define cpu_has_cache_cdex_s	? */
+/* #define cpu_has_prefetch	? */
+#define cpu_has_mcheck		1
+/* #define cpu_has_ejtag	? */
+#define cpu_has_llsc		1
+/* #define cpu_has_vtag_icache	? */
+/* #define cpu_has_dc_aliases	? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_nofpuex		0
+/* #define cpu_has_64bits	? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_subset_pcaches ? */
+#endif
+
+#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
new file mode 100644
index 000000000000..6cebe12af287
--- /dev/null
+++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
@@ -0,0 +1,47 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 MontaVista Software Inc.
+ * Author: Manish Lachwani, mlachwani@mvista.com
+ * Copyright (C) 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Momentum Ocelot-3 is based on Rm7900 processor which
+ * is based on the E9000 core.
+ */
+#define cpu_has_watch		1
+#define cpu_has_mips16		0
+#define cpu_has_divec		0
+#define cpu_has_vce		0
+#define cpu_has_cache_cdex_p	0
+#define cpu_has_cache_cdex_s	0
+#define cpu_has_prefetch	1
+#define cpu_has_mcheck		0
+#define cpu_has_ejtag		0
+
+#define cpu_has_llsc		1
+#define cpu_has_vtag_icache	0
+#define cpu_has_dc_aliases	0
+#define cpu_has_ic_fills_f_dc	0
+
+#define cpu_has_nofpuex 	0
+#define cpu_has_64bits		1
+
+#define cpu_has_subset_pcaches	0
+
+#define cpu_dcache_line_size()	32
+#define cpu_icache_line_size()	32
+#define cpu_scache_line_size()	32
+
+/*
+ * On the RM9000 we need to ensure that I-cache lines being fetches only
+ * contain valid instructions are funny things will happen.
+ */
+#define PLAT_TRAMPOLINE_STUFF_LINE	32UL
+
+#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
new file mode 100644
index 000000000000..5bb8b89a6e5d
--- /dev/null
+++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
@@ -0,0 +1,38 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ */
+#ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Sibyte are MIPS64 processors weired to a specific configuration
+ */
+#define cpu_has_watch		1
+#define cpu_has_mips16		0
+#define cpu_has_divec		1
+#define cpu_has_vce		0
+#define cpu_has_cache_cdex_p	0
+#define cpu_has_cache_cdex_s	0
+#define cpu_has_prefetch	1
+#define cpu_has_mcheck		1
+#define cpu_has_ejtag		1
+
+#define cpu_has_llsc		1
+#define cpu_has_vtag_icache	1
+#define cpu_has_dc_aliases	0
+#define cpu_has_ic_fills_f_dc	0
+
+#define cpu_has_nofpuex		0
+#define cpu_has_64bits		1
+
+#define cpu_has_subset_pcaches	0
+
+#define cpu_dcache_line_size()	32
+#define cpu_icache_line_size()	32
+#define cpu_scache_line_size()	32
+
+#endif /* __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
index 1de5c32a5884..ae12c1ccfb5c 100644
--- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
@@ -35,4 +35,10 @@
 #define cpu_icache_line_size()	32
 #define cpu_scache_line_size()	32
 
+/*
+ * On the RM9000 we need to ensure that I-cache lines being fetches only
+ * contain valid instructions are funny things will happen.
+ */
+#define PLAT_TRAMPOLINE_STUFF_LINE	32UL
+
 #endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/marvell.h b/include/asm-mips/marvell.h
index 2e3bc6732d1c..9225b3397a4f 100644
--- a/include/asm-mips/marvell.h
+++ b/include/asm-mips/marvell.h
@@ -11,7 +11,6 @@
 #include <linux/pci.h>
 
 #include <asm/byteorder.h>
-#include <asm/pci_channel.h>
 
 extern unsigned long marvell_base;
 
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 71198779fcd6..a3bdfc6bf607 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -253,6 +253,13 @@
 #define ST0_CE			0x00020000
 
 /*
+ * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
+ * cacheops in userspace.  This bit exists only on RM7000 and RM9000
+ * processors.
+ */
+#define ST0_CO			0x08000000
+
+/*
  * Bitfields in the R[23]000 cp0 status register.
  */
 #define ST0_IEC                 0x00000001
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
index dd7591b48ee1..9dbf3448ff17 100644
--- a/include/asm-mips/mmu_context.h
+++ b/include/asm-mips/mmu_context.h
@@ -126,8 +126,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 	 * Mark current->active_mm as not "active" anymore.
 	 * We don't want to mislead possible IPI tlb flush routines.
 	 */
-	clear_bit(cpu, &prev->cpu_vm_mask);
-	set_bit(cpu, &next->cpu_vm_mask);
+	cpu_clear(cpu, prev->cpu_vm_mask);
+	cpu_set(cpu, next->cpu_vm_mask);
 
 	local_irq_restore(flags);
 }
@@ -161,8 +161,8 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
 	TLBMISS_HANDLER_SETUP_PGD(next->pgd);
 
 	/* mark mmu ownership change */
-	clear_bit(cpu, &prev->cpu_vm_mask);
-	set_bit(cpu, &next->cpu_vm_mask);
+	cpu_clear(cpu, prev->cpu_vm_mask);
+	cpu_set(cpu, next->cpu_vm_mask);
 
 	local_irq_restore(flags);
 }
@@ -178,7 +178,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu)
 
 	local_irq_save(flags);
 
-	if (test_bit(cpu, &mm->cpu_vm_mask))  {
+	if (cpu_isset(cpu, mm->cpu_vm_mask))  {
 		get_new_mmu_context(mm, cpu);
 		write_c0_entryhi(cpu_asid(cpu, mm));
 	} else {
diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h
index 27ad26cb9fe9..29ee13be0b2a 100644
--- a/include/asm-mips/mmzone.h
+++ b/include/asm-mips/mmzone.h
@@ -8,9 +8,6 @@
 #include <asm/page.h>
 #include <mmzone.h>
 
-extern struct pglist_data *node_data[];
-
-#define NODE_DATA(n)		(node_data[(n)])
 #define kvaddr_to_nid(kvaddr)	pa_to_nid(__pa(kvaddr))
 #define pfn_to_nid(pfn)		pa_to_nid((pfn) << PAGE_SHIFT)
 
diff --git a/include/asm-mips/msc01_ic.h b/include/asm-mips/msc01_ic.h
new file mode 100644
index 000000000000..64f17208d602
--- /dev/null
+++ b/include/asm-mips/msc01_ic.h
@@ -0,0 +1,151 @@
+/*
+ * PCI Register definitions for the MIPS System Controller.
+ *
+ * Copyright (C) 2004 MIPS Technologies, Inc.  All rights reserved.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __ASM_MIPS_BOARDS_MSC01_IC_H
+#define __ASM_MIPS_BOARDS_MSC01_IC_H
+
+/*****************************************************************************
+ * Register offset addresses
+ *****************************************************************************/
+
+#define MSC01_IC_RST_OFS     0x00008    /* Software reset              */
+#define MSC01_IC_ENAL_OFS    0x00100    /* Int_in enable mask 31:0     */
+#define MSC01_IC_ENAH_OFS    0x00108    /* Int_in enable mask 63:32    */
+#define MSC01_IC_DISL_OFS    0x00120    /* Int_in disable mask 31:0    */
+#define MSC01_IC_DISH_OFS    0x00128    /* Int_in disable mask 63:32   */
+#define MSC01_IC_ISBL_OFS    0x00140    /* Raw int_in 31:0             */
+#define MSC01_IC_ISBH_OFS    0x00148    /* Raw int_in 63:32            */
+#define MSC01_IC_ISAL_OFS    0x00160    /* Masked int_in 31:0          */
+#define MSC01_IC_ISAH_OFS    0x00168    /* Masked int_in 63:32         */
+#define MSC01_IC_LVL_OFS     0x00180    /* Disable priority int_out    */
+#define MSC01_IC_RAMW_OFS    0x00180    /* Shadow set RAM (EI)	       */
+#define MSC01_IC_OSB_OFS     0x00188    /* Raw int_out                 */
+#define MSC01_IC_OSA_OFS     0x00190    /* Masked int_out              */
+#define MSC01_IC_GENA_OFS    0x00198    /* Global HW int enable        */
+#define MSC01_IC_BASE_OFS    0x001a0    /* Base address of IC_VEC      */
+#define MSC01_IC_VEC_OFS     0x001b0    /* Active int's vector address */
+#define MSC01_IC_EOI_OFS     0x001c0    /* Enable lower level ints     */
+#define MSC01_IC_CFG_OFS     0x001c8    /* Configuration register      */
+#define MSC01_IC_TRLD_OFS    0x001d0    /* Interval timer reload val   */
+#define MSC01_IC_TVAL_OFS    0x001e0    /* Interval timer current val  */
+#define MSC01_IC_TCFG_OFS    0x001f0    /* Interval timer config       */
+#define MSC01_IC_SUP_OFS     0x00200    /* Set up int_in line 0        */
+#define MSC01_IC_ENA_OFS     0x00800    /* Int_in enable mask 63:0     */
+#define MSC01_IC_DIS_OFS     0x00820    /* Int_in disable mask 63:0    */
+#define MSC01_IC_ISB_OFS     0x00840    /* Raw int_in 63:0             */
+#define MSC01_IC_ISA_OFS     0x00860    /* Masked int_in 63:0          */
+
+/*****************************************************************************
+ * Register field encodings
+ *****************************************************************************/
+
+#define MSC01_IC_RST_RST_SHF      0
+#define MSC01_IC_RST_RST_MSK      0x00000001
+#define MSC01_IC_RST_RST_BIT      MSC01_IC_RST_RST_MSK
+#define MSC01_IC_LVL_LVL_SHF      0
+#define MSC01_IC_LVL_LVL_MSK      0x000000ff
+#define MSC01_IC_LVL_SPUR_SHF     16
+#define MSC01_IC_LVL_SPUR_MSK     0x00010000
+#define MSC01_IC_LVL_SPUR_BIT     MSC01_IC_LVL_SPUR_MSK
+#define MSC01_IC_RAMW_RIPL_SHF	  0
+#define MSC01_IC_RAMW_RIPL_MSK	  0x0000003f
+#define MSC01_IC_RAMW_DATA_SHF	  6
+#define MSC01_IC_RAMW_DATA_MSK	  0x00000fc0
+#define MSC01_IC_RAMW_ADDR_SHF	  25
+#define MSC01_IC_RAMW_ADDR_MSK	  0x7e000000
+#define MSC01_IC_RAMW_READ_SHF	  31
+#define MSC01_IC_RAMW_READ_MSK	  0x80000000
+#define MSC01_IC_RAMW_READ_BIT	  MSC01_IC_RAMW_READ_MSK
+#define MSC01_IC_OSB_OSB_SHF      0
+#define MSC01_IC_OSB_OSB_MSK      0x000000ff
+#define MSC01_IC_OSA_OSA_SHF      0
+#define MSC01_IC_OSA_OSA_MSK      0x000000ff
+#define MSC01_IC_GENA_GENA_SHF    0
+#define MSC01_IC_GENA_GENA_MSK    0x00000001
+#define MSC01_IC_GENA_GENA_BIT    MSC01_IC_GENA_GENA_MSK
+#define MSC01_IC_CFG_DIS_SHF      0
+#define MSC01_IC_CFG_DIS_MSK      0x00000001
+#define MSC01_IC_CFG_DIS_BIT      MSC01_IC_CFG_DIS_MSK
+#define MSC01_IC_CFG_SHFT_SHF     8
+#define MSC01_IC_CFG_SHFT_MSK     0x00000f00
+#define MSC01_IC_TCFG_ENA_SHF     0
+#define MSC01_IC_TCFG_ENA_MSK     0x00000001
+#define MSC01_IC_TCFG_ENA_BIT     MSC01_IC_TCFG_ENA_MSK
+#define MSC01_IC_TCFG_INT_SHF     8
+#define MSC01_IC_TCFG_INT_MSK     0x00000100
+#define MSC01_IC_TCFG_INT_BIT     MSC01_IC_TCFG_INT_MSK
+#define MSC01_IC_TCFG_EDGE_SHF    16
+#define MSC01_IC_TCFG_EDGE_MSK    0x00010000
+#define MSC01_IC_TCFG_EDGE_BIT    MSC01_IC_TCFG_EDGE_MSK
+#define MSC01_IC_SUP_PRI_SHF      0
+#define MSC01_IC_SUP_PRI_MSK      0x00000007
+#define MSC01_IC_SUP_EDGE_SHF     8
+#define MSC01_IC_SUP_EDGE_MSK     0x00000100
+#define MSC01_IC_SUP_EDGE_BIT     MSC01_IC_SUP_EDGE_MSK
+#define MSC01_IC_SUP_STEP         8
+
+/*
+ * MIPS System controller interrupt register base.
+ *
+ * FIXME - are these macros specific to Malta and co or to the MSC?  If the
+ * latter, they should be moved elsewhere.
+ */
+#define MIPS_MSC01_IC_REG_BASE	0x1bc40000
+
+/*****************************************************************************
+ * Absolute register addresses
+ *****************************************************************************/
+
+#define MSC01_IC_RST     (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
+#define MSC01_IC_ENAL    (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
+#define MSC01_IC_ENAH    (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
+#define MSC01_IC_DISL    (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
+#define MSC01_IC_DISH    (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
+#define MSC01_IC_ISBL    (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
+#define MSC01_IC_ISBH    (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
+#define MSC01_IC_ISAL    (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
+#define MSC01_IC_ISAH    (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
+#define MSC01_IC_LVL     (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
+#define MSC01_IC_RAMW    (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
+#define MSC01_IC_OSB     (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
+#define MSC01_IC_OSA     (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
+#define MSC01_IC_GENA    (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
+#define MSC01_IC_BASE    (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
+#define MSC01_IC_VEC     (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
+#define MSC01_IC_EOI     (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
+#define MSC01_IC_CFG     (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
+#define MSC01_IC_TRLD    (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
+#define MSC01_IC_TVAL    (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
+#define MSC01_IC_TCFG    (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
+#define MSC01_IC_SUP     (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
+#define MSC01_IC_ENA     (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
+#define MSC01_IC_DIS     (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
+#define MSC01_IC_ISB     (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
+#define MSC01_IC_ISA     (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)
+
+/*
+ * Soc-it interrupts are configurable.
+ * Every board describes its IRQ mapping with this table.
+ */
+typedef struct msc_irqmap {
+	int	im_irq;
+	int	im_type;
+	int	im_lvl;
+} msc_irqmap_t;
+
+/* im_type */
+#define MSC01_IRQ_LEVEL		0
+#define MSC01_IRQ_EDGE		1
+
+extern void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq);
+extern void ll_msc_irq(struct pt_regs *regs);
+
+#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
+
diff --git a/include/asm-mips/numnodes.h b/include/asm-mips/numnodes.h
index fceef695ea5d..4f00c16ceeb0 100644
--- a/include/asm-mips/numnodes.h
+++ b/include/asm-mips/numnodes.h
@@ -2,6 +2,6 @@
 #define _ASM_MAX_NUMNODES_H
 
 /* Max 128 Nodes */
-#define NODES_SHIFT	7
+#define NODES_SHIFT	6
 
 #endif /* _ASM_MAX_NUMNODES_H */
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 47ca67f25e54..d1bf8240e73b 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -15,6 +15,8 @@
 
 #include <spaces.h>
 
+#endif
+
 /*
  * PAGE_SHIFT determines the page size
  */
@@ -31,8 +33,10 @@
 #define PAGE_SHIFT	16
 #endif
 #define PAGE_SIZE	(1UL << PAGE_SHIFT)
-#define PAGE_MASK	(~(PAGE_SIZE-1))
+#define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
 
+
+#ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 
 extern void clear_page(void * page);
@@ -72,15 +76,22 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
  * These are used to make use of C type-checking..
  */
 #ifdef CONFIG_64BIT_PHYS_ADDR
-typedef struct { unsigned long long pte; } pte_t;
+  #ifdef CONFIG_CPU_MIPS32
+    typedef struct { unsigned long pte_low, pte_high; } pte_t;
+    #define pte_val(x)    ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+  #else
+     typedef struct { unsigned long long pte; } pte_t;
+     #define pte_val(x)	((x).pte)
+  #endif
 #else
 typedef struct { unsigned long pte; } pte_t;
+#define pte_val(x)	((x).pte)
 #endif
+
 typedef struct { unsigned long pmd; } pmd_t;
 typedef struct { unsigned long pgd; } pgd_t;
 typedef struct { unsigned long pgprot; } pgprot_t;
 
-#define pte_val(x)	((x).pte)
 #define pmd_val(x)	((x).pmd)
 #define pgd_val(x)	((x).pgd)
 #define pgprot_val(x)	((x).pgprot)
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index 1af4e5b600c6..987090e07a65 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -11,6 +11,49 @@
 
 #ifdef __KERNEL__
 
+/*
+ * This file essentially defines the interface between board
+ * specific PCI code and MIPS common PCI code.  Should potentially put
+ * into include/asm/pci.h file.
+ */
+
+#include <linux/ioport.h>
+
+/*
+ * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
+ * multiple PCI channels may have multiple PCI host controllers or a
+ * single controller supporting multiple channels.
+ */
+struct pci_controller {
+	struct pci_controller *next;
+	struct pci_bus *bus;
+
+	struct pci_ops *pci_ops;
+	struct resource *mem_resource;
+	unsigned long mem_offset;
+	struct resource *io_resource;
+	unsigned long io_offset;
+
+	unsigned int index;
+	/* For compatibility with current (as of July 2003) pciutils
+	   and XFree86. Eventually will be removed. */
+	unsigned int need_domain_info;
+
+	int iommu;
+};
+
+/*
+ * Used by boards to register their PCI busses before the actual scanning.
+ */
+extern struct pci_controller * alloc_pci_controller(void);
+extern void register_pci_controller(struct pci_controller *hose);
+
+/*
+ * board supplied pci irq fixup routine
+ */
+extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
+
+
 /* Can be used to override the logic in pci_scan_bus for skipping
    already-configured bus numbers - to be used for buggy BIOSes
    or architectures with incomplete PCI setup by the loader */
@@ -90,6 +133,25 @@ extern void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev,
 extern void pcibios_resource_to_bus(struct pci_dev *dev,
 	struct pci_bus_region *region, struct resource *res);
 
+#ifdef CONFIG_PCI_DOMAINS
+
+#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
+
+static inline int
+pci_name_bus(char *name, struct pci_bus *bus)
+{
+	struct pci_controller *hose = bus->sysdata;
+
+	if (likely(hose->need_domain_info == 0)) {
+		sprintf(name, "%02x", bus->number);
+	} else {
+		sprintf(name, "%04x:%02x", hose->index, bus->number);
+	}
+	return 0;
+}
+
+#endif /* CONFIG_PCI_DOMAINS */
+
 #endif /* __KERNEL__ */
 
 /* implement the pci_ DMA API in terms of the generic device dma_ one */
@@ -99,4 +161,7 @@ static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 {
 }
 
+/* Do platform specific device initialization at pci_enable_device() time */
+extern int pcibios_plat_dev_init(struct pci_dev *dev);
+
 #endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h
index c043f643fac6..b4ee995c56e6 100644
--- a/include/asm-mips/pci/bridge.h
+++ b/include/asm-mips/pci/bridge.h
@@ -13,7 +13,7 @@
 #define _ASM_PCI_BRIDGE_H
 
 #include <linux/types.h>
-#include <asm/pci_channel.h>
+#include <linux/pci.h>
 #include <asm/xtalk/xwidget.h>		/* generic widget header */
 
 /* I/O page size */
@@ -830,7 +830,6 @@ typedef union ate_u {
 
 #define BRIDGE_INTERNAL_ATES	128
 
-
 struct bridge_controller {
 	struct pci_controller	pc;
 	struct resource		mem;
@@ -840,9 +839,13 @@ struct bridge_controller {
 	unsigned int		widget_id;
 	unsigned int 		irq_cpu;
 	dma64_addr_t		baddr;
+	unsigned int		pci_int[8];
 };
 
 #define BRIDGE_CONTROLLER(bus) \
 	((struct bridge_controller *)((bus)->sysdata))
 
+extern void register_bridge_irq(unsigned int irq);
+extern int request_bridge_irq(struct bridge_controller *bc);
+
 #endif /* _ASM_PCI_BRIDGE_H */
diff --git a/include/asm-mips/pci_channel.h b/include/asm-mips/pci_channel.h
deleted file mode 100644
index a7cdb42fa8bd..000000000000
--- a/include/asm-mips/pci_channel.h
+++ /dev/null
@@ -1,46 +0,0 @@
-#ifndef __ASM_PCI_CHANNEL_H
-#define __ASM_PCI_CHANNEL_H
-
-/*
- * This file essentially defines the interface between board
- * specific PCI code and MIPS common PCI code.  Should potentially put
- * into include/asm/pci.h file.
- */
-
-#include <linux/ioport.h>
-#include <linux/pci.h>
-
-/*
- * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
- * multiple PCI channels may have multiple PCI host controllers or a
- * single controller supporting multiple channels.
- */
-struct pci_controller {
-	struct pci_controller *next;
-	struct pci_bus *bus;
-
-	struct pci_ops *pci_ops;
-	struct resource *mem_resource;
-	unsigned long mem_offset;
-	struct resource *io_resource;
-	unsigned long io_offset;
-
-	/* For compatibility with current (as of July 2003) pciutils
-	   and XFree86. Eventually will be removed. */
-	unsigned int need_domain_info;
-
-	int iommu;
-};
-
-/*
- * Used by boards to register their PCI interfaces before the actual scanning.
- */
-extern struct pci_controller * alloc_pci_controller(void);
-extern void register_pci_controller(struct pci_controller *hose);
-
-/*
- * board supplied pci irq fixup routine
- */
-extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
-
-#endif  /* __ASM_PCI_CHANNEL_H */
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 65bee143ebe3..472a3e78e3fd 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -130,8 +130,21 @@ static inline int pgd_bad(pgd_t pgd)		{ return 0; }
 static inline int pgd_present(pgd_t pgd)	{ return 1; }
 static inline void pgd_clear(pgd_t *pgdp)	{ }
 
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 #define pte_page(x)		pfn_to_page(pte_pfn(x))
+#define pte_pfn(x)		((unsigned long)((x).pte_high >> 6))
+static inline pte_t
+pfn_pte(unsigned long pfn, pgprot_t prot)
+{
+	pte_t pte;
+	pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
+	pte.pte_low = pgprot_val(prot);
+	return pte;
+}
 
+#else
+
+#define pte_page(x)		pfn_to_page(pte_pfn(x))
 
 #ifdef CONFIG_CPU_VR41XX
 #define pte_pfn(x)		((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
@@ -140,6 +153,7 @@ static inline void pgd_clear(pgd_t *pgdp)	{ }
 #define pte_pfn(x)		((unsigned long)((x).pte >> PAGE_SHIFT))
 #define pfn_pte(pfn, prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 #endif
+#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 
 #define __pgd_offset(address)	pgd_index(address)
 #define __pmd_offset(address)	(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
@@ -207,11 +221,19 @@ static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
  */
 #define PTE_FILE_MAX_BITS	27
 
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+	/* fixme */
+#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
+#define pgoff_to_pte(off) \
+ 	((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)})
+
+#else
 #define pte_to_pgoff(_pte) \
 	((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 ))
 
 #define pgoff_to_pte(off) \
 	((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
+#endif
 
 #endif
 
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
index 333d9a8f585f..704b551f59e9 100644
--- a/include/asm-mips/pgtable-64.h
+++ b/include/asm-mips/pgtable-64.h
@@ -29,11 +29,10 @@
  * that the failure is recognized later on. Linux does not seem to
  * handle these failures very well though. The empty_bad_page_table has
  * invalid pte entries in it, to force page faults.
- * Vmalloc handling: vmalloc uses swapper_pg_dir[0] (returned by
- * pgd_offset_k), which is initalized to point to kpmdtbl. kpmdtbl is
- * the only single page pmd in the system. kpmdtbl entries point into
- * kptbl[] array. We reserve 1 << PGD_ORDER pages to hold the
- * vmalloc range translations, which the fault handler looks at.
+ *
+ * Kernel mappings: kernel mappings are held in the swapper_pg_table.
+ * The layout is identical to userspace except it's indexed with the
+ * fault address - VMALLOC_START.
  */
 
 /* PMD_SHIFT determines the size of the area a second-level page table can map */
@@ -66,7 +65,7 @@
  */
 #ifdef CONFIG_PAGE_SIZE_4KB
 #define PGD_ORDER		1
-#define PMD_ORDER		1
+#define PMD_ORDER		0
 #define PTE_ORDER		0
 #endif
 #ifdef CONFIG_PAGE_SIZE_8KB
@@ -94,7 +93,7 @@
 
 #define VMALLOC_START		XKSEG
 #define VMALLOC_END	\
-	(VMALLOC_START + ((1 << PGD_ORDER) * PTRS_PER_PTE * PAGE_SIZE))
+	(VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
 
 #define pte_ERROR(e) \
 	printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
@@ -225,10 +224,4 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
 #define pgoff_to_pte(off) \
 	((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
 
-/*
- * Used for the b0rked handling of kernel pagetables on the 64-bit kernel.
- */
-extern pte_t kptbl[(PAGE_SIZE << PGD_ORDER)/sizeof(pte_t)];
-extern pmd_t kpmdtbl[PTRS_PER_PMD];
-
 #endif /* _ASM_PGTABLE_64_H */
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
index 6a890420643f..3aad751ccd5f 100644
--- a/include/asm-mips/pgtable-bits.h
+++ b/include/asm-mips/pgtable-bits.h
@@ -33,6 +33,32 @@
  * unpredictable things.  The code (when it is written) to deal with
  * this problem will be in the update_mmu_cache() code for the r4k.
  */
+#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
+
+#define _PAGE_PRESENT               (1<<6)  /* implemented in software */
+#define _PAGE_READ                  (1<<7)  /* implemented in software */
+#define _PAGE_WRITE                 (1<<8)  /* implemented in software */
+#define _PAGE_ACCESSED              (1<<9)  /* implemented in software */
+#define _PAGE_MODIFIED              (1<<10) /* implemented in software */
+#define _PAGE_FILE                  (1<<10)  /* set:pagecache unset:swap */
+
+#define _PAGE_R4KBUG                (1<<0)  /* workaround for r4k bug  */
+#define _PAGE_GLOBAL                (1<<0)
+#define _PAGE_VALID                 (1<<1)
+#define _PAGE_SILENT_READ           (1<<1)  /* synonym                 */
+#define _PAGE_DIRTY                 (1<<2)  /* The MIPS dirty bit      */
+#define _PAGE_SILENT_WRITE          (1<<2)
+#define _CACHE_MASK                 (7<<3)
+
+/* MIPS32 defines only values 2 and 3. The rest are implementation
+ * dependent.
+ */
+#define _CACHE_UNCACHED             (2<<3)
+#define _CACHE_CACHABLE_NONCOHERENT (3<<3)
+#define _CACHE_CACHABLE_COW         (3<<3)  /* Au1x                    */
+
+#else
+
 #define _PAGE_PRESENT               (1<<0)  /* implemented in software */
 #define _PAGE_READ                  (1<<1)  /* implemented in software */
 #define _PAGE_WRITE                 (1<<2)  /* implemented in software */
@@ -97,6 +123,7 @@
 
 #endif
 #endif
+#endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */
 
 #define __READABLE	(_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
 #define __WRITEABLE	(_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
@@ -108,11 +135,15 @@
 #elif defined(CONFIG_DMA_NONCOHERENT)
 #define PAGE_CACHABLE_DEFAULT	_CACHE_CACHABLE_NONCOHERENT
 #elif defined(CONFIG_CPU_RM9000)
-#define PAGE_CACHABLE_DEFAULT	_CACHE_CWBEA
+#define PAGE_CACHABLE_DEFAULT	_CACHE_CWB
 #else
 #define PAGE_CACHABLE_DEFAULT	_CACHE_CACHABLE_COW
 #endif
 
+#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
+#define CONF_CM_DEFAULT		(PAGE_CACHABLE_DEFAULT >> 3)
+#else
 #define CONF_CM_DEFAULT		(PAGE_CACHABLE_DEFAULT >> 9)
+#endif
 
 #endif /* _ASM_PGTABLE_BITS_H */
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index c5d69bb707aa..1da0683985e2 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -80,6 +80,34 @@ extern void paging_init(void);
 #define pte_none(pte)		(!(pte_val(pte) & ~_PAGE_GLOBAL))
 #define pte_present(pte)	(pte_val(pte) & _PAGE_PRESENT)
 
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+static inline void set_pte(pte_t *ptep, pte_t pte)
+{
+	ptep->pte_high = pte.pte_high;
+	smp_wmb();
+	ptep->pte_low = pte.pte_low;
+	//printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low);
+
+	if (pte_val(pte) & _PAGE_GLOBAL) {
+		pte_t *buddy = ptep_buddy(ptep);
+		/*
+		 * Make sure the buddy is global too (if it's !none,
+		 * it better already be global)
+		 */
+		if (pte_none(*buddy))
+			buddy->pte_low |= _PAGE_GLOBAL;
+	}
+}
+
+static inline void pte_clear(pte_t *ptep)
+{
+	/* Preserve global status for the pair */
+	if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
+		set_pte(ptep, __pte(_PAGE_GLOBAL));
+	else
+		set_pte(ptep, __pte(0));
+}
+#else
 /*
  * Certain architectures need to do special things when pte's
  * within a page table are directly modified.  Thus, the following
@@ -111,6 +139,7 @@ static inline void pte_clear(pte_t *ptep)
 #endif
 		set_pte(ptep, __pte(0));
 }
+#endif
 
 /*
  * (pmds are folded into pgds so this doesn't get actually called,
@@ -130,6 +159,79 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
  * Undefined behaviour if not..
  */
 static inline int pte_user(pte_t pte)	{ BUG(); return 0; }
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+static inline int pte_read(pte_t pte)	{ return (pte).pte_low & _PAGE_READ; }
+static inline int pte_write(pte_t pte)	{ return (pte).pte_low & _PAGE_WRITE; }
+static inline int pte_dirty(pte_t pte)	{ return (pte).pte_low & _PAGE_MODIFIED; }
+static inline int pte_young(pte_t pte)	{ return (pte).pte_low & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)	{ return (pte).pte_low & _PAGE_FILE; }
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+	(pte).pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
+	(pte).pte_high &= ~_PAGE_SILENT_WRITE;
+	return pte;
+}
+
+static inline pte_t pte_rdprotect(pte_t pte)
+{
+	(pte).pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ);
+	(pte).pte_high &= ~_PAGE_SILENT_READ;
+	return pte;
+}
+
+static inline pte_t pte_mkclean(pte_t pte)
+{
+	(pte).pte_low &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
+	(pte).pte_high &= ~_PAGE_SILENT_WRITE;
+	return pte;
+}
+
+static inline pte_t pte_mkold(pte_t pte)
+{
+	(pte).pte_low &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
+	(pte).pte_high &= ~_PAGE_SILENT_READ;
+	return pte;
+}
+
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+	(pte).pte_low |= _PAGE_WRITE;
+	if ((pte).pte_low & _PAGE_MODIFIED) {
+		(pte).pte_low |= _PAGE_SILENT_WRITE;
+		(pte).pte_high |= _PAGE_SILENT_WRITE;
+	}
+	return pte;
+}
+
+static inline pte_t pte_mkread(pte_t pte)
+{
+	(pte).pte_low |= _PAGE_READ;
+	if ((pte).pte_low & _PAGE_ACCESSED) {
+		(pte).pte_low |= _PAGE_SILENT_READ;
+		(pte).pte_high |= _PAGE_SILENT_READ;
+	}
+	return pte;
+}
+
+static inline pte_t pte_mkdirty(pte_t pte)
+{
+	(pte).pte_low |= _PAGE_MODIFIED;
+	if ((pte).pte_low & _PAGE_WRITE) {
+		(pte).pte_low |= _PAGE_SILENT_WRITE;
+		(pte).pte_high |= _PAGE_SILENT_WRITE;
+	}
+	return pte;
+}
+
+static inline pte_t pte_mkyoung(pte_t pte)
+{
+	(pte).pte_low |= _PAGE_ACCESSED;
+	if ((pte).pte_low & _PAGE_READ)
+		(pte).pte_low |= _PAGE_SILENT_READ;
+		(pte).pte_high |= _PAGE_SILENT_READ;
+	return pte;
+}
+#else
 static inline int pte_read(pte_t pte)	{ return pte_val(pte) & _PAGE_READ; }
 static inline int pte_write(pte_t pte)	{ return pte_val(pte) & _PAGE_WRITE; }
 static inline int pte_dirty(pte_t pte)	{ return pte_val(pte) & _PAGE_MODIFIED; }
@@ -191,6 +293,7 @@ static inline pte_t pte_mkyoung(pte_t pte)
 		pte_val(pte) |= _PAGE_SILENT_READ;
 	return pte;
 }
+#endif
 
 /*
  * Macro to make mark a page protection value as "uncacheable".  Note
@@ -215,10 +318,20 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
  */
 #define mk_pte(page, pgprot)	pfn_pte(page_to_pfn(page), (pgprot))
 
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+	pte.pte_low &= _PAGE_CHG_MASK;
+	pte.pte_low |= pgprot_val(newprot);
+	pte.pte_high |= pgprot_val(newprot) & 0x3f;
+	return pte;
+}
+#else
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
 	return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
 }
+#endif
 
 
 extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
@@ -237,6 +350,24 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 #define kern_addr_valid(addr)	(1)
 #endif
 
+#ifdef CONFIG_64BIT_PHYS_ADDR
+extern phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size);
+extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
+
+static inline int io_remap_page_range(struct vm_area_struct *vma,
+		unsigned long vaddr,
+		unsigned long paddr,
+		unsigned long size,
+		pgprot_t prot)
+{
+	phys_t phys_addr_high = fixup_bigphys_addr(paddr, size);
+	return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
+}
+#else
+#define io_remap_page_range(vma, vaddr, paddr, size, prot)		\
+	remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
+#endif
+
 #include <asm-generic/pgtable.h>
 
 /*
@@ -245,9 +376,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
  */
 #define HAVE_ARCH_UNMAPPED_AREA
 
-#define io_remap_page_range(vma, vaddr, paddr, size, prot)		\
-		remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
-
 /*
  * No page table caches to initialise
  */
diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h
index 9ec09821c5fd..c2e8a0070daf 100644
--- a/include/asm-mips/posix_types.h
+++ b/include/asm-mips/posix_types.h
@@ -28,8 +28,8 @@ typedef unsigned int	__kernel_nlink_t;
 typedef long		__kernel_off_t;
 typedef int		__kernel_pid_t;
 typedef int		__kernel_ipc_pid_t;
-typedef int		__kernel_uid_t;
-typedef int		__kernel_gid_t;
+typedef unsigned int	__kernel_uid_t;
+typedef unsigned int	__kernel_gid_t;
 #if (_MIPS_SZLONG == 32)
 typedef unsigned int	__kernel_size_t;
 typedef int		__kernel_ssize_t;
@@ -50,8 +50,8 @@ typedef char *		__kernel_caddr_t;
 
 typedef unsigned short	__kernel_uid16_t;
 typedef unsigned short	__kernel_gid16_t;
-typedef int		__kernel_uid32_t;
-typedef int		__kernel_gid32_t;
+typedef unsigned int	__kernel_uid32_t;
+typedef unsigned int	__kernel_gid32_t;
 typedef __kernel_uid_t	__kernel_old_uid_t;
 typedef __kernel_gid_t	__kernel_old_gid_t;
 typedef unsigned int	__kernel_old_dev_t;
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index a502e8360230..b461fd0c9831 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -12,79 +12,15 @@
 #define _ASM_PROCESSOR_H
 
 #include <linux/config.h>
-#include <linux/cache.h>
 #include <linux/threads.h>
 
 #include <asm/cachectl.h>
 #include <asm/cpu.h>
+#include <asm/cpu-info.h>
 #include <asm/mipsregs.h>
 #include <asm/prefetch.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_SGI_IP27
-#include <asm/sn/types.h>
-#endif
-
-/*
- * Descriptor for a cache
- */
-struct cache_desc {
-	unsigned short linesz;	/* Size of line in bytes */
-	unsigned short ways;	/* Number of ways */
-	unsigned short sets;	/* Number of lines per set */
-	unsigned int waysize;	/* Bytes per way */
-	unsigned int waybit;	/* Bits to select in a cache set */
-	unsigned int flags;	/* Flags describing cache properties */
-};
-
-/*
- * Flag definitions
- */
-#define MIPS_CACHE_NOT_PRESENT	0x00000001
-#define MIPS_CACHE_VTAG		0x00000002	/* Virtually tagged cache */
-#define MIPS_CACHE_ALIASES	0x00000004	/* Cache could have aliases */
-#define MIPS_CACHE_IC_F_DC	0x00000008	/* Ic can refill from D-cache */
-
-struct cpuinfo_mips {
-	unsigned long		udelay_val;
-	unsigned long		asid_cache;
-#if defined(CONFIG_SGI_IP27)
-//	cpuid_t		p_cpuid;	/* PROM assigned cpuid */
-	cnodeid_t	p_nodeid;	/* my node ID in compact-id-space */
-	nasid_t		p_nasid;	/* my node ID in numa-as-id-space */
-	unsigned char	p_slice;	/* Physical position on node board */
-#endif
-#if 0
-	unsigned long		loops_per_sec;
-	unsigned long		ipi_count;
-	unsigned long		irq_attempt[NR_IRQS];
-	unsigned long		smp_local_irq_count;
-	unsigned long		prof_multiplier;
-	unsigned long		prof_counter;
-#endif
-
-	/*
-	 * Capability and feature descriptor structure for MIPS CPU
-	 */
-	unsigned long		options;
-	unsigned int		processor_id;
-	unsigned int		fpu_id;
-	unsigned int		cputype;
-	int			isa_level;
-	int			tlbsize;
-	struct cache_desc	icache;	/* Primary I-cache */
-	struct cache_desc	dcache;	/* Primary D or combined I/D cache */
-	struct cache_desc	scache;	/* Secondary cache */
-	struct cache_desc	tcache;	/* Tertiary/split secondary cache */
-	void 			*data;	/* Additional data */
-} __attribute__((aligned(SMP_CACHE_BYTES)));
-
-extern struct cpuinfo_mips cpu_data[];
-#define current_cpu_data cpu_data[smp_processor_id()]
-
-extern void cpu_probe(void);
-extern void cpu_report(void);
-
 /*
  * Return current * instruction pointer ("program counter").
  */
@@ -143,7 +79,7 @@ extern unsigned int vced_count, vcei_count;
 
 #define NUM_FPU_REGS	32
 
-typedef u64 fpureg_t;
+typedef __u64 fpureg_t;
 
 struct mips_fpu_hard_struct {
 	fpureg_t	fpr[NUM_FPU_REGS];
@@ -235,8 +171,6 @@ struct thread_struct {
 	MF_FIXADE, 0, 0 \
 }
 
-#ifdef __KERNEL__
-
 struct task_struct;
 
 /* Free all resources held by a thread. */
@@ -264,8 +198,6 @@ unsigned long get_wchan(struct task_struct *p);
 
 #define cpu_relax()	barrier()
 
-#endif /* __KERNEL__ */
-
 /*
  * Return_address is a replacement for __builtin_return_address(count)
  * which on certain architectures cannot reasonably be implemented in GCC
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 2a090cf369b7..d3c46d633826 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -60,6 +60,8 @@ struct pt_regs {
 
 #ifdef __KERNEL__
 
+#include <linux/linkage.h>
+
 /*
  * Does the process account for user or for system time?
  */
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 8a12fb6b07de..649f397a3472 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -26,7 +26,7 @@
  *  - We need a properly sign extended address for 64-bit code.  To get away
  *    without ifdefs we let the compiler do it by a type cast.
  */
-#define INDEX_BASE	((int) KSEG0)
+#define INDEX_BASE	CKSEG0
 
 #define cache_op(op,addr)						\
 	__asm__ __volatile__(						\
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
index 83c735adef98..8a70ff58f760 100644
--- a/include/asm-mips/serial.h
+++ b/include/asm-mips/serial.h
@@ -55,7 +55,7 @@
 
 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
 
-#ifdef CONFIG_MIPS_JAZZ
+#ifdef CONFIG_MACH_JAZZ
 #include <asm/jazz.h>
 
 #ifndef CONFIG_OLIVETTI_M700
@@ -152,15 +152,82 @@
 
 #ifdef CONFIG_SERIAL_AU1X00
 #include <asm/mach-au1x00/au1000.h>
-#define AU1000_SERIAL_PORT_DEFNS                              \
-    { .baud_base = 0, .port = UART0_ADDR, .irq = AU1000_UART0_INT,  \
-      .flags = STD_COM_FLAGS, .type = 1 },                        \
-    { .baud_base = 0, .port = UART1_ADDR, .irq = AU1000_UART1_INT,  \
-      .flags = STD_COM_FLAGS, .type = 1 },     \
-    { .baud_base = 0, .port = UART2_ADDR, .irq = AU1000_UART2_INT,  \
-      .flags = STD_COM_FLAGS, .type = 1 },    \
-    { .baud_base = 0, .port = UART3_ADDR, .irq = AU1000_UART3_INT,  \
-      .flags = STD_COM_FLAGS, .type = 1 },
+#ifdef CONFIG_SOC_AU1000
+#define AU1000_SERIAL_PORT_DEFNS                       \
+    { .baud_base = 0, .port = UART0_ADDR,              \
+      .iomem_base = (unsigned char *)UART0_ADDR,       \
+      .irq = AU1000_UART0_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART1_ADDR,              \
+      .iomem_base = (unsigned char *)UART1_ADDR,       \
+      .irq = AU1000_UART1_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART2_ADDR,              \
+      .iomem_base = (unsigned char *)UART2_ADDR,       \
+      .irq = AU1000_UART2_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART3_ADDR,              \
+      .iomem_base = (unsigned char *)UART3_ADDR,       \
+      .irq = AU1000_UART3_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },
+#endif
+
+#ifdef CONFIG_SOC_AU1500
+#define AU1000_SERIAL_PORT_DEFNS                       \
+    { .baud_base = 0, .port = UART0_ADDR,              \
+      .iomem_base = (unsigned char *)UART0_ADDR,       \
+      .irq = AU1500_UART0_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART3_ADDR,              \
+      .iomem_base = (unsigned char *)UART3_ADDR,       \
+      .irq = AU1500_UART3_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },
+#endif
+
+#ifdef CONFIG_SOC_AU1100
+#define AU1000_SERIAL_PORT_DEFNS                       \
+    { .baud_base = 0, .port = UART0_ADDR,              \
+      .iomem_base = (unsigned char *)UART0_ADDR,       \
+      .irq = AU1100_UART0_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART1_ADDR,              \
+      .iomem_base = (unsigned char *)UART1_ADDR,       \
+      .irq = AU1100_UART1_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART3_ADDR,              \
+      .iomem_base = (unsigned char *)UART3_ADDR,       \
+      .irq = AU1100_UART3_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },
+#endif
+
+#ifdef CONFIG_SOC_AU1550
+#define AU1000_SERIAL_PORT_DEFNS                       \
+    { .baud_base = 0, .port = UART0_ADDR,              \
+      .iomem_base = (unsigned char *)UART0_ADDR,       \
+      .irq = AU1550_UART0_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART1_ADDR,              \
+      .iomem_base = (unsigned char *)UART1_ADDR,       \
+      .irq = AU1550_UART1_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART3_ADDR,              \
+      .iomem_base = (unsigned char *)UART3_ADDR,       \
+      .irq = AU1550_UART3_INT,  .flags = STD_COM_FLAGS,\
+      .iomem_reg_shift = 2 },
+#endif
+
+#ifdef CONFIG_SOC_AU1200
+#define AU1000_SERIAL_PORT_DEFNS                       \
+    { .baud_base = 0, .port = UART0_ADDR,              \
+      .iomem_base = (unsigned char *)UART0_ADDR,       \
+      .irq = AU1200_UART0_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },                          \
+    { .baud_base = 0, .port = UART1_ADDR,              \
+      .iomem_base = (unsigned char *)UART1_ADDR,       \
+      .irq = AU1200_UART1_INT, .flags = STD_COM_FLAGS, \
+      .iomem_reg_shift = 2 },
+#endif
+
 #else
 #define AU1000_SERIAL_PORT_DEFNS
 #endif
@@ -252,6 +319,23 @@
 #define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
 #endif
 
+#ifdef CONFIG_MOMENCO_OCELOT_3
+#define OCELOT_3_BASE_BAUD	( 20000000 / 16 )
+#define OCELOT_3_SERIAL_IRQ	6
+#define OCELOT_3_SERIAL_BASE	(signed)0xfd000020
+
+#define _OCELOT_3_SERIAL_INIT(int, base)				\
+	{ baud_base: OCELOT_3_BASE_BAUD, irq: int, 			\
+	  flags: STD_COM_FLAGS,						\
+	  iomem_base: (u8 *) base, iomem_reg_shift: 2,			\
+	  io_type: SERIAL_IO_MEM }
+
+#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS				\
+	_OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
+#else
+#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
+#endif
+
 #ifdef CONFIG_MOMENCO_OCELOT
 /* Ordinary NS16552 duart with a 20MHz crystal.  */
 #define OCELOT_BASE_BAUD ( 20000000 / 16 )
@@ -353,6 +437,7 @@
 	MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS		\
 	MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS		\
 	MOMENCO_OCELOT_SERIAL_PORT_DEFNS		\
+	MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS		\
 	TXX927_SERIAL_PORT_DEFNS                        \
 	AU1000_SERIAL_PORT_DEFNS
 
diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h
index 3e16b4d9d621..169187f53fbc 100644
--- a/include/asm-mips/sgi/ioc.h
+++ b/include/asm-mips/sgi/ioc.h
@@ -120,7 +120,7 @@ extern u8 sgi_ioc_reset, sgi_ioc_write;
 struct sgioc_regs {
 	struct pi1_regs pport;
 	u32 _unused0[2];
-	struct sgioc_uart_regs serport;
+	struct sgioc_uart_regs uart;
 	struct sgioc_keyb_regs kbdmouse;
 	u8 _gcsel[3];
 	volatile u8 gcsel;
diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h
index d63ef67ceb27..59450335f049 100644
--- a/include/asm-mips/sgiarcs.h
+++ b/include/asm-mips/sgiarcs.h
@@ -371,7 +371,7 @@ struct linux_smonblock {
 
 #define __arc_clobbers							\
 	"$2","$3" /* ... */, "$8","$9","$10","$11",			\
-	"$12","$13","$14","$15","$16","$24","25","$31"
+	"$12","$13","$14","$15","$16","$24","$25","$31"
 
 #define ARC_CALL0(dest)							\
 ({	long __res;							\
@@ -464,7 +464,7 @@ struct linux_smonblock {
 	long __vec = (long) romvec->dest;				\
 	__asm__ __volatile__(						\
 	"dsubu\t$29, 32\n\t"						\
-	"sw\t%6, 16($29)\n\t"						\
+	"sw\t%7, 16($29)\n\t"						\
 	"jalr\t%1\n\t"							\
 	"daddu\t$29, 32\n\t"						\
 	"move\t%0, $2"							\
diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h
index fec216976f9e..8ddd3c99bcf7 100644
--- a/include/asm-mips/siginfo.h
+++ b/include/asm-mips/siginfo.h
@@ -13,7 +13,7 @@
 
 #define SIGEV_HEAD_SIZE	(sizeof(long) + 2*sizeof(int))
 #define SIGEV_PAD_SIZE	((SIGEV_MAX_SIZE-SIGEV_HEAD_SIZE) / sizeof(int))
-#define SI_PAD_SIZE	((SI_MAX_SIZE/sizeof(int)) - 4)
+#undef __ARCH_SI_TRAPNO	/* exception code needs to fill this ...  */
 
 #define HAVE_ARCH_SIGINFO_T
 
@@ -24,15 +24,23 @@
 #define HAVE_ARCH_COPY_SIGINFO
 struct siginfo;
 
-#include <asm-generic/siginfo.h>
+/*
+ * Careful to keep union _sifields from shifting ...
+ */
+#ifdef CONFIG_MIPS32
+#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
+#endif
+#ifdef CONFIG_MIPS64
+#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
+#endif
 
-/* This structure matches the 32/n32 ABIs for source compatibility but
-   has Linux extensions.  */
+#include <asm-generic/siginfo.h>
 
 typedef struct siginfo {
 	int si_signo;
 	int si_code;
 	int si_errno;
+	int __pad0[SI_MAX_SIZE / sizeof(int) - SI_PAD_SIZE - 3];
 
 	union {
 		int _pad[SI_PAD_SIZE];
@@ -40,131 +48,57 @@ typedef struct siginfo {
 		/* kill() */
 		struct {
 			pid_t _pid;		/* sender's pid */
-			uid_t _uid;		/* sender's uid */
+			__ARCH_SI_UID_T _uid;	/* sender's uid */
 		} _kill;
 
-		/* SIGCHLD */
-		struct {
-			pid_t _pid;		/* which child */
-			uid_t _uid;		/* sender's uid */
-			int _status;		/* exit code */
-			clock_t _utime;
-			clock_t _stime;
-		} _sigchld;
-
-		/* IRIX SIGCHLD */
-		struct {
-			pid_t _pid;		/* which child */
-			clock_t _utime;
-			int _status;		/* exit code */
-			clock_t _stime;
-		} _irix_sigchld;
-
-		/* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-		struct {
-			void *_addr; /* faulting insn/memory ref. */
-		} _sigfault;
-
-		/* SIGPOLL, SIGXFSZ (To do ...)  */
-		struct {
-#ifdef CONFIG_MIPS32
-			int _band;	/* POLL_IN, POLL_OUT, POLL_MSG */
-#endif
-#ifdef CONFIG_MIPS64
-			long _band;	/* POLL_IN, POLL_OUT, POLL_MSG */
-#endif
-			int _fd;
-		} _sigpoll;
-
 		/* POSIX.1b timers */
 		struct {
 			timer_t _tid;		/* timer id */
 			int _overrun;		/* overrun count */
 			char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)];
 			sigval_t _sigval;	/* same as below */
-			int _sys_private;	/* not to be passed to user */
+			int _sys_private;       /* not to be passed to user */
 		} _timer;
 
 		/* POSIX.1b signals */
 		struct {
 			pid_t _pid;		/* sender's pid */
-			uid_t _uid;		/* sender's uid */
+			__ARCH_SI_UID_T _uid;	/* sender's uid */
 			sigval_t _sigval;
 		} _rt;
 
-	} _sifields;
-} siginfo_t;
-
-#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
-
-#include <linux/compat.h>
-
-#define SI_PAD_SIZE32   ((SI_MAX_SIZE/sizeof(int)) - 3)
-
-typedef union sigval32 {
-	int sival_int;
-	s32 sival_ptr;
-} sigval_t32;
-
-typedef struct siginfo32 {
-	int si_signo;
-	int si_code;
-	int si_errno;
-
-	union {
-		int _pad[SI_PAD_SIZE32];
-
-		/* kill() */
-		struct {
-			compat_pid_t _pid;	/* sender's pid */
-			compat_uid_t _uid;	/* sender's uid */
-		} _kill;
-
 		/* SIGCHLD */
 		struct {
-			compat_pid_t _pid;	/* which child */
-			compat_uid_t _uid;	/* sender's uid */
-			compat_clock_t _utime;
+			pid_t _pid;		/* which child */
+			__ARCH_SI_UID_T _uid;	/* sender's uid */
 			int _status;		/* exit code */
-			compat_clock_t _stime;
+			clock_t _utime;
+			clock_t _stime;
 		} _sigchld;
 
 		/* IRIX SIGCHLD */
 		struct {
-			compat_pid_t _pid;	/* which child */
-			compat_clock_t _utime;
+			pid_t _pid;		/* which child */
+			clock_t _utime;
 			int _status;		/* exit code */
-			compat_clock_t _stime;
+			clock_t _stime;
 		} _irix_sigchld;
 
 		/* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
 		struct {
-			s32 _addr; /* faulting insn/memory ref. */
+			void __user *_addr; /* faulting insn/memory ref. */
+#ifdef __ARCH_SI_TRAPNO
+			int _trapno;	/* TRAP # which caused the signal */
+#endif
 		} _sigfault;
 
 		/* SIGPOLL, SIGXFSZ (To do ...)  */
 		struct {
-			int _band;	/* POLL_IN, POLL_OUT, POLL_MSG */
+			__ARCH_SI_BAND_T _band;	/* POLL_IN, POLL_OUT, POLL_MSG */
 			int _fd;
 		} _sigpoll;
-
-		/* POSIX.1b timers */
-		struct {
-			unsigned int _timer1;
-			unsigned int _timer2;
-		} _timer;
-
-		/* POSIX.1b signals */
-		struct {
-			compat_pid_t _pid;	/* sender's pid */
-			compat_uid_t _uid;	/* sender's uid */
-			sigval_t32 _sigval;
-		} _rt;
-
 	} _sifields;
-} siginfo_t32;
-
-#endif /* defined(__KERNEL__) && defined(CONFIG_COMPAT) */
+} siginfo_t;
 
 /*
  * si_code values
diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h
index a88c33750555..6333169be329 100644
--- a/include/asm-mips/sim.h
+++ b/include/asm-mips/sim.h
@@ -13,9 +13,6 @@
 
 #include <asm/offset.h>
 
-/* Used in declaration of save_static functions.  */
-#define static_unused static __attribute__((unused))
-
 #define __str2(x) #x
 #define __str(x) __str2(x)
 
@@ -39,6 +36,7 @@ __asm__ (								\
 	"sw\t$22,"__str(PT_R22)"($29)\n\t"				\
 	"sw\t$23,"__str(PT_R23)"($29)\n\t"				\
 	"sw\t$30,"__str(PT_R30)"($29)\n\t"				\
+	"j\t_" #symbol "\n\t"						\
 	".end\t" #symbol "\n\t"						\
 	".size\t" #symbol",. - " #symbol)
 
@@ -66,6 +64,7 @@ __asm__ (								\
 	"sd\t$22,"__str(PT_R22)"($29)\n\t"				\
 	"sd\t$23,"__str(PT_R23)"($29)\n\t"				\
 	"sd\t$30,"__str(PT_R30)"($29)\n\t"				\
+	"j\t_" #symbol "\n\t"						\
 	".end\t" #symbol "\n\t"						\
 	".size\t" #symbol",. - " #symbol)
 
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index f0ef26b43f7e..8ba370ecfd4c 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -68,11 +68,6 @@ static inline int num_booting_cpus(void)
 extern void core_send_ipi(int cpu, unsigned int action);
 
 /*
- * Detect available CPUs, populate phys_cpu_present_map
- */
-extern void prom_build_cpu_map(void);
-
-/*
  * Firmware CPU startup hook
  */
 extern void prom_boot_secondary(int cpu, struct task_struct *idle);
@@ -84,7 +79,7 @@ extern void prom_boot_secondary(int cpu, struct task_struct *idle);
 extern void prom_init_secondary(void);
 
 /*
- * Callout to firmware before smp_init
+ * Detect available CPUs, populate phys_cpu_present_map before smp_init
  */
 extern void prom_prepare_cpus(unsigned int max_cpus);
 
diff --git a/include/asm-mips/sn/hub.h b/include/asm-mips/sn/hub.h
index 89b92104f97e..1992d9254a08 100644
--- a/include/asm-mips/sn/hub.h
+++ b/include/asm-mips/sn/hub.h
@@ -8,25 +8,6 @@
 #include <asm/sn/klkernvars.h>
 #include <asm/xtalk/xtalk.h>
 
-#define LEVELS_PER_SLICE	128
-
-struct slice_data {
-	unsigned long irq_alloc_mask[2];
-	unsigned long irq_enable_mask[2];
-	int level_to_irq[LEVELS_PER_SLICE];
-};
-
-struct hub_data {
-	kern_vars_t	kern_vars;
-	DECLARE_BITMAP  (h_bigwin_used, HUB_NUM_BIG_WINDOW);
-	cpumask_t	h_cpus;
-	unsigned long slice_map;
-	struct slice_data slice[2];
-};
-
-extern struct hub_data *hub_data[];
-#define HUB_DATA(n)		(hub_data[(n)])
-
 /* ip27-hubio.c */
 extern unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget,
 			  unsigned long xtalk_addr, size_t size);
diff --git a/include/asm-mips/sn/sn_private.h b/include/asm-mips/sn/sn_private.h
index 8229c6e29a91..43d5dc9b3302 100644
--- a/include/asm-mips/sn/sn_private.h
+++ b/include/asm-mips/sn/sn_private.h
@@ -10,12 +10,10 @@ extern cnodeid_t get_compact_nodeid(void);
 extern void hub_rtc_init(cnodeid_t);
 extern void cpu_time_init(void);
 extern void per_cpu_init(void);
-extern void per_hub_init(cnodeid_t cnode);
 extern void install_cpu_nmi_handler(int slice);
 extern void install_ipi(void);
 extern void setup_replication_mask(int);
 extern void replicate_kernel_text(int);
 extern pfn_t node_getfirstfree(cnodeid_t);
-extern void mlreset(void);
 
 #endif /* __ASM_SN_SN_PRIVATE_H */
diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h
index eba99d2ac63b..020b4db70ee5 100644
--- a/include/asm-mips/socket.h
+++ b/include/asm-mips/socket.h
@@ -68,6 +68,8 @@ To add: #define SO_REUSEPORT 0x0200	/* Allow local address and port reuse.  */
 
 #define SO_PEERSEC		30
 
+#ifdef __KERNEL__
+
 /** sock_type - Socket types
  *
  * Please notice that for binary compat reasons MIPS has to
@@ -93,6 +95,8 @@ enum sock_type {
 
 #define SOCK_MAX (SOCK_PACKET + 1)
 
-#define ARCH_HAS_SOCKET_TYPES
+#define ARCH_HAS_SOCKET_TYPES 1
+
+#endif /* __KERNEL__ */
 
 #endif /* _ASM_SOCKET_H */
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
index f16118f57e79..adbca38ead51 100644
--- a/include/asm-mips/spinlock.h
+++ b/include/asm-mips/spinlock.h
@@ -9,6 +9,8 @@
 #ifndef _ASM_SPINLOCK_H
 #define _ASM_SPINLOCK_H
 
+#include <asm/war.h>
+
 /*
  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  */
@@ -36,27 +38,43 @@ static inline void _raw_spin_lock(spinlock_t *lock)
 {
 	unsigned int tmp;
 
-	__asm__ __volatile__(
-	".set\tnoreorder\t\t\t# _raw_spin_lock\n"
-	"1:\tll\t%1, %2\n\t"
-	"bnez\t%1, 1b\n\t"
-	" li\t%1, 1\n\t"
-	"sc\t%1, %0\n\t"
-	"beqz\t%1, 1b\n\t"
-	" sync\n\t"
-	".set\treorder"
-	: "=m" (lock->lock), "=&r" (tmp)
-	: "m" (lock->lock)
-	: "memory");
+	if (R10000_LLSC_WAR) {
+		__asm__ __volatile__(
+		"	.set	noreorder	# _raw_spin_lock	\n"
+		"1:	ll	%1, %2					\n"
+		"	bnez	%1, 1b					\n"
+		"	 li	%1, 1					\n"
+		"	sc	%1, %0					\n"
+		"	beqzl	%1, 1b					\n"
+		"	 nop						\n"
+		"	sync						\n"
+		"	.set	reorder					\n"
+		: "=m" (lock->lock), "=&r" (tmp)
+		: "m" (lock->lock)
+		: "memory");
+	} else {
+		__asm__ __volatile__(
+		"	.set	noreorder	# _raw_spin_lock	\n"
+		"1:	ll	%1, %2					\n"
+		"	bnez	%1, 1b					\n"
+		"	 li	%1, 1					\n"
+		"	sc	%1, %0					\n"
+		"	beqz	%1, 1b					\n"
+		"	 sync						\n"
+		"	.set	reorder					\n"
+		: "=m" (lock->lock), "=&r" (tmp)
+		: "m" (lock->lock)
+		: "memory");
+	}
 }
 
 static inline void _raw_spin_unlock(spinlock_t *lock)
 {
 	__asm__ __volatile__(
-	".set\tnoreorder\t\t\t# _raw_spin_unlock\n\t"
-	"sync\n\t"
-	"sw\t$0, %0\n\t"
-	".set\treorder"
+	"	.set	noreorder	# _raw_spin_unlock	\n"
+	"	sync						\n"
+	"	sw	$0, %0					\n"
+	"	.set\treorder					\n"
 	: "=m" (lock->lock)
 	: "m" (lock->lock)
 	: "memory");
@@ -66,17 +84,34 @@ static inline unsigned int _raw_spin_trylock(spinlock_t *lock)
 {
 	unsigned int temp, res;
 
-	__asm__ __volatile__(
-	".set\tnoreorder\t\t\t# _raw_spin_trylock\n\t"
-	"1:\tll\t%0, %3\n\t"
-	"ori\t%2, %0, 1\n\t"
-	"sc\t%2, %1\n\t"
-	"beqz\t%2, 1b\n\t"
-	" andi\t%2, %0, 1\n\t"
-	".set\treorder"
-	: "=&r" (temp), "=m" (lock->lock), "=&r" (res)
-	: "m" (lock->lock)
-	: "memory");
+	if (R10000_LLSC_WAR) {
+		__asm__ __volatile__(
+		"	.set	noreorder	# _raw_spin_trylock	\n"
+		"1:	ll	%0, %3					\n"
+		"	ori	%2, %0, 1				\n"
+		"	sc	%2, %1					\n"
+		"	beqzl	%2, 1b					\n"
+		"	 nop						\n"
+		"	andi	%2, %0, 1				\n"
+		"	sync						\n"
+		"	.set	reorder"
+		: "=&r" (temp), "=m" (lock->lock), "=&r" (res)
+		: "m" (lock->lock)
+		: "memory");
+	} else {
+		__asm__ __volatile__(
+		"	.set	noreorder	# _raw_spin_trylock	\n"
+		"1:	ll	%0, %3					\n"
+		"	ori	%2, %0, 1				\n"
+		"	sc	%2, %1					\n"
+		"	beqz	%2, 1b					\n"
+		"	 andi	%2, %0, 1				\n"
+		"	sync						\n"
+		"	.set	reorder"
+		: "=&r" (temp), "=m" (lock->lock), "=&r" (res)
+		: "m" (lock->lock)
+		: "memory");
+	}
 
 	return res == 0;
 }
@@ -104,18 +139,34 @@ static inline void _raw_read_lock(rwlock_t *rw)
 {
 	unsigned int tmp;
 
-	__asm__ __volatile__(
-	".set\tnoreorder\t\t\t# _raw_read_lock\n"
-	"1:\tll\t%1, %2\n\t"
-	"bltz\t%1, 1b\n\t"
-	" addu\t%1, 1\n\t"
-	"sc\t%1, %0\n\t"
-	"beqz\t%1, 1b\n\t"
-	" sync\n\t"
-	".set\treorder"
-	: "=m" (rw->lock), "=&r" (tmp)
-	: "m" (rw->lock)
-	: "memory");
+	if (R10000_LLSC_WAR) {
+		__asm__ __volatile__(
+		"	.set	noreorder	# _raw_read_lock	\n"
+		"1:	ll	%1, %2					\n"
+		"	bltz	%1, 1b					\n"
+		"	 addu	%1, 1					\n"
+		"	sc	%1, %0					\n"
+		"	beqzl	%1, 1b					\n"
+		"	 nop						\n"
+		"	sync						\n"
+		"	.set	reorder					\n"
+		: "=m" (rw->lock), "=&r" (tmp)
+		: "m" (rw->lock)
+		: "memory");
+	} else {
+		__asm__ __volatile__(
+		"	.set	noreorder	# _raw_read_lock	\n"
+		"1:	ll	%1, %2					\n"
+		"	bltz	%1, 1b					\n"
+		"	 addu	%1, 1					\n"
+		"	sc	%1, %0					\n"
+		"	beqz	%1, 1b					\n"
+		"	 sync						\n"
+		"	.set	reorder					\n"
+		: "=m" (rw->lock), "=&r" (tmp)
+		: "m" (rw->lock)
+		: "memory");
+	}
 }
 
 /* Note the use of sub, not subu which will make the kernel die with an
@@ -125,44 +176,71 @@ static inline void _raw_read_unlock(rwlock_t *rw)
 {
 	unsigned int tmp;
 
-	__asm__ __volatile__(
-	".set\tnoreorder\t\t\t# _raw_read_unlock\n"
-	"1:\tll\t%1, %2\n\t"
-	"sub\t%1, 1\n\t"
-	"sc\t%1, %0\n\t"
-	"beqz\t%1, 1b\n\t"
-	" sync\n\t"
-	".set\treorder"
-	: "=m" (rw->lock), "=&r" (tmp)
-	: "m" (rw->lock)
-	: "memory");
+	if (R10000_LLSC_WAR) {
+		__asm__ __volatile__(
+		"1:	ll	%1, %2		# _raw_read_unlock	\n"
+		"	sub	%1, 1					\n"
+		"	sc	%1, %0					\n"
+		"	beqzl	%1, 1b					\n"
+		"	sync						\n"
+		: "=m" (rw->lock), "=&r" (tmp)
+		: "m" (rw->lock)
+		: "memory");
+	} else {
+		__asm__ __volatile__(
+		"	.set	noreorder	# _raw_read_unlock	\n"
+		"1:	ll	%1, %2					\n"
+		"	sub	%1, 1					\n"
+		"	sc	%1, %0					\n"
+		"	beqz	%1, 1b					\n"
+		"	 sync						\n"
+		"	.set	reorder					\n"
+		: "=m" (rw->lock), "=&r" (tmp)
+		: "m" (rw->lock)
+		: "memory");
+	}
 }
 
 static inline void _raw_write_lock(rwlock_t *rw)
 {
 	unsigned int tmp;
 
-	__asm__ __volatile__(
-	".set\tnoreorder\t\t\t# _raw_write_lock\n"
-	"1:\tll\t%1, %2\n\t"
-	"bnez\t%1, 1b\n\t"
-	" lui\t%1, 0x8000\n\t"
-	"sc\t%1, %0\n\t"
-	"beqz\t%1, 1b\n\t"
-	" sync\n\t"
-	".set\treorder"
-	: "=m" (rw->lock), "=&r" (tmp)
-	: "m" (rw->lock)
-	: "memory");
+	if (R10000_LLSC_WAR) {
+		__asm__ __volatile__(
+		"	.set	noreorder	# _raw_write_lock	\n"
+		"1:	ll	%1, %2					\n"
+		"	bnez	%1, 1b					\n"
+		"	 lui	%1, 0x8000				\n"
+		"	sc	%1, %0					\n"
+		"	beqzl	%1, 1b					\n"
+		"	 nop						\n"
+		"	sync						\n"
+		"	.set	reorder					\n"
+		: "=m" (rw->lock), "=&r" (tmp)
+		: "m" (rw->lock)
+		: "memory");
+	} else {
+		__asm__ __volatile__(
+		"	.set	noreorder	# _raw_write_lock	\n"
+		"1:	ll	%1, %2					\n"
+		"	bnez	%1, 1b					\n"
+		"	 lui	%1, 0x8000				\n"
+		"	sc	%1, %0					\n"
+		"	beqz	%1, 1b					\n"
+		"	 nop						\n"
+		"	sync						\n"
+		"	.set	reorder					\n"
+		: "=m" (rw->lock), "=&r" (tmp)
+		: "m" (rw->lock)
+		: "memory");
+	}
 }
 
 static inline void _raw_write_unlock(rwlock_t *rw)
 {
 	__asm__ __volatile__(
-	".set\tnoreorder\t\t\t# _raw_write_unlock\n\t"
-	"sync\n\t"
-	"sw\t$0, %0\n\t"
-	".set\treorder"
+	"	sync			# _raw_write_unlock	\n"
+	"	sw	$0, %0					\n"
 	: "=m" (rw->lock)
 	: "m" (rw->lock)
 	: "memory");
@@ -173,21 +251,40 @@ static inline int _raw_write_trylock(rwlock_t *rw)
 	unsigned int tmp;
 	int ret;
 
-	__asm__ __volatile__(
-	".set\tnoreorder\t\t\t# _raw_write_trylock\n"
-	"li\t%2, 0\n\t"
-	"1:\tll\t%1, %3\n\t"
-	"bnez\t%1, 2f\n\t"
-	"lui\t%1, 0x8000\n\t"
-	"sc\t%1, %0\n\t"
-	"beqz\t%1, 1b\n\t"
-	"sync\n\t"
-	"li\t%2, 1\n\t"
-	".set\treorder\n"
-	"2:"
-	: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
-	: "m" (rw->lock)
-	: "memory");
+	if (R10000_LLSC_WAR) {
+		__asm__ __volatile__(
+		"	.set	noreorder	# _raw_write_trylock	\n"
+		"	li	%2, 0					\n"
+		"1:	ll	%1, %3					\n"
+		"	bnez	%1, 2f					\n"
+		"	 lui	%1, 0x8000				\n"
+		"	sc	%1, %0					\n"
+		"	beqzl	%1, 1b					\n"
+		"	 nop						\n"
+		"	sync						\n"
+		"	li	%2, 1					\n"
+		"	.set	reorder					\n"
+		"2:							\n"
+		: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+		: "m" (rw->lock)
+		: "memory");
+	} else {
+		__asm__ __volatile__(
+		"	.set	noreorder	# _raw_write_trylock	\n"
+		"	li	%2, 0					\n"
+		"1:	ll	%1, %3					\n"
+		"	bnez	%1, 2f					\n"
+		"	lui	%1, 0x8000				\n"
+		"	sc	%1, %0					\n"
+		"	beqz	%1, 1b					\n"
+		"	 sync						\n"
+		"	li	%2, 1					\n"
+		"	.set	reorder					\n"
+		"2:							\n"
+		: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
+		: "m" (rw->lock)
+		: "memory");
+	}
 
 	return ret;
 }
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 53a441c3cb3b..acf55526f356 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -68,7 +68,7 @@
 		MFC0	k1, CP0_CONTEXT
 		dsra	k1, 23
 		lui	k0, %hi(pgd_current)
-		daddiu	k0, %lo(pgd_current)
+		addiu	k0, %lo(pgd_current)
 		dsubu	k1, k0
 		lui	k0, %hi(kernelsp)
 		daddu	k1, k0
diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h
index ef15465abdf9..5076fec65780 100644
--- a/include/asm-mips/statfs.h
+++ b/include/asm-mips/statfs.h
@@ -28,9 +28,9 @@ struct statfs {
 	long		f_bfree;
 	long		f_files;
 	long		f_ffree;
+	long		f_bavail;
 
 	/* Linux specials */
-	long	f_bavail;
 	__kernel_fsid_t	f_fsid;
 	long		f_namelen;
 	long		f_spare[6];
@@ -44,15 +44,16 @@ struct statfs {
 struct statfs64 {
 	__u32	f_type;
 	__u32	f_bsize;
+	__u32	f_frsize;	/* Fragment size - unsupported */
+	__u32	__pad;
 	__u64	f_blocks;
 	__u64	f_bfree;
-	__u64	f_bavail;
 	__u64	f_files;
 	__u64	f_ffree;
+	__u64	f_bavail;
 	__kernel_fsid_t f_fsid;
 	__u32	f_namelen;
-	__u32	f_frsize;
-	__u32	f_spare[5];
+	__u32	f_spare[6];
 };
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
@@ -67,26 +68,27 @@ struct statfs64 {			/* Same as struct statfs */
 	long		f_bfree;
 	long		f_files;
 	long		f_ffree;
+	long		f_bavail;
 
 	/* Linux specials */
-	long	f_bavail;
 	__kernel_fsid_t	f_fsid;
 	long		f_namelen;
 	long		f_spare[6];
 };
 
 struct compat_statfs64 {
-	__u32 f_type;
-	__u32 f_bsize;
-	__u64 f_blocks;
-	__u64 f_bfree;
-	__u64 f_bavail;
-	__u64 f_files;
-	__u64 f_ffree;
+	__u32	f_type;
+	__u32	f_bsize;
+	__u32	f_frsize;	/* Fragment size - unsupported */
+	__u32	__pad;
+	__u64	f_blocks;
+	__u64	f_bfree;
+	__u64	f_files;
+	__u64	f_ffree;
+	__u64	f_bavail;
 	__kernel_fsid_t f_fsid;
-	__u32 f_namelen;
-	__u32 f_frsize;
-	__u32 f_spare[5];
+	__u32	f_namelen;
+	__u32	f_spare[6];
 };
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 9bacd119796b..a421cdb1e0da 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -13,131 +13,13 @@
 #define _ASM_SYSTEM_H
 
 #include <linux/config.h>
-#include <asm/sgidefs.h>
-
-#include <linux/kernel.h>
+#include <linux/types.h>
 
 #include <asm/addrspace.h>
+#include <asm/cpu-features.h>
 #include <asm/ptrace.h>
-#include <asm/hazards.h>
-
-__asm__ (
-	".macro\tlocal_irq_enable\n\t"
-	".set\tpush\n\t"
-	".set\treorder\n\t"
-	".set\tnoat\n\t"
-	"mfc0\t$1,$12\n\t"
-	"ori\t$1,0x1f\n\t"
-	"xori\t$1,0x1e\n\t"
-	"mtc0\t$1,$12\n\t"
-	"irq_enable_hazard\n\t"
-	".set\tpop\n\t"
-	".endm");
-
-static inline void local_irq_enable(void)
-{
-	__asm__ __volatile__(
-		"local_irq_enable"
-		: /* no outputs */
-		: /* no inputs */
-		: "memory");
-}
-
-/*
- * For cli() we have to insert nops to make sure that the new value
- * has actually arrived in the status register before the end of this
- * macro.
- * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
- * no nops at all.
- */
-__asm__ (
-	".macro\tlocal_irq_disable\n\t"
-	".set\tpush\n\t"
-	".set\tnoat\n\t"
-	"mfc0\t$1,$12\n\t"
-	"ori\t$1,1\n\t"
-	"xori\t$1,1\n\t"
-	".set\tnoreorder\n\t"
-	"mtc0\t$1,$12\n\t"
-	"irq_disable_hazard\n\t"
-	".set\tpop\n\t"
-	".endm");
-
-static inline void local_irq_disable(void)
-{
-	__asm__ __volatile__(
-		"local_irq_disable"
-		: /* no outputs */
-		: /* no inputs */
-		: "memory");
-}
-
-__asm__ (
-	".macro\tlocal_save_flags flags\n\t"
-	".set\tpush\n\t"
-	".set\treorder\n\t"
-	"mfc0\t\\flags, $12\n\t"
-	".set\tpop\n\t"
-	".endm");
-
-#define local_save_flags(x)						\
-__asm__ __volatile__(							\
-	"local_save_flags %0"						\
-	: "=r" (x))
-
-__asm__ (
-	".macro\tlocal_irq_save result\n\t"
-	".set\tpush\n\t"
-	".set\treorder\n\t"
-	".set\tnoat\n\t"
-	"mfc0\t\\result, $12\n\t"
-	"ori\t$1, \\result, 1\n\t"
-	"xori\t$1, 1\n\t"
-	".set\tnoreorder\n\t"
-	"mtc0\t$1, $12\n\t"
-	"irq_disable_hazard\n\t"
-	".set\tpop\n\t"
-	".endm");
-
-#define local_irq_save(x)						\
-__asm__ __volatile__(							\
-	"local_irq_save\t%0"						\
-	: "=r" (x)							\
-	: /* no inputs */						\
-	: "memory")
-
-__asm__ (
-	".macro\tlocal_irq_restore flags\n\t"
-	".set\tnoreorder\n\t"
-	".set\tnoat\n\t"
-	"mfc0\t$1, $12\n\t"
-	"andi\t\\flags, 1\n\t"
-	"ori\t$1, 1\n\t"
-	"xori\t$1, 1\n\t"
-	"or\t\\flags, $1\n\t"
-	"mtc0\t\\flags, $12\n\t"
-	"irq_disable_hazard\n\t"
-	".set\tat\n\t"
-	".set\treorder\n\t"
-	".endm");
-
-#define local_irq_restore(flags)					\
-do {									\
-	unsigned long __tmp1;						\
-									\
-	__asm__ __volatile__(						\
-		"local_irq_restore\t%0"					\
-		: "=r" (__tmp1)						\
-		: "0" (flags)						\
-		: "memory");						\
-} while(0)
-
-#define irqs_disabled()							\
-({									\
-	unsigned long flags;						\
-	local_save_flags(flags);					\
-	!(flags & 1);							\
-})
+#include <asm/war.h>
+#include <asm/interrupt.h>
 
 /*
  * read_barrier_depends - Flush all pending reads that subsequents reads
@@ -277,37 +159,51 @@ do { \
 	(last) = resume(prev, next, next->thread_info); \
 } while(0)
 
+#define ROT_IN_PIECES							\
+	"	.set	noreorder	\n"				\
+	"	.set	reorder		\n"
+
 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 {
 	__u32 retval;
 
-#ifdef CONFIG_CPU_HAS_LLSC
-	unsigned long dummy;
-
-	__asm__ __volatile__(
-		".set\tpush\t\t\t\t# xchg_u32\n\t"
-		".set\tnoreorder\n\t"
-		".set\tnomacro\n\t"
-		"ll\t%0, %3\n"
-		"1:\tmove\t%2, %z4\n\t"
-		"sc\t%2, %1\n\t"
-		"beqzl\t%2, 1b\n\t"
-		" ll\t%0, %3\n\t"
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long dummy;
+
+		__asm__ __volatile__(
+		"1:	ll	%0, %3			# xchg_u32	\n"
+		"	move	%2, %z4					\n"
+		"	sc	%2, %1					\n"
+		"	beqzl	%2, 1b					\n"
+		ROT_IN_PIECES
 #ifdef CONFIG_SMP
-		"sync\n\t"
+		"	sync						\n"
 #endif
-		".set\tpop"
 		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
 		: "R" (*m), "Jr" (val)
 		: "memory");
-#else
-	unsigned long flags;
-
-	local_irq_save(flags);
-	retval = *m;
-	*m = val;
-	local_irq_restore(flags);	/* implies memory barrier  */
+	} else if (cpu_has_llsc) {
+		unsigned long dummy;
+
+		__asm__ __volatile__(
+		"1:	ll	%0, %3			# xchg_u32	\n"
+		"	move	%2, %z4					\n"
+		"	sc	%2, %1					\n"
+		"	beqz	%2, 1b					\n"
+#ifdef CONFIG_SMP
+		"	sync						\n"
 #endif
+		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
+		: "R" (*m), "Jr" (val)
+		: "memory");
+	} else {
+		unsigned long flags;
+
+		local_irq_save(flags);
+		retval = *m;
+		*m = val;
+		local_irq_restore(flags);	/* implies memory barrier  */
+	}
 
 	return retval;
 }
@@ -317,33 +213,43 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 {
 	__u64 retval;
 
-#ifdef CONFIG_CPU_HAS_LLDSCD
-	unsigned long dummy;
-
-	__asm__ __volatile__(
-		".set\tpush\t\t\t\t# xchg_u64\n\t"
-		".set\tnoreorder\n\t"
-		".set\tnomacro\n\t"
-		"lld\t%0, %3\n"
-		"1:\tmove\t%2, %z4\n\t"
-		"scd\t%2, %1\n\t"
-		"beqzl\t%2, 1b\n\t"
-		" lld\t%0, %3\n\t"
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		unsigned long dummy;
+
+		__asm__ __volatile__(
+		"1:	lld	%0, %3			# xchg_u64	\n"
+		"	move	%2, %z4					\n"
+		"	scd	%2, %1					\n"
+		"	beqzl	%2, 1b					\n"
+		ROT_IN_PIECES
 #ifdef CONFIG_SMP
-		"sync\n\t"
+		"	sync						\n"
 #endif
-		".set\tpop"
 		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
 		: "R" (*m), "Jr" (val)
 		: "memory");
-#else
-	unsigned long flags;
-
-	local_irq_save(flags);
-	retval = *m;
-	*m = val;
-	local_irq_restore(flags);	/* implies memory barrier  */
+	} else if (cpu_has_llsc) {
+		unsigned long dummy;
+
+		__asm__ __volatile__(
+		"1:	lld	%0, %3			# xchg_u64	\n"
+		"	move	%2, %z4					\n"
+		"	scd	%2, %1					\n"
+		"	beqz	%2, 1b					\n"
+#ifdef CONFIG_SMP
+		"	sync						\n"
 #endif
+		: "=&r" (retval), "=m" (*m), "=&r" (dummy)
+		: "R" (*m), "Jr" (val)
+		: "memory");
+	} else {
+		unsigned long flags;
+
+		local_irq_save(flags);
+		retval = *m;
+		*m = val;
+		local_irq_restore(flags);	/* implies memory barrier  */
+	}
 
 	return retval;
 }
@@ -378,31 +284,48 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
 {
 	__u32 retval;
 
-#ifdef CONFIG_CPU_HAS_LLSC
-	__asm__ __volatile__(
-	"	.set	noat					\n"
-	"1:	ll	%0, %2			# __cmpxchg_u32	\n"
-	"	bne	%0, %z3, 2f				\n"
-	"	move	$1, %z4					\n"
-	"	sc	$1, %1					\n"
-	"	beqz	$1, 1b					\n"
+	if (cpu_has_llsc && R10000_LLSC_WAR) {
+		__asm__ __volatile__(
+		"	.set	noat					\n"
+		"1:	ll	%0, %2			# __cmpxchg_u32	\n"
+		"	bne	%0, %z3, 2f				\n"
+		"	move	$1, %z4					\n"
+		"	sc	$1, %1					\n"
+		"	beqzl	$1, 1b					\n"
+		ROT_IN_PIECES
 #ifdef CONFIG_SMP
-	"	sync						\n"
+		"	sync						\n"
 #endif
-	"2:							\n"
-	"	.set	at					\n"
-	: "=&r" (retval), "=m" (*m)
-	: "R" (*m), "Jr" (old), "Jr" (new)
-	: "memory");
-#else
-	unsigned long flags;
-
-	local_irq_save(flags);
-	retval = *m;
-	if (retval == old)
-		*m = new;
-	local_irq_restore(flags);	/* implies memory barrier  */
+		"2:							\n"
+		"	.set	at					\n"
+		: "=&r" (retval), "=m" (*m)
+		: "R" (*m), "Jr" (old), "Jr" (new)
+		: "memory");
+	} else if (cpu_has_llsc) {
+		__asm__ __volatile__(
+		"	.set	noat					\n"
+		"1:	ll	%0, %2			# __cmpxchg_u32	\n"
+		"	bne	%0, %z3, 2f				\n"
+		"	move	$1, %z4					\n"
+		"	sc	$1, %1					\n"
+		"	beqz	$1, 1b					\n"
+#ifdef CONFIG_SMP
+		"	sync						\n"
 #endif
+		"2:							\n"
+		"	.set	at					\n"
+		: "=&r" (retval), "=m" (*m)
+		: "R" (*m), "Jr" (old), "Jr" (new)
+		: "memory");
+	} else {
+		unsigned long flags;
+
+		local_irq_save(flags);
+		retval = *m;
+		if (retval == old)
+			*m = new;
+		local_irq_restore(flags);	/* implies memory barrier  */
+	}
 
 	return retval;
 }
@@ -413,31 +336,48 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
 {
 	__u64 retval;
 
-#ifdef CONFIG_CPU_HAS_LLDSCD
-	__asm__ __volatile__(
-	"	.set	noat					\n"
-	"1:	lld	%0, %2			# __cmpxchg_u64	\n"
-	"	bne	%0, %z3, 2f				\n"
-	"	move	$1, %z4					\n"
-	"	scd	$1, %1					\n"
-	"	beqz	$1, 1b					\n"
+	if (cpu_has_llsc) {
+		__asm__ __volatile__(
+		"	.set	noat					\n"
+		"1:	lld	%0, %2			# __cmpxchg_u64	\n"
+		"	bne	%0, %z3, 2f				\n"
+		"	move	$1, %z4					\n"
+		"	scd	$1, %1					\n"
+		"	beqzl	$1, 1b					\n"
+		ROT_IN_PIECES
 #ifdef CONFIG_SMP
-	"	sync						\n"
+		"	sync						\n"
 #endif
-	"2:							\n"
-	"	.set	at					\n"
-	: "=&r" (retval), "=m" (*m)
-	: "R" (*m), "Jr" (old), "Jr" (new)
-	: "memory");
-#else
-	unsigned long flags;
-
-	local_irq_save(flags);
-	retval = *m;
-	if (retval == old)
-		*m = new;
-	local_irq_restore(flags);	/* implies memory barrier  */
+		"2:							\n"
+		"	.set	at					\n"
+		: "=&r" (retval), "=m" (*m)
+		: "R" (*m), "Jr" (old), "Jr" (new)
+		: "memory");
+	} else if (cpu_has_llsc) {
+		__asm__ __volatile__(
+		"	.set	noat					\n"
+		"1:	lld	%0, %2			# __cmpxchg_u64	\n"
+		"	bne	%0, %z3, 2f				\n"
+		"	move	$1, %z4					\n"
+		"	scd	$1, %1					\n"
+		"	beqz	$1, 1b					\n"
+#ifdef CONFIG_SMP
+		"	sync						\n"
 #endif
+		"2:							\n"
+		"	.set	at					\n"
+		: "=&r" (retval), "=m" (*m)
+		: "R" (*m), "Jr" (old), "Jr" (new)
+		: "memory");
+	} else {
+		unsigned long flags;
+
+		local_irq_save(flags);
+		retval = *m;
+		if (retval == old)
+			*m = new;
+		local_irq_restore(flags);	/* implies memory barrier  */
+	}
 
 	return retval;
 }
@@ -479,14 +419,8 @@ extern void __die_if_kernel(const char *, struct pt_regs *, const char *file,
 #define die_if_kernel(msg, regs)					\
 	__die_if_kernel(msg, regs, __FILE__ ":", __FUNCTION__, __LINE__)
 
-extern int serial_console;
 extern int stop_a_enabled;
 
-static __inline__ int con_is_present(void)
-{
-	return serial_console ? 0 : 1;
-}
-
 /*
  * Taken from include/asm-ia64/system.h; prevents deadlock on SMP
  * systems.
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h
index 508b32ad330a..5f3b64875add 100644
--- a/include/asm-mips/thread_info.h
+++ b/include/asm-mips/thread_info.h
@@ -101,7 +101,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
 
 #endif /* !__ASSEMBLY__ */
 
-#define PREEMPT_ACTIVE		0x4000000
+#define PREEMPT_ACTIVE		0x10000000
 
 /*
  * thread information flags
diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h
index d820445e8ead..fd9599e40a0a 100644
--- a/include/asm-mips/titan_dep.h
+++ b/include/asm-mips/titan_dep.h
@@ -16,25 +16,19 @@
 #include <asm/addrspace.h>              /* for KSEG1ADDR() */
 #include <asm/byteorder.h>              /* for cpu_to_le32() */
 
-/* PCI */
-#define	TITAN_PCI_BASE			0xbb000000
-
-#define TITAN_WRITE(ofs, data)  \
-        *(volatile u32 *)(TITAN_PCI_BASE+(ofs)) = cpu_to_le32(data)
-#define TITAN_READ(ofs, data)   \
-        *(data) = le32_to_cpu(*(volatile u32 *)(TITAN_PCI_BASE+(ofs)))
-#define TITAN_READ_DATA(ofs)    \
-        le32_to_cpu(*(volatile u32 *)(TITAN_PCI_BASE+(ofs)))
-
-#define TITAN_WRITE_16(ofs, data)  \
-        *(volatile u16 *)(TITAN_PCI_BASE+(ofs)) = cpu_to_le16(data)
-#define TITAN_READ_16(ofs, data)   \
-        *(data) = le16_to_cpu(*(volatile u16 *)(TITAN_PCI_BASE+(ofs)))
-
-#define TITAN_WRITE_8(ofs, data)  \
-        *(volatile u8 *)(TITAN_PCI_BASE+(ofs)) = data
-#define TITAN_READ_8(ofs, data)   \
-        *(data) = *(volatile u8 *)(TITAN_PCI_BASE+(ofs))
+#define TITAN_READ(ofs)							\
+	(*(volatile u32 *)(ocd_base+(ofs)))
+#define TITAN_READ_16(ofs)						\
+	(*(volatile u16 *)(ocd_base+(ofs)))
+#define TITAN_READ_8(ofs)						\
+	(*(volatile u8 *)(ocd_base+(ofs)))
+
+#define TITAN_WRITE(ofs, data)						\
+	do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
+#define TITAN_WRITE_16(ofs, data)					\
+	do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
+#define TITAN_WRITE_8(ofs, data)					\
+	do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
 
 /*
  * PCI specific defines
@@ -45,11 +39,11 @@
 /*
  * HT specific defines
  */
-#define RM9000x2_HTLINK_REG     0xbb000644
-#define RM9000x2_BASE_ADDR      0xbb000000
+#define RM9000x2_HTLINK_REG		0xbb000644
+#define RM9000x2_BASE_ADDR		0xbb000000
 
-#define OCD_BASE                0xfb000000UL
-#define OCD_SIZE                0x3000UL
+#define OCD_BASE			0xfb000000UL
+#define OCD_SIZE			0x3000UL
 
 extern unsigned long ocd_base;
 
diff --git a/include/asm-mips/tx4927/smsc_fdc37m81x.h b/include/asm-mips/tx4927/smsc_fdc37m81x.h
new file mode 100644
index 000000000000..5d93bab51254
--- /dev/null
+++ b/include/asm-mips/tx4927/smsc_fdc37m81x.h
@@ -0,0 +1,69 @@
+/*
+ * linux/include/asm-mips/tx4927/smsc_fdc37m81x.h
+ *
+ * Interface for smsc fdc48m81x Super IO chip
+ *
+ * Author: MontaVista Software, Inc. source@mvista.com
+ *
+ * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ *
+ * Copyright (C) 2004 MontaVista Software Inc.
+ * Manish Lachwani, mlachwani@mvista.com
+ */
+
+#ifndef _SMSC_FDC37M81X_H_
+#define _SMSC_FDC37M81X_H_
+
+/* Common Registers */
+#define SMSC_FDC37M81X_CONFIG_INDEX  0x00
+#define SMSC_FDC37M81X_CONFIG_DATA   0x01
+#define SMSC_FDC37M81X_CONF          0x02
+#define SMSC_FDC37M81X_INDEX         0x03
+#define SMSC_FDC37M81X_DNUM          0x07
+#define SMSC_FDC37M81X_DID           0x20
+#define SMSC_FDC37M81X_DREV          0x21
+#define SMSC_FDC37M81X_PCNT          0x22
+#define SMSC_FDC37M81X_PMGT          0x23
+#define SMSC_FDC37M81X_OSC           0x24
+#define SMSC_FDC37M81X_CONFPA0       0x26
+#define SMSC_FDC37M81X_CONFPA1       0x27
+#define SMSC_FDC37M81X_TEST4         0x2B
+#define SMSC_FDC37M81X_TEST5         0x2C
+#define SMSC_FDC37M81X_TEST1         0x2D
+#define SMSC_FDC37M81X_TEST2         0x2E
+#define SMSC_FDC37M81X_TEST3         0x2F
+
+/* Logical device numbers */
+#define SMSC_FDC37M81X_FDD           0x00
+#define SMSC_FDC37M81X_PARALLEL      0x03
+#define SMSC_FDC37M81X_SERIAL1       0x04
+#define SMSC_FDC37M81X_SERIAL2       0x05
+#define SMSC_FDC37M81X_KBD           0x07
+#define SMSC_FDC37M81X_AUXIO         0x08
+#define SMSC_FDC37M81X_NONE          0xff
+
+/* Logical device Config Registers */
+#define SMSC_FDC37M81X_ACTIVE        0x30
+#define SMSC_FDC37M81X_BASEADDR0     0x60
+#define SMSC_FDC37M81X_BASEADDR1     0x61
+#define SMSC_FDC37M81X_INT           0x70
+#define SMSC_FDC37M81X_INT2          0x72
+#define SMSC_FDC37M81X_LDCR_F0       0xF0
+
+/* Chip Config Values */
+#define SMSC_FDC37M81X_CONFIG_ENTER  0x55
+#define SMSC_FDC37M81X_CONFIG_EXIT   0xaa
+#define SMSC_FDC37M81X_CHIP_ID       0x4d
+
+unsigned long __init smsc_fdc37m81x_init(unsigned long port);
+
+void smsc_fdc37m81x_config_beg(void);
+
+void smsc_fdc37m81x_config_end(void);
+
+void smsc_fdc37m81x_config_set(u8 reg, u8 val);
+
+#endif
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index 7116b0bc277c..5d939db6e220 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -88,8 +88,8 @@
 
 
 /* TX4927 Configuration registers (64-bit registers) */
-#define TX4927_CONFIG_BASE                       0xe300
-#define TX4927_CONFIG_CCFG                       0xe300
+#define TX4927_CONFIG_BASE                       0xe000
+#define TX4927_CONFIG_CCFG                       0xe000
 #define TX4927_CONFIG_CCFG_RESERVED_42_63                BM_63_42
 #define TX4927_CONFIG_CCFG_WDRST                         BM_41_41
 #define TX4927_CONFIG_CCFG_WDREXEN                       BM_40_40
@@ -124,14 +124,14 @@
 #define TX4927_CONFIG_CCFG_ENDIAN                        BM_02_02
 #define TX4927_CONFIG_CCFG_ARMODE                        BM_01_01
 #define TX4927_CONFIG_CCFG_ACEHOLD                       BM_00_00
-#define TX4927_CONFIG_REVID                      0xe308 
+#define TX4927_CONFIG_REVID                      0xe008
 #define TX4927_CONFIG_REVID_RESERVED_32_63               BM_32_63
 #define TX4927_CONFIG_REVID_PCODE                        BM_16_31
 #define TX4927_CONFIG_REVID_MJERREV                      BM_12_15
 #define TX4927_CONFIG_REVID_MINEREV                      BM_08_11
 #define TX4927_CONFIG_REVID_MJREV                        BM_04_07
 #define TX4927_CONFIG_REVID_MINREV                       BM_00_03
-#define TX4927_CONFIG_PCFG                       0xe310 
+#define TX4927_CONFIG_PCFG                       0xe010
 #define TX4927_CONFIG_PCFG_RESERVED_57_63                BM_57_63
 #define TX4927_CONFIG_PCFG_DRVDATA                       BM_56_56
 #define TX4927_CONFIG_PCFG_DRVCB                         BM_55_55
@@ -197,10 +197,10 @@
 #define TX4927_CONFIG_PCFG_DMASEL0_SIO1                  BM_00_00
 #define TX4927_CONFIG_PCFG_DMASEL0_ACLC0                 BM_01_01
 #define TX4927_CONFIG_PCFG_DMASEL0_ACLC2                 BM_00_01
-#define TX4927_CONFIG_TOEA                       0xe318 
+#define TX4927_CONFIG_TOEA                       0xe018
 #define TX4927_CONFIG_TOEA_RESERVED_36_63                BM_36_63
 #define TX4927_CONFIG_TOEA_TOEA                          BM_00_35
-#define TX4927_CONFIG_CLKCTR                     0xe320 
+#define TX4927_CONFIG_CLKCTR                     0xe020
 #define TX4927_CONFIG_CLKCTR_RESERVED_26_63              BM_26_63
 #define TX4927_CONFIG_CLKCTR_ACLCKD                      BM_25_25
 #define TX4927_CONFIG_CLKCTR_PIOCKD                      BM_24_24
@@ -223,7 +223,7 @@
 #define TX4927_CONFIG_CLKCTR_TM2RST                      BM_02_02
 #define TX4927_CONFIG_CLKCTR_SIO0RST                     BM_01_01
 #define TX4927_CONFIG_CLKCTR_SIO1RST                     BM_00_00
-#define TX4927_CONFIG_GARBC                      0xe330 
+#define TX4927_CONFIG_GARBC                      0xe030
 #define TX4927_CONFIG_GARBC_RESERVED_10_63               BM_10_63
 #define TX4927_CONFIG_GARBC_SET_09                       BM_09_09
 #define TX4927_CONFIG_GARBC_ARBMD                        BM_08_08
@@ -243,7 +243,7 @@
 #define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC            BM_00_00
 #define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC             BM_01_01
 #define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE        BM_00_01
-#define TX4927_CONFIG_RAMP                       0xe348 
+#define TX4927_CONFIG_RAMP                       0xe048
 #define TX4927_CONFIG_RAMP_RESERVED_20_63                BM_20_63
 #define TX4927_CONFIG_RAMP_RAMP                          BM_00_19
 #define TX4927_CONFIG_LIMIT                      0xefff
@@ -456,7 +456,7 @@
 #define TX4927_ACLC_ACINTSTS            0xf710
 #define TX4927_ACLC_ACINTMSTS           0xf714
 #define TX4927_ACLC_ACINTEN             0xf718
-#define TX4927_ACLC_ACINTDIS            0xfR71c
+#define TX4927_ACLC_ACINTDIS            0xf71c
 #define TX4927_ACLC_ACSEMAPH            0xf720
 #define TX4927_ACLC_ACGPIDAT            0xf740
 #define TX4927_ACLC_ACGPODAT            0xf744
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index adbb24bd920f..2f0328aab718 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -10,7 +10,7 @@
 #define _ASM_UACCESS_H
 
 #include <linux/config.h>
-#include <linux/compiler.h>
+#include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/thread_info.h>
 #include <asm-generic/uaccess.h>
@@ -225,89 +225,89 @@ struct __large_struct { unsigned long buf[100]; };
  * for 32 bit mode and old iron.
  */
 #ifdef __mips64
-#define __GET_USER_DW __get_user_asm("ld")
+#define __GET_USER_DW(__gu_err) __get_user_asm("ld", __gu_err)
 #else
-#define __GET_USER_DW __get_user_asm_ll32
+#define __GET_USER_DW(__gu_err) __get_user_asm_ll32(__gu_err)
 #endif
 
-#define __get_user_nocheck(x,ptr,size)				\
-({								\
-	long __gu_err;						\
-	__typeof(*(ptr)) __gu_val;				\
-	long __gu_addr;						\
-	might_sleep();						\
-	__asm__("":"=r" (__gu_val));				\
-	__gu_addr = (long) (ptr);				\
-	__asm__("":"=r" (__gu_err));				\
-	switch (size) {						\
-	case 1: __get_user_asm("lb"); break;			\
-	case 2: __get_user_asm("lh"); break;			\
-	case 4: __get_user_asm("lw"); break;			\
-	case 8: __GET_USER_DW; break;				\
-	default: __get_user_unknown(); break;			\
-	} x = (__typeof__(*(ptr))) __gu_val; __gu_err;		\
+#define __get_user_nocheck(x,ptr,size)					\
+({									\
+	long __gu_err = 0;						\
+	__typeof(*(ptr)) __gu_val = 0;					\
+	long __gu_addr;							\
+	might_sleep();							\
+	__gu_addr = (long) (ptr);					\
+	switch (size) {							\
+	case 1: __get_user_asm("lb", __gu_err); break;			\
+	case 2: __get_user_asm("lh", __gu_err); break;			\
+	case 4: __get_user_asm("lw", __gu_err); break;			\
+	case 8: __GET_USER_DW(__gu_err); break;				\
+	default: __get_user_unknown(); break;				\
+	}								\
+	 x = (__typeof__(*(ptr))) __gu_val;				\
+	__gu_err;							\
 })
 
 #define __get_user_check(x,ptr,size)					\
 ({									\
+	__typeof__(*(ptr)) __gu_val = 0;				\
+	long __gu_addr = (long) (ptr);					\
 	long __gu_err;							\
-	__typeof__(*(ptr)) __gu_val;					\
-	long __gu_addr;							\
+									\
 	might_sleep();							\
-	__asm__("":"=r" (__gu_val));					\
-	__gu_addr = (long) (ptr);					\
-	__asm__("":"=r" (__gu_err));					\
-	if (access_ok(VERIFY_READ,__gu_addr,size)) {			\
+	__gu_err = verify_area(VERIFY_READ, (void *) __gu_addr, size);	\
+									\
+	if (likely(!__gu_err)) {					\
 		switch (size) {						\
-		case 1: __get_user_asm("lb"); break;			\
-		case 2: __get_user_asm("lh"); break;			\
-		case 4: __get_user_asm("lw"); break;			\
-		case 8: __GET_USER_DW; break;				\
+		case 1: __get_user_asm("lb", __gu_err); break;		\
+		case 2: __get_user_asm("lh", __gu_err); break;		\
+		case 4: __get_user_asm("lw", __gu_err); break;		\
+		case 8: __GET_USER_DW(__gu_err); break;			\
 		default: __get_user_unknown(); break;			\
 		}							\
-	} x = (__typeof__(*(ptr))) __gu_val; __gu_err;			\
+	}								\
+	x = (__typeof__(*(ptr))) __gu_val;				\
+	 __gu_err;							\
 })
 
-#define __get_user_asm(insn)						\
+#define __get_user_asm(insn,__gu_err)					\
 ({									\
 	__asm__ __volatile__(						\
-	"1:\t" insn "\t%1,%2\n\t"					\
-	"move\t%0,$0\n"							\
-	"2:\n\t"							\
-	".section\t.fixup,\"ax\"\n"					\
-	"3:\tli\t%0,%3\n\t"						\
-	"move\t%1,$0\n\t"						\
-	"j\t2b\n\t"							\
-	".previous\n\t"							\
-	".section\t__ex_table,\"a\"\n\t"				\
-	__UA_ADDR "\t1b,3b\n\t"						\
-	".previous"							\
-	:"=r" (__gu_err), "=r" (__gu_val)				\
-	:"o" (__m(__gu_addr)), "i" (-EFAULT));				\
+	"1:	" insn "	%1, %3				\n"	\
+	"2:							\n"	\
+	"	.section .fixup,\"ax\"				\n"	\
+	"3:	li	%0, %4					\n"	\
+	"	j	2b					\n"	\
+	"	.previous					\n"	\
+	"	.section __ex_table,\"a\"			\n"	\
+	"	"__UA_ADDR "\t1b, 3b				\n"	\
+	"	.previous					\n"	\
+	: "=r" (__gu_err), "=r" (__gu_val)				\
+	: "0" (__gu_err), "o" (__m(__gu_addr)), "i" (-EFAULT));		\
 })
 
 /*
  * Get a long long 64 using 32 bit registers.
  */
-#define __get_user_asm_ll32						\
+#define __get_user_asm_ll32(__gu_err)					\
 ({									\
 	__asm__ __volatile__(						\
-	"1:\tlw\t%1,%2\n"						\
-	"2:\tlw\t%D1,%3\n\t"						\
-	"move\t%0,$0\n"							\
-	"3:\t.section\t.fixup,\"ax\"\n"					\
-	"4:\tli\t%0,%4\n\t"						\
-	"move\t%1,$0\n\t"						\
-	"move\t%D1,$0\n\t"						\
-	"j\t3b\n\t"							\
-	".previous\n\t"							\
-	".section\t__ex_table,\"a\"\n\t"				\
-	__UA_ADDR "\t1b,4b\n\t"						\
-	__UA_ADDR "\t2b,4b\n\t"						\
-	".previous"							\
-	:"=r" (__gu_err), "=&r" (__gu_val)				\
-	:"o" (__m(__gu_addr)), "o" (__m(__gu_addr + 4)),		\
-	 "i" (-EFAULT));						\
+	"1:	lw	%1, %3					\n"	\
+	"2:	lw	%D1, %4					\n"	\
+	"	move	%0, $0					\n"	\
+	"3:	.section	.fixup,\"ax\"			\n"	\
+	"4:	li	%0, %5					\n"	\
+	"	move	%1, $0					\n"	\
+	"	move	%D1, $0					\n"	\
+	"	j	3b					\n"	\
+	"	.previous					\n"	\
+	"	.section	__ex_table,\"a\"		\n"	\
+	"	" __UA_ADDR "	1b, 4b				\n"	\
+	"	" __UA_ADDR "	2b, 4b				\n"	\
+	"	.previous					\n"	\
+	: "=r" (__gu_err), "=&r" (__gu_val)				\
+	: "0" (__gu_err), "o" (__m(__gu_addr)),				\
+	  "o" (__m(__gu_addr + 4)), "i" (-EFAULT));			\
 })
 
 extern void __get_user_unknown(void);
@@ -317,25 +317,24 @@ extern void __get_user_unknown(void);
  * for 32 bit mode and old iron.
  */
 #ifdef __mips64
-#define __PUT_USER_DW __put_user_asm("sd")
+#define __PUT_USER_DW(__pu_val) __put_user_asm("sd", __pu_val)
 #else
-#define __PUT_USER_DW __put_user_asm_ll32
+#define __PUT_USER_DW(__pu_val) __put_user_asm_ll32(__pu_val)
 #endif
 
 #define __put_user_nocheck(x,ptr,size)					\
 ({									\
-	long __pu_err;							\
+	long __pu_err = 0;						\
 	__typeof__(*(ptr)) __pu_val;					\
 	long __pu_addr;							\
 	might_sleep();							\
 	__pu_val = (x);							\
 	__pu_addr = (long) (ptr);					\
-	__asm__("":"=r" (__pu_err));					\
 	switch (size) {							\
-	case 1: __put_user_asm("sb"); break;				\
-	case 2: __put_user_asm("sh"); break;				\
-	case 4: __put_user_asm("sw"); break;				\
-	case 8: __PUT_USER_DW; break;					\
+	case 1: __put_user_asm("sb", __pu_val); break;			\
+	case 2: __put_user_asm("sh", __pu_val); break;			\
+	case 4: __put_user_asm("sw", __pu_val); break;			\
+	case 8: __PUT_USER_DW(__pu_val); break;				\
 	default: __put_user_unknown(); break;				\
 	}								\
 	__pu_err;							\
@@ -343,60 +342,59 @@ extern void __get_user_unknown(void);
 
 #define __put_user_check(x,ptr,size)					\
 ({									\
+	__typeof__(*(ptr)) __pu_val = (x);				\
+	long __pu_addr = (long) (ptr);					\
 	long __pu_err;							\
-	__typeof__(*(ptr)) __pu_val;					\
-	long __pu_addr;							\
+									\
 	might_sleep();							\
-	__pu_val = (x);							\
-	__pu_addr = (long) (ptr);					\
-	__asm__("":"=r" (__pu_err));					\
-	if (access_ok(VERIFY_WRITE, __pu_addr, size)) {			\
+	__pu_err = verify_area(VERIFY_WRITE, (void *) __pu_addr, size);	\
+									\
+	if (likely(!__pu_err)) {					\
 		switch (size) {						\
-		case 1: __put_user_asm("sb"); break;			\
-		case 2: __put_user_asm("sh"); break;			\
-		case 4: __put_user_asm("sw"); break;			\
-		case 8: __PUT_USER_DW; break;				\
+		case 1: __put_user_asm("sb", __pu_val); break;		\
+		case 2: __put_user_asm("sh", __pu_val); break;		\
+		case 4: __put_user_asm("sw", __pu_val); break;		\
+		case 8: __PUT_USER_DW(__pu_val); break;			\
 		default: __put_user_unknown(); break;			\
 		}							\
 	}								\
 	__pu_err;							\
 })
 
-#define __put_user_asm(insn)						\
+#define __put_user_asm(insn, __pu_val)					\
 ({									\
 	__asm__ __volatile__(						\
-	"1:\t" insn "\t%z1, %2\t\t\t# __put_user_asm\n\t"		\
-	"move\t%0, $0\n"						\
-	"2:\n\t"							\
-	".section\t.fixup,\"ax\"\n"					\
-	"3:\tli\t%0,%3\n\t"						\
-	"j\t2b\n\t"							\
-	".previous\n\t"							\
-	".section\t__ex_table,\"a\"\n\t"				\
-	__UA_ADDR "\t1b,3b\n\t"						\
-	".previous"							\
-	:"=r" (__pu_err)						\
-	:"Jr" (__pu_val), "o" (__m(__pu_addr)), "i" (-EFAULT));		\
+	"1:	" insn "	%z2, %3		# __put_user_asm\n"	\
+	"2:							\n"	\
+	"	.section	.fixup,\"ax\"			\n"	\
+	"3:	li	%0, %4					\n"	\
+	"	j	2b					\n"	\
+	"	.previous					\n"	\
+	"	.section	__ex_table,\"a\"		\n"	\
+	"	" __UA_ADDR "	1b, 3b				\n"	\
+	"	.previous					\n"	\
+	: "=r" (__pu_err)						\
+	: "0" (__pu_err), "Jr" (__pu_val), "o" (__m(__pu_addr)),	\
+	  "i" (-EFAULT));						\
 })
 
-#define __put_user_asm_ll32						\
+#define __put_user_asm_ll32(__pu_val)					\
 ({									\
 	__asm__ __volatile__(						\
-	"1:\tsw\t%1, %2\t\t\t# __put_user_asm_ll32\n\t"			\
-	"2:\tsw\t%D1, %3\n"						\
-	"move\t%0, $0\n"						\
-	"3:\n\t"							\
-	".section\t.fixup,\"ax\"\n"					\
-	"4:\tli\t%0,%4\n\t"						\
-	"j\t3b\n\t"							\
-	".previous\n\t"							\
-	".section\t__ex_table,\"a\"\n\t"				\
-	__UA_ADDR "\t1b,4b\n\t"						\
-	__UA_ADDR "\t2b,4b\n\t"						\
-	".previous"							\
-	:"=r" (__pu_err)						\
-	:"r" (__pu_val), "o" (__m(__pu_addr)),				\
-	 "o" (__m(__pu_addr + 4)), "i" (-EFAULT));			\
+	"1:	sw	%2, %3		# __put_user_asm_ll32	\n"	\
+	"2:	sw	%D2, %4					\n"	\
+	"3:							\n"	\
+	"	.section	.fixup,\"ax\"			\n"	\
+	"4:	li	%0, %5					\n"	\
+	"	j	3b					\n"	\
+	"	.previous					\n"	\
+	"	.section	__ex_table,\"a\"		\n"	\
+	"	" __UA_ADDR "	1b, 4b				\n"	\
+	"	" __UA_ADDR "	2b, 4b				\n"	\
+	"	.previous"						\
+	: "=r" (__pu_err)						\
+	: "0" (__pu_err), "r" (__pu_val), "o" (__m(__pu_addr)),		\
+	  "o" (__m(__pu_addr + 4)), "i" (-EFAULT));			\
 })
 
 extern void __put_user_unknown(void);
@@ -511,8 +509,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 	".set\tnoat\n\t"						\
 	__UA_ADDU "\t$1, %1, %2\n\t"					\
 	".set\tat\n\t"							\
-	".set\treorder\n\t"						\
-	"move\t%0, $6"		/* XXX */				\
+	".set\treorder"							\
 	: "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)	\
 	:								\
 	: "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",		\
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index 7c5a30028776..4b0c21047839 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -298,16 +298,21 @@
 #define __NR_mq_notify			(__NR_Linux + 275)
 #define __NR_mq_getsetattr		(__NR_Linux + 276)
 #define __NR_vserver			(__NR_Linux + 277)
+#define __NR_waitid			(__NR_Linux + 278)
+/* #define __NR_sys_setaltroot		(__NR_Linux + 279) */
+#define __NR_add_key			(__NR_Linux + 280)
+#define __NR_request_key		(__NR_Linux + 281)
+#define __NR_keyctl			(__NR_Linux + 282)
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls		277
+#define __NR_Linux_syscalls		282
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux			4000
-#define __NR_O32_Linux_syscalls		277
+#define __NR_O32_Linux_syscalls		282
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -552,16 +557,21 @@
 #define __NR_mq_notify			(__NR_Linux + 234)
 #define __NR_mq_getsetattr		(__NR_Linux + 235)
 #define __NR_vserver			(__NR_Linux + 236)
+#define __NR_waitid			(__NR_Linux + 237)
+/* #define __NR_sys_setaltroot		(__NR_Linux + 238) */
+#define __NR_add_key			(__NR_Linux + 239)
+#define __NR_request_key		(__NR_Linux + 240)
+#define __NR_keyctl			(__NR_Linux + 241)
 
 /*
- * Offset of the last Linux flavoured syscall
+ * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls		236
+#define __NR_Linux_syscalls		241
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux			5000
-#define __NR_64_Linux_syscalls		236
+#define __NR_64_Linux_syscalls		241
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -810,16 +820,21 @@
 #define __NR_mq_notify			(__NR_Linux + 238)
 #define __NR_mq_getsetattr		(__NR_Linux + 239)
 #define __NR_vserver			(__NR_Linux + 240)
+#define __NR_waitid			(__NR_Linux + 241)
+/* #define __NR_sys_setaltroot		(__NR_Linux + 242) */
+#define __NR_add_key			(__NR_Linux + 243)
+#define __NR_request_key		(__NR_Linux + 244)
+#define __NR_keyctl			(__NR_Linux + 245)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls		240
+#define __NR_Linux_syscalls		245
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux			6000
-#define __NR_N32_Linux_syscalls		240
+#define __NR_N32_Linux_syscalls		245
 
 #ifndef __ASSEMBLY__
 
@@ -838,12 +853,13 @@ type name(void) \
 	".set\treorder" \
 	: "=&r" (__v0), "=r" (__a3) \
 	: "i" (__NR_##name) \
-	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
+	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+	  "memory"); \
 	\
 	if (__a3 == 0) \
 		return (type) __v0; \
 	errno = __v0; \
-	return -1; \
+	return (type) -1; \
 }
 
 /*
@@ -865,12 +881,13 @@ type name(atype a) \
 	".set\treorder" \
 	: "=&r" (__v0), "=r" (__a3) \
 	: "r" (__a0), "i" (__NR_##name) \
-	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
+	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+	  "memory"); \
 	\
 	if (__a3 == 0) \
 		return (type) __v0; \
 	errno = __v0; \
-	return -1; \
+	return (type) -1; \
 }
 
 #define _syscall2(type,name,atype,a,btype,b) \
@@ -889,12 +906,13 @@ type name(atype a, btype b) \
 	".set\treorder" \
 	: "=&r" (__v0), "=r" (__a3) \
 	: "r" (__a0), "r" (__a1), "i" (__NR_##name) \
-	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
+	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+	  "memory"); \
 	\
 	if (__a3 == 0) \
 		return (type) __v0; \
 	errno = __v0; \
-	return -1; \
+	return (type) -1; \
 }
 
 #define _syscall3(type,name,atype,a,btype,b,ctype,c) \
@@ -914,12 +932,13 @@ type name(atype a, btype b, ctype c) \
 	".set\treorder" \
 	: "=&r" (__v0), "=r" (__a3) \
 	: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
-	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
+	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+	  "memory"); \
 	\
 	if (__a3 == 0) \
 		return (type) __v0; \
 	errno = __v0; \
-	return -1; \
+	return (type) -1; \
 }
 
 #define _syscall4(type,name,atype,a,btype,b,ctype,c,dtype,d) \
@@ -939,12 +958,13 @@ type name(atype a, btype b, ctype c, dtype d) \
 	".set\treorder" \
 	: "=&r" (__v0), "+r" (__a3) \
 	: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
-	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
+	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+	  "memory"); \
 	\
 	if (__a3 == 0) \
 		return (type) __v0; \
 	errno = __v0; \
-	return -1; \
+	return (type) -1; \
 }
 
 #if (_MIPS_SIM == _MIPS_SIM_ABI32)
@@ -975,12 +995,13 @@ type name(atype a, btype b, ctype c, dtype d, etype e) \
 	: "=&r" (__v0), "+r" (__a3) \
 	: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name), \
 	  "m" ((unsigned long)e) \
-	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
+	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+	  "memory"); \
 	\
 	if (__a3 == 0) \
 		return (type) __v0; \
 	errno = __v0; \
-	return -1; \
+	return (type) -1; \
 }
 
 #define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \
@@ -1007,12 +1028,13 @@ type name(atype a, btype b, ctype c, dtype d, etype e, ftype f) \
 	: "=&r" (__v0), "+r" (__a3) \
 	: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name), \
 	  "m" ((unsigned long)e), "m" ((unsigned long)f) \
-	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
+	: "$2", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+	  "memory"); \
 	\
 	if (__a3 == 0) \
 		return (type) __v0; \
 	errno = __v0; \
-	return -1; \
+	return (type) -1; \
 }
 
 #endif /* (_MIPS_SIM == _MIPS_SIM_ABI32) */
@@ -1035,14 +1057,15 @@ type name (atype a,btype b,ctype c,dtype d,etype e) \
 	"syscall\n\t" \
 	"move\t%0, $2\n\t" \
 	".set\treorder" \
-	: "=&r" (__v0), "+r" (__a3), "+r" (__a4) \
-	: "r" (__a0), "r" (__a1), "r" (__a2), "i" (__NR_##name) \
-	: "$2","$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
+	: "=&r" (__v0), "+r" (__a3) \
+	: "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), "i" (__NR_##name) \
+	: "$2", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+	  "memory"); \
 	\
 	if (__a3 == 0) \
 		return (type) __v0; \
 	errno = __v0; \
-	return -1; \
+	return (type) -1; \
 }
 
 #define _syscall6(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e,ftype,f) \
@@ -1065,12 +1088,13 @@ type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \
 	: "=&r" (__v0), "+r" (__a3) \
 	: "r" (__a0), "r" (__a1), "r" (__a2), "r" (__a4), "r" (__a5), \
 	  "i" (__NR_##name) \
-	: "$2","$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24"); \
+	: "$2", "$9", "$10", "$11", "$12", "$13", "$14", "$15", "$24", \
+	  "memory"); \
 	\
 	if (__a3 == 0) \
 		return (type) __v0; \
 	errno = __v0; \
-	return -1; \
+	return (type) -1; \
 }
 
 #endif /* (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */
@@ -1120,21 +1144,7 @@ type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \
  * won't be any messing with the stack from main(), but we define
  * some others too.
  */
-static inline _syscall0(pid_t,setsid)
-static inline _syscall3(int,write,int,fd,const char *,buf,off_t,count)
-static inline _syscall3(int,read,int,fd,char *,buf,off_t,count)
-static inline _syscall3(off_t,lseek,int,fd,off_t,offset,int,count)
-static inline _syscall1(int,dup,int,fd)
 static inline _syscall3(int,execve,const char *,file,char **,argv,char **,envp)
-static inline _syscall3(int,open,const char *,file,int,flag,int,mode)
-static inline _syscall1(int,close,int,fd)
-struct rusage;
-static inline _syscall4(pid_t,wait4,pid_t,pid,int *,stat_addr,int,options,struct rusage *,ru)
-
-static inline pid_t waitpid(int pid, int * wait_stat, int flags)
-{
-	return wait4(pid, wait_stat, flags, NULL);
-}
 
 asmlinkage unsigned long sys_mmap(
 				unsigned long addr, size_t len,
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index a6f5c06c70e3..c4a704121343 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -177,6 +177,14 @@
 #endif
 
 /*
+ * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
+ * may cause ll / sc and lld / scd sequences to execute non-atomically.
+ */
+#ifdef CONFIG_SGI_IP27
+#define R10000_LLSC_WAR 1
+#endif
+
+/*
  * Workarounds default to off
  */
 #ifndef R4600_V1_INDEX_ICACHEOP_WAR
@@ -209,5 +217,8 @@
 #ifndef RM9000_CDEX_SMP_WAR
 #define RM9000_CDEX_SMP_WAR		0
 #endif
+#ifndef R10000_LLSC_WAR
+#define R10000_LLSC_WAR			0
+#endif
 
 #endif /* _ASM_WAR_H */
diff --git a/include/asm-s390/extmem.h b/include/asm-s390/extmem.h
index 8cecfb9a53a2..c8802c934b74 100644
--- a/include/asm-s390/extmem.h
+++ b/include/asm-s390/extmem.h
@@ -17,6 +17,7 @@
 #define SEG_TYPE_SN 4
 #define SEG_TYPE_EN 5
 #define SEG_TYPE_SC 6
+#define SEG_TYPE_EWEN 7
 
 #define SEGMENT_SHARED 0
 #define SEGMENT_EXCLUSIVE 1
@@ -24,7 +25,8 @@
 extern int segment_load (char *name,int segtype,unsigned long *addr,unsigned long *length);
 extern void segment_unload(char *name);
 extern void segment_save(char *name);
-extern int segment_info (char* name);
+extern int segment_type (char* name);
+extern int segment_modify_shared (char *name, int do_nonshared);
 
 #endif
 #endif
diff --git a/include/asm-s390/siginfo.h b/include/asm-s390/siginfo.h
index 446fa8cf2a00..72303537b732 100644
--- a/include/asm-s390/siginfo.h
+++ b/include/asm-s390/siginfo.h
@@ -9,7 +9,6 @@
 #ifndef _S390_SIGINFO_H
 #define _S390_SIGINFO_H
 
-#define HAVE_ARCH_SI_CODES
 #ifdef __s390x__
 #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
 #endif
@@ -22,74 +21,4 @@
 
 #include <asm-generic/siginfo.h>
 
-/*
- * SIGILL si_codes
- */
-#define ILL_ILLOPC	(__SI_FAULT|1)	/* illegal opcode */
-#define ILL_ILLOPN	(__SI_FAULT|2)	/* illegal operand */
-#define ILL_ILLADR	(__SI_FAULT|3)	/* illegal addressing mode */
-#define ILL_ILLTRP	(__SI_FAULT|4)	/* illegal trap */
-#define ILL_PRVOPC	(__SI_FAULT|5)	/* privileged opcode */
-#define ILL_PRVREG	(__SI_FAULT|6)	/* privileged register */
-#define ILL_COPROC	(__SI_FAULT|7)	/* coprocessor error */
-#define ILL_BADSTK	(__SI_FAULT|8)	/* internal stack error */
-#define NSIGILL		8
-
-/*
- * SIGFPE si_codes
- */
-#define FPE_INTDIV	(__SI_FAULT|1)	/* integer divide by zero */
-#define FPE_INTOVF	(__SI_FAULT|2)	/* integer overflow */
-#define FPE_FLTDIV	(__SI_FAULT|3)	/* floating point divide by zero */
-#define FPE_FLTOVF	(__SI_FAULT|4)	/* floating point overflow */
-#define FPE_FLTUND	(__SI_FAULT|5)	/* floating point underflow */
-#define FPE_FLTRES	(__SI_FAULT|6)	/* floating point inexact result */
-#define FPE_FLTINV	(__SI_FAULT|7)	/* floating point invalid operation */
-#define FPE_FLTSUB	(__SI_FAULT|8)	/* subscript out of range */
-#define NSIGFPE		8
-
-/*
- * SIGSEGV si_codes
- */
-#define SEGV_MAPERR	(__SI_FAULT|1)	/* address not mapped to object */
-#define SEGV_ACCERR	(__SI_FAULT|2)	/* invalid permissions for mapped object */
-#define NSIGSEGV	2
-
-/*
- * SIGBUS si_codes
- */
-#define BUS_ADRALN	(__SI_FAULT|1)	/* invalid address alignment */
-#define BUS_ADRERR	(__SI_FAULT|2)	/* non-existant physical address */
-#define BUS_OBJERR	(__SI_FAULT|3)	/* object specific hardware error */
-#define NSIGBUS		3
-
-/*
- * SIGTRAP si_codes
- */
-#define TRAP_BRKPT	(__SI_FAULT|1)	/* process breakpoint */
-#define TRAP_TRACE	(__SI_FAULT|2)	/* process trace trap */
-#define NSIGTRAP	2
-
-/*
- * SIGCHLD si_codes
- */
-#define CLD_EXITED	(__SI_CHLD|1)	/* child has exited */
-#define CLD_KILLED	(__SI_CHLD|2)	/* child was killed */
-#define CLD_DUMPED	(__SI_CHLD|3)	/* child terminated abnormally */
-#define CLD_TRAPPED	(__SI_CHLD|4)	/* traced child has trapped */
-#define CLD_STOPPED	(__SI_CHLD|5)	/* child has stopped */
-#define CLD_CONTINUED	(__SI_CHLD|6)	/* stopped child has continued */
-#define NSIGCHLD	6
-
-/*
- * SIGPOLL si_codes
- */
-#define POLL_IN		(__SI_POLL|1)	/* data input available */
-#define POLL_OUT	(__SI_POLL|2)	/* output buffers available */
-#define POLL_MSG	(__SI_POLL|3)	/* input message available */
-#define POLL_ERR	(__SI_POLL|4)	/* i/o error */
-#define POLL_PRI	(__SI_POLL|5)	/* high priority input available */
-#define POLL_HUP	(__SI_POLL|6)	/* device disconnected */
-#define NSIGPOLL	6
-
 #endif
diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h
index 4d46012fe6a3..78a2b979469a 100644
--- a/include/asm-s390/unistd.h
+++ b/include/asm-s390/unistd.h
@@ -269,8 +269,9 @@
 #define __NR_mq_timedreceive	274
 #define __NR_mq_notify		275
 #define __NR_mq_getsetattr	276
+/* Number 277 is reserved for new sys_kexec_load */
 
-#define NR_syscalls 277
+#define NR_syscalls 278
 
 /* 
  * There are some system calls that are not present on 64 bit, some
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 97ff28cd67e8..0bd6704baa60 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -489,15 +489,15 @@ static inline int acpi_blacklisted(void)
  * 2: C2 okay, but not C3 etc.
  */
 
-extern unsigned int acpi_cstate_limit;
+extern unsigned int max_cstate;
 
 static inline unsigned int acpi_get_cstate_limit(void)
 {
-	return acpi_cstate_limit;
+	return max_cstate;
 }
 static inline void acpi_set_cstate_limit(unsigned int new_limit)
 {
-	acpi_cstate_limit = new_limit;
+	max_cstate = new_limit;
 	return;
 }
 #else
diff --git a/include/linux/gen_stats.h b/include/linux/gen_stats.h
index ab631c3571ce..13f4e74609ac 100644
--- a/include/linux/gen_stats.h
+++ b/include/linux/gen_stats.h
@@ -14,6 +14,7 @@ enum {
 #define TCA_STATS_MAX (__TCA_STATS_MAX - 1)
 
 /**
+ * struct gnet_stats_basic - byte/packet throughput statistics
  * @bytes: number of seen bytes
  * @packets: number of seen packets
  */
@@ -24,6 +25,7 @@ struct gnet_stats_basic
 };
 
 /**
+ * struct gnet_stats_rate_est - rate estimator
  * @bps: current byte rate
  * @pps: current packet rate
  */
@@ -34,10 +36,12 @@ struct gnet_stats_rate_est
 };
 
 /**
+ * struct gnet_stats_queue - queuing statistics
  * @qlen: queue length
  * @backlog: backlog size of queue
  * @drops: number of dropped packets
  * @requeues: number of requeues
+ * @overlimits: number of enqueues over the limit
  */
 struct gnet_stats_queue
 {
@@ -49,6 +53,7 @@ struct gnet_stats_queue
 };
 
 /**
+ * struct gnet_estimator - rate estimator configuration
  * @interval: sampling period
  * @ewma_log: the log of measurement window weight
  */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 5cfcf8941445..f1946ad646e4 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1087,6 +1087,7 @@
 #define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE	0x0065
 #define PCI_DEVICE_ID_NVIDIA_NVENET_2		0x0066
 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO		0x006a
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS	0x0084
 #define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE	0x0085
 #define PCI_DEVICE_ID_NVIDIA_NVENET_4		0x0086
 #define PCI_DEVICE_ID_NVIDIA_NVENET_5		0x008c
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 0c8262c6d6b8..440393fcd5c7 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -671,6 +671,19 @@ static inline pid_t process_group(struct task_struct *tsk)
 	return tsk->signal->pgrp;
 }
 
+/**
+ * pid_alive - check that a task structure is not stale
+ * @p: Task structure to be checked.
+ *
+ * Test if a process is not yet dead (at most zombie state)
+ * If pid_alive fails, then pointers within the task structure
+ * can be stale and must not be dereferenced.
+ */
+static inline int pid_alive(struct task_struct *p)
+{
+	return p->pids[PIDTYPE_PID].nr != 0;
+}
+
 extern void free_task(struct task_struct *tsk);
 extern void __put_task_struct(struct task_struct *tsk);
 #define get_task_struct(tsk) do { atomic_inc(&(tsk)->usage); } while(0)
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 3fad76b0873c..9666c572f65b 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -91,12 +91,15 @@
 /* MPC52xx type numbers */
 #define PORT_MPC52xx	59
 
-/*IBM icom*/
-#define PORT_ICOM      60
+/* IBM icom */
+#define PORT_ICOM	60
 
 /* Samsung S3C2440 SoC */
 #define PORT_S3C2440	61
 
+/* Motorola i.MX SoC */
+#define PORT_IMX	62
+
 #ifdef __KERNEL__
 
 #include <linux/config.h>
@@ -241,11 +244,11 @@ struct uart_port {
  * within.
  */
 struct uart_state {
-	unsigned int		close_delay;
-	unsigned int		closing_wait;
+	unsigned int		close_delay;		/* msec */
+	unsigned int		closing_wait;		/* msec */
 
 #define USF_CLOSING_WAIT_INF	(0)
-#define USF_CLOSING_WAIT_NONE	(65535)
+#define USF_CLOSING_WAIT_NONE	(~0U)
 
 	int			count;
 	int			pm_state;
diff --git a/include/linux/usbdevice_fs.h b/include/linux/usbdevice_fs.h
index af49afaf7bb4..aed8193eb420 100644
--- a/include/linux/usbdevice_fs.h
+++ b/include/linux/usbdevice_fs.h
@@ -144,29 +144,4 @@ struct usbdevfs_hub_portinfo {
 #define USBDEVFS_DISCONNECT        _IO('U', 22)
 #define USBDEVFS_CONNECT           _IO('U', 23)
 
-/* --------------------------------------------------------------------- */
-
-#ifdef __KERNEL__
-
-#include <linux/list.h>
-#include <asm/semaphore.h>
-
-
-struct dev_state {
-	struct list_head list;      /* state list */
-	struct usb_device *dev;
-	struct file *file;
-	spinlock_t lock;            /* protects the async urb lists */
-	struct list_head async_pending;
-	struct list_head async_completed;
-	wait_queue_head_t wait;     /* wake up if a request completed */
-	unsigned int discsignr;
-	struct task_struct *disctask;
-	void __user *disccontext;
-	unsigned long ifclaimed;
-};
-
-#endif /* __KERNEL__ */
-
-/* --------------------------------------------------------------------- */
 #endif /* _LINUX_USBDEVICE_FS_H */
diff --git a/include/net/udp.h b/include/net/udp.h
index 2ef99a71bc30..c496d10101db 100644
--- a/include/net/udp.h
+++ b/include/net/udp.h
@@ -71,6 +71,8 @@ extern int	udp_sendmsg(struct kiocb *iocb, struct sock *sk,
 extern int	udp_rcv(struct sk_buff *skb);
 extern int	udp_ioctl(struct sock *sk, int cmd, unsigned long arg);
 extern int	udp_disconnect(struct sock *sk, int flags);
+extern unsigned int udp_poll(struct file *file, struct socket *sock,
+			     poll_table *wait);
 
 DECLARE_SNMP_STAT(struct udp_mib, udp_statistics);
 #define UDP_INC_STATS(field)		SNMP_INC_STATS(udp_statistics, field)