[PATCH] Altix update: various, mainly cleanups

From: Pat Gefre <pfg@sgi.com>

arch/ia64/sn/io/machvec/pci_bus_cvlink.c
    Changes for new pcireg_ interfaces
    pcibr reorg
    Some code cleanup/reorg

arch/ia64/sn/io/machvec/pci_dma.c
    IS_PCIA64() not needed

arch/ia64/sn/io/sn2/ml_iograph.c
    new pcireg_ interface

arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c
    code reorg/clean up

arch/ia64/sn/io/sn2/pcibr/pcibr_config.c
    code reorg/cleanup

arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c
    reorg/cleanup

arch/ia64/sn/io/sn2/pcibr/pcibr_error.c
    reorg/cleanup

arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c
    reorg/cleanup

arch/ia64/sn/io/sn2/pcibr/pcibr_reg.c
    Fixed the interface to these functions - one call/data type

arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c
    reorg/cleanup

arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c
    reorg/cleanup

arch/ia64/sn/io/sn2/pciio.c
    removed unused functions

arch/ia64/sn/io/sn2/pic.c
    reorg/cleanup

arch/ia64/sn/kernel/irq.c
    IS_PIC_SOFT not needed
    mod for new pcireg_ interfaces

include/asm-ia64/sn/module.h
    nodes/geoid[] -> MAX_SLABS

include/asm-ia64/sn/pci/bridge.h
    IS_[X]BRIDGE not needed

include/asm-ia64/sn/pci/pci_bus_cvlink.h
    SET_PCIA64 and IS_PCIA64 not needed
    isa64, dma_buf_sync, xbow_buf_sync gone

include/asm-ia64/sn/pci/pcibr.h
    mostly cleanup
    some reorg mods

include/asm-ia64/sn/pci/pcibr_private.h
    some reorg code
    protos for new pcireg_ interfaces

include/asm-ia64/sn/pci/pciio.h
    cleanup

include/asm-ia64/sn/pci/pic.h
    cleanup

include/asm-ia64/sn/sn2/intr.h
    changed IA64_SN2_FIRST_DEVICE_VECTOR and IA64_SN2_LAST_DEVICE_VECTOR

8 files changed, 289 insertions, 769 deletions

diff --git a/include/asm-ia64/sn/module.h b/include/asm-ia64/sn/module.h
index c4aff28d91b3..0b38f156260c 100644
--- a/include/asm-ia64/sn/module.h
+++ b/include/asm-ia64/sn/module.h
@@ -158,12 +158,9 @@ struct module_s {
     spinlock_t		lock;		/* Lock for this structure	   */
 
     /* List of nodes in this module */
-    cnodeid_t		nodes[MODULE_MAX_NODES];
-    geoid_t		geoid[MODULE_MAX_NODES];
-    struct {
-		char	moduleid[8];
-    } io[MODULE_MAX_NODES];
-    int			nodecnt;	/* Number of nodes in array        */
+    cnodeid_t		nodes[MAX_SLABS + 1];
+    geoid_t		geoid[MAX_SLABS + 1];
+
     /* Fields for Module System Controller */
     int			mesgpend;	/* Message pending                 */
     int			shutdown;	/* Shutdown in progress            */
diff --git a/include/asm-ia64/sn/pci/bridge.h b/include/asm-ia64/sn/pci/bridge.h
index fbb6e57b6170..d98f425eb682 100644
--- a/include/asm-ia64/sn/pci/bridge.h
+++ b/include/asm-ia64/sn/pci/bridge.h
@@ -918,6 +918,10 @@ typedef volatile struct bridge_s {
 #define PCIBR_TYPE0_CFG_DEV(ps, s) PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1)
 #define PCIBR_BUS_TYPE0_CFG_DEVF(ps,s,f) PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,(s+1),f)
 
+/* NOTE: 's' is the internal device number, not the external slot number */
+#define PCIBR_BUS_TYPE0_CFG_DEV(ps, s) \
+		PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1)
+
 #endif				/* LANGUAGE_C */
 
 #define BRIDGE_EXTERNAL_FLASH	0x00C00000	/* External Flash PROMS */
@@ -943,10 +947,6 @@ typedef volatile struct bridge_s {
 #define XBRIDGE_REV_B			0x2
 
 /* macros to determine bridge type. 'wid' == widget identification */
-#define IS_BRIDGE(wid) (XWIDGET_PART_NUM(wid) == BRIDGE_WIDGET_PART_NUM && \
-			XWIDGET_MFG_NUM(wid) == BRIDGE_WIDGET_MFGR_NUM)
-#define IS_XBRIDGE(wid) (XWIDGET_PART_NUM(wid) == XBRIDGE_WIDGET_PART_NUM && \
-			XWIDGET_MFG_NUM(wid) == XBRIDGE_WIDGET_MFGR_NUM)
 #define IS_PIC_BUS0(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS0 && \
 			XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM)
 #define IS_PIC_BUS1(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS1 && \
diff --git a/include/asm-ia64/sn/pci/pci_bus_cvlink.h b/include/asm-ia64/sn/pci/pci_bus_cvlink.h
index d1c30ab50df1..c5c04358e8d8 100644
--- a/include/asm-ia64/sn/pci/pci_bus_cvlink.h
+++ b/include/asm-ia64/sn/pci/pci_bus_cvlink.h
@@ -31,10 +31,6 @@
 #define MAX_PCI_XWIDGET 256
 #define MAX_ATE_MAPS 1024
 
-#define SET_PCIA64(dev) \
-	(((struct sn_device_sysdata *)((dev)->sysdata))->isa64) = 1
-#define IS_PCIA64(dev)	(((dev)->dma_mask == 0xffffffffffffffffUL) || \
-		(((struct sn_device_sysdata *)((dev)->sysdata))->isa64))
 #define IS_PCI32G(dev)	((dev)->dma_mask >= 0xffffffff)
 #define IS_PCI32L(dev)	((dev)->dma_mask < 0xffffffff)
 
@@ -50,9 +46,6 @@ struct sn_widget_sysdata {
 
 struct sn_device_sysdata {
         vertex_hdl_t  vhdl;
-	int		isa64;
-	volatile unsigned int *dma_buf_sync;
-	volatile unsigned int *xbow_buf_sync;
 	pciio_provider_t	*pci_provider;
 };
 
diff --git a/include/asm-ia64/sn/pci/pcibr.h b/include/asm-ia64/sn/pci/pcibr.h
index 5ae5814a3e2e..70910c97d880 100644
--- a/include/asm-ia64/sn/pci/pcibr.h
+++ b/include/asm-ia64/sn/pci/pcibr.h
@@ -41,26 +41,6 @@ typedef struct pcibr_dmamap_s *pcibr_dmamap_t;
 typedef struct pcibr_intr_s *pcibr_intr_t;
 
 /* =====================================================================
- *    primary entry points: Bridge (pcibr) device driver
- *
- *	These functions are normal device driver entry points
- *	and are called along with the similar entry points from
- *	other device drivers. They are included here as documentation
- *	of their existence and purpose.
- *
- *	pcibr_init() is called to inform us that there is a pcibr driver
- *	configured into the kernel; it is responsible for registering
- *	as a crosstalk widget and providing a routine to be called
- *	when a widget with the proper part number is observed.
- *
- *	pcibr_attach() is called for each vertex in the hardware graph
- *	corresponding to a crosstalk widget with the manufacturer
- *	code and part number registered by pcibr_init().
- */
-
-extern int		pcibr_attach(vertex_hdl_t);
-
-/* =====================================================================
  *    bus provider function table
  *
  *	Normally, this table is only handed off explicitly
@@ -72,7 +52,6 @@ extern int		pcibr_attach(vertex_hdl_t);
  *	pcibr, we can go directly to this ops table.
  */
 
-extern pciio_provider_t pcibr_provider;
 extern pciio_provider_t pci_pic_provider;
 
 /* =====================================================================
@@ -107,6 +86,11 @@ extern caddr_t		pcibr_piomap_addr(pcibr_piomap_t piomap,
 
 extern void		pcibr_piomap_done(pcibr_piomap_t piomap);
 
+extern int		pcibr_piomap_probe(pcibr_piomap_t piomap,
+					   off_t offset,
+					   int len,
+					   void *valp);
+
 extern caddr_t		pcibr_piotrans_addr(vertex_hdl_t dev,
 					    device_desc_t dev_desc,
 					    pciio_space_t space,
@@ -193,15 +177,10 @@ extern void		pcibr_provider_shutdown(vertex_hdl_t pcibr);
 
 extern int		pcibr_reset(vertex_hdl_t dev);
 
-extern int              pcibr_write_gather_flush(vertex_hdl_t dev);
-
 extern pciio_endian_t	pcibr_endian_set(vertex_hdl_t dev,
 					 pciio_endian_t device_end,
 					 pciio_endian_t desired_end);
 
-extern pciio_priority_t pcibr_priority_set(vertex_hdl_t dev,
-					   pciio_priority_t device_prio);
-
 extern uint64_t		pcibr_config_get(vertex_hdl_t conn,
 					 unsigned reg,
 					 unsigned size);
@@ -211,6 +190,10 @@ extern void		pcibr_config_set(vertex_hdl_t conn,
 					 unsigned size,
 					 uint64_t value);
 
+extern pciio_slot_t	pcibr_error_extract(vertex_hdl_t pcibr_vhdl,
+					    pciio_space_t *spacep,
+					    iopaddr_t *addrp);
+
 extern int		pcibr_wrb_flush(vertex_hdl_t pconn_vhdl);
 extern int		pcibr_rrb_check(vertex_hdl_t pconn_vhdl,
 					int *count_vchan0,
@@ -234,6 +217,12 @@ void			pcibr_set_rrb_callback(vertex_hdl_t xconn_vhdl,
 					       rrb_alloc_funct_f *func);
 
 extern int		pcibr_device_unregister(vertex_hdl_t);
+extern void             pcibr_driver_reg_callback(vertex_hdl_t, int, int, int);
+extern void             pcibr_driver_unreg_callback(vertex_hdl_t,
+                                                    int, int, int);
+
+
+extern void *		pcibr_bridge_ptr_get(vertex_hdl_t, int);
 
 /*
  * Bridge-specific flags that can be set via pcibr_device_flags_set
@@ -324,9 +313,6 @@ extern int		pcibr_rrb_alloc(vertex_hdl_t pconn_vhdl,
  * the allocation time in the current implementation of PCI bridge.
  */
 extern iopaddr_t	pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
-
-extern xwidget_intr_preset_f pcibr_xintr_preset;
-
 extern void		pcibr_hints_fix_rrbs(vertex_hdl_t);
 extern void		pcibr_hints_dualslot(vertex_hdl_t, pciio_slot_t, pciio_slot_t);
 extern void		pcibr_hints_subdevs(vertex_hdl_t, pciio_slot_t, ulong);
@@ -426,7 +412,6 @@ struct pcibr_slot_info_resp_s {
     unsigned                resp_bss_d64_flags;
     iopaddr_t               resp_bss_d32_base;
     unsigned                resp_bss_d32_flags;
-    atomic_t		    resp_bss_ext_ates_active;
     volatile unsigned      *resp_bss_cmd_pointer;
     unsigned                resp_bss_cmd_shadow;
     int                     resp_bs_rrb_valid;
@@ -438,8 +423,6 @@ struct pcibr_slot_info_resp_s {
     uint64_t		    resp_b_int_device;
     uint64_t		    resp_b_int_enable;
     uint64_t		    resp_b_int_host;
-    picreg_t		    resp_p_int_enable;
-    picreg_t		    resp_p_int_host;
     struct pcibr_slot_func_info_resp_s {
         int                     resp_f_status;
         char                    resp_f_slot_name[MAXDEVNAME];
diff --git a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h
index b7b8c123d461..fd67e38b88e7 100644
--- a/include/asm-ia64/sn/pci/pcibr_private.h
+++ b/include/asm-ia64/sn/pci/pcibr_private.h
@@ -39,18 +39,119 @@ typedef volatile bridgereg_t *reg_p;
 /*
  * extern functions
  */
-cfg_p pcibr_slot_config_addr(bridge_t *, pciio_slot_t, int);
-cfg_p pcibr_func_config_addr(bridge_t *, pciio_bus_t bus, pciio_slot_t, pciio_function_t, int);
-unsigned pcibr_slot_config_get(bridge_t *, pciio_slot_t, int);
-unsigned pcibr_func_config_get(bridge_t *, pciio_slot_t, pciio_function_t, int);
-extern void pcireg_intr_enable_bit_clr(void *, uint64_t);
-extern void pcireg_intr_enable_bit_set(void *, uint64_t);
-extern void pcireg_intr_addr_addr_set(void *, int, uint64_t);
-extern void pcireg_force_intr_set(void *, int);
+cfg_p pcibr_slot_config_addr(pcibr_soft_t, pciio_slot_t, int);
+cfg_p pcibr_func_config_addr(pcibr_soft_t, pciio_bus_t bus, pciio_slot_t, pciio_function_t, int);
 void pcibr_debug(uint32_t, vertex_hdl_t, char *, ...);
-void pcibr_slot_config_set(bridge_t *, pciio_slot_t, int, unsigned);
-void pcibr_func_config_set(bridge_t *, pciio_slot_t, pciio_function_t, int, 
-								unsigned);
+void pcibr_func_config_set(pcibr_soft_t, pciio_slot_t, pciio_function_t, int, unsigned);
+/*
+ * pcireg_ externs
+ */
+
+extern uint64_t		pcireg_id_get(pcibr_soft_t);
+extern uint64_t		pcireg_bridge_id_get(void *);
+extern uint64_t		pcireg_bus_err_get(pcibr_soft_t);
+extern uint64_t		pcireg_control_get(pcibr_soft_t);
+extern uint64_t		pcireg_bridge_control_get(void *);
+extern void		pcireg_control_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_control_bit_clr(pcibr_soft_t, uint64_t);
+extern void		pcireg_control_bit_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_req_timeout_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_intr_dst_set(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_intr_dst_target_id_get(pcibr_soft_t);
+extern void		pcireg_intr_dst_target_id_set(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_intr_dst_addr_get(pcibr_soft_t);
+extern void		pcireg_intr_dst_addr_set(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_cmdword_err_get(pcibr_soft_t);
+extern uint64_t		pcireg_llp_cfg_get(pcibr_soft_t);
+extern void		pcireg_llp_cfg_set(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_tflush_get(pcibr_soft_t);
+extern uint64_t		pcireg_linkside_err_get(pcibr_soft_t);
+extern uint64_t		pcireg_resp_err_get(pcibr_soft_t);
+extern uint64_t		pcireg_resp_err_addr_get(pcibr_soft_t);
+extern uint64_t		pcireg_resp_err_buf_get(pcibr_soft_t);
+extern uint64_t		pcireg_resp_err_dev_get(pcibr_soft_t);
+extern uint64_t		pcireg_linkside_err_addr_get(pcibr_soft_t);
+extern uint64_t		pcireg_dirmap_get(pcibr_soft_t);
+extern void		pcireg_dirmap_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_dirmap_wid_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_dirmap_diroff_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_dirmap_add512_set(pcibr_soft_t);
+extern void		pcireg_dirmap_add512_clr(pcibr_soft_t);
+extern uint64_t		pcireg_map_fault_get(pcibr_soft_t);
+extern uint64_t		pcireg_arbitration_get(pcibr_soft_t);
+extern void		pcireg_arbitration_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_arbitration_bit_clr(pcibr_soft_t, uint64_t);
+extern void		pcireg_arbitration_bit_set(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_parity_err_get(pcibr_soft_t);
+extern uint64_t		pcireg_type1_cntr_get(pcibr_soft_t);
+extern void		pcireg_type1_cntr_set(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_timeout_get(pcibr_soft_t);
+extern void		pcireg_timeout_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_timeout_bit_clr(pcibr_soft_t, uint64_t);
+extern void		pcireg_timeout_bit_set(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_pci_bus_addr_get(pcibr_soft_t);
+extern uint64_t		pcireg_pci_bus_addr_addr_get(pcibr_soft_t);
+extern uint64_t		pcireg_intr_status_get(pcibr_soft_t);
+extern uint64_t		pcireg_intr_enable_get(pcibr_soft_t);
+extern void		pcireg_intr_enable_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_intr_enable_bit_clr(pcibr_soft_t, uint64_t);
+extern void		pcireg_intr_enable_bit_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_intr_reset_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_intr_reset_bit_set(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_intr_mode_get(pcibr_soft_t);
+extern void		pcireg_intr_mode_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_intr_mode_bit_clr(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_intr_device_get(pcibr_soft_t);
+extern void		pcireg_intr_device_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_intr_device_bit_set(pcibr_soft_t, uint64_t);
+extern void		pcireg_bridge_intr_device_bit_set(void *, uint64_t);
+extern void		pcireg_intr_device_bit_clr(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_intr_host_err_get(pcibr_soft_t);
+extern void		pcireg_intr_host_err_set(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_intr_addr_get(pcibr_soft_t, int);
+extern void		pcireg_intr_addr_set(pcibr_soft_t, int, uint64_t);
+extern void		pcireg_bridge_intr_addr_set(void *, int, uint64_t);
+extern void *		pcireg_intr_addr_addr(pcibr_soft_t, int);
+extern void		pcireg_intr_addr_vect_set(pcibr_soft_t, int, uint64_t);
+extern void		pcireg_bridge_intr_addr_vect_set(void *, int, uint64_t);
+extern uint64_t		pcireg_intr_addr_addr_get(pcibr_soft_t, int);
+extern void		pcireg_intr_addr_addr_set(pcibr_soft_t, int, uint64_t);
+extern void		pcireg_bridge_intr_addr_addr_set(void *, int, uint64_t);
+extern uint64_t		pcireg_intr_view_get(pcibr_soft_t);
+extern uint64_t		pcireg_intr_multiple_get(pcibr_soft_t);
+extern void		pcireg_force_always_set(pcibr_soft_t, int);
+extern void *		pcireg_bridge_force_always_addr_get(void *, int);
+extern void *		pcireg_force_always_addr_get(pcibr_soft_t, int);
+extern void		pcireg_force_intr_set(pcibr_soft_t, int);
+extern uint64_t		pcireg_device_get(pcibr_soft_t, int);
+extern void		pcireg_device_set(pcibr_soft_t, int, uint64_t);
+extern void		pcireg_device_bit_set(pcibr_soft_t, int, uint64_t);
+extern void		pcireg_device_bit_clr(pcibr_soft_t, int, uint64_t);
+extern uint64_t		pcireg_rrb_get(pcibr_soft_t, int);
+extern void		pcireg_rrb_set(pcibr_soft_t, int, uint64_t);
+extern void		pcireg_rrb_bit_set(pcibr_soft_t, int, uint64_t);
+extern void		pcireg_rrb_bit_clr(pcibr_soft_t, int, uint64_t);
+extern uint64_t		pcireg_rrb_status_get(pcibr_soft_t);
+extern void		pcireg_rrb_clear_set(pcibr_soft_t, uint64_t);
+extern uint64_t		pcireg_wrb_flush_get(pcibr_soft_t, int);
+extern uint64_t		pcireg_pcix_bus_err_addr_get(pcibr_soft_t);
+extern uint64_t		pcireg_pcix_bus_err_attr_get(pcibr_soft_t);
+extern uint64_t		pcireg_pcix_bus_err_data_get(pcibr_soft_t);
+extern uint64_t		pcireg_pcix_req_err_attr_get(pcibr_soft_t);
+extern uint64_t		pcireg_pcix_req_err_addr_get(pcibr_soft_t);
+extern uint64_t		pcireg_pcix_pio_split_addr_get(pcibr_soft_t);
+extern uint64_t		pcireg_pcix_pio_split_attr_get(pcibr_soft_t);
+extern cfg_p		pcireg_type1_cfg_addr(pcibr_soft_t, pciio_function_t,
+					      int);
+extern cfg_p		pcireg_type0_cfg_addr(pcibr_soft_t, pciio_slot_t,
+					      pciio_function_t, int);
+extern bridge_ate_t	pcireg_int_ate_get(pcibr_soft_t, int);
+extern void		pcireg_int_ate_set(pcibr_soft_t, int, bridge_ate_t);
+extern bridge_ate_p	pcireg_int_ate_addr(pcibr_soft_t, int);
+
+extern uint64_t		pcireg_speed_get(pcibr_soft_t);
+extern uint64_t		pcireg_mode_get(pcibr_soft_t);
+
 /*
  * PCIBR_DEBUG() macro and debug bitmask defines
  */
@@ -117,7 +218,7 @@ struct pcibr_piomap_s {
     xtalk_piomap_t          bp_xtalk_pio;	/* corresponding xtalk resource */
     pcibr_piomap_t	    bp_next;	/* Next piomap on the list */
     pcibr_soft_t	    bp_soft;	/* backpointer to bridge soft data */
-    atomic_t		    bp_toc[1];	/* PCI timeout counter */
+    atomic_t		    bp_toc;	/* PCI timeout counter */
 
 };
 
@@ -143,6 +244,7 @@ struct pcibr_dmamap_s {
     bridge_ate_t            bd_ate_proto;	/* prototype ATE (for xioaddr=0) */
     bridge_ate_t            bd_ate_prime;	/* value of 1st ATE written */
     dma_addr_t		    bd_dma_addr;	/* Linux dma handle */
+    struct resource	    resource;
 };
 
 #define	IBUFSIZE	5		/* size of circular buffer (holds 4) */
@@ -245,7 +347,8 @@ struct pcibr_info_s {
 struct pcibr_intr_list_s {
     pcibr_intr_list_t       il_next;
     pcibr_intr_t            il_intr;
-    volatile bridgereg_t   *il_wrbf;	/* ptr to b_wr_req_buf[] */
+    pcibr_soft_t	    il_soft;
+    pciio_slot_t	    il_slot;
 };
 
 /* =====================================================================
@@ -271,7 +374,7 @@ struct pcibr_intr_wrap_s {
  * To reduce the size of the internal resource mapping structures, do
  * not use the entire PCI bus I/O address space
  */ 
-#define PCIBR_BUS_IO_BASE      0x100000
+#define PCIBR_BUS_IO_BASE      0x200000
 #define PCIBR_BUS_IO_MAX       0x0FFFFFFF
 #define PCIBR_BUS_IO_PAGE      0x100000
 
@@ -284,8 +387,6 @@ struct pcibr_intr_wrap_s {
 #define PCIBR_BUS_MEM_PAGE     0x100000
 
 /* defines for pcibr_soft_s->bs_bridge_type */
-#define PCIBR_BRIDGETYPE_BRIDGE		0
-#define PCIBR_BRIDGETYPE_XBRIDGE	1
 #define PCIBR_BRIDGETYPE_PIC		2
 #define IS_PIC_BUSNUM_SOFT(ps, bus)	((ps)->bs_busnum == (bus))
 
@@ -310,10 +411,6 @@ struct pcibr_intr_wrap_s {
 #define PV862253 (1 << 1) /* PIC: don't enable write req RAM parity checking */
 #define PV867308 (3 << 1) /* PIC: make LLP error interrupts FATAL for PIC */
 
-/* Bridgetype macros given a pcibr_soft structure */
-#define IS_PIC_SOFT(ps)     (ps->bs_bridge_type == PCIBR_BRIDGETYPE_PIC)
-
-
 /* defines for pcibr_soft_s->bs_bridge_mode */
 #define PCIBR_BRIDGEMODE_PCI_33		0x0
 #define PCIBR_BRIDGEMODE_PCI_66		0x2
@@ -349,14 +446,16 @@ struct pcibr_soft_s {
     vertex_hdl_t          bs_conn;		/* xtalk connection point */
     vertex_hdl_t          bs_vhdl;		/* vertex owned by pcibr */
     uint64_t                bs_int_enable;	/* Mask of enabled intrs */
-    bridge_t               *bs_base;		/* PIO pointer to Bridge chip */
+    void               *bs_base;		/* PIO pointer to Bridge chip */
     char                   *bs_name;		/* hw graph name */
+    char		    bs_asic_name[16];	/* ASIC name */
     xwidgetnum_t            bs_xid;		/* Bridge's xtalk ID number */
     vertex_hdl_t          bs_master;		/* xtalk master vertex */
     xwidgetnum_t            bs_mxid;		/* master's xtalk ID number */
     pciio_slot_t            bs_first_slot;      /* first existing slot */
     pciio_slot_t            bs_last_slot;       /* last existing slot */
     pciio_slot_t            bs_last_reset;      /* last slot to reset */
+    uint32_t		    bs_unused_slot;	/* unavailable slots bitmask */
     pciio_slot_t	    bs_min_slot;	/* lowest possible slot */
     pciio_slot_t	    bs_max_slot;	/* highest possible slot */
     pcibr_soft_t	    bs_peers_soft;	/* PICs other bus's soft */
@@ -474,14 +573,6 @@ struct pcibr_soft_s {
 	unsigned		bss_d64_flags;
 	iopaddr_t		bss_d32_base;
 	unsigned		bss_d32_flags;
-
-	/* Shadow information used for implementing
-	 * Bridge Hardware WAR #484930
-	 */
-	atomic_t		bss_ext_ates_active;
-        volatile unsigned      *bss_cmd_pointer;
-	unsigned		bss_cmd_shadow;
-
     } bs_slot[8];
 
     pcibr_intr_bits_f	       *bs_intr_bits;
diff --git a/include/asm-ia64/sn/pci/pciio.h b/include/asm-ia64/sn/pci/pciio.h
index 4519a84dda6c..7b6740a6a272 100644
--- a/include/asm-ia64/sn/pci/pciio.h
+++ b/include/asm-ia64/sn/pci/pciio.h
@@ -433,18 +433,11 @@ pciio_provider_shutdown_f (vertex_hdl_t pciio_provider);
 typedef int	
 pciio_reset_f		(vertex_hdl_t conn);	/* pci connection point */
 
-typedef int
-pciio_write_gather_flush_f (vertex_hdl_t dev);    /* Device flushing buffers */
-
 typedef pciio_endian_t			/* actual endianness */
 pciio_endian_set_f      (vertex_hdl_t dev,	/* specify endianness for this device */
 			 pciio_endian_t device_end,	/* endianness of device */
 			 pciio_endian_t desired_end);	/* desired endianness */
 
-typedef pciio_priority_t
-pciio_priority_set_f    (vertex_hdl_t pcicard,
-			 pciio_priority_t device_prio);
-
 typedef uint64_t
 pciio_config_get_f	(vertex_hdl_t conn,	/* pci connection point */
 			 unsigned reg,		/* register byte offset */
@@ -476,13 +469,14 @@ pciio_driver_unreg_callback_f	(vertex_hdl_t conn, /* pci connection point */
 typedef int
 pciio_device_unregister_f	(vertex_hdl_t conn);
 
-typedef pciio_businfo_t
-pciio_businfo_get_f		(vertex_hdl_t conn);
 
 /*
  * Adapters that provide a PCI interface adhere to this software interface.
  */
 typedef struct pciio_provider_s {
+    /* ASIC PROVIDER ID */
+    pciio_asic_type_t	   provider_asic;
+
     /* PIO MANAGEMENT */
     pciio_piomap_alloc_f   *piomap_alloc;
     pciio_piomap_free_f    *piomap_free;
@@ -513,9 +507,7 @@ typedef struct pciio_provider_s {
     pciio_provider_startup_f *provider_startup;
     pciio_provider_shutdown_f *provider_shutdown;
     pciio_reset_f	   *reset;
-    pciio_write_gather_flush_f *write_gather_flush;
     pciio_endian_set_f     *endian_set;
-    pciio_priority_set_f   *priority_set;
     pciio_config_get_f	   *config_get;
     pciio_config_set_f	   *config_set;
 
@@ -526,9 +518,6 @@ typedef struct pciio_provider_s {
     pciio_driver_reg_callback_f *driver_reg_callback;
     pciio_driver_unreg_callback_f *driver_unreg_callback;
     pciio_device_unregister_f 	*device_unregister;
-
-    /* GENERIC BUS INFO */
-    pciio_businfo_get_f *businfo_get;
 } pciio_provider_t;
 
 /* PCI devices use these standard PCI provider interfaces */
@@ -556,12 +545,9 @@ extern pciio_intr_cpu_get_f pciio_intr_cpu_get;
 extern pciio_provider_startup_f pciio_provider_startup;
 extern pciio_provider_shutdown_f pciio_provider_shutdown;
 extern pciio_reset_f pciio_reset;
-extern pciio_write_gather_flush_f pciio_write_gather_flush;
 extern pciio_endian_set_f pciio_endian_set;
-extern pciio_priority_set_f pciio_priority_set;
 extern pciio_config_get_f pciio_config_get;
 extern pciio_config_set_f pciio_config_set;
-extern pciio_error_extract_f pciio_error_extract;
 
 /* Widgetdev in the IOERROR structure is encoded as follows.
  *	+---------------------------+
@@ -706,10 +692,8 @@ extern pciio_provider_t *pciio_provider_fns_get(vertex_hdl_t provider);
 /* Generic pci slot information access interface */
 extern pciio_info_t     pciio_info_chk(vertex_hdl_t vhdl);
 extern pciio_info_t     pciio_info_get(vertex_hdl_t vhdl);
-extern pciio_info_t     pciio_hostinfo_get(vertex_hdl_t vhdl);
 extern void             pciio_info_set(vertex_hdl_t vhdl, pciio_info_t widget_info);
 extern vertex_hdl_t     pciio_info_dev_get(pciio_info_t pciio_info);
-extern vertex_hdl_t     pciio_info_hostdev_get(pciio_info_t pciio_info);
 extern pciio_bus_t	pciio_info_bus_get(pciio_info_t pciio_info);
 extern pciio_slot_t     pciio_info_slot_get(pciio_info_t pciio_info);
 extern pciio_function_t	pciio_info_function_get(pciio_info_t pciio_info);
@@ -753,8 +737,7 @@ sn_pci_set_vchan(struct pci_dev *pci_dev,
 	if (vchan == 1) {
 		/* Set Bit 57 */
 		*addr |= (1UL << 57);
-	}
-	else {
+	} else {
 		/* Clear Bit 57 */
 		*addr &= ~(1UL << 57);
 	}
diff --git a/include/asm-ia64/sn/pci/pic.h b/include/asm-ia64/sn/pci/pic.h
index 32322ff4ab54..143534986ea3 100644
--- a/include/asm-ia64/sn/pci/pic.h
+++ b/include/asm-ia64/sn/pci/pic.h
@@ -66,7 +66,7 @@
 #include <asm/sn/pci/pciio.h>
 
 
-/*********************************************************************
+/*
  *    bus provider function table
  *
  *	Normally, this table is only handed off explicitly
@@ -81,705 +81,178 @@
 extern pciio_provider_t pci_pic_provider;
 
 
-/*********************************************************************
+/*
  * misc defines
  *
  */
+
 #define PIC_WIDGET_PART_NUM_BUS0 0xd102
 #define PIC_WIDGET_PART_NUM_BUS1 0xd112
 #define PIC_WIDGET_MFGR_NUM 0x24
 #define PIC_WIDGET_REV_A  0x1
+#define PIC_WIDGET_REV_B  0x2
+#define PIC_WIDGET_REV_C  0x3
+
+#define PIC_XTALK_ADDR_MASK                     0x0000FFFFFFFFFFFF
+#define PIC_INTERNAL_ATES                       1024
+
 
 #define IS_PIC_PART_REV_A(rev) \
 	((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_A)) || \
 	(rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_A)))
+#define IS_PIC_PART_REV_B(rev) \
+        ((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_B)) || \
+        (rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_B)))
+#define IS_PIC_PART_REV_C(rev) \
+        ((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_C)) || \
+        (rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_C)))
+
 
-/*********************************************************************
- * register offset defines
+/*
+ * misc typedefs
  *
  */
-	/* Identification Register  -- read-only */
-#define PIC_IDENTIFICATION 0x00000000
-
-	/* Status Register  -- read-only */
-#define PIC_STATUS 0x00000008
-
-	/* Upper Address Holding Register Bus Side Errors  -- read-only */
-#define PIC_UPPER_ADDR_REG_BUS_SIDE_ERRS 0x00000010
-
-	/* Lower Address Holding Register Bus Side Errors  -- read-only */
-#define PIC_LOWER_ADDR_REG_BUS_SIDE_ERRS 0x00000018
-
-	/* Control Register  -- read/write */
-#define PIC_CONTROL 0x00000020
-
-	/* PCI Request Time-out Value Register  -- read/write */
-#define PIC_PCI_REQ_TIME_OUT_VALUE 0x00000028
-
-	/* Interrupt Destination Upper Address Register  -- read/write */
-#define PIC_INTR_DEST_UPPER_ADDR 0x00000030
-
-	/* Interrupt Destination Lower Address Register  -- read/write */
-#define PIC_INTR_DEST_LOWER_ADDR 0x00000038
-
-	/* Command Word Holding Register Bus Side  -- read-only */
-#define PIC_CMD_WORD_REG_BUS_SIDE 0x00000040
-
-	/* LLP Configuration Register (Bus 0 Only)  -- read/write */
-#define PIC_LLP_CFG_REG_(BUS_0_ONLY) 0x00000048
-
-	/* PCI Target Flush Register  -- read-only */
-#define PIC_PCI_TARGET_FLUSH 0x00000050
-
-	/* Command Word Holding Register Link Side  -- read-only */
-#define PIC_CMD_WORD_REG_LINK_SIDE 0x00000058
-
-	/* Response Buffer Error Upper Address Holding  -- read-only */
-#define PIC_RESP_BUF_ERR_UPPER_ADDR_ 0x00000060
-
-	/* Response Buffer Error Lower Address Holding  -- read-only */
-#define PIC_RESP_BUF_ERR_LOWER_ADDR_ 0x00000068
-
-	/* Test Pin Control Register  -- read/write */
-#define PIC_TEST_PIN_CONTROL 0x00000070
-
-	/* Address Holding Register Link Side Errors  -- read-only */
-#define PIC_ADDR_REG_LINK_SIDE_ERRS 0x00000078
-
-	/* Direct Map Register  -- read/write */
-#define PIC_DIRECT_MAP 0x00000080
-
-	/* PCI Map Fault Address Register  -- read-only */
-#define PIC_PCI_MAP_FAULT_ADDR 0x00000090
-
-	/* Arbitration Priority Register  -- read/write */
-#define PIC_ARBITRATION_PRIORITY 0x000000A0
-
-	/* Internal Ram Parity Error Register  -- read-only */
-#define PIC_INTERNAL_RAM_PARITY_ERR 0x000000B0
-
-	/* PCI Time-out Register  -- read/write */
-#define PIC_PCI_TIME_OUT 0x000000C0
-
-	/* PCI Type 1 Configuration Register  -- read/write */
-#define PIC_PCI_TYPE_1_CFG 0x000000C8
-
-	/* PCI Bus Error Upper Address Holding Register  -- read-only */
-#define PIC_PCI_BUS_ERR_UPPER_ADDR_ 0x000000D0
-
-	/* PCI Bus Error Lower Address Holding Register  -- read-only */
-#define PIC_PCI_BUS_ERR_LOWER_ADDR_ 0x000000D8
-
-	/* PCIX Error Address Register  -- read-only */
-#define PIC_PCIX_ERR_ADDR 0x000000E0
-
-	/* PCIX Error Attribute Register  -- read-only */
-#define PIC_PCIX_ERR_ATTRIBUTE 0x000000E8
-
-	/* PCIX Error Data Register  -- read-only */
-#define PIC_PCIX_ERR_DATA 0x000000F0
-
-	/* PCIX Read Request Timeout Error Register  -- read-only */
-#define PIC_PCIX_READ_REQ_TIMEOUT_ERR 0x000000F8
-
-	/* Interrupt Status Register  -- read-only */
-#define PIC_INTR_STATUS 0x00000100
-
-	/* Interrupt Enable Register  -- read/write */
-#define PIC_INTR_ENABLE 0x00000108
-
-	/* Reset Interrupt Status Register  -- write-only */
-#define PIC_RESET_INTR_STATUS 0x00000110
-
-	/* Interrupt Mode Register  -- read/write */
-#define PIC_INTR_MODE 0x00000118
-
-	/* Interrupt Device Register  -- read/write */
-#define PIC_INTR_DEVICE 0x00000120
-
-	/* Host Error Field Register  -- read/write */
-#define PIC_HOST_ERR_FIELD 0x00000128
-
-	/* Interrupt Pin 0 Host Address Register  -- read/write */
-#define PIC_INTR_PIN_0_HOST_ADDR 0x00000130
-
-	/* Interrupt Pin 1 Host Address Register  -- read/write */
-#define PIC_INTR_PIN_1_HOST_ADDR 0x00000138
-
-	/* Interrupt Pin 2 Host Address Register  -- read/write */
-#define PIC_INTR_PIN_2_HOST_ADDR 0x00000140
-
-	/* Interrupt Pin 3 Host Address Register  -- read/write */
-#define PIC_INTR_PIN_3_HOST_ADDR 0x00000148
-
-	/* Interrupt Pin 4 Host Address Register  -- read/write */
-#define PIC_INTR_PIN_4_HOST_ADDR 0x00000150
-
-	/* Interrupt Pin 5 Host Address Register  -- read/write */
-#define PIC_INTR_PIN_5_HOST_ADDR 0x00000158
-
-	/* Interrupt Pin 6 Host Address Register  -- read/write */
-#define PIC_INTR_PIN_6_HOST_ADDR 0x00000160
-
-	/* Interrupt Pin 7 Host Address Register  -- read/write */
-#define PIC_INTR_PIN_7_HOST_ADDR 0x00000168
-
-	/* Error Interrupt View Register  -- read-only */
-#define PIC_ERR_INTR_VIEW 0x00000170
-
-	/* Multiple Interrupt Register  -- read-only */
-#define PIC_MULTIPLE_INTR 0x00000178
-
-	/* Force Always Interrupt 0 Register  -- write-only */
-#define PIC_FORCE_ALWAYS_INTR_0 0x00000180
-
-	/* Force Always Interrupt 1 Register  -- write-only */
-#define PIC_FORCE_ALWAYS_INTR_1 0x00000188
-
-	/* Force Always Interrupt 2 Register  -- write-only */
-#define PIC_FORCE_ALWAYS_INTR_2 0x00000190
-
-	/* Force Always Interrupt 3 Register  -- write-only */
-#define PIC_FORCE_ALWAYS_INTR_3 0x00000198
-
-	/* Force Always Interrupt 4 Register  -- write-only */
-#define PIC_FORCE_ALWAYS_INTR_4 0x000001A0
-
-	/* Force Always Interrupt 5 Register  -- write-only */
-#define PIC_FORCE_ALWAYS_INTR_5 0x000001A8
-
-	/* Force Always Interrupt 6 Register  -- write-only */
-#define PIC_FORCE_ALWAYS_INTR_6 0x000001B0
-
-	/* Force Always Interrupt 7 Register  -- write-only */
-#define PIC_FORCE_ALWAYS_INTR_7 0x000001B8
-
-	/* Force w/Pin Interrupt 0 Register  -- write-only */
-#define PIC_FORCE_PIN_INTR_0 0x000001C0
-
-	/* Force w/Pin Interrupt 1 Register  -- write-only */
-#define PIC_FORCE_PIN_INTR_1 0x000001C8
-
-	/* Force w/Pin Interrupt 2 Register  -- write-only */
-#define PIC_FORCE_PIN_INTR_2 0x000001D0
-
-	/* Force w/Pin Interrupt 3 Register  -- write-only */
-#define PIC_FORCE_PIN_INTR_3 0x000001D8
-
-	/* Force w/Pin Interrupt 4 Register  -- write-only */
-#define PIC_FORCE_PIN_INTR_4 0x000001E0
-
-	/* Force w/Pin Interrupt 5 Register  -- write-only */
-#define PIC_FORCE_PIN_INTR_5 0x000001E8
-
-	/* Force w/Pin Interrupt 6 Register  -- write-only */
-#define PIC_FORCE_PIN_INTR_6 0x000001F0
-
-	/* Force w/Pin Interrupt 7 Register  -- write-only */
-#define PIC_FORCE_PIN_INTR_7 0x000001F8
-
-	/* Device 0 Register  -- read/write */
-#define PIC_DEVICE_0 0x00000200
-
-	/* Device 1 Register  -- read/write */
-#define PIC_DEVICE_1 0x00000208
-
-	/* Device 2 Register  -- read/write */
-#define PIC_DEVICE_2 0x00000210
-
-	/* Device 3 Register  -- read/write */
-#define PIC_DEVICE_3 0x00000218
-
-	/* Device 0 Write Request Buffer Register  -- read-only */
-#define PIC_DEVICE_0_WRITE_REQ_BUF 0x00000240
-
-	/* Device 1 Write Request Buffer Register  -- read-only */
-#define PIC_DEVICE_1_WRITE_REQ_BUF 0x00000248
-
-	/* Device 2 Write Request Buffer Register  -- read-only */
-#define PIC_DEVICE_2_WRITE_REQ_BUF 0x00000250
-
-	/* Device 3 Write Request Buffer Register  -- read-only */
-#define PIC_DEVICE_3_WRITE_REQ_BUF 0x00000258
-
-	/* Even Device Response Buffer Register  -- read/write */
-#define PIC_EVEN_DEVICE_RESP_BUF 0x00000280
-
-	/* Odd Device Response Buffer Register  -- read/write */
-#define PIC_ODD_DEVICE_RESP_BUF 0x00000288
-
-	/* Read Response Buffer Status Register  -- read-only */
-#define PIC_READ_RESP_BUF_STATUS 0x00000290
-
-	/* Read Response Buffer Clear Register  -- write-only */
-#define PIC_READ_RESP_BUF_CLEAR 0x00000298
-
-	/* PCI RR 0 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_0_UPPER_ADDR_MATCH 0x00000300
-
-	/* PCI RR 0 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_0_LOWER_ADDR_MATCH 0x00000308
-
-	/* PCI RR 1 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_1_UPPER_ADDR_MATCH 0x00000310
-
-	/* PCI RR 1 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_1_LOWER_ADDR_MATCH 0x00000318
-
-	/* PCI RR 2 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_2_UPPER_ADDR_MATCH 0x00000320
-
-	/* PCI RR 2 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_2_LOWER_ADDR_MATCH 0x00000328
-
-	/* PCI RR 3 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_3_UPPER_ADDR_MATCH 0x00000330
-
-	/* PCI RR 3 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_3_LOWER_ADDR_MATCH 0x00000338
-
-	/* PCI RR 4 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_4_UPPER_ADDR_MATCH 0x00000340
-
-	/* PCI RR 4 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_4_LOWER_ADDR_MATCH 0x00000348
-
-	/* PCI RR 5 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_5_UPPER_ADDR_MATCH 0x00000350
-
-	/* PCI RR 5 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_5_LOWER_ADDR_MATCH 0x00000358
-
-	/* PCI RR 6 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_6_UPPER_ADDR_MATCH 0x00000360
-
-	/* PCI RR 6 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_6_LOWER_ADDR_MATCH 0x00000368
-
-	/* PCI RR 7 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_7_UPPER_ADDR_MATCH 0x00000370
-
-	/* PCI RR 7 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_7_LOWER_ADDR_MATCH 0x00000378
-
-	/* PCI RR 8 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_8_UPPER_ADDR_MATCH 0x00000380
-
-	/* PCI RR 8 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_8_LOWER_ADDR_MATCH 0x00000388
-
-	/* PCI RR 9 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_9_UPPER_ADDR_MATCH 0x00000390
-
-	/* PCI RR 9 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_9_LOWER_ADDR_MATCH 0x00000398
-
-	/* PCI RR 10 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_10_UPPER_ADDR_MATCH 0x000003A0
-
-	/* PCI RR 10 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_10_LOWER_ADDR_MATCH 0x000003A8
-
-	/* PCI RR 11 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_11_UPPER_ADDR_MATCH 0x000003B0
-
-	/* PCI RR 11 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_11_LOWER_ADDR_MATCH 0x000003B8
-
-	/* PCI RR 12 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_12_UPPER_ADDR_MATCH 0x000003C0
-
-	/* PCI RR 12 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_12_LOWER_ADDR_MATCH 0x000003C8
-
-	/* PCI RR 13 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_13_UPPER_ADDR_MATCH 0x000003D0
-
-	/* PCI RR 13 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_13_LOWER_ADDR_MATCH 0x000003D8
-
-	/* PCI RR 14 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_14_UPPER_ADDR_MATCH 0x000003E0
-
-	/* PCI RR 14 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_14_LOWER_ADDR_MATCH 0x000003E8
-
-	/* PCI RR 15 Upper Address Match Register  -- read-only */
-#define PIC_PCI_RR_15_UPPER_ADDR_MATCH 0x000003F0
-
-	/* PCI RR 15 Lower Address Match Register  -- read-only */
-#define PIC_PCI_RR_15_LOWER_ADDR_MATCH 0x000003F8
-
-	/* Buffer 0 Flush Count with Data Touch Register  -- read/write */
-#define PIC_BUF_0_FLUSH_CNT_WITH_DATA_TOUCH 0x00000400
-
-	/* Buffer 0 Flush Count w/o Data Touch Register  -- read/write */
-#define PIC_BUF_0_FLUSH_CNT_W_O_DATA_TOUCH 0x00000408
-
-	/* Buffer 0 Request in Flight Count Register  -- read/write */
-#define PIC_BUF_0_REQ_IN_FLIGHT_CNT 0x00000410
-
-	/* Buffer 0 Prefetch Request Count Register  -- read/write */
-#define PIC_BUF_0_PREFETCH_REQ_CNT 0x00000418
-
-	/* Buffer 0 Total PCI Retry Count Register  -- read/write */
-#define PIC_BUF_0_TOTAL_PCI_RETRY_CNT 0x00000420
-
-	/* Buffer 0 Max PCI Retry Count Register  -- read/write */
-#define PIC_BUF_0_MAX_PCI_RETRY_CNT 0x00000428
-
-	/* Buffer 0 Max Latency Count Register  -- read/write */
-#define PIC_BUF_0_MAX_LATENCY_CNT 0x00000430
-
-	/* Buffer 0 Clear All Register  -- read/write */
-#define PIC_BUF_0_CLEAR_ALL 0x00000438
-
-	/* Buffer 2 Flush Count with Data Touch Register  -- read/write */
-#define PIC_BUF_2_FLUSH_CNT_WITH_DATA_TOUCH 0x00000440
-
-	/* Buffer 2 Flush Count w/o Data Touch Register  -- read/write */
-#define PIC_BUF_2_FLUSH_CNT_W_O_DATA_TOUCH 0x00000448
-
-	/* Buffer 2 Request in Flight Count Register  -- read/write */
-#define PIC_BUF_2_REQ_IN_FLIGHT_CNT 0x00000450
-
-	/* Buffer 2 Prefetch Request Count Register  -- read/write */
-#define PIC_BUF_2_PREFETCH_REQ_CNT 0x00000458
-
-	/* Buffer 2 Total PCI Retry Count Register  -- read/write */
-#define PIC_BUF_2_TOTAL_PCI_RETRY_CNT 0x00000460
-
-	/* Buffer 2 Max PCI Retry Count Register  -- read/write */
-#define PIC_BUF_2_MAX_PCI_RETRY_CNT 0x00000468
-
-	/* Buffer 2 Max Latency Count Register  -- read/write */
-#define PIC_BUF_2_MAX_LATENCY_CNT 0x00000470
-
-	/* Buffer 2 Clear All Register  -- read/write */
-#define PIC_BUF_2_CLEAR_ALL 0x00000478
-
-	/* Buffer 4 Flush Count with Data Touch Register  -- read/write */
-#define PIC_BUF_4_FLUSH_CNT_WITH_DATA_TOUCH 0x00000480
-
-	/* Buffer 4 Flush Count w/o Data Touch Register  -- read/write */
-#define PIC_BUF_4_FLUSH_CNT_W_O_DATA_TOUCH 0x00000488
-
-	/* Buffer 4 Request in Flight Count Register  -- read/write */
-#define PIC_BUF_4_REQ_IN_FLIGHT_CNT 0x00000490
-
-	/* Buffer 4 Prefetch Request Count Register  -- read/write */
-#define PIC_BUF_4_PREFETCH_REQ_CNT 0x00000498
-
-	/* Buffer 4 Total PCI Retry Count Register  -- read/write */
-#define PIC_BUF_4_TOTAL_PCI_RETRY_CNT 0x000004A0
-
-	/* Buffer 4 Max PCI Retry Count Register  -- read/write */
-#define PIC_BUF_4_MAX_PCI_RETRY_CNT 0x000004A8
-
-	/* Buffer 4 Max Latency Count Register  -- read/write */
-#define PIC_BUF_4_MAX_LATENCY_CNT 0x000004B0
-
-	/* Buffer 4 Clear All Register  -- read/write */
-#define PIC_BUF_4_CLEAR_ALL 0x000004B8
-
-	/* Buffer 6 Flush Count with Data Touch Register  -- read/write */
-#define PIC_BUF_6_FLUSH_CNT_WITH_DATA_TOUCH 0x000004C0
-
-	/* Buffer 6 Flush Count w/o Data Touch Register  -- read/write */
-#define PIC_BUF_6_FLUSH_CNT_W_O_DATA_TOUCH 0x000004C8
-
-	/* Buffer 6 Request in Flight Count Register  -- read/write */
-#define PIC_BUF_6_REQ_IN_FLIGHT_CNT 0x000004D0
-
-	/* Buffer 6 Prefetch Request Count Register  -- read/write */
-#define PIC_BUF_6_PREFETCH_REQ_CNT 0x000004D8
-
-	/* Buffer 6 Total PCI Retry Count Register  -- read/write */
-#define PIC_BUF_6_TOTAL_PCI_RETRY_CNT 0x000004E0
-
-	/* Buffer 6 Max PCI Retry Count Register  -- read/write */
-#define PIC_BUF_6_MAX_PCI_RETRY_CNT 0x000004E8
-
-	/* Buffer 6 Max Latency Count Register  -- read/write */
-#define PIC_BUF_6_MAX_LATENCY_CNT 0x000004F0
-
-	/* Buffer 6 Clear All Register  -- read/write */
-#define PIC_BUF_6_CLEAR_ALL 0x000004F8
-
-	/* Buffer 8 Flush Count with Data Touch Register  -- read/write */
-#define PIC_BUF_8_FLUSH_CNT_WITH_DATA_TOUCH 0x00000500
-
-	/* Buffer 8 Flush Count w/o Data Touch Register  -- read/write */
-#define PIC_BUF_8_FLUSH_CNT_W_O_DATA_TOUCH 0x00000508
-
-	/* Buffer 8 Request in Flight Count Register  -- read/write */
-#define PIC_BUF_8_REQ_IN_FLIGHT_CNT 0x00000510
-
-	/* Buffer 8 Prefetch Request Count Register  -- read/write */
-#define PIC_BUF_8_PREFETCH_REQ_CNT 0x00000518
-
-	/* Buffer 8 Total PCI Retry Count Register  -- read/write */
-#define PIC_BUF_8_TOTAL_PCI_RETRY_CNT 0x00000520
-
-	/* Buffer 8 Max PCI Retry Count Register  -- read/write */
-#define PIC_BUF_8_MAX_PCI_RETRY_CNT 0x00000528
-
-	/* Buffer 8 Max Latency Count Register  -- read/write */
-#define PIC_BUF_8_MAX_LATENCY_CNT 0x00000530
-
-	/* Buffer 8 Clear All Register  -- read/write */
-#define PIC_BUF_8_CLEAR_ALL 0x00000538
-
-	/* Buffer 10 Flush Count with Data Touch Register  -- read/write */
-#define PIC_BUF_10_FLUSH_CNT_WITH_DATA_TOUCH 0x00000540
-
-	/* Buffer 10 Flush Count w/o Data Touch Register  -- read/write */
-#define PIC_BUF_10_FLUSH_CNT_W_O_DATA_TOUCH 0x00000548
-
-	/* Buffer 10 Request in Flight Count Register  -- read/write */
-#define PIC_BUF_10_REQ_IN_FLIGHT_CNT 0x00000550
-
-	/* Buffer 10 Prefetch Request Count Register  -- read/write */
-#define PIC_BUF_10_PREFETCH_REQ_CNT 0x00000558
-
-	/* Buffer 10 Total PCI Retry Count Register  -- read/write */
-#define PIC_BUF_10_TOTAL_PCI_RETRY_CNT 0x00000560
-
-	/* Buffer 10 Max PCI Retry Count Register  -- read/write */
-#define PIC_BUF_10_MAX_PCI_RETRY_CNT 0x00000568
-
-	/* Buffer 10 Max Latency Count Register  -- read/write */
-#define PIC_BUF_10_MAX_LATENCY_CNT 0x00000570
-
-	/* Buffer 10 Clear All Register  -- read/write */
-#define PIC_BUF_10_CLEAR_ALL 0x00000578
-
-	/* Buffer 12 Flush Count with Data Touch Register  -- read/write */
-#define PIC_BUF_12_FLUSH_CNT_WITH_DATA_TOUCH 0x00000580
-
-	/* Buffer 12 Flush Count w/o Data Touch Register  -- read/write */
-#define PIC_BUF_12_FLUSH_CNT_W_O_DATA_TOUCH 0x00000588
-
-	/* Buffer 12 Request in Flight Count Register  -- read/write */
-#define PIC_BUF_12_REQ_IN_FLIGHT_CNT 0x00000590
-
-	/* Buffer 12 Prefetch Request Count Register  -- read/write */
-#define PIC_BUF_12_PREFETCH_REQ_CNT 0x00000598
-
-	/* Buffer 12 Total PCI Retry Count Register  -- read/write */
-#define PIC_BUF_12_TOTAL_PCI_RETRY_CNT 0x000005A0
-
-	/* Buffer 12 Max PCI Retry Count Register  -- read/write */
-#define PIC_BUF_12_MAX_PCI_RETRY_CNT 0x000005A8
-
-	/* Buffer 12 Max Latency Count Register  -- read/write */
-#define PIC_BUF_12_MAX_LATENCY_CNT 0x000005B0
-
-	/* Buffer 12 Clear All Register  -- read/write */
-#define PIC_BUF_12_CLEAR_ALL 0x000005B8
-
-	/* Buffer 14 Flush Count with Data Touch Register  -- read/write */
-#define PIC_BUF_14_FLUSH_CNT_WITH_DATA_TOUCH 0x000005C0
-
-	/* Buffer 14 Flush Count w/o Data Touch Register  -- read/write */
-#define PIC_BUF_14_FLUSH_CNT_W_O_DATA_TOUCH 0x000005C8
-
-	/* Buffer 14 Request in Flight Count Register  -- read/write */
-#define PIC_BUF_14_REQ_IN_FLIGHT_CNT 0x000005D0
-
-	/* Buffer 14 Prefetch Request Count Register  -- read/write */
-#define PIC_BUF_14_PREFETCH_REQ_CNT 0x000005D8
-
-	/* Buffer 14 Total PCI Retry Count Register  -- read/write */
-#define PIC_BUF_14_TOTAL_PCI_RETRY_CNT 0x000005E0
-
-	/* Buffer 14 Max PCI Retry Count Register  -- read/write */
-#define PIC_BUF_14_MAX_PCI_RETRY_CNT 0x000005E8
-
-	/* Buffer 14 Max Latency Count Register  -- read/write */
-#define PIC_BUF_14_MAX_LATENCY_CNT 0x000005F0
-
-	/* Buffer 14 Clear All Register  -- read/write */
-#define PIC_BUF_14_CLEAR_ALL 0x000005F8
-
-	/* PCIX Read Buffer 0 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_0_ADDR 0x00000A00
-
-	/* PCIX Read Buffer 0 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_0_ATTRIBUTE 0x00000A08
-
-	/* PCIX Read Buffer 1 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_1_ADDR 0x00000A10
-
-	/* PCIX Read Buffer 1 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_1_ATTRIBUTE 0x00000A18
-
-	/* PCIX Read Buffer 2 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_2_ADDR 0x00000A20
-
-	/* PCIX Read Buffer 2 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_2_ATTRIBUTE 0x00000A28
-
-	/* PCIX Read Buffer 3 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_3_ADDR 0x00000A30
-
-	/* PCIX Read Buffer 3 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_3_ATTRIBUTE 0x00000A38
-
-	/* PCIX Read Buffer 4 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_4_ADDR 0x00000A40
-
-	/* PCIX Read Buffer 4 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_4_ATTRIBUTE 0x00000A48
-
-	/* PCIX Read Buffer 5 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_5_ADDR 0x00000A50
-
-	/* PCIX Read Buffer 5 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_5_ATTRIBUTE 0x00000A58
-
-	/* PCIX Read Buffer 6 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_6_ADDR 0x00000A60
-
-	/* PCIX Read Buffer 6 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_6_ATTRIBUTE 0x00000A68
-
-	/* PCIX Read Buffer 7 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_7_ADDR 0x00000A70
-
-	/* PCIX Read Buffer 7 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_7_ATTRIBUTE 0x00000A78
-
-	/* PCIX Read Buffer 8 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_8_ADDR 0x00000A80
-
-	/* PCIX Read Buffer 8 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_8_ATTRIBUTE 0x00000A88
-
-	/* PCIX Read Buffer 9 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_9_ADDR 0x00000A90
-
-	/* PCIX Read Buffer 9 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_9_ATTRIBUTE 0x00000A98
-
-	/* PCIX Read Buffer 10 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_10_ADDR 0x00000AA0
-
-	/* PCIX Read Buffer 10 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_10_ATTRIBUTE 0x00000AA8
-
-	/* PCIX Read Buffer 11 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_11_ADDR 0x00000AB0
-
-	/* PCIX Read Buffer 11 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_11_ATTRIBUTE 0x00000AB8
-
-	/* PCIX Read Buffer 12 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_12_ADDR 0x00000AC0
-
-	/* PCIX Read Buffer 12 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_12_ATTRIBUTE 0x00000AC8
-
-	/* PCIX Read Buffer 13 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_13_ADDR 0x00000AD0
-
-	/* PCIX Read Buffer 13 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_13_ATTRIBUTE 0x00000AD8
-
-	/* PCIX Read Buffer 14 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_14_ADDR 0x00000AE0
-
-	/* PCIX Read Buffer 14 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_14_ATTRIBUTE 0x00000AE8
-
-	/* PCIX Read Buffer 15 Address Register  -- read-only */
-#define PIC_PCIX_READ_BUF_15_ADDR 0x00000AF0
-
-	/* PCIX Read Buffer 15 Attribute Register  -- read-only */
-#define PIC_PCIX_READ_BUF_15_ATTRIBUTE 0x00000AF8
-
-	/* PCIX Write Buffer 0 Address Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_0_ADDR 0x00000B00
-
-	/* PCIX Write Buffer 0 Attribute Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_0_ATTRIBUTE 0x00000B08
-
-	/* PCIX Write Buffer 0 Valid Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_0_VALID 0x00000B10
-
-	/* PCIX Write Buffer 1 Address Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_1_ADDR 0x00000B20
-
-	/* PCIX Write Buffer 1 Attribute Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_1_ATTRIBUTE 0x00000B28
-
-	/* PCIX Write Buffer 1 Valid Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_1_VALID 0x00000B30
-
-	/* PCIX Write Buffer 2 Address Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_2_ADDR 0x00000B40
-
-	/* PCIX Write Buffer 2 Attribute Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_2_ATTRIBUTE 0x00000B48
+typedef uint64_t picreg_t;
+typedef uint64_t picate_t;
 
-	/* PCIX Write Buffer 2 Valid Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_2_VALID 0x00000B50
+/*
+ * PIC Bridge MMR defines
+ */
 
-	/* PCIX Write Buffer 3 Address Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_3_ADDR 0x00000B60
+/*
+ * PIC STATUS register          offset 0x00000008
+ */
 
-	/* PCIX Write Buffer 3 Attribute Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_3_ATTRIBUTE 0x00000B68
+#define PIC_STAT_PCIX_ACTIVE_SHFT       33
 
-	/* PCIX Write Buffer 3 Valid Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_3_VALID 0x00000B70
+/*
+ * PIC CONTROL register         offset 0x00000020
+ */
 
-	/* PCIX Write Buffer 4 Address Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_4_ADDR 0x00000B80
+#define PIC_CTRL_PCI_SPEED_SHFT         4
+#define PIC_CTRL_PCI_SPEED              (0x3 << PIC_CTRL_PCI_SPEED_SHFT)
+#define PIC_CTRL_PAGE_SIZE_SHFT         21
+#define PIC_CTRL_PAGE_SIZE              (0x1 << PIC_CTRL_PAGE_SIZE_SHFT)
 
-	/* PCIX Write Buffer 4 Attribute Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_4_ATTRIBUTE 0x00000B88
 
-	/* PCIX Write Buffer 4 Valid Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_4_VALID 0x00000B90
+/*
+ * PIC Intr Destination Addr    offset 0x00000038
+ */
 
-	/* PCIX Write Buffer 5 Address Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_5_ADDR 0x00000BA0
+#define PIC_INTR_DEST_ADDR              0x0000FFFFFFFFFFFF
+#define PIC_INTR_DEST_TID_SHFT          48
+#define PIC_INTR_DEST_TID               (0xFull << PIC_INTR_DEST_TID_SHFT)
 
-	/* PCIX Write Buffer 5 Attribute Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_5_ATTRIBUTE 0x00000BA8
+/*
+ * PIC PCI Responce Buffer      offset 0x00000068
+ */
+#define PIC_RSP_BUF_ADDR                0x0000FFFFFFFFFFFF
+#define PIC_RSP_BUF_NUM_SHFT            48
+#define PIC_RSP_BUF_NUM                 (0xFull << PIC_RSP_BUF_NUM_SHFT)
+#define PIC_RSP_BUF_DEV_NUM_SHFT        52
+#define PIC_RSP_BUF_DEV_NUM             (0x3ull << PIC_RSP_BUF_DEV_NUM_SHFT)
 
-	/* PCIX Write Buffer 5 Valid Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_5_VALID 0x00000BB0
+/*
+ * PIC PCI DIRECT MAP register  offset 0x00000080
+ */
+#define PIC_DIRMAP_DIROFF_SHFT          0
+#define PIC_DIRMAP_DIROFF               (0x1FFFF << PIC_DIRMAP_DIROFF_SHFT)
+#define PIC_DIRMAP_ADD512_SHFT          17
+#define PIC_DIRMAP_ADD512               (0x1 << PIC_DIRMAP_ADD512_SHFT)
+#define PIC_DIRMAP_WID_SHFT             20
+#define PIC_DIRMAP_WID                  (0xF << PIC_DIRMAP_WID_SHFT)
 
-	/* PCIX Write Buffer 6 Address Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_6_ADDR 0x00000BC0
+#define PIC_DIRMAP_OFF_ADDRSHFT         31
 
-	/* PCIX Write Buffer 6 Attribute Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_6_ATTRIBUTE 0x00000BC8
+/*
+ * Interrupt Status register            offset 0x00000100
+ */
+#define PIC_ISR_PCIX_SPLIT_MSG_PE     (0x1ull << 45)
+#define PIC_ISR_PCIX_SPLIT_EMSG       (0x1ull << 44)
+#define PIC_ISR_PCIX_SPLIT_TO         (0x1ull << 43)
+#define PIC_ISR_PCIX_UNEX_COMP        (0x1ull << 42)
+#define PIC_ISR_INT_RAM_PERR          (0x1ull << 41)
+#define PIC_ISR_PCIX_ARB_ERR          (0x1ull << 40)
+#define PIC_ISR_PCIX_REQ_TOUT         (0x1ull << 39)
+#define PIC_ISR_PCIX_TABORT           (0x1ull << 38)
+#define PIC_ISR_PCIX_PERR             (0x1ull << 37)
+#define PIC_ISR_PCIX_SERR             (0x1ull << 36)
+#define PIC_ISR_PCIX_MRETRY           (0x1ull << 35)
+#define PIC_ISR_PCIX_MTOUT            (0x1ull << 34)
+#define PIC_ISR_PCIX_DA_PARITY        (0x1ull << 33)
+#define PIC_ISR_PCIX_AD_PARITY        (0x1ull << 32)
+#define PIC_ISR_PMU_PAGE_FAULT        (0x1ull << 30)
+#define PIC_ISR_UNEXP_RESP            (0x1ull << 29)
+#define PIC_ISR_BAD_XRESP_PKT         (0x1ull << 28)
+#define PIC_ISR_BAD_XREQ_PKT          (0x1ull << 27)
+#define PIC_ISR_RESP_XTLK_ERR         (0x1ull << 26)
+#define PIC_ISR_REQ_XTLK_ERR          (0x1ull << 25)
+#define PIC_ISR_INVLD_ADDR            (0x1ull << 24)
+#define PIC_ISR_UNSUPPORTED_XOP       (0x1ull << 23)
+#define PIC_ISR_XREQ_FIFO_OFLOW       (0x1ull << 22)
+#define PIC_ISR_LLP_REC_SNERR         (0x1ull << 21)
+#define PIC_ISR_LLP_REC_CBERR         (0x1ull << 20)
+#define PIC_ISR_LLP_RCTY              (0x1ull << 19)
+#define PIC_ISR_LLP_TX_RETRY          (0x1ull << 18)
+#define PIC_ISR_LLP_TCTY              (0x1ull << 17)
+#define PIC_ISR_PCI_ABORT             (0x1ull << 15)
+#define PIC_ISR_PCI_PARITY            (0x1ull << 14)
+#define PIC_ISR_PCI_SERR              (0x1ull << 13)
+#define PIC_ISR_PCI_PERR              (0x1ull << 12)
+#define PIC_ISR_PCI_MST_TIMEOUT       (0x1ull << 11)
+#define PIC_ISR_PCI_RETRY_CNT         (0x1ull << 10)
+#define PIC_ISR_XREAD_REQ_TIMEOUT     (0x1ull << 9)
+#define PIC_ISR_INT_MSK               (0xffull << 0)
+#define PIC_ISR_INT(x)                (0x1ull << (x))
+
+#define PIC_ISR_LINK_ERROR            \
+                (PIC_ISR_LLP_REC_SNERR|PIC_ISR_LLP_REC_CBERR|       \
+                 PIC_ISR_LLP_RCTY|PIC_ISR_LLP_TX_RETRY|             \
+                 PIC_ISR_LLP_TCTY)
+
+#define PIC_ISR_PCIBUS_PIOERR         \
+                (PIC_ISR_PCI_MST_TIMEOUT|PIC_ISR_PCI_ABORT|         \
+                 PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT)
+
+#define PIC_ISR_PCIBUS_ERROR          \
+                (PIC_ISR_PCIBUS_PIOERR|PIC_ISR_PCI_PERR|            \
+                 PIC_ISR_PCI_SERR|PIC_ISR_PCI_RETRY_CNT|            \
+                 PIC_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR|              \
+                 PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY|             \
+                 PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY|     \
+                 PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP|      \
+                 PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG|     \
+                 PIC_ISR_PCIX_SPLIT_MSG_PE)
+
+#define PIC_ISR_XTALK_ERROR           \
+                (PIC_ISR_XREAD_REQ_TIMEOUT|PIC_ISR_XREQ_FIFO_OFLOW| \
+                 PIC_ISR_UNSUPPORTED_XOP|PIC_ISR_INVLD_ADDR|        \
+                 PIC_ISR_REQ_XTLK_ERR|PIC_ISR_RESP_XTLK_ERR|        \
+                 PIC_ISR_BAD_XREQ_PKT|PIC_ISR_BAD_XRESP_PKT|        \
+                 PIC_ISR_UNEXP_RESP)
+
+#define PIC_ISR_ERRORS                \
+                (PIC_ISR_LINK_ERROR|PIC_ISR_PCIBUS_ERROR|           \
+                 PIC_ISR_XTALK_ERROR|                                 \
+                 PIC_ISR_PMU_PAGE_FAULT|PIC_ISR_INT_RAM_PERR)
 
-	/* PCIX Write Buffer 6 Valid Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_6_VALID 0x00000BD0
+/*
+ * PIC RESET INTR register      offset 0x00000110
+ */
 
-	/* PCIX Write Buffer 7 Address Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_7_ADDR 0x00000BE0
+#define PIC_IRR_ALL_CLR                 0xffffffffffffffff
 
-	/* PCIX Write Buffer 7 Attribute Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_7_ATTRIBUTE 0x00000BE8
+/*
+ * PIC PCI Host Intr Addr       offset 0x00000130 - 0x00000168
+ */
+#define PIC_HOST_INTR_ADDR              0x0000FFFFFFFFFFFF
+#define PIC_HOST_INTR_FLD_SHFT          48
+#define PIC_HOST_INTR_FLD               (0xFFull << PIC_HOST_INTR_FLD_SHFT)
 
-	/* PCIX Write Buffer 7 Valid Register  -- read-only */
-#define PIC_PCIX_WRITE_BUF_7_VALID 0x00000BF0
 
-/*********************************************************************
- * misc typedefs
- *
+/*
+ * PIC MMR structure mapping
  */
-typedef uint64_t picreg_t;
-typedef uint64_t picate_t;
-
-/*****************************************************************************
- *********************** PIC MMR structure mapping ***************************
- *****************************************************************************/
 
 /* NOTE: PIC WAR. PV#854697.  PIC does not allow writes just to [31:0]
  * of a 64-bit register.  When writing PIC registers, always write the 
diff --git a/include/asm-ia64/sn/sn2/intr.h b/include/asm-ia64/sn/sn2/intr.h
index 270b78bf99e5..2d3df0574b8c 100644
--- a/include/asm-ia64/sn/sn2/intr.h
+++ b/include/asm-ia64/sn/sn2/intr.h
@@ -19,8 +19,8 @@
 #define SGI_ACPI_SCI_INT		(0x34)
 #define SGI_XPC_NOTIFY			(0xe7)
 
-#define IA64_SN2_FIRST_DEVICE_VECTOR	(0x34)
-#define IA64_SN2_LAST_DEVICE_VECTOR	(0xe7)
+#define IA64_SN2_FIRST_DEVICE_VECTOR	(0x37)
+#define IA64_SN2_LAST_DEVICE_VECTOR	(0xe6)
 
 #define SN2_IRQ_RESERVED        (0x1)
 #define SN2_IRQ_CONNECTED       (0x2)