diff options
| author | Ben Dooks <ben-linux@org.rmk.(none)> | 2004-11-10 00:13:49 +0000 |
|---|---|---|
| committer | Russell King <rmk@flint.arm.linux.org.uk> | 2004-11-10 00:13:49 +0000 |
| commit | 5bffe1b1ac1ead8c9b07bcba90aee11c9e9e20d1 (patch) | |
| tree | e7a340f0de80896b37249f9a88d498f98e2268f8 /include | |
| parent | b26fed8e2c0c0930fc4419e664e95a52f3dbfcbc (diff) | |
[ARM PATCH] 2220/1: S3C2410 - regs-dsc.h fixes
Patch from Ben Dooks
The following fixes are included:
- fix the addresses of S3C2440_DSCx (off by 4)
- SCK0/SCK1 definitions the wrong way around
- renable ENABLE to DISABLE
Signed-off-by: Ben Dooks
Signed-off-by: Russell King
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-s3c2410/regs-dsc.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h index 0da1ec7b7675..a023b0434efe 100644 --- a/include/asm-arm/arch-s3c2410/regs-dsc.h +++ b/include/asm-arm/arch-s3c2410/regs-dsc.h @@ -20,15 +20,15 @@ #ifdef CONFIG_CPU_S3C2440 -#define S3C2440_DSC0 S3C2410_GPIOREG(0xc0) -#define S3C2440_DSC1 S3C2410_GPIOREG(0xc4) +#define S3C2440_DSC0 S3C2410_GPIOREG(0xc4) +#define S3C2440_DSC1 S3C2410_GPIOREG(0xc8) #define S3C2440_SELECT_DSC0 (0) #define S3C2440_SELECT_DSC1 (1<<31) #define S3C2440_DSC_GETSHIFT(x) ((x) & 31) -#define S3C2440_DSC0_ENABLE (1<<31) +#define S3C2440_DSC0_DISABLE (1<<31) #define S3C2440_DSC0_ADDR (S3C2440_SELECT_DSC0 | 8) #define S3C2440_DSC0_ADDR_12mA (0<<8) @@ -69,19 +69,19 @@ #define S3C2440_DSC0_DATA0_6mA (3<<0) #define S3C2440_DSC0_DATA0_MASK (3<<0) -#define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 28) -#define S3C2440_DSC1_SCK0_12mA (0<<28) -#define S3C2440_DSC1_SCK0_10mA (1<<28) -#define S3C2440_DSC1_SCK0_8mA (2<<28) -#define S3C2440_DSC1_SCK0_6mA (3<<28) -#define S3C2440_DSC1_SCK0_MASK (3<<28) - -#define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 26) -#define S3C2440_DSC1_SCK1_12mA (0<<26) -#define S3C2440_DSC1_SCK1_10mA (1<<26) -#define S3C2440_DSC1_SCK1_8mA (2<<26) -#define S3C2440_DSC1_SCK1_6mA (3<<26) -#define S3C2440_DSC1_SCK1_MASK (3<<26) +#define S3C2440_DSC1_SCK1 (S3C2440_SELECT_DSC1 | 28) +#define S3C2440_DSC1_SCK1_12mA (0<<28) +#define S3C2440_DSC1_SCK1_10mA (1<<28) +#define S3C2440_DSC1_SCK1_8mA (2<<28) +#define S3C2440_DSC1_SCK1_6mA (3<<28) +#define S3C2440_DSC1_SCK1_MASK (3<<28) + +#define S3C2440_DSC1_SCK0 (S3C2440_SELECT_DSC1 | 26) +#define S3C2440_DSC1_SCK0_12mA (0<<26) +#define S3C2440_DSC1_SCK0_10mA (1<<26) +#define S3C2440_DSC1_SCK0_8mA (2<<26) +#define S3C2440_DSC1_SCK0_6mA (3<<26) +#define S3C2440_DSC1_SCK0_MASK (3<<26) #define S3C2440_DSC1_SCKE (S3C2440_SELECT_DSC1 | 24) #define S3C2440_DSC1_SCKE_10mA (0<<24) |