[PATCH] x86-64 typo fixes

(Steven Cole)

5 files changed, 5 insertions, 5 deletions

diff --git a/include/asm-x86_64/byteorder.h b/include/asm-x86_64/byteorder.h
index daef6afb4f25..fd6ae95b4ffd 100644
--- a/include/asm-x86_64/byteorder.h
+++ b/include/asm-x86_64/byteorder.h
@@ -17,7 +17,7 @@ static __inline__ __const__ __u32 ___arch__swab32(__u32 x)
 	return x;
 }
 
-/* Do not define swab16.  Gcc is smart enought to recognize "C" version and
+/* Do not define swab16.  Gcc is smart enough to recognize "C" version and
    convert it into rotation or exhange.  */
 
 #define __arch__swab32(x) ___arch__swab32(x)
diff --git a/include/asm-x86_64/fixmap.h b/include/asm-x86_64/fixmap.h
index fe37141fada3..1133a85d40ed 100644
--- a/include/asm-x86_64/fixmap.h
+++ b/include/asm-x86_64/fixmap.h
@@ -66,7 +66,7 @@ extern void __this_fixmap_does_not_exist(void);
 
 /*
  * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
+ * directly without translation, we catch the bug with a NULL-deference
  * kernel oops. Illegal ranges of incoming indices are caught too.
  */
 extern inline unsigned long fix_to_virt(const unsigned int idx)
diff --git a/include/asm-x86_64/mmzone.h b/include/asm-x86_64/mmzone.h
index 9d5b9772f81c..9db87d94b771 100644
--- a/include/asm-x86_64/mmzone.h
+++ b/include/asm-x86_64/mmzone.h
@@ -1,6 +1,6 @@
 /* K8 NUMA support */
 /* Copyright 2002,2003 by Andi Kleen, SuSE Labs */
-/* 2.5 Version losely based on the NUMAQ Code by Pat Gaughen. */
+/* 2.5 Version loosely based on the NUMAQ Code by Pat Gaughen. */
 #ifndef _ASM_X86_64_MMZONE_H
 #define _ASM_X86_64_MMZONE_H 1
 
diff --git a/include/asm-x86_64/rwsem.h b/include/asm-x86_64/rwsem.h
index fdada1f26b74..c002175b6e82 100644
--- a/include/asm-x86_64/rwsem.h
+++ b/include/asm-x86_64/rwsem.h
@@ -26,7 +26,7 @@
  * This should be totally fair - if anything is waiting, a process that wants a
  * lock will go to the back of the queue. When the currently active lock is
  * released, if there's a writer at the front of the queue, then that and only
- * that will be woken up; if there's a bunch of consequtive readers at the
+ * that will be woken up; if there's a bunch of consecutive readers at the
  * front, then they'll all be woken up, but no other readers will be.
  */
 
diff --git a/include/asm-x86_64/system.h b/include/asm-x86_64/system.h
index 3d3846fc9e04..a392e47b5fa7 100644
--- a/include/asm-x86_64/system.h
+++ b/include/asm-x86_64/system.h
@@ -40,7 +40,7 @@ struct save_context_frame {
 /* It would be more efficient to let the compiler clobber most of these registers.
    Clobbering all is not possible because that lets reload freak out. Even just 
    clobbering six generates wrong code with gcc 3.1 for me so do it this way for now.
-   rbp needs to be always explicitely saved because gcc cannot clobber the
+   rbp needs to be always explicitly saved because gcc cannot clobber the
    frame pointer and the scheduler is compiled with frame pointers. -AK */
 #define SAVE_CONTEXT \
 	__PUSH(rsi) __PUSH(rdi) \