diff options
| author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-02-20 01:33:47 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-02-20 01:33:47 -0800 |
| commit | 6dc30fc274e54ce93478e2a9ae12c10f36216f27 (patch) | |
| tree | 973e183d24bd830798291be2bea3f1284264f8aa /include | |
| parent | 05de55a47c534d4aefd2c6f381d1e562fec039eb (diff) | |
| parent | 1d50e5e7a6e0325b1a652c4be296a71dc54a6e96 (diff) | |
Merge ppc970.osdl.org:/home/torvalds/v2.5/mips
into ppc970.osdl.org:/home/torvalds/v2.5/linux
Diffstat (limited to 'include')
182 files changed, 5073 insertions, 3790 deletions
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h index ec5cb629bf97..8e816364aec1 100644 --- a/include/asm-mips/addrspace.h +++ b/include/asm-mips/addrspace.h @@ -11,6 +11,7 @@ #define _ASM_ADDRSPACE_H #include <linux/config.h> +#include <spaces.h> /* * Configure language @@ -46,8 +47,6 @@ #define KSEG2 0xc0000000 #define KSEG3 0xe0000000 -//#define K0BASE KSEG0 - /* * Returns the kernel segment base of a given address */ @@ -148,25 +147,23 @@ #define KUBASE 0 #define KUSIZE_32 0x0000000080000000 /* KUSIZE for a 32 bit proc */ -//#define K0BASE 0xa800000000000000 -#define K0BASE_EXL_WR K0BASE /* exclusive on write */ +#define K0BASE_EXL_WR 0xa800000000000000 /* exclusive on write */ #define K0BASE_NONCOH 0x9800000000000000 /* noncoherent */ #define K0BASE_EXL 0xa000000000000000 /* exclusive */ -#ifdef CONFIG_SGI_IP27 -#define K1BASE 0x9600000000000000 /* uncached attr 3, - uncac */ -#else -#define K1BASE 0x9000000000000000 -#endif -#define K2BASE 0xc000000000000000 +#ifndef CONFIG_CPU_R8000 + +/* + * The R8000 doesn't have the 32-bit compat spaces so we don't define them + * in order to catch bugs in the source code. + */ -#if !defined (CONFIG_CPU_R8000) #define COMPAT_K1BASE32 0xffffffffa0000000 #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ + #endif #define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) -#define PHYS_TO_K0(x) (_ACAST64_ (x) | K0BASE) +#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) #endif /* _ASM_ADDRSPACE_H */ diff --git a/include/asm-mips/arc/types.h b/include/asm-mips/arc/types.h index 79ca5d9da1f4..bbb725c366fb 100644 --- a/include/asm-mips/arc/types.h +++ b/include/asm-mips/arc/types.h @@ -69,4 +69,19 @@ typedef USHORT *PUSHORT; typedef ULONG *PULONG; typedef VOID *PVOID; +/* + * Return type of ArcGetDisplayStatus() + */ +typedef struct { + USHORT CursorXPosition; + USHORT CursorYPosition; + USHORT CursorMaxXPosition; + USHORT CursorMaxYPosition; + USHORT ForegroundColor; + USHORT BackgroundColor; + UCHAR HighIntensity; + UCHAR Underscored; + UCHAR ReverseVideo; +} DISPLAY_STATUS; + #endif /* _ASM_ARC_TYPES_H */ diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h index e2f08891cf11..d93e636aed77 100644 --- a/include/asm-mips/asm.h +++ b/include/asm-mips/asm.h @@ -6,6 +6,7 @@ * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle * Copyright (C) 1999 by Silicon Graphics, Inc. * Copyright (C) 2001 MIPS Technologies, Inc. + * Copyright (C) 2002 Maciej W. Rozycki * * Some useful macros for MIPS assembler code * @@ -13,8 +14,8 @@ * away by gas in -O mode. These nops are however required to fill delay * slots in noreorder mode. */ -#ifndef _ASM_ASM_H -#define _ASM_ASM_H +#ifndef __ASM_ASM_H +#define __ASM_ASM_H #include <linux/config.h> #include <asm/sgidefs.h> @@ -204,13 +205,11 @@ symbol = value /* * Stack alignment */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) +#if (_MIPS_SIM == _MIPS_SIM_ABI32) #define ALSZ 7 #define ALMASK ~7 #endif -#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64) +#if (_MIPS_SIM == _MIPS_SIM_ABIN32) || (_MIPS_SIM == _MIPS_SIM_ABI64) #define ALSZ 15 #define ALMASK ~15 #endif @@ -232,15 +231,13 @@ symbol = value * Use the following macros in assemblercode to load/store registers, * pointers etc. */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) +#if (_MIPS_SIM == _MIPS_SIM_ABI32) #define REG_S sw #define REG_L lw #define REG_SUBU subu #define REG_ADDU addu #endif -#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64) +#if (_MIPS_SIM == _MIPS_SIM_ABIN32) || (_MIPS_SIM == _MIPS_SIM_ABI64) #define REG_S sd #define REG_L ld #define REG_SUBU dsubu @@ -385,17 +382,15 @@ symbol = value /* * Some cp0 registers were extended to 64bit for MIPS III. */ -#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS32) +#if (_MIPS_SIM == _MIPS_SIM_ABI32) #define MFC0 mfc0 #define MTC0 mtc0 #endif -#if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \ - (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64) +#if (_MIPS_SIM == _MIPS_SIM_ABIN32) || (_MIPS_SIM == _MIPS_SIM_ABI64) #define MFC0 dmfc0 #define MTC0 dmtc0 #endif #define SSNOP sll zero,zero,1 -#endif /* _ASM_ASM_H */ +#endif /* __ASM_ASM_H */ diff --git a/include/asm-mips/asmmacro-32.h b/include/asm-mips/asmmacro-32.h index 98b46645ea21..1d927d07cf14 100644 --- a/include/asm-mips/asmmacro-32.h +++ b/include/asm-mips/asmmacro-32.h @@ -7,7 +7,6 @@ #ifndef _ASM_ASMMACRO_32_H #define _ASM_ASMMACRO_32_H -#include <linux/config.h> #include <asm/offset.h> #include <asm/regdef.h> #include <asm/fpregdef.h> diff --git a/include/asm-mips/asmmacro-64.h b/include/asm-mips/asmmacro-64.h index abc38322045d..10b71cc877bc 100644 --- a/include/asm-mips/asmmacro-64.h +++ b/include/asm-mips/asmmacro-64.h @@ -8,7 +8,6 @@ #ifndef _ASM_ASMMACRO_64_H #define _ASM_ASMMACRO_64_H -#include <linux/config.h> #include <asm/offset.h> #include <asm/regdef.h> #include <asm/fpregdef.h> diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index 69d676ddb1ab..1262c6eafb95 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h @@ -11,19 +11,23 @@ * * Copyright (C) 1996, 97, 99, 2000, 03 by Ralf Baechle */ -#ifndef _ASM_ATOMIC_H -#define _ASM_ATOMIC_H +/* + * As workaround for the ATOMIC_DEC_AND_LOCK / atomic_dec_and_lock mess in + * <linux/spinlock.h> we have to include <linux/spinlock.h> outside the + * main big wrapper ... + */ #include <linux/config.h> +#include <linux/spinlock.h> + +#ifndef _ASM_ATOMIC_H +#define _ASM_ATOMIC_H -#include <asm/system.h> +extern spinlock_t atomic_lock; typedef struct { volatile int counter; } atomic_t; -typedef struct { volatile __s64 counter; } atomic64_t; -#ifdef __KERNEL__ #define ATOMIC_INIT(i) { (i) } -#define ATOMIC64_INIT(i) { (i) } /* * atomic_read - read atomic variable @@ -34,13 +38,6 @@ typedef struct { volatile __s64 counter; } atomic64_t; #define atomic_read(v) ((v)->counter) /* - * atomic64_read - read atomic variable - * @v: pointer of type atomic64_t - * - */ -#define atomic64_read(v) ((v)->counter) - -/* * atomic_set - set atomic variable * @v: pointer of type atomic_t * @i: required value @@ -49,84 +46,7 @@ typedef struct { volatile __s64 counter; } atomic64_t; */ #define atomic_set(v,i) ((v)->counter = (i)) -/* - * atomic64_set - set atomic variable - * @v: pointer of type atomic64_t - * @i: required value - */ -#define atomic64_set(v,i) ((v)->counter = (i)) - -#ifndef CONFIG_CPU_HAS_LLSC - -/* - * The MIPS I implementation is only atomic with respect to - * interrupts. R3000 based multiprocessor machines are rare anyway ... - * - * atomic_add - add integer to atomic variable - * @i: integer value to add - * @v: pointer of type atomic_t - * - * Atomically adds @i to @v. - */ -static __inline__ void atomic_add(int i, atomic_t * v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter += i; - local_irq_restore(flags); -} - -/* - * atomic_sub - subtract the atomic variable - * @i: integer value to subtract - * @v: pointer of type atomic_t - * - * Atomically subtracts @i from @v. - */ -static __inline__ void atomic_sub(int i, atomic_t * v) -{ - unsigned long flags; - - local_irq_save(flags); - v->counter -= i; - local_irq_restore(flags); -} - -static __inline__ int atomic_add_return(int i, atomic_t * v) -{ - unsigned long flags; - int temp; - - local_irq_save(flags); - temp = v->counter; - temp += i; - v->counter = temp; - local_irq_restore(flags); - - return temp; -} - -static __inline__ int atomic_sub_return(int i, atomic_t * v) -{ - unsigned long flags; - int temp; - - local_irq_save(flags); - temp = v->counter; - temp -= i; - v->counter = temp; - local_irq_restore(flags); - - return temp; -} - -#else - -/* - * ... while for MIPS II and better we can use ll/sc instruction. This - * implementation is SMP safe ... - */ +#ifdef CONFIG_CPU_HAS_LLSC /* * atomic_add - add integer to atomic variable @@ -160,12 +80,10 @@ static __inline__ void atomic_sub(int i, atomic_t * v) unsigned long temp; __asm__ __volatile__( - " .set noreorder # atomic_sub \n" - "1: ll %0, %1 \n" + "1: ll %0, %1 # atomic_sub \n" " subu %0, %2 \n" " sc %0, %1 \n" " beqz %0, 1b \n" - " .set reorder \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } @@ -178,14 +96,12 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) unsigned long temp, result; __asm__ __volatile__( - " .set noreorder # atomic_add_return \n" - "1: ll %1, %2 \n" + "1: ll %1, %2 # atomic_add_return \n" " addu %0, %1, %3 \n" " sc %0, %2 \n" " beqz %0, 1b \n" " addu %0, %1, %3 \n" " sync \n" - " .set reorder \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -198,93 +114,168 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) unsigned long temp, result; __asm__ __volatile__( - " .set noreorder # atomic_sub_return \n" - "1: ll %1, %2 \n" + "1: ll %1, %2 # atomic_sub_return \n" " subu %0, %1, %3 \n" " sc %0, %2 \n" " beqz %0, 1b \n" " subu %0, %1, %3 \n" " sync \n" - " .set reorder \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); return result; } -#endif -#ifndef CONFIG_CPU_HAS_LLDSCD +#else /* - * This implementation is only atomic with respect to interrupts. It can't - * be used on SMP + * The MIPS I implementation is only atomic with respect to + * interrupts. R3000 based multiprocessor machines are rare anyway ... * - * atomic64_add - add integer to atomic variable + * atomic_add - add integer to atomic variable * @i: integer value to add - * @v: pointer of type atomic64_t + * @v: pointer of type atomic_t * * Atomically adds @i to @v. */ -static __inline__ void atomic64_add(int i, atomic64_t * v) +static __inline__ void atomic_add(int i, atomic_t * v) { unsigned long flags; - local_irq_save(flags); + spin_lock_irqsave(&atomic_lock, flags); v->counter += i; - local_irq_restore(flags); + spin_unlock_irqrestore(&atomic_lock, flags); } /* - * atomic64_sub - subtract the atomic variable + * atomic_sub - subtract the atomic variable * @i: integer value to subtract - * @v: pointer of type atomic64_t + * @v: pointer of type atomic_t * * Atomically subtracts @i from @v. */ -static __inline__ void atomic64_sub(int i, atomic64_t * v) +static __inline__ void atomic_sub(int i, atomic_t * v) { unsigned long flags; - local_irq_save(flags); + spin_lock_irqsave(&atomic_lock, flags); v->counter -= i; - local_irq_restore(flags); + spin_unlock_irqrestore(&atomic_lock, flags); } -static __inline__ int atomic64_add_return(int i, atomic64_t * v) +static __inline__ int atomic_add_return(int i, atomic_t * v) { unsigned long flags; int temp; - local_irq_save(flags); + spin_lock_irqsave(&atomic_lock, flags); temp = v->counter; temp += i; v->counter = temp; - local_irq_restore(flags); + spin_unlock_irqrestore(&atomic_lock, flags); return temp; } -static __inline__ int atomic64_sub_return(int i, atomic64_t * v) +static __inline__ int atomic_sub_return(int i, atomic_t * v) { unsigned long flags; int temp; - local_irq_save(flags); + spin_lock_irqsave(&atomic_lock, flags); temp = v->counter; temp -= i; v->counter = temp; - local_irq_restore(flags); + spin_unlock_irqrestore(&atomic_lock, flags); return temp; } -#else +#endif /* CONFIG_CPU_HAS_LLSC */ + +#define atomic_dec_return(v) atomic_sub_return(1,(v)) +#define atomic_inc_return(v) atomic_add_return(1,(v)) + +/* + * atomic_sub_and_test - subtract value from variable and test result + * @i: integer value to subtract + * @v: pointer of type atomic_t + * + * Atomically subtracts @i from @v and returns + * true if the result is zero, or false for all + * other cases. + */ +#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) + +/* + * atomic_inc_and_test - increment and test + * @v: pointer of type atomic_t + * + * Atomically increments @v by 1 + * and returns true if the result is zero, or false for all + * other cases. + */ +#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0) + +/* + * atomic_dec_and_test - decrement by 1 and test + * @v: pointer of type atomic_t + * + * Atomically decrements @v by 1 and + * returns true if the result is 0, or false for all other + * cases. + */ +#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) /* - * ... while for MIPS III and better we can use ll/sc instruction. This - * implementation is SMP safe ... + * atomic_inc - increment atomic variable + * @v: pointer of type atomic_t + * + * Atomically increments @v by 1. */ +#define atomic_inc(v) atomic_add(1,(v)) + +/* + * atomic_dec - decrement and test + * @v: pointer of type atomic_t + * + * Atomically decrements @v by 1. + */ +#define atomic_dec(v) atomic_sub(1,(v)) + +/* + * atomic_add_negative - add and test if negative + * @v: pointer of type atomic_t + * @i: integer value to add + * + * Atomically adds @i to @v and returns true + * if the result is negative, or false when + * result is greater than or equal to zero. + */ +#define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0) + +#ifdef CONFIG_MIPS64 + +typedef struct { volatile __s64 counter; } atomic64_t; + +#define ATOMIC64_INIT(i) { (i) } + +/* + * atomic64_read - read atomic variable + * @v: pointer of type atomic64_t + * + */ +#define atomic64_read(v) ((v)->counter) + +/* + * atomic64_set - set atomic variable + * @v: pointer of type atomic64_t + * @i: required value + */ +#define atomic64_set(v,i) ((v)->counter = (i)) + +#ifdef CONFIG_CPU_HAS_LLDSCD /* * atomic64_add - add integer to atomic variable @@ -298,9 +289,9 @@ static __inline__ void atomic64_add(int i, atomic64_t * v) unsigned long temp; __asm__ __volatile__( - "1: ll %0, %1 # atomic64_add \n" + "1: lld %0, %1 # atomic64_add \n" " addu %0, %2 \n" - " sc %0, %1 \n" + " scd %0, %1 \n" " beqz %0, 1b \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); @@ -318,12 +309,10 @@ static __inline__ void atomic64_sub(int i, atomic64_t * v) unsigned long temp; __asm__ __volatile__( - " .set noreorder # atomic64_sub \n" - "1: ll %0, %1 \n" + "1: lld %0, %1 # atomic64_sub \n" " subu %0, %2 \n" - " sc %0, %1 \n" + " scd %0, %1 \n" " beqz %0, 1b \n" - " .set reorder \n" : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } @@ -336,14 +325,12 @@ static __inline__ int atomic64_add_return(int i, atomic64_t * v) unsigned long temp, result; __asm__ __volatile__( - " .set noreorder # atomic64_add_return \n" - "1: ll %1, %2 \n" + "1: lld %1, %2 # atomic64_add_return \n" " addu %0, %1, %3 \n" - " sc %0, %2 \n" + " scd %0, %2 \n" " beqz %0, 1b \n" " addu %0, %1, %3 \n" " sync \n" - " .set reorder \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); @@ -356,37 +343,88 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) unsigned long temp, result; __asm__ __volatile__( - " .set noreorder # atomic64_sub_return \n" - "1: ll %1, %2 \n" + "1: lld %1, %2 # atomic64_sub_return \n" " subu %0, %1, %3 \n" - " sc %0, %2 \n" + " scd %0, %2 \n" " beqz %0, 1b \n" " subu %0, %1, %3 \n" " sync \n" - " .set reorder \n" : "=&r" (result), "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter) : "memory"); return result; } -#endif -#define atomic_dec_return(v) atomic_sub_return(1,(v)) -#define atomic64_dec_return(v) atomic64_sub_return(1,(v)) -#define atomic_inc_return(v) atomic_add_return(1,(v)) -#define atomic64_inc_return(v) atomic64_add_return(1,(v)) +#else /* - * atomic_sub_and_test - subtract value from variable and test result + * This implementation is only atomic with respect to interrupts. It can't + * be used on SMP + * + * atomic64_add - add integer to atomic variable + * @i: integer value to add + * @v: pointer of type atomic64_t + * + * Atomically adds @i to @v. + */ +static __inline__ void atomic64_add(int i, atomic64_t * v) +{ + unsigned long flags; + + spin_lock_irqsave(&atomic_lock, flags); + v->counter += i; + spin_unlock_irqrestore(&atomic_lock, flags); +} + +/* + * atomic64_sub - subtract the atomic variable * @i: integer value to subtract - * @v: pointer of type atomic_t + * @v: pointer of type atomic64_t * - * Atomically subtracts @i from @v and returns - * true if the result is zero, or false for all - * other cases. + * Atomically subtracts @i from @v. */ -#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) +static __inline__ void atomic64_sub(int i, atomic64_t * v) +{ + unsigned long flags; + + spin_lock_irqsave(&atomic_lock, flags); + v->counter -= i; + spin_unlock_irqrestore(&atomic_lock, flags); +} + +static __inline__ int atomic64_add_return(int i, atomic64_t * v) +{ + unsigned long flags; + int temp; + + spin_lock_irqsave(&atomic_lock, flags); + temp = v->counter; + temp += i; + v->counter = temp; + spin_unlock_irqrestore(&atomic_lock, flags); + + return temp; +} + +static __inline__ int atomic64_sub_return(int i, atomic64_t * v) +{ + unsigned long flags; + int temp; + + spin_lock_irqsave(&atomic_lock, flags); + temp = v->counter; + temp -= i; + v->counter = temp; + spin_unlock_irqrestore(&atomic_lock, flags); + + return temp; +} + +#endif /* CONFIG_CPU_HAS_LLDSCD */ + +#define atomic64_dec_return(v) atomic64_sub_return(1,(v)) +#define atomic64_inc_return(v) atomic64_add_return(1,(v)) /* * atomic64_sub_and_test - subtract value from variable and test result @@ -400,16 +438,6 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) #define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0) /* - * atomic_inc_and_test - increment and test - * @v: pointer of type atomic_t - * - * Atomically increments @v by 1 - * and returns true if the result is zero, or false for all - * other cases. - */ -#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0) - -/* * atomic64_inc_and_test - increment and test * @v: pointer of type atomic64_t * @@ -420,16 +448,6 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) #define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0) /* - * atomic_dec_and_test - decrement by 1 and test - * @v: pointer of type atomic_t - * - * Atomically decrements @v by 1 and - * returns true if the result is 0, or false for all other - * cases. - */ -#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) - -/* * atomic64_dec_and_test - decrement by 1 and test * @v: pointer of type atomic64_t * @@ -440,14 +458,6 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) #define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0) /* - * atomic_inc - increment atomic variable - * @v: pointer of type atomic_t - * - * Atomically increments @v by 1. - */ -#define atomic_inc(v) atomic_add(1,(v)) - -/* * atomic64_inc - increment atomic variable * @v: pointer of type atomic64_t * @@ -456,14 +466,6 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) #define atomic64_inc(v) atomic64_add(1,(v)) /* - * atomic_dec - decrement and test - * @v: pointer of type atomic_t - * - * Atomically decrements @v by 1. - */ -#define atomic_dec(v) atomic_sub(1,(v)) - -/* * atomic64_dec - decrement and test * @v: pointer of type atomic64_t * @@ -472,17 +474,6 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) #define atomic64_dec(v) atomic64_sub(1,(v)) /* - * atomic_add_negative - add and test if negative - * @v: pointer of type atomic_t - * @i: integer value to add - * - * Atomically adds @i to @v and returns true - * if the result is negative, or false when - * result is greater than or equal to zero. - */ -#define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0) - -/* * atomic64_add_negative - add and test if negative * @v: pointer of type atomic64_t * @i: integer value to add @@ -493,12 +484,15 @@ static __inline__ int atomic64_sub_return(int i, atomic64_t * v) */ #define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0) -/* Atomic operations are already serializing */ +#endif /* CONFIG_MIPS64 */ + +/* + * atomic*_return operations are serializing but not the non-*_return + * versions. + */ #define smp_mb__before_atomic_dec() smp_mb() #define smp_mb__after_atomic_dec() smp_mb() #define smp_mb__before_atomic_inc() smp_mb() #define smp_mb__after_atomic_inc() smp_mb() -#endif /* defined(__KERNEL__) */ - #endif /* _ASM_ATOMIC_H */ diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 5befbf3df737..8a3d1a32505b 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -19,11 +19,13 @@ #define SZLONG_MASK 31UL #define __LL "ll" #define __SC "sc" +#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) #elif (_MIPS_SZLONG == 64) #define SZLONG_LOG 6 #define SZLONG_MASK 63UL #define __LL "lld" #define __SC "scd" +#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) #endif #ifdef __KERNEL__ @@ -627,7 +629,7 @@ static inline int __test_and_change_bit(unsigned long nr, */ static inline int test_bit(unsigned long nr, const volatile unsigned long *addr) { - return 1UL & (((const volatile unsigned long *) addr)[nr >> SZLONG_LOG] >> (nr & SZLONG_MASK)); + return 1UL & (addr[nr >> SZLONG_LOG] >> (nr & SZLONG_MASK)); } /* @@ -683,10 +685,10 @@ static inline unsigned long __ffs(unsigned long word) * @offset: The bitnumber to start searching at * @size: The maximum size to search */ -static inline unsigned long find_next_zero_bit(unsigned long *addr, +static inline unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size, unsigned long offset) { - unsigned long *p = ((unsigned long *) addr) + (offset >> SZLONG_LOG); + const unsigned long *p = addr + (offset >> SZLONG_LOG); unsigned long result = offset & ~SZLONG_MASK; unsigned long tmp; @@ -731,10 +733,10 @@ found_middle: * @offset: The bitnumber to start searching at * @size: The maximum size to search */ -static inline unsigned long find_next_bit(unsigned long *addr, +static inline unsigned long find_next_bit(const unsigned long *addr, unsigned long size, unsigned long offset) { - unsigned long *p = addr + (offset >> SZLONG_LOG); + const unsigned long *p = addr + (offset >> SZLONG_LOG); unsigned long result = offset & ~SZLONG_MASK; unsigned long tmp; @@ -789,7 +791,7 @@ found_middle: * unlikely to be set. It's guaranteed that at least one of the 140 * bits is cleared. */ -static inline int sched_find_first_bit(unsigned long *b) +static inline int sched_find_first_bit(const unsigned long *b) { #ifdef CONFIG_MIPS32 if (unlikely(b[0])) @@ -829,6 +831,7 @@ static inline int sched_find_first_bit(unsigned long *b) * The Hamming Weight of a number is the total number of bits set in it. */ +#define hweight64(x) generic_hweight64(x) #define hweight32(x) generic_hweight32(x) #define hweight16(x) generic_hweight16(x) #define hweight8(x) generic_hweight8(x) @@ -870,59 +873,44 @@ static inline int test_le_bit(unsigned long nr, const unsigned long * addr) return ((mask & *ADDR) != 0); } -static inline unsigned long ext2_ffz(unsigned int word) -{ - int b = 0, s; - - word = ~word; - s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s; - s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s; - s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s; - s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s; - s = 1; if (word << 31 != 0) s = 0; b += s; - - return b; -} - static inline unsigned long find_next_zero_le_bit(unsigned long *addr, unsigned long size, unsigned long offset) { - unsigned int *p = ((unsigned int *) addr) + (offset >> SZLONG_LOG); - unsigned int result = offset & ~SZLONG_MASK; - unsigned int tmp; + unsigned long *p = ((unsigned long *) addr) + (offset >> SZLONG_LOG); + unsigned long result = offset & ~SZLONG_MASK; + unsigned long tmp; if (offset >= size) return size; - size -= result; offset &= SZLONG_MASK; if (offset) { - tmp = cpu_to_le32p(p++); - tmp |= ~0U >> (32-offset); /* bug or feature ? */ - if (size < 32) + tmp = cpu_to_lelongp(p++); + tmp |= ~0UL >> (_MIPS_SZLONG-offset); /* bug or feature ? */ + if (size < _MIPS_SZLONG) goto found_first; - if (tmp != ~0U) + if (~tmp) goto found_middle; - size -= 32; - result += 32; + size -= _MIPS_SZLONG; + result += _MIPS_SZLONG; } - while (size >= 32) { - if ((tmp = cpu_to_le32p(p++)) != ~0U) + while (size & ~SZLONG_MASK) { + if (~(tmp = cpu_to_lelongp(p++))) goto found_middle; - result += 32; - size -= 32; + result += _MIPS_SZLONG; + size -= _MIPS_SZLONG; } if (!size) return result; + tmp = cpu_to_lelongp(p); - tmp = cpu_to_le32p(p); found_first: - tmp |= ~0 << size; - if (tmp == ~0U) /* Are any bits zero? */ + tmp |= ~0UL << size; + if (tmp == ~0UL) /* Are any bits zero? */ return result + size; /* Nope. */ found_middle: - return result + ext2_ffz(tmp); + return result + ffz(tmp); } #define find_first_zero_le_bit(addr, size) \ diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 16ebdd7d259c..3519b50ac065 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -3,8 +3,10 @@ * License. See the file COPYING in the main directory of this archive * for more details. * - * Copyright (C) 1995, 1996 by Ralf Baechle, Andreas Busse, - * Stoned Elipot and Paul M. Antoine. + * Copyright (C) 1995, 1996, 2003 by Ralf Baechle + * Copyright (C) 1995, 1996 Andreas Busse + * Copyright (C) 1995, 1996 Stoned Elipot + * Copyright (C) 1995, 1996 Paul M. Antoine. */ #ifndef _ASM_BOOTINFO_H #define _ASM_BOOTINFO_H @@ -12,180 +14,199 @@ #include <linux/types.h> /* - * Values for machgroup + * The MACH_GROUP_ IDs are the equivalent to PCI vendor IDs; the remaining + * MACH_ values equivalent to product IDs. As such the numbers do not + * necessarily reflect technical relations or similarities between systems. */ -#define MACH_GROUP_UNKNOWN 0 /* whatever... */ -#define MACH_GROUP_JAZZ 1 /* Jazz */ -#define MACH_GROUP_DEC 2 /* Digital Equipment */ -#define MACH_GROUP_ARC 3 /* Wreckstation Tyne, rPC44, possibly other */ -#define MACH_GROUP_SNI_RM 4 /* Siemens Nixdorf RM series */ -#define MACH_GROUP_ACN 5 -#define MACH_GROUP_SGI 6 /* Silicon Graphics */ -#define MACH_GROUP_COBALT 7 /* Cobalt servers */ -#define MACH_GROUP_NEC_DDB 8 /* NEC DDB */ -#define MACH_GROUP_BAGET 9 /* Baget */ -#define MACH_GROUP_COSINE 10 /* CoSine Orion */ -#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */ -#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ -#define MACH_GROUP_ITE 13 /* ITE Semi Eval Boards */ -#define MACH_GROUP_PHILIPS 14 -#define MACH_GROUP_GLOBESPAN 15 /* Globespan PVR Referrence Board */ -#define MACH_GROUP_SIBYTE 16 /* Sibyte Eval Boards */ -#define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */ -#define MACH_GROUP_ALCHEMY 18 /* Alchemy Semi Eval Boards */ -#define MACH_GROUP_NEC_VR41XX 19 /* NEC Vr41xx based boards/gadgets */ -#define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */ -#define MACH_GROUP_LASAT 21 /* - * Valid machtype values for group unknown (low order halfword of mips_machtype) + * Valid machtype values for group unknown */ -#define MACH_UNKNOWN 0 /* whatever... */ +#define MACH_GROUP_UNKNOWN 0 /* whatever... */ +#define MACH_UNKNOWN 0 /* whatever... */ /* * Valid machtype values for group JAZZ */ -#define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */ -#define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */ -#define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */ +#define MACH_GROUP_JAZZ 1 /* Jazz */ +#define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */ +#define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */ +#define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */ /* * Valid machtype for group DEC */ -#define MACH_DSUNKNOWN 0 -#define MACH_DS23100 1 /* DECstation 2100 or 3100 */ -#define MACH_DS5100 2 /* DECsystem 5100 */ -#define MACH_DS5000_200 3 /* DECstation 5000/200 */ -#define MACH_DS5000_1XX 4 /* DECstation 5000/120, 125, 133, 150 */ -#define MACH_DS5000_XX 5 /* DECstation 5000/20, 25, 33, 50 */ -#define MACH_DS5000_2X0 6 /* DECstation 5000/240, 260 */ -#define MACH_DS5400 7 /* DECsystem 5400 */ -#define MACH_DS5500 8 /* DECsystem 5500 */ -#define MACH_DS5800 9 /* DECsystem 5800 */ -#define MACH_DS5900 10 /* DECsystem 5900 */ +#define MACH_GROUP_DEC 2 /* Digital Equipment */ +#define MACH_DSUNKNOWN 0 +#define MACH_DS23100 1 /* DECstation 2100 or 3100 */ +#define MACH_DS5100 2 /* DECsystem 5100 */ +#define MACH_DS5000_200 3 /* DECstation 5000/200 */ +#define MACH_DS5000_1XX 4 /* DECstation 5000/120, 125, 133, 150 */ +#define MACH_DS5000_XX 5 /* DECstation 5000/20, 25, 33, 50 */ +#define MACH_DS5000_2X0 6 /* DECstation 5000/240, 260 */ +#define MACH_DS5400 7 /* DECsystem 5400 */ +#define MACH_DS5500 8 /* DECsystem 5500 */ +#define MACH_DS5800 9 /* DECsystem 5800 */ +#define MACH_DS5900 10 /* DECsystem 5900 */ /* * Valid machtype for group ARC */ +#define MACH_GROUP_ARC 3 /* Deskstation */ #define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */ #define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */ /* * Valid machtype for group SNI_RM */ -#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ +#define MACH_GROUP_SNI_RM 4 /* Siemens Nixdorf RM series */ +#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */ /* * Valid machtype for group ACN */ -#define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */ +#define MACH_GROUP_ACN 5 +#define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */ /* * Valid machtype for group SGI */ -#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ -#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ -#define MACH_SGI_IP28 2 /* Indigo2 Impact */ -#define MACH_SGI_IP32 3 /* O2 */ +#define MACH_GROUP_SGI 6 /* Silicon Graphics */ +#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */ +#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */ +#define MACH_SGI_IP28 2 /* Indigo2 Impact */ +#define MACH_SGI_IP32 3 /* O2 */ /* * Valid machtype for group COBALT */ -#define MACH_COBALT_27 0 /* Proto "27" hardware */ +#define MACH_GROUP_COBALT 7 /* Cobalt servers */ +#define MACH_COBALT_27 0 /* Proto "27" hardware */ /* * Valid machtype for group NEC DDB */ -#define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */ -#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */ -#define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */ -#define MACH_NEC_ROCKHOPPER 3 /* Rockhopper base board */ -#define MACH_NEC_ROCKHOPPERII 4 /* Rockhopper II base board */ +#define MACH_GROUP_NEC_DDB 8 /* NEC DDB */ +#define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */ +#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */ +#define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */ +#define MACH_NEC_ROCKHOPPER 3 /* Rockhopper base board */ +#define MACH_NEC_ROCKHOPPERII 4 /* Rockhopper II base board */ /* * Valid machtype for group BAGET */ -#define MACH_BAGET201 0 /* BT23-201 */ -#define MACH_BAGET202 1 /* BT23-202 */ +#define MACH_GROUP_BAGET 9 /* Baget */ +#define MACH_BAGET201 0 /* BT23-201 */ +#define MACH_BAGET202 1 /* BT23-202 */ /* * Cosine boards. */ -#define MACH_COSINE_ORION 0 +#define MACH_GROUP_COSINE 10 /* CoSine Orion */ +#define MACH_COSINE_ORION 0 /* * Valid machtype for group GALILEO */ -#define MACH_EV96100 0 /* EV96100 */ -#define MACH_EV64120A 1 /* EV64120A */ +#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */ +#define MACH_EV96100 0 /* EV96100 */ +#define MACH_EV64120A 1 /* EV64120A */ /* * Valid machtype for group MOMENCO */ -#define MACH_MOMENCO_OCELOT 0 -#define MACH_MOMENCO_OCELOT_G 1 -#define MACH_MOMENCO_OCELOT_C 2 +#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */ +#define MACH_MOMENCO_OCELOT 0 +#define MACH_MOMENCO_OCELOT_G 1 +#define MACH_MOMENCO_OCELOT_C 2 +#define MACH_MOMENCO_JAGUAR_ATX 3 /* * Valid machtype for group ITE */ -#define MACH_QED_4N_S01B 0 /* ITE8172 based eval board */ +#define MACH_GROUP_ITE 13 /* ITE Semi Eval Boards */ +#define MACH_QED_4N_S01B 0 /* ITE8172 based eval board */ /* - * Valid machtype for group Globespan + * Valid machtype for group PHILIPS */ -#define MACH_IVR 0 /* IVR eval board */ +#define MACH_GROUP_PHILIPS 14 +#define MACH_PHILIPS_NINO 0 /* Nino */ +#define MACH_PHILIPS_VELO 1 /* Velo */ /* - * Valid machtype for group PHILIPS + * Valid machtype for group Globespan */ -#define MACH_PHILIPS_NINO 0 /* Nino */ -#define MACH_PHILIPS_VELO 1 /* Velo */ +#define MACH_GROUP_GLOBESPAN 15 /* Globespan */ +#define MACH_IVR 0 /* IVR eval board */ /* * Valid machtype for group SIBYTE */ -#define MACH_SWARM 0 +#define MACH_GROUP_SIBYTE 16 /* Sibyte / Broadcom */ +#define MACH_SWARM 0 /* * Valid machtypes for group Toshiba */ -#define MACH_PALLAS 0 -#define MACH_TOPAS 1 -#define MACH_JMR 2 -#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */ -#define MACH_TOSHIBA_RBTX4927 4 -#define MACH_TOSHIBA_RBTX4937 5 +#define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */ +#define MACH_PALLAS 0 +#define MACH_TOPAS 1 +#define MACH_JMR 2 +#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */ +#define MACH_TOSHIBA_RBTX4927 4 +#define MACH_TOSHIBA_RBTX4937 5 + #define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \ "RBTX4927", "RBTX4937" } /* - * Valid machtype for group LASAT + * Valid machtype for group Alchemy */ -#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ -#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ +#define MACH_GROUP_ALCHEMY 18 /* AMD Alchemy */ +#define MACH_PB1000 0 /* Au1000-based eval board */ +#define MACH_PB1100 1 /* Au1100-based eval board */ +#define MACH_PB1500 2 /* Au1500-based eval board */ +#define MACH_DB1000 3 /* Au1000-based eval board */ +#define MACH_DB1100 4 /* Au1100-based eval board */ +#define MACH_DB1500 5 /* Au1500-based eval board */ +#define MACH_XXS1500 6 /* Au1500-based eval board */ +#define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */ /* - * Valid machtype for group Alchemy + * Valid machtype for group NEC_VR41XX + * + * Various NEC-based devices. + * + * FIXME: MACH_GROUPs should be by _MANUFACTURER_ of * the device, not by + * technical properties, so no new additions to this group. */ -#define MACH_PB1000 0 /* Au1000-based eval board */ -#define MACH_PB1100 1 /* Au1100-based eval board */ -#define MACH_PB1500 2 /* Au1500-based eval board */ -#define MACH_DB1000 3 /* Au1000-based eval board */ -#define MACH_DB1100 4 /* Au1100-based eval board */ -#define MACH_DB1500 5 /* Au1500-based eval board */ +#define MACH_GROUP_NEC_VR41XX 19 +#define MACH_NEC_OSPREY 0 /* Osprey eval board */ +#define MACH_NEC_EAGLE 1 /* NEC Eagle/Hawk board */ +#define MACH_ZAO_CAPCELLA 2 /* ZAO Networks Capcella */ +#define MACH_VICTOR_MPC30X 3 /* Victor MP-C303/304 */ +#define MACH_IBM_WORKPAD 4 /* IBM WorkPad z50 */ +#define MACH_CASIO_E55 5 /* CASIO CASSIOPEIA E-10/15/55/65 */ +#define MACH_TANBAC_TB0226 6 /* TANBAC TB0226 (Mbase) */ +#define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */ + +#define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */ +#define MACH_HP_LASERJET 1 /* - * Valid machtype for group NEC_VR41XX + * Valid machtype for group LASAT + */ +#define MACH_GROUP_LASAT 21 +#define MACH_LASAT_100 1 /* Masquerade II/SP100/SP50/SP25 */ +#define MACH_LASAT_200 2 /* Masquerade PRO/SP200 */ + +/* + * Valid machtype for group TITAN */ -#define MACH_NEC_OSPREY 0 /* Osprey eval board */ -#define MACH_NEC_EAGLE 1 /* NEC Eagle/Hawk board */ -#define MACH_ZAO_CAPCELLA 2 /* ZAO Networks Capcella */ -#define MACH_VICTOR_MPC30X 3 /* Victor MP-C303/304 */ -#define MACH_IBM_WORKPAD 4 /* IBM WorkPad z50 */ -#define MACH_CASIO_E55 5 /* CASIO CASSIOPEIA E-10/15/55/65 */ -#define MACH_TANBAC_TB0226 6 /* TANBAC TB0226 (Mbase) */ -#define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */ +#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ +#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ #define CL_SIZE (256) @@ -205,7 +226,7 @@ extern unsigned long mips_machgroup; */ struct boot_mem_map { int nr_map; - struct { + struct boot_mem_map_entry { phys_t addr; /* start of memory segment */ phys_t size; /* size of memory segment */ long type; /* type of memory segment */ @@ -216,4 +237,15 @@ extern struct boot_mem_map boot_mem_map; extern void add_memory_region(phys_t start, phys_t size, long type); +extern void prom_init(void); + +/* + * Initial kernel command line, usually setup by prom_init() + */ +extern char arcs_cmdline[CL_SIZE]; + +/* + * Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware + */ +extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3; #endif /* _ASM_BOOTINFO_H */ diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h index d34c34f30282..f1f483d4fc34 100644 --- a/include/asm-mips/bug.h +++ b/include/asm-mips/bug.h @@ -5,7 +5,6 @@ #define BUG() \ do { \ - printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ __asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \ } while (0) #define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h index 4057cb45f744..fda57132db2c 100644 --- a/include/asm-mips/cache.h +++ b/include/asm-mips/cache.h @@ -11,15 +11,11 @@ #include <linux/config.h> -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_R6000) || \ - defined(CONFIG_CPU_TX39XX) -#define L1_CACHE_BYTES 16 -#define L1_CACHE_SHIFT_MAX 4 /* largest L1 which this arch supports */ -#else -#define L1_CACHE_BYTES 32 /* A guess */ -#define L1_CACHE_SHIFT_MAX 6 /* largest L1 which this arch supports */ -#endif +#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define L1_CACHE_SHIFT_MAX 6 +#define SMP_CACHE_SHIFT L1_CACHE_SHIFT #define SMP_CACHE_BYTES L1_CACHE_BYTES #endif /* _ASM_CACHE_H */ diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h index 5f432f507cb3..39b10d84d01d 100644 --- a/include/asm-mips/cacheflush.h +++ b/include/asm-mips/cacheflush.h @@ -9,8 +9,6 @@ #ifndef _ASM_CACHEFLUSH_H #define _ASM_CACHEFLUSH_H -#include <linux/config.h> - /* Keep includes the same across arches. */ #include <linux/mm.h> @@ -41,16 +39,15 @@ extern void flush_dcache_page(struct page *page); extern void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); extern void (*flush_icache_range)(unsigned long start, unsigned long end); -#define flush_icache_user_range(vma, page, addr, len) \ - flush_icache_page(vma, page) #define flush_cache_vmap(start, end) flush_cache_all() #define flush_cache_vunmap(start, end) flush_cache_all() -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ -do { memcpy(dst, src, len); \ - flush_icache_user_range(vma, page, vaddr, len); \ +#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ +do { \ + memcpy(dst, (void *) src, len); \ + flush_icache_page(vma, page); \ } while (0) -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ +#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ memcpy(dst, src, len) extern void (*flush_cache_sigtramp)(unsigned long addr); diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h index d0cb514e8c03..0db85f430619 100644 --- a/include/asm-mips/checksum.h +++ b/include/asm-mips/checksum.h @@ -89,56 +89,43 @@ static inline unsigned short int csum_fold(unsigned int sum) * By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by * Arnt Gulbrandsen. */ -static inline unsigned short ip_fast_csum(unsigned char *iph, - unsigned int ihl) +static inline unsigned short ip_fast_csum(unsigned char *iph, unsigned int ihl) { - unsigned int dummy, sum; - - /* - * This is for 32-bit processors ... but works just fine for 64-bit - * processors for now ... XXX - */ - __asm__ __volatile__( - ".set\tnoreorder\t\t\t# ip_fast_csum\n\t" - ".set\tnoat\n\t" - "lw\t%0, (%1)\n\t" - "subu\t%2, 4\n\t" - "sll\t%2, 2\n\t" - "lw\t%3, 4(%1)\n\t" - "addu\t%2, %1\n\t" - "addu\t%0, %3\n\t" - "sltu\t$1, %0, %3\n\t" - "lw\t%3, 8(%1)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %3\n\t" - "sltu\t$1, %0, %3\n\t" - "lw\t%3, 12(%1)\n\t" - "addu\t%0, $1\n\t" - "addu\t%0, %3\n\t" - "sltu\t$1, %0, %3\n\t" - "addu\t%0, $1\n" - - "1:\tlw\t%3, 16(%1)\n\t" - "addiu\t%1, 4\n\t" - "addu\t%0, %3\n\t" - "sltu\t$1, %0, %3\n\t" - "bne\t%2, %1, 1b\n\t" - " addu\t%0, $1\n" - - "2:\t.set\tat\n\t" - ".set\treorder" - : "=&r" (sum), "=&r" (iph), "=&r" (ihl), "=&r" (dummy) - : "1" (iph), "2" (ihl)); - - return csum_fold(sum); + unsigned int *word = (unsigned int *) iph; + unsigned int *stop = word + ihl; + unsigned int csum; + int carry; + + csum = word[0]; + csum += word[1]; + carry = (csum < word[1]); + csum += carry; + + csum += word[2]; + carry = (csum < word[2]); + csum += carry; + + csum += word[3]; + carry = (csum < word[3]); + csum += carry; + + word += 4; + do { + csum += *word; + carry = (csum < *word); + csum += carry; + word++; + } while (word != stop); + + return csum_fold(csum); } /* * computes the checksum of the TCP/UDP pseudo-header * returns a 16-bit checksum, already complemented */ -static inline unsigned int csum_tcpudp_nofold(unsigned int saddr, - unsigned int daddr, unsigned short len, unsigned short proto, +static inline unsigned int csum_tcpudp_nofold(unsigned long saddr, + unsigned long daddr, unsigned short len, unsigned short proto, unsigned int sum) { __asm__( @@ -168,9 +155,9 @@ static inline unsigned int csum_tcpudp_nofold(unsigned int saddr, : "=r" (sum) : "0" (daddr), "r"(saddr), #ifdef __MIPSEL__ - "r" ((ntohs(len)<<16)+proto*256), + "r" (((unsigned long)htons(len)<<16) + proto*256), #else - "r" (((proto)<<16)+len), + "r" (((unsigned long)(proto)<<16) + len), #endif "r" (sum)); diff --git a/include/asm-mips/cobalt/cobalt.h b/include/asm-mips/cobalt/cobalt.h index eb9bc7bfe340..ca1fbc0579fe 100644 --- a/include/asm-mips/cobalt/cobalt.h +++ b/include/asm-mips/cobalt/cobalt.h @@ -6,47 +6,31 @@ * for more details. * * Copyright (C) 1997 Cobalt Microserver - * Copyright (C) 1997 Ralf Baechle + * Copyright (C) 1997, 2003 Ralf Baechle * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv) - * - */ -#ifndef __ASM_MIPS_COBALT_H -#define __ASM_MIPS_COBALT_H - -/* - * COBALT interrupt enable bits */ -#define COBALT_IE_PCI (1 << 0) -#define COBALT_IE_FLOPPY (1 << 1) -#define COBALT_IE_KEYBOARD (1 << 2) -#define COBALT_IE_SERIAL1 (1 << 3) -#define COBALT_IE_SERIAL2 (1 << 4) -#define COBALT_IE_PARALLEL (1 << 5) -#define COBALT_IE_GPIO (1 << 6) -#define COBALT_IE_RTC (1 << 7) +#ifndef __ASM_COBALT_H +#define __ASM_COBALT_H /* - * PCI defines - */ -#define COBALT_IE_ETHERNET (1 << 7) -#define COBALT_IE_SCSI (1 << 7) - -/* - * COBALT Interrupt Level definitions. - * These should match the request IRQ id's. + * i8259 legacy interrupts used on Cobalt: + * + * 8 - RTC + * 9 - PCI + * 14 - IDE0 + * 15 - IDE1 + * + * CPU IRQs are 16 ... 23 */ -#define COBALT_TIMER_IRQ 0 -#define COBALT_KEYBOARD_IRQ 1 -#define COBALT_QUBE_SLOT_IRQ 9 -#define COBALT_ETH0_IRQ 4 -#define COBALT_ETH1_IRQ 13 -#define COBALT_SCC_IRQ 4 -#define COBALT_SERIAL2_IRQ 4 -#define COBALT_PARALLEL_IRQ 5 -#define COBALT_FLOPPY_IRQ 6 /* needs to be consistent with floppy driver! */ -#define COBALT_SCSI_IRQ 7 -#define COBALT_SERIAL_IRQ 7 -#define COBALT_RAQ_SCSI_IRQ 4 +#define COBALT_TIMER_IRQ 18 +#define COBALT_SCC_IRQ 19 /* pre-production has 85C30 */ +#define COBALT_RAQ_SCSI_IRQ 19 +#define COBALT_ETH0_IRQ 19 +#define COBALT_ETH1_IRQ 20 +#define COBALT_SERIAL_IRQ 21 +#define COBALT_SCSI_IRQ 21 +#define COBALT_VIA_IRQ 22 /* Chained to VIA ISA bridge */ +#define COBALT_QUBE_SLOT_IRQ 23 /* * PCI configuration space manifest constants. These are wired into @@ -78,21 +62,29 @@ #define COBALT_BRD_ID_QUBE2 0x5 #define COBALT_BRD_ID_RAQ2 0x6 - /* * Galileo chipset access macros for the Cobalt. The base address for * the GT64111 chip is 0x14000000 + * + * Most of this really should go into a separate GT64111 header file. */ -#define GT64111_BASE 0x04000000 -#define GALILEO_REG(ofs) (GT64111_BASE + (ofs)) +#define GT64111_IO_BASE 0x10000000UL +#define GT64111_BASE 0x14000000UL +#define GALILEO_REG(ofs) (KSEG0 + GT64111_BASE + (unsigned long)(ofs)) -#define GALILEO_INL(port) (inl(GALILEO_REG(port))) -#define GALILEO_OUTL(val, port) outl(val, GALILEO_REG(port)) +#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port)) +#define GALILEO_OUTL(val, port) \ +do { \ + *(volatile unsigned int *) GALILEO_REG(port) = (port); \ +} while (0) #define GALILEO_T0EXP 0x0100 #define GALILEO_ENTC0 0x01 #define GALILEO_SELTC0 0x02 +#define PCI_CFG_SET(devfn,where) \ + GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \ + (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS) -#endif /* __ASM_MIPS_COBALT_H */ +#endif /* __ASM_COBALT_H */ diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h new file mode 100644 index 000000000000..1bc8758b39cc --- /dev/null +++ b/include/asm-mips/cpu-features.h @@ -0,0 +1,125 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_CPU_FEATURES_H +#define __ASM_CPU_FEATURES_H + +#include <cpu-feature-overrides.h> + +/* + * SMP assumption: Options of CPU 0 are a superset of all processors. + * This is true for all known MIPS systems. + */ +#ifndef cpu_has_tlb +#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) +#endif +#ifndef cpu_has_4kex +#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) +#endif +#ifndef cpu_has_4ktlb +#define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB) +#endif +#ifndef cpu_has_fpu +#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU) +#endif +#ifndef cpu_has_32fpr +#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) +#endif +#ifndef cpu_has_counter +#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) +#endif +#ifndef cpu_has_watch +#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) +#endif +#ifndef cpu_has_mips16 +#define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16) +#endif +#ifndef cpu_has_divec +#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) +#endif +#ifndef cpu_has_vce +#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) +#endif +#ifndef cpu_has_cache_cdex_p +#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) +#endif +#ifndef cpu_has_cache_cdex_s +#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) +#endif +#ifndef cpu_has_prefetch +#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) +#endif +#ifndef cpu_has_mcheck +#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) +#endif +#ifndef cpu_has_ejtag +#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) +#endif +#ifndef cpu_has_llsc +#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) +#endif +#ifndef cpu_has_vtag_icache +#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) +#endif +#ifndef cpu_has_dc_aliases +#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) +#endif +#ifndef cpu_has_ic_fills_f_dc +#define cpu_has_ic_fills_f_dc (cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC) +#endif + +#ifdef CONFIG_MIPS32 +# ifndef cpu_has_nofpuex +# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) +# endif +# ifndef cpu_has_64bits +# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) +# endif +# ifndef cpu_has_64bit_zero_reg +# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) +# endif +# ifndef cpu_has_64bit_gp_regs +# define cpu_has_64bit_gp_regs 0 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 0 +# endif +#endif + +#ifdef CONFIG_MIPS64 +# ifndef cpu_has_nofpuex +# define cpu_has_nofpuex 0 +# endif +# ifndef cpu_has_64bits +# define cpu_has_64bits 1 +# endif +# ifndef cpu_has_64bit_zero_reg +# define cpu_has_64bit_zero_reg 1 +# endif +# ifndef cpu_has_64bit_gp_regs +# define cpu_has_64bit_gp_regs 1 +# endif +# ifndef cpu_has_64bit_addresses +# define cpu_has_64bit_addresses 1 +# endif +#endif + +#ifndef cpu_has_subset_pcaches +#define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) +#endif + +#ifndef cpu_dcache_line_size +#define cpu_dcache_line_size() current_cpu_data.dcache.linesz +#endif +#ifndef cpu_icache_line_size +#define cpu_icache_line_size() current_cpu_data.icache.linesz +#endif +#ifndef cpu_scache_line_size +#define cpu_scache_line_size() current_cpu_data.scache.linesz +#endif + +#endif /* __ASM_CPU_FEATURES_H */ diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index f2289ddc5432..dec060b49556 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -7,8 +7,6 @@ #ifndef _ASM_CPU_H #define _ASM_CPU_H -#include <linux/cpu.h> - /* Assigned Company values for bits 23:16 of the PRId Register (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from MTI, the PRId register is defined in this (backwards compatible) @@ -59,6 +57,7 @@ #define PRID_IMP_MAGIC 0x2500 #define PRID_IMP_RM7000 0x2700 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ +#define PRID_IMP_RM9000 0x3400 #define PRID_IMP_R5432 0x5400 #define PRID_IMP_R5500 0x5500 #define PRID_IMP_4KC 0x8000 @@ -66,7 +65,12 @@ #define PRID_IMP_20KC 0x8200 #define PRID_IMP_4KEC 0x8400 #define PRID_IMP_4KSC 0x8600 - +#define PRID_IMP_25KF 0x8800 +#define PRID_IMP_5KE 0x8900 +#define PRID_IMP_4KECR2 0x9000 +#define PRID_IMP_4KEMPR2 0x9100 +#define PRID_IMP_4KSD 0x9200 +#define PRID_IMP_24K 0x9300 #define PRID_IMP_UNKNOWN 0xff00 @@ -101,7 +105,7 @@ #define PRID_REV_VR4121 0x0060 #define PRID_REV_VR4122 0x0070 #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ -#define PRID_REV_VR4131 0x0080 +#define PRID_REV_VR4130 0x0080 /* * FPU implementation/revision register (CP1 control register 0). @@ -168,7 +172,12 @@ #define CPU_VR4181A 51 #define CPU_AU1100 52 #define CPU_SR71000 53 -#define CPU_LAST 53 +#define CPU_RM9000 54 +#define CPU_25KF 55 +#define CPU_VR4133 56 +#define CPU_AU1550 57 +#define CPU_24K 58 +#define CPU_LAST 58 /* * ISA Level encodings @@ -201,11 +210,13 @@ #define MIPS_CPU_MIPS16 0x00000100 /* code compression */ #define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ #define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ -#define MIPS_CPU_CACHE_CDEX 0x00000800 /* Create_Dirty_Exclusive CACHE op */ -#define MIPS_CPU_MCHECK 0x00001000 /* Machine check exception */ -#define MIPS_CPU_EJTAG 0x00002000 /* EJTAG exception */ -#define MIPS_CPU_NOFPUEX 0x00004000 /* no FPU exception */ -#define MIPS_CPU_LLSC 0x00008000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_SUBSET_CACHES 0x00010000 /* P-cache subset enforced */ +#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */ +#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */ +#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */ +#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */ +#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */ +#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */ +#define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */ +#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */ #endif /* _ASM_CPU_H */ diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h index 8d83a3b60b38..724908b0bf13 100644 --- a/include/asm-mips/dec/ecc.h +++ b/include/asm-mips/dec/ecc.h @@ -42,10 +42,14 @@ #ifndef __ASSEMBLY__ + +#include <linux/interrupt.h> + struct pt_regs; + extern void dec_ecc_be_init(void); extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup); -extern void dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs); +extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs); #endif #endif /* __ASM_MIPS_DEC_ECC_H */ diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h index 71a2b8eeced0..b120362b8f13 100644 --- a/include/asm-mips/dec/kn05.h +++ b/include/asm-mips/dec/kn05.h @@ -50,6 +50,7 @@ */ #define KN05_MB_INT_TC (1<<0) /* TURBOchannel? */ #define KN05_MB_INT_RTC (1<<1) /* RTC? */ +#define KN05_MB_INT_MT (1<<3) /* ??? */ /* * Bits for the MB control & status register. diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h index 93d7f858443c..b63e2f2317d1 100644 --- a/include/asm-mips/dec/prom.h +++ b/include/asm-mips/dec/prom.h @@ -15,6 +15,7 @@ #ifndef _ASM_DEC_PROM_H #define _ASM_DEC_PROM_H +#include <linux/config.h> #include <linux/types.h> #include <asm/addrspace.h> @@ -166,4 +167,7 @@ extern void prom_meminit(u32); extern void prom_identify_arch(u32); extern void prom_init_cmdline(s32, s32 *, u32); +extern void register_prom_console(void); +extern void unregister_prom_console(void); + #endif /* _ASM_DEC_PROM_H */ diff --git a/include/asm-mips/dec/rtc-dec.h b/include/asm-mips/dec/rtc-dec.h deleted file mode 100644 index 056da821ffeb..000000000000 --- a/include/asm-mips/dec/rtc-dec.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * include/asm-mips/dec/rtc-dec.h - * - * RTC definitions for DECstation style attached Dallas DS1287 chip. - * - * Copyright (C) 2002 Maciej W. Rozycki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ -#ifndef __ASM_MIPS_DEC_RTC_DEC_H -#define __ASM_MIPS_DEC_RTC_DEC_H - -#include <linux/types.h> - -#include <asm/addrspace.h> - -extern volatile u8 *dec_rtc_base; -extern unsigned long dec_kn_slot_size; - -extern struct rtc_ops dec_rtc_ops; - -#define RTC_PORT(x) CPHYSADDR(dec_rtc_base) -#define RTC_IO_EXTENT dec_kn_slot_size -#define RTC_IOMAPPED 0 -#define RTC_IRQ 0 - -#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */ - -#endif /* __ASM_MIPS_DEC_RTC_DEC_H */ diff --git a/include/asm-mips/dma-mapping.h b/include/asm-mips/dma-mapping.h index d72e991e4a2b..722cb7b97fbe 100644 --- a/include/asm-mips/dma-mapping.h +++ b/include/asm-mips/dma-mapping.h @@ -1,10 +1,15 @@ #ifndef _ASM_DMA_MAPPING_H #define _ASM_DMA_MAPPING_H +#include <linux/device.h> +#include <asm/scatterlist.h> #include <asm/cache.h> -#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f) -#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) +void *dma_alloc_noncoherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, int flag); + +void dma_free_noncoherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle); void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle, int flag); @@ -12,8 +17,6 @@ void *dma_alloc_coherent(struct device *dev, size_t size, void dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle); -#ifdef CONFIG_MAPPED_DMA_IO - extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size, enum dma_data_direction direction); extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, @@ -33,162 +36,7 @@ extern void dma_sync_single_range(struct device *dev, dma_addr_t dma_handle, extern void dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, enum dma_data_direction direction); -#else - -static inline dma_addr_t -dma_map_single(struct device *dev, void *ptr, size_t size, - enum dma_data_direction direction) -{ - unsigned long addr = (unsigned long) ptr; - - BUG_ON(direction == DMA_NONE); - - dma_cache_wback_inv(addr, size); - - return bus_to_baddr(hwdev->bus, __pa(ptr)); -} - -static inline void -dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); - - if (direction != DMA_TO_DEVICE) { - unsigned long addr; - - addr = baddr_to_bus(hwdev->bus, dma_addr) + PAGE_OFFSET; - dma_cache_wback_inv(addr, size); - } -} - -static inline int -dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction direction) -{ - int i; - - BUG_ON(direction == DMA_NONE); - - for (i = 0; i < nents; i++, sg++) { - unsigned long addr; - - addr = (unsigned long) page_address(sg->page); - if (addr) - dma_cache_wback_inv(addr + sg->offset, sg->length); - sg->dma_address = (dma_addr_t) bus_to_baddr(hwdev->bus, - page_to_phys(sg->page) + sg->offset); - } - - return nents; -} - -static inline dma_addr_t -dma_map_page(struct device *dev, struct page *page, unsigned long offset, - size_t size, enum dma_data_direction direction) -{ - unsigned long addr; - - BUG_ON(direction == DMA_NONE); - addr = (unsigned long) page_address(page) + offset; - dma_cache_wback_inv(addr, size); - - return bus_to_baddr(hwdev->bus, page_to_phys(page) + offset); -} - -static inline void -dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, - enum dma_data_direction direction) -{ - BUG_ON(direction == DMA_NONE); - - if (direction != DMA_TO_DEVICE) { - unsigned long addr; - - addr = baddr_to_bus(hwdev->bus, dma_address) + PAGE_OFFSET; - dma_cache_wback_inv(addr, size); - } -} - -static inline void -dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, - enum dma_data_direction direction) -{ - int i; - - BUG_ON(direction == DMA_NONE); - - if (direction == DMA_TO_DEVICE) - return; - - for (i = 0; i < nhwentries; i++, sg++) { - unsigned long addr; - - BUG_ON(!sg->page); - - addr = (unsigned long) page_address(sg->page); - if (addr) - dma_cache_wback_inv(addr + sg->offset, sg->length); - } -} - -static inline void -dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, - enum dma_data_direction direction) -{ - unsigned long addr; - - BUG_ON(direction == DMA_NONE); - - addr = baddr_to_bus(hwdev->bus, dma_handle) + PAGE_OFFSET; - dma_cache_wback_inv(addr, size); -} - -static inline void -dma_sync_single_range(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, - enum dma_data_direction direction) -{ - unsigned long addr; - - BUG_ON(direction == DMA_NONE); - - addr = baddr_to_bus(hwdev->bus, dma_handle) + PAGE_OFFSET; - dma_cache_wback_inv(addr, size); -} - -static inline void -dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, - enum dma_data_direction direction) -{ -#ifdef CONFIG_NONCOHERENT_IO - int i; -#endif - - BUG_ON(direction == DMA_NONE); - - /* Make sure that gcc doesn't leave the empty loop body. */ -#ifdef CONFIG_NONCOHERENT_IO - for (i = 0; i < nelems; i++, sg++) - dma_cache_wback_inv((unsigned long)page_address(sg->page), - sg->length); -#endif -} -#endif /* CONFIG_MAPPED_DMA_IO */ - -static inline int -dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if (mask < 0x00ffffff) - return 0; - - return 1; -} +extern int dma_supported(struct device *dev, u64 mask); static inline int dma_set_mask(struct device *dev, u64 mask) @@ -208,17 +56,9 @@ dma_get_cache_alignment(void) return 128; } -#ifdef CONFIG_NONCOHERENT_IO -#define dma_is_consistent(d) (0) -#else -#define dma_is_consistent(d) (1) -#endif +extern int dma_is_consistent(dma_addr_t dma_addr); -static inline void -dma_cache_sync(void *vaddr, size_t size, - enum dma_data_direction direction) -{ - dma_cache_wback_inv((unsigned long)vaddr, size); -} +extern void dma_cache_sync(void *vaddr, size_t size, + enum dma_data_direction direction); #endif /* _ASM_DMA_MAPPING_H */ diff --git a/include/asm-mips/ds1286.h b/include/asm-mips/ds1286.h index 56af9b10d01b..6983b6ff0af3 100644 --- a/include/asm-mips/ds1286.h +++ b/include/asm-mips/ds1286.h @@ -3,57 +3,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM - * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993 - * derived from Data Sheet, Copyright Motorola 1984 (!). - * It was written to be part of the Linux operating system. + * Machine dependent access functions for RTC registers. * - * Copyright (C) 1998, 1999 Ralf Baechle + * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org) */ -#ifndef _ASM_DS1286_h -#define _ASM_DS1286_h +#ifndef _ASM_DS1286_H +#define _ASM_DS1286_H -#include <asm/mc146818rtc.h> +#include <ds1286.h> -/********************************************************************** - * register summary - **********************************************************************/ -#define RTC_HUNDREDTH_SECOND 0 -#define RTC_SECONDS 1 -#define RTC_MINUTES 2 -#define RTC_MINUTES_ALARM 3 -#define RTC_HOURS 4 -#define RTC_HOURS_ALARM 5 -#define RTC_DAY 6 -#define RTC_DAY_ALARM 7 -#define RTC_DATE 8 -#define RTC_MONTH 9 -#define RTC_YEAR 10 -#define RTC_CMD 11 -#define RTC_WHSEC 12 -#define RTC_WSEC 13 -#define RTC_UNUSED 14 - -/* RTC_*_alarm is always true if 2 MSBs are set */ -# define RTC_ALARM_DONT_CARE 0xC0 - - -/* - * Bits in the month register - */ -#define RTC_EOSC 0x80 -#define RTC_ESQW 0x40 - -/* - * Bits in the Command register - */ -#define RTC_TDF 0x01 -#define RTC_WAF 0x02 -#define RTC_TDM 0x04 -#define RTC_WAM 0x08 -#define RTC_PU_LVL 0x10 -#define RTC_IBH_LO 0x20 -#define RTC_IPSW 0x40 -#define RTC_TE 0x80 - -#endif /* _ASM_DS1286_h */ +#endif /* _ASM_DS1286_H */ diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index e2df9ee000c4..aad1db9e170e 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h @@ -124,6 +124,7 @@ typedef double elf_fpreg_t; typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #ifdef CONFIG_MIPS32 + /* * This is used to ensure we don't load something for the wrong architecture. */ @@ -134,7 +135,12 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; \ if (__h->e_machine != EM_MIPS) \ __res = 0; \ - if (__h->e_ident[EI_CLASS] != ELFCLASS64) \ + if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ + __res = 0; \ + if ((__h->e_flags & EF_MIPS_ABI2) != 0) \ + __res = 0; \ + if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ + ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ __res = 0; \ \ __res; \ @@ -148,7 +154,6 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #endif /* CONFIG_MIPS32 */ #ifdef CONFIG_MIPS64 - /* * This is used to ensure we don't load something for the wrong architecture. */ @@ -159,12 +164,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; \ if (__h->e_machine != EM_MIPS) \ __res = 0; \ - if (__h->e_ident[EI_CLASS] != ELFCLASS32) \ - __res = 0; \ - if ((__h->e_flags & EF_MIPS_ABI2) != 0) \ - __res = 0; \ - if (((__h->e_flags & EF_MIPS_ABI) != 0) && \ - ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \ + if (__h->e_ident[EI_CLASS] != ELFCLASS64) \ __res = 0; \ \ __res; \ @@ -228,7 +228,7 @@ do { current->thread.mflags &= ~MF_ABI_MASK; \ #define irix_elf_check_arch(hdr) ((hdr)->e_machine == EM_MIPS) #define USE_ELF_CORE_DUMP -#define ELF_EXEC_PAGESIZE 4096 +#define ELF_EXEC_PAGESIZE PAGE_SIZE #define ELF_CORE_COPY_REGS(_dest,_regs) \ memcpy((char *) &_dest, (char *) _regs, \ diff --git a/include/asm-mips/floppy.h b/include/asm-mips/floppy.h index 29b7c27b13a7..aa1ef8b352cc 100644 --- a/include/asm-mips/floppy.h +++ b/include/asm-mips/floppy.h @@ -10,57 +10,10 @@ #ifndef _ASM_FLOPPY_H #define _ASM_FLOPPY_H -struct fd_ops { - unsigned char (*fd_inb)(unsigned int port); - void (*fd_outb)(unsigned char value, unsigned int port); - - /* - * How to access the floppy DMA functions. - */ - void (*fd_enable_dma)(int channel); - void (*fd_disable_dma)(int channel); - int (*fd_request_dma)(int channel); - void (*fd_free_dma)(int channel); - void (*fd_clear_dma_ff)(int channel); - void (*fd_set_dma_mode)(int channel, char mode); - void (*fd_set_dma_addr)(int channel, unsigned int a); - void (*fd_set_dma_count)(int channel, unsigned int count); - int (*fd_get_dma_residue)(int channel); - void (*fd_enable_irq)(int irq); - void (*fd_disable_irq)(int irq); - unsigned long (*fd_getfdaddr1)(void); - unsigned long (*fd_dma_mem_alloc)(unsigned long size); - void (*fd_dma_mem_free)(unsigned long addr, unsigned long size); - unsigned long (*fd_drive_type)(unsigned long); -}; - -extern struct fd_ops *fd_ops; - -#define fd_inb(port) fd_ops->fd_inb(port) -#define fd_outb(value,port) fd_ops->fd_outb(value,port) - -#define fd_enable_dma() fd_ops->fd_enable_dma(FLOPPY_DMA) -#define fd_disable_dma() fd_ops->fd_disable_dma(FLOPPY_DMA) -#define fd_request_dma() fd_ops->fd_request_dma(FLOPPY_DMA) -#define fd_free_dma() fd_ops->fd_free_dma(FLOPPY_DMA) -#define fd_clear_dma_ff() fd_ops->fd_clear_dma_ff(FLOPPY_DMA) -#define fd_set_dma_mode(mode) fd_ops->fd_set_dma_mode(FLOPPY_DMA, mode) -#define fd_set_dma_addr(addr) fd_ops->fd_set_dma_addr(FLOPPY_DMA, \ - isa_virt_to_bus(addr)) -#define fd_set_dma_count(count) fd_ops->fd_set_dma_count(FLOPPY_DMA,count) -#define fd_get_dma_residue() fd_ops->fd_get_dma_residue(FLOPPY_DMA) - -#define fd_enable_irq() fd_ops->fd_enable_irq(FLOPPY_IRQ) -#define fd_disable_irq() fd_ops->fd_disable_irq(FLOPPY_IRQ) -#define fd_request_irq() request_irq(FLOPPY_IRQ, floppy_interrupt, \ - SA_INTERRUPT | SA_SAMPLE_RANDOM, \ - "floppy", NULL) -#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); -#define fd_dma_mem_alloc(size) fd_ops->fd_dma_mem_alloc(size) -#define fd_dma_mem_free(mem,size) fd_ops->fd_dma_mem_free(mem,size) -#define fd_drive_type(n) fd_ops->fd_drive_type(n) -#define fd_cacheflush(addr,size) \ - dma_cache_wback_inv((unsigned long)(addr),(size)) +static inline void fd_cacheflush(char * addr, long size) +{ + dma_cache_wback_inv((unsigned long)addr,size); +} #define MAX_BUFFER_SECTORS 24 @@ -71,10 +24,10 @@ extern struct fd_ops *fd_ops; * FIXME: This information should come from the ARC configuration tree * or whereever a particular machine has stored this ... */ -#define FLOPPY0_TYPE fd_drive_type(0) -#define FLOPPY1_TYPE fd_drive_type(1) +#define FLOPPY0_TYPE fd_drive_type(0) +#define FLOPPY1_TYPE fd_drive_type(1) -#define FDC1 fd_ops->fd_getfdaddr1(); +#define FDC1 fd_getfdaddr1(); #define N_FDC 1 /* do you *really* want a second controller? */ #define N_DRIVE 8 @@ -98,4 +51,6 @@ extern struct fd_ops *fd_ops; #define EXTRA_FLOPPY_PARAMS +#include <floppy.h> + #endif /* _ASM_FLOPPY_H */ diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h index 1957677c4515..6cb38d5c0407 100644 --- a/include/asm-mips/fpu.h +++ b/include/asm-mips/fpu.h @@ -16,6 +16,7 @@ #include <asm/mipsregs.h> #include <asm/cpu.h> +#include <asm/cpu-features.h> #include <asm/bitops.h> #include <asm/processor.h> #include <asm/current.h> diff --git a/include/asm-mips/galileo-boards/ev64120.h b/include/asm-mips/galileo-boards/ev64120.h deleted file mode 100644 index e0b7423ddcdd..000000000000 --- a/include/asm-mips/galileo-boards/ev64120.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This is a direct copy of the ev96100.h file, with a global - * search and replace. The numbers are the same. - * - * The reason I'm duplicating this is so that the 64120/96100 - * defines won't be confusing in the source code. - */ -#ifndef _MIPS_EV64120_H -#define _MIPS_EV64120_H - -#include <asm/addrspace.h> - -/* - * GT64120 config space base address - */ -#define GT64120_BASE (KSEG1ADDR(0x14000000)) -#define MIPS_GT_BASE GT64120_BASE - -/* - * PCI Bus allocation - */ -#define GT_PCI_MEM_BASE 0x12000000 -#define GT_PCI_MEM_SIZE 0x02000000 -#define GT_PCI_IO_BASE 0x10000000 -#define GT_PCI_IO_SIZE 0x02000000 -#define GT_ISA_IO_BASE PCI_IO_BASE - -/* - * Duart I/O ports. - */ -#define EV64120_COM1_BASE_ADDR (0x1d000000 + 0x20) -#define EV64120_COM2_BASE_ADDR (0x1d000000 + 0x00) - - -/* - * EV64120 interrupt controller register base. - */ -#define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) - -/* - * EV64120 UART register base. - */ -#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR)) -#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR)) -#define EV64120_BASE_BAUD ( 3686400 / 16 ) - - -/* - * Because of an error/peculiarity in the Galileo chip, we need to swap the - * bytes when running bigendian. - */ - -#define GT_WRITE(ofs, data) \ - *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data) -#define GT_READ(ofs, data) \ - *data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs)) - - -#endif /* !(_MIPS_EV64120_H) */ diff --git a/include/asm-mips/galileo-boards/ev64120int.h b/include/asm-mips/galileo-boards/ev64120int.h deleted file mode 100644 index 2ceb4a0fd315..000000000000 --- a/include/asm-mips/galileo-boards/ev64120int.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef IRQ_HANDLER_ -#define IRQ_HANDLER_ - -#define INT_CAUSE_MAIN 0 -#define INT_CAUSE_HIGH 1 - -#define MAX_CAUSE_REGS 4 -#define MAX_CAUSE_REG_WIDTH 32 - -void hook_irq_handler (int int_cause , int bit_num , void *isr_ptr); -int disable_galileo_irq (int int_cause , int bit_num); -int enable_galileo_irq (int int_cause , int bit_num); - -extern struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH]; - -/* - PCI interrupts will come in on either the INTA or - INTD interrups lines, which are mapped to the #2 and - #5 interrupt pins of the MIPS. On our boards, they - all either come in on IntD or they all come in on - IntA, they aren't mixed. There can be numerous PCI - interrupts, so we keep a list of the "requested" - interrupt numbers and go through the list whenever - we get an IntA/D. - - All PCI interrupts have numbers >= 20 by arbitrary convention. Any - interrupt < 8 is an interrupt that is maskable on the - MIPS. -*/ - -#define TIMER 4 -#define INTA 2 -#define INTD 5 - - -#endif /* IRQ_HANDLER_ */ diff --git a/include/asm-mips/galileo-boards/ev96100.h b/include/asm-mips/galileo-boards/ev96100.h index 128ca2b2557b..070dfd84a8e8 100644 --- a/include/asm-mips/galileo-boards/ev96100.h +++ b/include/asm-mips/galileo-boards/ev96100.h @@ -9,47 +9,47 @@ /* * GT64120 config space base address */ -#define GT64120_BASE (KSEG1ADDR(0x14000000)) -#define MIPS_GT_BASE GT64120_BASE +#define GT64120_BASE (KSEG1ADDR(0x14000000)) +#define MIPS_GT_BASE GT64120_BASE /* * PCI Bus allocation */ -#define GT_PCI_MEM_BASE 0x12000000 -#define GT_PCI_MEM_SIZE 0x02000000 -#define GT_PCI_IO_BASE 0x10000000 -#define GT_PCI_IO_SIZE 0x02000000 +#define GT_PCI_MEM_BASE 0x12000000UL +#define GT_PCI_MEM_SIZE 0x02000000UL +#define GT_PCI_IO_BASE 0x10000000UL +#define GT_PCI_IO_SIZE 0x02000000UL #define GT_ISA_IO_BASE PCI_IO_BASE /* * Duart I/O ports. */ -#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20) -#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00) +#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20) +#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00) /* * EV96100 interrupt controller register base. */ -#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) +#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) /* * EV96100 UART register base. */ -#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR -#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR -#define EV96100_BASE_BAUD ( 3686400 / 16 ) +#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR +#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR +#define EV96100_BASE_BAUD ( 3686400 / 16 ) /* * Because of an error/peculiarity in the Galileo chip, we need to swap the * bytes when running bigendian. */ - -#define GT_WRITE(ofs, data) \ - *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data) -#define GT_READ(ofs, data) \ - data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs)) - +#define __GT_READ(ofs) \ + (*(volatile u32 *)(GT64120_BASE+(ofs))) +#define __GT_WRITE(ofs, data) \ + do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0) +#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs)) +#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) #endif /* !(_MIPS_EV96100_H) */ diff --git a/include/asm-mips/galileo-boards/gt96100.h b/include/asm-mips/galileo-boards/gt96100.h index 24312b339ca9..aabd1b629c19 100644 --- a/include/asm-mips/galileo-boards/gt96100.h +++ b/include/asm-mips/galileo-boards/gt96100.h @@ -3,8 +3,6 @@ * Author: MontaVista Software, Inc. * stevel@mvista.com or source@mvista.com * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -18,10 +16,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - * * Register offsets of the MIPS GT96100 Advanced Communication Controller. - * */ #ifndef _GT96100_H #define _GT96100_H diff --git a/include/asm-mips/gdb-stub.h b/include/asm-mips/gdb-stub.h index 1e269fa2704f..bbc328f248a1 100644 --- a/include/asm-mips/gdb-stub.h +++ b/include/asm-mips/gdb-stub.h @@ -22,11 +22,11 @@ * Stack layout for the GDB exception handler * Derived from the stack layout described in asm-mips/stackframe.h * - * The first PTRSIZE*5 bytes are argument save space for C subroutines. + * The first PTRSIZE*6 bytes are argument save space for C subroutines. */ #define NUMREGS 90 -#define GDB_FR_REG0 (PTRSIZE*5) /* 0 */ +#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */ #define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */ #define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */ #define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */ @@ -143,9 +143,9 @@ struct gdb_regs { /* * Pad bytes for argument save space on the stack - * 20/40 Bytes for 32/64 bit code + * 24/48 Bytes for 32/64 bit code */ - unsigned long pad0[5]; + unsigned long pad0[6]; /* * saved main processor registers diff --git a/include/asm-mips/gt64120.h b/include/asm-mips/gt64120.h index 9cf9edcdd54d..8a02ef79e17c 100644 --- a/include/asm-mips/gt64120.h +++ b/include/asm-mips/gt64120.h @@ -18,6 +18,10 @@ #ifndef _ASM_GT64120_H #define _ASM_GT64120_H +#include <linux/config.h> +#include <asm/addrspace.h> +#include <asm/byteorder.h> + #define MSK(n) ((1 << (n)) - 1) /* @@ -391,9 +395,36 @@ /* * Misc */ -#define GT_DEF_BASE 0x14000000 -#define GT_DEF_PCI0_MEM0_BASE 0x12000000 +#define GT_DEF_PCI0_IO_BASE 0x10000000UL +#define GT_DEF_PCI0_IO_SIZE 0x02000000UL +#define GT_DEF_PCI0_MEM0_BASE 0x12000000UL +#define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL +#define GT_DEF_BASE 0x14000000UL + #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ #define GT_LATTIM_MIN 6 /* Minimum lat */ +/* + * The gt64120_dep.h file must define the following macros + * + * GT_READ(ofs, data_pointer) + * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit + * + * TIMER - gt64120 timer irq, temporary solution until + * full gt64120 cascade interrupt support is in place + */ + +#include <mach-gt64120.h> + +/* + * Because of an error/peculiarity in the Galileo chip, we need to swap the + * bytes when running bigendian. We also provide non-swapping versions. + */ +#define __GT_READ(ofs) \ + (*(volatile u32 *)(GT64120_BASE+(ofs))) +#define __GT_WRITE(ofs, data) \ + do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0) +#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs)) +#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) + #endif /* _ASM_GT64120_H */ diff --git a/include/asm-mips/gt64120/gt64120.h b/include/asm-mips/gt64120/gt64120.h deleted file mode 100644 index 73a4ca4e8c8b..000000000000 --- a/include/asm-mips/gt64120/gt64120.h +++ /dev/null @@ -1,444 +0,0 @@ -/* - * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. - * Carsten Langgaard, carstenl@mips.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#ifndef __ASM_GT64120_GT64120_H -#define __ASM_GT64120_GT64120_H - -#define MSK(n) ((1 << (n)) - 1) - -/* - * Register offset addresses - */ -#define GT_CPU_OFS 0x000 - -/* - * Interrupt Registers - */ -#define GT_SCS10LD_OFS 0x008 -#define GT_SCS10HD_OFS 0x010 -#define GT_SCS32LD_OFS 0x018 -#define GT_SCS32HD_OFS 0x020 -#define GT_CS20LD_OFS 0x028 -#define GT_CS20HD_OFS 0x030 -#define GT_CS3BOOTLD_OFS 0x038 -#define GT_CS3BOOTHD_OFS 0x040 -#define GT_PCI0IOLD_OFS 0x048 -#define GT_PCI0IOHD_OFS 0x050 -#define GT_PCI0M0LD_OFS 0x058 -#define GT_PCI0M0HD_OFS 0x060 -#define GT_ISD_OFS 0x068 -#define GT_PCI0M1LD_OFS 0x080 -#define GT_PCI0M1HD_OFS 0x088 -#define GT_PCI1IOLD_OFS 0x090 -#define GT_PCI1IOHD_OFS 0x098 -#define GT_PCI1M0LD_OFS 0x0a0 -#define GT_PCI1M0HD_OFS 0x0a8 -#define GT_PCI1M1LD_OFS 0x0b0 -#define GT_PCI1M1HD_OFS 0x0b8 - -/* - * GT64120A only - */ -#define GT_PCI0IOREMAP_OFS 0x0f0 -#define GT_PCI0M0REMAP_OFS 0x0f8 -#define GT_PCI0M1REMAP_OFS 0x100 -#define GT_PCI1IOREMAP_OFS 0x108 -#define GT_PCI1M0REMAP_OFS 0x110 -#define GT_PCI1M1REMAP_OFS 0x118 - -#define GT_SCS0LD_OFS 0x400 -#define GT_SCS0HD_OFS 0x404 -#define GT_SCS1LD_OFS 0x408 -#define GT_SCS1HD_OFS 0x40c -#define GT_SCS2LD_OFS 0x410 -#define GT_SCS2HD_OFS 0x414 -#define GT_SCS3LD_OFS 0x418 -#define GT_SCS3HD_OFS 0x41c -#define GT_CS0LD_OFS 0x420 -#define GT_CS0HD_OFS 0x424 -#define GT_CS1LD_OFS 0x428 -#define GT_CS1HD_OFS 0x42c -#define GT_CS2LD_OFS 0x430 -#define GT_CS2HD_OFS 0x434 -#define GT_CS3LD_OFS 0x438 -#define GT_CS3HD_OFS 0x43c -#define GT_BOOTLD_OFS 0x440 -#define GT_BOOTHD_OFS 0x444 - -#define GT_SDRAM_B0_OFS 0x44c -#define GT_SDRAM_CFG_OFS 0x448 -#define GT_SDRAM_B2_OFS 0x454 -#define GT_SDRAM_OPMODE_OFS 0x474 -#define GT_SDRAM_BM_OFS 0x478 -#define GT_SDRAM_ADDRDECODE_OFS 0x47c - -#define GT_PCI0_CMD_OFS 0xc00 /* GT64120A only */ -#define GT_PCI0_TOR_OFS 0xc04 -#define GT_PCI0_BS_SCS10_OFS 0xc08 -#define GT_PCI0_BS_SCS32_OFS 0xc0c -#define GT_INTRCAUSE_OFS 0xc18 -#define GT_INTRMASK_OFS 0xc1c /* GT64120A only */ -#define GT_PCI0_IACK_OFS 0xc34 -#define GT_PCI0_BARE_OFS 0xc3c -#define GT_HINTRCAUSE_OFS 0xc98 /* GT64120A only */ -#define GT_HINTRMASK_OFS 0xc9c /* GT64120A only */ -#define GT_PCI1_CFGADDR_OFS 0xcf0 /* GT64120A only */ -#define GT_PCI1_CFGDATA_OFS 0xcf4 /* GT64120A only */ -#define GT_PCI0_CFGADDR_OFS 0xcf8 -#define GT_PCI0_CFGDATA_OFS 0xcfc - - -/* - * Timer/Counter. GT64120A only. - */ -#define GT_TC0_OFS 0x850 -#define GT_TC1_OFS 0x854 -#define GT_TC2_OFS 0x858 -#define GT_TC3_OFS 0x85C -#define GT_TC_CONTROL_OFS 0x864 - -/* - * I2O Support Registers - */ -#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 -#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 -#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 -#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c -#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 -#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 -#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 -#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 -#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 -#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 -#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c - -#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 -#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 -#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 -#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c -#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 -#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 -#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 -#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c -#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 -#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 -#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 -#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 -#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 -#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 -#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 -#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 -#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 -#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c -#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 -#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 -#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 -#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c - -/* - * Register encodings - */ -#define GT_CPU_ENDIAN_SHF 12 -#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) -#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK -#define GT_CPU_WR_SHF 16 -#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) -#define GT_CPU_WR_BIT GT_CPU_WR_MSK -#define GT_CPU_WR_DXDXDXDX 0 -#define GT_CPU_WR_DDDD 1 - - -#define GT_CFGADDR_CFGEN_SHF 31 -#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) -#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK - -#define GT_CFGADDR_BUSNUM_SHF 16 -#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) - -#define GT_CFGADDR_DEVNUM_SHF 11 -#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) - -#define GT_CFGADDR_FUNCNUM_SHF 8 -#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) - -#define GT_CFGADDR_REGNUM_SHF 2 -#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) - - -#define GT_SDRAM_BM_ORDER_SHF 2 -#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) -#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK -#define GT_SDRAM_BM_ORDER_SUB 1 -#define GT_SDRAM_BM_ORDER_LIN 0 - -#define GT_SDRAM_BM_RSVD_ALL1 0xffb - - -#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 -#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) -#define GT_SDRAM_ADDRDECODE_ADDR_0 0 -#define GT_SDRAM_ADDRDECODE_ADDR_1 1 -#define GT_SDRAM_ADDRDECODE_ADDR_2 2 -#define GT_SDRAM_ADDRDECODE_ADDR_3 3 -#define GT_SDRAM_ADDRDECODE_ADDR_4 4 -#define GT_SDRAM_ADDRDECODE_ADDR_5 5 -#define GT_SDRAM_ADDRDECODE_ADDR_6 6 -#define GT_SDRAM_ADDRDECODE_ADDR_7 7 - - -#define GT_SDRAM_B0_CASLAT_SHF 0 -#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) -#define GT_SDRAM_B0_CASLAT_2 1 -#define GT_SDRAM_B0_CASLAT_3 2 - -#define GT_SDRAM_B0_FTDIS_SHF 2 -#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) -#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK - -#define GT_SDRAM_B0_SRASPRCHG_SHF 3 -#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) -#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK -#define GT_SDRAM_B0_SRASPRCHG_2 0 -#define GT_SDRAM_B0_SRASPRCHG_3 1 - -#define GT_SDRAM_B0_B0COMPAB_SHF 4 -#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) -#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK - -#define GT_SDRAM_B0_64BITINT_SHF 5 -#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) -#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK -#define GT_SDRAM_B0_64BITINT_2 0 -#define GT_SDRAM_B0_64BITINT_4 1 - -#define GT_SDRAM_B0_BW_SHF 6 -#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) -#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK -#define GT_SDRAM_B0_BW_32 0 -#define GT_SDRAM_B0_BW_64 1 - -#define GT_SDRAM_B0_BLODD_SHF 7 -#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) -#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK - -#define GT_SDRAM_B0_PAR_SHF 8 -#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) -#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK - -#define GT_SDRAM_B0_BYPASS_SHF 9 -#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) -#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK - -#define GT_SDRAM_B0_SRAS2SCAS_SHF 10 -#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) -#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK -#define GT_SDRAM_B0_SRAS2SCAS_2 0 -#define GT_SDRAM_B0_SRAS2SCAS_3 1 - -#define GT_SDRAM_B0_SIZE_SHF 11 -#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) -#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK -#define GT_SDRAM_B0_SIZE_16M 0 -#define GT_SDRAM_B0_SIZE_64M 1 - -#define GT_SDRAM_B0_EXTPAR_SHF 12 -#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) -#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK - -#define GT_SDRAM_B0_BLEN_SHF 13 -#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) -#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK -#define GT_SDRAM_B0_BLEN_8 0 -#define GT_SDRAM_B0_BLEN_4 1 - - -#define GT_SDRAM_CFG_REFINT_SHF 0 -#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) - -#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 -#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) -#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK - -#define GT_SDRAM_CFG_RMW_SHF 15 -#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) -#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK - -#define GT_SDRAM_CFG_NONSTAGREF_SHF 16 -#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) -#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK - -#define GT_SDRAM_CFG_DUPCNTL_SHF 19 -#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) -#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK - -#define GT_SDRAM_CFG_DUPBA_SHF 20 -#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) -#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK - -#define GT_SDRAM_CFG_DUPEOT0_SHF 21 -#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) -#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK - -#define GT_SDRAM_CFG_DUPEOT1_SHF 22 -#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) -#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK - -#define GT_SDRAM_OPMODE_OP_SHF 0 -#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) -#define GT_SDRAM_OPMODE_OP_NORMAL 0 -#define GT_SDRAM_OPMODE_OP_NOP 1 -#define GT_SDRAM_OPMODE_OP_PRCHG 2 -#define GT_SDRAM_OPMODE_OP_MODE 3 -#define GT_SDRAM_OPMODE_OP_CBR 4 - - -#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 -#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) -#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK - -#define GT_PCI0_BARE_SWSCS32DIS_SHF 1 -#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) -#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK - -#define GT_PCI0_BARE_SWSCS10DIS_SHF 2 -#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) -#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK - -#define GT_PCI0_BARE_INTIODIS_SHF 3 -#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) -#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK - -#define GT_PCI0_BARE_INTMEMDIS_SHF 4 -#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) -#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK - -#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 -#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) -#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK - -#define GT_PCI0_BARE_CS20DIS_SHF 6 -#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) -#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK - -#define GT_PCI0_BARE_SCS32DIS_SHF 7 -#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) -#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK - -#define GT_PCI0_BARE_SCS10DIS_SHF 8 -#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) -#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK - - -#define GT_INTRCAUSE_MASABORT0_SHF 18 -#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) -#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK - -#define GT_INTRCAUSE_TARABORT0_SHF 19 -#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) -#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK - - -#define GT_PCI0_CFGADDR_REGNUM_SHF 2 -#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) -#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 -#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) -#define GT_PCI0_CFGADDR_DEVNUM_SHF 11 -#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) -#define GT_PCI0_CFGADDR_BUSNUM_SHF 16 -#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 -#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) -#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK - -#define GT_PCI0_CMD_MBYTESWAP_SHF 0 -#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) -#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK -#define GT_PCI0_CMD_MWORDSWAP_SHF 10 -#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) -#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK -#define GT_PCI0_CMD_SBYTESWAP_SHF 16 -#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) -#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK -#define GT_PCI0_CMD_SWORDSWAP_SHF 11 -#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) -#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK - -/* - * Misc - */ -#define GT_DEF_BASE 0x14000000 - -#define GT_DEF_PCI0_IO_BASE 0x10000000 -#define GT_DEF_PCI0_IO_SIZE 0x02000000 -#define GT_DEF_PCI0_MEM0_BASE 0x12000000 -#define GT_DEF_PCI0_MEM0_SIZE 0x02000000 - -#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ -#define GT_LATTIM_MIN 6 /* Minimum lat */ - - -/*********************************************************************** - * BOARD-DEPENDENT SECTIONS * - *********************************************************************** - */ - -/* - * include asm/gt64120/<board>/gt64120_dep.h file - */ - -#include <linux/config.h> -#include <linux/init.h> -#include <linux/pci.h> - -#if defined(CONFIG_MOMENCO_OCELOT) -#include <asm/gt64120/momenco_ocelot/gt64120_dep.h> -#endif - -/* - * The gt64120_dep.h file must define the following macros - * - * GT_READ(ofs, data_pointer) - * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit - * - * TIMER - gt64120 timer irq, temporary solution until - * full gt64120 cascade interrupt support is in place - */ - -/* - * Board-dependent functions, which must be defined in - * arch/mips/gt64120/<board>/pci.c file. - * - * This function is called by pcibios_fixup_bus(bus), which in turn is - * invoked a bus is scanned. You typically fixes IRQ numbers in this routine. - */ -extern void __init gt64120_board_pcibios_fixup_bus(struct pci_bus *bus); - -#endif /* __ASM_GT64120_GT64120_H */ diff --git a/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h b/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h deleted file mode 100644 index fcccb7441c9d..000000000000 --- a/include/asm-mips/gt64120/momenco_ocelot/gt64120_dep.h +++ /dev/null @@ -1,49 +0,0 @@ -/*********************************************************************** - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * include/asm-mips/gt64120/momenco-ocelot/gt64120-dep.h - * Board-dependent definitions for GT-64120 chip. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - *********************************************************************** - */ - -#ifndef _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H -#define _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H - -#include <asm/addrspace.h> /* for KSEG1ADDR() */ -#include <asm/byteorder.h> /* for cpu_to_le32() */ - -/* - * PCI address allocation - */ -#define GT_PCI_MEM_BASE (0x22000000) -#define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE -#define GT_PCI_IO_BASE (0x20000000) -#define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE - -extern unsigned long gt64120_base; - -#define GT64120_BASE (gt64120_base) - -/* - * Because of an error/peculiarity in the Galileo chip, we need to swap the - * bytes when running bigendian. - */ - -#define GT_WRITE(ofs, data) \ - *(volatile u32 *)(GT64120_BASE+ofs) = cpu_to_le32(data) -#define GT_READ(ofs, data) \ - *data = le32_to_cpu(*(volatile u32 *)(GT64120_BASE+ofs)) - - -/* - * gt timer irq - */ -#define TIMER 6 - -#endif /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */ diff --git a/include/asm-mips/hardirq.h b/include/asm-mips/hardirq.h index 6f5f9a35dbe6..82f90500030a 100644 --- a/include/asm-mips/hardirq.h +++ b/include/asm-mips/hardirq.h @@ -80,6 +80,7 @@ typedef struct { #define irq_enter() (preempt_count() += HARDIRQ_OFFSET) #ifdef CONFIG_PREEMPT +# include <linux/smp_lock.h> # define in_atomic() (preempt_count() != kernel_locked()) # define IRQ_EXIT_OFFSET (HARDIRQ_OFFSET-1) #else diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h new file mode 100644 index 000000000000..1c8d3132484e --- /dev/null +++ b/include/asm-mips/hazards.h @@ -0,0 +1,49 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef _ASM_HAZARDS_H +#define _ASM_HAZARDS_H + +#include <linux/config.h> + +#ifdef __ASSEMBLY__ + +/* + * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent + * use of the JTLB for instructions should not occur for 4 cpu cycles and use + * for data translations should not occur for 3 cpu cycles. + */ +#ifdef CONFIG_CPU_RM9000 +#define rm9000_tlb_hazard \ + .set push; \ + .set mips32; \ + ssnop; ssnop; ssnop; ssnop; \ + .set pop +#else +#define rm9000_tlb_hazard +#endif + +#else + +/* + * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent + * use of the JTLB for instructions should not occur for 4 cpu cycles and use + * for data translations should not occur for 3 cpu cycles. + */ +#ifdef CONFIG_CPU_RM9000 +#define rm9000_tlb_hazard() \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "ssnop; ssnop; ssnop; ssnop\n\t" \ + ".set\tmips0") +#else +#define rm9000_tlb_hazard() do { } while (0) +#endif + +#endif + +#endif /* _ASM_HAZARDS_H */ diff --git a/include/asm-mips/highmem.h b/include/asm-mips/highmem.h index 963c9c6c81c9..205c69d9a3f4 100644 --- a/include/asm-mips/highmem.h +++ b/include/asm-mips/highmem.h @@ -19,7 +19,6 @@ #ifdef __KERNEL__ -#include <linux/config.h> #include <linux/init.h> #include <linux/interrupt.h> #include <asm/kmap_types.h> diff --git a/include/asm-mips/hw_irq.h b/include/asm-mips/hw_irq.h index 6996095113d4..8be338b9ac10 100644 --- a/include/asm-mips/hw_irq.h +++ b/include/asm-mips/hw_irq.h @@ -19,8 +19,6 @@ extern int i8259A_irq_pending(unsigned int irq); extern void make_8259A_irq(unsigned int irq); extern void init_8259A(int aeoi); -#include <asm/atomic.h> - extern atomic_t irq_err_count; /* This may not be apropriate for all machines, we'll see ... */ diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h index 742130c8be47..0214abe3f0af 100644 --- a/include/asm-mips/i8259.h +++ b/include/asm-mips/i8259.h @@ -4,6 +4,7 @@ * i8259A interrupt definitions. * * Copyright (C) 2003 Maciej W. Rozycki + * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -13,11 +14,54 @@ #ifndef _ASM_I8259_H #define _ASM_I8259_H +#include <linux/compiler.h> #include <linux/spinlock.h> #include <asm/io.h> -#include <asm/system.h> + +extern spinlock_t i8259A_lock; extern void init_i8259_irqs(void); +/* + * Do the traditional i8259 interrupt polling thing. This is for the few + * cases where no better interrupt acknowledge method is available and we + * absolutely must touch the i8259. + */ +static inline int i8259_irq(void) +{ + int irq; + + spin_lock(&i8259A_lock); + + /* Perform an interrupt acknowledge cycle on controller 1. */ + outb(0x0C, 0x20); /* prepare for poll */ + irq = inb(0x20) & 7; + if (irq == 2) { + /* + * Interrupt is cascaded so perform interrupt + * acknowledge on controller 2. + */ + outb(0x0C, 0xA0); /* prepare for poll */ + irq = (inb(0xA0) & 7) + 8; + } + + if (unlikely(irq == 7)) { + /* + * This may be a spurious interrupt. + * + * Read the interrupt status register (ISR). If the most + * significant bit is not set then there is no valid + * interrupt. + */ + outb(0x0B, 0x20); /* ISR register */ + if(~inb(0x20) & 0x80) + irq = -1; + } + + spin_unlock(&i8259A_lock); + + return irq; +} + #endif /* _ASM_I8259_H */ diff --git a/include/asm-mips/ide.h b/include/asm-mips/ide.h index f377adcfb1a3..1992aac41a8e 100644 --- a/include/asm-mips/ide.h +++ b/include/asm-mips/ide.h @@ -13,56 +13,7 @@ #ifdef __KERNEL__ -#include <linux/config.h> -#include <asm/byteorder.h> -#include <asm/io.h> - -#ifndef MAX_HWIFS -# ifdef CONFIG_PCI -#define MAX_HWIFS 10 -# else -#define MAX_HWIFS 6 -# endif -#endif - -struct ide_ops { - int (*ide_default_irq)(ide_ioreg_t base); - ide_ioreg_t (*ide_default_io_base)(int index); - void (*ide_init_hwif_ports)(hw_regs_t *hw, ide_ioreg_t data_port, - ide_ioreg_t ctrl_port, int *irq); -}; - -extern struct ide_ops *ide_ops; - -static __inline__ int ide_default_irq(ide_ioreg_t base) -{ - return ide_ops->ide_default_irq(base); -} - -static __inline__ ide_ioreg_t ide_default_io_base(int index) -{ - return ide_ops->ide_default_io_base(index); -} - -static inline void ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, - ide_ioreg_t ctrl_port, int *irq) -{ - ide_ops->ide_init_hwif_ports(hw, data_port, ctrl_port, irq); -} - -static __inline__ void ide_init_default_hwifs(void) -{ -#ifndef CONFIG_PCI - hw_regs_t hw; - int index; - - for(index = 0; index < MAX_HWIFS; index++) { - ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL); - hw.irq = ide_default_irq(ide_default_io_base(index)); - ide_register_hw(&hw, NULL); - } -#endif -} +#include <ide.h> #define __ide_mm_insw ide_insw #define __ide_mm_insl ide_insl diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index a8962b53d96a..9ec7ced7a0f0 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -14,19 +14,13 @@ #include <linux/types.h> #include <asm/addrspace.h> +#include <asm/cpu.h> +#include <asm/cpu-features.h> #include <asm/page.h> #include <asm/pgtable-bits.h> +#include <asm/processor.h> #include <asm/byteorder.h> - -#ifdef CONFIG_SGI_IP27 -extern unsigned long bus_to_baddr[256]; - -#define bus_to_baddr(bus, addr) (bus_to_baddr[(bus)->number] + (addr)) -#define baddr_to_bus(bus, addr) ((addr) - bus_to_baddr[(bus)->number]) -#else -#define bus_to_baddr(bus, addr) (addr) -#define baddr_to_bus(bus, addr) (addr) -#endif +#include <mangle-port.h> /* * Slowdown I/O port space accesses for antique hardware. @@ -177,6 +171,24 @@ extern unsigned long isa_slot_offset; extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags); extern void __iounmap(void *addr); +static inline void * __ioremap_mode(unsigned long offset, unsigned long size, + unsigned long flags) +{ + if (cpu_has_64bit_addresses) { + u64 base = UNCAC_BASE; + + /* + * R10000 supports a 2 bit uncached attribute therefore + * UNCAC_BASE may not equal IO_BASE. + */ + if (flags == _CACHE_UNCACHED) + base = (u64) IO_BASE; + return (void *) (unsigned long) (base + offset); + } + + return __ioremap(offset, size, flags); +} + /* * ioremap - map bus memory into CPU space * @offset: bus address of the memory @@ -189,7 +201,7 @@ extern void __iounmap(void *addr); * address. */ #define ioremap(offset, size) \ - __ioremap((offset), (size), _CACHE_UNCACHED) + __ioremap_mode((offset), (size), _CACHE_UNCACHED) /* * ioremap_nocache - map bus memory into CPU space @@ -211,19 +223,27 @@ extern void __iounmap(void *addr); * write combining or read caching is not desirable: */ #define ioremap_nocache(offset, size) \ - __ioremap((offset), (size), _CACHE_UNCACHED) + __ioremap_mode((offset), (size), _CACHE_UNCACHED) + +/* + * These two are MIPS specific ioremap variant. ioremap_cacheable_cow + * requests a cachable mapping, ioremap_uncached_accelerated requests a + * mapping using the uncached accelerated mode which isn't supported on + * all processors. + */ #define ioremap_cacheable_cow(offset, size) \ - __ioremap((offset), (size), _CACHE_CACHABLE_COW) + __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW) #define ioremap_uncached_accelerated(offset, size) \ - __ioremap((offset), (size), _CACHE_UNCACHED_ACCELERATED) + __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED) -extern void iounmap(void *addr); +static inline void iounmap(void *addr) +{ + if (cpu_has_64bits) + return; + + __iounmap(addr); +} -/* - * XXX We need system specific versions of these to handle EISA address bits - * 24-31 on SNI. - * XXX more SNI hacks. - */ #define __raw_readb(addr) (*(volatile unsigned char *)(addr)) #define __raw_readw(addr) (*(volatile unsigned short *)(addr)) #define __raw_readl(addr) (*(volatile unsigned int *)(addr)) @@ -240,14 +260,8 @@ extern void iounmap(void *addr); " .set mips0 \n" \ : "=r" (__res) \ : "r" (addr)); \ - \ __res; \ }) -#endif -#ifdef CONFIG_MIPS64 -#define ____raw_readq(addr) (*(volatile unsigned long *)(addr)) -#endif - #define __raw_readq(addr) \ ({ \ unsigned long __flags; \ @@ -256,9 +270,13 @@ extern void iounmap(void *addr); local_irq_save(__flags); \ __res = ____raw_readq(addr); \ local_irq_restore(__flags); \ - \ __res; \ }) +#endif +#ifdef CONFIG_MIPS64 +#define ____raw_readq(addr) (*(volatile unsigned long *)(addr)) +#define __raw_readq(addr) ____raw_readq(addr) +#endif #define readb(addr) __ioswab8(__raw_readb(addr)) #define readw(addr) __ioswab16(__raw_readw(addr)) @@ -273,7 +291,7 @@ extern void iounmap(void *addr); #define __raw_writew(w,addr) ((*(volatile unsigned short *)(addr)) = (w)) #define __raw_writel(l,addr) ((*(volatile unsigned int *)(addr)) = (l)) #ifdef CONFIG_MIPS32 -#define ____raw_writeq(val,addr) \ +#define ____raw_writeq(val,addr) \ ({ \ u64 __tmp; \ \ @@ -288,11 +306,6 @@ extern void iounmap(void *addr); : "=r" (__tmp) \ : "0" ((unsigned long long)val), "r" (addr)); \ }) -#endif -#ifdef CONFIG_MIPS64 -#define ____raw_writeq(l,addr) ((*(volatile unsigned long *)(addr)) = (l)) -#endif - #define __raw_writeq(val,addr) \ ({ \ unsigned long __flags; \ @@ -301,6 +314,11 @@ extern void iounmap(void *addr); ____raw_writeq(val, addr); \ local_irq_restore(__flags); \ }) +#endif +#ifdef CONFIG_MIPS64 +#define ____raw_writeq(q,addr) ((*(volatile unsigned long *)(addr)) = (q)) +#define __raw_writeq(q,addr) ____raw_writeq(q, addr) +#endif #define writeb(b,addr) __raw_writeb(__ioswab8(b),(addr)) #define writew(w,addr) __raw_writew(__ioswab16(w),(addr)) @@ -380,51 +398,76 @@ out: */ #define isa_check_signature(io, s, l) check_signature(i,s,l) -#define outb(val,port) \ -do { \ - *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \ -} while(0) - -#define outw(val,port) \ -do { \ - *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\ -} while(0) - -#define outl(val,port) \ -do { \ - *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\ -} while(0) - -#define outb_p(val,port) \ -do { \ - *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \ - SLOW_DOWN_IO; \ -} while(0) - -#define outw_p(val,port) \ -do { \ - *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\ - SLOW_DOWN_IO; \ -} while(0) - -#define outl_p(val,port) \ -do { \ - *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\ - SLOW_DOWN_IO; \ -} while(0) +static inline void __outb(unsigned char val, unsigned long port) +{ + port = __swizzle_addr_b(port); + + *(volatile u8 *)(mips_io_port_base + port) = __ioswab8(val); +} + +static inline void __outw(unsigned short val, unsigned long port) +{ + port = __swizzle_addr_w(port); + + *(volatile u16 *)(mips_io_port_base + port) = __ioswab16(val); +} + +static inline void __outl(unsigned int val, unsigned long port) +{ + port = __swizzle_addr_l(port); + + *(volatile u32 *)(mips_io_port_base + port) = __ioswab32(val); +} + +static inline void __outb_p(unsigned char val, unsigned long port) +{ + port = __swizzle_addr_b(port); + + *(volatile u8 *)(mips_io_port_base + port) = __ioswab8(val); + SLOW_DOWN_IO; +} + +static inline void __outw_p(unsigned short val, unsigned long port) +{ + port = __swizzle_addr_w(port); + + *(volatile u16 *)(mips_io_port_base + port) = __ioswab16(val); + SLOW_DOWN_IO; +} + +static inline void __outl_p(unsigned int val, unsigned long port) +{ + port = __swizzle_addr_l(port); + + *(volatile u32 *)(mips_io_port_base + port) = __ioswab32(val); + SLOW_DOWN_IO; +} + +#define outb(val, port) __outb(val, port) +#define outw(val, port) __outw(val, port) +#define outl(val, port) __outl(val, port) +#define outb_p(val, port) __outb_p(val, port) +#define outw_p(val, port) __outw_p(val, port) +#define outl_p(val, port) __outl_p(val, port) static inline unsigned char __inb(unsigned long port) { + port = __swizzle_addr_b(port); + return __ioswab8(*(volatile u8 *)(mips_io_port_base + port)); } static inline unsigned short __inw(unsigned long port) { + port = __swizzle_addr_w(port); + return __ioswab16(*(volatile u16 *)(mips_io_port_base + port)); } static inline unsigned int __inl(unsigned long port) { + port = __swizzle_addr_l(port); + return __ioswab32(*(volatile u32 *)(mips_io_port_base + port)); } @@ -432,6 +475,8 @@ static inline unsigned char __inb_p(unsigned long port) { u8 __val; + port = __swizzle_addr_b(port); + __val = *(volatile u8 *)(mips_io_port_base + port); SLOW_DOWN_IO; @@ -442,6 +487,8 @@ static inline unsigned short __inw_p(unsigned long port) { u16 __val; + port = __swizzle_addr_w(port); + __val = *(volatile u16 *)(mips_io_port_base + port); SLOW_DOWN_IO; @@ -452,8 +499,11 @@ static inline unsigned int __inl_p(unsigned long port) { u32 __val; + port = __swizzle_addr_l(port); + __val = *(volatile u32 *)(mips_io_port_base + port); SLOW_DOWN_IO; + return __ioswab32(__val); } @@ -537,7 +587,7 @@ static inline void __insl(unsigned long port, void *addr, unsigned int count) * be discarded. This operation is necessary before dma operations * to the memory. */ -#ifdef CONFIG_NONCOHERENT_IO +#ifdef CONFIG_DMA_NONCOHERENT extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); @@ -556,7 +606,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); #define dma_cache_inv(start,size) \ do { (void) (start); (void) (size); } while (0) -#endif /* CONFIG_NONCOHERENT_IO */ +#endif /* CONFIG_DMA_NONCOHERENT */ /* * Read a 32-bit register that requires a 64-bit read cycle on the bus. diff --git a/include/asm-mips/ioctl.h b/include/asm-mips/ioctl.h index d0fc1a9051db..cba641a6ce09 100644 --- a/include/asm-mips/ioctl.h +++ b/include/asm-mips/ioctl.h @@ -65,11 +65,22 @@ ((nr) << _IOC_NRSHIFT) | \ ((size) << _IOC_SIZESHIFT)) +/* provoke compile error for invalid uses of size argument */ +extern unsigned int __invalid_size_argument_for_IOC; +#define _IOC_TYPECHECK(t) \ + ((sizeof(t) == sizeof(t[1]) && \ + sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ + sizeof(t) : __invalid_size_argument_for_IOC) + /* used to create numbers */ #define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) -#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) -#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) -#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) +#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size))) +#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) +#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size))) +#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) +#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) +#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) + /* used to decode them.. */ #define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) diff --git a/include/asm-mips/ip32/crime.h b/include/asm-mips/ip32/crime.h index 8101f315e337..8caae23e183d 100644 --- a/include/asm-mips/ip32/crime.h +++ b/include/asm-mips/ip32/crime.h @@ -11,32 +11,30 @@ #ifndef __ASM_CRIME_H__ #define __ASM_CRIME_H__ -#include <asm/types.h> #include <asm/addrspace.h> +#include <asm/io.h> /* * Address map */ -#ifndef __ASSEMBLY__ -#define CRIME_BASE KSEG1ADDR(0x14000000) -#else -#define CRIME_BASE 0xffffffffb4000000 -#endif - -#ifndef __ASSEMBLY__ -static inline u64 crime_read_64 (unsigned long __offset) { - return *((volatile u64 *) (CRIME_BASE + __offset)); +#define CRIME_BASE 0x14000000 /* physical */ + +extern void *sgi_crime; + +static inline uint64_t crime_read(unsigned long offset) +{ + return readq(sgi_crime + offset); } -static inline void crime_write_64 (unsigned long __offset, u64 __val) { - *((volatile u64 *) (CRIME_BASE + __offset)) = __val; +static inline void crime_write(uint64_t val, unsigned long offset) +{ + writeq(val, sgi_crime + offset); } -#endif #undef BIT #define BIT(x) (1UL << (x)) /* All CRIME registers are 64 bits */ -#define CRIME_ID 0 +#define CRIME_ID 0x000 #define CRIME_ID_MASK 0xff #define CRIME_ID_IDBITS 0xf0 @@ -48,8 +46,8 @@ static inline void crime_write_64 (unsigned long __offset, u64 __val) { #define CRIME_REV_13 0x13 #define CRIME_REV_14 0x14 -#define CRIME_CONTROL (0x00000008) -#define CRIME_CONTROL_MASK 0x3fff /* 14-bit registers */ +#define CRIME_CONTROL 0x008 +#define CRIME_CONTROL_MASK 0x3fff /* CRIME_CONTROL register bits */ #define CRIME_CONTROL_TRITON_SYSADC 0x2000 @@ -67,10 +65,10 @@ static inline void crime_write_64 (unsigned long __offset, u64 __val) { #define CRIME_CONTROL_WBUF_HWM 0x00f0 #define CRIME_CONTROL_WBUF_SHFT 8 -#define CRIME_INT_STAT (0x00000010) -#define CRIME_INT_MASK (0x00000018) -#define CRIME_SOFT_INT (0x00000020) -#define CRIME_HARD_INT (0x00000028) +#define CRIME_INT_STAT 0x010 +#define CRIME_INT_MASK 0x018 +#define CRIME_SOFT_INT 0x020 +#define CRIME_HARD_INT 0x028 /* Bits in CRIME_INT_XXX and CRIME_HARD_INT */ #define MACE_VID_IN1_INT BIT (0) @@ -113,40 +111,32 @@ static inline void crime_write_64 (unsigned long __offset, u64 __val) { #define CRIME_MACEPCI_INT_MASK 0xff00 #define CRIME_CRIME_INT_MASK 0xffff0000 -/* - * XXX Todo - */ -#define CRIME_DOG (0x00000030) -/* We are word-play compatible but not misspelling compatible */ -#define MC_GRUFF CRIME_DOG -#define CRIME_DOG_MASK (0x001fffff) +#define CRIME_DOG 0x030 +#define CRIME_DOG_MASK 0x001fffff /* CRIME_DOG register bits */ -#define CRIME_DOG_POWER_ON_RESET (0x00010000) -#define CRIME_DOG_WARM_RESET (0x00080000) +#define CRIME_DOG_POWER_ON_RESET 0x00010000 +#define CRIME_DOG_WARM_RESET 0x00080000 #define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET) -#define CRIME_DOG_VALUE (0x00007fff) /* ??? */ +#define CRIME_DOG_VALUE 0x00007fff -#define CRIME_TIME (0x00000038) -#define CRIME_TIME_MASK (0x0000ffffffffffff) +#define CRIME_TIMER 0x038 +#define CRIME_TIMER_MASK 0x0000ffffffffffff -#ifdef MASTER_FREQ -#undef MASTER_FREQ -#endif #define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */ -#define CRIME_NS_PER_TICK 15 /* for delay_calibrate */ +#define CRIME_NS_PER_TICK 15 /* for delay_calibrate */ -#define CRIME_CPU_ERROR_ADDR (0x00000040) -#define CRIME_CPU_ERROR_ADDR_MASK (0x3ffffffff) +#define CRIME_CPU_ERROR_ADDR 0x040 +#define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff -#define CRIME_CPU_ERROR_STAT (0x00000048) +#define CRIME_CPU_ERROR_STAT 0x048 /* REV_PETTY only! */ -#define CRIME_CPU_ERROR_ENA (0x00000050) +#define CRIME_CPU_ERROR_ENA 0x050 /* * bit definitions for CRIME/VICE error status and enable registers */ -#define CRIME_CPU_ERROR_MASK 0x7UL /* cpu error stat is 3 bits */ +#define CRIME_CPU_ERROR_MASK 0x7 /* cpu error stat is 3 bits */ #define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4 #define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2 #define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1 @@ -168,10 +158,10 @@ static inline void crime_write_64 (unsigned long __offset, u64 __val) { #define CRIME_CPU_ERROR_CPU_INV_ADDR_WR 0x2 #define CRIME_CPU_ERROR_CPU_INV_REG_ADDR 0x1 -#define CRIME_VICE_ERROR_ADDR (0x00000058) -#define CRIME_VICE_ERROR_ADDR_MASK (0x3fffffff) +#define CRIME_VICE_ERROR_ADDR 0x058 +#define CRIME_VICE_ERROR_ADDR_MASK 0x3fffffff -#define CRIME_MEM_CONTROL (0x00000200) +#define CRIME_MEM_CONTROL 0x200 #define CRIME_MEM_CONTROL_MASK 0x3 /* 25 cent register */ #define CRIME_MEM_CONTROL_ECC_ENA 0x1 #define CRIME_MEM_CONTROL_USE_ECC_REPL 0x2 @@ -179,20 +169,19 @@ static inline void crime_write_64 (unsigned long __offset, u64 __val) { /* * macros for CRIME memory bank control registers. */ -#define CRIME_MEM_BANK_CONTROL(__bank) (0x00000208 + ((__bank) << 3)) +#define CRIME_MEM_BANK_CONTROL(__bank) (0x208 + ((__bank) << 3)) #define CRIME_MEM_BANK_CONTROL_MASK 0x11f /* 9 bits 7:5 reserved */ #define CRIME_MEM_BANK_CONTROL_ADDR 0x01f #define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100 +#define CRIME_MAXBANKS 8 -#define CRIME_MEM_REFRESH_COUNTER (0x00000248) -#define CRIME_MEM_REFRESH_COUNTER_MASK 0x7ff /* 11-bit register */ - -#define CRIME_MAXBANKS 8 +#define CRIME_MEM_REFRESH_COUNTER 0x248 +#define CRIME_MEM_REFRESH_COUNTER_MASK 0x7ff /* * CRIME Memory error status register bit definitions */ -#define CRIME_MEM_ERROR_STAT (0x00000250) +#define CRIME_MEM_ERROR_STAT 0x250 #define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */ #define CRIME_MEM_ERROR_MACE_ID 0x0000007f #define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080 @@ -213,16 +202,16 @@ static inline void crime_write_64 (unsigned long __offset, u64 __val) { #define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000 -#define CRIME_MEM_ERROR_ADDR (0x00000258) +#define CRIME_MEM_ERROR_ADDR 0x258 #define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff -#define CRIME_MEM_ERROR_ECC_SYN (0x00000260) +#define CRIME_MEM_ERROR_ECC_SYN 0x260 #define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff -#define CRIME_MEM_ERROR_ECC_CHK (0x00000268) +#define CRIME_MEM_ERROR_ECC_CHK 0x268 #define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff -#define CRIME_MEM_ERROR_ECC_REPL (0x00000270) +#define CRIME_MEM_ERROR_ECC_REPL 0x270 #define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff #endif /* __ASM_CRIME_H__ */ diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h index 81d6bdc91927..0f56aaddd6e0 100644 --- a/include/asm-mips/ip32/mace.h +++ b/include/asm-mips/ip32/mace.h @@ -1,90 +1,63 @@ /* - * Definitions for the SGI O2 Mace chip. + * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine) * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2000 Harald Koerfgen + * Copyright (C) 2004 Ladislav Michl */ #ifndef __ASM_MACE_H__ #define __ASM_MACE_H__ -#include <asm/addrspace.h> -#include <asm/system.h> +#include <linux/config.h> +#include <asm/io.h> + /* * Address map */ -#define MACE_BASE KSEG1ADDR(0x1f000000) -#define MACE_PCI (0x00080000) -#define MACE_VIN1 (0x00100000) -#define MACE_VIN2 (0x00180000) -#define MACE_VOUT (0x00200000) -#define MACE_ENET (0x00280000) -#define MACE_PERIF (0x00300000) -#define MACE_ISA_EXT (0x00380000) - -#define MACE_AUDIO_BASE (MACE_PERIF ) -#define MACE_ISA_BASE (MACE_PERIF + 0x00010000) -#define MACE_KBDMS_BASE (MACE_PERIF + 0x00020000) -#define MACE_I2C_BASE (MACE_PERIF + 0x00030000) -#define MACE_UST_BASE (MACE_PERIF + 0x00040000) - +#define MACE_BASE 0x1f000000 /* physical */ #undef BIT -#define BIT(__bit_offset) (1UL << (__bit_offset)) - -/* - * Mace MACEPCI interface, 32 bit regs - */ -#define MACEPCI_ERROR_ADDR (MACE_PCI ) -#define MACEPCI_ERROR_FLAGS (MACE_PCI + 0x00000004) -#define MACEPCI_CONTROL (MACE_PCI + 0x00000008) -#define MACEPCI_REV (MACE_PCI + 0x0000000c) -#define MACEPCI_WFLUSH (MACE_PCI + 0x0000000c) /* ??? --IV !!! It's for flushing read buffers on PCI MEMORY accesses!!! */ -#define MACEPCI_CONFIG_ADDR (MACE_PCI + 0x00000cf8) -#define MACEPCI_CONFIG_DATA (MACE_PCI + 0x00000cfc) -#define MACEPCI_LOW_MEMORY 0x1a000000 -#define MACEPCI_LOW_IO 0x18000000 -#define MACEPCI_SWAPPED_VIEW 0 -#define MACEPCI_NATIVE_VIEW 0x40000000 -#define MACEPCI_IO 0x80000000 -/*#define MACEPCI_HI_MEMORY 0x0000000280000000UL * This mipght be just 0x0000000200000000UL 2G more :) (or maybe it is different between 1.1 & 1.5 */ -#define MACEPCI_HI_MEMORY 0x0000000200000000UL /* This mipght be just 0x0000000200000000UL 2G more :) (or maybe it is different between 1.1 & 1.5 */ -#define MACEPCI_HI_IO 0x0000000100000000UL - -/* - * Bits in the MACEPCI_CONTROL register - */ -#define MACEPCI_CONTROL_INT(x) BIT(x) -#define MACEPCI_CONTROL_INT_MASK 0xff -#define MACEPCI_CONTROL_SERR_ENA BIT(8) -#define MACEPCI_CONTROL_ARB_N6 BIT(9) -#define MACEPCI_CONTROL_PARITY_ERR BIT(10) -#define MACEPCI_CONTROL_MRMRA_ENA BIT(11) -#define MACEPCI_CONTROL_ARB_N3 BIT(12) -#define MACEPCI_CONTROL_ARB_N4 BIT(13) -#define MACEPCI_CONTROL_ARB_N5 BIT(14) -#define MACEPCI_CONTROL_PARK_LIU BIT(15) -#define MACEPCI_CONTROL_INV_INT(x) BIT(16+x) -#define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000 -#define MACEPCI_CONTROL_OVERRUN_INT BIT(24) -#define MACEPCI_CONTROL_PARITY_INT BIT(25) -#define MACEPCI_CONTROL_SERR_INT BIT(26) -#define MACEPCI_CONTROL_IT_INT BIT(27) -#define MACEPCI_CONTROL_RE_INT BIT(28) -#define MACEPCI_CONTROL_DPED_INT BIT(29) -#define MACEPCI_CONTROL_TAR_INT BIT(30) -#define MACEPCI_CONTROL_MAR_INT BIT(31) +#define BIT(x) (1ULL << (x)) + +#ifdef CONFIG_MIPS32 +typedef struct { + volatile unsigned long long reg; +} mace64_t; + +typedef struct { + unsigned long pad; + volatile unsigned long reg; +} mace32_t; +#endif +#ifdef CONFIG_MIPS64 +typedef struct { + volatile unsigned long reg; +} mace64_t; + +typedef struct { + volatile unsigned long reg; +} mace32_t; +#endif + +#define mace_read(r) \ + (sizeof(r.reg) == 4 ? readl(&r.reg) : readq(&r.reg)) +#define mace_write(v,r) \ + (sizeof(r.reg) == 4 ? writel(v,&r.reg) : writeq(v,&r.reg)) /* - * Bits in the MACE_PCI error register + * PCI interface */ +struct mace_pci { + volatile unsigned int error_addr; + volatile unsigned int error; #define MACEPCI_ERROR_MASTER_ABORT BIT(31) #define MACEPCI_ERROR_TARGET_ABORT BIT(30) #define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29) -#define MACEPCI_ERROR_RETRY_ERR BIT(28) +#define MACEPCI_ERROR_RETRY_ERR BIT(28) #define MACEPCI_ERROR_ILLEGAL_CMD BIT(27) #define MACEPCI_ERROR_SYSTEM_ERR BIT(26) #define MACEPCI_ERROR_INTERRUPT_TEST BIT(25) @@ -104,210 +77,299 @@ #define MACEPCI_ERROR_DEVSEL_SLOW 0x80 #define MACEPCI_ERROR_FBB BIT(1) #define MACEPCI_ERROR_66MHZ BIT(0) + volatile unsigned int control; +#define MACEPCI_CONTROL_INT(x) BIT(x) +#define MACEPCI_CONTROL_INT_MASK 0xff +#define MACEPCI_CONTROL_SERR_ENA BIT(8) +#define MACEPCI_CONTROL_ARB_N6 BIT(9) +#define MACEPCI_CONTROL_PARITY_ERR BIT(10) +#define MACEPCI_CONTROL_MRMRA_ENA BIT(11) +#define MACEPCI_CONTROL_ARB_N3 BIT(12) +#define MACEPCI_CONTROL_ARB_N4 BIT(13) +#define MACEPCI_CONTROL_ARB_N5 BIT(14) +#define MACEPCI_CONTROL_PARK_LIU BIT(15) +#define MACEPCI_CONTROL_INV_INT(x) BIT(16+x) +#define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000 +#define MACEPCI_CONTROL_OVERRUN_INT BIT(24) +#define MACEPCI_CONTROL_PARITY_INT BIT(25) +#define MACEPCI_CONTROL_SERR_INT BIT(26) +#define MACEPCI_CONTROL_IT_INT BIT(27) +#define MACEPCI_CONTROL_RE_INT BIT(28) +#define MACEPCI_CONTROL_DPED_INT BIT(29) +#define MACEPCI_CONTROL_TAR_INT BIT(30) +#define MACEPCI_CONTROL_MAR_INT BIT(31) + volatile unsigned int rev; + unsigned int _pad[0xcf8/4 - 4]; + volatile unsigned int config_addr; + union { + volatile unsigned char b[4]; + volatile unsigned short w[2]; + volatile unsigned int l; + } config_data; +}; +#define MACEPCI_LOW_MEMORY 0x1a000000 +#define MACEPCI_LOW_IO 0x18000000 +#define MACEPCI_SWAPPED_VIEW 0 +#define MACEPCI_NATIVE_VIEW 0x40000000 +#define MACEPCI_IO 0x80000000 +#define MACEPCI_HI_MEMORY 0x280000000 +#define MACEPCI_HI_IO 0x100000000 /* - * Mace timer registers - 64 bit regs (63:32 are UST, 31:0 are MSC) - */ -#define MSC_PART(__reg) ((__reg) & 0x00000000ffffffff) -#define UST_PART(__reg) (((__reg) & 0xffffffff00000000) >> 32) - -#define MACE_UST_UST (MACE_UST_BASE ) /* Universial system time */ -#define MACE_UST_COMPARE1 (MACE_UST_BASE + 0x00000008) /* Interrupt compare reg 1 */ -#define MACE_UST_COMPARE2 (MACE_UST_BASE + 0x00000010) /* Interrupt compare reg 2 */ -#define MACE_UST_COMPARE3 (MACE_UST_BASE + 0x00000018) /* Interrupt compare reg 3 */ -#define MACE_UST_PERIOD_NS 960 /* UST Period in ns */ - -#define MACE_UST_AIN_MSC (MACE_UST_BASE + 0x00000020) /* Audio in MSC/UST pair */ -#define MACE_UST_AOUT1_MSC (MACE_UST_BASE + 0x00000028) /* Audio out 1 MSC/UST pair */ -#define MACE_UST_AOUT2_MSC (MACE_UST_BASE + 0x00000030) /* Audio out 2 MSC/UST pair */ -#define MACE_VIN1_MSC_UST (MACE_UST_BASE + 0x00000038) /* Video In 1 MSC/UST pair */ -#define MACE_VIN2_MSC_UST (MACE_UST_BASE + 0x00000040) /* Video In 2 MSC/UST pair */ -#define MACE_VOUT_MSC_UST (MACE_UST_BASE + 0x00000048) /* Video out MSC/UST pair */ - -/* - * Mace "ISA" peripherals - */ -#define MACEISA_EPP_BASE (MACE_ISA_EXT ) -#define MACEISA_ECP_BASE (MACE_ISA_EXT + 0x00008000) -#define MACEISA_SER1_BASE (MACE_ISA_EXT + 0x00010000) -#define MACEISA_SER1_REGS (MACE_ISA_BASE + 0x00020000) -#define MACEISA_SER2_BASE (MACE_ISA_EXT + 0x00018000) -#define MACEISA_SER2_REGS (MACE_ISA_BASE + 0x00030000) -#define MACEISA_RTC_BASE (MACE_ISA_EXT + 0x00020000) -#define MACEISA_GAME_BASE (MACE_ISA_EXT + 0x00030000) - -/* - * Ringbase address and reset register - 64 bits - */ -#define MACEISA_RINGBASE MACE_ISA_BASE -/* Ring buffers occupy 8 4K buffers */ -#define MACEISA_RINGBUFFERS_SIZE 8*4*1024 - -/* - * Flash-ROM/LED/DP-RAM/NIC Controller Register - 64 bits (?) + * Video interface */ -#define MACEISA_FLASH_NIC_REG (MACE_ISA_BASE + 0x00000008) +struct mace_video { + mace32_t xxx; /* later... */ +}; -/* - * Bit definitions for that +/* + * Ethernet interface */ -#define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */ -#define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */ -#define MACEISA_NIC_DEASSERT BIT(2) -#define MACEISA_NIC_DATA BIT(3) -#define MACEISA_LED_RED BIT(4) /* 0=> Illuminate RED LED */ -#define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate GREEN LED */ -#define MACEISA_DP_RAM_ENABLE BIT(6) - -/* - * ISA interrupt and status registers - 32 bit +struct mace_ethernet { + mace32_t mac_ctrl; + mace32_t int_stat; + mace32_t dma_ctrl; + mace32_t timer; + mace32_t tx_int_al; + mace32_t rx_int_al; + mace32_t tx_info; + mace32_t tx_info_al; + mace32_t rx_buff; + mace32_t rx_buff_al1; + mace32_t rx_buff_al2; + mace64_t diag; + mace32_t phy_data; + mace32_t phy_regs; + mace32_t phy_trans_go; + mace32_t backoff_seed; + /*===================================*/ + mace64_t imq_reserved[4]; + mace64_t mac_addr; + mace64_t mac_addr2; + mace64_t mcast_filter; + mace32_t tx_ring_base; + /* Following are read-only registers for debugging */ + mace64_t tx_pkt1_hdr; + mace64_t tx_pkt1_ptr[3]; + mace64_t tx_pkt2_hdr; + mace64_t tx_pkt2_ptr[3]; + /*===================================*/ + mace32_t rx_fifo; +}; +#define mace_eth_read(r) \ + mace_read(mace->eth.r) +#define mace_eth_write(v,r) \ + mace_write(v,mace->eth.r) + + +/* + * Peripherals */ -#define MACEISA_INT_STAT (MACE_ISA_BASE + 0x00000014) -#define MACEISA_INT_MASK (MACE_ISA_BASE + 0x0000001c) -/* - * Bits in the status/mask registers - */ -#define MACEISA_AUDIO_SW_INT BIT (0) -#define MACEISA_AUDIO_SC_INT BIT (1) -#define MACEISA_AUDIO1_DMAT_INT BIT (2) -#define MACEISA_AUDIO1_OF_INT BIT (3) -#define MACEISA_AUDIO2_DMAT_INT BIT (4) -#define MACEISA_AUDIO2_MERR_INT BIT (5) -#define MACEISA_AUDIO3_DMAT_INT BIT (6) -#define MACEISA_AUDIO3_MERR_INT BIT (7) -#define MACEISA_RTC_INT BIT (8) -#define MACEISA_KEYB_INT BIT (9) -#define MACEISA_KEYB_POLL_INT BIT (10) -#define MACEISA_MOUSE_INT BIT (11) -#define MACEISA_MOUSE_POLL_INT BIT (12) -#define MACEISA_TIMER0_INT BIT (13) -#define MACEISA_TIMER1_INT BIT (14) -#define MACEISA_TIMER2_INT BIT (15) -#define MACEISA_PARALLEL_INT BIT (16) -#define MACEISA_PAR_CTXA_INT BIT (17) -#define MACEISA_PAR_CTXB_INT BIT (18) -#define MACEISA_PAR_MERR_INT BIT (19) -#define MACEISA_SERIAL1_INT BIT (20) -#define MACEISA_SERIAL1_TDMAT_INT BIT (21) -#define MACEISA_SERIAL1_TDMAPR_INT BIT (22) -#define MACEISA_SERIAL1_TDMAME_INT BIT (23) -#define MACEISA_SERIAL1_RDMAT_INT BIT (24) -#define MACEISA_SERIAL1_RDMAOR_INT BIT (25) -#define MACEISA_SERIAL2_INT BIT (26) -#define MACEISA_SERIAL2_TDMAT_INT BIT (27) -#define MACEISA_SERIAL2_TDMAPR_INT BIT (28) -#define MACEISA_SERIAL2_TDMAME_INT BIT (29) -#define MACEISA_SERIAL2_RDMAT_INT BIT (30) -#define MACEISA_SERIAL2_RDMAOR_INT BIT (31) - -#define MACEI2C_CONFIG MACE_I2C_BASE -#define MACEI2C_CONTROL (MACE_I2C_BASE|0x10) -#define MACEI2C_DATA (MACE_I2C_BASE|0x18) - -/* Bits for I2C_CONFIG */ +/* Audio registers */ +struct mace_audio { + mace32_t control; + mace32_t codec_control; /* codec status control */ + mace32_t codec_mask; /* codec status input mask */ + mace32_t codec_read; /* codec status read data */ + struct { + mace32_t control; /* channel control */ + mace32_t read_ptr; /* channel read pointer */ + mace32_t write_ptr; /* channel write pointer */ + mace32_t depth; /* channel depth */ + } channel[3]; +}; +#define mace_perif_audio_read(r) \ + mace_read(mace->perif.audio.r) +#define mace_perif_audio_write(v,r) \ + mace_write(v,mace->perif.audio.r) + +/* ISA Control and DMA registers */ +struct mace_isactrl { + mace32_t ringbase; +#define MACEISA_RINGBUFFERS_SIZE (8 * 4096) + + mace32_t misc; +#define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */ +#define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */ +#define MACEISA_NIC_DEASSERT BIT(2) +#define MACEISA_NIC_DATA BIT(3) +#define MACEISA_LED_RED BIT(4) /* 0=> Illuminate red LED */ +#define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate green LED */ +#define MACEISA_DP_RAM_ENABLE BIT(6) + + mace32_t istat; + mace32_t imask; +#define MACEISA_AUDIO_SW_INT BIT(0) +#define MACEISA_AUDIO_SC_INT BIT(1) +#define MACEISA_AUDIO1_DMAT_INT BIT(2) +#define MACEISA_AUDIO1_OF_INT BIT(3) +#define MACEISA_AUDIO2_DMAT_INT BIT(4) +#define MACEISA_AUDIO2_MERR_INT BIT(5) +#define MACEISA_AUDIO3_DMAT_INT BIT(6) +#define MACEISA_AUDIO3_MERR_INT BIT(7) +#define MACEISA_RTC_INT BIT(8) +#define MACEISA_KEYB_INT BIT(9) +#define MACEISA_KEYB_POLL_INT BIT(10) +#define MACEISA_MOUSE_INT BIT(11) +#define MACEISA_MOUSE_POLL_INT BIT(12) +#define MACEISA_TIMER0_INT BIT(13) +#define MACEISA_TIMER1_INT BIT(14) +#define MACEISA_TIMER2_INT BIT(15) +#define MACEISA_PARALLEL_INT BIT(16) +#define MACEISA_PAR_CTXA_INT BIT(17) +#define MACEISA_PAR_CTXB_INT BIT(18) +#define MACEISA_PAR_MERR_INT BIT(19) +#define MACEISA_SERIAL1_INT BIT(20) +#define MACEISA_SERIAL1_TDMAT_INT BIT(21) +#define MACEISA_SERIAL1_TDMAPR_INT BIT(22) +#define MACEISA_SERIAL1_TDMAME_INT BIT(23) +#define MACEISA_SERIAL1_RDMAT_INT BIT(24) +#define MACEISA_SERIAL1_RDMAOR_INT BIT(25) +#define MACEISA_SERIAL2_INT BIT(26) +#define MACEISA_SERIAL2_TDMAT_INT BIT(27) +#define MACEISA_SERIAL2_TDMAPR_INT BIT(28) +#define MACEISA_SERIAL2_TDMAME_INT BIT(29) +#define MACEISA_SERIAL2_RDMAT_INT BIT(30) +#define MACEISA_SERIAL2_RDMAOR_INT BIT(31) + + mace64_t _pad[0x2000/8 - 4]; + + mace64_t dp_ram[0x400]; +}; +#define mace_perif_ctrl_read(r) \ + mace_read(mace->perif.ctrl.r) +#define mace_perif_ctrl_write(v,r) \ + mace_write(v,mace->perif.ctrl.r) + +/* Keyboard & Mouse registers + * -> drivers/input/serio/maceps2.c */ +struct mace_ps2port { + mace32_t tx; + mace32_t rx; + mace32_t control; + mace32_t status; +}; + +struct mace_ps2 { + struct mace_ps2port keyb; + struct mace_ps2port mouse; +}; + +/* I2C registers + * -> drivers/i2c/algos/i2c-algo-sgi.c */ +struct mace_i2c { + mace32_t config; #define MACEI2C_RESET BIT(0) #define MACEI2C_FAST BIT(1) #define MACEI2C_DATA_OVERRIDE BIT(2) #define MACEI2C_CLOCK_OVERRIDE BIT(3) #define MACEI2C_DATA_STATUS BIT(4) #define MACEI2C_CLOCK_STATUS BIT(5) + mace32_t control; + mace32_t data; +}; + +/* Timer registers */ +typedef union { + mace64_t ust_msc; + struct reg { + volatile unsigned int ust; + volatile unsigned int msc; + } reg; +} timer_reg; + +struct mace_timers { + mace32_t ust; +#define MACE_UST_PERIOD_NS 960 + + mace32_t compare1; + mace32_t compare2; + mace32_t compare3; + + timer_reg audio_in; + timer_reg audio_out1; + timer_reg audio_out2; + timer_reg video_in1; + timer_reg video_in2; + timer_reg video_out; +}; + +struct mace_perif { + struct mace_audio audio; + char _pad0[0x10000 - sizeof(struct mace_audio)]; + + struct mace_isactrl ctrl; + char _pad1[0x10000 - sizeof(struct mace_isactrl)]; + + struct mace_ps2 ps2; + char _pad2[0x10000 - sizeof(struct mace_ps2)]; + + struct mace_i2c i2c; + char _pad3[0x10000 - sizeof(struct mace_i2c)]; + + struct mace_timers timers; + char _pad4[0x10000 - sizeof(struct mace_timers)]; +}; + + +/* + * ISA peripherals + */ -/* Bits for I2C_CONTROL */ -#define MACEI2C_NOT_IDLE BIT(0) /* write: 0=force idle - * read: 0=idle 1=not idle */ -#define MACEI2C_DIR BIT(1) /* 0=write 1=read */ -#define MACEI2C_MORE_BYTES BIT(2) /* 0=last byte 1=more bytes */ -#define MACEI2C_TRANS_BUSY BIT(4) /* 0=trans done 1=trans busy */ -#define MACEI2C_NACK BIT(5) /* 0=ack received 1=ack not */ -#define MACEI2C_BUS_ERROR BIT(7) /* 0=no bus err 1=bus err */ - - -#define MACEISA_AUDIO_INT (MACEISA_AUDIO_SW_INT | \ - MACEISA_AUDIO_SC_INT | \ - MACEISA_AUDIO1_DMAT_INT | \ - MACEISA_AUDIO1_OF_INT | \ - MACEISA_AUDIO2_DMAT_INT | \ - MACEISA_AUDIO2_MERR_INT | \ - MACEISA_AUDIO3_DMAT_INT | \ - MACEISA_AUDIO3_MERR_INT) -#define MACEISA_MISC_INT (MACEISA_RTC_INT | \ - MACEISA_KEYB_INT | \ - MACEISA_KEYB_POLL_INT | \ - MACEISA_MOUSE_INT | \ - MACEISA_MOUSE_POLL_INT | \ - MACEISA_TIMER0_INT | \ - MACEISA_TIMER1_INT | \ - MACEISA_TIMER2_INT) -#define MACEISA_SUPERIO_INT (MACEISA_PARALLEL_INT | \ - MACEISA_PAR_CTXA_INT | \ - MACEISA_PAR_CTXB_INT | \ - MACEISA_PAR_MERR_INT | \ - MACEISA_SERIAL1_INT | \ - MACEISA_SERIAL1_TDMAT_INT | \ - MACEISA_SERIAL1_TDMAPR_INT | \ - MACEISA_SERIAL1_TDMAME_INT | \ - MACEISA_SERIAL1_RDMAT_INT | \ - MACEISA_SERIAL1_RDMAOR_INT | \ - MACEISA_SERIAL2_INT | \ - MACEISA_SERIAL2_TDMAT_INT | \ - MACEISA_SERIAL2_TDMAPR_INT | \ - MACEISA_SERIAL2_TDMAME_INT | \ - MACEISA_SERIAL2_RDMAT_INT | \ - MACEISA_SERIAL2_RDMAOR_INT) - -#ifndef __ASSEMBLY__ -#include <asm/types.h> +/* Parallel port */ +struct mace_parallel { /* later... */ +}; -/* - * XXX Some of these are probably not needed (or even legal?) - */ -static inline u8 mace_read_8 (unsigned long __offset) -{ - return *((volatile u8 *) (MACE_BASE + __offset)); -} - -static inline u16 mace_read_16 (unsigned long __offset) -{ - return *((volatile u16 *) (MACE_BASE + __offset)); -} - -static inline u32 mace_read_32 (unsigned long __offset) -{ - return *((volatile u32 *) (MACE_BASE + __offset)); -} - -static inline u64 mace_read_64 (unsigned long __offset) -{ - return *((volatile u64 *) (MACE_BASE + __offset)); -} - -static inline void mace_write_8 (unsigned long __offset, u8 __val) -{ - *((volatile u8 *) (MACE_BASE + __offset)) = __val; -} - -static inline void mace_write_16 (unsigned long __offset, u16 __val) -{ - *((volatile u16 *) (MACE_BASE + __offset)) = __val; -} - -static inline void mace_write_32 (unsigned long __offset, u32 __val) -{ - *((volatile u32 *) (MACE_BASE + __offset)) = __val; -} - -static inline void mace_write_64 (unsigned long __offset, u64 __val) -{ - *((volatile u64 *) (MACE_BASE + __offset)) = __val; -} - -/* Call it whenever device needs to read data from main memory coherently */ -static inline void mace_inv_read_buffers(void) -{ -/* mace_write_32(MACEPCI_WFLUSH,0xffffffff);*/ -} -#endif /* !__ASSEMBLY__ */ +struct mace_ecp1284 { /* later... */ +}; + +/* Serial port */ +struct mace_serial { + mace64_t xxx; /* later... */ +}; + +struct mace_isa { + struct mace_parallel parallel; + char _pad1[0x8000 - sizeof(struct mace_parallel)]; + + struct mace_ecp1284 ecp1284; + char _pad2[0x8000 - sizeof(struct mace_ecp1284)]; + + struct mace_serial serial1; + char _pad3[0x8000 - sizeof(struct mace_serial)]; + + struct mace_serial serial2; + char _pad4[0x8000 - sizeof(struct mace_serial)]; + + mace32_t rtc[0x10000/8]; +}; + +struct sgi_mace { + char _reserved[0x80000]; + + struct mace_pci pci; + char _pad0[0x80000 - sizeof(struct mace_pci)]; + + struct mace_video video_in1; + char _pad1[0x80000 - sizeof(struct mace_video)]; + + struct mace_video video_in2; + char _pad2[0x80000 - sizeof(struct mace_video)]; + + struct mace_video video_out; + char _pad3[0x80000 - sizeof(struct mace_video)]; + + struct mace_ethernet eth; + char _pad4[0x80000 - sizeof(struct mace_ethernet)]; + + struct mace_perif perif; + char _pad5[0x80000 - sizeof(struct mace_perif)]; + + struct mace_isa isa; + char _pad6[0x80000 - sizeof(struct mace_isa)]; +}; +extern struct sgi_mace *mace; #endif /* __ASM_MACE_H__ */ diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 92001d3b4015..90b4ae1258a8 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h @@ -4,46 +4,14 @@ * for more details. * * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle - * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - * Copyright (C) 2001 Kanoj Sarcar + * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle */ #ifndef _ASM_IRQ_H #define _ASM_IRQ_H #include <linux/config.h> #include <linux/linkage.h> -#include <asm/sn/arch.h> - -#ifdef CONFIG_SGI_IP27 - -#define NR_IRQS 256 - -/* - * Number of levels in INT_PEND0. Can be set to 128 if we also - * consider INT_PEND1. - */ -#define PERNODE_LEVELS 64 - -extern int node_level_to_irq[MAX_COMPACT_NODES][PERNODE_LEVELS]; - -/* - * we need to map irq's up to at least bit 7 of the INT_MASK0_A register - * since bits 0-6 are pre-allocated for other purposes. - */ -#define LEAST_LEVEL 7 -#define FAST_IRQ_TO_LEVEL(i) ((i) + LEAST_LEVEL) -#define LEVEL_TO_IRQ(c, l) \ - (node_level_to_irq[CPUID_TO_COMPACT_NODEID(c)][(l)]) - -#else - -/* - * Largest number of ints of all machines except IP27 - */ -#define NR_IRQS 128 - -#endif +#include <irq.h> #ifdef CONFIG_I8259 static inline int irq_canonicalize(int irq) @@ -61,9 +29,6 @@ extern void enable_irq(unsigned int); struct pt_regs; extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs); -/* Machine specific interrupt initialization */ -extern void (*irq_setup)(void); - extern void init_generic_irq(void); #endif /* _ASM_IRQ_H */ diff --git a/include/asm-mips/irq_cpu.h b/include/asm-mips/irq_cpu.h index d49ec776024c..9dc44a1acbe5 100644 --- a/include/asm-mips/irq_cpu.h +++ b/include/asm-mips/irq_cpu.h @@ -14,5 +14,6 @@ #define _ASM_IRQ_CPU_H extern void mips_cpu_irq_init(int irq_base); +extern void rm7k_cpu_irq_init(int irq_base); #endif /* _ASM_IRQ_CPU_H */ diff --git a/include/asm-mips/jazz.h b/include/asm-mips/jazz.h index 5cbc7d0dd683..4e62ee69e219 100644 --- a/include/asm-mips/jazz.h +++ b/include/asm-mips/jazz.h @@ -203,7 +203,7 @@ typedef struct { * we remap the Jazz interrupts to the usual ISA style interrupt numbers. */ #define JAZZ_PARALLEL_IRQ 16 -#define JAZZ_FLOPPY_IRQ 6 /* needs to be consistent with floppy driver! */ +#define JAZZ_FLOPPY_IRQ 17 #define JAZZ_SOUND_IRQ 18 #define JAZZ_VIDEO_IRQ 19 #define JAZZ_ETHERNET_IRQ 20 @@ -283,27 +283,27 @@ __asm__ __volatile__( ".set\treorder"); } -static inline unsigned short r4030_read_reg16(unsigned addr) +static inline unsigned short r4030_read_reg16(unsigned long addr) { unsigned short ret = *((volatile unsigned short *)addr); r4030_delay(); return ret; } -static inline unsigned int r4030_read_reg32(unsigned addr) +static inline unsigned int r4030_read_reg32(unsigned long addr) { unsigned int ret = *((volatile unsigned int *)addr); r4030_delay(); return ret; } -static inline void r4030_write_reg16(unsigned addr, unsigned val) +static inline void r4030_write_reg16(unsigned long addr, unsigned val) { *((volatile unsigned short *)addr) = val; r4030_delay(); } -static inline void r4030_write_reg32(unsigned addr, unsigned val) +static inline void r4030_write_reg32(unsigned long addr, unsigned val) { *((volatile unsigned int *)addr) = val; r4030_delay(); diff --git a/include/asm-mips/jmr3927/ds1742rtc.h b/include/asm-mips/jmr3927/ds1742rtc.h deleted file mode 100644 index c7e06cde0a45..000000000000 --- a/include/asm-mips/jmr3927/ds1742rtc.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * ds1742rtc.h - register definitions for the Real-Time-Clock / CMOS RAM - * - * Based on include/asm-mips/ds1643rtc.h. - * - * Copyright (C) 1999-2001 Toshiba Corporation - * It was written to be part of the Linux operating system. - */ -/* permission is hereby granted to copy, modify and redistribute this code - * in terms of the GNU Library General Public License, Version 2 or later, - * at your option. - */ -#ifndef _DS1742RTC_H -#define _DS1742RTC_H - -#include <linux/rtc.h> -#include <asm/mc146818rtc.h> /* bad name... */ - -#define RTC_BRAM_SIZE 0x800 -#define RTC_OFFSET 0x7f8 - -/********************************************************************** - * register summary - **********************************************************************/ -#define RTC_CONTROL (RTC_OFFSET + 0) -#define RTC_CENTURY (RTC_OFFSET + 0) -#define RTC_SECONDS (RTC_OFFSET + 1) -#define RTC_MINUTES (RTC_OFFSET + 2) -#define RTC_HOURS (RTC_OFFSET + 3) -#define RTC_DAY (RTC_OFFSET + 4) -#define RTC_DATE (RTC_OFFSET + 5) -#define RTC_MONTH (RTC_OFFSET + 6) -#define RTC_YEAR (RTC_OFFSET + 7) - -#define RTC_CENTURY_MASK 0x3f -#define RTC_SECONDS_MASK 0x7f -#define RTC_DAY_MASK 0x07 - -/* - * Bits in the Control/Century register - */ -#define RTC_WRITE 0x80 -#define RTC_READ 0x40 - -/* - * Bits in the Seconds register - */ -#define RTC_STOP 0x80 - -/* - * Bits in the Day register - */ -#define RTC_BATT_FLAG 0x80 -#define RTC_FREQ_TEST 0x40 - -/* - * Conversion between binary and BCD. - */ -#ifndef BCD_TO_BIN -#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) -#endif - -#ifndef BIN_TO_BCD -#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) -#endif - -#endif /* _DS1742RTC_H */ diff --git a/include/asm-mips/jmr3927/pci.h b/include/asm-mips/jmr3927/pci.h deleted file mode 100644 index 4350e4704e10..000000000000 --- a/include/asm-mips/jmr3927/pci.h +++ /dev/null @@ -1,64 +0,0 @@ -/*********************************************************************** - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ahennessy@mvista.com - * - * include/asm-mips/jmr3927/pci.h - * Based on include/asm-mips/ddb5xxx/pci.h - * - * This file essentially defines the interface between board - * specific PCI code and MIPS common PCI code. Should potentially put - * into include/asm/pci.h file. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - *********************************************************************** - */ - -#ifndef __ASM_TX3927_PCI_H -#define __ASM_TX3927__PCI_H - -#include <linux/ioport.h> -#include <linux/pci.h> - -/* - * Each pci channel is a top-level PCI bus seem by CPU. A machine with - * multiple PCI channels may have multiple PCI host controllers or a - * single controller supporting multiple channels. - */ -struct pci_channel { - struct pci_ops *pci_ops; - struct resource *io_resource; - struct resource *mem_resource; -}; - -/* - * each board defines an array of pci_channels, that ends with all NULL entry - */ -extern struct pci_channel mips_pci_channels[]; - -/* - * board supplied pci irq fixup routine - */ -extern void pcibios_fixup_irqs(void); - -#endif /* __ASM_TX3927_PCI_H */ diff --git a/include/asm-mips/keyboard.h b/include/asm-mips/keyboard.h deleted file mode 100644 index b80dd875e71c..000000000000 --- a/include/asm-mips/keyboard.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999 Ralf Baechle - */ -#ifndef _ASM_KEYBOARD_H -#define _ASM_KEYBOARD_H - -#ifdef __KERNEL__ - -#include <linux/config.h> -#include <linux/delay.h> -#include <linux/ioport.h> -#include <linux/kd.h> -#include <linux/pm.h> - -#define DISABLE_KBD_DURING_INTERRUPTS 0 - -#ifdef CONFIG_PC_KEYB - -extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode); -extern int pckbd_getkeycode(unsigned int scancode); -extern int pckbd_translate(unsigned char scancode, unsigned char *keycode, - char raw_mode); -extern char pckbd_unexpected_up(unsigned char keycode); -extern void pckbd_leds(unsigned char leds); -extern void pckbd_init_hw(void); -extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *); -extern pm_callback pm_kbd_request_override; -extern unsigned char pckbd_sysrq_xlate[128]; -extern void kbd_forward_char (int ch); - -#define kbd_setkeycode pckbd_setkeycode -#define kbd_getkeycode pckbd_getkeycode -#define kbd_translate pckbd_translate -#define kbd_unexpected_up pckbd_unexpected_up -#define kbd_leds pckbd_leds -#define kbd_init_hw pckbd_init_hw -#define kbd_sysrq_xlate pckbd_sysrq_xlate - -#define SYSRQ_KEY 0x54 - -/* Some stoneage hardware needs delays after some operations. */ -#define kbd_pause() do { } while(0) - -struct kbd_ops { - /* Keyboard driver resource allocation */ - void (*kbd_request_region)(void); - int (*kbd_request_irq)(void (*handler)(int, void *, struct pt_regs *)); - - /* PSaux driver resource management */ - int (*aux_request_irq)(void (*handler)(int, void *, struct pt_regs *)); - void (*aux_free_irq)(void); - - /* Methods to access the keyboard processor's I/O registers */ - unsigned char (*kbd_read_input)(void); - void (*kbd_write_output)(unsigned char val); - void (*kbd_write_command)(unsigned char val); - unsigned char (*kbd_read_status)(void); -}; - -extern struct kbd_ops *kbd_ops; - -/* Do the actual calls via kbd_ops vector */ -#define kbd_request_region() kbd_ops->kbd_request_region() -#define kbd_request_irq(handler) kbd_ops->kbd_request_irq(handler) - -#define aux_request_irq(hand, dev_id) kbd_ops->aux_request_irq(hand) -#define aux_free_irq(dev_id) kbd_ops->aux_free_irq() - -#define kbd_read_input() kbd_ops->kbd_read_input() -#define kbd_write_output(val) kbd_ops->kbd_write_output(val) -#define kbd_write_command(val) kbd_ops->kbd_write_command(val) -#define kbd_read_status() kbd_ops->kbd_read_status() - -#else - -extern int kbd_setkeycode(unsigned int scancode, unsigned int keycode); -extern int kbd_getkeycode(unsigned int scancode); -extern int kbd_translate(unsigned char scancode, unsigned char *keycode, - char raw_mode); -extern char kbd_unexpected_up(unsigned char keycode); -extern void kbd_leds(unsigned char leds); -extern void kbd_init_hw(void); -extern unsigned char *kbd_sysrq_xlate; - -extern unsigned char kbd_sysrq_key; -#define SYSRQ_KEY kbd_sysrq_key - -#endif - -#endif /* __KERNEL */ - -#endif /* _ASM_KEYBOARD_H */ diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h new file mode 100644 index 000000000000..55166f4b7c64 --- /dev/null +++ b/include/asm-mips/mach-atlas/mc146818rtc.h @@ -0,0 +1,53 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2003 by Ralf Baechle + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#ifndef __ASM_MACH_ATLAS_MC146818RTC_H +#define __ASM_MACH_ATLAS_MC146818RTC_H + +#include <asm/io.h> +#include <asm/mips-boards/atlas.h> +#include <asm/mips-boards/atlasint.h> + + +#define RTC_PORT(x) (ATLAS_RTC_ADR_REG + (x)*8) +#define RTC_IOMAPPED 1 +#define RTC_EXTENT 16 +#define RTC_IRQ ATLASINT_RTC + +#if CONFIG_CPU_LITTLE_ENDIAN +#define ATLAS_RTC_PORT(x) (RTC_PORT(x) + 0) +#else +#define ATLAS_RTC_PORT(x) (RTC_PORT(x) + 3) +#endif + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + outb(addr, ATLAS_RTC_PORT(0)); + + return inb(ATLAS_RTC_PORT(1)); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + outb(addr, ATLAS_RTC_PORT(0)); + outb(data, ATLAS_RTC_PORT(1)); +} + +#define RTC_ALWAYS_BCD 0 + +#endif /* __ASM_MACH_ATLAS_MC146818RTC_H */ diff --git a/include/asm-mips/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index b0457b938ac9..8cb99b6a4e1c 100644 --- a/include/asm-mips/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -35,6 +35,8 @@ #ifndef _AU1000_H_ #define _AU1000_H_ +#ifndef _LANGUAGE_ASSEMBLY + #include <linux/delay.h> #include <asm/io.h> @@ -86,6 +88,47 @@ static inline u32 au_readl(unsigned long port) return (*(volatile u32 *)port); } +/* These next three functions should be a generic part of the MIPS + * kernel (with the 'au_' removed from the name) and selected for + * processors that support the instructions. + * Taken from PPC tree. -- Dan + */ +/* Return the bit position of the most significant 1 bit in a word */ +static __inline__ int __ilog2(unsigned int x) +{ + int lz; + + asm volatile ( + ".set\tnoreorder\n\t" + ".set\tnoat\n\t" + ".set\tmips32\n\t" + "clz\t%0,%1\n\t" + ".set\tmips0\n\t" + ".set\tat\n\t" + ".set\treorder" + : "=r" (lz) + : "r" (x)); + + return 31 - lz; +} + +static __inline__ int au_ffz(unsigned int x) +{ + if ((x = ~x) == 0) + return 32; + return __ilog2(x & -x); +} + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ +static __inline__ int au_ffs(int x) +{ + return __ilog2(x & -x) + 1; +} + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); @@ -94,6 +137,22 @@ extern unsigned long get_au1x00_uart_baud_base(void); extern void set_au1x00_lcd_clock(void); extern unsigned int get_au1x00_lcd_clock(void); +/* + * Every board describes its IRQ mapping with this table. + */ +typedef struct au1xxx_irqmap { + int im_irq; + int im_type; + int im_request; +} au1xxx_irq_map_t; + +/* + * init_IRQ looks for a table with this name. + */ +extern au1xxx_irq_map_t au1xxx_irq_map[]; + +#endif /* !defined (_LANGUAGE_ASSEMBLY) */ + #ifdef CONFIG_PM /* no CP0 timer irq */ #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) @@ -318,8 +377,56 @@ extern unsigned int get_au1x00_lcd_clock(void); #define AU1100_SD 2 #define AU1100_GPIO_208_215 29 -// REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE +// Seperate defines for AU1550 SOC +#define AU1550_UART0_INT AU1000_UART0_INT +#define AU1550_PCI_INTA AU1000_PCI_INTA +#define AU1550_PCI_INTB AU1000_PCI_INTB +#define AU1550_DDMA_INT 3 +#define AU1550_CRYPTO_INT 4 +#define AU1550_PCI_INTC 5 +#define AU1550_PCI_INTD 6 +#define AU1550_PCI_RST_INT 7 +#define AU1550_UART1_INT 8 +#define AU1550_UART3_INT 9 +#define AU1550_PSC0_INT 10 +#define AU1550_PSC1_INT 11 +#define AU1550_PSC2_INT 12 +#define AU1550_PSC3_INT 13 +#define AU1550_TOY_INT 14 +#define AU1550_TOY_MATCH0_INT 15 +#define AU1550_TOY_MATCH1_INT 16 +#define AU1550_TOY_MATCH2_INT 17 +#define AU1550_RTC_INT 18 +#define AU1550_RTC_MATCH0_INT 19 +#define AU1550_RTC_MATCH1_INT 20 +#define AU1550_RTC_MATCH2_INT 21 +#define AU1550_NAND_INT 23 +#define AU1550_USB_DEV_REQ_INT 24 +#define AU1550_USB_DEV_SUS_INT 25 +#define AU1550_USB_HOST_INT 26 +#define AU1550_MAC0_DMA_INT 27 +#define AU1550_MAC1_DMA_INT 28 +#define AU1550_ETH0_IRQ AU1550_MAC0_DMA_INT +#define AU1550_ETH1_IRQ AU1550_MAC1_DMA_INT + +#define AU1550_GPIO_200 48 +#define AU1500_GPIO_201_205 49 // Logical or of GPIO201:205 +#define AU1500_GPIO_16 50 +#define AU1500_GPIO_17 51 +#define AU1500_GPIO_20 52 +#define AU1500_GPIO_21 53 +#define AU1500_GPIO_22 54 +#define AU1500_GPIO_23 55 +#define AU1500_GPIO_24 56 +#define AU1500_GPIO_25 57 +#define AU1500_GPIO_26 58 +#define AU1500_GPIO_27 59 +#define AU1500_GPIO_28 60 +#define AU1500_GPIO_206 61 +#define AU1500_GPIO_207 62 +#define AU1500_GPIO_208_218 63 // Logical or of GPIO208:218 +// REDEFINE SECONDARY GPIO BLOCK INTO IC1 CONTROLLER HERE /* Programmable Counters 0 and 1 */ @@ -394,9 +501,15 @@ extern unsigned int get_au1x00_lcd_clock(void); /* USB Host Controller */ // We pass USB_OHCI_BASE to ioremap, so it needs to be a physical address +#if defined( CONFIG_SOC_AU1550 ) +#define USB_OHCI_BASE 0x14020000 +#define USB_OHCI_LEN 0x00100000 +#define USB_HOST_CONFIG 0xB4027ffc +#else #define USB_OHCI_BASE 0x10100000 #define USB_OHCI_LEN 0x00100000 #define USB_HOST_CONFIG 0xB017fffc +#endif /* USB Device Controller */ #define USBD_EP0RD 0xB0200000 @@ -446,6 +559,8 @@ extern unsigned int get_au1x00_lcd_clock(void); #define AU1500_ETH0_BASE 0xB1500000 #define AU1500_ETH1_BASE 0xB1510000 #define AU1100_ETH0_BASE 0xB0500000 +#define AU1550_ETH0_BASE 0xB0500000 +#define AU1550_ETH1_BASE 0xB0510000 /* 4 byte offsets from AU1000_ETH_BASE */ #define MAC_CONTROL 0x0 @@ -583,7 +698,7 @@ extern unsigned int get_au1x00_lcd_clock(void); #define UART2_ADDR 0xB1300000 #define UART3_ADDR 0xB1400000 #define UART_BASE UART0_ADDR -#define UART_DEBUG_BASE UART2_ADDR +#define UART_DEBUG_BASE UART3_ADDR #define UART_RX 0 /* Receive buffer */ #define UART_TX 4 /* Transmit buffer */ @@ -829,6 +944,13 @@ extern unsigned int get_au1x00_lcd_clock(void); #define SYS_PF_RD (1<<2) /* IRTXD/GPIO19 */ #define SYS_PF_A97 (1<<1) /* AC97/SSL1 */ #define SYS_PF_S0 (1<<0) /* SSI_0/GPIO[16:18] */ + +/* Au1100 Only */ + #define SYS_PF_PC (1<<18) /* PCMCIA/GPIO[207:204] */ + #define SYS_PF_LCD (1<<17) /* extern lcd/GPIO[203:200] */ + #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ + #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ + #define SYS_TRIOUTRD 0xB1900100 #define SYS_TRIOUTCLR 0xB1900100 #define SYS_OUTPUTRD 0xB1900108 @@ -840,9 +962,9 @@ extern unsigned int get_au1x00_lcd_clock(void); /* GPIO2, Au1500 only */ #define GPIO2_BASE 0xB1700000 #define GPIO2_DIR (GPIO2_BASE + 0) -#define GPIO2_DATA_EN (GPIO2_BASE + 8) -#define GPIO2_PIN_STATE (GPIO2_BASE + 0xC) -#define GPIO2_INT_ENABLE (GPIO2_BASE + 0x10) +#define GPIO2_OUTPUT (GPIO2_BASE + 8) +#define GPIO2_PINSTATE (GPIO2_BASE + 0xC) +#define GPIO2_INTENABLE (GPIO2_BASE + 0x10) #define GPIO2_ENABLE (GPIO2_BASE + 0x14) /* Power Management */ @@ -858,53 +980,53 @@ extern unsigned int get_au1x00_lcd_clock(void); /* Clock Controller */ #define SYS_FREQCTRL0 0xB1900020 #define SYS_FC_FRDIV2_BIT 22 - #define SYS_FC_FRDIV2_MASK (0xff << FQC2_FRDIV2_BIT) + #define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT) #define SYS_FC_FE2 (1<<21) #define SYS_FC_FS2 (1<<20) #define SYS_FC_FRDIV1_BIT 12 - #define SYS_FC_FRDIV1_MASK (0xff << FQC2_FRDIV1_BIT) + #define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT) #define SYS_FC_FE1 (1<<11) #define SYS_FC_FS1 (1<<10) #define SYS_FC_FRDIV0_BIT 2 - #define SYS_FC_FRDIV0_MASK (0xff << FQC2_FRDIV0_BIT) + #define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT) #define SYS_FC_FE0 (1<<1) #define SYS_FC_FS0 (1<<0) #define SYS_FREQCTRL1 0xB1900024 #define SYS_FC_FRDIV5_BIT 22 - #define SYS_FC_FRDIV5_MASK (0xff << FQC2_FRDIV5_BIT) + #define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT) #define SYS_FC_FE5 (1<<21) #define SYS_FC_FS5 (1<<20) #define SYS_FC_FRDIV4_BIT 12 - #define SYS_FC_FRDIV4_MASK (0xff << FQC2_FRDIV4_BIT) + #define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT) #define SYS_FC_FE4 (1<<11) #define SYS_FC_FS4 (1<<10) #define SYS_FC_FRDIV3_BIT 2 - #define SYS_FC_FRDIV3_MASK (0xff << FQC2_FRDIV3_BIT) + #define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT) #define SYS_FC_FE3 (1<<1) #define SYS_FC_FS3 (1<<0) #define SYS_CLKSRC 0xB1900028 #define SYS_CS_ME1_BIT 27 - #define SYS_CS_ME1_MASK (0x7<<CSC_ME1_BIT) + #define SYS_CS_ME1_MASK (0x7<<SYS_CS_ME1_BIT) #define SYS_CS_DE1 (1<<26) #define SYS_CS_CE1 (1<<25) #define SYS_CS_ME0_BIT 22 - #define SYS_CS_ME0_MASK (0x7<<CSC_ME0_BIT) + #define SYS_CS_ME0_MASK (0x7<<SYS_CS_ME0_BIT) #define SYS_CS_DE0 (1<<21) #define SYS_CS_CE0 (1<<20) #define SYS_CS_MI2_BIT 17 - #define SYS_CS_MI2_MASK (0x7<<CSC_MI2_BIT) + #define SYS_CS_MI2_MASK (0x7<<SYS_CS_MI2_BIT) #define SYS_CS_DI2 (1<<16) #define SYS_CS_CI2 (1<<15) #define SYS_CS_MUH_BIT 12 - #define SYS_CS_MUH_MASK (0x7<<CSC_MUH_BIT) + #define SYS_CS_MUH_MASK (0x7<<SYS_CS_MUH_BIT) #define SYS_CS_DUH (1<<11) #define SYS_CS_CUH (1<<10) #define SYS_CS_MUD_BIT 7 - #define SYS_CS_MUD_MASK (0x7<<CSC_MUD_BIT) + #define SYS_CS_MUD_MASK (0x7<<SYS_CS_MUD_BIT) #define SYS_CS_DUD (1<<6) #define SYS_CS_CUD (1<<5) #define SYS_CS_MIR_BIT 2 - #define SYS_CS_MIR_MASK (0x7<<CSC_MIR_BIT) + #define SYS_CS_MIR_MASK (0x7<<SYS_CS_MIR_BIT) #define SYS_CS_DIR (1<<1) #define SYS_CS_CIR (1<<0) @@ -949,7 +1071,7 @@ extern unsigned int get_au1x00_lcd_clock(void); #define AC97C_RS (1<<1) #define AC97C_CE (1<<0) -#ifdef CONFIG_SOC_AU1500 +#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) /* Au1500 PCI Controller */ #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0) @@ -983,7 +1105,7 @@ extern unsigned int get_au1x00_lcd_clock(void); #define Au1500_PCI_IO_START 0x500000000 #define Au1500_PCI_IO_END 0x5000FFFFF #define Au1500_PCI_MEM_START 0x440000000 -#define Au1500_PCI_MEM_END 0x443FFFFFF +#define Au1500_PCI_MEM_END 0x44FFFFFFF #define PCI_IO_START (Au1500_PCI_IO_START + 0x300) #define PCI_IO_END (Au1500_PCI_IO_END) @@ -992,9 +1114,27 @@ extern unsigned int get_au1x00_lcd_clock(void); #define PCI_FIRST_DEVFN (0<<3) #define PCI_LAST_DEVFN (19<<3) -#endif - -#if defined(CONFIG_SOC_AU1100) || (defined(CONFIG_SOC_AU1000) && !defined(CONFIG_MIPS_PB1000)) +#define IOPORT_RESOURCE_START 0x00000000 +#define IOPORT_RESOURCE_END 0xffffffff +#define IOMEM_RESOURCE_START 0x10000000 +#define IOMEM_RESOURCE_END 0xffffffff + +#else /* Au1000 and Au1100 */ + +/* don't allow any legacy ports probing */ +#define IOPORT_RESOURCE_START 0x10000000; +#define IOPORT_RESOURCE_END 0xffffffff +#define IOMEM_RESOURCE_START 0x10000000 +#define IOMEM_RESOURCE_END 0xffffffff + +#ifdef CONFIG_MIPS_PB1000 +#define PCI_IO_START 0x10000000 +#define PCI_IO_END 0x1000ffff +#define PCI_MEM_START 0x18000000 +#define PCI_MEM_END 0x18ffffff +#define PCI_FIRST_DEVFN 0 +#define PCI_LAST_DEVFN 1 +#else /* no PCI bus controller */ #define PCI_IO_START 0 #define PCI_IO_END 0 @@ -1005,3 +1145,11 @@ extern unsigned int get_au1x00_lcd_clock(void); #endif #endif + +#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) +#define NUM_ETH_INTERFACES 2 +#elif defined(CONFIG_SOC_AU1100) +#define NUM_ETH_INTERFACES 1 +#endif + +#endif diff --git a/include/asm-mips/au1000_dma.h b/include/asm-mips/mach-au1x00/au1000_dma.h index 06d80127f90b..02caee4eef6b 100644 --- a/include/asm-mips/au1000_dma.h +++ b/include/asm-mips/mach-au1x00/au1000_dma.h @@ -31,7 +31,6 @@ #ifndef __ASM_AU1000_DMA_H #define __ASM_AU1000_DMA_H -#include <linux/config.h> #include <asm/io.h> /* need byte IO */ #include <linux/spinlock.h> /* And spinlocks */ #include <linux/delay.h> @@ -114,7 +113,7 @@ struct dma_chan { extern struct dma_chan au1000_dma_table[]; extern int request_au1000_dma(int dev_id, const char *dev_str, - void (*irqhandler)(int, void *, + irqreturn_t (*irqhandler)(int, void *, struct pt_regs *), unsigned long irqflags, void *irq_dev_id); @@ -229,7 +228,7 @@ static __inline__ void init_dma(unsigned int dmanr) disable_dma(dmanr); // set device FIFO address - au_writel(PHYSADDR(chan->fifo_addr), + au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR); mode = chan->mode | (chan->dev_id << DMA_DID_BIT); @@ -290,7 +289,7 @@ static __inline__ void set_dma_fifo_addr(unsigned int dmanr, if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05) return; - au_writel(PHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR); + au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR); } /* diff --git a/include/asm-mips/au1000_gpio.h b/include/asm-mips/mach-au1x00/au1000_gpio.h index 298f92012e8e..298f92012e8e 100644 --- a/include/asm-mips/au1000_gpio.h +++ b/include/asm-mips/mach-au1x00/au1000_gpio.h diff --git a/include/asm-mips/au1000_pcmcia.h b/include/asm-mips/mach-au1x00/au1000_pcmcia.h index 2ba4f7bb19f7..4ba34a9be79f 100644 --- a/include/asm-mips/au1000_pcmcia.h +++ b/include/asm-mips/mach-au1x00/au1000_pcmcia.h @@ -1,13 +1,10 @@ /* - * * Alchemy Semi Au1000 pcmcia driver include file * * Copyright 2001 MontaVista Software Inc. * Author: MontaVista Software, Inc. * ppopov@mvista.com or source@mvista.com * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -20,14 +17,11 @@ * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * */ #ifndef __ASM_AU1000_PCMCIA_H #define __ASM_AU1000_PCMCIA_H +#include <linux/config.h> #define AU1000_PCMCIA_POLL_PERIOD (2*HZ) #define AU1000_PCMCIA_IO_SPEED (255) @@ -104,6 +98,8 @@ struct pcmcia_low_level { extern struct pcmcia_low_level pb1x00_pcmcia_ops; #elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) extern struct pcmcia_low_level db1x00_pcmcia_ops; +#elif defined(CONFIG_MIPS_XXS1500) +extern struct pcmcia_low_level xxs1500_pcmcia_ops; #else error unknown Au1000 board #endif diff --git a/include/asm-mips/au1000_usbdev.h b/include/asm-mips/mach-au1x00/au1000_usbdev.h index 05bc74bed0b1..05bc74bed0b1 100644 --- a/include/asm-mips/au1000_usbdev.h +++ b/include/asm-mips/mach-au1x00/au1000_usbdev.h diff --git a/include/asm-mips/mach-au1x00/timex.h b/include/asm-mips/mach-au1x00/timex.h new file mode 100644 index 000000000000..e3ada66cb636 --- /dev/null +++ b/include/asm-mips/mach-au1x00/timex.h @@ -0,0 +1,13 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_AU1X00_TIMEX_H +#define __ASM_MACH_AU1X00_TIMEX_H + +#define CLOCK_TICK_RATE ((HZ * 100000UL) / 2) + +#endif /* __ASM_MACH_AU1X00_TIMEX_H */ diff --git a/include/asm-mips/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h index 859614ae1edd..46247e2320b5 100644 --- a/include/asm-mips/db1x00.h +++ b/include/asm-mips/mach-db1x00/db1x00.h @@ -45,6 +45,7 @@ typedef volatile struct } BCSR; + /* * Register/mask bit definitions for the BCSRs */ @@ -75,6 +76,12 @@ typedef volatile struct #define BCSR_RESETS_PHY0 0x0001 #define BCSR_RESETS_PHY1 0x0002 #define BCSR_RESETS_DC 0x0004 +#define BCSR_RESETS_FIR_SEL 0x2000 +#define BCSR_RESETS_IRDA_MODE_MASK 0xC000 +#define BCSR_RESETS_IRDA_MODE_FULL 0x0000 +#define BCSR_RESETS_IRDA_MODE_OFF 0x4000 +#define BCSR_RESETS_IRDA_MODE_2_3 0x8000 +#define BCSR_RESETS_IRDA_MODE_1_3 0xC000 #define BCSR_PCMCIA_PC0VPP 0x0003 #define BCSR_PCMCIA_PC0VCC 0x000C diff --git a/include/asm-mips/mach-ddb5074/mc146818rtc.h b/include/asm-mips/mach-ddb5074/mc146818rtc.h new file mode 100644 index 000000000000..2eb9acb10a5a --- /dev/null +++ b/include/asm-mips/mach-ddb5074/mc146818rtc.h @@ -0,0 +1,31 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * + * RTC routines for PC style attached Dallas chip. + */ +#ifndef __ASM_MACH_DDB5074_MC146818RTC_H +#define __ASM_MACH_DDB5074_MC146818RTC_H + +#include <asm/ddb5xxx/ddb5074.h> +#include <asm/ddb5xxx/ddb5xxx.h> + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_IRQ 8 + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr) = data; +} + +#define RTC_ALWAYS_BCD 1 + +#endif /* __ASM_MACH_DDB5074_MC146818RTC_H */ diff --git a/include/asm-mips/mach-dec/mc146818rtc.h b/include/asm-mips/mach-dec/mc146818rtc.h new file mode 100644 index 000000000000..6fe8e9b54ea8 --- /dev/null +++ b/include/asm-mips/mach-dec/mc146818rtc.h @@ -0,0 +1,46 @@ +/* + * RTC definitions for DECstation style attached Dallas DS1287 chip. + * + * Copyright (C) 1998, 2001 by Ralf Baechle + * Copyright (C) 1998 by Harald Koerfgen + * Copyright (C) 2002 Maciej W. Rozycki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#ifndef __ASM_MIPS_DEC_RTC_DEC_H +#define __ASM_MIPS_DEC_RTC_DEC_H + +#include <linux/types.h> + +#include <asm/addrspace.h> + +extern volatile u8 *dec_rtc_base; +extern unsigned long dec_kn_slot_size; + +#define RTC_PORT(x) CPHYSADDR(dec_rtc_base) +#define RTC_IO_EXTENT dec_kn_slot_size +#define RTC_IOMAPPED 0 +#define RTC_IRQ 0 + +#define RTC_DEC_YEAR 0x3f /* Where we store the real year on DECs. */ + +#include <linux/mc146818rtc.h> +#include <linux/module.h> +#include <linux/types.h> + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + return dec_rtc_base[addr * 4]; +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + dec_rtc_base[addr * 4] = data; +} + +#define RTC_ALWAYS_BCD 0 + +#endif /* __ASM_MIPS_DEC_RTC_DEC_H */ diff --git a/include/asm-mips/mach-dec/param.h b/include/asm-mips/mach-dec/param.h new file mode 100644 index 000000000000..3e4f0e390847 --- /dev/null +++ b/include/asm-mips/mach-dec/param.h @@ -0,0 +1,18 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_DEC_PARAM_H +#define __ASM_MACH_DEC_PARAM_H + +/* + * log2(HZ), change this here if you want another HZ value. This is also + * used in dec_time_init. Minimum is 1, Maximum is 15. + */ +#define LOG_2_HZ 7 +#define HZ (1 << LOG_2_HZ) + +#endif /* __ASM_MACH_DEC_PARAM_H */ diff --git a/include/asm-mips/mach-ev64120/mach-gt64120.h b/include/asm-mips/mach-ev64120/mach-gt64120.h new file mode 100644 index 000000000000..0e5bc40772ea --- /dev/null +++ b/include/asm-mips/mach-ev64120/mach-gt64120.h @@ -0,0 +1,61 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef __ASM_GALILEO_BOARDS_MIPS_EV64120_H +#define __ASM_GALILEO_BOARDS_MIPS_EV64120_H + +/* + * GT64120 config space base address + */ +extern unsigned long gt64120_base; + +#define GT64120_BASE (gt64120_base) + +/* + * PCI Bus allocation + */ +#define GT_PCI_MEM_BASE 0x12000000UL +#define GT_PCI_MEM_SIZE 0x02000000UL +#define GT_PCI_IO_BASE 0x10000000UL +#define GT_PCI_IO_SIZE 0x02000000UL +#define GT_ISA_IO_BASE PCI_IO_BASE + +/* + * Duart I/O ports. + */ +#define EV64120_COM1_BASE_ADDR (0x1d000000 + 0x20) +#define EV64120_COM2_BASE_ADDR (0x1d000000 + 0x00) + + +/* + * EV64120 interrupt controller register base. + */ +#define EV64120_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) + +/* + * EV64120 UART register base. + */ +#define EV64120_UART0_REGS_BASE (KSEG1ADDR(EV64120_COM1_BASE_ADDR)) +#define EV64120_UART1_REGS_BASE (KSEG1ADDR(EV64120_COM2_BASE_ADDR)) +#define EV64120_BASE_BAUD ( 3686400 / 16 ) + +/* + * PCI interrupts will come in on either the INTA or INTD interrups lines, + * which are mapped to the #2 and #5 interrupt pins of the MIPS. On our + * boards, they all either come in on IntD or they all come in on IntA, they + * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the + * "requested" interrupt numbers and go through the list whenever we get an + * IntA/D. + * + * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and + * INTD is 11. + */ +#define GT_TIMER 4 +#define GT_INTA 2 +#define GT_INTD 5 + +#endif /* __ASM_GALILEO_BOARDS_MIPS_EV64120_H */ diff --git a/include/asm-mips/mach-ev96100/mach-gt64120.h b/include/asm-mips/mach-ev96100/mach-gt64120.h new file mode 100644 index 000000000000..54b4ffb33e9c --- /dev/null +++ b/include/asm-mips/mach-ev96100/mach-gt64120.h @@ -0,0 +1,46 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef _ASM_GT64120_EV96100_GT64120_DEP_H +#define _ASM_GT64120_EV96100_GT64120_DEP_H + +/* + * GT96100 config space base address + */ +#define GT64120_BASE (KSEG1ADDR(0x14000000)) + +/* + * PCI Bus allocation + * + * (Guessing ...) + */ +#define GT_PCI_MEM_BASE 0x12000000UL +#define GT_PCI_MEM_SIZE 0x02000000UL +#define GT_PCI_IO_BASE 0x10000000UL +#define GT_PCI_IO_SIZE 0x02000000UL +#define GT_ISA_IO_BASE PCI_IO_BASE + +/* + * Duart I/O ports. + */ +#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20) +#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00) + + +/* + * EV96100 interrupt controller register base. + */ +#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) + +/* + * EV96100 UART register base. + */ +#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR +#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR +#define EV96100_BASE_BAUD ( 3686400 / 16 ) + +#endif /* _ASM_GT64120_EV96100_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-generic/cpu-feature-overrides.h b/include/asm-mips/mach-generic/cpu-feature-overrides.h new file mode 100644 index 000000000000..0aecfd08e39a --- /dev/null +++ b/include/asm-mips/mach-generic/cpu-feature-overrides.h @@ -0,0 +1,13 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H + +/* Intensionally empty file ... */ + +#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-generic/floppy.h b/include/asm-mips/mach-generic/floppy.h new file mode 100644 index 000000000000..d47601392f0f --- /dev/null +++ b/include/asm-mips/mach-generic/floppy.h @@ -0,0 +1,140 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 1997, 1998, 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_FLOPPY_H +#define __ASM_MACH_GENERIC_FLOPPY_H + +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/linkage.h> +#include <linux/types.h> +#include <linux/mm.h> + +#include <asm/bootinfo.h> +#include <asm/cachectl.h> +#include <asm/dma.h> +#include <asm/floppy.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/pgtable.h> + +/* + * How to access the FDC's registers. + */ +static inline unsigned char fd_inb(unsigned int port) +{ + return inb_p(port); +} + +static inline void fd_outb(unsigned char value, unsigned int port) +{ + outb_p(value, port); +} + +/* + * How to access the floppy DMA functions. + */ +static inline void fd_enable_dma(void) +{ + enable_dma(FLOPPY_DMA); +} + +static inline void fd_disable_dma(void) +{ + disable_dma(FLOPPY_DMA); +} + +static inline int fd_request_dma(void) +{ + return request_dma(FLOPPY_DMA, "floppy"); +} + +static inline void fd_free_dma(void) +{ + free_dma(FLOPPY_DMA); +} + +static inline void fd_clear_dma_ff(void) +{ + clear_dma_ff(FLOPPY_DMA); +} + +static inline void fd_set_dma_mode(char mode) +{ + set_dma_mode(FLOPPY_DMA, mode); +} + +static inline void fd_set_dma_addr(char *addr) +{ + set_dma_addr(FLOPPY_DMA, (unsigned long) addr); +} + +static inline void fd_set_dma_count(unsigned int count) +{ + set_dma_count(FLOPPY_DMA, count); +} + +static inline int fd_get_dma_residue(void) +{ + return get_dma_residue(FLOPPY_DMA); +} + +static inline void fd_enable_irq(void) +{ + enable_irq(FLOPPY_IRQ); +} + +static inline void fd_disable_irq(void) +{ + disable_irq(FLOPPY_IRQ); +} + +static inline int fd_request_irq(void) +{ + return request_irq(FLOPPY_IRQ, floppy_interrupt, + SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL); +} + +static inline void fd_free_irq(void) +{ + free_irq(FLOPPY_IRQ, NULL); +} + +#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL); + + +static inline unsigned long fd_getfdaddr1(void) +{ + return 0x3f0; +} + +static inline unsigned long fd_dma_mem_alloc(unsigned long size) +{ + unsigned long mem; + + mem = __get_dma_pages(GFP_KERNEL, get_order(size)); + + return mem; +} + +static inline void fd_dma_mem_free(unsigned long addr, unsigned long size) +{ + free_pages(addr, get_order(size)); +} + +static inline unsigned long fd_drive_type(unsigned long n) +{ + if (n == 0) + return 4; /* 3,5", 1.44mb */ + + return 0; +} + +#endif /* __ASM_MACH_GENERIC_FLOPPY_H */ diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h new file mode 100644 index 000000000000..95a50fe448c2 --- /dev/null +++ b/include/asm-mips/mach-generic/ide.h @@ -0,0 +1,86 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * IDE routines for typical pc-like legacy IDE configurations. + * + * Copyright (C) 1998, 1999, 2001, 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_IDE_H +#define __ASM_MACH_GENERIC_IDE_H + +#include <linux/config.h> + +#ifndef MAX_HWIFS +# ifdef CONFIG_BLK_DEV_IDEPCI +#define MAX_HWIFS 10 +# else +#define MAX_HWIFS 6 +# endif +#endif + +static inline int ide_default_irq(unsigned long base) +{ + switch (base) { + case 0x1f0: return 14; + case 0x170: return 15; + case 0x1e8: return 11; + case 0x168: return 10; + case 0x1e0: return 8; + case 0x160: return 12; + default: + return 0; + } +} + +static inline ide_ioreg_t ide_default_io_base(int index) +{ + switch (index) { + case 0: return 0x1f0; + case 1: return 0x170; + case 2: return 0x1e8; + case 3: return 0x168; + case 4: return 0x1e0; + case 5: return 0x160; + default: + return 0; + } +} + +static inline void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, + unsigned long ctrl_port, int *irq) +{ + unsigned long reg = data_port; + int i; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) { + hw->io_ports[i] = reg; + reg += 1; + } + if (ctrl_port) { + hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; + } else { + hw->io_ports[IDE_CONTROL_OFFSET] = hw->io_ports[IDE_DATA_OFFSET] + 0x206; + } + if (irq != NULL) + *irq = 0; + hw->io_ports[IDE_IRQ_OFFSET] = 0; +} + +static inline void ide_init_default_hwifs(void) +{ +#ifndef CONFIG_BLK_DEV_IDEPCI + hw_regs_t hw; + int index; + + for(index = 0; index < MAX_HWIFS; index++) { + memset(&hw, 0, sizeof hw); + ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL); + hw.irq = ide_default_irq(ide_default_io_base(index)); + ide_register_hw(&hw, NULL); + } +#endif /* CONFIG_BLK_DEV_IDEPCI */ +} + +#endif /* __ASM_MACH_GENERIC_IDE_H */ diff --git a/include/asm-mips/mach-generic/irq.h b/include/asm-mips/mach-generic/irq.h new file mode 100644 index 000000000000..500e10ff24de --- /dev/null +++ b/include/asm-mips/mach-generic/irq.h @@ -0,0 +1,13 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_IRQ_H +#define __ASM_MACH_GENERIC_IRQ_H + +#define NR_IRQS 128 + +#endif /* __ASM_MACH_GENERIC_IRQ_H */ diff --git a/include/asm-mips/mach-generic/mangle-port.h b/include/asm-mips/mach-generic/mangle-port.h new file mode 100644 index 000000000000..ba82007a57a1 --- /dev/null +++ b/include/asm-mips/mach-generic/mangle-port.h @@ -0,0 +1,15 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H +#define __ASM_MACH_GENERIC_MANGLE_PORT_H + +#define __swizzle_addr_b(port) (port) +#define __swizzle_addr_w(port) (port) +#define __swizzle_addr_l(port) (port) + +#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-generic/mc146818rtc.h b/include/asm-mips/mach-generic/mc146818rtc.h new file mode 100644 index 000000000000..90c2e6f77faa --- /dev/null +++ b/include/asm-mips/mach-generic/mc146818rtc.h @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * + * RTC routines for PC style attached Dallas chip. + */ +#ifndef __ASM_MACH_GENERIC_MC146818RTC_H +#define __ASM_MACH_GENERIC_MC146818RTC_H + +#include <asm/io.h> + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_IRQ 8 + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + return inb_p(RTC_PORT(1)); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + outb_p(data, RTC_PORT(1)); +} + +#define RTC_ALWAYS_BCD 1 + +#ifndef mc146818_decode_year +#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) +#endif + +#endif /* __ASM_MACH_GENERIC_MC146818RTC_H */ diff --git a/include/asm-mips/mach-generic/param.h b/include/asm-mips/mach-generic/param.h new file mode 100644 index 000000000000..a0d12f964e4f --- /dev/null +++ b/include/asm-mips/mach-generic/param.h @@ -0,0 +1,13 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_PARAM_H +#define __ASM_MACH_GENERIC_PARAM_H + +#define HZ 1000 /* Internal kernel timer frequency */ + +#endif /* __ASM_MACH_GENERIC_PARAM_H */ diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h new file mode 100644 index 000000000000..e204dec688dd --- /dev/null +++ b/include/asm-mips/mach-generic/spaces.h @@ -0,0 +1,41 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 99 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. + */ +#ifndef _ASM_MACH_SPACES_H +#define _ASM_MACH_SPACES_H + +#include <linux/config.h> + +#ifdef CONFIG_MIPS32 + +#define CAC_BASE 0x80000000 +#define IO_BASE 0xa0000000 +#define UNCAC_BASE 0xa0000000 +#define MAP_BASE 0xc0000000 + +#endif /* CONFIG_MIPS32 */ + +#ifdef CONFIG_MIPS64 + +#ifdef CONFIG_DMA_NONCOHERENT +#define CAC_BASE 0x9800000000000000 +#else +#define CAC_BASE 0xa800000000000000 +#endif +#define IO_BASE 0x9000000000000000 +#define UNCAC_BASE 0x9000000000000000 +#define MAP_BASE 0xc000000000000000 + +#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) +#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) + +#endif /* CONFIG_MIPS64 */ + +#endif /* _ASM_MACH_SPACES_H */ diff --git a/include/asm-mips/mach-generic/timex.h b/include/asm-mips/mach-generic/timex.h new file mode 100644 index 000000000000..c6a2e5f0574a --- /dev/null +++ b/include/asm-mips/mach-generic/timex.h @@ -0,0 +1,22 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_GENERIC_TIMEX_H +#define __ASM_MACH_GENERIC_TIMEX_H + +#include <linux/config.h> + +/* + * Last remaining user of the i8254 PIC, will be converted, too ... + */ +#ifdef CONFIG_SNI_RM200_PCI +#define CLOCK_TICK_RATE 1193182 +#else +#define CLOCK_TICK_RATE 500000 +#endif + +#endif /* __ASM_MACH_GENERIC_TIMEX_H */ diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h new file mode 100644 index 000000000000..3c8896d9b133 --- /dev/null +++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H + +/* + * IP22 with a variety of processors so we can't use defaults for everything. + */ +#define cpu_has_mips16 0 +#define cpu_has_divec 0 +#define cpu_has_cache_cdex_p 1 +#define cpu_has_prefetch 0 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 /* Needs to change for R8000 */ +#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) +#define cpu_has_ic_fills_f_dc 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-ip22/ds1286.h b/include/asm-mips/mach-ip22/ds1286.h new file mode 100644 index 000000000000..f19f1eafbc71 --- /dev/null +++ b/include/asm-mips/mach-ip22/ds1286.h @@ -0,0 +1,18 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * + * RTC routines for PC style attached Dallas chip. + */ +#ifndef __ASM_MACH_IP22_DS1286_H +#define __ASM_MACH_IP22_DS1286_H + +#include <asm/sgi/hpc3.h> + +#define rtc_read(reg) (hpc3c0->rtcregs[(reg)] & 0xff) +#define rtc_write(data, reg) do { hpc3c0->rtcregs[(reg)] = (data); } while(0) + +#endif /* __ASM_MACH_IP22_DS1286_H */ diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h new file mode 100644 index 000000000000..771e5fcb7257 --- /dev/null +++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h @@ -0,0 +1,38 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H + +/* + * IP27 only comes with R10000 family processors all using the same config + */ +#define cpu_has_watch 1 +#define cpu_has_mips16 0 +#define cpu_has_divec 0 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_subset_pcaches 1 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 64 +#define cpu_scache_line_size() 128 + +#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-ip27/irq.h b/include/asm-mips/mach-ip27/irq.h new file mode 100644 index 000000000000..806213ce31b6 --- /dev/null +++ b/include/asm-mips/mach-ip27/irq.h @@ -0,0 +1,22 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999, 2000, 01, 02, 03 by Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Copyright (C) 2001 Kanoj Sarcar + */ +#ifndef __ASM_MACH_IP27_IRQ_H +#define __ASM_MACH_IP27_IRQ_H + +#include <asm/sn/arch.h> + +/* + * A hardwired interrupt number is completly stupid for this system - a + * large configuration might have thousands if not tenthousands of + * interrupts. + */ +#define NR_IRQS 256 + +#endif /* __ASM_MACH_IP27_IRQ_H */ diff --git a/include/asm-mips/mach-ip27/mangle-port.h b/include/asm-mips/mach-ip27/mangle-port.h new file mode 100644 index 000000000000..661995e769a5 --- /dev/null +++ b/include/asm-mips/mach-ip27/mangle-port.h @@ -0,0 +1,15 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ralf Baechle + */ +#ifndef __ASM_MACH_IP27_MANGLE_PORT_H +#define __ASM_MACH_IP27_MANGLE_PORT_H + +#define __swizzle_addr_b(port) (port) +#define __swizzle_addr_w(port) ((port) ^ 2) +#define __swizzle_addr_l(port) (port) + +#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-ip27/mmzone.h b/include/asm-mips/mach-ip27/mmzone.h new file mode 100644 index 000000000000..724d5dba8347 --- /dev/null +++ b/include/asm-mips/mach-ip27/mmzone.h @@ -0,0 +1,8 @@ +#ifndef _ASM_MACH_MMZONE_H +#define _ASM_MACH_MMZONE_H + +#include <asm/sn/addrs.h> + +#define pa_to_nid(addr) NASID_TO_COMPACT_NODEID(NASID_GET(addr)) + +#endif /* _ASM_MACH_MMZONE_H */ diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h new file mode 100644 index 000000000000..b3137a9a22de --- /dev/null +++ b/include/asm-mips/mach-ip27/spaces.h @@ -0,0 +1,30 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 99 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. + */ +#ifndef _ASM_MACH_SPACES_H +#define _ASM_MACH_SPACES_H + +/* + * IP27 uses the R10000's uncached attribute feature. Attribute 3 selects + * uncached memory addressing. + */ +#define CAC_BASE 0xa800000000000000 + +#define HSPEC_BASE 0x9000000000000000 +#define IO_BASE 0x9200000000000000 +#define MSPEC_BASE 0x9400000000000000 +#define UNCAC_BASE 0x9600000000000000 + +#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) +#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) + +#endif /* _ASM_MACH_SPACES_H */ diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/include/asm-mips/mach-ip32/mangle-port.h new file mode 100644 index 000000000000..6842af46eeff --- /dev/null +++ b/include/asm-mips/mach-ip32/mangle-port.h @@ -0,0 +1,15 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 Ladislav Michl + */ +#ifndef __ASM_MACH_IP32_MANGLE_PORT_H +#define __ASM_MACH_IP32_MANGLE_PORT_H + +#define __swizzle_addr_b(port) ((port) ^ 3) +#define __swizzle_addr_w(port) ((port) ^ 2) +#define __swizzle_addr_l(port) (port) + +#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */ diff --git a/include/asm-mips/mach-ip32/mc146818rtc.h b/include/asm-mips/mach-ip32/mc146818rtc.h new file mode 100644 index 000000000000..3d98e355111c --- /dev/null +++ b/include/asm-mips/mach-ip32/mc146818rtc.h @@ -0,0 +1,32 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * Copyright (C) 2000 Harald Koerfgen + * + * RTC routines for IP32 style attached Dallas chip. + */ +#ifndef __ASM_MACH_IP32_MC146818RTC_H +#define __ASM_MACH_IP32_MC146818RTC_H + +#include <asm/io.h> +#include <asm/ip32/mace.h> + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_IRQ MACEISA_RTC_IRQ + +static unsigned char CMOS_READ(unsigned long addr) +{ + return readb(mace->isa.rtc + addr); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + writeb(data, mace->isa.rtc + addr); +} + +#define RTC_ALWAYS_BCD 0 + +#endif /* __ASM_MACH_IP32_MC146818RTC_H */ diff --git a/include/asm-mips/mach-jazz/floppy.h b/include/asm-mips/mach-jazz/floppy.h new file mode 100644 index 000000000000..8cf0d042c864 --- /dev/null +++ b/include/asm-mips/mach-jazz/floppy.h @@ -0,0 +1,135 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_JAZZ_FLOPPY_H +#define __ASM_MACH_JAZZ_FLOPPY_H + +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/linkage.h> +#include <linux/types.h> +#include <linux/mm.h> +#include <asm/addrspace.h> +#include <asm/jazz.h> +#include <asm/jazzdma.h> +#include <asm/pgtable.h> + +static inline unsigned char fd_inb(unsigned int port) +{ + unsigned char c; + + c = *(volatile unsigned char *) port; + udelay(1); + + return c; +} + +static inline void fd_outb(unsigned char value, unsigned int port) +{ + *(volatile unsigned char *) port = value; +} + +/* + * How to access the floppy DMA functions. + */ +static inline void fd_enable_dma(void) +{ + vdma_enable(JAZZ_FLOPPY_DMA); +} + +static inline void fd_disable_dma(void) +{ + vdma_disable(JAZZ_FLOPPY_DMA); +} + +static inline int fd_request_dma(void) +{ + return 0; +} + +static inline void fd_free_dma(void) +{ +} + +static inline void fd_clear_dma_ff(void) +{ +} + +static inline void fd_set_dma_mode(char mode) +{ + vdma_set_mode(JAZZ_FLOPPY_DMA, mode); +} + +static inline void fd_set_dma_addr(char *a) +{ + vdma_set_addr(JAZZ_FLOPPY_DMA, vdma_phys2log(CPHYSADDR((unsigned long)a))); +} + +static inline void fd_set_dma_count(unsigned int count) +{ + vdma_set_count(JAZZ_FLOPPY_DMA, count); +} + +static inline int fd_get_dma_residue(void) +{ + return vdma_get_residue(JAZZ_FLOPPY_DMA); +} + +static inline void fd_enable_irq(void) +{ +} + +static inline void fd_disable_irq(void) +{ +} + +static inline int fd_request_irq(void) +{ + return request_irq(FLOPPY_IRQ, floppy_interrupt, + SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL); +} + +static inline void fd_free_irq(void) +{ + free_irq(FLOPPY_IRQ, NULL); +} + +static inline unsigned long fd_getfdaddr1(void) +{ + return JAZZ_FDC_BASE; +} + +static inline unsigned long fd_dma_mem_alloc(unsigned long size) +{ + unsigned long mem; + + mem = __get_dma_pages(GFP_KERNEL, get_order(size)); + if(!mem) + return 0; + vdma_alloc(CPHYSADDR(mem), size); /* XXX error checking */ + + return mem; +} + +static inline void fd_dma_mem_free(unsigned long addr, unsigned long size) +{ + vdma_free(vdma_phys2log(CPHYSADDR(addr))); + free_pages(addr, get_order(size)); +} + +static inline unsigned long fd_drive_type(unsigned long n) +{ + /* XXX This is wrong for machines with ED 2.88mb disk drives like the + Olivetti M700. Anyway, we should suck this from the ARC + firmware. */ + if (n == 0) + return 4; /* 3,5", 1.44mb */ + + return 0; +} + +#endif /* __ASM_MACH_JAZZ_FLOPPY_H */ diff --git a/include/asm-mips/mach-jazz/mc146818rtc.h b/include/asm-mips/mach-jazz/mc146818rtc.h new file mode 100644 index 000000000000..f44fdba1998b --- /dev/null +++ b/include/asm-mips/mach-jazz/mc146818rtc.h @@ -0,0 +1,34 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * + * RTC routines for Jazz style attached Dallas chip. + */ +#ifndef __ASM_MACH_JAZZ_MC146818RTC_H +#define __ASM_MACH_JAZZ_MC146818RTC_H + +#include <asm/io.h> +#include <asm/jazz.h> + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_IRQ 8 + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + + return *(char *)JAZZ_RTC_BASE; +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + *(char *)JAZZ_RTC_BASE = data; +} + +#define RTC_ALWAYS_BCD 0 + +#endif /* __ASM_MACH_JAZZ_MC146818RTC_H */ diff --git a/include/asm-mips/mach-jazz/param.h b/include/asm-mips/mach-jazz/param.h new file mode 100644 index 000000000000..639763a517bc --- /dev/null +++ b/include/asm-mips/mach-jazz/param.h @@ -0,0 +1,16 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_JAZZ_PARAM_H +#define __ASM_MACH_JAZZ_PARAM_H + +/* + * Jazz is currently using the internal 100Hz timer of the R4030 + */ +#define HZ 100 /* Internal kernel timer frequency */ + +#endif /* __ASM_MACH_JAZZ_PARAM_H */ diff --git a/include/asm-mips/mach-jazz/timex.h b/include/asm-mips/mach-jazz/timex.h new file mode 100644 index 000000000000..93affa33dfa8 --- /dev/null +++ b/include/asm-mips/mach-jazz/timex.h @@ -0,0 +1,16 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_JAZZ_TIMEX_H +#define __ASM_MACH_JAZZ_TIMEX_H + +/* + * Jazz is still using the R4030 100Hz counter + */ +#define CLOCK_TICK_RATE 100 + +#endif /* __ASM_MACH_JAZZ_TIMEX_H */ diff --git a/include/asm-mips/mach-jmr3927/asm/ds1742.h b/include/asm-mips/mach-jmr3927/asm/ds1742.h new file mode 100644 index 000000000000..134a4b6c334a --- /dev/null +++ b/include/asm-mips/mach-jmr3927/asm/ds1742.h @@ -0,0 +1,16 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_MACH_JMR3927_ASM_DS1742_H +#define __ASM_MACH_JMR3927_ASM_DS1742_H + +#include <asm/jmr3927/jmr3927.h> + +#define rtc_read(reg) (jmr3927_nvram_in(addr)) +#define rtc_write(data, reg) (jmr3927_nvram_out((data),(reg))) + +#endif /* __ASM_MACH_JMR3927_ASM_DS1742_H */ diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h new file mode 100644 index 000000000000..f7dc20f2f195 --- /dev/null +++ b/include/asm-mips/mach-lasat/mach-gt64120.h @@ -0,0 +1,27 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H +#define _ASM_GT64120_LASAT_GT64120_DEP_H + +/* + * GT64120 config space base address on Lasat 100 + */ +#define GT64120_BASE (KSEG1ADDR(0x14000000)) + +/* + * PCI Bus allocation + * + * (Guessing ...) + */ +#define GT_PCI_MEM_BASE 0x12000000UL +#define GT_PCI_MEM_SIZE 0x02000000UL +#define GT_PCI_IO_BASE 0x10000000UL +#define GT_PCI_IO_SIZE 0x02000000UL +#define GT_ISA_IO_BASE PCI_IO_BASE + +#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-mips/mach-gt64120.h new file mode 100644 index 000000000000..ea3661baa84d --- /dev/null +++ b/include/asm-mips/mach-mips/mach-gt64120.h @@ -0,0 +1,28 @@ +/* + * This is a direct copy of the ev96100.h file, with a global + * search and replace. The numbers are the same. + * + * The reason I'm duplicating this is so that the 64120/96100 + * defines won't be confusing in the source code. + */ +#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H +#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H + +#define MIPS_GT_BASE 0x1be00000 + +extern unsigned long _pcictrl_gt64120; +/* + * GT64120 config space base address + */ +#define GT64120_BASE _pcictrl_gt64120 + +/* + * PCI Bus allocation + */ +#define GT_PCI_MEM_BASE 0x12000000UL +#define GT_PCI_MEM_SIZE 0x02000000UL +#define GT_PCI_IO_BASE 0x10000000UL +#define GT_PCI_IO_SIZE 0x02000000UL +#define GT_ISA_IO_BASE PCI_IO_BASE + +#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-mips/mc146818rtc.h b/include/asm-mips/mach-mips/mc146818rtc.h new file mode 100644 index 000000000000..893ecf7cfb1c --- /dev/null +++ b/include/asm-mips/mach-mips/mc146818rtc.h @@ -0,0 +1,46 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Copyright (C) 2003 by Ralf Baechle + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * RTC routines for Malta style attached PIIX4 device, which contains a + * Motorola MC146818A-compatible Real Time Clock. + */ +#ifndef __ASM_MACH_MALTA_MC146818RTC_H +#define __ASM_MACH_MALTA_MC146818RTC_H + +#include <asm/io.h> +#include <asm/mips-boards/generic.h> +#include <asm/mips-boards/malta.h> + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_IRQ 8 + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + outb(addr, MALTA_RTC_ADR_REG); + return inb(MALTA_RTC_DAT_REG); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + outb(addr, MALTA_RTC_ADR_REG); + outb(data, MALTA_RTC_DAT_REG); +} + +#define RTC_ALWAYS_BCD 0 + +#endif /* __ASM_MACH_MALTA_MC146818RTC_H */ diff --git a/include/asm-mips/mach-ocelot/mach-gt64120.h b/include/asm-mips/mach-ocelot/mach-gt64120.h new file mode 100644 index 000000000000..c3ab0cb8592a --- /dev/null +++ b/include/asm-mips/mach-ocelot/mach-gt64120.h @@ -0,0 +1,30 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H +#define _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H + +/* + * PCI address allocation + */ +#define GT_PCI_MEM_BASE (0x22000000UL) +#define GT_PCI_MEM_SIZE GT_DEF_PCI0_MEM0_SIZE +#define GT_PCI_IO_BASE (0x20000000UL) +#define GT_PCI_IO_SIZE GT_DEF_PCI0_IO_SIZE + +extern unsigned long gt64120_base; + +#define GT64120_BASE (gt64120_base) + +/* + * GT timer irq + */ +#define GT_TIMER 6 + +#endif /* _ASM_GT64120_MOMENCO_OCELOT_GT64120_DEP_H */ diff --git a/include/asm-mips/mach-pb1x00/mc146818rtc.h b/include/asm-mips/mach-pb1x00/mc146818rtc.h new file mode 100644 index 000000000000..622c58710e5b --- /dev/null +++ b/include/asm-mips/mach-pb1x00/mc146818rtc.h @@ -0,0 +1,34 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 2001, 03 by Ralf Baechle + * + * RTC routines for PC style attached Dallas chip. + */ +#ifndef __ASM_MACH_AU1XX_MC146818RTC_H +#define __ASM_MACH_AU1XX_MC146818RTC_H + +#include <asm/io.h> +#include <asm/mach-au1x00/au1000.h> + +#define RTC_PORT(x) (0x0c000000 + (x)) +#define RTC_IRQ 8 +#define PB1500_RTC_ADDR 0x0c000000 + +static inline unsigned char CMOS_READ(unsigned long offset) +{ + offset <<= 2; + return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long offset) +{ + offset <<= 2; + au_writel(data, offset + PB1500_RTC_ADDR); +} + +#define RTC_ALWAYS_BCD 1 + +#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */ diff --git a/include/asm-mips/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h index 50c1e413a688..50c1e413a688 100644 --- a/include/asm-mips/pb1000.h +++ b/include/asm-mips/mach-pb1x00/pb1000.h diff --git a/include/asm-mips/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h index 4c5a1cd01841..4c5a1cd01841 100644 --- a/include/asm-mips/pb1100.h +++ b/include/asm-mips/mach-pb1x00/pb1100.h diff --git a/include/asm-mips/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h index d6c779747b3c..d6c779747b3c 100644 --- a/include/asm-mips/pb1500.h +++ b/include/asm-mips/mach-pb1x00/pb1500.h diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h new file mode 100644 index 000000000000..f48736032b2a --- /dev/null +++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h @@ -0,0 +1,42 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Ralf Baechle + * + * SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors. + */ +#ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H + +#include <cpu-feature-overrides.h> + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4ktlb 1 +#define cpu_has_fpu 1 +#define cpu_has_32fpr 1 +#define cpu_has_counter 1 +#define cpu_has_watch 0 +#define cpu_has_mips16 0 +#define cpu_has_divec 0 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 1 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 0 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_subset_pcaches 0 /* No S-cache on R5000 I think ... */ +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */ + +#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-rm200/mc146818rtc.h b/include/asm-mips/mach-rm200/mc146818rtc.h new file mode 100644 index 000000000000..d37ae68dc6a3 --- /dev/null +++ b/include/asm-mips/mach-rm200/mc146818rtc.h @@ -0,0 +1,17 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004 by Ralf Baechle + * + * RTC routines for PC style attached Dallas chip with ARC epoch. + */ +#ifndef __ASM_MACH_RM200_MC146818RTC_H +#define __ASM_MACH_RM200_MC146818RTC_H + +#define mc146818_decode_year(year) ((year) + 1980) + +#include_next <mc146818rtc.h> + +#endif /* __ASM_MACH_RM200_MC146818RTC_H */ diff --git a/include/asm-mips/mach-vr41xx/timex.h b/include/asm-mips/mach-vr41xx/timex.h new file mode 100644 index 000000000000..8d71485d003a --- /dev/null +++ b/include/asm-mips/mach-vr41xx/timex.h @@ -0,0 +1,18 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +/* + * Changes: + * Yoichi Yuasa <yuasa@hh.iij4u.or.jp> + * - CLOCK_TICK_RATE is changed into 32768 from 6144000. + */ +#ifndef __ASM_MACH_VR41XX_TIMEX_H +#define __ASM_MACH_VR41XX_TIMEX_H + +#define CLOCK_TICK_RATE 32768 + +#endif /* __ASM_MACH_VR41XX_TIMEX_H */ diff --git a/include/asm-mips/mc146818-time.h b/include/asm-mips/mc146818-time.h new file mode 100644 index 000000000000..5da4f3a12fc6 --- /dev/null +++ b/include/asm-mips/mc146818-time.h @@ -0,0 +1,129 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Machine dependent access functions for RTC registers. + */ +#ifndef __ASM_MC146818_TIME_H +#define __ASM_MC146818_TIME_H + +#include <linux/bcd.h> +#include <linux/mc146818rtc.h> +#include <linux/time.h> + +/* + * For check timing call set_rtc_mmss() 500ms; used in timer interrupt. + */ +#define USEC_AFTER 500000 +#define USEC_BEFORE 500000 + +/* + * In order to set the CMOS clock precisely, set_rtc_mmss has to be + * called 500 ms after the second nowtime has started, because when + * nowtime is written into the registers of the CMOS clock, it will + * jump to the next second precisely 500 ms later. Check the Motorola + * MC146818A or Dallas DS12887 data sheet for details. + * + * BUG: This routine does not handle hour overflow properly; it just + * sets the minutes. Usually you'll only notice that after reboot! + */ +static inline int mc146818_set_rtc_mmss(unsigned long nowtime) +{ + int real_seconds, real_minutes, cmos_minutes; + unsigned char save_control, save_freq_select; + int retval = 0; + + save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */ + CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL); + + save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */ + CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT); + + cmos_minutes = CMOS_READ(RTC_MINUTES); + if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) + BCD_TO_BIN(cmos_minutes); + + /* + * since we're only adjusting minutes and seconds, + * don't interfere with hour overflow. This avoids + * messing with unknown time zones but requires your + * RTC not to be off by more than 15 minutes + */ + real_seconds = nowtime % 60; + real_minutes = nowtime / 60; + if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) + real_minutes += 30; /* correct for half hour time zone */ + real_minutes %= 60; + + if (abs(real_minutes - cmos_minutes) < 30) { + if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { + BIN_TO_BCD(real_seconds); + BIN_TO_BCD(real_minutes); + } + CMOS_WRITE(real_seconds,RTC_SECONDS); + CMOS_WRITE(real_minutes,RTC_MINUTES); + } else { + printk(KERN_WARNING + "set_rtc_mmss: can't update from %d to %d\n", + cmos_minutes, real_minutes); + retval = -1; + } + + /* The following flags have to be released exactly in this order, + * otherwise the DS12887 (popular MC146818A clone with integrated + * battery and quartz) will not reset the oscillator and will not + * update precisely 500 ms later. You won't find this mentioned in + * the Dallas Semiconductor data sheets, but who believes data + * sheets anyway ... -- Markus Kuhn + */ + CMOS_WRITE(save_control, RTC_CONTROL); + CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); + + return retval; +} + +static inline unsigned long mc146818_get_cmos_time(void) +{ + unsigned int year, mon, day, hour, min, sec; + int i; + + /* + * The Linux interpretation of the CMOS clock register contents: + * When the Update-In-Progress (UIP) flag goes from 1 to 0, the + * RTC registers show the second which has precisely just started. + * Let's hope other operating systems interpret the RTC the same way. + */ + + /* read RTC exactly on falling edge of update flag */ + for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */ + if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP) + break; + for (i = 0 ; i < 1000000 ; i++) /* must try at least 2.228 ms */ + if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)) + break; + + do { /* Isn't this overkill ? UIP above should guarantee consistency */ + sec = CMOS_READ(RTC_SECONDS); + min = CMOS_READ(RTC_MINUTES); + hour = CMOS_READ(RTC_HOURS); + day = CMOS_READ(RTC_DAY_OF_MONTH); + mon = CMOS_READ(RTC_MONTH); + year = CMOS_READ(RTC_YEAR); + } while (sec != CMOS_READ(RTC_SECONDS)); + + if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { + BCD_TO_BIN(sec); + BCD_TO_BIN(min); + BCD_TO_BIN(hour); + BCD_TO_BIN(day); + BCD_TO_BIN(mon); + BCD_TO_BIN(year); + } + if ((year += 1900) < 1970) + year += 100; + + return mktime(year, mon, day, hour, min, sec); +} + +#endif /* __ASM_MC146818_TIME_H */ diff --git a/include/asm-mips/mc146818rtc.h b/include/asm-mips/mc146818rtc.h index cc6eeef7cbad..68b4da6d520b 100644 --- a/include/asm-mips/mc146818rtc.h +++ b/include/asm-mips/mc146818rtc.h @@ -11,56 +11,6 @@ #ifndef _ASM_MC146818RTC_H #define _ASM_MC146818RTC_H -#include <linux/config.h> - -#include <asm/io.h> - - -/* - * This structure defines how to access various features of - * different machine types and how to access them. - */ -struct rtc_ops { - /* How to access the RTC register in a DS1287. */ - unsigned char (*rtc_read_data)(unsigned long addr); - void (*rtc_write_data)(unsigned char data, unsigned long addr); - int (*rtc_bcd_mode)(void); -}; - -extern struct rtc_ops *rtc_ops; - -/* - * Most supported machines access the RTC index register via an ISA - * port access but the way to access the date register differs ... - * The DECstation directly maps the RTC memory in the CPU's address - * space with the chipset generating necessary index write/data access - * cycles automagically. - */ -#define CMOS_READ(addr) ({ \ -rtc_ops->rtc_read_data(addr); \ -}) -#define CMOS_WRITE(val, addr) ({ \ -rtc_ops->rtc_write_data(val, addr); \ -}) -#define RTC_ALWAYS_BCD \ -rtc_ops->rtc_bcd_mode() - - -#ifdef CONFIG_DECSTATION - -#include <asm/dec/rtc-dec.h> - -#elif defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_PB1100) - -#define RTC_PORT(x) (0x0c000000 + (x)) -#define RTC_IOMAPPED 0 -#define RTC_IRQ 0 - -#else - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_IRQ 8 - -#endif +#include <mc146818rtc.h> #endif /* _ASM_MC146818RTC_H */ diff --git a/include/asm-mips/mips-boards/atlas.h b/include/asm-mips/mips-boards/atlas.h index 07d2e6f1c144..0998151fb3a1 100644 --- a/include/asm-mips/mips-boards/atlas.h +++ b/include/asm-mips/mips-boards/atlas.h @@ -30,25 +30,25 @@ /* * Atlas RTC-device indirect register access. */ -#define ATLAS_RTC_ADR_REG (KSEG1ADDR(0x1f000800)) -#define ATLAS_RTC_DAT_REG (KSEG1ADDR(0x1f000808)) +#define ATLAS_RTC_ADR_REG 0x1f000800 +#define ATLAS_RTC_DAT_REG 0x1f000808 /* * Atlas interrupt controller register base. */ -#define ATLAS_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000)) +#define ATLAS_ICTRL_REGS_BASE 0x1f000000 /* * Atlas UART register base. */ -#define ATLAS_UART_REGS_BASE (0x1f000900) +#define ATLAS_UART_REGS_BASE 0x1f000900 #define ATLAS_BASE_BAUD ( 3686400 / 16 ) /* * Atlas PSU standby register. */ -#define ATLAS_PSUSTBY_REG (KSEG1ADDR(0x1f000600)) +#define ATLAS_PSUSTBY_REG 0x1f000600 #define ATLAS_GOSTBY 0x4d /* @@ -57,6 +57,8 @@ * This is not ideal, but is needed for setting up remote debugging as * soon as possible. */ -#define ATLAS_SAA9730_REG (KSEG1ADDR(0x08800000)) +#define ATLAS_SAA9730_REG 0x10800000 + +#define ATLAS_SAA9730_BAUDCLOCK 3692300 #endif /* !(_MIPS_ATLAS_H) */ diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h index 06ef8e9fe790..bba35c183d08 100644 --- a/include/asm-mips/mips-boards/atlasint.h +++ b/include/asm-mips/mips-boards/atlasint.h @@ -25,25 +25,58 @@ #ifndef _MIPS_ATLASINT_H #define _MIPS_ATLASINT_H -/* Number of IRQ supported on hw interrupt 0. */ -#define ATLASINT_UART 0 -#define ATLASINT_END 32 +#define ATLASINT_BASE 1 +#define ATLASINT_UART (ATLASINT_BASE+0) +#define ATLASINT_TIM0 (ATLASINT_BASE+1) +#define ATLASINT_RES2 (ATLASINT_BASE+2) +#define ATLASINT_RES3 (ATLASINT_BASE+3) +#define ATLASINT_RTC (ATLASINT_BASE+4) +#define ATLASINT_COREHI (ATLASINT_BASE+5) +#define ATLASINT_CORELO (ATLASINT_BASE+6) +#define ATLASINT_RES7 (ATLASINT_BASE+7) +#define ATLASINT_PCIA (ATLASINT_BASE+8) +#define ATLASINT_PCIB (ATLASINT_BASE+9) +#define ATLASINT_PCIC (ATLASINT_BASE+10) +#define ATLASINT_PCID (ATLASINT_BASE+11) +#define ATLASINT_ENUM (ATLASINT_BASE+12) +#define ATLASINT_DEG (ATLASINT_BASE+13) +#define ATLASINT_ATXFAIL (ATLASINT_BASE+14) +#define ATLASINT_INTA (ATLASINT_BASE+15) +#define ATLASINT_INTB (ATLASINT_BASE+16) +#define ATLASINT_ETH ATLASINT_INTB +#define ATLASINT_INTC (ATLASINT_BASE+17) +#define ATLASINT_SCSI ATLASINT_INTC +#define ATLASINT_INTD (ATLASINT_BASE+18) +#define ATLASINT_SERR (ATLASINT_BASE+19) +#define ATLASINT_RES20 (ATLASINT_BASE+20) +#define ATLASINT_RES21 (ATLASINT_BASE+21) +#define ATLASINT_RES22 (ATLASINT_BASE+22) +#define ATLASINT_RES23 (ATLASINT_BASE+23) +#define ATLASINT_RES24 (ATLASINT_BASE+24) +#define ATLASINT_RES25 (ATLASINT_BASE+25) +#define ATLASINT_RES26 (ATLASINT_BASE+26) +#define ATLASINT_RES27 (ATLASINT_BASE+27) +#define ATLASINT_RES28 (ATLASINT_BASE+28) +#define ATLASINT_RES29 (ATLASINT_BASE+29) +#define ATLASINT_RES30 (ATLASINT_BASE+30) +#define ATLASINT_RES31 (ATLASINT_BASE+31) +#define ATLASINT_END (ATLASINT_BASE+31) /* * Atlas registers are memory mapped on 64-bit aligned boundaries and * only word access are allowed. */ struct atlas_ictrl_regs { - volatile unsigned long intraw; - long dummy1; - volatile unsigned long intseten; - long dummy2; - volatile unsigned long intrsten; - long dummy3; - volatile unsigned long intenable; - long dummy4; - volatile unsigned long intstatus; - long dummy5; + volatile unsigned int intraw; + int dummy1; + volatile unsigned int intseten; + int dummy2; + volatile unsigned int intrsten; + int dummy3; + volatile unsigned int intenable; + int dummy4; + volatile unsigned int intstatus; + int dummy5; }; extern void atlasint_init(void); diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h index f2fdf9c4e9b6..cd7125610100 100644 --- a/include/asm-mips/mips-boards/bonito64.h +++ b/include/asm-mips/mips-boards/bonito64.h @@ -1,28 +1,18 @@ /* - * bonito.h - * - * Carsten Langgaard, carstenl@mips.com - * Copyright (C) 2001 MIPS Technologies, Inc. All rights reserved. - * - * ######################################################################## + * Bonito Register Map * * This file is the original bonito.h from Algorithmics with minor changes * to fit into linux. - */ - -/* - * Bonito Register Map + * * Copyright (c) 1999 Algorithmics Ltd * + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2001 MIPS Technologies, Inc. All rights reserved. + * * Algorithmics gives permission for anyone to use and modify this file * without any obligation or license condition except that you retain * this copyright message in any source redistribution in whole or part. * - * Updated copies of this and other files can be found at - * ftp://ftp.algor.co.uk/pub/bonito/ - * - * Users of the Bonito controller are warmly recommended to contribute - * any useful changes back to Algorithmics (mail to bonito@algor.co.uk). */ /* Revision 1.48 autogenerated on 08/17/99 15:20:01 */ @@ -38,9 +28,13 @@ #else /* !__ASSEMBLY__ */ -/* offsets from base pointer, this construct allows optimisation */ -/* static char * const _bonito = PA_TO_KVA1(BONITO_BASE); */ -#define BONITO(x) *(volatile u32 *)(_bonito + (x)) +/* + * Algorithmics Bonito64 system controller register base. + */ +extern unsigned long _pcictrl_bonito; +extern unsigned long _pcictrl_bonito_pcicfg; + +#define BONITO(x) *(volatile u32 *)(_pcictrl_bonito + (x)) #endif /* __ASSEMBLY__ */ @@ -312,6 +306,11 @@ #define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT 3 #define BONITO_PCICACHECTRL_CMDEXEC 0x00000020 +#define BONITO_PCICACHECTRL_IOBCCOH_PRES 0x00000100 +#define BONITO_PCICACHECTRL_IOBCCOH_EN 0x00000200 +#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400 +#define BONITO_PCICACHECTRL_CPUCOH_EN 0x00000800 + #define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001 #define BONITO_IODEVCFG_SPEEDBIT_CS0 0x00000002 #define BONITO_IODEVCFG_MOREABITS_CS0 0x00000004 diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h index ef146b32e609..65d1d16eab16 100644 --- a/include/asm-mips/mips-boards/generic.h +++ b/include/asm-mips/mips-boards/generic.h @@ -2,28 +2,23 @@ * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. * - * ######################################################################## + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * * Defines of the MIPS boards specific address-MAP, registers, etc. - * */ -#ifndef _MIPS_GENERIC_H -#define _MIPS_GENERIC_H +#ifndef __ASM_MIPS_BOARDS_GENERIC_H +#define __ASM_MIPS_BOARDS_GENERIC_H #include <linux/config.h> #include <asm/addrspace.h> @@ -33,79 +28,55 @@ /* * Display register base. */ -#if defined(CONFIG_MIPS_SEAD) -#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f0005c0)) +#ifdef CONFIG_MIPS_SEAD +#define ASCII_DISPLAY_POS_BASE 0x1f0005c0 #else -#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410)) -#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418)) +#define ASCII_DISPLAY_WORD_BASE 0x1f000410 +#define ASCII_DISPLAY_POS_BASE 0x1f000418 #endif /* * Yamon Prom print address. */ -#define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504)) +#define YAMON_PROM_PRINT_ADDR 0x1fc00504 /* * Reset register. */ -#if defined(CONFIG_MIPS_SEAD) -#define SOFTRES_REG (KSEG1ADDR(0x1e800050)) +#ifdef CONFIG_MIPS_SEAD +#define SOFTRES_REG 0x1e800050 #define GORESET 0x4d #else -#define SOFTRES_REG (KSEG1ADDR(0x1f000500)) +#define SOFTRES_REG 0x1f000500 #define GORESET 0x42 #endif /* * Revision register. */ -#define MIPS_REVISION_REG (KSEG1ADDR(0x1fc00010)) +#define MIPS_REVISION_REG 0x1fc00010 #define MIPS_REVISION_CORID_QED_RM5261 0 #define MIPS_REVISION_CORID_CORE_LV 1 #define MIPS_REVISION_CORID_BONITO64 2 #define MIPS_REVISION_CORID_CORE_20K 3 #define MIPS_REVISION_CORID_CORE_FPGA 4 #define MIPS_REVISION_CORID_CORE_MSC 5 +#define MIPS_REVISION_CORID_CORE_EMUL 6 +#define MIPS_REVISION_CORID_CORE_FPGA2 7 +#define MIPS_REVISION_CORID_CORE_FPGAR2 8 -#define MIPS_REVISION_CORID (((*(volatile u32 *)(MIPS_REVISION_REG)) >> 10) & 0x3f) - -extern unsigned int mips_revision_corid; - - +/**** Artificial corid defines ****/ /* - * Galileo GT64120 system controller register base. + * CoreEMUL with Bonito System Controller is treated like a Core20K + * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC */ -#define MIPS_GT_BASE (KSEG1ADDR(0x1be00000)) +#define MIPS_REVISION_CORID_CORE_EMUL_BON 0x63 +#define MIPS_REVISION_CORID_CORE_EMUL_MSC 0x65 -/* - * Because of the way the internal register works on the Galileo chip, - * we need to swap the bytes when running bigendian. - */ -#define GT_WRITE(ofs, data) \ - *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data) -#define GT_READ(ofs, data) \ - data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs)) +#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) -#define GT_PCI_WRITE(ofs, data) \ - *(volatile u32 *)(MIPS_GT_BASE+ofs) = data -#define GT_PCI_READ(ofs, data) \ - data = *(volatile u32 *)(MIPS_GT_BASE+ofs) - -/* - * Algorithmics Bonito64 system controller register base. - */ -static char * const _bonito = (char *)KSEG1ADDR(BONITO_REG_BASE); - -/* - * MIPS System controller PCI register base. - */ -#define MSC01_PCI_REG_BASE (KSEG1ADDR(0x1bd00000)) - -#define MSC_WRITE(reg, data) \ - *(volatile u32 *)(reg) = data -#define MSC_READ(reg, data) \ - data = *(volatile u32 *)(reg) +extern unsigned int mips_revision_corid; -#endif /* !(_MIPS_GENERIC_H) */ +#endif /* __ASM_MIPS_BOARDS_GENERIC_H */ diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h index 3e59db9ec6da..b0ba3c5a921e 100644 --- a/include/asm-mips/mips-boards/malta.h +++ b/include/asm-mips/mips-boards/malta.h @@ -17,33 +17,34 @@ * * Defines of the Malta board specific address-MAP, registers, etc. */ -#ifndef __ASM_MIPS_MALTA_H -#define __ASM_MIPS_MALTA_H +#ifndef __ASM_MIPS_BOARDS_MALTA_H +#define __ASM_MIPS_BOARDS_MALTA_H #include <asm/addrspace.h> -#include <asm/gt64120/gt64120.h> #include <asm/io.h> +#include <asm/mips-boards/msc01_pci.h> +#include <asm/gt64120.h> /* * Malta I/O ports base address for the Galileo GT64120 and Algorithmics * Bonito system controllers. */ #define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS) -#define MALTA_BONITO_PORT_BASE (KSEG1ADDR(0x1fd00000)) +#define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000)) #define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL) static inline unsigned long get_gt_port_base(unsigned long reg) { unsigned long addr; - GT_READ(reg, addr); - return KSEG1ADDR((addr & 0xffff) << 21); + addr = GT_READ(reg); + return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000); } static inline unsigned long get_msc_port_base(unsigned long reg) { unsigned long addr; MSC_READ(reg, addr); - return KSEG1ADDR(addr); + return (unsigned long) ioremap(addr, 0x10000); } /* @@ -69,6 +70,6 @@ static inline unsigned long get_msc_port_base(unsigned long reg) #define SMSC_WRITE(x,a) outb(x,a) -#define MALTA_JMPRS_REG (KSEG1ADDR(0x1f000210)) +#define MALTA_JMPRS_REG 0x1f000210 -#endif /* __ASM_MIPS_MALTA_H */ +#endif /* __ASM_MIPS_BOARDS_MALTA_H */ diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h index e9dce14de506..6b2a87a38f4b 100644 --- a/include/asm-mips/mips-boards/msc01_pci.h +++ b/include/asm-mips/mips-boards/msc01_pci.h @@ -1,19 +1,19 @@ /* - * mcs01_pci.h + * PCI Register definitions for the MIPS System Controller. * * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. * - * ######################################################################## - * - * PCI Register definitions for the MIPS System Controller. + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. */ -#ifndef MSC01_PCI_H -#define MSC01_PCI_H +#ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H +#define __ASM_MIPS_BOARDS_MSC01_PCI_H -/***************************************************************************** +/* * Register offset addresses - ****************************************************************************/ + */ #define MSC01_PCI_ID_OFS 0x0000 #define MSC01_PCI_SC2PMBASL_OFS 0x0208 @@ -200,9 +200,24 @@ #define MSC01_PCI_SWAP_NOSWAP 0 #define MSC01_PCI_SWAP_BYTESWAP 1 -/***************************************************************************** +/* + * MIPS System controller PCI register base. + * + * FIXME - are these macros specific to Malta and co or to the MSC? If the + * latter, they should be moved elsewhere. + */ +#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 + +extern unsigned long _pcictrl_msc; + +#define MSC01_PCI_REG_BASE _pcictrl_msc + +#define MSC_WRITE(reg, data) do { *(volatile u32 *)(reg) = data; } while (0) +#define MSC_READ(reg, data) do { data = *(volatile u32 *)(reg); } while (0) + +/* * Registers absolute addresses - ****************************************************************************/ + */ #define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS) #define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS) @@ -238,7 +253,4 @@ #define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS) #define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS) -#endif -/***************************************************************************** - * End of msc01_pci.h - *****************************************************************************/ +#endif /* __ASM_MIPS_BOARDS_MSC01_PCI_H */ diff --git a/include/asm-mips/mips-boards/piix4.h b/include/asm-mips/mips-boards/piix4.h index 1136314a7e3c..2971d60f2e95 100644 --- a/include/asm-mips/mips-boards/piix4.h +++ b/include/asm-mips/mips-boards/piix4.h @@ -2,8 +2,6 @@ * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -17,14 +15,10 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - * * Register definitions for Intel PIIX4 South Bridge Device. - * */ - -#ifndef PIIX4_H -#define PIIX4_H +#ifndef __ASM_MIPS_BOARDS_PIIX4_H +#define __ASM_MIPS_BOARDS_PIIX4_H /************************************************************************ * IO register offsets @@ -83,4 +77,4 @@ #define PIIX4_OCW3_IRR 0x2 #define PIIX4_OCW3_ISR 0x3 -#endif /* !(PIIX4_H) */ +#endif /* __ASM_MIPS_BOARDS_PIIX4_H */ diff --git a/include/asm-mips/mips-boards/prom.h b/include/asm-mips/mips-boards/prom.h index 78bdc2c76be2..4168c7fcd43e 100644 --- a/include/asm-mips/mips-boards/prom.h +++ b/include/asm-mips/mips-boards/prom.h @@ -2,6 +2,8 @@ * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. * + * ######################################################################## + * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -15,10 +17,14 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * + * ######################################################################## + * * MIPS boards bootprom interface for the Linux kernel. + * */ -#ifndef _ASM_MIPS_BOARDS_PROM_H -#define _ASM_MIPS_BOARDS_PROM_H + +#ifndef _MIPS_PROM_H +#define _MIPS_PROM_H extern char *prom_getcmdline(void); extern char *prom_getenv(char *name); @@ -27,7 +33,7 @@ extern void prom_printf(char *fmt, ...); extern void prom_init_cmdline(void); extern void prom_meminit(void); extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); -extern void prom_free_prom_memory (void); +extern unsigned long prom_free_prom_memory (void); extern void mips_display_message(const char *str); extern void mips_display_word(unsigned int num); extern int get_ethernet_addr(char *ethernet_addr); @@ -35,9 +41,9 @@ extern int get_ethernet_addr(char *ethernet_addr); /* Memory descriptor management. */ #define PROM_MAX_PMEMBLOCKS 32 struct prom_pmemblock { - unsigned long base; /* Phys addr. */ + unsigned long base; /* Within KSEG0. */ unsigned int size; /* In bytes. */ unsigned int type; /* free or prom memory */ }; -#endif /* _ASM_MIPS_BOARDS_PROM_H */ +#endif /* !(_MIPS_PROM_H) */ diff --git a/include/asm-mips/mips-boards/seadint.h b/include/asm-mips/mips-boards/seadint.h index 138ff0b24264..c3dcfcb928b6 100644 --- a/include/asm-mips/mips-boards/seadint.h +++ b/include/asm-mips/mips-boards/seadint.h @@ -2,8 +2,6 @@ * Carsten Langgaard, carstenl@mips.com * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. * - * ######################################################################## - * * This program is free software; you can distribute it and/or modify it * under the terms of the GNU General Public License (Version 2) as * published by the Free Software Foundation. @@ -17,18 +15,13 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. * - * ######################################################################## - * * Defines for the SEAD interrupt controller. - * */ #ifndef _MIPS_SEADINT_H #define _MIPS_SEADINT_H -/* Number of IRQ supported */ -#define SEADINT_UART0 0 -#define SEADINT_UART1 1 -#define SEADINT_END 2 +#define SEADINT_UART0 2 +#define SEADINT_UART1 3 extern void seadint_init(void); diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 62e7d85c393b..66f5d2e02ff2 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -15,6 +15,7 @@ #include <linux/config.h> #include <linux/linkage.h> +#include <asm/hazards.h> /* * The following macros are especially useful for __asm__ @@ -185,6 +186,20 @@ #endif /* + * Default page size for a given kernel configuration + */ +#ifdef CONFIG_PAGE_SIZE_4KB +#define PM_DEFAULT_MASK PM_4K +#elif defined(CONFIG_PAGE_SIZE_16KB) +#define PM_DEFAULT_MASK PM_16K +#elif defined(CONFIG_PAGE_SIZE_64KB) +#define PM_DEFAULT_MASK PM_64K +#else +#error Bad page size configuration! +#endif + + +/* * Values used for computation of new tlb entries */ #define PL_4K 12 @@ -578,13 +593,13 @@ do { \ if (sel == 0) \ __asm__ __volatile__( \ "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" (value)); \ + : : "Jr" ((unsigned int)value)); \ else \ __asm__ __volatile__( \ ".set\tmips32\n\t" \ "mtc0\t%z0, " #register ", " #sel "\n\t" \ ".set\tmips0" \ - : : "Jr" (value)); \ + : : "Jr" ((unsigned int)value)); \ } while (0) #define __write_64bit_c0_register(register, sel, value) \ @@ -821,37 +836,47 @@ do { \ : "=r" (__res)); \ __res;}) -/* TLB operations. */ +/* + * TLB operations. + */ static inline void tlb_probe(void) { + rm9000_tlb_hazard(); __asm__ __volatile__( ".set noreorder\n\t" "tlbp\n\t" ".set reorder"); + rm9000_tlb_hazard(); } static inline void tlb_read(void) { + rm9000_tlb_hazard(); __asm__ __volatile__( ".set noreorder\n\t" "tlbr\n\t" ".set reorder"); + rm9000_tlb_hazard(); } static inline void tlb_write_indexed(void) { + rm9000_tlb_hazard(); __asm__ __volatile__( ".set noreorder\n\t" "tlbwi\n\t" ".set reorder"); + rm9000_tlb_hazard(); } static inline void tlb_write_random(void) { + rm9000_tlb_hazard(); __asm__ __volatile__( ".set noreorder\n\t" "tlbwr\n\t" ".set reorder"); + rm9000_tlb_hazard(); } /* @@ -898,6 +923,7 @@ change_c0_##name(unsigned int change, unsigned int new) \ __BUILD_SET_C0(status,CP0_STATUS) __BUILD_SET_C0(cause,CP0_CAUSE) __BUILD_SET_C0(config,CP0_CONFIG) +__BUILD_SET_C0(intcontrol,CP0_CONFIG) #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h index db7ac0c7b7fc..79c40323a615 100644 --- a/include/asm-mips/mmu_context.h +++ b/include/asm-mips/mmu_context.h @@ -30,12 +30,12 @@ pgd_current[smp_processor_id()] = (unsigned long)(pgd) #ifdef CONFIG_MIPS32 #define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << (23 + 3)); \ + write_c0_context((unsigned long) smp_processor_id() << 23); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif #ifdef CONFIG_MIPS64 #define TLBMISS_HANDLER_SETUP() \ - write_c0_context((unsigned long) smp_processor_id() << 23); \ + write_c0_context((unsigned long) &pgd_current[smp_processor_id()] << 23); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif extern unsigned long pgd_current[]; diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h index 69cb153bb254..27ad26cb9fe9 100644 --- a/include/asm-mips/mmzone.h +++ b/include/asm-mips/mmzone.h @@ -1,94 +1,42 @@ /* * Written by Kanoj Sarcar (kanoj@sgi.com) Aug 99 + * Rewritten for Linux 2.6 by Christoph Hellwig (hch@lst.de) Jan 2004 */ #ifndef _ASM_MMZONE_H_ #define _ASM_MMZONE_H_ -#include <linux/config.h> -#include <asm/sn/types.h> -#include <asm/sn/addrs.h> -#include <asm/sn/arch.h> -#include <asm/sn/klkernvars.h> - -typedef struct plat_pglist_data { - pg_data_t gendata; - kern_vars_t kern_vars; -} plat_pg_data_t; - -/* - * Following are macros that are specific to this numa platform. - */ - -extern int numa_debug(void); -extern plat_pg_data_t *plat_node_data[]; - -#define PHYSADDR_TO_NID(pa) NASID_TO_COMPACT_NODEID(NASID_GET(pa)) -#define PLAT_NODE_DATA(n) (plat_node_data[n]) -#define PLAT_NODE_DATA_SIZE(n) (PLAT_NODE_DATA(n)->gendata.node_spanned_pages) -#define PLAT_NODE_DATA_LOCALNR(p, n) \ - (((p) >> PAGE_SHIFT) - PLAT_NODE_DATA(n)->gendata.node_start_pfn) - -#ifdef CONFIG_DISCONTIGMEM - -/* - * Following are macros that each numa implmentation must define. - */ - -/* - * Given a kernel address, find the home node of the underlying memory. - */ -#define KVADDR_TO_NID(kaddr) \ - ((NASID_TO_COMPACT_NODEID(NASID_GET(__pa(kaddr))) != -1) ? \ - (NASID_TO_COMPACT_NODEID(NASID_GET(__pa(kaddr)))) : \ - (printk("NUMABUG: %s line %d addr 0x%lx", __FILE__, __LINE__, kaddr), \ - numa_debug(), -1)) - -/* - * Return a pointer to the node data for node n. - */ -#define NODE_DATA(n) (&((PLAT_NODE_DATA(n))->gendata)) - -/* - * NODE_MEM_MAP gives the kaddr for the mem_map of the node. - */ -#define NODE_MEM_MAP(nid) (NODE_DATA(nid)->node_mem_map) - -/* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and returns the mem_map of that node. - */ -#define ADDR_TO_MAPBASE(kaddr) \ - NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr))) - -/* - * Given a kaddr, LOCAL_BASE_ADDR finds the owning node of the memory - * and returns the kaddr corresponding to first physical page in the - * node's mem_map. - */ -#define LOCAL_BASE_ADDR(kaddr) ((unsigned long)(kaddr) & ~(NODE_MAX_MEM_SIZE-1)) - -#define LOCAL_MAP_NR(kvaddr) \ - (((unsigned long)(kvaddr)-LOCAL_BASE_ADDR((kvaddr))) >> PAGE_SHIFT) - -#define MIPS64_NR(kaddr) (((unsigned long)(kaddr) > (unsigned long)high_memory)\ - ? (max_mapnr + 1) : (LOCAL_MAP_NR((kaddr)) + \ - (((unsigned long)ADDR_TO_MAPBASE((kaddr)) - PAGE_OFFSET) / \ - sizeof(struct page)))) +#include <asm/page.h> +#include <mmzone.h> + +extern struct pglist_data *node_data[]; + +#define NODE_DATA(n) (node_data[(n)]) +#define kvaddr_to_nid(kvaddr) pa_to_nid(__pa(kvaddr)) +#define pfn_to_nid(pfn) pa_to_nid((pfn) << PAGE_SHIFT) + +#define pfn_valid(pfn) \ +({ \ + unsigned long __pfn = (pfn); \ + int __n = pfn_to_nid(__pfn); \ + ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \ + NODE_DATA(__n)->node_spanned_pages) : 0);\ +}) + +#define pfn_to_page(pfn) \ +({ \ + unsigned long __pfn = (pfn); \ + pg_data_t *__pg = NODE_DATA(pfn_to_nid(__pfn)); \ + __pg->node_mem_map + (__pfn - __pg->node_start_pfn); \ +}) + +#define page_to_pfn(p) \ +({ \ + struct page *__p = (p); \ + struct zone *__z = page_zone(__p); \ + ((__p - __z->zone_mem_map) + __z->zone_start_pfn); \ +}) /* XXX: FIXME -- wli */ #define kern_addr_valid(addr) (0) -#define pfn_to_page(pfn) (mem_map + (pfn)) -#define page_to_pfn(page) \ - ((((page)-(page)->zone->zone_mem_map) + (page)->zone->zone_start_pfn) \ - << PAGE_SHIFT) -#define virt_to_page(kaddr) pfn_to_page(MIPS64_NR(kaddr)) - -#define pfn_valid(pfn) ((pfn) < max_mapnr) -#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) -#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) - -#endif /* CONFIG_DISCONTIGMEM */ - #endif /* _ASM_MMZONE_H_ */ diff --git a/include/asm-mips/msgbuf.h b/include/asm-mips/msgbuf.h index 1d4d90fb4a5e..513b2824838b 100644 --- a/include/asm-mips/msgbuf.h +++ b/include/asm-mips/msgbuf.h @@ -1,23 +1,41 @@ #ifndef _ASM_MSGBUF_H #define _ASM_MSGBUF_H +#include <linux/config.h> + /* - * The msqid64_ds structure for alpha architecture. + * The msqid64_ds structure for the MIPS architecture. * Note extra padding because this structure is passed back and forth * between kernel and user space. * * Pad space is left for: - * - 2 miscellaneous 64-bit values + * - extension of time_t to 64-bit on 32-bitsystem to solve the y2038 problem + * - 2 miscellaneous unsigned long values */ struct msqid64_ds { struct ipc64_perm msg_perm; +#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN) + unsigned long __unused1; +#endif __kernel_time_t msg_stime; /* last msgsnd time */ +#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused1; +#endif +#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN) + unsigned long __unused2; +#endif __kernel_time_t msg_rtime; /* last msgrcv time */ +#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused2; +#endif +#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN) + unsigned long __unused3; +#endif __kernel_time_t msg_ctime; /* last change time */ +#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN) unsigned long __unused3; +#endif unsigned long msg_cbytes; /* current number of bytes on queue */ unsigned long msg_qnum; /* number of messages in queue */ unsigned long msg_qbytes; /* max number of bytes on queue */ diff --git a/include/asm-mips/mv64340.h b/include/asm-mips/mv64340.h index d7d89bf0f6dc..13caa2fc663b 100644 --- a/include/asm-mips/mv64340.h +++ b/include/asm-mips/mv64340.h @@ -1,18 +1,17 @@ -/******************************************************************************* -* mv64340.h - MV-64340 Internal registers definition file. -* -* Copyright 2002 Momentum Computer, Inc. -* Copyright 2002 GALILEO TECHNOLOGY, LTD. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms of the GNU General Public License as published by the -* Free Software Foundation; either version 2 of the License, or (at your -* option) any later version. -* -*******************************************************************************/ - -#ifndef __MV64340_H__ -#define __MV64340_H__ +/* + * mv64340.h - MV-64340 Internal registers definition file. + * + * Copyright 2002 Momentum Computer, Inc. + * Copyright 2002 GALILEO TECHNOLOGY, LTD. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#ifndef __ASM_MV64340_H +#define __ASM_MV64340_H #include <asm/mv64340_dep.h> @@ -1034,4 +1033,9 @@ #define MV64340_SERIAL_INIT_CONTROL 0xf328 #define MV64340_SERIAL_INIT_STATUS 0xf32c -#endif +struct pci; + +extern mv64340_bus0_pci_ops; +extern mv64340_bus1_pci_ops; + +#endif /* __ASM_MV64340_H */ diff --git a/include/asm-mips/namei.h b/include/asm-mips/namei.h index 5f2308a4f628..c94d12d1f868 100644 --- a/include/asm-mips/namei.h +++ b/include/asm-mips/namei.h @@ -1,27 +1,26 @@ -/* - * Included from linux/fs/namei.c - */ #ifndef _ASM_NAMEI_H #define _ASM_NAMEI_H -#include <linux/config.h> +#include <linux/personality.h> +#include <linux/stddef.h> -/* Only one at this time. */ -#define IRIX32_EMUL "usr/gnemul/irix/" - -#ifdef CONFIG_BINFMT_IRIX +#define IRIX_EMUL "/usr/gnemul/irix/" +#define RISCOS_EMUL "/usr/gnemul/riscos/" static inline char *__emul_prefix(void) { - if (current->personality != PER_IRIX32) - return NULL; - return IRIX32_EMUL; -} + switch (current->personality) { + case PER_IRIX32: + case PER_IRIXN32: + case PER_IRIX64: + return IRIX_EMUL; -#else /* !defined(CONFIG_BINFMT_IRIX) */ + case PER_RISCOS: + return RISCOS_EMUL; -#define __emul_prefix() NULL - -#endif /* !defined(CONFIG_BINFMT_IRIX) */ + default: + return NULL; + } +} #endif /* _ASM_NAMEI_H */ diff --git a/include/asm-mips/numnodes.h b/include/asm-mips/numnodes.h new file mode 100644 index 000000000000..fceef695ea5d --- /dev/null +++ b/include/asm-mips/numnodes.h @@ -0,0 +1,7 @@ +#ifndef _ASM_MAX_NUMNODES_H +#define _ASM_MAX_NUMNODES_H + +/* Max 128 Nodes */ +#define NODES_SHIFT 7 + +#endif /* _ASM_MAX_NUMNODES_H */ diff --git a/include/asm-mips/page-32.h b/include/asm-mips/page-32.h index dcc4e0d047c0..ad1421de54c0 100644 --- a/include/asm-mips/page-32.h +++ b/include/asm-mips/page-32.h @@ -9,14 +9,11 @@ #ifndef _ASM_PAGE_32_H #define _ASM_PAGE_32_H -#include <linux/config.h> - /* * This handles the memory map. * We handle pages at KSEG0 for kernels with 32 bit address space. */ #define PAGE_OFFSET 0x80000000UL -#define UNCAC_BASE 0xa0000000UL /* * Memory above this physical address will be considered highmem. diff --git a/include/asm-mips/page-64.h b/include/asm-mips/page-64.h index 1581d26c8e31..d8e1591c23ea 100644 --- a/include/asm-mips/page-64.h +++ b/include/asm-mips/page-64.h @@ -14,13 +14,12 @@ /* * This handles the memory map. */ -#ifdef CONFIG_NONCOHERENT_IO +#ifdef CONFIG_DMA_NONCOHERENT #define PAGE_OFFSET 0x9800000000000000UL #else #define PAGE_OFFSET 0xa800000000000000UL #endif - /* * Memory above this physical address will be considered highmem. * Fixme: 59 bits is a fictive number and makes assumptions about processors diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 41e3beb9395e..6d2352350fa1 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -18,20 +18,27 @@ #include <asm/page-64.h> #endif -/* PAGE_SHIFT determines the page size */ +#ifdef __KERNEL__ + +/* + * PAGE_SHIFT determines the page size + */ +#ifdef CONFIG_PAGE_SIZE_4KB #define PAGE_SHIFT 12 +#endif +#ifdef CONFIG_PAGE_SIZE_16KB +#define PAGE_SHIFT 14 +#endif +#ifdef CONFIG_PAGE_SIZE_64KB +#define PAGE_SHIFT 16 +#endif #define PAGE_SIZE (1UL << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) -#ifdef __KERNEL__ - #ifndef __ASSEMBLY__ -extern void (*_clear_page)(void * page); -extern void (*_copy_page)(void * to, void * from); - -#define clear_page(addr) _clear_page((void *)(addr)) -#define copy_page(to, from) _copy_page((void *)(to), (void *)(from)) +extern void clear_page(void * page); +extern void copy_page(void * to, void * from); extern unsigned long shm_align_mask; @@ -114,12 +121,12 @@ static __inline__ int get_order(unsigned long size) #ifndef CONFIG_DISCONTIGMEM #define pfn_to_page(pfn) (mem_map + (pfn)) #define page_to_pfn(page) ((unsigned long)((page) - mem_map)) -#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) - #define pfn_valid(pfn) ((pfn) < max_mapnr) -#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) #endif +#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) +#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) + #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) diff --git a/include/asm-mips/param.h b/include/asm-mips/param.h index 47f0883b3724..2bead8273ced 100644 --- a/include/asm-mips/param.h +++ b/include/asm-mips/param.h @@ -11,18 +11,7 @@ #ifdef __KERNEL__ -#include <linux/config.h> - -#ifdef CONFIG_DECSTATION - /* - * log2(HZ), change this here if you want another HZ value. This is also - * used in dec_time_init. Minimum is 1, Maximum is 15. - */ -# define LOG_2_HZ 7 -# define HZ (1 << LOG_2_HZ) -#else -# define HZ 1000 /* Internal kernel timer frequency */ -#endif +# include <param.h> /* Internal kernel timer frequency */ # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ #endif @@ -31,7 +20,7 @@ #define HZ 100 #endif -#define EXEC_PAGESIZE 4096 +#define EXEC_PAGESIZE 65536 #ifndef NOGROUP #define NOGROUP (-1) diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 75a2b5536bb0..49783849fb72 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h @@ -15,20 +15,16 @@ already-configured bus numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the loader */ -#ifdef CONFIG_PCI extern unsigned int pcibios_assign_all_busses(void); -#else -#define pcibios_assign_all_busses() 0 -#endif + #define pcibios_scan_all_fns(a, b) 0 -#define PCIBIOS_MIN_IO 0x1000 -#define PCIBIOS_MIN_MEM 0x10000000 +extern unsigned long PCIBIOS_MIN_IO; +extern unsigned long PCIBIOS_MIN_MEM; -static inline void pcibios_set_master(struct pci_dev *dev) -{ - /* No special bus mastering setup handling */ -} +#define PCIBIOS_MIN_CARDBUS_IO 0x4000 + +extern void pcibios_set_master(struct pci_dev *dev); static inline void pcibios_penalize_isa_irq(int irq) { @@ -46,21 +42,14 @@ static inline void pcibios_penalize_isa_irq(int irq) #include <linux/string.h> #include <asm/io.h> -#if defined(CONFIG_DDB5074) || defined(CONFIG_DDB5476) -#undef PCIBIOS_MIN_IO -#undef PCIBIOS_MIN_MEM -#define PCIBIOS_MIN_IO 0x0100000 -#define PCIBIOS_MIN_MEM 0x1000000 -#endif - struct pci_dev; /* * The PCI address space does equal the physical memory address space. The * networking and block device layers use this boolean for bounce buffer - * decisions. + * decisions. This is set if any hose does not have an IOMMU. */ -#define PCI_DMA_BUS_IS_PHYS (1) +extern unsigned int PCI_DMA_BUS_IS_PHYS; #ifdef CONFIG_MAPPED_DMA_IO @@ -87,49 +76,22 @@ struct pci_dev; /* This is always fine. */ #define pci_dac_dma_supported(pci_dev, mask) (1) -static inline dma64_addr_t pci_dac_page_to_dma(struct pci_dev *pdev, - struct page *page, unsigned long offset, int direction) -{ - dma64_addr_t addr = page_to_phys(page) + offset; - - return (dma64_addr_t) bus_to_baddr(pdev->bus, addr); -} - -static inline struct page *pci_dac_dma_to_page(struct pci_dev *pdev, - dma64_addr_t dma_addr) -{ - unsigned long poff = baddr_to_bus(pdev->bus, dma_addr) >> PAGE_SHIFT; - - return mem_map + poff; -} - -static inline unsigned long pci_dac_dma_to_offset(struct pci_dev *pdev, - dma64_addr_t dma_addr) -{ - return dma_addr & ~PAGE_MASK; -} - -static inline void pci_dac_dma_sync_single(struct pci_dev *pdev, - dma64_addr_t dma_addr, size_t len, int direction) -{ - unsigned long addr; - - BUG_ON(direction == PCI_DMA_NONE); - - addr = baddr_to_bus(pdev->bus, dma_addr) + PAGE_OFFSET; - dma_cache_wback_inv(addr, len); -} - -static inline void pcibios_add_platform_entries(struct pci_dev *dev) -{ -} +extern dma64_addr_t pci_dac_page_to_dma(struct pci_dev *pdev, + struct page *page, unsigned long offset, int direction); +extern struct page *pci_dac_dma_to_page(struct pci_dev *pdev, + dma64_addr_t dma_addr); +extern unsigned long pci_dac_dma_to_offset(struct pci_dev *pdev, + dma64_addr_t dma_addr); +extern void pci_dac_dma_sync_single(struct pci_dev *pdev, + dma64_addr_t dma_addr, size_t len, int direction); #endif /* __KERNEL__ */ /* implement the pci_ DMA API in terms of the generic device dma_ one */ #include <asm-generic/pci-dma-compat.h> -/* generic pci stuff */ -#include <asm-generic/pci.h> +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} #endif /* _ASM_PCI_H */ diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h index 7d2545dcb8e7..c043f643fac6 100644 --- a/include/asm-mips/pci/bridge.h +++ b/include/asm-mips/pci/bridge.h @@ -13,6 +13,7 @@ #define _ASM_PCI_BRIDGE_H #include <linux/types.h> +#include <asm/pci_channel.h> #include <asm/xtalk/xwidget.h> /* generic widget header */ /* I/O page size */ @@ -388,9 +389,11 @@ typedef struct bridge_err_cmdword_s { /* Widget part number of bridge */ #define BRIDGE_WIDGET_PART_NUM 0xc002 +#define XBRIDGE_WIDGET_PART_NUM 0xd002 /* Manufacturer of bridge */ #define BRIDGE_WIDGET_MFGR_NUM 0x036 +#define XBRIDGE_WIDGET_MFGR_NUM 0x024 /* Revision numbers for known Bridge revisions */ #define BRIDGE_REV_A 0x1 @@ -827,11 +830,19 @@ typedef union ate_u { #define BRIDGE_INTERNAL_ATES 128 -/* - * Linux pci bus mappings to sn physical id's - */ -extern unsigned char bus_to_wid[]; /* widget id for linux pci bus */ -extern unsigned char bus_to_nid[]; /* nasid for linux pci bus */ -extern unsigned char num_bridges; /* number of bridges in the system */ + +struct bridge_controller { + struct pci_controller pc; + struct resource mem; + struct resource io; + bridge_t *base; + nasid_t nasid; + unsigned int widget_id; + unsigned int irq_cpu; + dma64_addr_t baddr; +}; + +#define BRIDGE_CONTROLLER(bus) \ + ((struct bridge_controller *)((bus)->sysdata)) #endif /* _ASM_PCI_BRIDGE_H */ diff --git a/include/asm-mips/pci_channel.h b/include/asm-mips/pci_channel.h index ce1ecaf2625b..a7cdb42fa8bd 100644 --- a/include/asm-mips/pci_channel.h +++ b/include/asm-mips/pci_channel.h @@ -15,27 +15,32 @@ * multiple PCI channels may have multiple PCI host controllers or a * single controller supporting multiple channels. */ -struct pci_channel { +struct pci_controller { + struct pci_controller *next; + struct pci_bus *bus; + struct pci_ops *pci_ops; - struct resource *io_resource; struct resource *mem_resource; - int first_devfn; - int last_devfn; + unsigned long mem_offset; + struct resource *io_resource; + unsigned long io_offset; + + /* For compatibility with current (as of July 2003) pciutils + and XFree86. Eventually will be removed. */ + unsigned int need_domain_info; + + int iommu; }; /* - * each board defines an array of pci_channels, that ends with all NULL entry + * Used by boards to register their PCI interfaces before the actual scanning. */ -extern struct pci_channel mips_pci_channels[]; +extern struct pci_controller * alloc_pci_controller(void); +extern void register_pci_controller(struct pci_controller *hose); /* * board supplied pci irq fixup routine */ -extern void pcibios_fixup_irqs(void); - -/* - * board supplied pci fixup routines - */ -extern void pcibios_fixup_resources(struct pci_dev *dev); +extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin); #endif /* __ASM_PCI_CHANNEL_H */ diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h index 7e27e2732d6d..3d133a6a3ffc 100644 --- a/include/asm-mips/pgalloc.h +++ b/include/asm-mips/pgalloc.h @@ -86,7 +86,6 @@ static inline void pte_free(struct page *pte) } #define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) -#define __pmd_free_tlb(tlb,x) do { } while (0) #ifdef CONFIG_MIPS32 #define pgd_populate(mm, pmd, pte) BUG() @@ -97,6 +96,7 @@ static inline void pte_free(struct page *pte) */ #define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); }) #define pmd_free(x) do { } while (0) +#define __pmd_free_tlb(tlb,x) do { } while (0) #endif #ifdef CONFIG_MIPS64 @@ -118,6 +118,8 @@ static inline void pmd_free(pmd_t *pmd) free_pages((unsigned long)pmd, PMD_ORDER); } +#define __pmd_free_tlb(tlb,x) pmd_free(x) + #endif /* diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h index 8914882f4ab9..8beb5f4f5c4c 100644 --- a/include/asm-mips/pgtable-32.h +++ b/include/asm-mips/pgtable-32.h @@ -60,21 +60,19 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, * we don't really have any PMD directory physically. */ #ifdef CONFIG_64BIT_PHYS_ADDR -#define PTRS_PER_PTE 512 -#define PTRS_PER_PMD 1 -#define PTRS_PER_PGD 2048 #define PGD_ORDER 1 #define PMD_ORDER 0 #define PTE_ORDER 0 #else -#define PTRS_PER_PTE 1024 -#define PTRS_PER_PMD 1 -#define PTRS_PER_PGD 1024 #define PGD_ORDER 0 #define PMD_ORDER 0 #define PTE_ORDER 0 #endif +#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) +#define PTRS_PER_PMD 1 +#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) + #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) #define FIRST_USER_PGD_NR 0 @@ -133,8 +131,15 @@ static inline int pgd_present(pgd_t pgd) { return 1; } static inline void pgd_clear(pgd_t *pgdp) { } #define pte_page(x) pfn_to_page(pte_pfn(x)) + + +#ifdef CONFIG_CPU_VR41XX +#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) +#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) +#else #define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#endif #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) @@ -195,9 +200,6 @@ static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address) #define pte_unmap(pte) ((void)(pte)) #define pte_unmap_nested(pte) ((void)(pte)) -extern pgd_t swapper_pg_dir[1024]; -extern void paging_init(void); - /* Swap entries must have VALID and GLOBAL bits cleared. */ #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h index 448a0d335f6e..0673441399be 100644 --- a/include/asm-mips/pgtable-64.h +++ b/include/asm-mips/pgtable-64.h @@ -10,13 +10,10 @@ #define _ASM_PGTABLE_64_H #include <linux/config.h> +#include <linux/linkage.h> + #include <asm/addrspace.h> #include <asm/page.h> - -#ifndef __ASSEMBLY__ - -#include <linux/linkage.h> -#include <linux/mmzone.h> #include <asm/cachectl.h> /* @@ -39,8 +36,6 @@ * vmalloc range translations, which the fault handler looks at. */ -#endif /* !__ASSEMBLY__ */ - /* PMD_SHIFT determines the size of the area a second-level page table can map */ #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3)) #define PMD_SIZE (1UL << PMD_SHIFT) @@ -51,14 +46,39 @@ #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) -/* Entries per page directory level: we use two-level, so we don't really - have any PMD directory physically. */ -#define PTRS_PER_PGD 1024 -#define PTRS_PER_PMD 1024 -#define PTRS_PER_PTE 512 +/* + * For 4kB page size we use a 3 level page tree and a 8kB pmd and pgds which + * permits us mapping 40 bits of virtual address space. + * + * We used to implement 41 bits by having an order 1 pmd level but that seemed + * rather pointless. + * + * For 16kB page size we use a 2 level page tree which permit a total of + * 36 bits of virtual address space. We could add a third leve. but it seems + * like at the moment there's no need for this. + * + * For 64kB page size we use a 2 level page table tree for a total of 42 bits + * of virtual address space. + */ +#ifdef CONFIG_PAGE_SIZE_4KB #define PGD_ORDER 1 #define PMD_ORDER 1 #define PTE_ORDER 0 +#endif +#ifdef CONFIG_PAGE_SIZE_16KB +#define PGD_ORDER 0 +#define PMD_ORDER 0 +#define PTE_ORDER 0 +#endif +#ifdef CONFIG_PAGE_SIZE_64KB +#define PGD_ORDER 0 +#define PMD_ORDER 0 +#define PTE_ORDER 0 +#endif + +#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) +#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t)) +#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) #define FIRST_USER_PGD_NR 0 @@ -67,8 +87,6 @@ #define VMALLOC_END \ (VMALLOC_START + ((1 << PGD_ORDER) * PTRS_PER_PTE * PAGE_SIZE)) -#ifndef __ASSEMBLY__ - #define pte_ERROR(e) \ printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e)) #define pmd_ERROR(e) \ @@ -121,13 +139,11 @@ static inline void pgd_clear(pgd_t *pgdp) pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table); } -#ifdef CONFIG_DISCONTIGMEM - -#define pte_page(x) (NODE_MEM_MAP(PHYSADDR_TO_NID(pte_val(x))) + \ - PLAT_NODE_DATA_LOCALNR(pte_val(x), PHYSADDR_TO_NID(pte_val(x)))) - +#define pte_page(x) pfn_to_page((unsigned long)((pte_val(x) >> PAGE_SHIFT))) +#ifdef CONFIG_CPU_VR41XX +#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) +#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) #else -#define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT))) #define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) #endif @@ -185,9 +201,6 @@ static inline pmd_t *pmd_offset(pgd_t * dir, unsigned long address) extern void pgd_init(unsigned long page); extern void pmd_init(unsigned long page, unsigned long pagetable); -extern pgd_t swapper_pg_dir[1024]; -extern void paging_init(void); - /* * Non-present pages: high 24 bits are offset, next 8 bits type, * low 32 bits zero. @@ -203,6 +216,4 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) typedef pte_t *pte_addr_t; -#endif /* !__ASSEMBLY__ */ - #endif /* _ASM_PGTABLE_64_H */ diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h index fd79206b2fae..22d19833a4b4 100644 --- a/include/asm-mips/pgtable-bits.h +++ b/include/asm-mips/pgtable-bits.h @@ -91,7 +91,7 @@ #ifdef CONFIG_MIPS_UNCACHED #define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED -#elif defined(CONFIG_NONCOHERENT_IO) +#elif defined(CONFIG_DMA_NONCOHERENT) #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT #else #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index d0add5ddacd7..5b2aa070cfa2 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -9,7 +9,6 @@ #define _ASM_PGTABLE_H #include <linux/config.h> - #ifdef CONFIG_MIPS32 #include <asm/pgtable-32.h> #endif @@ -67,6 +66,8 @@ extern unsigned long zero_page_mask; #define ZERO_PAGE(vaddr) \ (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))) +extern void paging_init(void); + /* * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. @@ -118,6 +119,11 @@ static inline void pte_clear(pte_t *ptep) #define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0) #define set_pgd(pgdptr, pgdval) do { *(pgdptr) = (pgdval); } while(0) +#define PGD_T_LOG2 ffz(~sizeof(pgd_t)) +#define PMD_T_LOG2 ffz(~sizeof(pmd_t)) +#define PTE_T_LOG2 ffz(~sizeof(pte_t)) + +extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; #define PTE_FILE_MAX_BITS 27 diff --git a/include/asm-mips/prefetch.h b/include/asm-mips/prefetch.h new file mode 100644 index 000000000000..799a8a69d394 --- /dev/null +++ b/include/asm-mips/prefetch.h @@ -0,0 +1,43 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_PREFETCH_H +#define __ASM_PREFETCH_H + +/* + * R5000 and RM5200 implements pref and prefx instructions but they're nops, so + * rather than wasting time we pretend these processors don't support + * prefetching at all. + * + * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained, + * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore. + * + * Hell (and the book on my shelf I can't open ...) know what the R8000 does. + * + * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements + * Pref_PrepareForStore also. + * + * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; + * it's Pref_WriteBackInvalidate is a nop. + * + * VR7701 only implements the Load prefetch. + * + * Finally MIPS32 and MIPS64 implement all of the following hints. + */ + +#define Pref_Load 0 +#define Pref_Store 1 + /* 2 and 3 are reserved */ +#define Pref_LoadStreamed 4 +#define Pref_StoreStreamed 5 +#define Pref_LoadRetained 6 +#define Pref_StoreRetained 7 + /* 8 ... 24 are reserved */ +#define Pref_WriteBackInvalidate 25 +#define Pref_PrepareForStore 30 + +#endif /* __ASM_PREFETCH_H */ diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 33e8cc7c721d..769719bee46a 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -12,21 +12,15 @@ #define _ASM_PROCESSOR_H #include <linux/config.h> - -/* - * Return current * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#ifndef __ASSEMBLY__ #include <linux/cache.h> #include <linux/threads.h> #include <asm/cachectl.h> +#include <asm/cpu.h> #include <asm/mipsregs.h> #include <asm/system.h> -#if defined(CONFIG_SGI_IP27) +#ifdef CONFIG_SGI_IP27 #include <asm/sn/types.h> #include <asm/sn/intr_public.h> #endif @@ -55,11 +49,11 @@ struct cpuinfo_mips { unsigned long udelay_val; unsigned long asid_cache; #if defined(CONFIG_SGI_IP27) - cpuid_t p_cpuid; /* PROM assigned cpuid */ +// cpuid_t p_cpuid; /* PROM assigned cpuid */ cnodeid_t p_nodeid; /* my node ID in compact-id-space */ nasid_t p_nasid; /* my node ID in numa-as-id-space */ unsigned char p_slice; /* Physical position on node board */ - hub_intmasks_t p_intmasks; /* SN0 per-CPU interrupt masks */ + struct hub_intmasks_s p_intmasks; /* SN0 per-CPU interrupt masks */ #endif #if 0 unsigned long loops_per_sec; @@ -85,40 +79,6 @@ struct cpuinfo_mips { struct cache_desc tcache; /* Tertiary/split secondary cache */ } __attribute__((aligned(SMP_CACHE_BYTES))); -/* - * Assumption: Options of CPU 0 are a superset of all processors. - * This is true for all known MIPS systems. - */ -#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) -#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) -#define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB) -#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU) -#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) -#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) -#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) -#define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16) -#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) -#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) -#define cpu_has_cache_cdex (cpu_data[0].options & MIPS_CPU_CACHE_CDEX) -#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) -#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) -/* no FPU exception; never set on 64-bit */ -#ifdef CONFIG_MIPS64 -#define cpu_has_nofpuex 0 -#else -#define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) -#endif -#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) -#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) -#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) -#define cpu_has_ic_fills_f_dc (cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC) -#ifdef CONFIG_MIPS64 -#define cpu_has_64bits 1 -#else -#define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) -#endif -#define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) - extern struct cpuinfo_mips cpu_data[]; #define current_cpu_data cpu_data[smp_processor_id()] @@ -126,6 +86,11 @@ extern void cpu_probe(void); extern void cpu_report(void); /* + * Return current * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +/* * System setup and hardware flags.. */ extern void (*cpu_wait)(void); @@ -244,8 +209,6 @@ struct thread_struct { #define MF_N32 MF_32BIT_ADDR #define MF_N64 0 -#endif /* !__ASSEMBLY__ */ - #define INIT_THREAD { \ /* \ * saved main processor registers \ @@ -271,7 +234,6 @@ struct thread_struct { } #ifdef __KERNEL__ -#ifndef __ASSEMBLY__ struct task_struct; @@ -300,7 +262,6 @@ unsigned long get_wchan(struct task_struct *p); #define cpu_relax() barrier() -#endif /* !__ASSEMBLY__ */ #endif /* __KERNEL__ */ /* @@ -317,4 +278,13 @@ unsigned long get_wchan(struct task_struct *p); */ #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);}) +/* + * For now. The 32-bit cycle counter is screwed up so solving this nicely takes a little + * brainwork ... + */ +static inline unsigned long long sched_clock(void) +{ + return 0ULL; +} + #endif /* _ASM_PROCESSOR_H */ diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index 4f816115db61..36df5fc7b37b 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h @@ -23,8 +23,6 @@ #define FPC_CSR 69 #define FPC_EIR 70 -#ifndef __ASSEMBLY__ - /* * This struct defines the way the registers are stored on the stack during a * system call/exception. As usual the registers k0/k1 aren't being saved. @@ -38,21 +36,15 @@ struct pt_regs { /* Saved main processor registers. */ unsigned long regs[32]; - /* Other saved registers. */ + /* Saved special registers. */ + unsigned long cp0_status; unsigned long lo; unsigned long hi; - - /* - * saved cp0 registers - */ - unsigned long cp0_epc; unsigned long cp0_badvaddr; - unsigned long cp0_status; unsigned long cp0_cause; + unsigned long cp0_epc; }; -#endif /* !__ASSEMBLY__ */ - /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ /* #define PTRACE_GETREGS 12 */ /* #define PTRACE_SETREGS 13 */ @@ -66,13 +58,8 @@ struct pt_regs { #define PTRACE_GET_THREAD_AREA 25 #define PTRACE_SET_THREAD_AREA 26 -#ifdef __ASSEMBLY__ -#include <asm/offset.h> -#endif - #ifdef __KERNEL__ -#ifndef __ASSEMBLY__ /* * Does the process account for user or for system time? */ @@ -81,7 +68,6 @@ struct pt_regs { #define instruction_pointer(regs) ((regs)->cp0_epc) extern void show_regs(struct pt_regs *); -#endif /* !__ASSEMBLY__ */ #endif diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h index 84aa8535bc2b..8a12fb6b07de 100644 --- a/include/asm-mips/r4kcache.h +++ b/include/asm-mips/r4kcache.h @@ -7,19 +7,33 @@ * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) */ -#ifndef __ASM_R4KCACHE_H -#define __ASM_R4KCACHE_H +#ifndef _ASM_R4KCACHE_H +#define _ASM_R4KCACHE_H #include <asm/asm.h> #include <asm/cacheops.h> +/* + * This macro return a properly sign-extended address suitable as base address + * for indexed cache operations. Two issues here: + * + * - The MIPS32 and MIPS64 specs permit an implementation to directly derive + * the index bits from the virtual address. This breaks with tradition + * set by the R4000. To keep unpleassant surprises from happening we pick + * an address in KSEG0 / CKSEG0. + * - We need a properly sign extended address for 64-bit code. To get away + * without ifdefs we let the compiler do it by a type cast. + */ +#define INDEX_BASE ((int) KSEG0) + #define cache_op(op,addr) \ __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3\n\t \n" \ - " cache %0, %1 \n" \ - " .set mips0 \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set mips0 \n" \ " .set reorder" \ : \ : "i" (op), "m" (*(unsigned char *)(addr))) @@ -111,35 +125,35 @@ static inline void invalidate_tcache_page(unsigned long addr) cache_op(Page_Invalidate_T, addr); } -#define cache16_unroll32(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, 0x000(%0); cache %1, 0x010(%0); \ - cache %1, 0x020(%0); cache %1, 0x030(%0); \ - cache %1, 0x040(%0); cache %1, 0x050(%0); \ - cache %1, 0x060(%0); cache %1, 0x070(%0); \ - cache %1, 0x080(%0); cache %1, 0x090(%0); \ - cache %1, 0x0a0(%0); cache %1, 0x0b0(%0); \ - cache %1, 0x0c0(%0); cache %1, 0x0d0(%0); \ - cache %1, 0x0e0(%0); cache %1, 0x0f0(%0); \ - cache %1, 0x100(%0); cache %1, 0x110(%0); \ - cache %1, 0x120(%0); cache %1, 0x130(%0); \ - cache %1, 0x140(%0); cache %1, 0x150(%0); \ - cache %1, 0x160(%0); cache %1, 0x170(%0); \ - cache %1, 0x180(%0); cache %1, 0x190(%0); \ - cache %1, 0x1a0(%0); cache %1, 0x1b0(%0); \ - cache %1, 0x1c0(%0); cache %1, 0x1d0(%0); \ - cache %1, 0x1e0(%0); cache %1, 0x1f0(%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ +#define cache16_unroll32(base,op) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ + " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ + " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ + " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ + " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ + " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ + " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ + " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ + " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ + " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ + " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ + " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ + " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ + " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ + " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ + " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ + " .set mips0 \n" \ + " .set reorder \n" \ + : \ + : "r" (base), \ "i" (op)); static inline void blast_dcache16(void) { - unsigned long start = KSEG0; + unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.dcache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; unsigned long ws_end = current_cpu_data.dcache.ways << @@ -156,10 +170,10 @@ static inline void blast_dcache16_page(unsigned long page) unsigned long start = page; unsigned long end = start + PAGE_SIZE; - while (start < end) { + do { cache16_unroll32(start,Hit_Writeback_Inv_D); start += 0x200; - } + } while (start < end); } static inline void blast_dcache16_page_indexed(unsigned long page) @@ -178,7 +192,7 @@ static inline void blast_dcache16_page_indexed(unsigned long page) static inline void blast_icache16(void) { - unsigned long start = KSEG0; + unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.icache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; unsigned long ws_end = current_cpu_data.icache.ways << @@ -195,10 +209,10 @@ static inline void blast_icache16_page(unsigned long page) unsigned long start = page; unsigned long end = start + PAGE_SIZE; - while (start < end) { + do { cache16_unroll32(start,Hit_Invalidate_I); start += 0x200; - } + } while (start < end); } static inline void blast_icache16_page_indexed(unsigned long page) @@ -217,7 +231,7 @@ static inline void blast_icache16_page_indexed(unsigned long page) static inline void blast_scache16(void) { - unsigned long start = KSEG0; + unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << @@ -234,10 +248,10 @@ static inline void blast_scache16_page(unsigned long page) unsigned long start = page; unsigned long end = page + PAGE_SIZE; - while (start < end) { + do { cache16_unroll32(start,Hit_Writeback_Inv_SD); start += 0x200; - } + } while (start < end); } static inline void blast_scache16_page_indexed(unsigned long page) @@ -254,35 +268,35 @@ static inline void blast_scache16_page_indexed(unsigned long page) cache16_unroll32(addr|ws,Index_Writeback_Inv_SD); } -#define cache32_unroll32(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, 0x000(%0); cache %1, 0x020(%0); \ - cache %1, 0x040(%0); cache %1, 0x060(%0); \ - cache %1, 0x080(%0); cache %1, 0x0a0(%0); \ - cache %1, 0x0c0(%0); cache %1, 0x0e0(%0); \ - cache %1, 0x100(%0); cache %1, 0x120(%0); \ - cache %1, 0x140(%0); cache %1, 0x160(%0); \ - cache %1, 0x180(%0); cache %1, 0x1a0(%0); \ - cache %1, 0x1c0(%0); cache %1, 0x1e0(%0); \ - cache %1, 0x200(%0); cache %1, 0x220(%0); \ - cache %1, 0x240(%0); cache %1, 0x260(%0); \ - cache %1, 0x280(%0); cache %1, 0x2a0(%0); \ - cache %1, 0x2c0(%0); cache %1, 0x2e0(%0); \ - cache %1, 0x300(%0); cache %1, 0x320(%0); \ - cache %1, 0x340(%0); cache %1, 0x360(%0); \ - cache %1, 0x380(%0); cache %1, 0x3a0(%0); \ - cache %1, 0x3c0(%0); cache %1, 0x3e0(%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ +#define cache32_unroll32(base,op) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0x000(%0); cache %1, 0x020(%0) \n" \ + " cache %1, 0x040(%0); cache %1, 0x060(%0) \n" \ + " cache %1, 0x080(%0); cache %1, 0x0a0(%0) \n" \ + " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0) \n" \ + " cache %1, 0x100(%0); cache %1, 0x120(%0) \n" \ + " cache %1, 0x140(%0); cache %1, 0x160(%0) \n" \ + " cache %1, 0x180(%0); cache %1, 0x1a0(%0) \n" \ + " cache %1, 0x1c0(%0); cache %1, 0x1e0(%0) \n" \ + " cache %1, 0x200(%0); cache %1, 0x220(%0) \n" \ + " cache %1, 0x240(%0); cache %1, 0x260(%0) \n" \ + " cache %1, 0x280(%0); cache %1, 0x2a0(%0) \n" \ + " cache %1, 0x2c0(%0); cache %1, 0x2e0(%0) \n" \ + " cache %1, 0x300(%0); cache %1, 0x320(%0) \n" \ + " cache %1, 0x340(%0); cache %1, 0x360(%0) \n" \ + " cache %1, 0x380(%0); cache %1, 0x3a0(%0) \n" \ + " cache %1, 0x3c0(%0); cache %1, 0x3e0(%0) \n" \ + " .set mips0 \n" \ + " .set reorder \n" \ + : \ + : "r" (base), \ "i" (op)); static inline void blast_dcache32(void) { - unsigned long start = KSEG0; + unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.dcache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit; unsigned long ws_end = current_cpu_data.dcache.ways << @@ -299,10 +313,10 @@ static inline void blast_dcache32_page(unsigned long page) unsigned long start = page; unsigned long end = start + PAGE_SIZE; - while (start < end) { + do { cache32_unroll32(start,Hit_Writeback_Inv_D); start += 0x400; - } + } while (start < end); } static inline void blast_dcache32_page_indexed(unsigned long page) @@ -321,7 +335,7 @@ static inline void blast_dcache32_page_indexed(unsigned long page) static inline void blast_icache32(void) { - unsigned long start = KSEG0; + unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.icache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; unsigned long ws_end = current_cpu_data.icache.ways << @@ -338,10 +352,10 @@ static inline void blast_icache32_page(unsigned long page) unsigned long start = page; unsigned long end = start + PAGE_SIZE; - while (start < end) { + do { cache32_unroll32(start,Hit_Invalidate_I); start += 0x400; - } + } while (start < end); } static inline void blast_icache32_page_indexed(unsigned long page) @@ -360,7 +374,7 @@ static inline void blast_icache32_page_indexed(unsigned long page) static inline void blast_scache32(void) { - unsigned long start = KSEG0; + unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << @@ -377,10 +391,10 @@ static inline void blast_scache32_page(unsigned long page) unsigned long start = page; unsigned long end = page + PAGE_SIZE; - while (start < end) { + do { cache32_unroll32(start,Hit_Writeback_Inv_SD); start += 0x400; - } + } while (start < end); } static inline void blast_scache32_page_indexed(unsigned long page) @@ -397,35 +411,35 @@ static inline void blast_scache32_page_indexed(unsigned long page) cache32_unroll32(addr|ws,Index_Writeback_Inv_SD); } -#define cache64_unroll32(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, 0x000(%0); cache %1, 0x040(%0); \ - cache %1, 0x080(%0); cache %1, 0x0c0(%0); \ - cache %1, 0x100(%0); cache %1, 0x140(%0); \ - cache %1, 0x180(%0); cache %1, 0x1c0(%0); \ - cache %1, 0x200(%0); cache %1, 0x240(%0); \ - cache %1, 0x280(%0); cache %1, 0x2c0(%0); \ - cache %1, 0x300(%0); cache %1, 0x340(%0); \ - cache %1, 0x380(%0); cache %1, 0x3c0(%0); \ - cache %1, 0x400(%0); cache %1, 0x440(%0); \ - cache %1, 0x480(%0); cache %1, 0x4c0(%0); \ - cache %1, 0x500(%0); cache %1, 0x540(%0); \ - cache %1, 0x580(%0); cache %1, 0x5c0(%0); \ - cache %1, 0x600(%0); cache %1, 0x640(%0); \ - cache %1, 0x680(%0); cache %1, 0x6c0(%0); \ - cache %1, 0x700(%0); cache %1, 0x740(%0); \ - cache %1, 0x780(%0); cache %1, 0x7c0(%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ +#define cache64_unroll32(base,op) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0x000(%0); cache %1, 0x040(%0) \n" \ + " cache %1, 0x080(%0); cache %1, 0x0c0(%0) \n" \ + " cache %1, 0x100(%0); cache %1, 0x140(%0) \n" \ + " cache %1, 0x180(%0); cache %1, 0x1c0(%0) \n" \ + " cache %1, 0x200(%0); cache %1, 0x240(%0) \n" \ + " cache %1, 0x280(%0); cache %1, 0x2c0(%0) \n" \ + " cache %1, 0x300(%0); cache %1, 0x340(%0) \n" \ + " cache %1, 0x380(%0); cache %1, 0x3c0(%0) \n" \ + " cache %1, 0x400(%0); cache %1, 0x440(%0) \n" \ + " cache %1, 0x480(%0); cache %1, 0x4c0(%0) \n" \ + " cache %1, 0x500(%0); cache %1, 0x540(%0) \n" \ + " cache %1, 0x580(%0); cache %1, 0x5c0(%0) \n" \ + " cache %1, 0x600(%0); cache %1, 0x640(%0) \n" \ + " cache %1, 0x680(%0); cache %1, 0x6c0(%0) \n" \ + " cache %1, 0x700(%0); cache %1, 0x740(%0) \n" \ + " cache %1, 0x780(%0); cache %1, 0x7c0(%0) \n" \ + " .set mips0 \n" \ + " .set reorder \n" \ + : \ + : "r" (base), \ "i" (op)); static inline void blast_icache64(void) { - unsigned long start = KSEG0; + unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.icache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; unsigned long ws_end = current_cpu_data.icache.ways << @@ -442,10 +456,10 @@ static inline void blast_icache64_page(unsigned long page) unsigned long start = page; unsigned long end = start + PAGE_SIZE; - while (start < end) { + do { cache64_unroll32(start,Hit_Invalidate_I); start += 0x800; - } + } while (start < end); } static inline void blast_icache64_page_indexed(unsigned long page) @@ -464,7 +478,7 @@ static inline void blast_icache64_page_indexed(unsigned long page) static inline void blast_scache64(void) { - unsigned long start = KSEG0; + unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << @@ -481,10 +495,10 @@ static inline void blast_scache64_page(unsigned long page) unsigned long start = page; unsigned long end = page + PAGE_SIZE; - while (start < end) { + do { cache64_unroll32(start,Hit_Writeback_Inv_SD); start += 0x800; - } + } while (start < end); } static inline void blast_scache64_page_indexed(unsigned long page) @@ -501,35 +515,35 @@ static inline void blast_scache64_page_indexed(unsigned long page) cache64_unroll32(addr|ws,Index_Writeback_Inv_SD); } -#define cache128_unroll32(base,op) \ - __asm__ __volatile__(" \ - .set noreorder; \ - .set mips3; \ - cache %1, 0x000(%0); cache %1, 0x080(%0); \ - cache %1, 0x100(%0); cache %1, 0x180(%0); \ - cache %1, 0x200(%0); cache %1, 0x280(%0); \ - cache %1, 0x300(%0); cache %1, 0x380(%0); \ - cache %1, 0x400(%0); cache %1, 0x480(%0); \ - cache %1, 0x500(%0); cache %1, 0x580(%0); \ - cache %1, 0x600(%0); cache %1, 0x680(%0); \ - cache %1, 0x700(%0); cache %1, 0x780(%0); \ - cache %1, 0x800(%0); cache %1, 0x880(%0); \ - cache %1, 0x900(%0); cache %1, 0x980(%0); \ - cache %1, 0xa00(%0); cache %1, 0xa80(%0); \ - cache %1, 0xb00(%0); cache %1, 0xb80(%0); \ - cache %1, 0xc00(%0); cache %1, 0xc80(%0); \ - cache %1, 0xd00(%0); cache %1, 0xd80(%0); \ - cache %1, 0xe00(%0); cache %1, 0xe80(%0); \ - cache %1, 0xf00(%0); cache %1, 0xf80(%0); \ - .set mips0; \ - .set reorder" \ - : \ - : "r" (base), \ +#define cache128_unroll32(base,op) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0x000(%0); cache %1, 0x080(%0) \n" \ + " cache %1, 0x100(%0); cache %1, 0x180(%0) \n" \ + " cache %1, 0x200(%0); cache %1, 0x280(%0) \n" \ + " cache %1, 0x300(%0); cache %1, 0x380(%0) \n" \ + " cache %1, 0x400(%0); cache %1, 0x480(%0) \n" \ + " cache %1, 0x500(%0); cache %1, 0x580(%0) \n" \ + " cache %1, 0x600(%0); cache %1, 0x680(%0) \n" \ + " cache %1, 0x700(%0); cache %1, 0x780(%0) \n" \ + " cache %1, 0x800(%0); cache %1, 0x880(%0) \n" \ + " cache %1, 0x900(%0); cache %1, 0x980(%0) \n" \ + " cache %1, 0xa00(%0); cache %1, 0xa80(%0) \n" \ + " cache %1, 0xb00(%0); cache %1, 0xb80(%0) \n" \ + " cache %1, 0xc00(%0); cache %1, 0xc80(%0) \n" \ + " cache %1, 0xd00(%0); cache %1, 0xd80(%0) \n" \ + " cache %1, 0xe00(%0); cache %1, 0xe80(%0) \n" \ + " cache %1, 0xf00(%0); cache %1, 0xf80(%0) \n" \ + " .set mips0 \n" \ + " .set reorder \n" \ + : \ + : "r" (base), \ "i" (op)); static inline void blast_scache128(void) { - unsigned long start = KSEG0; + unsigned long start = INDEX_BASE; unsigned long end = start + current_cpu_data.scache.waysize; unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit; unsigned long ws_end = current_cpu_data.scache.ways << @@ -546,10 +560,10 @@ static inline void blast_scache128_page(unsigned long page) unsigned long start = page; unsigned long end = page + PAGE_SIZE; - while (start < end) { + do { cache128_unroll32(start,Hit_Writeback_Inv_SD); start += 0x1000; - } + } while (start < end); } static inline void blast_scache128_page_indexed(unsigned long page) @@ -566,4 +580,4 @@ static inline void blast_scache128_page_indexed(unsigned long page) cache128_unroll32(addr|ws,Index_Writeback_Inv_SD); } -#endif /* __ASM_R4KCACHE_H */ +#endif /* _ASM_R4KCACHE_H */ diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h index ffd02109a0e5..31c0c2347f4f 100644 --- a/include/asm-mips/rtc.h +++ b/include/asm-mips/rtc.h @@ -1,10 +1,37 @@ -#ifndef _I386_RTC_H -#define _I386_RTC_H - /* - * x86 uses the default access methods for the RTC. + * include/asm-mips/rtc.h + * + * (Really an interface for drivers/char/genrtc.c) + * + * Copyright (C) 2004 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * + * Please read the COPYING file for all license details. */ -#include <asm-generic/rtc.h> +#ifndef _MIPS_RTC_H +#define _MIPS_RTC_H + +#ifdef __KERNEL__ + +#include <linux/rtc.h> + +#define RTC_PIE 0x40 /* periodic interrupt enable */ +#define RTC_AIE 0x20 /* alarm interrupt enable */ +#define RTC_UIE 0x10 /* update-finished interrupt enable */ +/* some dummy definitions */ +#define RTC_BATT_BAD 0x100 /* battery bad */ +#define RTC_SQWE 0x08 /* enable square-wave output */ +#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ +#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ +#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ + +unsigned int get_rtc_time(struct rtc_time *time); +int set_rtc_time(struct rtc_time *time); +unsigned int get_rtc_ss(void); +int get_rtc_pll(struct rtc_pll_info *pll); +int set_rtc_pll(struct rtc_pll_info *pll); + +#endif #endif diff --git a/include/asm-mips/semaphore-helper.h b/include/asm-mips/semaphore-helper.h deleted file mode 100644 index 1151c37e1a16..000000000000 --- a/include/asm-mips/semaphore-helper.h +++ /dev/null @@ -1,182 +0,0 @@ -/* - * SMP- and interrupt-safe semaphores helper functions. - * - * Copyright (C) 1996 Linus Torvalds - * Copyright (C) 1999 Andrea Arcangeli - * Copyright (C) 1999, 2001, 2002 Ralf Baechle - * Copyright (C) 1999, 2001 Silicon Graphics, Inc. - * Copyright (C) 2000 MIPS Technologies, Inc. - */ -#ifndef _ASM_SEMAPHORE_HELPER_H -#define _ASM_SEMAPHORE_HELPER_H - -#include <linux/config.h> -#include <linux/errno.h> - -#define sem_read(a) ((a)->counter) -#define sem_inc(a) (((a)->counter)++) -#define sem_dec(a) (((a)->counter)--) -/* - * These two _must_ execute atomically wrt each other. - */ -static inline void wake_one_more(struct semaphore * sem) -{ - atomic_inc(&sem->waking); -} - -#ifdef CONFIG_CPU_HAS_LLSC - -static inline int waking_non_zero(struct semaphore *sem) -{ - int ret, tmp; - - __asm__ __volatile__( - "1:\tll\t%1, %2\t\t\t# waking_non_zero\n\t" - "blez\t%1, 2f\n\t" - "subu\t%0, %1, 1\n\t" - "sc\t%0, %2\n\t" - "beqz\t%0, 1b\n" - "2:" - : "=r" (ret), "=r" (tmp), "+m" (sem->waking) - : "0" (0)); - - return ret; -} - -#else /* !CONFIG_CPU_HAS_LLSC */ - -/* - * It doesn't make sense, IMHO, to endlessly turn interrupts off and on again. - * Do it once and that's it. ll/sc *has* it's advantages. HK - */ - -static inline int waking_non_zero(struct semaphore *sem) -{ - unsigned long flags; - int ret = 0; - - local_irq_save(flags); - if (sem_read(&sem->waking) > 0) { - sem_dec(&sem->waking); - ret = 1; - } - local_irq_restore(flags); - return ret; -} -#endif /* !CONFIG_CPU_HAS_LLSC */ - -#ifdef CONFIG_CPU_HAS_LLDSCD - -/* - * waking_non_zero_interruptible: - * 1 got the lock - * 0 go to sleep - * -EINTR interrupted - * - * We must undo the sem->count down_interruptible decrement - * simultaneously and atomically with the sem->waking adjustment, - * otherwise we can race with wake_one_more. - * - * This is accomplished by doing a 64-bit lld/scd on the 2 32-bit words. - * - * This is crazy. Normally it's strictly forbidden to use 64-bit operations - * in the 32-bit MIPS kernel. In this case it's however ok because if an - * interrupt has destroyed the upper half of registers sc will fail. - * Note also that this will not work for MIPS32 CPUs! - * - * Pseudocode: - * - * If(sem->waking > 0) { - * Decrement(sem->waking) - * Return(SUCCESS) - * } else If(signal_pending(tsk)) { - * Increment(sem->count) - * Return(-EINTR) - * } else { - * Return(SLEEP) - * } - */ - -static inline int -waking_non_zero_interruptible(struct semaphore *sem, struct task_struct *tsk) -{ - long ret, tmp; - - __asm__ __volatile__( - ".set\tpush\t\t\t# waking_non_zero_interruptible\n\t" - ".set\tmips3\n\t" - ".set\tnoat\n" - "0:\tlld\t%1, %2\n\t" - "li\t%0, 0\n\t" - "sll\t$1, %1, 0\n\t" - "blez\t$1, 1f\n\t" - "daddiu\t%1, %1, -1\n\t" - "li\t%0, 1\n\t" - "b\t2f\n" - "1:\tbeqz\t%3, 2f\n\t" - "li\t%0, %4\n\t" - "dli\t$1, 0x0000000100000000\n\t" - "daddu\t%1, %1, $1\n" - "2:\tscd\t%1, %2\n\t" - "beqz\t%1, 0b\n\t" - ".set\tpop" - : "=&r" (ret), "=&r" (tmp), "=m" (*sem) - : "r" (signal_pending(tsk)), "i" (-EINTR)); - - return ret; -} - -/* - * waking_non_zero_trylock is unused. we do everything in - * down_trylock and let non-ll/sc hosts bounce around. - */ - -static inline int waking_non_zero_trylock(struct semaphore *sem) -{ -#if WAITQUEUE_DEBUG - CHECK_MAGIC(sem->__magic); -#endif - - return 0; -} - -#else /* !CONFIG_CPU_HAS_LLDSCD */ - -static inline int waking_non_zero_interruptible(struct semaphore *sem, - struct task_struct *tsk) -{ - int ret = 0; - unsigned long flags; - - local_irq_save(flags); - if (sem_read(&sem->waking) > 0) { - sem_dec(&sem->waking); - ret = 1; - } else if (signal_pending(tsk)) { - sem_inc(&sem->count); - ret = -EINTR; - } - local_irq_restore(flags); - return ret; -} - -static inline int waking_non_zero_trylock(struct semaphore *sem) -{ - int ret = 1; - unsigned long flags; - - local_irq_save(flags); - if (sem_read(&sem->waking) <= 0) - sem_inc(&sem->count); - else { - sem_dec(&sem->waking); - ret = 0; - } - local_irq_restore(flags); - - return ret; -} - -#endif /* !CONFIG_CPU_HAS_LLDSCD */ - -#endif /* _ASM_SEMAPHORE_HELPER_H */ diff --git a/include/asm-mips/semaphore.h b/include/asm-mips/semaphore.h index a867bb1014be..bab913a90644 100644 --- a/include/asm-mips/semaphore.h +++ b/include/asm-mips/semaphore.h @@ -11,12 +11,12 @@ #ifndef _ASM_SEMAPHORE_H #define _ASM_SEMAPHORE_H +#include <linux/compiler.h> #include <linux/config.h> -#include <asm/system.h> -#include <asm/atomic.h> #include <linux/spinlock.h> #include <linux/wait.h> #include <linux/rwsem.h> +#include <asm/atomic.h> struct semaphore { #ifdef __MIPSEB__ @@ -33,29 +33,24 @@ struct semaphore { } __attribute__((aligned(8))); #if WAITQUEUE_DEBUG -# define __SEM_DEBUG_INIT(name) \ - , (long)&(name).__magic +# define __SEM_DEBUG_INIT(name) , .__magic = (long)&(name).__magic #else # define __SEM_DEBUG_INIT(name) #endif -#ifdef __MIPSEB__ -#define __SEMAPHORE_INITIALIZER(name,count) \ -{ ATOMIC_INIT(count), ATOMIC_INIT(0), __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \ - __SEM_DEBUG_INIT(name) } -#else -#define __SEMAPHORE_INITIALIZER(name,count) \ -{ ATOMIC_INIT(0), ATOMIC_INIT(count), __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \ - __SEM_DEBUG_INIT(name) } -#endif +#define __SEMAPHORE_INITIALIZER(name,_count) { \ + .count = ATOMIC_INIT(_count), \ + .waking = ATOMIC_INIT(0), \ + .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \ + __SEM_DEBUG_INIT(name) \ +} -#define __MUTEX_INITIALIZER(name) \ - __SEMAPHORE_INITIALIZER(name,1) +#define __MUTEX_INITIALIZER(name) __SEMAPHORE_INITIALIZER(name, 1) #define __DECLARE_SEMAPHORE_GENERIC(name,count) \ - struct semaphore name = __SEMAPHORE_INITIALIZER(name,count) + struct semaphore name = __SEMAPHORE_INITIALIZER(name, count) -#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1) +#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1) #define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0) static inline void sema_init (struct semaphore *sem, int val) @@ -78,19 +73,29 @@ static inline void init_MUTEX_LOCKED (struct semaphore *sem) sema_init(sem, 0); } -asmlinkage void __down(struct semaphore * sem); -asmlinkage int __down_interruptible(struct semaphore * sem); -asmlinkage int __down_trylock(struct semaphore * sem); -asmlinkage void __up(struct semaphore * sem); +#ifndef CONFIG_CPU_HAS_LLDSCD +/* + * On machines without lld/scd we need a spinlock to make the manipulation of + * sem->count and sem->waking atomic. + */ +extern spinlock_t semaphore_lock; +#endif + +extern void __down_failed(struct semaphore * sem); +extern int __down_failed_interruptible(struct semaphore * sem); +extern void __up_wakeup(struct semaphore * sem); static inline void down(struct semaphore * sem) { + int count; + #if WAITQUEUE_DEBUG CHECK_MAGIC(sem->__magic); #endif might_sleep(); - if (atomic_dec_return(&sem->count) < 0) - __down(sem); + count = atomic_dec_return(&sem->count); + if (unlikely(count < 0)) + __down_failed(sem); } /* @@ -99,32 +104,20 @@ static inline void down(struct semaphore * sem) */ static inline int down_interruptible(struct semaphore * sem) { - int ret = 0; + int count; #if WAITQUEUE_DEBUG CHECK_MAGIC(sem->__magic); #endif might_sleep(); - if (atomic_dec_return(&sem->count) < 0) - ret = __down_interruptible(sem); - return ret; -} - -#ifndef CONFIG_CPU_HAS_LLDSCD + count = atomic_dec_return(&sem->count); + if (unlikely(count < 0)) + return __down_failed_interruptible(sem); -/* - * Non-blockingly attempt to down() a semaphore. - * Returns zero if we acquired it - */ -static inline int down_trylock(struct semaphore * sem) -{ - int ret = 0; - if (atomic_dec_return(&sem->count) < 0) - ret = __down_trylock(sem); - return ret; + return 0; } -#else +#ifdef CONFIG_CPU_HAS_LLDSCD /* * down_trylock returns 0 on success, 1 if we failed to get the lock. @@ -156,21 +149,22 @@ static inline int down_trylock(struct semaphore * sem) #endif __asm__ __volatile__( - ".set\tmips3\t\t\t# down_trylock\n" - "0:\tlld\t%1, %4\n\t" - "dli\t%3, 0x0000000100000000\n\t" - "dsubu\t%1, %3\n\t" - "li\t%0, 0\n\t" - "bgez\t%1, 2f\n\t" - "sll\t%2, %1, 0\n\t" - "blez\t%2, 1f\n\t" - "daddiu\t%1, %1, -1\n\t" - "b\t2f\n" - "1:\tdaddu\t%1, %1, %3\n\t" - "li\t%0, 1\n" - "2:\tscd\t%1, %4\n\t" - "beqz\t%1, 0b\n\t" - ".set\tmips0" + " .set mips3 # down_trylock \n" + "0: lld %1, %4 \n" + " dli %3, 0x0000000100000000 # count -= 1 \n" + " dsubu %1, %3 \n" + " li %0, 0 # ret = 0 \n" + " bgez %1, 2f # if count >= 0 \n" + " sll %2, %1, 0 # extract waking \n" + " blez %2, 1f # if waking < 0 -> 1f \n" + " daddiu %1, %1, -1 # waking -= 1 \n" + " b 2f \n" + "1: daddu %1, %1, %3 # count += 1 \n" + " li %0, 1 # ret = 1 \n" + "2: scd %1, %4 \n" + " beqz %1, 0b \n" + " sync \n" + " .set mips0 \n" : "=&r"(ret), "=&r"(tmp), "=&r"(tmp2), "=&r"(sub) : "m"(*sem) : "memory"); @@ -178,7 +172,80 @@ static inline int down_trylock(struct semaphore * sem) return ret; } -#endif /* CONFIG_CPU_HAS_LLDSCD */ +/* + * Note! This is subtle. We jump to wake people up only if + * the semaphore was negative (== somebody was waiting on it). + */ +static inline void up(struct semaphore * sem) +{ + unsigned long tmp, tmp2; + int count; + +#if WAITQUEUE_DEBUG + CHECK_MAGIC(sem->__magic); +#endif + /* + * We must manipulate count and waking simultaneously and atomically. + * Otherwise we have races between up and __down_failed_interruptible + * waking up on a signal. + */ + + __asm__ __volatile__( + " .set mips3 \n" + " sync # up \n" + "1: lld %1, %3 \n" + " dsra32 %0, %1, 0 # extract count to %0 \n" + " daddiu %0, 1 # count += 1 \n" + " slti %2, %0, 1 # %3 = (%0 <= 0) \n" + " daddu %1, %2 # waking += %3 \n" + " dsll32 %1, %1, 0 # zero-extend %1 \n" + " dsrl32 %1, %1, 0 \n" + " dsll32 %2, %0, 0 # Reassemble union \n" + " or %1, %2 # from count and waking \n" + " scd %1, %3 \n" + " beqz %1, 1b \n" + " .set mips0 \n" + : "=&r"(count), "=&r"(tmp), "=&r"(tmp2), "+m"(*sem) + : + : "memory"); + + if (unlikely(count <= 0)) + __up_wakeup(sem); +} + +#else + +/* + * Non-blockingly attempt to down() a semaphore. + * Returns zero if we acquired it + */ +static inline int down_trylock(struct semaphore * sem) +{ + unsigned long flags; + int count, waking; + int ret = 0; + +#if WAITQUEUE_DEBUG + CHECK_MAGIC(sem->__magic); +#endif + + spin_lock_irqsave(&semaphore_lock, flags); + count = atomic_read(&sem->count) - 1; + atomic_set(&sem->count, count); + if (unlikely(count < 0)) { + waking = atomic_read(&sem->waking); + if (waking <= 0) { + atomic_set(&sem->count, count + 1); + ret = 1; + } else { + atomic_set(&sem->waking, waking - 1); + ret = 0; + } + } + spin_unlock_irqrestore(&semaphore_lock, flags); + + return ret; +} /* * Note! This is subtle. We jump to wake people up only if @@ -186,11 +253,31 @@ static inline int down_trylock(struct semaphore * sem) */ static inline void up(struct semaphore * sem) { + unsigned long flags; + int count, waking; + #if WAITQUEUE_DEBUG CHECK_MAGIC(sem->__magic); #endif - if (atomic_inc_return(&sem->count) <= 0) - __up(sem); + /* + * We must manipulate count and waking simultaneously and atomically. + * Otherwise we have races between up and __down_failed_interruptible + * waking up on a signal. + */ + + spin_lock_irqsave(&semaphore_lock, flags); + count = atomic_read(&sem->count) + 1; + waking = atomic_read(&sem->waking); + if (count <= 0) + waking++; + atomic_set(&sem->count, count); + atomic_set(&sem->waking, waking); + spin_unlock_irqrestore(&semaphore_lock, flags); + + if (unlikely(count <= 0)) + __up_wakeup(sem); } +#endif /* CONFIG_CPU_HAS_LLDSCD */ + #endif /* _ASM_SEMAPHORE_H */ diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h index 4e95feb89d16..4711c0e7af43 100644 --- a/include/asm-mips/serial.h +++ b/include/asm-mips/serial.h @@ -10,7 +10,6 @@ #define _ASM_SERIAL_H #include <linux/config.h> -#include <asm/jazz.h> /* * This assumes you have a 1.8432 MHz clock for your UART. @@ -21,15 +20,6 @@ */ #define BASE_BAUD (1843200 / 16) -#ifndef CONFIG_OLIVETTI_M700 - /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know - exactly which ones ... XXX */ -#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */ -#else -/* but the M700 isn't such a strange beast */ -#define JAZZ_BASE_BAUD BASE_BAUD -#endif - /* Standard COM flags (except for COM4, because of the 8514 problem) */ #ifdef CONFIG_SERIAL_DETECT_IRQ #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) @@ -66,6 +56,17 @@ #define C_P(card,port) (((card)<<6|(port)<<3) + 1) #ifdef CONFIG_MIPS_JAZZ +#include <asm/jazz.h> + +#ifndef CONFIG_OLIVETTI_M700 + /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know + exactly which ones ... XXX */ +#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */ +#else +/* but the M700 isn't such a strange beast */ +#define JAZZ_BASE_BAUD BASE_BAUD +#endif + #define _JAZZ_SERIAL_INIT(int, base) \ { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \ .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \ @@ -77,26 +78,6 @@ #define JAZZ_SERIAL_PORT_DEFNS #endif -#ifdef CONFIG_MIPS_ATLAS -#include <asm/mips-boards/atlas.h> -#include <asm/mips-boards/atlasint.h> -#define ATLAS_SERIAL_PORT_DEFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, ATLAS_BASE_BAUD, ATLAS_UART_REGS_BASE, ATLASINT_UART, STD_COM_FLAGS }, /* ttyS0 */ -#else -#define ATLAS_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_MIPS_SEAD -#include <asm/mips-boards/sead.h> -#include <asm/mips-boards/seadint.h> -#define SEAD_SERIAL_PORT_DEFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, SEAD_BASE_BAUD, SEAD_UART0_REGS_BASE, SEADINT_UART0, STD_COM_FLAGS }, /* ttyS0 */ -#else -#define SEAD_SERIAL_PORT_DEFNS -#endif - #ifdef CONFIG_MIPS_COBALT #include <asm/cobalt/cobalt.h> #define COBALT_BASE_BAUD (18432000 / 16) @@ -158,35 +139,6 @@ #define IVR_SERIAL_PORT_DEFNS #endif -#ifdef CONFIG_LASAT -/* This dummy definition allocates one element in the SERIAL_PORT_DFNS - * list below. This element is filled out by the the code in serial_init() - * in arch/mips/lasat/setup.c which autoselects the configuration based - * on machine type. */ -#define LASAT_SERIAL_PORT_DEFNS { }, -#else -#define LASAT_SERIAL_PORT_DEFNS -#endif - -#ifdef CONFIG_SERIAL_AU1X00 -#include <asm/au1000.h> -#define AU1X00_SERIAL_PORT_DEFNS \ - { .baud_base = 0, .iomem_base = (u8 *)UART0_ADDR, \ - .irq = AU1000_UART0_INT, .flags = STD_COM_FLAGS, \ - .iomem_reg_shift = 2, }, \ - { .baud_base = 0, .iomem_base = (u8 *)UART1_ADDR, \ - .irq = AU1000_UART1_INT, .flags = STD_COM_FLAGS, \ - .iomem_reg_shift = 2 }, \ - { .baud_base = 0, .iomem_base = (u8 *)UART2_ADDR, \ - .irq = AU1000_UART2_INT, .flags = STD_COM_FLAGS, \ - .iomem_reg_shift = 2}, \ - { .baud_base = 0, .iomem_base = (u8 *)UART3_ADDR, \ - .irq = AU1000_UART3_INT, .flags = STD_COM_FLAGS, \ - .iomem_reg_shift = 2}, -#else -#define AU1X00_SERIAL_PORT_DEFNS -#endif - #ifdef CONFIG_TOSHIBA_JMR3927 #include <asm/jmr3927/jmr3927.h> #define TXX927_SERIAL_PORT_DEFNS \ @@ -198,6 +150,21 @@ #define TXX927_SERIAL_PORT_DEFNS #endif +#ifdef CONFIG_SERIAL_AU1X00 +#include <asm/mach-au1x00/au1000.h> +#define AU1000_SERIAL_PORT_DEFNS \ + { .baud_base = 0, .port = UART0_ADDR, .irq = AU1000_UART0_INT, \ + .flags = STD_COM_FLAGS, .type = 1 }, \ + { .baud_base = 0, .port = UART1_ADDR, .irq = AU1000_UART1_INT, \ + .flags = STD_COM_FLAGS, .type = 1 }, \ + { .baud_base = 0, .port = UART2_ADDR, .irq = AU1000_UART2_INT, \ + .flags = STD_COM_FLAGS, .type = 1 }, \ + { .baud_base = 0, .port = UART3_ADDR, .irq = AU1000_UART3_INT, \ + .flags = STD_COM_FLAGS, .type = 1 }, +#else +#define AU1000_SERIAL_PORT_DEFNS +#endif + #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT #define STD_SERIAL_PORT_DEFNS \ /* UART CLK PORT IRQ FLAGS */ \ @@ -341,6 +308,24 @@ #define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS #endif +#ifdef CONFIG_TITAN_SERIAL +/* 16552 20 MHz crystal */ +#define TITAN_SERIAL_BASE_BAUD ( 20000000 / 16 ) +#define TITAN_SERIAL_IRQ XXX +#define TITAN_SERIAL_BASE 0xffffffff + +#define _TITAN_SERIAL_INIT(int, base) \ + { baud_base: TITAN_SERIAL_BASE_BAUD, irq: int, \ + flags: STD_COM_FLAGS, iomem_base: (u8 *) base, \ + iomem_reg_shift: 2, io_type: SERIAL_IO_MEM \ + } + +#define TITAN_SERIAL_PORT_DEFNS \ + _TITAN_SERIAL_INIT(TITAN_SERIAL_IRQ, TITAN_SERIAL_BASE) +#else +#define TITAN_SERIAL_PORT_DEFNS +#endif + #ifdef CONFIG_DDB5477 #include <asm/ddb5xxx/ddb5477.h> #define DDB5477_SERIAL_PORT_DEFNS \ @@ -354,95 +339,33 @@ #define DDB5477_SERIAL_PORT_DEFNS #endif -#ifdef CONFIG_SGI_IP27 - -/* - * Note about serial ports and consoles: - * For console output, everyone uses the IOC3 UARTA (offset 0x178) - * connected to the master node (look in ip27_setup_console() and - * ip27prom_console_write()). - * - * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port - * addresses on a partitioned machine. Since we currently use the ioc3 - * serial ports, we use dynamic serial port discovery that the serial.c - * driver uses for pci/pnp ports (there is an entry for the SGI ioc3 - * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater - * than UARTB's, although UARTA on o200s has traditionally been known as - * port 0. So, we just use one serial port from each ioc3 (since the - * serial driver adds addresses to get to higher ports). - * - * The first one to do a register_console becomes the preferred console - * (if there is no kernel command line console= directive). /dev/console - * (ie 5, 1) is then "aliased" into the device number returned by the - * "device" routine referred to in this console structure - * (ip27prom_console_dev). - * - * Also look in ip27-pci.c:pci_fixuop_ioc3() for some comments on working - * around ioc3 oddities in this respect. - * - * The IOC3 serials use a 22MHz clock rate with an additional divider by 3. - * (IOC3_BAUD = (22000000 / (3*16))) - * - * At the moment this is only a skeleton definition as we register all serials - * at runtime. - */ - -#define IP27_SERIAL_PORT_DEFNS -#else -#define IP27_SERIAL_PORT_DEFNS -#endif /* CONFIG_SGI_IP27 */ - #ifdef CONFIG_SGI_IP32 - -#include <asm/ip32/ip32_ints.h> - /* * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory + * They are initialized in ip32_setup */ - -/* Standard COM flags (except for COM4, because of the 8514 problem) */ -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF/* | ASYNC_SKIP_TEST*/) -#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF -#endif - #define IP32_SERIAL_PORT_DEFNS \ - { .baud_base = BASE_BAUD, \ - .irq = MACEISA_SERIAL1_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8*)MACE_BASE+MACEISA_SER1_BASE, \ - .iomem_reg_shift = 8, \ - .io_type = SERIAL_IO_MEM}, \ - { .baud_base = BASE_BAUD, \ - .irq = MACEISA_SERIAL2_IRQ, \ - .flags = STD_COM_FLAGS, \ - .iomem_base = (u8*)MACE_BASE+MACEISA_SER2_BASE, \ - .iomem_reg_shift = 8, \ - .io_type = SERIAL_IO_MEM}, + {},{}, #else #define IP32_SERIAL_PORT_DEFNS -#endif /* CONFIG_SGI_IP31 */ +#endif /* CONFIG_SGI_IP32 */ #define SERIAL_PORT_DFNS \ - IVR_SERIAL_PORT_DEFNS \ - ITE_SERIAL_PORT_DEFNS \ - ATLAS_SERIAL_PORT_DEFNS \ - SEAD_SERIAL_PORT_DEFNS \ COBALT_SERIAL_PORT_DEFNS \ - LASAT_SERIAL_PORT_DEFNS \ + DDB5477_SERIAL_PORT_DEFNS \ EV96100_SERIAL_PORT_DEFNS \ - JAZZ_SERIAL_PORT_DEFNS \ - STD_SERIAL_PORT_DEFNS \ EXTRA_SERIAL_PORT_DEFNS \ HUB6_SERIAL_PORT_DFNS \ - MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ + IP32_SERIAL_PORT_DEFNS \ + ITE_SERIAL_PORT_DEFNS \ + IVR_SERIAL_PORT_DEFNS \ + JAZZ_SERIAL_PORT_DEFNS \ + STD_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \ MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \ - AU1X00_SERIAL_PORT_DEFNS \ - TXX927_SERIAL_PORT_DEFNS \ - DDB5477_SERIAL_PORT_DEFNS + MOMENCO_OCELOT_SERIAL_PORT_DEFNS \ + TITAN_SERIAL_PORT_DEFNS \ + TXX927_SERIAL_PORT_DEFNS \ + AU1000_SERIAL_PORT_DEFNS #endif /* _ASM_SERIAL_H */ diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h index 1cad06cda8f7..3e16b4d9d621 100644 --- a/include/asm-mips/sgi/ioc.h +++ b/include/asm-mips/sgi/ioc.h @@ -14,48 +14,13 @@ #define _SGI_IOC_H #include <linux/types.h> +#include <asm/sgi/pi1.h> /* * All registers are 8-bit wide alligned on 32-bit boundary. Bad things * happen if you try word access them. You have been warned. */ -struct sgioc_pport_regs { - u8 _data[3]; - volatile u8 data; - u8 _ctrl[3]; - volatile u8 ctrl; -#define SGIOC_PCTRL_STROBE 0x01 -#define SGIOC_PCTRL_AFD 0x02 -#define SGIOC_PCTRL_INIT 0x04 -#define SGIOC_PCTRL_SLIN 0x08 -#define SGIOC_PCTRL_DIRECTION 0x20 -#define SGIOC_PCTRL_SEL 0x40 - u8 _status[3]; - volatile u8 status; -#define SGIOC_PSTAT_DEVID 0x03 -#define SGIOC_PSTAT_NOINK 0x04 -#define SGIOC_PSTAT_ERROR 0x08 -#define SGIOC_PSTAT_ONLINE 0x10 -#define SGIOC_PSTAT_PE 0x20 -#define SGIOC_PSTAT_ACK 0x40 -#define SGIOC_PSTAT_BUSY 0x80 - u8 _dmactrl[3]; - volatile u8 dmactrl; - u8 _intrstat[3]; - volatile u8 intrstat; - u8 _intrmask[3]; - volatile u8 intrmask; - u8 _timer1[3]; - volatile u8 timer1; - u8 _timer2[3]; - volatile u8 timer2; - u8 _timer3[3]; - volatile u8 timer3; - u8 _timer4[3]; - volatile u8 timer4; -}; - struct sgioc_uart_regs { u8 _ctrl1[3]; volatile u8 ctrl1; @@ -153,7 +118,7 @@ struct sgint_regs { extern u8 sgi_ioc_reset, sgi_ioc_write; struct sgioc_regs { - struct sgioc_pport_regs pport; + struct pi1_regs pport; u32 _unused0[2]; struct sgioc_uart_regs serport; struct sgioc_keyb_regs kbdmouse; diff --git a/include/asm-mips/sgi/pi1.h b/include/asm-mips/sgi/pi1.h new file mode 100644 index 000000000000..c9506915dc5c --- /dev/null +++ b/include/asm-mips/sgi/pi1.h @@ -0,0 +1,71 @@ +/* + * pi1.h: Definitions for SGI PI1 parallel port + */ + +#ifndef _SGI_PI1_H +#define _SGI_PI1_H + +struct pi1_regs { + u8 _data[3]; + volatile u8 data; + u8 _ctrl[3]; + volatile u8 ctrl; +#define PI1_CTRL_STROBE_N 0x01 +#define PI1_CTRL_AFD_N 0x02 +#define PI1_CTRL_INIT_N 0x04 +#define PI1_CTRL_SLIN_N 0x08 +#define PI1_CTRL_IRQ_ENA 0x10 +#define PI1_CTRL_DIR 0x20 +#define PI1_CTRL_SEL 0x40 + u8 _status[3]; + volatile u8 status; +#define PI1_STAT_DEVID 0x03 /* bits 0-1 */ +#define PI1_STAT_NOINK 0x04 /* SGI MODE only */ +#define PI1_STAT_ERROR 0x08 +#define PI1_STAT_ONLINE 0x10 +#define PI1_STAT_PE 0x20 +#define PI1_STAT_ACK 0x40 +#define PI1_STAT_BUSY 0x80 + u8 _dmactrl[3]; + volatile u8 dmactrl; +#define PI1_DMACTRL_FIFO_EMPTY 0x01 /* fifo empty R/O */ +#define PI1_DMACTRL_ABORT 0x02 /* reset DMA and internal fifo W/O */ +#define PI1_DMACTRL_STDMODE 0x00 /* bits 2-3 */ +#define PI1_DMACTRL_SGIMODE 0x04 /* bits 2-3 */ +#define PI1_DMACTRL_RICOHMODE 0x08 /* bits 2-3 */ +#define PI1_DMACTRL_HPMODE 0x0c /* bits 2-3 */ +#define PI1_DMACTRL_BLKMODE 0x10 /* block mode */ +#define PI1_DMACTRL_FIFO_CLEAR 0x20 /* clear fifo W/O */ +#define PI1_DMACTRL_READ 0x40 /* read */ +#define PI1_DMACTRL_RUN 0x80 /* pedal to the metal */ + u8 _intstat[3]; + volatile u8 intstat; +#define PI1_INTSTAT_ACK 0x04 +#define PI1_INTSTAT_FEMPTY 0x08 +#define PI1_INTSTAT_NOINK 0x10 +#define PI1_INTSTAT_ONLINE 0x20 +#define PI1_INTSTAT_ERR 0x40 +#define PI1_INTSTAT_PE 0x80 + u8 _intmask[3]; + volatile u8 intmask; /* enabled low, reset high*/ +#define PI1_INTMASK_ACK 0x04 +#define PI1_INTMASK_FIFO_EMPTY 0x08 +#define PI1_INTMASK_NOINK 0x10 +#define PI1_INTMASK_ONLINE 0x20 +#define PI1_INTMASK_ERR 0x40 +#define PI1_INTMASK_PE 0x80 + u8 _timer1[3]; + volatile u8 timer1; +#define PI1_TIME1 0x27 + u8 _timer2[3]; + volatile u8 timer2; +#define PI1_TIME2 0x13 + u8 _timer3[3]; + volatile u8 timer3; +#define PI1_TIME3 0x10 + u8 _timer4[3]; + volatile u8 timer4; +#define PI1_TIME4 0x00 +}; + +#endif diff --git a/include/asm-mips/sgialib.h b/include/asm-mips/sgialib.h index 30b497b82a2f..73f097315502 100644 --- a/include/asm-mips/sgialib.h +++ b/include/asm-mips/sgialib.h @@ -24,11 +24,10 @@ extern LONG *_prom_argv, *_prom_envp; #define prom_argc(index) ((char *) (long) _prom_argc[(index)]) extern int prom_flags; + #define PROM_FLAG_ARCS 1 #define PROM_FLAG_USE_AS_CONSOLE 2 - -/* Init the PROM library and it's internal data structures. */ -extern void prom_init(int argc, char **argv, char **envp, int *prom_vec); +#define PROM_FLAG_DONT_FREE_TEMP 4 /* Simple char-by-char console I/O. */ extern void prom_putchar(char c); @@ -123,5 +122,6 @@ extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn)); extern long prom_cfgsave(VOID); extern struct linux_sysid *prom_getsysid(VOID); extern VOID ArcFlushAllCaches(VOID); +extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID); #endif /* _ASM_SGIALIB_H */ diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h index 48325845ab77..d63ef67ceb27 100644 --- a/include/asm-mips/sgiarcs.h +++ b/include/asm-mips/sgiarcs.h @@ -236,6 +236,8 @@ struct linux_romvec { /* Miscellaneous. */ LONG cache_flush; + LONG TestUnicodeCharacter; /* ARC; not sure if ARCS too */ + LONG GetDisplayStatus; }; /* The SGI ARCS parameter block is in a fixed location for standalone diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h index 57473ab5c6f8..7afa8a2501ce 100644 --- a/include/asm-mips/sibyte/board.h +++ b/include/asm-mips/sibyte/board.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2000, 2001 Broadcom Corporation + * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -19,10 +19,13 @@ #ifndef _SIBYTE_BOARD_H #define _SIBYTE_BOARD_H +#include <linux/config.h> + #ifdef CONFIG_SIBYTE_BOARD #if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \ - defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) + defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \ + defined(CONFIG_SIBYTE_LITTLESUR) #include <asm/sibyte/swarm.h> #endif diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h index e691b6dadba8..7ac5da13ce8a 100644 --- a/include/asm-mips/sibyte/carmel.h +++ b/include/asm-mips/sibyte/carmel.h @@ -18,6 +18,8 @@ #ifndef __ASM_SIBYTE_CARMEL_H #define __ASM_SIBYTE_CARMEL_H +#include <linux/config.h> + #include <asm/sibyte/sb1250.h> #include <asm/sibyte/sb1250_int.h> diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h index 58d8f4580b7b..c79a101756c9 100644 --- a/include/asm-mips/sibyte/sb1250.h +++ b/include/asm-mips/sibyte/sb1250.h @@ -58,6 +58,6 @@ extern void prom_printf(char *fmt, ...); #endif -#define IO_SPACE_BASE KSEG1 +#define IOADDR(a) (UNCAC_BASE + (a)) #endif diff --git a/include/asm-mips/sibyte/sentosa.h b/include/asm-mips/sibyte/sentosa.h index 64c47874f32d..824605847af4 100644 --- a/include/asm-mips/sibyte/sentosa.h +++ b/include/asm-mips/sibyte/sentosa.h @@ -18,6 +18,7 @@ #ifndef __ASM_SIBYTE_SENTOSA_H #define __ASM_SIBYTE_SENTOSA_H +#include <linux/config.h> #include <asm/sibyte/sb1250.h> #include <asm/sibyte/sb1250_int.h> diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h index 9a460fe32b5a..97fa0494c30c 100644 --- a/include/asm-mips/sibyte/swarm.h +++ b/include/asm-mips/sibyte/swarm.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2000, 2001 Broadcom Corporation + * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -18,36 +18,52 @@ #ifndef __ASM_SIBYTE_SWARM_H #define __ASM_SIBYTE_SWARM_H +#include <linux/config.h> #include <asm/sibyte/sb1250.h> #include <asm/sibyte/sb1250_int.h> #ifdef CONFIG_SIBYTE_SWARM #define SIBYTE_BOARD_NAME "BCM91250A (SWARM)" +#define SIBYTE_HAVE_PCMCIA 1 +#define SIBYTE_HAVE_IDE 1 #endif #ifdef CONFIG_SIBYTE_PTSWARM #define SIBYTE_BOARD_NAME "PTSWARM" +#define SIBYTE_HAVE_PCMCIA 1 +#define SIBYTE_HAVE_IDE 1 +#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200" +#endif +#ifdef CONFIG_SIBYTE_LITTLESUR +#define SIBYTE_BOARD_NAME "BCM1250C2 (LittleSur)" +#define SIBYTE_HAVE_PCMCIA 0 +#define SIBYTE_HAVE_IDE 1 +#define SIBYTE_DEFAULT_CONSOLE "cfe0" #endif #ifdef CONFIG_SIBYTE_CRHONE #define SIBYTE_BOARD_NAME "BCM91125C (CRhone)" +#define SIBYTE_HAVE_PCMCIA 0 +#define SIBYTE_HAVE_IDE 0 #endif #ifdef CONFIG_SIBYTE_CRHINE #define SIBYTE_BOARD_NAME "BCM91120C (CRhine)" +#define SIBYTE_HAVE_PCMCIA 0 +#define SIBYTE_HAVE_IDE 0 #endif /* Generic bus chip selects */ #define LEDS_CS 3 #define LEDS_PHYS 0x100a0000 -#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) + +#ifdef SIBYTE_HAVE_IDE #define IDE_CS 4 #define IDE_PHYS 0x100b0000 -#define PCMCIA_CS 6 -#define PCMCIA_PHYS 0x11000000 -#endif - -/* GPIOs */ -#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) #define K_GPIO_GB_IDE 4 #define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE) +#endif + +#ifdef SIBYTE_HAVE_PCMCIA +#define PCMCIA_CS 6 +#define PCMCIA_PHYS 0x11000000 #define K_GPIO_PC_READY 9 #define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY) #endif diff --git a/include/asm-mips/sibyte/trace_prof.h b/include/asm-mips/sibyte/trace_prof.h index 38157a9e400e..557792075e9a 100644 --- a/include/asm-mips/sibyte/trace_prof.h +++ b/include/asm-mips/sibyte/trace_prof.h @@ -19,6 +19,7 @@ #ifndef __ASM_SIBYTE_TRACE_PROF_H #define __ASM_SIBYTE_TRACE_PROF_H +#undef DBG #if SBPROF_TB_DEBUG #define DBG(a) a #else @@ -62,10 +63,10 @@ struct sbprof_tb { saturate 40 bits. No subsequent use of SCD performance counters or trace buffer. Effect: Starts gathering random ZBbus profiles using trace buffer. */ -static int sbprof_zbprof_start(struct file *filp); +extern int sbprof_zbprof_start(struct file *filp); /* Effect: Stops collection of ZBbus profiles */ -static int sbprof_zbprof_stop(void); +extern int sbprof_zbprof_stop(void); /*************************************************************************** diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h index 09979bd22513..844879d63b77 100644 --- a/include/asm-mips/sigcontext.h +++ b/include/asm-mips/sigcontext.h @@ -65,6 +65,7 @@ struct sigcontext { unsigned int sc_cause; }; +#ifdef __KERNEL__ struct sigcontext32 { __u32 sc_regmask; /* Unused */ __u32 sc_status; @@ -84,6 +85,7 @@ struct sigcontext32 { __u32 sc_sigset[4]; /* kernel's sigset_t */ }; +#endif /* __KERNEL__ */ #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */ diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h index 2137ba458365..39d9ca204104 100644 --- a/include/asm-mips/siginfo.h +++ b/include/asm-mips/siginfo.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1998, 1999, 2001 Ralf Baechle + * Copyright (C) 1998, 1999, 2001, 2003 Ralf Baechle * Copyright (C) 2000, 2001 Silicon Graphics, Inc. */ #ifndef _ASM_SIGINFO_H @@ -11,11 +11,11 @@ #include <linux/config.h> -#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4) +#define SIGEV_HEAD_SIZE (sizeof(long) + 2*sizeof(int)) +#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE-SIGEV_HEAD_SIZE) / sizeof(int)) #define SI_PAD_SIZE ((SI_MAX_SIZE/sizeof(int)) - 4) #define HAVE_ARCH_SIGINFO_T -#define HAVE_ARCH_SIGEVENT_T /* * We duplicate the generic versions - <asm-generic/siginfo.h> is just borked @@ -177,38 +177,6 @@ typedef struct siginfo32 { #define SI_TIMER __SI_CODE(__SI_TIMER,-3) /* sent by timer expiration */ #define SI_MESGQ -4 /* sent by real time mesq state change */ -/* - * sigevent definitions - * - * It seems likely that SIGEV_THREAD will have to be handled from - * userspace, libpthread transmuting it to SIGEV_SIGNAL, which the - * thread manager then catches and does the appropriate nonsense. - * However, everything is written out here so as to not get lost. - */ -#undef SIGEV_NONE -#undef SIGEV_SIGNAL -#undef SIGEV_THREAD -#define SIGEV_NONE 128 /* other notification: meaningless */ -#define SIGEV_SIGNAL 129 /* notify via signal */ -#define SIGEV_CALLBACK 130 /* ??? */ -#define SIGEV_THREAD 131 /* deliver via thread creation */ - -/* XXX This one isn't yet IRIX / ABI compatible. */ -typedef struct sigevent { - int sigev_notify; - sigval_t sigev_value; - int sigev_signo; - union { - int _pad[SIGEV_PAD_SIZE]; - int _tid; - - struct { - void (*_function)(sigval_t); - void *_attribute; /* really pthread_attr_t */ - } _sigev_thread; - } _sigev_un; -} sigevent_t; - #ifdef __KERNEL__ /* diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h index 59de82024d3b..a88c33750555 100644 --- a/include/asm-mips/sim.h +++ b/include/asm-mips/sim.h @@ -13,14 +13,14 @@ #include <asm/offset.h> -#ifdef CONFIG_MIPS32 - /* Used in declaration of save_static functions. */ #define static_unused static __attribute__((unused)) #define __str2(x) #x #define __str(x) __str2(x) +#ifdef CONFIG_MIPS32 + #define save_static_function(symbol) \ __asm__ ( \ ".text\n\t" \ @@ -42,20 +42,12 @@ __asm__ ( \ ".end\t" #symbol "\n\t" \ ".size\t" #symbol",. - " #symbol) -#define save_static(frame) do { } while (0) - #define nabi_no_regargs #endif /* CONFIG_MIPS32 */ #ifdef CONFIG_MIPS64 -/* Used in declaration of save_static functions. */ -#define static_unused static __attribute__((unused)) - -#define __str2(x) #x -#define __str(x) __str2(x) - #define save_static_function(symbol) \ __asm__ ( \ ".text\n\t" \ @@ -65,23 +57,18 @@ __asm__ ( \ ".ent\t" #symbol ", 0\n" \ #symbol":\n\t" \ ".frame\t$29, 0, $31\n\t" \ + "sd\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t" \ + "sd\t$17,"__str(PT_R17)"($29)\n\t" \ + "sd\t$18,"__str(PT_R18)"($29)\n\t" \ + "sd\t$19,"__str(PT_R19)"($29)\n\t" \ + "sd\t$20,"__str(PT_R20)"($29)\n\t" \ + "sd\t$21,"__str(PT_R21)"($29)\n\t" \ + "sd\t$22,"__str(PT_R22)"($29)\n\t" \ + "sd\t$23,"__str(PT_R23)"($29)\n\t" \ + "sd\t$30,"__str(PT_R30)"($29)\n\t" \ ".end\t" #symbol "\n\t" \ ".size\t" #symbol",. - " #symbol) -#define save_static(frame) \ - __asm__ __volatile__( \ - "sd\t$16,"__str(PT_R16)"(%0)\n\t" \ - "sd\t$17,"__str(PT_R17)"(%0)\n\t" \ - "sd\t$18,"__str(PT_R18)"(%0)\n\t" \ - "sd\t$19,"__str(PT_R19)"(%0)\n\t" \ - "sd\t$20,"__str(PT_R20)"(%0)\n\t" \ - "sd\t$21,"__str(PT_R21)"(%0)\n\t" \ - "sd\t$22,"__str(PT_R22)"(%0)\n\t" \ - "sd\t$23,"__str(PT_R23)"(%0)\n\t" \ - "sd\t$30,"__str(PT_R30)"(%0)\n\t" \ - : /* No outputs */ \ - : "r" (frame)) - #define nabi_no_regargs \ unsigned long __dummy0, \ unsigned long __dummy1, \ diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h index c8d1ed35c1cc..4c9d2618ee8d 100644 --- a/include/asm-mips/smp.h +++ b/include/asm-mips/smp.h @@ -16,6 +16,7 @@ #ifdef CONFIG_SMP #include <linux/bitops.h> +#include <linux/linkage.h> #include <linux/threads.h> #include <linux/cpumask.h> #include <asm/atomic.h> @@ -52,11 +53,6 @@ extern cpumask_t cpu_online_map; #define cpu_online(cpu) cpu_isset(cpu, cpu_online_map) -static inline unsigned int num_online_cpus(void) -{ - return cpus_weight(cpu_online_map); -} - extern cpumask_t cpu_callout_map; /* We don't mark CPUs online until __cpu_up(), so we need another measure */ static inline int num_booting_cpus(void) @@ -64,6 +60,63 @@ static inline int num_booting_cpus(void) return cpus_weight(cpu_callout_map); } +/* These are defined by the board-specific code. */ + +/* + * Cause the function described by call_data to be executed on the passed + * cpu. When the function has finished, increment the finished field of + * call_data. + */ +extern void core_send_ipi(int cpu, unsigned int action); + +/* + * Detect available CPUs, populate phys_cpu_present_map + */ +extern void prom_build_cpu_map(void); + +/* + * Firmware CPU startup hook + */ +extern void prom_boot_secondary(int cpu, struct task_struct *idle); + +/* + * After we've done initial boot, this function is called to allow the + * board code to clean up state, if needed + */ +extern void prom_init_secondary(void); + +/* + * Callout to firmware before smp_init + */ +extern void prom_prepare_cpus(unsigned int max_cpus); + +/* + * Do whatever setup needs to be done for SMP at the board level. Return + * the number of cpus in the system, including this one + */ +extern int prom_setup_smp(void); + +/* + * Last chance for the board code to finish SMP initialization before + * the CPU is "online". + */ +extern void prom_smp_finish(void); + +/* Hook for after all CPUs are online */ +extern void prom_cpus_done(void); + +extern void asmlinkage smp_bootstrap(void); + +/* + * this function sends a 'reschedule' IPI to another CPU. + * it goes straight through and wastes no time serializing + * anything. Worst case is that we lose a reschedule ... + */ +static inline void smp_send_reschedule(int cpu) +{ + core_send_ipi(cpu, SMP_RESCHEDULE_YOURSELF); +} + #endif /* CONFIG_SMP */ #endif /* __ASM_SMP_H */ diff --git a/include/asm-mips/smplock.h b/include/asm-mips/smplock.h deleted file mode 100644 index 861274910044..000000000000 --- a/include/asm-mips/smplock.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Default SMP lock implementation - */ -#include <linux/config.h> -#include <linux/interrupt.h> -#include <linux/spinlock.h> - -extern spinlock_t kernel_flag; - -#ifdef CONFIG_SMP -#define kernel_locked() spin_is_locked(&kernel_flag) -#else -#ifdef CONFIG_PREEMPT -#define kernel_locked() preempt_count() -#else -#define kernel_locked() 1 -#endif -#endif - -/* - * Release global kernel lock and global interrupt lock - */ -#define release_kernel_lock(task) \ -do { \ - if (unlikely(task->lock_depth >= 0)) \ - spin_unlock(&kernel_flag); \ -} while (0) - -/* - * Re-acquire the kernel lock - */ -#define reacquire_kernel_lock(task) \ -do { \ - if (unlikely(task->lock_depth >= 0)) \ - spin_lock(&kernel_flag); \ -} while (0) - - -/* - * Getting the big kernel lock. - * - * This cannot happen asynchronously, - * so we only need to worry about other - * CPU's. - */ -static __inline__ void lock_kernel(void) -{ -#ifdef CONFIG_PREEMPT - if (current->lock_depth == -1) - spin_lock(&kernel_flag); - ++current->lock_depth; -#else - - if (!++current->lock_depth) - spin_lock(&kernel_flag); -#endif -} - -static __inline__ void unlock_kernel(void) -{ - if (--current->lock_depth < 0) - spin_unlock(&kernel_flag); -} diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h index 51c89b946dbd..2b5cef1ba37f 100644 --- a/include/asm-mips/sn/addrs.h +++ b/include/asm-mips/sn/addrs.h @@ -16,7 +16,6 @@ #endif /* !__ASSEMBLY__ */ #include <asm/addrspace.h> -#include <asm/reg.h> #include <asm/sn/kldir.h> #if defined(CONFIG_SGI_IP27) @@ -439,9 +438,9 @@ #define PI_ERROR_SIZE(nasid) KLD_PI_ERROR(nasid)->size #define NODE_OFFSET_TO_K0(_nasid, _off) \ - PHYS_TO_K0((NODE_OFFSET(_nasid) + (_off)) | K0BASE) + PHYS_TO_K0((NODE_OFFSET(_nasid) + (_off)) | CAC_BASE) #define NODE_OFFSET_TO_K1(_nasid, _off) \ - TO_UNCAC((NODE_OFFSET(_nasid) + (_off)) | K1BASE) + TO_UNCAC((NODE_OFFSET(_nasid) + (_off)) | UNCAC_BASE) #define K0_TO_NODE_OFFSET(_k0addr) \ ((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK) diff --git a/include/asm-mips/sn/arch.h b/include/asm-mips/sn/arch.h index b225ca5a0f2d..ef03180e2dde 100644 --- a/include/asm-mips/sn/arch.h +++ b/include/asm-mips/sn/arch.h @@ -35,12 +35,9 @@ typedef u64 nic_t; #define CNODE_NUM_CPUS(_cnode) (NODEPDA(_cnode)->node_num_cpus) #define CNODE_TO_CPU_BASE(_cnode) (NODEPDA(_cnode)->node_first_cpu) -#define cputocnode(cpu) \ - (cpu_data[(cpu)].p_nodeid) -#define cputonasid(cpu) \ - (cpu_data[(cpu)].p_nasid) -#define cputoslice(cpu) \ - (cpu_data[(cpu)].p_slice) +#define cputocnode(cpu) (cpu_data[(cpu)].p_nodeid) +#define cputonasid(cpu) (cpu_data[(cpu)].p_nasid) +#define cputoslice(cpu) (cpu_data[(cpu)].p_slice) #define makespnum(_nasid, _slice) \ (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice)) @@ -100,8 +97,6 @@ nasid_t compact_to_nasid_nodeid(cnodeid_t cnode); #define CPUID_TO_COMPACT_NODEID(cpu) (cpuid_to_compact_node[(cpu)]) #endif -extern int node_getlastslot(cnodeid_t); - #endif /* !__ASSEMBLY__ */ #define SLOT_BITMASK (MAX_MEM_SLOTS - 1) diff --git a/include/asm-mips/sn/hub.h b/include/asm-mips/sn/hub.h new file mode 100644 index 000000000000..17bfedb6456c --- /dev/null +++ b/include/asm-mips/sn/hub.h @@ -0,0 +1,15 @@ +#ifndef __ASM_SN_HUB_H +#define __ASM_SN_HUB_H + +#include <asm/sn/types.h> +#include <asm/sn/io.h> +#include <asm/sn/klkernvars.h> + +struct hub_data { + kern_vars_t kern_vars; +}; + +extern struct hub_data *hub_data[]; +#define HUB_DATA(n) (hub_data[(n)]) + +#endif /* __ASM_SN_HUB_H */ diff --git a/include/asm-mips/sn/intr.h b/include/asm-mips/sn/intr.h index 4d5ae6fe00f7..6718b644b970 100644 --- a/include/asm-mips/sn/intr.h +++ b/include/asm-mips/sn/intr.h @@ -17,18 +17,14 @@ #define N_INTPENDJUNK_BITS 8 #define INTPENDJUNK_CLRBIT 0x80 -#include <asm/sn/intr_public.h> - -#ifndef __ASSEMBLY__ - /* * Macros to manipulate the interrupt register on the calling hub chip. */ -#define LOCAL_HUB_SEND_INTR(_level) LOCAL_HUB_S(PI_INT_PEND_MOD, \ - (0x100|(_level))) -#define REMOTE_HUB_SEND_INTR(_hub, _level) \ - REMOTE_HUB_S((_hub), PI_INT_PEND_MOD, (0x100|(_level))) +#define LOCAL_HUB_SEND_INTR(level) \ + LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level))) +#define REMOTE_HUB_SEND_INTR(hub, level) \ + REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level))) /* * When clearing the interrupt, make sure this clear does make it @@ -36,16 +32,19 @@ * We do an uncached load of the int_pend0 register to ensure this. */ -#define LOCAL_HUB_CLR_INTR(_level) \ - LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)), \ - LOCAL_HUB_L(PI_INT_PEND0) -#define REMOTE_HUB_CLR_INTR(_hub, _level) \ - REMOTE_HUB_S((_hub), PI_INT_PEND_MOD, (_level)), \ - REMOTE_HUB_L((_hub), PI_INT_PEND0) - -#else /* __ASSEMBLY__ */ +#define LOCAL_HUB_CLR_INTR(level) \ +do { \ + LOCAL_HUB_S(PI_INT_PEND_MOD, (level)); \ + LOCAL_HUB_L(PI_INT_PEND0); \ +} while (0); -#endif /* __ASSEMBLY__ */ +#define REMOTE_HUB_CLR_INTR(hub, level) \ +do { \ + nasid_t __hub = (hub); \ + \ + REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level)); \ + REMOTE_HUB_L(__hub, PI_INT_PEND0); \ +} while (0); /* * Hard-coded interrupt levels: @@ -63,60 +62,68 @@ */ -/* INT_PEND0 hard-coded bits. */ -#ifdef SABLE -#define SDISK_INTR 63 -#endif -#ifdef DEBUG_INTR_TSTAMP -/* hard coded interrupt level for interrupt latency test interrupt */ -#define CPU_INTRLAT_B 62 -#define CPU_INTRLAT_A 61 -#endif - -/* Hardcoded bits required by software. */ -#define MSC_MESG_INTR 13 -#define CPU_ACTION_B 11 -#define CPU_ACTION_A 10 - -/* These are determined by hardware: */ -#define CC_PEND_B 6 -#define CC_PEND_A 5 -#define UART_INTR 4 -#define PG_MIG_INTR 3 -#define GFX_INTR_B 2 -#define GFX_INTR_A 1 -#define RESERVED_INTR 0 - -/* INT_PEND1 hard-coded bits: */ -#define MSC_PANIC_INTR 63 -#define NI_ERROR_INTR 62 -#define MD_COR_ERR_INTR 61 -#define COR_ERR_INTR_B 60 -#define COR_ERR_INTR_A 59 -#define CLK_ERR_INTR 58 -#define IO_ERROR_INTR 57 /* set up by prom */ - -#define DEBUG_INTR_B 55 /* used by symmon to stop all cpus */ -#define DEBUG_INTR_A 54 - -#define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch Bridge Errors */ - -#define IP27_INTR_0 52 /* Reserved for PROM use */ -#define IP27_INTR_1 51 /* (do not use in Kernel) */ -#define IP27_INTR_2 50 -#define IP27_INTR_3 49 -#define IP27_INTR_4 48 -#define IP27_INTR_5 47 -#define IP27_INTR_6 46 -#define IP27_INTR_7 45 - -#define TLB_INTR_B 44 /* used for tlb flush random */ -#define TLB_INTR_A 43 - -#define LLP_PFAIL_INTR_B 42 /* see ml/SN/SN0/sysctlr.c */ -#define LLP_PFAIL_INTR_A 41 - -#define NI_BRDCAST_ERR_B 40 -#define NI_BRDCAST_ERR_A 39 +/* + * INT_PEND0 hard-coded bits. + */ + +/* + * INT_PEND0 bits determined by hardware: + */ +#define RESERVED_INTR 0 /* What is this bit? */ +#define GFX_INTR_A 1 +#define GFX_INTR_B 2 +#define PG_MIG_INTR 3 +#define UART_INTR 4 +#define CC_PEND_A 5 +#define CC_PEND_B 6 + +/* + * INT_PEND0 used by the kernel for itself ... + */ +#define CPU_RESCHED_A_IRQ 7 +#define CPU_RESCHED_B_IRQ 8 +#define CPU_CALL_A_IRQ 9 +#define CPU_CALL_B_IRQ 10 +#define MSC_MESG_INTR 11 +#define BASE_PCI_IRQ 12 + +/* + * INT_PEND0 again, bits determined by hardware / hardcoded: + */ +#define SDISK_INTR 63 /* SABLE name */ +#define IP_PEND0_6_63 63 /* What is this bit? */ + +/* + * INT_PEND1 hard-coded bits: + */ +#define NI_BRDCAST_ERR_A 39 +#define NI_BRDCAST_ERR_B 40 + +#define LLP_PFAIL_INTR_A 41 /* see ml/SN/SN0/sysctlr.c */ +#define LLP_PFAIL_INTR_B 42 + +#define TLB_INTR_A 43 /* used for tlb flush random */ +#define TLB_INTR_B 44 + +#define IP27_INTR_0 45 /* Reserved for PROM use */ +#define IP27_INTR_1 46 /* do not use in Kernel */ +#define IP27_INTR_2 47 +#define IP27_INTR_3 48 +#define IP27_INTR_4 49 +#define IP27_INTR_5 50 +#define IP27_INTR_6 51 +#define IP27_INTR_7 52 + +#define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch */ + /* Bridge Errors */ +#define DEBUG_INTR_A 54 +#define DEBUG_INTR_B 55 /* Used by symmon to stop all cpus */ +#define IO_ERROR_INTR 57 /* Setup by PROM */ +#define CLK_ERR_INTR 58 +#define COR_ERR_INTR_A 59 +#define COR_ERR_INTR_B 60 +#define MD_COR_ERR_INTR 61 +#define NI_ERROR_INTR 62 +#define MSC_PANIC_INTR 63 #endif /* __ASM_SN_INTR_H */ diff --git a/include/asm-mips/sn/intr_public.h b/include/asm-mips/sn/intr_public.h index 380581c7f983..7521889ad4c8 100644 --- a/include/asm-mips/sn/intr_public.h +++ b/include/asm-mips/sn/intr_public.h @@ -8,46 +8,24 @@ #ifndef __ASM_SN_INTR_PUBLIC_H #define __ASM_SN_INTR_PUBLIC_H - -/* REMEMBER: If you change these, the whole world needs to be recompiled. - * It would also require changing the hubspl.s code and SN0/intr.c - * Currently, the spl code has no support for multiple INTPEND1 masks. - */ - -#define N_INTPEND0_MASKS 1 -#define N_INTPEND1_MASKS 1 - -#define INTPEND0_MAXMASK (N_INTPEND0_MASKS - 1) -#define INTPEND1_MAXMASK (N_INTPEND1_MASKS - 1) - -#ifndef __ASSEMBLY__ #include <asm/sn/arch.h> -struct intr_vecblk_s; /* defined in asm/sn/intr.h */ - /* - * The following are necessary to create the illusion of a CEL - * on the SN0 hub. We'll add more priority levels soon, but for - * now, any interrupt in a particular band effectively does an spl. - * These must be in the PDA since they're different for each processor. - * Users of this structure must hold the vector_lock in the appropriate vector - * block before modifying the mask arrays. There's only one vector block - * for each Hub so a lock in the PDA wouldn't be adequate. + * The following are necessary to create the illusion of a CEL on the SN0 hub. + * We'll add more priority levels soon, but for now, any interrupt in a + * particular band effectively does an spl. These must be in the PDA since + * they're different for each processor. Users of this structure must hold the + * vector_lock in the appropriate vector block before modifying the mask arrays. + * There's only one vector block for each Hub so a lock in the PDA wouldn't be + * adequate. */ -typedef struct hub_intmasks_s { +struct hub_intmasks_s { /* * The masks are stored with the lowest-priority (most inclusive) * in the lowest-numbered masks (i.e., 0, 1, 2...). */ - /* INT_PEND0: */ - hubreg_t intpend0_masks[N_INTPEND0_MASKS]; - /* INT_PEND1: */ - hubreg_t intpend1_masks[N_INTPEND1_MASKS]; - /* INT_PEND0: */ - struct intr_vecblk_s *dispatch0; - /* INT_PEND1: */ - struct intr_vecblk_s *dispatch1; -} hub_intmasks_t; + hubreg_t intpend0_masks; /* INT_PEND0 */ + hubreg_t intpend1_masks; /* INT_PEND1 */ +}; -#endif /* !__ASSEMBLY__ */ #endif /* __ASM_SN_INTR_PUBLIC_H */ diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h index 7bf16e9e4f54..d028e28d6239 100644 --- a/include/asm-mips/sn/klconfig.h +++ b/include/asm-mips/sn/klconfig.h @@ -30,7 +30,9 @@ #include <linux/config.h> #include <linux/types.h> #include <asm/sn/types.h> + #if defined(CONFIG_SGI_IP27) + #include <asm/sn/sn0/addrs.h> //#include <sys/SN/router.h> // XXX Stolen from <sys/SN/router.h>: @@ -38,12 +40,16 @@ #include <asm/sn/sn0/sn0_fru.h> //#include <sys/graph.h> //#include <sys/xtalk/xbow.h> + #elif defined(CONFIG_SGI_IP35) + #include <asm/sn/sn1/addrs.h> #include <sys/sn/router.h> #include <sys/graph.h> #include <asm/xtalk/xbow.h> + #endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */ + #if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35) #include <asm/sn/agent.h> #include <asm/arc/types.h> diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h index 5f3068210bc6..398815639fb8 100644 --- a/include/asm-mips/sn/sn0/addrs.h +++ b/include/asm-mips/sn/sn0/addrs.h @@ -40,20 +40,6 @@ * use some new ANSI preprocessor stuff to paste these on where needed. */ -#define CAC_BASE 0xa800000000000000 - -#define HSPEC_BASE 0x9000000000000000 -#define IO_BASE 0x9200000000000000 -#define MSPEC_BASE 0x9400000000000000 -#define UNCAC_BASE 0x9600000000000000 - -#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) - - /* * The following couple of definitions will eventually need to be variables, * since the amount of address space assigned to each node depends on @@ -192,7 +178,7 @@ #define IP27PROM_DECOMP_SIZE 0xfff00 #define IP27PROM_BASE PHYS_TO_K0(0x01a00000) -#define IP27PROM_BASE_MAPPED (K2BASE | 0x1fc00000) +#define IP27PROM_BASE_MAPPED (UNCAC_BASE | 0x1fc00000) #define IP27PROM_SIZE_MAX 0x100000 #define IP27PROM_PCFG PHYS_TO_K0(0x01b00000) @@ -223,7 +209,7 @@ #define IO6PROM_BASE PHYS_TO_K0(0x01c00000) #define IO6PROM_SIZE 0x400000 -#define IO6PROM_BASE_MAPPED (K2BASE | 0x11c00000) +#define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000) #define IO6DPROM_BASE PHYS_TO_K0(0x01c00000) #define IO6DPROM_SIZE 0x200000 diff --git a/include/asm-mips/sn/sn0/ip27.h b/include/asm-mips/sn/sn0/ip27.h index cfa45ce6fac4..ade0e974dd78 100644 --- a/include/asm-mips/sn/sn0/ip27.h +++ b/include/asm-mips/sn/sn0/ip27.h @@ -84,14 +84,9 @@ /* Sanity hazzard ... Below all the Origin hacks are following. */ -#define CPU_RESCHED_A_IRQ 0 -#define CPU_RESCHED_B_IRQ 1 -#define CPU_CALL_A_IRQ 2 -#define CPU_CALL_B_IRQ 3 -#define BASE_PCI_IRQ 4 - #define SN00_BRIDGE 0x9200000008000000 #define SN00I_BRIDGE0 0x920000000b000000 #define SN00I_BRIDGE1 0x920000000e000000 #define SN00I_BRIDGE2 0x920000000f000000 + #endif /* _ASM_SN_SN0_IP27_H */ diff --git a/include/asm-mips/sn/sn_private.h b/include/asm-mips/sn/sn_private.h index 2715ce5db0b7..a17c0a0c911e 100644 --- a/include/asm-mips/sn/sn_private.h +++ b/include/asm-mips/sn/sn_private.h @@ -1,11 +1,20 @@ +#ifndef __ASM_SN_SN_PRIVATE_H +#define __ASM_SN_SN_PRIVATE_H + +#include <asm/sn/types.h> + extern nasid_t master_nasid; +extern void cpu_node_probe(void); extern cnodeid_t get_compact_nodeid(void); extern void hub_rtc_init(cnodeid_t); extern void cpu_time_init(void); extern void per_cpu_init(void); -extern void install_cpuintr(int cpu); -extern void install_tlbintr(int cpu); +extern void per_hub_init(cnodeid_t cnode); +extern void install_cpu_nmi_handler(int slice); +extern void install_ipi(void); extern void setup_replication_mask(int); extern void replicate_kernel_text(int); extern pfn_t node_getfirstfree(cnodeid_t); + +#endif /* __ASM_SN_SN_PRIVATE_H */ diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h index 45d01fb22530..b3bc698dfdee 100644 --- a/include/asm-mips/sni.h +++ b/include/asm-mips/sni.h @@ -78,9 +78,12 @@ /* * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned * to the other interrupts generated by ASIC PCI. + * + * INT2 is a wired-or of the push button interrupt, high temperature interrupt + * ASIC PCI interrupt. */ #define PCIMT_KEYBOARD_IRQ 1 -#define PCIMT_IRQ_INT2 16 /* What is that? */ +#define PCIMT_IRQ_INT2 16 #define PCIMT_IRQ_INTD 17 #define PCIMT_IRQ_INTC 18 #define PCIMT_IRQ_INTB 19 diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h index 871344330047..6556c10be8f0 100644 --- a/include/asm-mips/socket.h +++ b/include/asm-mips/socket.h @@ -66,7 +66,7 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse. */ #define SO_TIMESTAMP 29 #define SCM_TIMESTAMP SO_TIMESTAMP -#define SO_PEERSEC 30 +#define SO_PEERSEC 30 /* Nast libc5 fixup - bletch */ #if defined(__KERNEL__) diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h index 4a46e61ba379..0b57b65f8f21 100644 --- a/include/asm-mips/spinlock.h +++ b/include/asm-mips/spinlock.h @@ -36,7 +36,7 @@ static inline void _raw_spin_lock(spinlock_t *lock) unsigned int tmp; __asm__ __volatile__( - ".set\tnoreorder\t\t\t# spin_lock\n" + ".set\tnoreorder\t\t\t# _raw_spin_lock\n" "1:\tll\t%1, %2\n\t" "bnez\t%1, 1b\n\t" " li\t%1, 1\n\t" @@ -52,7 +52,7 @@ static inline void _raw_spin_lock(spinlock_t *lock) static inline void _raw_spin_unlock(spinlock_t *lock) { __asm__ __volatile__( - ".set\tnoreorder\t\t\t# spin_unlock\n\t" + ".set\tnoreorder\t\t\t# _raw_spin_unlock\n\t" "sync\n\t" "sw\t$0, %0\n\t" ".set\treorder" @@ -66,7 +66,7 @@ static inline unsigned int _raw_spin_trylock(spinlock_t *lock) unsigned int temp, res; __asm__ __volatile__( - ".set\tnoreorder\t\t\t# spin_trylock\n\t" + ".set\tnoreorder\t\t\t# _raw_spin_trylock\n\t" "1:\tll\t%0, %3\n\t" "ori\t%2, %0, 1\n\t" "sc\t%2, %1\n\t" @@ -104,7 +104,7 @@ static inline void _raw_read_lock(rwlock_t *rw) unsigned int tmp; __asm__ __volatile__( - ".set\tnoreorder\t\t\t# read_lock\n" + ".set\tnoreorder\t\t\t# _raw_read_lock\n" "1:\tll\t%1, %2\n\t" "bltz\t%1, 1b\n\t" " addu\t%1, 1\n\t" @@ -125,7 +125,7 @@ static inline void _raw_read_unlock(rwlock_t *rw) unsigned int tmp; __asm__ __volatile__( - ".set\tnoreorder\t\t\t# read_unlock\n" + ".set\tnoreorder\t\t\t# _raw_read_unlock\n" "1:\tll\t%1, %2\n\t" "sub\t%1, 1\n\t" "sc\t%1, %0\n\t" @@ -142,7 +142,7 @@ static inline void _raw_write_lock(rwlock_t *rw) unsigned int tmp; __asm__ __volatile__( - ".set\tnoreorder\t\t\t# write_lock\n" + ".set\tnoreorder\t\t\t# _raw_write_lock\n" "1:\tll\t%1, %2\n\t" "bnez\t%1, 1b\n\t" " lui\t%1, 0x8000\n\t" @@ -158,7 +158,7 @@ static inline void _raw_write_lock(rwlock_t *rw) static inline void _raw_write_unlock(rwlock_t *rw) { __asm__ __volatile__( - ".set\tnoreorder\t\t\t# write_unlock\n\t" + ".set\tnoreorder\t\t\t# _raw_write_unlock\n\t" "sync\n\t" "sw\t$0, %0\n\t" ".set\treorder" diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index 298dc4f6dd2e..e84aed10221b 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -26,8 +26,10 @@ .macro SAVE_TEMP mfhi v1 +#ifdef CONFIG_MIPS32 LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) +#endif LONG_S v1, PT_HI(sp) mflo v1 LONG_S $10, PT_R10(sp) @@ -79,7 +81,7 @@ mfc0 \temp, CP0_CONTEXT srl \temp, 23 sll \temp, 2 - LONG_S \stackp, kernelsp(temp) + LONG_S \stackp, kernelsp(\temp) #endif #ifdef CONFIG_MIPS64 lw \temp, TI_CPU(gp) @@ -137,6 +139,10 @@ LONG_S $6, PT_R6(sp) MFC0 v1, CP0_EPC LONG_S $7, PT_R7(sp) +#ifdef CONFIG_MIPS64 + LONG_S $8, PT_R8(sp) + LONG_S $9, PT_R9(sp) +#endif LONG_S v1, PT_EPC(sp) LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) @@ -163,8 +169,10 @@ .macro RESTORE_TEMP LONG_L $24, PT_LO(sp) +#ifdef CONFIG_MIPS32 LONG_L $8, PT_R8(sp) LONG_L $9, PT_R9(sp) +#endif mtlo $24 LONG_L $24, PT_HI(sp) LONG_L $10, PT_R10(sp) @@ -194,27 +202,32 @@ .macro RESTORE_SOME .set push .set reorder - mfc0 t0, CP0_STATUS - .set pop - ori t0, 0x1f - xori t0, 0x1f - mtc0 t0, CP0_STATUS + .set noat + mfc0 a0, CP0_STATUS + ori a0, 0x1f + xori a0, 0x1f + mtc0 a0, CP0_STATUS li v1, 0xff00 - and t0, v1 + and a0, v1 LONG_L v0, PT_STATUS(sp) nor v1, $0, v1 and v0, v1 - or v0, t0 + or v0, a0 mtc0 v0, CP0_STATUS LONG_L $31, PT_R31(sp) LONG_L $28, PT_R28(sp) LONG_L $25, PT_R25(sp) +#ifdef CONFIG_MIPS64 + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) +#endif LONG_L $7, PT_R7(sp) LONG_L $6, PT_R6(sp) LONG_L $5, PT_R5(sp) LONG_L $4, PT_R4(sp) LONG_L $3, PT_R3(sp) LONG_L $2, PT_R2(sp) + .set pop .endm .macro RESTORE_SP_AND_RET @@ -232,29 +245,34 @@ .macro RESTORE_SOME .set push .set reorder - mfc0 t0, CP0_STATUS - .set pop - ori t0, 0x1f - xori t0, 0x1f - mtc0 t0, CP0_STATUS + .set noat + mfc0 a0, CP0_STATUS + ori a0, 0x1f + xori a0, 0x1f + mtc0 a0, CP0_STATUS li v1, 0xff00 - and t0, v1 + and a0, v1 LONG_L v0, PT_STATUS(sp) nor v1, $0, v1 and v0, v1 - or v0, t0 + or v0, a0 mtc0 v0, CP0_STATUS LONG_L v1, PT_EPC(sp) MTC0 v1, CP0_EPC LONG_L $31, PT_R31(sp) LONG_L $28, PT_R28(sp) LONG_L $25, PT_R25(sp) +#ifdef CONFIG_MIPS64 + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) +#endif LONG_L $7, PT_R7(sp) LONG_L $6, PT_R6(sp) LONG_L $5, PT_R5(sp) LONG_L $4, PT_R4(sp) LONG_L $3, PT_R3(sp) LONG_L $2, PT_R2(sp) + .set pop .endm .macro RESTORE_SP_AND_RET @@ -271,18 +289,18 @@ .endm .macro RESTORE_ALL - RESTORE_SOME - RESTORE_AT RESTORE_TEMP + RESTORE_AT RESTORE_STATIC + RESTORE_SOME RESTORE_SP .endm .macro RESTORE_ALL_AND_RET - RESTORE_SOME - RESTORE_AT RESTORE_TEMP + RESTORE_AT RESTORE_STATIC + RESTORE_SOME RESTORE_SP_AND_RET .endm diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index c227061e39c5..9b7354b872f1 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h @@ -219,7 +219,7 @@ do { \ "nop\n\t" \ ".set pop" \ : /* no output */ \ - : "m" (*(int *)KSEG1) \ + : "m" (*(int *)CKSEG1) \ : "memory") #define fast_wmb() __sync() @@ -237,8 +237,8 @@ do { \ #define wmb() fast_wmb() #define rmb() fast_rmb() -#define mb() wbflush(); -#define iob() wbflush(); +#define mb() wbflush() +#define iob() wbflush() #else /* !CONFIG_CPU_HAS_WB */ @@ -280,7 +280,7 @@ do { \ (last) = resume(prev, next, next->thread_info); \ } while(0) -static inline unsigned long xchg_u32(volatile int * m, unsigned int val) +static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) { __u32 retval; @@ -296,7 +296,9 @@ static inline unsigned long xchg_u32(volatile int * m, unsigned int val) "sc\t%2, %1\n\t" "beqzl\t%2, 1b\n\t" " ll\t%0, %3\n\t" +#ifdef CONFIG_SMP "sync\n\t" +#endif ".set\tpop" : "=&r" (retval), "=m" (*m), "=&r" (dummy) : "R" (*m), "Jr" (val) @@ -314,7 +316,7 @@ static inline unsigned long xchg_u32(volatile int * m, unsigned int val) } #ifdef CONFIG_MIPS64 -static inline __u64 xchg_u64(volatile __u64 * m, __u64 long val) +static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) { __u64 retval; @@ -330,7 +332,9 @@ static inline __u64 xchg_u64(volatile __u64 * m, __u64 long val) "scd\t%2, %1\n\t" "beqzl\t%2, 1b\n\t" " lld\t%0, %3\n\t" +#ifdef CONFIG_SMP "sync\n\t" +#endif ".set\tpop" : "=&r" (retval), "=m" (*m), "=&r" (dummy) : "R" (*m), "Jr" (val) @@ -348,28 +352,128 @@ static inline __u64 xchg_u64(volatile __u64 * m, __u64 long val) } #else extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val); -#define xchg_u64 __xchg_u64_unsupported_on_32bit_kernels +#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels #endif -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) -#define tas(ptr) (xchg((ptr),1)) +/* This function doesn't exist, so you'll get a linker error + if something tries to do an invalid xchg(). */ +extern void __xchg_called_with_bad_pointer(void); static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) { switch (size) { case 4: - return xchg_u32(ptr, x); + return __xchg_u32(ptr, x); case 8: - return xchg_u64(ptr, x); + return __xchg_u64(ptr, x); } + __xchg_called_with_bad_pointer(); return x; } +#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) +#define tas(ptr) (xchg((ptr),1)) + +#define __HAVE_ARCH_CMPXCHG 1 + +static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, + unsigned long new) +{ + __u32 retval; + +#ifdef CONFIG_CPU_HAS_LLSC + __asm__ __volatile__( + " .set noat \n" + "1: ll %0, %2 # __cmpxchg_u32 \n" + " bne %0, %z3, 2f \n" + " move $1, %z4 \n" + " sc $1, %1 \n" + " beqz $1, 1b \n" +#ifdef CONFIG_SMP + " sync \n" +#endif + "2: \n" + " .set at \n" + : "=&r" (retval), "=m" (*m) + : "R" (*m), "Jr" (old), "Jr" (new) + : "memory"); +#else + unsigned long flags; + + local_irq_save(flags); + retval = *m; + if (retval == old) + *m = new; + local_irq_restore(flags); /* implies memory barrier */ +#endif + + return retval; +} + +#ifdef CONFIG_MIPS64 +static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, + unsigned long new) +{ + __u64 retval; + +#ifdef CONFIG_CPU_HAS_LLDSCD + __asm__ __volatile__( + " .set noat \n" + "1: lld %0, %2 # __cmpxchg_u64 \n" + " bne %0, %z3, 2f \n" + " move $1, %z4 \n" + " scd $1, %1 \n" + " beqz $1, 1b \n" +#ifdef CONFIG_SMP + " sync \n" +#endif + "2: \n" + " .set at \n" + : "=&r" (retval), "=m" (*m) + : "R" (*m), "Jr" (old), "Jr" (new) + : "memory"); +#else + unsigned long flags; + + local_irq_save(flags); + retval = *m; + if (retval == old) + *m = new; + local_irq_restore(flags); /* implies memory barrier */ +#endif + + return retval; +} +#else +extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels( + volatile int * m, unsigned long old, unsigned long new); +#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels +#endif + +/* This function doesn't exist, so you'll get a linker error + if something tries to do an invalid cmpxchg(). */ +extern void __cmpxchg_called_with_bad_pointer(void); + +static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, + unsigned long new, int size) +{ + switch (size) { + case 4: + return __cmpxchg_u32(ptr, old, new); + case 8: + return __cmpxchg_u64(ptr, old, new); + } + __cmpxchg_called_with_bad_pointer(); + return old; +} + +#define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr)))) + extern void *set_except_vector(int n, void *addr); extern void per_cpu_trap_init(void); -extern void __die(const char *, struct pt_regs *, const char *file, - const char *func, unsigned long line) __attribute__((noreturn)); +extern NORET_TYPE void __die(const char *, struct pt_regs *, const char *file, + const char *func, unsigned long line); extern void __die_if_kernel(const char *, struct pt_regs *, const char *file, const char *func, unsigned long line); @@ -386,4 +490,16 @@ static __inline__ int con_is_present(void) return serial_console ? 0 : 1; } +/* + * Taken from include/asm-ia64/system.h; prevents deadlock on SMP + * systems. + */ +#define prepare_arch_switch(rq, next) \ +do { \ + spin_lock(&(next)->switch_lock); \ + spin_unlock(&(rq)->lock); \ +} while (0) +#define finish_arch_switch(rq, prev) spin_unlock_irq(&(prev)->switch_lock) +#define task_running(rq, p) ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock)) + #endif /* _ASM_SYSTEM_H */ diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h index 3bf796a975d6..4906204d34fe 100644 --- a/include/asm-mips/termios.h +++ b/include/asm-mips/termios.h @@ -59,6 +59,8 @@ struct termio { }; #ifdef __KERNEL__ +#include <linux/module.h> + /* * intr=^C quit=^\ erase=del kill=^U * vmin=\1 vtime=\0 eol2=\0 swtc=\0 diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index cf54b5b41fa9..82889016dc5b 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -36,8 +36,6 @@ struct thread_info { struct restart_block restart_block; }; -#define PREEMPT_ACTIVE 0x4000000 - /* * macros/functions for gaining access to the thread information structure * @@ -64,22 +62,44 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define current_thread_info() __current_thread_info /* thread information allocation */ -#ifdef CONFIG_MIPS32 +#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS32) #define THREAD_SIZE_ORDER (1) #endif -#ifdef CONFIG_MIPS64 -#define THREAD_SIZE_ORDER (1) +#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS64) +#define THREAD_SIZE_ORDER (2) #endif +#ifdef CONFIG_PAGE_SIZE_16KB +#define THREAD_SIZE_ORDER (0) +#endif +#ifdef CONFIG_PAGE_SIZE_64KB +#define THREAD_SIZE_ORDER (0) +#endif + #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) #define THREAD_MASK (THREAD_SIZE - 1UL) -#define alloc_thread_info(task) \ - ((struct thread_info *)kmalloc(THREAD_SIZE, GFP_KERNEL)) + +#ifdef CONFIG_DEBUG_STACK_USAGE +#define alloc_thread_info(tsk) \ +({ \ + struct thread_info *ret; \ + \ + ret = kmalloc(THREAD_SIZE, GFP_KERNEL); \ + if (ret) \ + memset(ret, 0, THREAD_SIZE); \ + ret; \ +}) +#else +#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) +#endif + #define free_thread_info(info) kfree(info) #define get_thread_info(ti) get_task_struct((ti)->task) #define put_thread_info(ti) put_task_struct((ti)->task) #endif /* !__ASSEMBLY__ */ +#define PREEMPT_ACTIVE 0x4000000 + /* * thread information flags * - these are process state flags that various assembly files may need to diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index a22d7d29dd03..e22a20665871 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -33,6 +33,21 @@ extern int (*rtc_set_time)(unsigned long); extern int (*rtc_set_mmss)(unsigned long); /* + * Timer interrupt functions. + * mips_timer_state is needed for high precision timer calibration. + * mips_timer_ack may be NULL if the interrupt is self-recoverable. + */ +extern int (*mips_timer_state)(void); +extern void (*mips_timer_ack)(void); + +/* + * High precision timer functions. + * If mips_hpt_read is NULL, an R4k-compatible timer setup is attempted. + */ +extern unsigned int (*mips_hpt_read)(void); +extern void (*mips_hpt_init)(unsigned int); + +/* * to_tm() converts system time back to (year, mon, day, hour, min, sec). * It is intended to help implement rtc_set_time() functions. * Copied from PPC implementation. @@ -46,11 +61,6 @@ extern void to_tm(unsigned long tim, struct rtc_time *tm); */ extern unsigned long (*do_gettimeoffset)(void); -extern unsigned long null_gettimeoffset(void); -extern unsigned long fixed_rate_gettimeoffset(void); -extern unsigned long calibrate_div32_gettimeoffset(void); -extern unsigned long calibrate_div64_gettimeoffset(void); - /* * high-level timer interrupt routines. */ @@ -77,9 +87,10 @@ extern void (*board_time_init)(void); extern void (*board_timer_setup)(struct irqaction *irq); /* - * mips_counter_frequency - must be set if you intend to use - * counter as timer interrupt source or use fixed_rate_gettimeoffset. + * mips_hpt_frequency - must be set if you intend to use an R4k-compatible + * counter as a timer interrupt source; otherwise it can be set up + * automagically with an aid of mips_timer_state. */ -extern unsigned int mips_counter_frequency; +extern unsigned int mips_hpt_frequency; #endif /* _ASM_TIME_H */ diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h index 623e2e8d6045..3ce263092841 100644 --- a/include/asm-mips/timex.h +++ b/include/asm-mips/timex.h @@ -8,7 +8,6 @@ #ifndef _ASM_TIMEX_H #define _ASM_TIMEX_H -#include <linux/config.h> #include <asm/mipsregs.h> /* @@ -16,25 +15,23 @@ * The value should be defined as accurate as possible or under certain * circumstances Linux timekeeping might become inaccurate or fail. * - * For IP22 we cheat and pretend to have a 1MHz timer whic isn't strictly - * true - we only use the 8259 timer to calibrate the actual interrupt - * timer, so after all it's the master clock source of the system. + * For many system the exact clockrate of the timer isn't known but due to + * the way this value is used we can get away with a wrong value as long + * as this value is: + * + * - a multiple of HZ + * - a divisor of the actual rate + * + * 500000 is a good such cheat value. * * The obscure number 1193182 is the same as used by the original i8254 * time in legacy PC hardware; the chip unfortunately also found in a - * bunch of MIPS systems. + * bunch of MIPS systems. The last remaining user of the i8254 for the + * timer interrupt is the RM200; it's a very standard system so there is + * no reason to make this a separate architecture. */ -#ifdef CONFIG_ACER_PICA_61 -#define CLOCK_TICK_RATE 1193182 -#elif defined(CONFIG_MIPS_MAGNUM_4000) -#define CLOCK_TICK_RATE 1193182 -#elif defined(CONFIG_OLIVETTI_M700) -#define CLOCK_TICK_RATE 1193182 -#elif defined(CONFIG_SGI_IP22) -#define CLOCK_TICK_RATE 1000000 -#elif defined(CONFIG_SNI_RM200_PCI) -#define CLOCK_TICK_RATE 1193182 -#endif + +#include <timex.h> /* * Standard way to access the cycle counter. diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h new file mode 100644 index 000000000000..e25423d39bb5 --- /dev/null +++ b/include/asm-mips/titan_dep.h @@ -0,0 +1,68 @@ +/* + * Copyright 2003 PMC-Sierra + * Author: Manish Lachwani (lachwani@pmc-sierra.com) + * + * Board specific definititions for the PMC-Sierra Yosemite + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __TITAN_DEP_H__ +#define __TITAN_DEP_H__ + +#include <asm/addrspace.h> /* for KSEG1ADDR() */ +#include <asm/byteorder.h> /* for cpu_to_le32() */ + +/* Turn on serial */ +#define CONFIG_TITAN_SERIAL + +/* PCI */ +#define TITAN_PCI_BASE 0xbb000000 + +#define TITAN_WRITE(ofs, data) \ + *(volatile u32 *)(TITAN_PCI_BASE+(ofs)) = cpu_to_le32(data) +#define TITAN_READ(ofs, data) \ + *(data) = le32_to_cpu(*(volatile u32 *)(TITAN_PCI_BASE+(ofs))) +#define TITAN_READ_DATA(ofs) \ + le32_to_cpu(*(volatile u32 *)(TITAN_PCI_BASE+(ofs))) + +#define TITAN_WRITE_16(ofs, data) \ + *(volatile u16 *)(TITAN_PCI_BASE+(ofs)) = cpu_to_le16(data) +#define TITAN_READ_16(ofs, data) \ + *(data) = le16_to_cpu(*(volatile u16 *)(TITAN_PCI_BASE+(ofs))) + +#define TITAN_WRITE_8(ofs, data) \ + *(volatile u8 *)(TITAN_PCI_BASE+(ofs)) = data +#define TITAN_READ_8(ofs, data) \ + *(data) = *(volatile u8 *)(TITAN_PCI_BASE+(ofs)) + +/* + * PCI specific defines + */ +#define TITAN_PCI_0_CONFIG_ADDRESS 0x780 +#define TITAN_PCI_0_CONFIG_DATA 0x784 + +/* + * HT specific defines + */ +#define RM9000x2_HTLINK_REG 0xbb000644 +#define RM9000x2_BASE_ADDR 0xbb000000 +#define RM9000x2_OCD_HTCFGA 0x06f8 +#define RM9000x2_OCD_HTCFGD 0x06fc + +/* + * Hypertransport specific macros + */ +#define RM9K_WRITE(ofs, data) *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data +#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data +#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data + +#define RM9K_READ(ofs, val) *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) +#define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) +#define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) + +#endif + diff --git a/include/asm-mips/tlb.h b/include/asm-mips/tlb.h index 9376fd6fffc9..80d9dfcf1e88 100644 --- a/include/asm-mips/tlb.h +++ b/include/asm-mips/tlb.h @@ -2,9 +2,14 @@ #define __ASM_TLB_H /* - * MIPS doesn't need any special per-pte or per-vma handling.. + * MIPS doesn't need any special per-pte or per-vma handling, except + * we need to flush cache for area to be unmapped. */ -#define tlb_start_vma(tlb, vma) do { } while (0) +#define tlb_start_vma(tlb, vma) \ + do { \ + if (!tlb->fullmm) \ + flush_cache_range(vma, vma->vm_start, vma->vm_end); \ + } while (0) #define tlb_end_vma(tlb, vma) do { } while (0) #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0) diff --git a/include/asm-mips/topology.h b/include/asm-mips/topology.h index 8e85e624367f..7b18240f0586 100644 --- a/include/asm-mips/topology.h +++ b/include/asm-mips/topology.h @@ -1,6 +1,8 @@ #ifndef __ASM_TOPOLOGY_H #define __ASM_TOPOLOGY_H +#include <linux/config.h> + #ifdef CONFIG_SGI_IP27 #include <asm/mmzone.h> diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h index 94bef03d9635..6ce1e9475f99 100644 --- a/include/asm-mips/tx4927/toshiba_rbtx4927.h +++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h @@ -27,6 +27,7 @@ #ifndef __ASM_TX4927_TOSHIBA_RBTX4927_H #define __ASM_TX4927_TOSHIBA_RBTX4927_H +#include <linux/config.h> #include <asm/tx4927/tx4927.h> #include <asm/tx4927/tx4927_mips.h> #ifdef CONFIG_PCI diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h index a53c07ac052c..170433492246 100644 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ b/include/asm-mips/tx4927/tx4927_pci.h @@ -21,7 +21,7 @@ #define TX4927_CCFG_REG 0xff1fe000 #define TX4927_IRC_REG 0xff1ff600 #define TX4927_CE3 0x17f00000 /* 1M */ -#define TX4927_PCIRESET_ADDR 0x1c00f006 +#define TX4927_PCIRESET_ADDR 0xbc00f006 #define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020) #define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n)) diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h index f2e512303a4b..b949ab33e8e2 100644 --- a/include/asm-mips/types.h +++ b/include/asm-mips/types.h @@ -9,16 +9,9 @@ #ifndef _ASM_TYPES_H #define _ASM_TYPES_H -#include <linux/config.h> - #ifndef __ASSEMBLY__ -#ifdef CONFIG_MIPS32 typedef unsigned short umode_t; -#endif -#ifdef CONFIG_MIPS64 -typedef unsigned int umode_t; -#endif /* * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the @@ -59,6 +52,8 @@ typedef unsigned long long __u64; #ifndef __ASSEMBLY__ +#include <linux/config.h> + typedef __signed char s8; typedef unsigned char u8; diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index e167bbe31eff..2d259ea20d1f 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -3,12 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 1997, 1998, 1999, 2000 by Ralf Baechle + * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_UACCESS_H #define _ASM_UACCESS_H +#include <linux/config.h> +#include <linux/compiler.h> #include <linux/errno.h> #include <linux/thread_info.h> @@ -20,47 +22,43 @@ * For historical reasons, these macros are grossly misnamed. */ #ifdef CONFIG_MIPS32 + +#define __UA_LIMIT 0x80000000UL + #define __UA_ADDR ".word" #define __UA_LA "la" #define __UA_ADDU "addu" - -#define KERNEL_DS ((mm_segment_t) { (unsigned long) 0L }) -#define USER_DS ((mm_segment_t) { (unsigned long) -1L }) - -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 - -#define __access_ok(addr, size, mask) \ - (((signed long)((mask)&(addr | ((addr) + (size)) | __ua_size(size)))) >= 0) - -#define __access_mask ((long)(get_fs().seg)) - -#define access_ok(type, addr, size) \ - __access_ok(((unsigned long)(addr)),(size),__access_mask) +#define __UA_t0 "$8" +#define __UA_t1 "$9" #endif /* CONFIG_MIPS32 */ #ifdef CONFIG_MIPS64 + +#define __UA_LIMIT (- TASK_SIZE) + #define __UA_ADDR ".dword" #define __UA_LA "dla" #define __UA_ADDU "daddu" +#define __UA_t0 "$12" +#define __UA_t1 "$13" + +#endif /* CONFIG_MIPS64 */ + +/* + * USER_DS is a bitmask that has the bits set that may not be set in a valid + * userspace address. Note that we limit 32-bit userspace to 0x7fff8000 but + * the arithmetic we're doing only works if the limit is a power of two, so + * we use 0x80000000 here on 32-bit kernels. If a process passes an invalid + * address in this range it's the process's problem, not ours :-) + */ #define KERNEL_DS ((mm_segment_t) { 0UL }) -#define USER_DS ((mm_segment_t) { -TASK_SIZE }) +#define USER_DS ((mm_segment_t) { __UA_LIMIT }) #define VERIFY_READ 0 #define VERIFY_WRITE 1 -#define __access_ok(addr, size, mask) \ - (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) - -#define __access_mask get_fs().seg - -#define access_ok(type, addr, size) \ - __access_ok((unsigned long)(addr), (size), __access_mask) - -#endif /* CONFIG_MIPS64 */ - #define get_ds() (KERNEL_DS) #define get_fs() (current_thread_info()->addr_limit) #define set_fs(x) (current_thread_info()->addr_limit = (x)) @@ -84,35 +82,137 @@ #define __ua_size(size) \ ((__builtin_constant_p(size) && (signed long) (size) > 0) ? 0 : (size)) +/* + * access_ok: - Checks if a user space pointer is valid + * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that + * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe + * to write to a block, it is always safe to read from it. + * @addr: User space pointer to start of block to check + * @size: Size of block to check + * + * Context: User context only. This function may sleep. + * + * Checks if a pointer to a block of memory in user space is valid. + * + * Returns true (nonzero) if the memory block may be valid, false (zero) + * if it is definitely invalid. + * + * Note that, depending on architecture, this function probably just + * checks that the pointer is in the user space range - after calling + * this function, memory access functions may still return -EFAULT. + */ + +#define __access_mask get_fs().seg + +#define __access_ok(addr, size, mask) \ + (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0) + +#define access_ok(type, addr, size) \ + likely(__access_ok((unsigned long)(addr), (size),__access_mask)) + +/* + * verify_area: - Obsolete, use access_ok() + * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE + * @addr: User space pointer to start of block to check + * @size: Size of block to check + * + * Context: User context only. This function may sleep. + * + * This function has been replaced by access_ok(). + * + * Checks if a pointer to a block of memory in user space is valid. + * + * Returns zero if the memory block may be valid, -EFAULT + * if it is definitely invalid. + * + * See access_ok() for more details. + */ static inline int verify_area(int type, const void * addr, unsigned long size) { return access_ok(type, addr, size) ? 0 : -EFAULT; } /* - * Uh, these should become the main single-value transfer routines ... - * They automatically use the right size if we just have the right - * pointer type ... + * put_user: - Write a simple value into user space. + * @x: Value to copy to user space. + * @ptr: Destination address, in user space. + * + * Context: User context only. This function may sleep. + * + * This macro copies a single simple value from kernel space to user + * space. It supports simple types like char and int, but not larger + * data types like structures or arrays. * - * As MIPS uses the same address space for kernel and user data, we - * can just do these as direct assignments. + * @ptr must have pointer-to-simple-variable type, and @x must be assignable + * to the result of dereferencing @ptr. * - * Careful to not - * (a) re-use the arguments for side effects (sizeof is ok) - * (b) require any knowledge of processes at this stage + * Returns zero on success, or -EFAULT on error. */ #define put_user(x,ptr) \ __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) + +/* + * get_user: - Get a simple variable from user space. + * @x: Variable to store result. + * @ptr: Source address, in user space. + * + * Context: User context only. This function may sleep. + * + * This macro copies a single simple variable from user space to kernel + * space. It supports simple types like char and int, but not larger + * data types like structures or arrays. + * + * @ptr must have pointer-to-simple-variable type, and the result of + * dereferencing @ptr must be assignable to @x without a cast. + * + * Returns zero on success, or -EFAULT on error. + * On error, the variable @x is set to zero. + */ #define get_user(x,ptr) \ __get_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) /* - * The "__xxx" versions do not do address space checking, useful when - * doing multiple accesses to the same area (the user has to do the - * checks by hand with "access_ok()") + * __put_user: - Write a simple value into user space, with less checking. + * @x: Value to copy to user space. + * @ptr: Destination address, in user space. + * + * Context: User context only. This function may sleep. + * + * This macro copies a single simple value from kernel space to user + * space. It supports simple types like char and int, but not larger + * data types like structures or arrays. + * + * @ptr must have pointer-to-simple-variable type, and @x must be assignable + * to the result of dereferencing @ptr. + * + * Caller must check the pointer with access_ok() before calling this + * function. + * + * Returns zero on success, or -EFAULT on error. */ #define __put_user(x,ptr) \ __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) + +/* + * __get_user: - Get a simple variable from user space, with less checking. + * @x: Variable to store result. + * @ptr: Source address, in user space. + * + * Context: User context only. This function may sleep. + * + * This macro copies a single simple variable from user space to kernel + * space. It supports simple types like char and int, but not larger + * data types like structures or arrays. + * + * @ptr must have pointer-to-simple-variable type, and the result of + * dereferencing @ptr must be assignable to @x without a cast. + * + * Caller must check the pointer with access_ok() before calling this + * function. + * + * Returns zero on success, or -EFAULT on error. + * On error, the variable @x is set to zero. + */ #define __get_user(x,ptr) \ __get_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) @@ -134,6 +234,7 @@ struct __large_struct { unsigned long buf[100]; }; long __gu_err; \ __typeof(*(ptr)) __gu_val; \ long __gu_addr; \ + might_sleep(); \ __asm__("":"=r" (__gu_val)); \ __gu_addr = (long) (ptr); \ __asm__("":"=r" (__gu_err)); \ @@ -146,65 +247,66 @@ struct __large_struct { unsigned long buf[100]; }; } x = (__typeof__(*(ptr))) __gu_val; __gu_err; \ }) -#define __get_user_check(x,ptr,size) \ -({ \ - long __gu_err; \ - __typeof__(*(ptr)) __gu_val; \ - long __gu_addr; \ - __asm__("":"=r" (__gu_val)); \ - __gu_addr = (long) (ptr); \ - __asm__("":"=r" (__gu_err)); \ - if (__access_ok(__gu_addr,size,__access_mask)) { \ - switch (size) { \ - case 1: __get_user_asm("lb"); break; \ - case 2: __get_user_asm("lh"); break; \ - case 4: __get_user_asm("lw"); break; \ - case 8: __GET_USER_DW; break; \ - default: __get_user_unknown(); break; \ - } \ - } x = (__typeof__(*(ptr))) __gu_val; __gu_err; \ +#define __get_user_check(x,ptr,size) \ +({ \ + long __gu_err; \ + __typeof__(*(ptr)) __gu_val; \ + long __gu_addr; \ + might_sleep(); \ + __asm__("":"=r" (__gu_val)); \ + __gu_addr = (long) (ptr); \ + __asm__("":"=r" (__gu_err)); \ + if (access_ok(VERIFY_READ,__gu_addr,size)) { \ + switch (size) { \ + case 1: __get_user_asm("lb"); break; \ + case 2: __get_user_asm("lh"); break; \ + case 4: __get_user_asm("lw"); break; \ + case 8: __GET_USER_DW; break; \ + default: __get_user_unknown(); break; \ + } \ + } x = (__typeof__(*(ptr))) __gu_val; __gu_err; \ }) -#define __get_user_asm(insn) \ -({ \ - __asm__ __volatile__( \ - "1:\t" insn "\t%1,%2\n\t" \ - "move\t%0,$0\n" \ - "2:\n\t" \ - ".section\t.fixup,\"ax\"\n" \ - "3:\tli\t%0,%3\n\t" \ - "move\t%1,$0\n\t" \ - "j\t2b\n\t" \ - ".previous\n\t" \ - ".section\t__ex_table,\"a\"\n\t" \ - __UA_ADDR "\t1b,3b\n\t" \ - ".previous" \ - :"=r" (__gu_err), "=r" (__gu_val) \ - :"o" (__m(__gu_addr)), "i" (-EFAULT)); \ +#define __get_user_asm(insn) \ +({ \ + __asm__ __volatile__( \ + "1:\t" insn "\t%1,%2\n\t" \ + "move\t%0,$0\n" \ + "2:\n\t" \ + ".section\t.fixup,\"ax\"\n" \ + "3:\tli\t%0,%3\n\t" \ + "move\t%1,$0\n\t" \ + "j\t2b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + __UA_ADDR "\t1b,3b\n\t" \ + ".previous" \ + :"=r" (__gu_err), "=r" (__gu_val) \ + :"o" (__m(__gu_addr)), "i" (-EFAULT)); \ }) /* * Get a long long 64 using 32 bit registers. */ -#define __get_user_asm_ll32 \ -({ \ - __asm__ __volatile__( \ - "1:\tlw\t%1,%2\n" \ - "2:\tlw\t%D1,%3\n\t" \ - "move\t%0,$0\n" \ - "3:\t.section\t.fixup,\"ax\"\n" \ - "4:\tli\t%0,%4\n\t" \ - "move\t%1,$0\n\t" \ - "move\t%D1,$0\n\t" \ - "j\t3b\n\t" \ - ".previous\n\t" \ - ".section\t__ex_table,\"a\"\n\t" \ - __UA_ADDR "\t1b,4b\n\t" \ - __UA_ADDR "\t2b,4b\n\t" \ - ".previous" \ - :"=r" (__gu_err), "=&r" (__gu_val) \ - :"o" (__m(__gu_addr)), "o" (__m(__gu_addr + 4)), \ - "i" (-EFAULT)); \ +#define __get_user_asm_ll32 \ +({ \ + __asm__ __volatile__( \ + "1:\tlw\t%1,%2\n" \ + "2:\tlw\t%D1,%3\n\t" \ + "move\t%0,$0\n" \ + "3:\t.section\t.fixup,\"ax\"\n" \ + "4:\tli\t%0,%4\n\t" \ + "move\t%1,$0\n\t" \ + "move\t%D1,$0\n\t" \ + "j\t3b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + __UA_ADDR "\t1b,4b\n\t" \ + __UA_ADDR "\t2b,4b\n\t" \ + ".previous" \ + :"=r" (__gu_err), "=&r" (__gu_val) \ + :"o" (__m(__gu_addr)), "o" (__m(__gu_addr + 4)), \ + "i" (-EFAULT)); \ }) extern void __get_user_unknown(void); @@ -219,59 +321,61 @@ extern void __get_user_unknown(void); #define __PUT_USER_DW __put_user_asm_ll32 #endif -#define __put_user_nocheck(x,ptr,size) \ -({ \ - long __pu_err; \ - __typeof__(*(ptr)) __pu_val; \ - long __pu_addr; \ - __pu_val = (x); \ - __pu_addr = (long) (ptr); \ - __asm__("":"=r" (__pu_err)); \ - switch (size) { \ - case 1: __put_user_asm("sb"); break; \ - case 2: __put_user_asm("sh"); break; \ - case 4: __put_user_asm("sw"); break; \ - case 8: __PUT_USER_DW; break; \ - default: __put_user_unknown(); break; \ - } \ - __pu_err; \ +#define __put_user_nocheck(x,ptr,size) \ +({ \ + long __pu_err; \ + __typeof__(*(ptr)) __pu_val; \ + long __pu_addr; \ + might_sleep(); \ + __pu_val = (x); \ + __pu_addr = (long) (ptr); \ + __asm__("":"=r" (__pu_err)); \ + switch (size) { \ + case 1: __put_user_asm("sb"); break; \ + case 2: __put_user_asm("sh"); break; \ + case 4: __put_user_asm("sw"); break; \ + case 8: __PUT_USER_DW; break; \ + default: __put_user_unknown(); break; \ + } \ + __pu_err; \ }) -#define __put_user_check(x,ptr,size) \ -({ \ - long __pu_err; \ - __typeof__(*(ptr)) __pu_val; \ - long __pu_addr; \ - __pu_val = (x); \ - __pu_addr = (long) (ptr); \ - __asm__("":"=r" (__pu_err)); \ - if (__access_ok(__pu_addr,size,__access_mask)) { \ - switch (size) { \ - case 1: __put_user_asm("sb"); break; \ - case 2: __put_user_asm("sh"); break; \ - case 4: __put_user_asm("sw"); break; \ - case 8: __PUT_USER_DW; break; \ - default: __put_user_unknown(); break; \ - } \ - } \ - __pu_err; \ +#define __put_user_check(x,ptr,size) \ +({ \ + long __pu_err; \ + __typeof__(*(ptr)) __pu_val; \ + long __pu_addr; \ + might_sleep(); \ + __pu_val = (x); \ + __pu_addr = (long) (ptr); \ + __asm__("":"=r" (__pu_err)); \ + if (access_ok(VERIFY_WRITE, __pu_addr, size)) { \ + switch (size) { \ + case 1: __put_user_asm("sb"); break; \ + case 2: __put_user_asm("sh"); break; \ + case 4: __put_user_asm("sw"); break; \ + case 8: __PUT_USER_DW; break; \ + default: __put_user_unknown(); break; \ + } \ + } \ + __pu_err; \ }) -#define __put_user_asm(insn) \ -({ \ - __asm__ __volatile__( \ - "1:\t" insn "\t%z1, %2\t\t\t# __put_user_asm\n\t" \ - "move\t%0, $0\n" \ - "2:\n\t" \ - ".section\t.fixup,\"ax\"\n" \ - "3:\tli\t%0,%3\n\t" \ - "j\t2b\n\t" \ - ".previous\n\t" \ - ".section\t__ex_table,\"a\"\n\t" \ - __UA_ADDR "\t1b,3b\n\t" \ - ".previous" \ - :"=r" (__pu_err) \ - :"Jr" (__pu_val), "o" (__m(__pu_addr)), "i" (-EFAULT)); \ +#define __put_user_asm(insn) \ +({ \ + __asm__ __volatile__( \ + "1:\t" insn "\t%z1, %2\t\t\t# __put_user_asm\n\t" \ + "move\t%0, $0\n" \ + "2:\n\t" \ + ".section\t.fixup,\"ax\"\n" \ + "3:\tli\t%0,%3\n\t" \ + "j\t2b\n\t" \ + ".previous\n\t" \ + ".section\t__ex_table,\"a\"\n\t" \ + __UA_ADDR "\t1b,3b\n\t" \ + ".previous" \ + :"=r" (__pu_err) \ + :"Jr" (__pu_val), "o" (__m(__pu_addr)), "i" (-EFAULT)); \ }) #define __put_user_asm_ll32 \ @@ -331,12 +435,27 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); __cu_len_r; \ }) +/* + * __copy_to_user: - Copy a block of data into user space, with less checking. + * @to: Destination address, in user space. + * @from: Source address, in kernel space. + * @n: Number of bytes to copy. + * + * Context: User context only. This function may sleep. + * + * Copy data from kernel space to user space. Caller must check + * the specified block with access_ok() before calling this function. + * + * Returns number of bytes that could not be copied. + * On success, this will be zero. + */ #define __copy_to_user(to,from,n) \ ({ \ void *__cu_to; \ const void *__cu_from; \ long __cu_len; \ \ + might_sleep(); \ __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ @@ -344,12 +463,26 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); __cu_len; \ }) +/* + * copy_to_user: - Copy a block of data into user space. + * @to: Destination address, in user space. + * @from: Source address, in kernel space. + * @n: Number of bytes to copy. + * + * Context: User context only. This function may sleep. + * + * Copy data from kernel space to user space. + * + * Returns number of bytes that could not be copied. + * On success, this will be zero. + */ #define copy_to_user(to,from,n) \ ({ \ void *__cu_to; \ const void *__cu_from; \ long __cu_len; \ \ + might_sleep(); \ __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ @@ -383,12 +516,29 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); __cu_len_r; \ }) +/* + * __copy_from_user: - Copy a block of data from user space, with less checking. * @to: Destination address, in kernel space. + * @from: Source address, in user space. + * @n: Number of bytes to copy. + * + * Context: User context only. This function may sleep. + * + * Copy data from user space to kernel space. Caller must check + * the specified block with access_ok() before calling this function. + * + * Returns number of bytes that could not be copied. + * On success, this will be zero. + * + * If some data could not be copied, this function will pad the copied + * data to the requested size using zero bytes. + */ #define __copy_from_user(to,from,n) \ ({ \ void *__cu_to; \ const void *__cu_from; \ long __cu_len; \ \ + might_sleep(); \ __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ @@ -397,12 +547,29 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); __cu_len; \ }) +/* + * copy_from_user: - Copy a block of data from user space. + * @to: Destination address, in kernel space. + * @from: Source address, in user space. + * @n: Number of bytes to copy. + * + * Context: User context only. This function may sleep. + * + * Copy data from user space to kernel space. + * + * Returns number of bytes that could not be copied. + * On success, this will be zero. + * + * If some data could not be copied, this function will pad the copied + * data to the requested size using zero bytes. + */ #define copy_from_user(to,from,n) \ ({ \ void *__cu_to; \ const void *__cu_from; \ long __cu_len; \ \ + might_sleep(); \ __cu_to = (to); \ __cu_from = (from); \ __cu_len = (n); \ @@ -412,11 +579,25 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); __cu_len; \ }) +#define __copy_in_user(to, from, n) __copy_from_user(to, from, n) + +/* + * __clear_user: - Zero a block of memory in user space, with less checking. + * @to: Destination address, in user space. + * @n: Number of bytes to zero. + * + * Zero a block of memory in user space. Caller must check + * the specified block with access_ok() before calling this function. + * + * Returns number of bytes that could not be cleared. + * On success, this will be zero. + */ static inline __kernel_size_t __clear_user(void *addr, __kernel_size_t size) { __kernel_size_t res; + might_sleep(); __asm__ __volatile__( "move\t$4, %1\n\t" "move\t$5, $0\n\t" @@ -425,30 +606,47 @@ __clear_user(void *addr, __kernel_size_t size) "move\t%0, $6" : "=r" (res) : "r" (addr), "r" (size) - : "$4", "$5", "$6", "$8", "$9", "$31"); + : "$4", "$5", "$6", __UA_t0, __UA_t1, "$31"); return res; } -#define clear_user(addr,n) \ -({ \ - void * __cl_addr = (addr); \ - unsigned long __cl_size = (n); \ - if (__cl_size && access_ok(VERIFY_WRITE, \ - ((unsigned long)(__cl_addr)), __cl_size)) \ - __cl_size = __clear_user(__cl_addr, __cl_size); \ - __cl_size; \ +#define clear_user(addr,n) \ +({ \ + void * __cl_addr = (addr); \ + unsigned long __cl_size = (n); \ + if (__cl_size && access_ok(VERIFY_WRITE, \ + ((unsigned long)(__cl_addr)), __cl_size)) \ + __cl_size = __clear_user(__cl_addr, __cl_size); \ + __cl_size; \ }) /* - * Returns: -EFAULT if exception before terminator, N if the entire - * buffer filled, else strlen. + * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking. + * @dst: Destination address, in kernel space. This buffer must be at + * least @count bytes long. + * @src: Source address, in user space. + * @count: Maximum number of bytes to copy, including the trailing NUL. + * + * Copies a NUL-terminated string from userspace to kernel space. + * Caller must check the specified block with access_ok() before calling + * this function. + * + * On success, returns the length of the string (not including the trailing + * NUL). + * + * If access to userspace fails, returns -EFAULT (some data may have been + * copied). + * + * If @count is smaller than the length of the string, copies @count bytes + * and returns @count. */ static inline long __strncpy_from_user(char *__to, const char *__from, long __len) { long res; + might_sleep(); __asm__ __volatile__( "move\t$4, %1\n\t" "move\t$5, %2\n\t" @@ -457,16 +655,35 @@ __strncpy_from_user(char *__to, const char *__from, long __len) "move\t%0, $2" : "=r" (res) : "r" (__to), "r" (__from), "r" (__len) - : "$2", "$3", "$4", "$5", "$6", "$8", "$31", "memory"); + : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); return res; } +/* + * strncpy_from_user: - Copy a NUL terminated string from userspace. + * @dst: Destination address, in kernel space. This buffer must be at + * least @count bytes long. + * @src: Source address, in user space. + * @count: Maximum number of bytes to copy, including the trailing NUL. + * + * Copies a NUL-terminated string from userspace to kernel space. + * + * On success, returns the length of the string (not including the trailing + * NUL). + * + * If access to userspace fails, returns -EFAULT (some data may have been + * copied). + * + * If @count is smaller than the length of the string, copies @count bytes + * and returns @count. + */ static inline long strncpy_from_user(char *__to, const char *__from, long __len) { long res; + might_sleep(); __asm__ __volatile__( "move\t$4, %1\n\t" "move\t$5, %2\n\t" @@ -475,7 +692,7 @@ strncpy_from_user(char *__to, const char *__from, long __len) "move\t%0, $2" : "=r" (res) : "r" (__to), "r" (__from), "r" (__len) - : "$2", "$3", "$4", "$5", "$6", "$8", "$31", "memory"); + : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory"); return res; } @@ -485,28 +702,44 @@ static inline long __strlen_user(const char *s) { long res; + might_sleep(); __asm__ __volatile__( "move\t$4, %1\n\t" __MODULE_JAL(__strlen_user_nocheck_asm) "move\t%0, $2" : "=r" (res) : "r" (s) - : "$2", "$4", "$8", "$31"); + : "$2", "$4", __UA_t0, "$31"); return res; } +/* + * strlen_user: - Get the size of a string in user space. + * @str: The string to measure. + * + * Context: User context only. This function may sleep. + * + * Get the size of a NUL-terminated string in user space. + * + * Returns the size of the string INCLUDING the terminating NUL. + * On exception, returns 0. + * + * If there is a limit on the length of a valid string, you may wish to + * consider using strnlen_user() instead. + */ static inline long strlen_user(const char *s) { long res; + might_sleep(); __asm__ __volatile__( "move\t$4, %1\n\t" __MODULE_JAL(__strlen_user_asm) "move\t%0, $2" : "=r" (res) : "r" (s) - : "$2", "$4", "$8", "$31"); + : "$2", "$4", __UA_t0, "$31"); return res; } @@ -516,6 +749,7 @@ static inline long __strnlen_user(const char *s, long n) { long res; + might_sleep(); __asm__ __volatile__( "move\t$4, %1\n\t" "move\t$5, %2\n\t" @@ -523,15 +757,30 @@ static inline long __strnlen_user(const char *s, long n) "move\t%0, $2" : "=r" (res) : "r" (s), "r" (n) - : "$2", "$4", "$5", "$8", "$31"); + : "$2", "$4", "$5", __UA_t0, "$31"); return res; } +/* + * strlen_user: - Get the size of a string in user space. + * @str: The string to measure. + * + * Context: User context only. This function may sleep. + * + * Get the size of a NUL-terminated string in user space. + * + * Returns the size of the string INCLUDING the terminating NUL. + * On exception, returns 0. + * + * If there is a limit on the length of a valid string, you may wish to + * consider using strnlen_user() instead. + */ static inline long strnlen_user(const char *s, long n) { long res; + might_sleep(); __asm__ __volatile__( "move\t$4, %1\n\t" "move\t$5, %2\n\t" @@ -539,7 +788,7 @@ static inline long strnlen_user(const char *s, long n) "move\t%0, $2" : "=r" (res) : "r" (s), "r" (n) - : "$2", "$4", "$5", "$8", "$31"); + : "$2", "$4", "$5", __UA_t0, "$31"); return res; } @@ -550,4 +799,6 @@ struct exception_table_entry unsigned long nextinsn; }; +extern int fixup_exception(struct pt_regs *regs); + #endif /* _ASM_UACCESS_H */ diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h index de71d13ec5b9..7bfeabc1de0e 100644 --- a/include/asm-mips/unaligned.h +++ b/include/asm-mips/unaligned.h @@ -58,19 +58,19 @@ struct __una_u16 { __u16 x __attribute__((packed)); }; * Elemental unaligned loads */ -extern inline __u64 __uldq(const __u64 * r11) +static inline __u64 __uldq(const __u64 * r11) { const struct __una_u64 *ptr = (const struct __una_u64 *) r11; return ptr->x; } -extern inline __u32 __uldl(const __u32 * r11) +static inline __u32 __uldl(const __u32 * r11) { const struct __una_u32 *ptr = (const struct __una_u32 *) r11; return ptr->x; } -extern inline __u16 __uldw(const __u16 * r11) +static inline __u16 __uldw(const __u16 * r11) { const struct __una_u16 *ptr = (const struct __una_u16 *) r11; return ptr->x; @@ -80,25 +80,25 @@ extern inline __u16 __uldw(const __u16 * r11) * Elemental unaligned stores */ -extern inline void __ustq(__u64 r5, __u64 * r11) +static inline void __ustq(__u64 r5, __u64 * r11) { struct __una_u64 *ptr = (struct __una_u64 *) r11; ptr->x = r5; } -extern inline void __ustl(__u32 r5, __u32 * r11) +static inline void __ustl(__u32 r5, __u32 * r11) { struct __una_u32 *ptr = (struct __una_u32 *) r11; ptr->x = r5; } -extern inline void __ustw(__u16 r5, __u16 * r11) +static inline void __ustw(__u16 r5, __u16 * r11) { struct __una_u16 *ptr = (struct __una_u16 *) r11; ptr->x = r5; } -extern inline __u64 __get_unaligned(const void *ptr, size_t size) +static inline __u64 __get_unaligned(const void *ptr, size_t size) { __u64 val; @@ -121,7 +121,7 @@ extern inline __u64 __get_unaligned(const void *ptr, size_t size) return val; } -extern inline void __put_unaligned(__u64 val, void *ptr, size_t size) +static inline void __put_unaligned(__u64 val, void *ptr, size_t size) { switch (size) { case 1: diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index 7977d9c20f2b..d2b9429d1f07 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -498,7 +498,7 @@ #define __NR_lremovexattr (__NR_Linux + 190) #define __NR_fremovexattr (__NR_Linux + 191) #define __NR_tkill (__NR_Linux + 192) -#define __NR_time (__NR_Linux + 193) +#define __NR_reserved193 (__NR_Linux + 193) #define __NR_futex (__NR_Linux + 194) #define __NR_sched_setaffinity (__NR_Linux + 195) #define __NR_sched_getaffinity (__NR_Linux + 196) @@ -742,7 +742,7 @@ #define __NR_lremovexattr (__NR_Linux + 190) #define __NR_fremovexattr (__NR_Linux + 191) #define __NR_tkill (__NR_Linux + 192) -#define __NR_time (__NR_Linux + 193) +#define __NR_reserved193 (__NR_Linux + 193) #define __NR_futex (__NR_Linux + 194) #define __NR_sched_setaffinity (__NR_Linux + 195) #define __NR_sched_getaffinity (__NR_Linux + 196) @@ -769,27 +769,27 @@ #define __NR_statfs64 (__NR_Linux + 217) #define __NR_fstatfs64 (__NR_Linux + 218) #define __NR_sendfile64 (__NR_Linux + 219) -#define __NR_timer_create (__NR_Linux + 221) -#define __NR_timer_settime (__NR_Linux + 222) -#define __NR_timer_gettime (__NR_Linux + 223) -#define __NR_timer_getoverrun (__NR_Linux + 224) -#define __NR_timer_delete (__NR_Linux + 225) -#define __NR_clock_settime (__NR_Linux + 226) -#define __NR_clock_gettime (__NR_Linux + 227) -#define __NR_clock_getres (__NR_Linux + 228) -#define __NR_clock_nanosleep (__NR_Linux + 229) -#define __NR_tgkill (__NR_Linux + 230) -#define __NR_utimes (__NR_Linux + 231) +#define __NR_timer_create (__NR_Linux + 220) +#define __NR_timer_settime (__NR_Linux + 221) +#define __NR_timer_gettime (__NR_Linux + 222) +#define __NR_timer_getoverrun (__NR_Linux + 223) +#define __NR_timer_delete (__NR_Linux + 224) +#define __NR_clock_settime (__NR_Linux + 225) +#define __NR_clock_gettime (__NR_Linux + 226) +#define __NR_clock_getres (__NR_Linux + 227) +#define __NR_clock_nanosleep (__NR_Linux + 228) +#define __NR_tgkill (__NR_Linux + 229) +#define __NR_utimes (__NR_Linux + 230) /* * Offset of the last N32 flavoured syscall */ -#define __NR_Linux_syscalls 231 +#define __NR_Linux_syscalls 230 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */ #define __NR_N32_Linux 6000 -#define __NR_N32_Linux_syscalls 231 +#define __NR_N32_Linux_syscalls 230 #ifndef __ASSEMBLY__ @@ -1059,7 +1059,6 @@ type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \ * won't be any messing with the stack from main(), but we define * some others too. */ -#define __NR__exit __NR_exit static inline _syscall0(pid_t,setsid) static inline _syscall3(int,write,int,fd,const char *,buf,off_t,count) static inline _syscall3(int,read,int,fd,char *,buf,off_t,count) @@ -1068,7 +1067,6 @@ static inline _syscall1(int,dup,int,fd) static inline _syscall3(int,execve,const char *,file,char **,argv,char **,envp) static inline _syscall3(int,open,const char *,file,int,flag,int,mode) static inline _syscall1(int,close,int,fd) -static inline _syscall1(int,_exit,int,exitcode) struct rusage; static inline _syscall4(pid_t,wait4,pid_t,pid,int *,stat_addr,int,options,struct rusage *,ru) diff --git a/include/asm-mips/vr41xx/mpc30x.h b/include/asm-mips/vr41xx/mpc30x.h index 5c0b64ebe754..bff9f0aafcce 100644 --- a/include/asm-mips/vr41xx/mpc30x.h +++ b/include/asm-mips/vr41xx/mpc30x.h @@ -16,8 +16,6 @@ #ifndef __VICTOR_MPC30X_H #define __VICTOR_MPC30X_H -#include <linux/config.h> - #include <asm/addrspace.h> #include <asm/vr41xx/vr41xx.h> diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h index bc6308c68544..f4ab4b029a9c 100644 --- a/include/asm-mips/vr41xx/vr41xx.h +++ b/include/asm-mips/vr41xx/vr41xx.h @@ -7,6 +7,7 @@ * Copyright (C) 2001, 2002 Paul Mundt * Copyright (C) 2002 MontaVista Software, Inc. * Copyright (C) 2002 TimeSys Corp. + * Copyright (C) 2003 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -32,23 +33,44 @@ #define PRID_VR4181A_REV1_0 0x00000c73 #define PRID_VR4181A_REV1_1 0x00000c74 -/* VR4131 0x00000c80-0x00000c8f */ +/* VR4131 0x00000c80-0x00000c83 */ #define PRID_VR4131_REV1_2 0x00000c80 #define PRID_VR4131_REV2_0 0x00000c81 #define PRID_VR4131_REV2_1 0x00000c82 #define PRID_VR4131_REV2_2 0x00000c83 +/* VR4133 0x00000c84- */ +#define PRID_VR4133 0x00000c84 + /* * Bus Control Uint */ extern void vr41xx_bcu_init(void); +extern unsigned long vr41xx_get_vtclock_frequency(void); +extern unsigned long vr41xx_get_tclock_frequency(void); /* * Clock Mask Unit */ -extern void vr41xx_cmu_init(u16 mask); -extern void vr41xx_clock_supply(u16 mask); -extern void vr41xx_clock_mask(u16 mask); +extern void vr41xx_cmu_init(void); +extern void vr41xx_clock_supply(unsigned int clock); +extern void vr41xx_clock_mask(unsigned int clock); + +enum { + PIU_CLOCK, + SIU_CLOCK, + AIU_CLOCK, + KIU_CLOCK, + FIR_CLOCK, + DSIU_CLOCK, + CSI_CLOCK, + PCIU_CLOCK, + HSP_CLOCK, + PCI_CLOCK, + CEU_CLOCK, + ETHER0_CLOCK, + ETHER1_CLOCK +}; /* * Interrupt Control Unit @@ -58,59 +80,84 @@ extern void vr41xx_clock_mask(u16 mask); #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) #define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0) #define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1) -#define ICU_CASCADE_IRQ MIPS_CPU_IRQ(2) -#define RTC_LONG1_IRQ MIPS_CPU_IRQ(3) -#define RTC_LONG2_IRQ MIPS_CPU_IRQ(4) -/* RFU */ -#define BATTERY_IRQ MIPS_CPU_IRQ(6) +#define INT0_CASCADE_IRQ MIPS_CPU_IRQ(2) +#define INT1_CASCADE_IRQ MIPS_CPU_IRQ(3) +#define INT2_CASCADE_IRQ MIPS_CPU_IRQ(4) +#define INT3_CASCADE_IRQ MIPS_CPU_IRQ(5) +#define INT4_CASCADE_IRQ MIPS_CPU_IRQ(6) #define MIPS_COUNTER_IRQ MIPS_CPU_IRQ(7) /* SYINT1 Interrupt Numbers */ #define SYSINT1_IRQ_BASE 8 #define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x)) -/* RFU */ +#define BATTRY_IRQ SYSINT1_IRQ(0) #define POWER_IRQ SYSINT1_IRQ(1) +#define RTCLONG1_IRQ SYSINT1_IRQ(2) +#define ELAPSEDTIME_IRQ SYSINT1_IRQ(3) /* RFU */ +#define PIU_IRQ SYSINT1_IRQ(5) +#define AIU_IRQ SYSINT1_IRQ(6) +#define KIU_IRQ SYSINT1_IRQ(7) #define GIUINT_CASCADE_IRQ SYSINT1_IRQ(8) #define SIU_IRQ SYSINT1_IRQ(9) -/* RFU */ +#define BUSERR_IRQ SYSINT1_IRQ(10) #define SOFTINT_IRQ SYSINT1_IRQ(11) #define CLKRUN_IRQ SYSINT1_IRQ(12) -#define SYSINT1_IRQ_LAST CLKRUN_IRQ +#define DOZEPIU_IRQ SYSINT1_IRQ(13) +#define SYSINT1_IRQ_LAST DOZEPIU_IRQ /* SYSINT2 Interrupt Numbers */ #define SYSINT2_IRQ_BASE 24 #define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x)) -/* RFU */ +#define RTCLONG2_IRQ SYSINT2_IRQ(0) #define LED_IRQ SYSINT2_IRQ(1) -/* RFU */ -#define VTCLOCK_IRQ SYSINT2_IRQ(3) +#define HSP_IRQ SYSINT2_IRQ(2) +#define TCLOCK_IRQ SYSINT2_IRQ(3) #define FIR_IRQ SYSINT2_IRQ(4) +#define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */ #define DSIU_IRQ SYSINT2_IRQ(5) #define PCI_IRQ SYSINT2_IRQ(6) #define SCU_IRQ SYSINT2_IRQ(7) #define CSI_IRQ SYSINT2_IRQ(8) #define BCU_IRQ SYSINT2_IRQ(9) -#define SYSINT2_IRQ_LAST BCU_IRQ +#define ETHERNET_IRQ SYSINT2_IRQ(10) +#define SYSINT2_IRQ_LAST ETHERNET_IRQ /* GIU Interrupt Numbers */ #define GIU_IRQ_BASE 40 #define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */ #define GIU_IRQ_LAST GIU_IRQ(31) +#define GIU_IRQ_TO_PIN(x) ((x) - GIU_IRQ_BASE) /* Pin 0-31 */ extern void (*board_irq_init)(void); +extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)); /* - * Gegeral-Purpose I/O Unit + * Power Management Unit */ -extern void vr41xx_enable_giuint(int pin); -extern void vr41xx_disable_giuint(int pin); -extern void vr41xx_clear_giuint(int pin); +extern void vr41xx_pmu_init(void); +/* + * RTC + */ +extern void vr41xx_set_rtclong1_cycle(uint32_t cycles); +extern uint32_t vr41xx_read_rtclong1_counter(void); + +extern void vr41xx_set_rtclong2_cycle(uint32_t cycles); +extern uint32_t vr41xx_read_rtclong2_counter(void); + +extern void vr41xx_set_tclock_cycle(uint32_t cycles); +extern uint32_t vr41xx_read_tclock_counter(void); + +/* + * General-Purpose I/O Unit + */ enum { TRIGGER_LEVEL, - TRIGGER_EDGE + TRIGGER_EDGE, + TRIGGER_EDGE_FALLING, + TRIGGER_EDGE_RISING }; enum { @@ -185,8 +232,4 @@ extern void vr41xx_pciu_init(struct vr41xx_pci_address_map *map); extern void vr41xx_time_init(void); extern void vr41xx_timer_setup(struct irqaction *irq); -extern void vr41xx_restart(char *command); -extern void vr41xx_halt(void); -extern void vr41xx_power_off(void); - #endif /* __NEC_VR41XX_H */ diff --git a/include/asm-mips/vr41xx/vrc4171.h b/include/asm-mips/vr41xx/vrc4171.h new file mode 100644 index 000000000000..ff9693627005 --- /dev/null +++ b/include/asm-mips/vr41xx/vrc4171.h @@ -0,0 +1,43 @@ +/* + * vrc4171.h, Include file for NEC VRC4171. + * + * Copyright (C) 2003 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __NEC_VRC4171_H +#define __NEC_VRC4171_H + +/* + * Configuration 1 + */ +enum { + SLOTB_IS_NONE, + SLOTB_IS_PCCARD, + SLOTB_IS_CF, + SLOTB_IS_FLASHROM +}; + +extern void vrc4171_set_multifunction_pin(int config); + +/* + * Interrupt Status Mask + */ +#define IRQ_A 0x02 +#define IRQ_B 0x04 + +extern uint16_t vrc4171_get_irq_status(void); + +#endif /* __NEC_VRC4171_H */ diff --git a/include/asm-mips/vr41xx/vrc4173.h b/include/asm-mips/vr41xx/vrc4173.h index 1d0f30a9d547..a8e873c06481 100644 --- a/include/asm-mips/vr41xx/vrc4173.h +++ b/include/asm-mips/vr41xx/vrc4173.h @@ -72,6 +72,19 @@ extern unsigned long vrc4173_io_offset; /* * Clock Mask Unit */ +#define VRC4173_PIU_CLOCK 0x0001 +#define VRC4173_KIU_CLOCK 0x0002 +#define VRC4173_AIU_CLOCK 0x0004 +#define VRC4173_PS2CH1_CLOCK 0x0008 +#define VRC4173_PS2CH2_CLOCK 0x0010 +#define VRC4173_USBU_PCI_CLOCK 0x0020 +#define VRC4173_CARDU1_PCI_CLOCK 0x0040 +#define VRC4173_CARDU2_PCI_CLOCK 0x0080 +#define VRC4173_AC97U_PCI_CLOCK 0x0100 +#define VRC4173_USBU_48MHz_CLOCK 0x0400 +#define VRC4173_EXT_48MHz_CLOCK 0x0800 +#define VRC4173_48MHz_CLOCK 0x1000 + extern void vrc4173_clock_supply(u16 mask); extern void vrc4173_clock_mask(u16 mask); diff --git a/include/asm-mips/vr41xx/workpad.h b/include/asm-mips/vr41xx/workpad.h index e2d2ac1efca7..c7d27300370d 100644 --- a/include/asm-mips/vr41xx/workpad.h +++ b/include/asm-mips/vr41xx/workpad.h @@ -22,7 +22,7 @@ /* * Board specific address mapping */ -#define VR41XX_ISA_MEM_BASE 0x100000000 +#define VR41XX_ISA_MEM_BASE 0x10000000 #define VR41XX_ISA_MEM_SIZE 0x04000000 /* VR41XX_ISA_IO_BASE includes offset from real base. */ diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index a62c7d63240e..36f4ffc8bad8 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2002 by Ralf Baechle + * Copyright (C) 2002, 2004 by Ralf Baechle */ #ifndef _ASM_WAR_H #define _ASM_WAR_H @@ -11,7 +11,16 @@ #include <linux/config.h> /* - * Pleassures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: + * Another R4600 erratum. Due to the lack of errata information the exact + * technical details aren't known. I've experimentally found that disabling + * interrupts during indexed I-cache flushes seems to be sufficient to deal + * with the issue. + * + * #define R4600_V1_INDEX_ICACHEOP_WAR 1 + */ + +/* + * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: * * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, * Hit_Invalidate_D and Create_Dirty_Excl_D should only be @@ -59,6 +68,7 @@ */ #ifdef CONFIG_SGI_IP22 +#define R4600_V1_INDEX_ICACHEOP_WAR 1 #define R4600_V1_HIT_CACHEOP_WAR 1 #define R4600_V2_HIT_CACHEOP_WAR 1 @@ -111,8 +121,59 @@ #endif /* + * Fill buffers not flushed on CACHE instructions + * + * Hit_Invalidate_I cacheops invalidate an icache line but the refill + * for that line can get stale data from the fill buffer instead of + * accessing memory if the previous icache miss was also to that line. + * + * Workaround: generate an icache refill from a different line + * + * Affects: + * MIPS 4K RTL revision <3.0, PRID revision <4 + */ +#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ + defined(CONFIG_MIPS_SEAD) +#define MIPS4K_ICACHE_REFILL_WAR 1 +#endif + +/* + * Missing implicit forced flush of evictions caused by CACHE + * instruction + * + * Evictions caused by a CACHE instructions are not forced on to the + * bus. The BIU gives higher priority to fetches than to the data from + * the eviction buffer and no collision detection is performed between + * fetches and pending data from the eviction buffer. + * + * Workaround: Execute a SYNC instruction after the cache instruction + * + * Affects: + * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8 + * MIPS 20Kc RTL revision <4.0, PRID revision <? + */ +#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ + defined(CONFIG_MIPS_SEAD) +#define MIPS_CACHE_SYNC_WAR 1 +#endif + +/* + * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for + * the line which this instruction itself exists, the following + * operation is not guaranteed." + * + * Workaround: do two phase flushing for Index_Invalidate_I + */ +#ifdef CONFIG_CPU_TX49XX +#define TX49XX_ICACHE_INDEX_INV_WAR 1 +#endif + +/* * Workarounds default to off */ +#ifndef R4600_V1_INDEX_ICACHEOP_WAR +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#endif #ifndef R4600_V1_HIT_CACHEOP_WAR #define R4600_V1_HIT_CACHEOP_WAR 0 #endif @@ -128,5 +189,14 @@ #ifndef SIBYTE_1956_WAR #define SIBYTE_1956_WAR 0 #endif +#ifndef MIPS4K_ICACHE_REFILL_WAR +#define MIPS4K_ICACHE_REFILL_WAR 0 +#endif +#ifndef MIPS_CACHE_SYNC_WAR +#define MIPS_CACHE_SYNC_WAR 0 +#endif +#ifndef TX49XX_ICACHE_INDEX_INV_WAR +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#endif #endif /* _ASM_WAR_H */ diff --git a/include/asm-mips/xxs1500.h b/include/asm-mips/xxs1500.h new file mode 100644 index 000000000000..75c0ddfeca13 --- /dev/null +++ b/include/asm-mips/xxs1500.h @@ -0,0 +1,35 @@ +/* + * MyCable XXS1500 Referrence Board + * + * Copyright 2003 MontaVista Software Inc. + * Author: Pete Popov, MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * + */ +#ifndef __ASM_XXS1500_H +#define __ASM_XXS1500_H + +/* PCMCIA XXS1500 specific defines */ +#define PCMCIA_MAX_SOCK 0 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) +#define PCMCIA_IRQ AU1000_GPIO_4 + +#endif /* __ASM_XXS1500_ */ |