diff options
| author | Andrew Morton <akpm@osdl.org> | 2004-04-19 17:59:56 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-04-19 17:59:56 -0700 |
| commit | 70e2d422332806f48d95b02716b019d9dfe2ef43 (patch) | |
| tree | c2afb9ddf79ce30a88641d35b2629c605ca9cf51 /include | |
| parent | fb4e0779895245c02e06181a6bb4d3201734e498 (diff) | |
[PATCH] MIPS update
From: Ralf Baechle <ralf@linux-mips.org>
- more work on resurrecting AMD Alchemy platforms
- cleanup of unnecessary <asm/pgalloc.h> inclusions
- update default config files
- cleanup 32-bit compat ioctl code
- support for Montum Jaguar ATX
- workarounds for early revs of the RM9000
- fixes for RM5000 and RM7000 cache handling
- add support for PMC-Sierra Yosemite eval board
- further cleanup and bugfixes for SGI IP27
- make LASAT and VR41xx build and work in 2.6
- improved SGI IP32 support
- plenty of small fixes
Diffstat (limited to 'include')
60 files changed, 1557 insertions, 477 deletions
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h index d93e636aed77..f53237772985 100644 --- a/include/asm-mips/asm.h +++ b/include/asm-mips/asm.h @@ -209,7 +209,7 @@ symbol = value #define ALSZ 7 #define ALMASK ~7 #endif -#if (_MIPS_SIM == _MIPS_SIM_ABIN32) || (_MIPS_SIM == _MIPS_SIM_ABI64) +#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) #define ALSZ 15 #define ALMASK ~15 #endif @@ -237,7 +237,7 @@ symbol = value #define REG_SUBU subu #define REG_ADDU addu #endif -#if (_MIPS_SIM == _MIPS_SIM_ABIN32) || (_MIPS_SIM == _MIPS_SIM_ABI64) +#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) #define REG_S sd #define REG_L ld #define REG_SUBU dsubu @@ -386,7 +386,7 @@ symbol = value #define MFC0 mfc0 #define MTC0 mtc0 #endif -#if (_MIPS_SIM == _MIPS_SIM_ABIN32) || (_MIPS_SIM == _MIPS_SIM_ABI64) +#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) #define MFC0 dmfc0 #define MTC0 dmtc0 #endif diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 3519b50ac065..aacab4d6ebf6 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h @@ -173,6 +173,7 @@ #define MACH_DB1500 5 /* Au1500-based eval board */ #define MACH_XXS1500 6 /* Au1500-based eval board */ #define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */ +#define MACH_PB1550 8 /* Au1550-based eval board */ /* * Valid machtype for group NEC_VR41XX @@ -199,8 +200,8 @@ * Valid machtype for group LASAT */ #define MACH_GROUP_LASAT 21 -#define MACH_LASAT_100 1 /* Masquerade II/SP100/SP50/SP25 */ -#define MACH_LASAT_200 2 /* Masquerade PRO/SP200 */ +#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */ +#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */ /* * Valid machtype for group TITAN diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h index 39b10d84d01d..0ab4f7d671b3 100644 --- a/include/asm-mips/cacheflush.h +++ b/include/asm-mips/cacheflush.h @@ -11,6 +11,7 @@ /* Keep includes the same across arches. */ #include <linux/mm.h> +#include <asm/cpu-features.h> /* Cache flushing: * @@ -35,7 +36,15 @@ extern void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, unsigned long end); extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page); -extern void flush_dcache_page(struct page *page); +extern void __flush_dcache_page(struct page *page); + +static inline void flush_dcache_page(struct page *page) +{ + if (cpu_has_dc_aliases) + __flush_dcache_page(page); + +} + extern void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page); extern void (*flush_icache_range)(unsigned long start, unsigned long end); diff --git a/include/asm-mips/dma-mapping.h b/include/asm-mips/dma-mapping.h index 9d8ad3a6afe3..a11cf994d526 100644 --- a/include/asm-mips/dma-mapping.h +++ b/include/asm-mips/dma-mapping.h @@ -31,17 +31,19 @@ extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, enum dma_data_direction direction); extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction); -extern void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, - size_t size, enum dma_data_direction direction); -extern void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, enum dma_data_direction direction); -extern void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle, - unsigned long offset, size_t size, enum dma_data_direction direction); -extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems, +extern void dma_sync_single_for_device(struct device *dev, + dma_addr_t dma_handle, size_t size, enum dma_data_direction direction); +extern void dma_sync_single_range_for_cpu(struct device *dev, + dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction); -extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nelems, +extern void dma_sync_single_range_for_device(struct device *dev, + dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction); - +extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, + int nelems, enum dma_data_direction direction); +extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, + int nelems, enum dma_data_direction direction); +extern int dma_mapping_error(dma_addr_t dma_addr); extern int dma_supported(struct device *dev, u64 mask); static inline int diff --git a/include/asm-mips/hardirq.h b/include/asm-mips/hardirq.h index 82f90500030a..a045970ebd9e 100644 --- a/include/asm-mips/hardirq.h +++ b/include/asm-mips/hardirq.h @@ -81,7 +81,7 @@ typedef struct { #ifdef CONFIG_PREEMPT # include <linux/smp_lock.h> -# define in_atomic() (preempt_count() != kernel_locked()) +# define in_atomic() ((preempt_count() & ~PREEMPT_ACTIVE) != kernel_locked()) # define IRQ_EXIT_OFFSET (HARDIRQ_OFFSET-1) #else # define in_atomic() (preempt_count() != 0) diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h index 1c8d3132484e..4a024fa727cc 100644 --- a/include/asm-mips/hazards.h +++ b/include/asm-mips/hazards.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2003 Ralf Baechle + * Copyright (C) 2003, 2004 Ralf Baechle */ #ifndef _ASM_HAZARDS_H #define _ASM_HAZARDS_H @@ -18,16 +18,32 @@ * for data translations should not occur for 3 cpu cycles. */ #ifdef CONFIG_CPU_RM9000 -#define rm9000_tlb_hazard \ +#define mtc0_tlbw_hazard \ .set push; \ .set mips32; \ ssnop; ssnop; ssnop; ssnop; \ .set pop + +#define tlbw_eret_hazard \ + .set push; \ + .set mips32; \ + ssnop; ssnop; ssnop; ssnop; \ + .set pop + #else -#define rm9000_tlb_hazard + +/* + * The taken branch will result in a two cycle penalty for the two killed + * instructions on R4000 / R4400. Other processors only have a single cycle + * hazard so this is nice trick to have an optimal code for a range of + * processors. + */ +#define mtc0_tlbw_hazard \ + b . + 8 +#define tlbw_eret_hazard #endif -#else +#else /* __ASSEMBLY__ */ /* * RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent @@ -35,15 +51,37 @@ * for data translations should not occur for 3 cpu cycles. */ #ifdef CONFIG_CPU_RM9000 -#define rm9000_tlb_hazard() \ + +#define mtc0_tlbw_hazard() \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "ssnop; ssnop; ssnop; ssnop\n\t" \ + ".set\tmips0") + +#define tlbw_use_hazard() \ __asm__ __volatile__( \ ".set\tmips32\n\t" \ "ssnop; ssnop; ssnop; ssnop\n\t" \ ".set\tmips0") #else -#define rm9000_tlb_hazard() do { } while (0) -#endif + +/* + * Overkill warning ... + */ +#define mtc0_tlbw_hazard() \ + __asm__ __volatile__( \ + ".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") + +#define tlbw_use_hazard() \ + __asm__ __volatile__( \ + ".set noreorder\n\t" \ + "nop; nop; nop; nop; nop; nop;\n\t" \ + ".set reorder\n\t") #endif +#endif /* __ASSEMBLY__ */ + #endif /* _ASM_HAZARDS_H */ diff --git a/include/asm-mips/highmem.h b/include/asm-mips/highmem.h index 205c69d9a3f4..f49930d947d4 100644 --- a/include/asm-mips/highmem.h +++ b/include/asm-mips/highmem.h @@ -19,6 +19,7 @@ #ifdef __KERNEL__ +#include <linux/config.h> #include <linux/init.h> #include <linux/interrupt.h> #include <asm/kmap_types.h> @@ -47,14 +48,56 @@ extern pte_t *pkmap_page_table; extern void * kmap_high(struct page *page); extern void kunmap_high(struct page *page); -extern void *kmap(struct page *page); -extern void kunmap(struct page *page); -extern void *kmap_atomic(struct page *page, enum km_type type); -extern void kunmap_atomic(void *kvaddr, enum km_type type); -extern struct page *kmap_atomic_to_page(void *ptr); +/* + * CONFIG_LIMITED_DMA is for systems with DMA limitations such as Momentum's + * Jaguar ATX. This option exploits the highmem code in the kernel so is + * always enabled together with CONFIG_HIGHMEM but at this time doesn't + * actually add highmem functionality. + */ + +#ifdef CONFIG_LIMITED_DMA + +/* + * These are the default functions for the no-highmem case from + * <linux/highmem.h> + */ +static inline void *kmap(struct page *page) +{ + might_sleep(); + return page_address(page); +} + +#define kunmap(page) do { (void) (page); } while (0) + +static inline void *kmap_atomic(struct page *page, enum km_type type) +{ + return page_address(page); +} + +static inline void kunmap_atomic(void *kvaddr, enum km_type type) { } + +#define kmap_atomic_to_page(ptr) virt_to_page(ptr) + +#define flush_cache_kmaps() do { } while (0) + +#else /* LIMITED_DMA */ + +extern void *__kmap(struct page *page); +extern void __kunmap(struct page *page); +extern void *__kmap_atomic(struct page *page, enum km_type type); +extern void __kunmap_atomic(void *kvaddr, enum km_type type); +extern struct page *__kmap_atomic_to_page(void *ptr); + +#define kmap __kmap +#define kunmap __kunmap +#define kmap_atomic __kmap_atomic +#define kunmap_atomic __kunmap_atomic +#define kmap_atomic_to_page __kmap_atomic_to_page #define flush_cache_kmaps() flush_cache_all() +#endif /* LIMITED_DMA */ + #endif /* __KERNEL__ */ #endif /* _ASM_HIGHMEM_H */ diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h index 8fa05eeb50ed..c3c280e3d591 100644 --- a/include/asm-mips/ip32/ip32_ints.h +++ b/include/asm-mips/ip32/ip32_ints.h @@ -16,7 +16,7 @@ */ /* CPU */ -#define CLOCK_IRQ 0 +#define IP32_R4K_TIMER_IRQ 0 /* MACE */ #define MACE_VID_IN1_IRQ 1 diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h index 0f56aaddd6e0..255e9b2b87f5 100644 --- a/include/asm-mips/ip32/mace.h +++ b/include/asm-mips/ip32/mace.h @@ -342,7 +342,7 @@ struct mace_isa { struct mace_serial serial2; char _pad4[0x8000 - sizeof(struct mace_serial)]; - mace32_t rtc[0x10000/8]; + volatile unsigned char rtc[0x10000]; }; struct sgi_mace { diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h index 39c4abe52bc1..181afc5c0f1d 100644 --- a/include/asm-mips/lasat/lasat.h +++ b/include/asm-mips/lasat/lasat.h @@ -220,7 +220,22 @@ extern void lasat_write_eeprom_info(void); #define N_MACHTYPES 2 /* for calibration of delays */ +/* the lasat_ndelay function is necessary because it is used at an + * early stage of the boot process where ndelay is not calibrated. + * It is used for the bit-banging rtc and eeprom drivers */ + #include <asm/delay.h> +/* calculating with the slowest board with 100 MHz clock */ +#define LASAT_100_DIVIDER 20 +/* All 200's run at 250 MHz clock */ +#define LASAT_200_DIVIDER 8 + +extern unsigned int lasat_ndelay_divider; + +static inline void lasat_ndelay(unsigned int ns) +{ + __delay(ns / lasat_ndelay_divider); +} extern void (* prom_printf)(const char *fmt, ...); diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h index 55166f4b7c64..8799f921af96 100644 --- a/include/asm-mips/mach-atlas/mc146818rtc.h +++ b/include/asm-mips/mach-atlas/mc146818rtc.h @@ -50,4 +50,6 @@ static inline void CMOS_WRITE(unsigned char data, unsigned long addr) #define RTC_ALWAYS_BCD 0 +#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) + #endif /* __ASM_MACH_ATLAS_MC146818RTC_H */ diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 8cb99b6a4e1c..91b1b07a5d78 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -197,6 +197,15 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define MEM_STTIME3 0xB4001034 #define MEM_STADDR3 0xB4001038 +#ifdef CONFIG_SOC_AU1550 +#define MEM_STNDCTL 0xB4001100 +#define MEM_STSTAT 0xB4001104 + +#define MEM_STNAND_CMD (0x0) +#define MEM_STNAND_ADDR (0x4) +#define MEM_STNAND_DATA (0x20) +#endif + /* Interrupt Controller 0 */ #define IC0_CFG0RD 0xB0400040 #define IC0_CFG0SET 0xB0400040 @@ -951,6 +960,23 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define SYS_PF_CS (1<<16) /* EXTCLK0/32khz to gpio2 */ #define SYS_PF_EX0 (1<<9) /* gpio2/clock */ +/* Au1550 Only. Redefines lots of pins */ + #define SYS_PF_PSC2_MASK (7 << 17) + #define SYS_PF_PSC2_AC97 (0) + #define SYS_PF_PSC2_SPI (0) + #define SYS_PF_PSC2_I2S (1 << 17) + #define SYS_PF_PSC2_SMBUS (3 << 17) + #define SYS_PF_PSC2_GPIO (7 << 17) + #define SYS_PF_PSC3_MASK (7 << 20) + #define SYS_PF_PSC3_AC97 (0) + #define SYS_PF_PSC3_SPI (0) + #define SYS_PF_PSC3_I2S (1 << 20) + #define SYS_PF_PSC3_SMBUS (3 << 20) + #define SYS_PF_PSC3_GPIO (7 << 20) + #define SYS_PF_PSC1_S1 (1 << 1) + #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) + + #define SYS_TRIOUTRD 0xB1900100 #define SYS_TRIOUTCLR 0xB1900100 #define SYS_OUTPUTRD 0xB1900108 @@ -959,7 +985,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define SYS_PINSTATERD 0xB1900110 #define SYS_PININPUTEN 0xB1900110 -/* GPIO2, Au1500 only */ +/* GPIO2, Au1500, Au1550 only */ #define GPIO2_BASE 0xB1700000 #define GPIO2_DIR (GPIO2_BASE + 0) #define GPIO2_OUTPUT (GPIO2_BASE + 8) @@ -1071,6 +1097,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define AC97C_RS (1<<1) #define AC97C_CE (1<<0) + +/* Secure Digital (SD) Controller */ +#define SD0_XMIT_FIFO 0xB0600000 +#define SD0_RECV_FIFO 0xB0600004 +#define SD1_XMIT_FIFO 0xB0680000 +#define SD1_RECV_FIFO 0xB0680004 + + #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) /* Au1500 PCI Controller */ #define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr @@ -1119,6 +1153,20 @@ extern au1xxx_irq_map_t au1xxx_irq_map[]; #define IOMEM_RESOURCE_START 0x10000000 #define IOMEM_RESOURCE_END 0xffffffff + /* + * Borrowed from the PPC arch: + * The following macro is used to lookup irqs in a standard table + * format for those PPC systems that do not already have PCI + * interrupts properly routed. + */ + /* FIXME - double check this from asm-ppc/pci-bridge.h */ +#define PCI_IRQ_TABLE_LOOKUP \ + ({ long _ctl_ = -1; \ + if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ + _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ + _ctl_; }) + + #else /* Au1000 and Au1100 */ /* don't allow any legacy ports probing */ diff --git a/include/asm-mips/mach-au1x00/au1000_dma.h b/include/asm-mips/mach-au1x00/au1000_dma.h index 02caee4eef6b..810f2fa33444 100644 --- a/include/asm-mips/mach-au1x00/au1000_dma.h +++ b/include/asm-mips/mach-au1x00/au1000_dma.h @@ -50,6 +50,7 @@ #define DMA_DAH_MASK (0x0f << 20) #define DMA_DID_BIT 16 #define DMA_DID_MASK (0x0f << DMA_DID_BIT) +#define DMA_DS (1<<15) #define DMA_BE (1<<13) #define DMA_DR (1<<12) #define DMA_TS8 (1<<11) @@ -99,6 +100,15 @@ enum { DMA_NUM_DEV }; +/* DMA Device ID's for 2nd bank (AU1100) follow */ +enum { + DMA_ID_SD0_TX = 0, + DMA_ID_SD0_RX, + DMA_ID_SD1_TX, + DMA_ID_SD1_RX, + DMA_NUM_DEV_BANK2 +}; + struct dma_chan { int dev_id; // this channel is allocated if >=0, free otherwise unsigned int io; @@ -126,7 +136,7 @@ extern spinlock_t au1000_dma_spin_lock; static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr) { - if (dmanr > NUM_AU1000_DMA_CHANNELS + if (dmanr >= NUM_AU1000_DMA_CHANNELS || au1000_dma_table[dmanr].dev_id < 0) return NULL; return &au1000_dma_table[dmanr]; @@ -205,8 +215,8 @@ static __inline__ void disable_dma(unsigned int dmanr) halt_dma(dmanr); - // now we can disable the buffers - au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); + // now we can disable the buffers + au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); } static __inline__ int dma_halted(unsigned int dmanr) @@ -286,6 +296,9 @@ static __inline__ void set_dma_fifo_addr(unsigned int dmanr, if (!chan) return; + if (chan->mode & DMA_DS) /* second bank of device ids */ + return; + if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05) return; @@ -430,3 +443,4 @@ static __inline__ int get_dma_residue(unsigned int dmanr) } #endif /* __ASM_AU1000_DMA_H */ + diff --git a/include/asm-mips/mach-au1x00/au1000_pcmcia.h b/include/asm-mips/mach-au1x00/au1000_pcmcia.h deleted file mode 100644 index 4ba34a9be79f..000000000000 --- a/include/asm-mips/mach-au1x00/au1000_pcmcia.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Alchemy Semi Au1000 pcmcia driver include file - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - */ -#ifndef __ASM_AU1000_PCMCIA_H -#define __ASM_AU1000_PCMCIA_H - -#include <linux/config.h> - -#define AU1000_PCMCIA_POLL_PERIOD (2*HZ) -#define AU1000_PCMCIA_IO_SPEED (255) -#define AU1000_PCMCIA_MEM_SPEED (300) - -#define AU1X_SOCK0_IO 0xF00000000 -#define AU1X_SOCK0_PHYS_ATTR 0xF40000000 -#define AU1X_SOCK0_PHYS_MEM 0xF80000000 - -/* pcmcia socket 1 needs external glue logic so the memory map - * differs from board to board. - */ -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_PB1500) -#define AU1X_SOCK1_IO 0xF08000000 -#define AU1X_SOCK1_PHYS_ATTR 0xF48000000 -#define AU1X_SOCK1_PHYS_MEM 0xF88000000 -#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) -#define AU1X_SOCK1_IO 0xF04000000 -#define AU1X_SOCK1_PHYS_ATTR 0xF44000000 -#define AU1X_SOCK1_PHYS_MEM 0xF84000000 -#endif - -struct pcmcia_state { - unsigned detect: 1, - ready: 1, - wrprot: 1, - bvd1: 1, - bvd2: 1, - vs_3v: 1, - vs_Xv: 1; -}; - -struct pcmcia_configure { - unsigned sock: 8, - vcc: 8, - vpp: 8, - output: 1, - speaker: 1, - reset: 1; -}; - -struct pcmcia_irq_info { - unsigned int sock; - unsigned int irq; -}; - - -struct au1000_pcmcia_socket { - socket_state_t cs_state; - struct pcmcia_state k_state; - unsigned int irq; - void (*handler)(void *, unsigned int); - void *handler_info; - pccard_io_map io_map[MAX_IO_WIN]; - pccard_mem_map mem_map[MAX_WIN]; - u32 virt_io; - ioaddr_t phys_attr, phys_mem; - unsigned short speed_io, speed_attr, speed_mem; -}; - -struct pcmcia_init { - void (*handler)(int irq, void *dev, struct pt_regs *regs); -}; - -struct pcmcia_low_level { - int (*init)(struct pcmcia_init *); - int (*shutdown)(void); - int (*socket_state)(unsigned sock, struct pcmcia_state *); - int (*get_irq_info)(struct pcmcia_irq_info *); - int (*configure_socket)(const struct pcmcia_configure *); -}; - -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_PB1500) -extern struct pcmcia_low_level pb1x00_pcmcia_ops; -#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || defined(CONFIG_MIPS_DB1500) -extern struct pcmcia_low_level db1x00_pcmcia_ops; -#elif defined(CONFIG_MIPS_XXS1500) -extern struct pcmcia_low_level xxs1500_pcmcia_ops; -#else -error unknown Au1000 board -#endif - -#endif /* __ASM_AU1000_PCMCIA_H */ diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h new file mode 100644 index 000000000000..9e7d1ba21b55 --- /dev/null +++ b/include/asm-mips/mach-au1x00/au1100_mmc.h @@ -0,0 +1,205 @@ +/* + * BRIEF MODULE DESCRIPTION + * Defines for using the MMC/SD controllers on the + * Alchemy Au1100 mips processor. + * + * Copyright (c) 2003 Embedded Edge, LLC. + * Author: Embedded Edge, LLC. + * dan@embeddededge.com or tim@embeddededge.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +/* + * AU1100 MMC/SD definitions. + * + * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary" + * June, 2003 + */ + +#ifndef __ASM_AU1100_MMC_H +#define __ASM_AU1100_MMC_H + + +#define NUM_AU1100_MMC_CONTROLLERS 2 + + +#define AU1100_SD_IRQ 2 + + +#define SD0_BASE 0xB0600000 +#define SD1_BASE 0xB0680000 + + +/* + * Register offsets. + */ +#define SD_TXPORT (0x0000) +#define SD_RXPORT (0x0004) +#define SD_CONFIG (0x0008) +#define SD_ENABLE (0x000C) +#define SD_CONFIG2 (0x0010) +#define SD_BLKSIZE (0x0014) +#define SD_STATUS (0x0018) +#define SD_DEBUG (0x001C) +#define SD_CMD (0x0020) +#define SD_CMDARG (0x0024) +#define SD_RESP3 (0x0028) +#define SD_RESP2 (0x002C) +#define SD_RESP1 (0x0030) +#define SD_RESP0 (0x0034) +#define SD_TIMEOUT (0x0038) + + +/* + * SD_TXPORT bit definitions. + */ +#define SD_TXPORT_TXD (0x000000ff) + + +/* + * SD_RXPORT bit definitions. + */ +#define SD_RXPORT_RXD (0x000000ff) + + +/* + * SD_CONFIG bit definitions. + */ +#define SD_CONFIG_DIV (0x000001ff) +#define SD_CONFIG_DE (0x00000200) +#define SD_CONFIG_NE (0x00000400) +#define SD_CONFIG_TU (0x00000800) +#define SD_CONFIG_TO (0x00001000) +#define SD_CONFIG_RU (0x00002000) +#define SD_CONFIG_RO (0x00004000) +#define SD_CONFIG_I (0x00008000) +#define SD_CONFIG_CR (0x00010000) +#define SD_CONFIG_RAT (0x00020000) +#define SD_CONFIG_DD (0x00040000) +#define SD_CONFIG_DT (0x00080000) +#define SD_CONFIG_SC (0x00100000) +#define SD_CONFIG_RC (0x00200000) +#define SD_CONFIG_WC (0x00400000) +#define SD_CONFIG_xxx (0x00800000) +#define SD_CONFIG_TH (0x01000000) +#define SD_CONFIG_TE (0x02000000) +#define SD_CONFIG_TA (0x04000000) +#define SD_CONFIG_RH (0x08000000) +#define SD_CONFIG_RA (0x10000000) +#define SD_CONFIG_RF (0x20000000) +#define SD_CONFIG_CD (0x40000000) +#define SD_CONFIG_SI (0x80000000) + + +/* + * SD_ENABLE bit definitions. + */ +#define SD_ENABLE_CE (0x00000001) +#define SD_ENABLE_R (0x00000002) + + +/* + * SD_CONFIG2 bit definitions. + */ +#define SD_CONFIG2_EN (0x00000001) +#define SD_CONFIG2_FF (0x00000002) +#define SD_CONFIG2_xx1 (0x00000004) +#define SD_CONFIG2_DF (0x00000008) +#define SD_CONFIG2_DC (0x00000010) +#define SD_CONFIG2_xx2 (0x000000e0) +#define SD_CONFIG2_WB (0x00000100) +#define SD_CONFIG2_RW (0x00000200) + + +/* + * SD_BLKSIZE bit definitions. + */ +#define SD_BLKSIZE_BS (0x000007ff) +#define SD_BLKSIZE_BS_SHIFT (0) +#define SD_BLKSIZE_BC (0x01ff0000) +#define SD_BLKSIZE_BC_SHIFT (16) + + +/* + * SD_STATUS bit definitions. + */ +#define SD_STATUS_DCRCW (0x00000007) +#define SD_STATUS_xx1 (0x00000008) +#define SD_STATUS_CB (0x00000010) +#define SD_STATUS_DB (0x00000020) +#define SD_STATUS_CF (0x00000040) +#define SD_STATUS_D3 (0x00000080) +#define SD_STATUS_xx2 (0x00000300) +#define SD_STATUS_NE (0x00000400) +#define SD_STATUS_TU (0x00000800) +#define SD_STATUS_TO (0x00001000) +#define SD_STATUS_RU (0x00002000) +#define SD_STATUS_RO (0x00004000) +#define SD_STATUS_I (0x00008000) +#define SD_STATUS_CR (0x00010000) +#define SD_STATUS_RAT (0x00020000) +#define SD_STATUS_DD (0x00040000) +#define SD_STATUS_DT (0x00080000) +#define SD_STATUS_SC (0x00100000) +#define SD_STATUS_RC (0x00200000) +#define SD_STATUS_WC (0x00400000) +#define SD_STATUS_xx3 (0x00800000) +#define SD_STATUS_TH (0x01000000) +#define SD_STATUS_TE (0x02000000) +#define SD_STATUS_TA (0x04000000) +#define SD_STATUS_RH (0x08000000) +#define SD_STATUS_RA (0x10000000) +#define SD_STATUS_RF (0x20000000) +#define SD_STATUS_CD (0x40000000) +#define SD_STATUS_SI (0x80000000) + + +/* + * SD_CMD bit definitions. + */ +#define SD_CMD_GO (0x00000001) +#define SD_CMD_RY (0x00000002) +#define SD_CMD_xx1 (0x0000000c) +#define SD_CMD_CT_MASK (0x000000f0) +#define SD_CMD_CT_0 (0x00000000) +#define SD_CMD_CT_1 (0x00000010) +#define SD_CMD_CT_2 (0x00000020) +#define SD_CMD_CT_3 (0x00000030) +#define SD_CMD_CT_4 (0x00000040) +#define SD_CMD_CT_5 (0x00000050) +#define SD_CMD_CT_6 (0x00000060) +#define SD_CMD_CT_7 (0x00000070) +#define SD_CMD_CI (0x0000ff00) +#define SD_CMD_CI_SHIFT (8) +#define SD_CMD_RT_MASK (0x00ff0000) +#define SD_CMD_RT_0 (0x00000000) +#define SD_CMD_RT_1 (0x00010000) +#define SD_CMD_RT_2 (0x00020000) +#define SD_CMD_RT_3 (0x00030000) +#define SD_CMD_RT_4 (0x00040000) +#define SD_CMD_RT_5 (0x00050000) +#define SD_CMD_RT_6 (0x00060000) +#define SD_CMD_RT_1B (0x00810000) + + +#endif /* __ASM_AU1100_MMC_H */ + diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h new file mode 100644 index 000000000000..15e84ca2739a --- /dev/null +++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h @@ -0,0 +1,297 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Include file for Alchemy Semiconductor's Au1550 Descriptor + * Based DMA Controller. + * + * Copyright 2004 Embedded Edge, LLC + * dan@embeddededge.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first + * seen in the AU1550 part. + */ +#ifndef _AU1000_DBDMA_H_ +#define _AU1000_DBDMA_H_ + +#ifndef _LANGUAGE_ASSEMBLY + +/* The DMA base addresses. + * The Channels are every 256 bytes (0x0100) from the channel 0 base. + * Interrupt status/enable is bits 15:0 for channels 15 to zero. + */ +#define DDMA_GLOBAL_BASE 0xb4003000 +#define DDMA_CHANNEL_BASE 0xb4002000 + +typedef struct dbdma_global { + u32 ddma_config; + u32 ddma_intstat; + u32 ddma_throttle; + u32 ddma_inten; +} dbdma_global_t; + +/* General Configuration. +*/ +#define DDMA_CONFIG_AF (1 << 2) +#define DDMA_CONFIG_AH (1 << 1) +#define DDMA_CONFIG_AL (1 << 0) + +#define DDMA_THROTTLE_EN (1 << 31) + +/* The structure of a DMA Channel. +*/ +typedef struct au1xxx_dma_channel { + u32 ddma_cfg; /* See below */ + u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */ + u32 ddma_statptr; /* word aligned pointer to status word */ + u32 ddma_dbell; /* A write activates channel operation */ + u32 ddma_irq; /* If bit 0 set, interrupt pending */ + u32 ddma_stat; /* See below */ + u32 ddma_bytecnt; /* Byte count, valid only when chan idle */ + /* Remainder, up to the 256 byte boundary, is reserved. + */ +} au1x_dma_chan_t; + +#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */ +#define DDMA_CFG_SP (1 << 8) /* source DMA polarity */ +#define DDMA_CFG_DED (1 << 7) /* destination DMA level/edge detect */ +#define DDMA_CFG_DP (1 << 6) /* destination DMA polarity */ +#define DDMA_CFG_SYNC (1 << 5) /* Sync static bus controller */ +#define DDMA_CFG_PPR (1 << 4) /* PCI posted read/write control */ +#define DDMA_CFG_DFN (1 << 3) /* Descriptor fetch non-coherent */ +#define DDMA_CFG_SBE (1 << 2) /* Source big endian */ +#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */ +#define DDMA_CFG_EN (1 << 0) /* Channel enable */ + +/* Always set when descriptor processing done, regardless of + * interrupt enable state. Reflected in global intstat, don't + * clear this until global intstat is read/used. + */ +#define DDMA_IRQ_IN (1 << 0) + +#define DDMA_STAT_DB (1 << 2) /* Doorbell pushed */ +#define DDMA_STAT_V (1 << 1) /* Descriptor valid */ +#define DDMA_STAT_H (1 << 0) /* Channel Halted */ + +/* "Standard" DDMA Descriptor. + * Must be 32-byte aligned. + */ +typedef struct au1xxx_ddma_desc { + u32 dscr_cmd0; /* See below */ + u32 dscr_cmd1; /* See below */ + u32 dscr_source0; /* source phys address */ + u32 dscr_source1; /* See below */ + u32 dscr_dest0; /* Destination address */ + u32 dscr_dest1; /* See below */ + u32 dscr_stat; /* completion status */ + u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ +} au1x_ddma_desc_t; + +#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */ +#define DSCR_CMD0_MEM (1 << 30) /* mem-mem transfer */ +#define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */ +#define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */ +#define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */ +#define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */ +#define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */ +#define DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */ +#define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */ +#define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */ +#define DSCR_CMD0_SM (0x1 << 10) /* Stride mode */ +#define DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */ +#define DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */ +#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ +#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ + +/* Command 0 device IDs. +*/ +#define DSCR_CMD0_UART0_TX 0 +#define DSCR_CMD0_UART0_RX 1 +#define DSCR_CMD0_UART3_TX 2 +#define DSCR_CMD0_UART3_RX 3 +#define DSCR_CMD0_DMA_REQ0 4 +#define DSCR_CMD0_DMA_REQ1 5 +#define DSCR_CMD0_DMA_REQ2 6 +#define DSCR_CMD0_DMA_REQ3 7 +#define DSCR_CMD0_USBDEV_RX0 8 +#define DSCR_CMD0_USBDEV_TX0 9 +#define DSCR_CMD0_USBDEV_TX1 10 +#define DSCR_CMD0_USBDEV_TX2 11 +#define DSCR_CMD0_USBDEV_RX3 12 +#define DSCR_CMD0_USBDEV_RX4 13 +#define DSCR_CMD0_PSC0_TX 14 +#define DSCR_CMD0_PSC0_RX 15 +#define DSCR_CMD0_PSC1_TX 16 +#define DSCR_CMD0_PSC1_RX 17 +#define DSCR_CMD0_PSC2_TX 18 +#define DSCR_CMD0_PSC2_RX 19 +#define DSCR_CMD0_PSC3_TX 20 +#define DSCR_CMD0_PSC3_RX 21 +#define DSCR_CMD0_PCI_WRITE 22 +#define DSCR_CMD0_NAND_FLASH 23 +#define DSCR_CMD0_MAC0_RX 24 +#define DSCR_CMD0_MAC0_TX 25 +#define DSCR_CMD0_MAC1_RX 26 +#define DSCR_CMD0_MAC1_TX 27 +#define DSCR_CMD0_THROTTLE 30 +#define DSCR_CMD0_ALWAYS 31 +#define DSCR_NDEV_IDS 32 + +#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) +#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) + +/* Source/Destination transfer width. +*/ +#define DSCR_CMD0_BYTE 0 +#define DSCR_CMD0_HALFWORD 1 +#define DSCR_CMD0_WORD 2 + +#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18) +#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16) + +/* DDMA Descriptor Type. +*/ +#define DSCR_CMD0_STANDARD 0 +#define DSCR_CMD0_LITERAL 1 +#define DSCR_CMD0_CMP_BRANCH 2 + +#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13) + +/* Status Instruction. +*/ +#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */ +#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */ +#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */ +#define DSCR_CMD0_ST_BYTECNT 3 /* Write remaining byte count */ + +#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0) + +/* Descriptor Command 1 +*/ +#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */ +#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */ +#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */ +#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */ + +/* Flag description. +*/ +#define DSCR_CMD1_FL_MEM_STRIDE0 0 +#define DSCR_CMD1_FL_MEM_STRIDE1 1 +#define DSCR_CMD1_FL_MEM_STRIDE2 2 + +#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22) + +/* Source1, 1-dimensional stride. +*/ +#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */ +#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */ +#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */ +#define DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14) +#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */ +#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0) + +/* Dest1, 1-dimensional stride. +*/ +#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */ +#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */ +#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */ +#define DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14) +#define DSCR_DEST1_DS_MASK (0x3fff << 0) /* Stride */ +#define DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0) + +#define DSCR_xTS_SIZE1 0 +#define DSCR_xTS_SIZE2 1 +#define DSCR_xTS_SIZE4 2 +#define DSCR_xTS_SIZE8 3 +#define DSCR_SRC1_STS(x) (((x) & 3) << 30) +#define DSCR_DEST1_DTS(x) (((x) & 3) << 30) + +#define DSCR_xAM_INCREMENT 0 +#define DSCR_xAM_DECREMENT 1 +#define DSCR_xAM_STATIC 2 +#define DSCR_xAM_BURST 3 +#define DSCR_SRC1_SAM(x) (((x) & 3) << 28) +#define DSCR_DEST1_DAM(x) (((x) & 3) << 28) + +/* The next descriptor pointer. +*/ +#define DSCR_NXTPTR_MASK (0x07ffffff) +#define DSCR_NXTPTR(x) ((x) >> 5) +#define DSCR_GET_NXTPTR(x) ((x) << 5) +#define DSCR_NXTPTR_MS (1 << 27) + +/* The number of DBDMA channels. +*/ +#define NUM_DBDMA_CHANS 16 + +/* External functions for drivers to use. +*/ +/* Use this to allocate a dbdma channel. The device ids are one of the + * DSCR_CMD0 devices IDs, which is usually redefined to a more + * meaningful name. The 'callback' is called during dma completion + * interrupt. + */ +u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, + void (*callback)(int, void *, struct pt_regs *), void *callparam); + +#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS + +/* ACK! These should be in a board specific description file. +*/ +#ifdef CONFIG_MIPS_PB1550 +#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX +#endif +#ifdef CONFIG_MIPS_DB1550 +#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX +#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX +#endif + + +/* Set the device width of a in/out fifo. +*/ +u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); + +/* Allocate a ring of descriptors for dbdma. +*/ +u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries); + +/* Put buffers on source/destination descriptors. +*/ +u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes); +u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes); + +/* Get a buffer from the destination descriptor. +*/ +u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes); + +void au1xxx_dbdma_stop(u32 chanid); +void au1xxx_dbdma_start(u32 chanid); +void au1xxx_dbdma_reset(u32 chanid); +u32 au1xxx_get_dma_residue(u32 chanid); + +void au1xxx_dbdma_chan_free(u32 chanid); +void au1xxx_dbdma_dump(u32 chanid); + +#endif /* _LANGUAGE_ASSEMBLY */ +#endif /* _AU1000_DBDMA_H_ */ diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h new file mode 100644 index 000000000000..bc831c367c6a --- /dev/null +++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h @@ -0,0 +1,211 @@ +/* + * + * BRIEF MODULE DESCRIPTION + * Include file for Alchemy Semiconductor's Au1k CPU. + * + * Copyright 2004 Embedded Edge, LLC + * dan@embeddededge.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* Specifics for the Au1xxx Programmable Serial Controllers, first + * seen in the AU1550 part. + */ +#ifndef _AU1000_PSC_H_ +#define _AU1000_PSC_H_ + +/* The PSC base addresses. +*/ +#define PSC_BASE0 0xb1a00000 +#define PSC_BASE1 0xb1b00000 +#define PSC_BASE2 0xb0a00000 +#define PSC_BASE3 0xb0d00000 + +/* These should be defined in a board specific file! +*/ +#ifdef CONFIG_MIPS_PB1550 +#define SPI_PSC_BASE PSC_BASE0 +#define AC97_PSC_BASE PSC_BASE1 +#define SMBUS_PSC_BASE PSC_BASE2 +#endif +#ifdef CONFIG_MIPS_DB1550 +#define SPI_PSC_BASE PSC_BASE0 +#define AC97_PSC_BASE PSC_BASE1 +#define SMBUS_PSC_BASE PSC_BASE2 +#endif + + +/* The PSC select and control registers are common to + * all protocols. + */ +#define PSC_SEL_OFFSET 0x00000000 +#define PSC_CTRL_OFFSET 0x00000004 + +#define PSC_SEL_CLK_MASK (3 << 4) +#define PSC_SEL_CLK_INTCLK (0 << 4) +#define PSC_SEL_CLK_EXTCLK (1 << 4) +#define PSC_SEL_CLK_SERCLK (2 << 4) + +#define PSC_SEL_PS_MASK 0x00000007 +#define PSC_SEL_PS_DISABLED (0) +#define PSC_SEL_PS_SPIMODE (2) +#define PSC_SEL_PS_I2SMODE (3) +#define PSC_SEL_PS_AC97MODE (4) +#define PSC_SEL_PS_SMBUSMODE (5) + +#define PSC_CTRL_DISABLE (0) +#define PSC_CTRL_SUSPEND (2) +#define PSC_CTRL_ENABLE (3) + +/* AC97 Registers. +*/ +#define PSC_AC97CFG_OFFSET 0x00000008 +#define PSC_AC97MSK_OFFSET 0x0000000c +#define PSC_AC97PCR_OFFSET 0x00000010 +#define PSC_AC97STAT_OFFSET 0x00000014 +#define PSC_AC97EVNT_OFFSET 0x00000018 +#define PSC_AC97TXRX_OFFSET 0x0000001c +#define PSC_AC97CDC_OFFSET 0x00000020 +#define PSC_AC97RST_OFFSET 0x00000024 +#define PSC_AC97GPO_OFFSET 0x00000028 +#define PSC_AC97GPI_OFFSET 0x0000002c + +#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET) +#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET) +#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET) +#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET) +#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET) +#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET) +#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET) +#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET) +#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET) +#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET) +#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET) +#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET) + +/* AC97 Config Register. +*/ +#define PSC_AC97CFG_RT_MASK (3 << 30) +#define PSC_AC97CFG_RT_FIFO1 (0 << 30) +#define PSC_AC97CFG_RT_FIFO2 (1 << 30) +#define PSC_AC97CFG_RT_FIFO4 (2 << 30) +#define PSC_AC97CFG_RT_FIFO8 (3 << 30) + +#define PSC_AC97CFG_TT_MASK (3 << 28) +#define PSC_AC97CFG_TT_FIFO1 (0 << 28) +#define PSC_AC97CFG_TT_FIFO2 (1 << 28) +#define PSC_AC97CFG_TT_FIFO4 (2 << 28) +#define PSC_AC97CFG_TT_FIFO8 (3 << 28) + +#define PSC_AC97CFG_DD_DISABLE (1 << 27) +#define PSC_AC97CFG_DE_ENABLE (1 << 26) +#define PSC_AC97CFG_SE_ENABLE (1 << 25) + +#define PSC_AC97CFG_LEN_MASK (0xf << 21) +#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11) +#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1) +#define PSC_AC97CFG_GE_ENABLE (1) + +/* Enable slots 3-12. +*/ +#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11)) +#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1)) + +/* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately. + * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the + * arithmetic in the macro. + */ +#define PSC_AC97CFG_SET_LEN(x) (((((x)-2)/2) & 0xf) << 21) +#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2) + +/* AC97 Mask Register. +*/ +#define PSC_AC97MSK_GR (1 << 25) +#define PSC_AC97MSK_CD (1 << 24) +#define PSC_AC97MSK_RR (1 << 13) +#define PSC_AC97MSK_RO (1 << 12) +#define PSC_AC97MSK_RU (1 << 11) +#define PSC_AC97MSK_TR (1 << 10) +#define PSC_AC97MSK_TO (1 << 9) +#define PSC_AC97MSK_TU (1 << 8) +#define PSC_AC97MSK_RD (1 << 5) +#define PSC_AC97MSK_TD (1 << 4) +#define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \ + PSC_AC97MSK_RR | PSC_AC97MSK_RO | \ + PSC_AC97MSK_RU | PSC_AC97MSK_TR | \ + PSC_AC97MSK_TO | PSC_AC97MSK_TU | \ + PSC_AC97MSK_RD | PSC_AC97MSK_TD) + +/* AC97 Protocol Control Register. +*/ +#define PSC_AC97PCR_RC (1 << 6) +#define PSC_AC97PCR_RP (1 << 5) +#define PSC_AC97PCR_RS (1 << 4) +#define PSC_AC97PCR_TC (1 << 2) +#define PSC_AC97PCR_TP (1 << 1) +#define PSC_AC97PCR_TS (1 << 0) + +/* AC97 Status register (read only). +*/ +#define PSC_AC97STAT_CB (1 << 26) +#define PSC_AC97STAT_CP (1 << 25) +#define PSC_AC97STAT_CR (1 << 24) +#define PSC_AC97STAT_RF (1 << 13) +#define PSC_AC97STAT_RE (1 << 12) +#define PSC_AC97STAT_RR (1 << 11) +#define PSC_AC97STAT_TF (1 << 10) +#define PSC_AC97STAT_TE (1 << 9) +#define PSC_AC97STAT_TR (1 << 8) +#define PSC_AC97STAT_RB (1 << 5) +#define PSC_AC97STAT_TB (1 << 4) +#define PSC_AC97STAT_DI (1 << 2) +#define PSC_AC97STAT_DR (1 << 1) +#define PSC_AC97STAT_SR (1 << 0) + +/* AC97 Event Register. +*/ +#define PSC_AC97EVNT_GR (1 << 25) +#define PSC_AC97EVNT_CD (1 << 24) +#define PSC_AC97EVNT_RR (1 << 13) +#define PSC_AC97EVNT_RO (1 << 12) +#define PSC_AC97EVNT_RU (1 << 11) +#define PSC_AC97EVNT_TR (1 << 10) +#define PSC_AC97EVNT_TO (1 << 9) +#define PSC_AC97EVNT_TU (1 << 8) +#define PSC_AC97EVNT_RD (1 << 5) +#define PSC_AC97EVNT_TD (1 << 4) + +/* CODEC Command Register. +*/ +#define PSC_AC97CDC_RD (1 << 25) +#define PSC_AC97CDC_ID_MASK (3 << 23) +#define PSC_AC97CDC_INDX_MASK (0x7f << 16) +#define PSC_AC97CDC_ID(x) (((x) & 0x3) << 23) +#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16) + +/* AC97 Reset Control Register. +*/ +#define PSC_AC97RST_RST (1 << 1) +#define PSC_AC97RST_SNC (1 << 0) + + +#endif /* _AU1000_PSC_H_ */ diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h index 46247e2320b5..65990e18a4ec 100644 --- a/include/asm-mips/mach-db1x00/db1x00.h +++ b/include/asm-mips/mach-db1x00/db1x00.h @@ -93,9 +93,13 @@ typedef volatile struct #define BCSR_PCMCIA_PC1RST 0x8000 #define BCSR_BOARD_PCIM66EN 0x0001 +#define BCSR_BOARD_SD0_PWR 0x0040 +#define BCSR_BOARD_SD1_PWR 0x0080 #define BCSR_BOARD_PCIM33 0x0100 #define BCSR_BOARD_GPIO200RST 0x0400 #define BCSR_BOARD_PCICFG 0x1000 +#define BCSR_BOARD_SD0_WP 0x4000 +#define BCSR_BOARD_SD1_WP 0x8000 #define BCSR_LEDS_DECIMALS 0x0003 #define BCSR_LEDS_LED0 0x0100 @@ -122,4 +126,48 @@ typedef volatile struct #define DB1X00_USER_ONLY #endif +/* SD controller macros */ +/* + * Detect card. + */ +#define mmc_card_inserted(_n_, _res_) \ + do { \ + BCSR * const bcsr = (BCSR *)0xAE000000; \ + unsigned long mmc_wp, board_specific; \ + if ((_n_)) { \ + mmc_wp = BCSR_BOARD_SD1_WP; \ + } else { \ + mmc_wp = BCSR_BOARD_SD0_WP; \ + } \ + board_specific = au_readl((unsigned long)(&bcsr->specific)); \ + if (!(board_specific & mmc_wp)) {/* low means card present */ \ + *(int *)(_res_) = 1; \ + } else { \ + *(int *)(_res_) = 0; \ + } \ + } while (0) + +/* + * Apply power to card slot(s). + */ +#define mmc_power_on(_n_) \ + do { \ + BCSR * const bcsr = (BCSR *)0xAE000000; \ + unsigned long mmc_pwr, mmc_wp, board_specific; \ + if ((_n_)) { \ + mmc_pwr = BCSR_BOARD_SD1_PWR; \ + mmc_wp = BCSR_BOARD_SD1_WP; \ + } else { \ + mmc_pwr = BCSR_BOARD_SD0_PWR; \ + mmc_wp = BCSR_BOARD_SD0_WP; \ + } \ + board_specific = au_readl((unsigned long)(&bcsr->specific)); \ + if (!(board_specific & mmc_wp)) {/* low means card present */ \ + board_specific |= mmc_pwr; \ + au_writel(board_specific, (int)(&bcsr->specific)); \ + au_sync(); \ + } \ + } while (0) + #endif /* __ASM_DB1X00_H */ + diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h index e204dec688dd..4b565cfb7976 100644 --- a/include/asm-mips/mach-generic/spaces.h +++ b/include/asm-mips/mach-generic/spaces.h @@ -3,9 +3,9 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1996, 99 Ralf Baechle + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle * Copyright (C) 2000, 2002 Maciej W. Rozycki - * Copyright (C) 1990, 1999 by Silicon Graphics, Inc. + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_MACH_SPACES_H #define _ASM_MACH_SPACES_H @@ -19,10 +19,41 @@ #define UNCAC_BASE 0xa0000000 #define MAP_BASE 0xc0000000 +/* + * This handles the memory map. + * We handle pages at KSEG0 for kernels with 32 bit address space. + */ +#define PAGE_OFFSET 0x80000000UL + +/* + * Memory above this physical address will be considered highmem. + */ +#ifndef HIGHMEM_START +#define HIGHMEM_START 0x20000000UL +#endif + #endif /* CONFIG_MIPS32 */ #ifdef CONFIG_MIPS64 +/* + * This handles the memory map. + */ +#ifdef CONFIG_DMA_NONCOHERENT +#define PAGE_OFFSET 0x9800000000000000UL +#else +#define PAGE_OFFSET 0xa800000000000000UL +#endif + +/* + * Memory above this physical address will be considered highmem. + * Fixme: 59 bits is a fictive number and makes assumptions about processors + * in the distant future. Nobody will care for a few years :-) + */ +#ifndef HIGHMEM_START +#define HIGHMEM_START (1UL << 59UL) +#endif + #ifdef CONFIG_DMA_NONCOHERENT #define CAC_BASE 0x9800000000000000 #else @@ -38,4 +69,4 @@ #endif /* CONFIG_MIPS64 */ -#endif /* _ASM_MACH_SPACES_H */ +#endif /* __ASM_MACH_GENERIC_SPACES_H */ diff --git a/include/asm-mips/mach-generic/topology.h b/include/asm-mips/mach-generic/topology.h new file mode 100644 index 000000000000..5428f333a02c --- /dev/null +++ b/include/asm-mips/mach-generic/topology.h @@ -0,0 +1 @@ +#include <asm-generic/topology.h> diff --git a/include/asm-mips/mach-ip27/mmzone.h b/include/asm-mips/mach-ip27/mmzone.h index 724d5dba8347..4d95609b1c72 100644 --- a/include/asm-mips/mach-ip27/mmzone.h +++ b/include/asm-mips/mach-ip27/mmzone.h @@ -2,6 +2,7 @@ #define _ASM_MACH_MMZONE_H #include <asm/sn/addrs.h> +#include <asm/sn/arch.h> #define pa_to_nid(addr) NASID_TO_COMPACT_NODEID(NASID_GET(addr)) diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h index b3137a9a22de..e0cf74d32937 100644 --- a/include/asm-mips/mach-ip27/spaces.h +++ b/include/asm-mips/mach-ip27/spaces.h @@ -27,4 +27,8 @@ #define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) #define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) +#define PAGE_OFFSET CAC_BASE + +#define HIGHMEM_START (~0UL) + #endif /* _ASM_MACH_SPACES_H */ diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h new file mode 100644 index 000000000000..0e9312613748 --- /dev/null +++ b/include/asm-mips/mach-ip27/topology.h @@ -0,0 +1,18 @@ +#ifndef _ASM_MACH_TOPOLOGY_H +#define _ASM_MACH_TOPOLOGY_H 1 + +#include <asm/sn/hub.h> + +#define cpu_to_node(cpu) (cpu_data[(cpu)].p_nodeid) +#define parent_node(node) (node) +#define node_to_cpumask(node) (HUB_DATA(node)->h_cpus) +#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node))) +#define pcibus_to_cpumask(bus) (cpu_online_map) + +extern int node_distance(nasid_t nasid_a, nasid_t nasid_b); +#define node_distance(from, to) node_distance(from, to) + +/* Cross-node load balancing interval. */ +#define NODE_BALANCE_RATE 10 + +#endif /* _ASM_MACH_TOPOLOGY_H */ diff --git a/include/asm-mips/mach-ip32/mc146818rtc.h b/include/asm-mips/mach-ip32/mc146818rtc.h index 3d98e355111c..3024a2145f8c 100644 --- a/include/asm-mips/mach-ip32/mc146818rtc.h +++ b/include/asm-mips/mach-ip32/mc146818rtc.h @@ -19,14 +19,18 @@ static unsigned char CMOS_READ(unsigned long addr) { - return readb(mace->isa.rtc + addr); + return mace->isa.rtc[addr << 8]; } static inline void CMOS_WRITE(unsigned char data, unsigned long addr) { - writeb(data, mace->isa.rtc + addr); + mace->isa.rtc[addr << 8] = data; } +/* FIXME: Do it right. For now just assume that noone lives in 20th century + * and no O2 user in 22th century ;-) */ +#define mc146818_decode_year(year) ((year) + 2000) + #define RTC_ALWAYS_BCD 0 #endif /* __ASM_MACH_IP32_MC146818RTC_H */ diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h new file mode 100644 index 000000000000..2dce66f287ef --- /dev/null +++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h @@ -0,0 +1,38 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2003, 2004 Ralf Baechle + */ +#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H + +/* + * Momentum Jaguar ATX always has the RM9000 processor. + */ +#define cpu_has_watch 1 +#define cpu_has_mips16 0 +#define cpu_has_divec 0 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 0 +#define cpu_has_ejtag 0 + +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 0 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 1 + +#define cpu_has_subset_pcaches 0 + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 32 + +#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */ diff --git a/include/asm-mips/mach-ja/spaces.h b/include/asm-mips/mach-ja/spaces.h new file mode 100644 index 000000000000..8466a0e69c79 --- /dev/null +++ b/include/asm-mips/mach-ja/spaces.h @@ -0,0 +1,20 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. + */ +#ifndef __ASM_MACH_JA_SPACES_H +#define __ASM_MACH_JA_SPACES_H + +/* + * Memory above this physical address will be considered highmem. + */ +#define HIGHMEM_START 0x08000000UL + +#include_next <spaces.h> + +#endif /* __ASM_MACH_JA_SPACES_H */ diff --git a/include/asm-mips/mach-mips/mc146818rtc.h b/include/asm-mips/mach-mips/mc146818rtc.h index 893ecf7cfb1c..6730ba066576 100644 --- a/include/asm-mips/mach-mips/mc146818rtc.h +++ b/include/asm-mips/mach-mips/mc146818rtc.h @@ -43,4 +43,6 @@ static inline void CMOS_WRITE(unsigned char data, unsigned long addr) #define RTC_ALWAYS_BCD 0 +#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) + #endif /* __ASM_MACH_MALTA_MC146818RTC_H */ diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h new file mode 100644 index 000000000000..5d28b40fa62e --- /dev/null +++ b/include/asm-mips/mach-pb1x00/pb1550.h @@ -0,0 +1,157 @@ +/* + * AMD Alchemy Semi PB1550 Referrence Board + * Board Registers defines. + * + * Copyright 2004 Embedded Edge LLC. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + * + */ +#ifndef __ASM_PB1550_H +#define __ASM_PB1550_H + +#include <linux/types.h> + +#define BCSR_PHYS_ADDR 0xAF000000 + +typedef volatile struct +{ + /*00*/ u16 whoami; + u16 reserved0; + /*04*/ u16 status; + u16 reserved1; + /*08*/ u16 switches; + u16 reserved2; + /*0C*/ u16 resets; + u16 reserved3; + /*10*/ u16 pcmcia; + u16 reserved4; + /*14*/ u16 pci; + u16 reserved5; + /*18*/ u16 leds; + u16 reserved6; + /*1C*/ u16 system; + u16 reserved7; + +} BCSR; + +static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; + +/* + * Register bit definitions for the BCSRs + */ +#define BCSR_WHOAMI_DCID 0x000F +#define BCSR_WHOAMI_CPLD 0x00F0 +#define BCSR_WHOAMI_BOARD 0x0F00 + +#define BCSR_STATUS_PCMCIA0VS 0x0003 +#define BCSR_STATUS_PCMCIA1VS 0x000C +#define BCSR_STATUS_PCMCIA0FI 0x0010 +#define BCSR_STATUS_PCMCIA1FI 0x0020 +#define BCSR_STATUS_SWAPBOOT 0x0040 +#define BCSR_STATUS_SRAMWIDTH 0x0080 +#define BCSR_STATUS_FLASHBUSY 0x0100 +#define BCSR_STATUS_ROMBUSY 0x0200 +#define BCSR_STATUS_USBOTGID 0x0800 +#define BCSR_STATUS_U0RXD 0x1000 +#define BCSR_STATUS_U1RXD 0x2000 +#define BCSR_STATUS_U3RXD 0x8000 + +#define BCSR_SWITCHES_OCTAL 0x00FF +#define BCSR_SWITCHES_DIP_1 0x0080 +#define BCSR_SWITCHES_DIP_2 0x0040 +#define BCSR_SWITCHES_DIP_3 0x0020 +#define BCSR_SWITCHES_DIP_4 0x0010 +#define BCSR_SWITCHES_DIP_5 0x0008 +#define BCSR_SWITCHES_DIP_6 0x0004 +#define BCSR_SWITCHES_DIP_7 0x0002 +#define BCSR_SWITCHES_DIP_8 0x0001 +#define BCSR_SWITCHES_ROTARY 0x0F00 + +#define BCSR_RESETS_PHY0 0x0001 +#define BCSR_RESETS_PHY1 0x0002 +#define BCSR_RESETS_DC 0x0004 +#define BCSR_RESETS_WSC 0x2000 +#define BCSR_RESETS_SPISEL 0x4000 +#define BCSR_RESETS_DMAREQ 0x8000 + +#define BCSR_PCMCIA_PC0VPP 0x0003 +#define BCSR_PCMCIA_PC0VCC 0x000C +#define BCSR_PCMCIA_PC0DRVEN 0x0010 +#define BCSR_PCMCIA_PC0RST 0x0080 +#define BCSR_PCMCIA_PC1VPP 0x0300 +#define BCSR_PCMCIA_PC1VCC 0x0C00 +#define BCSR_PCMCIA_PC1DRVEN 0x1000 +#define BCSR_PCMCIA_PC1RST 0x8000 + +#define BCSR_PCI_M66EN 0x0001 +#define BCSR_PCI_M33 0x0100 +#define BCSR_PCI_EXTERNARB 0x0200 +#define BCSR_PCI_GPIO200RST 0x0400 +#define BCSR_PCI_CLKOUT 0x0800 +#define BCSR_PCI_CFGHOST 0x1000 + +#define BCSR_LEDS_DECIMALS 0x00FF +#define BCSR_LEDS_LED0 0x0100 +#define BCSR_LEDS_LED1 0x0200 +#define BCSR_LEDS_LED2 0x0400 +#define BCSR_LEDS_LED3 0x0800 + +#define BCSR_SYSTEM_VDDI 0x001F +#define BCSR_SYSTEM_POWEROFF 0x4000 +#define BCSR_SYSTEM_RESET 0x8000 + +#define PCMCIA_MAX_SOCK 1 +#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) + +/* VPP/VCC */ +#define SET_VCC_VPP(VCC, VPP, SLOT)\ + ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) + +#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) +#define PB1550_BOTH_BANKS +#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER) +#define PB1550_BOOT_ONLY +#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) +#define PB1550_USER_ONLY +#endif + +/* Timing values as described in databook, * ns value stripped of + * lower 2 bits. + * These defines are here rather than an SOC1550 generic file because + * the parts chosen on another board may be different and may require + * different timings. + */ +#define NAND_T_H (18 >> 2) +#define NAND_T_PUL (30 >> 2) +#define NAND_T_SU (30 >> 2) +#define NAND_T_WH (30 >> 2) + +/* Bitfield shift amounts */ +#define NAND_T_H_SHIFT 0 +#define NAND_T_PUL_SHIFT 4 +#define NAND_T_SU_SHIFT 8 +#define NAND_T_WH_SHIFT 12 + +#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ + ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ + ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ + ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) + +#endif /* __ASM_PB1550_H */ diff --git a/include/asm-mips/mc146818-time.h b/include/asm-mips/mc146818-time.h index 5da4f3a12fc6..a2c2d2c24303 100644 --- a/include/asm-mips/mc146818-time.h +++ b/include/asm-mips/mc146818-time.h @@ -120,8 +120,7 @@ static inline unsigned long mc146818_get_cmos_time(void) BCD_TO_BIN(mon); BCD_TO_BIN(year); } - if ((year += 1900) < 1970) - year += 100; + year = mc146818_decode_year(year); return mktime(year, mon, day, hour, min, sec); } diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 66f5d2e02ff2..8bdab9794feb 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h @@ -632,6 +632,24 @@ do { \ } while (0) /* + * On The RM7000 these are use to access cop0 set 1 registers + */ +#define __read_32bit_c0_ctrl_register(source) \ +({ int __res; \ + __asm__ __volatile__( \ + "cfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __write_32bit_c0_ctrl_register(register, value) \ +do { \ + __asm__ __volatile__( \ + "ctc0\t%z0, " #register "\n\t" \ + : : "Jr" ((unsigned int)value)); \ +} while (0) + +/* * These versions are only needed for systems with more than 38 bits of * physical address space running the 32-bit kernel. That's none atm :-) */ @@ -791,12 +809,30 @@ do { \ #define read_c0_xcontext() __read_ulong_c0_register($20, 0) #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) -#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) -#define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) +#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) +#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) #define read_c0_framemask() __read_32bit_c0_register($21, 0) #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) +#define read_c0_diag() __read_32bit_c0_register($22, 0) +#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) + +#define read_c0_diag1() __read_32bit_c0_register($22, 1) +#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) + +#define read_c0_diag2() __read_32bit_c0_register($22, 2) +#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) + +#define read_c0_diag3() __read_32bit_c0_register($22, 3) +#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) + +#define read_c0_diag4() __read_32bit_c0_register($22, 4) +#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) + +#define read_c0_diag5() __read_32bit_c0_register($22, 5) +#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) + #define read_c0_debug() __read_32bit_c0_register($23, 0) #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) @@ -838,51 +874,45 @@ do { \ /* * TLB operations. + * + * It is responsibility of the caller to take care of any TLB hazards. */ static inline void tlb_probe(void) { - rm9000_tlb_hazard(); __asm__ __volatile__( ".set noreorder\n\t" "tlbp\n\t" ".set reorder"); - rm9000_tlb_hazard(); } static inline void tlb_read(void) { - rm9000_tlb_hazard(); __asm__ __volatile__( ".set noreorder\n\t" "tlbr\n\t" ".set reorder"); - rm9000_tlb_hazard(); } static inline void tlb_write_indexed(void) { - rm9000_tlb_hazard(); __asm__ __volatile__( ".set noreorder\n\t" "tlbwi\n\t" ".set reorder"); - rm9000_tlb_hazard(); } static inline void tlb_write_random(void) { - rm9000_tlb_hazard(); __asm__ __volatile__( ".set noreorder\n\t" "tlbwr\n\t" ".set reorder"); - rm9000_tlb_hazard(); } /* * Manipulate bits in a c0 register. */ -#define __BUILD_SET_C0(name,register) \ +#define __BUILD_SET_C0(name) \ static inline unsigned int \ set_c0_##name(unsigned int set) \ { \ @@ -920,10 +950,10 @@ change_c0_##name(unsigned int change, unsigned int new) \ return res; \ } -__BUILD_SET_C0(status,CP0_STATUS) -__BUILD_SET_C0(cause,CP0_CAUSE) -__BUILD_SET_C0(config,CP0_CONFIG) -__BUILD_SET_C0(intcontrol,CP0_CONFIG) +__BUILD_SET_C0(status) +__BUILD_SET_C0(cause) +__BUILD_SET_C0(config) +__BUILD_SET_C0(intcontrol) #endif /* !__ASSEMBLY__ */ diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h index 79c40323a615..e42794180211 100644 --- a/include/asm-mips/mmu_context.h +++ b/include/asm-mips/mmu_context.h @@ -45,6 +45,11 @@ extern unsigned long pgd_current[]; #define ASID_INC 0x40 #define ASID_MASK 0xfc0 +#elif defined(CONFIG_CPU_RM9000) + +#define ASID_INC 0x1 +#define ASID_MASK 0xfff + #else /* FIXME: not correct for R6000, R8000 */ #define ASID_INC 0x1 diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h index 39bcec8134e8..99635e6b610e 100644 --- a/include/asm-mips/module.h +++ b/include/asm-mips/module.h @@ -1,14 +1,41 @@ #ifndef _ASM_MODULE_H #define _ASM_MODULE_H +#include <linux/config.h> + struct mod_arch_specific { /* Data Bus Error exception tables */ const struct exception_table_entry *dbe_table_start; const struct exception_table_entry *dbe_table_end; }; -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr +typedef uint8_t Elf64_Byte; /* Type for a 8-bit quantity. */ + +typedef struct +{ + Elf64_Addr r_offset; /* Address of relocation. */ + Elf64_Word r_sym; /* Symbol index. */ + Elf64_Byte r_ssym; /* Special symbol. */ + Elf64_Byte r_type3; /* Third relocation. */ + Elf64_Byte r_type2; /* Second relocation. */ + Elf64_Byte r_type; /* First relocation. */ + Elf64_Sxword r_addend; /* Addend. */ +} Elf64_Mips_Rela; + +#ifdef CONFIG_MIPS32 + +#define Elf_Shdr Elf32_Shdr +#define Elf_Sym Elf32_Sym +#define Elf_Ehdr Elf32_Ehdr + +#endif + +#ifdef CONFIG_MIPS64 + +#define Elf_Shdr Elf64_Shdr +#define Elf_Sym Elf64_Sym +#define Elf_Ehdr Elf64_Ehdr + +#endif #endif /* _ASM_MODULE_H */ diff --git a/include/asm-mips/mv64340.h b/include/asm-mips/mv64340.h index 13caa2fc663b..442f2fbf7341 100644 --- a/include/asm-mips/mv64340.h +++ b/include/asm-mips/mv64340.h @@ -2,18 +2,19 @@ * mv64340.h - MV-64340 Internal registers definition file. * * Copyright 2002 Momentum Computer, Inc. + * Author: Matthew Dharm <mdharm@momenco.com> * Copyright 2002 GALILEO TECHNOLOGY, LTD. * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * */ #ifndef __ASM_MV64340_H #define __ASM_MV64340_H -#include <asm/mv64340_dep.h> +#include <asm/addrspace.h> +#include <asm/byteorder.h> /****************************************/ /* Processor Address Space */ @@ -1033,9 +1034,38 @@ #define MV64340_SERIAL_INIT_CONTROL 0xf328 #define MV64340_SERIAL_INIT_STATUS 0xf32c -struct pci; +extern unsigned long mv64340_base; + +#define MV64340_BASE (mv64340_base) + +/* + * Because of an error/peculiarity in the Galileo chip, we need to swap the + * bytes when running bigendian. + */ + +#define MV_WRITE(ofs, data) \ + *(volatile u32 *)(MV64340_BASE + (ofs)) = cpu_to_le32((u32)data) +#define MV_READ(ofs) \ + (le32_to_cpu(*(volatile u32 *)(MV64340_BASE + (ofs)))) + +#define MV_WRITE_16(ofs, data) \ + *(volatile u16 *)(MV64340_BASE + (ofs)) = cpu_to_le16((u16)data) +#define MV_READ_16(ofs) \ + le16_to_cpu(*(volatile u16 *)(MV64340_BASE + (ofs))) + +#define MV_WRITE_8(ofs, data) \ + *(volatile u8 *)(MV64340_BASE + (ofs)) = ((u16)data) +#define MV_READ_8(ofs) \ + (*(volatile u8 *)(MV64340_BASE + (ofs))) + +#define MV_SET_REG_BITS(ofs, bits) \ + (*((volatile u32 *)(MV64340_BASE + (ofs)))) |= ((u32)cpu_to_le32(bits)) +#define MV_RESET_REG_BITS(ofs, bits) \ + (*((volatile u32 *)(MV64340_BASE + (ofs)))) &= ~((u32)cpu_to_le32(bits)) + +extern void mv64340_irq_init(unsigned int base); -extern mv64340_bus0_pci_ops; -extern mv64340_bus1_pci_ops; +extern struct pci_ops mv64340_bus0_pci_ops; +extern struct pci_ops mv64340_bus1_pci_ops; #endif /* __ASM_MV64340_H */ diff --git a/include/asm-mips/mv64340_dep.h b/include/asm-mips/mv64340_dep.h deleted file mode 100644 index f550fdfba7fa..000000000000 --- a/include/asm-mips/mv64340_dep.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm <mdharm@momenco.com> - * - * include/asm-mips/mv64340-dep.h - * Board-dependent definitions for MV-64340 chip. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#ifndef __MV64340_DEP_H__ -#define __MV64340_DEP_H__ - -#include <asm/addrspace.h> /* for KSEG1ADDR() */ -#include <asm/byteorder.h> /* for cpu_to_le32() */ - -extern unsigned long mv64340_base; - -#define MV64340_BASE (mv64340_base) - -/* - * Because of an error/peculiarity in the Galileo chip, we need to swap the - * bytes when running bigendian. - */ - -#define MV_WRITE(ofs, data) \ - *(volatile u32 *)(MV64340_BASE+(ofs)) = cpu_to_le32(data) -#define MV_READ(ofs, data) \ - *(data) = le32_to_cpu(*(volatile u32 *)(MV64340_BASE+(ofs))) -#define MV_READ_DATA(ofs) \ - le32_to_cpu(*(volatile u32 *)(MV64340_BASE+(ofs))) - -#define MV_WRITE_16(ofs, data) \ - *(volatile u16 *)(MV64340_BASE+(ofs)) = cpu_to_le16(data) -#define MV_READ_16(ofs, data) \ - *(data) = le16_to_cpu(*(volatile u16 *)(MV64340_BASE+(ofs))) - -#define MV_WRITE_8(ofs, data) \ - *(volatile u8 *)(MV64340_BASE+(ofs)) = data -#define MV_READ_8(ofs, data) \ - *(data) = *(volatile u8 *)(MV64340_BASE+(ofs)) - -#define MV_SET_REG_BITS(ofs,bits) \ - (*((volatile u32 *)(MV64340_BASE+(ofs)))) |= ((u32)cpu_to_le32(bits)) -#define MV_RESET_REG_BITS(ofs,bits) \ - (*((volatile u32 *)(MV64340_BASE+(ofs)))) &= ~((u32)cpu_to_le32(bits)) - -#endif diff --git a/include/asm-mips/page-32.h b/include/asm-mips/page-32.h deleted file mode 100644 index ad1421de54c0..000000000000 --- a/include/asm-mips/page-32.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PAGE_32_H -#define _ASM_PAGE_32_H - -/* - * This handles the memory map. - * We handle pages at KSEG0 for kernels with 32 bit address space. - */ -#define PAGE_OFFSET 0x80000000UL - -/* - * Memory above this physical address will be considered highmem. - */ -#define HIGHMEM_START 0x20000000UL - -#endif /* _ASM_PAGE_32_H */ diff --git a/include/asm-mips/page-64.h b/include/asm-mips/page-64.h deleted file mode 100644 index d8e1591c23ea..000000000000 --- a/include/asm-mips/page-64.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_PAGE_64_H -#define _ASM_PAGE_64_H - -#include <linux/config.h> - -/* - * This handles the memory map. - */ -#ifdef CONFIG_DMA_NONCOHERENT -#define PAGE_OFFSET 0x9800000000000000UL -#else -#define PAGE_OFFSET 0xa800000000000000UL -#endif - -/* - * Memory above this physical address will be considered highmem. - * Fixme: 59 bits is a fictive number and makes assumptions about processors - * in the distant future. Nobody will care for a few years :-) - */ -#define HIGHMEM_START (1UL << 59UL) - -#endif /* _ASM_PAGE_64_H */ diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 6d2352350fa1..37de18f63b43 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h @@ -10,13 +10,7 @@ #define _ASM_PAGE_H #include <linux/config.h> - -#ifdef CONFIG_MIPS32 -#include <asm/page-32.h> -#endif -#ifdef CONFIG_MIPS64 -#include <asm/page-64.h> -#endif +#include <spaces.h> #ifdef __KERNEL__ @@ -135,4 +129,8 @@ static __inline__ int get_order(unsigned long size) #endif /* defined (__KERNEL__) */ +#ifdef CONFIG_LIMITED_DMA +#define WANT_PAGE_VIRTUAL +#endif + #endif /* _ASM_PAGE_H */ diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h index 3d133a6a3ffc..4f96427f89f4 100644 --- a/include/asm-mips/pgalloc.h +++ b/include/asm-mips/pgalloc.h @@ -122,12 +122,6 @@ static inline void pmd_free(pmd_t *pmd) #endif -/* - * Used for the b0rked handling of kernel pagetables on the 64-bit kernel. - */ -extern pte_t kptbl[(PAGE_SIZE << PGD_ORDER)/sizeof(pte_t)]; -extern pmd_t kpmdtbl[PTRS_PER_PMD]; - #define check_pgt_cache() do { } while (0) #endif /* _ASM_PGALLOC_H */ diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h index 0673441399be..2bd879e4c27a 100644 --- a/include/asm-mips/pgtable-64.h +++ b/include/asm-mips/pgtable-64.h @@ -216,4 +216,10 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset) typedef pte_t *pte_addr_t; +/* + * Used for the b0rked handling of kernel pagetables on the 64-bit kernel. + */ +extern pte_t kptbl[(PAGE_SIZE << PGD_ORDER)/sizeof(pte_t)]; +extern pmd_t kpmdtbl[PTRS_PER_PMD]; + #endif /* _ASM_PGTABLE_64_H */ diff --git a/include/asm-mips/prefetch.h b/include/asm-mips/prefetch.h index 799a8a69d394..0b712cac8b19 100644 --- a/include/asm-mips/prefetch.h +++ b/include/asm-mips/prefetch.h @@ -21,8 +21,9 @@ * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements * Pref_PrepareForStore also. * - * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; - * it's Pref_WriteBackInvalidate is a nop. + * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's + * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in + * current versions due to erratum G105. * * VR7701 only implements the Load prefetch. * diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index 769719bee46a..f13b15ac0b10 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h @@ -18,11 +18,11 @@ #include <asm/cachectl.h> #include <asm/cpu.h> #include <asm/mipsregs.h> +#include <asm/prefetch.h> #include <asm/system.h> #ifdef CONFIG_SGI_IP27 #include <asm/sn/types.h> -#include <asm/sn/intr_public.h> #endif /* @@ -53,7 +53,6 @@ struct cpuinfo_mips { cnodeid_t p_nodeid; /* my node ID in compact-id-space */ nasid_t p_nasid; /* my node ID in numa-as-id-space */ unsigned char p_slice; /* Physical position on node board */ - struct hub_intmasks_s p_intmasks; /* SN0 per-CPU interrupt masks */ #endif #if 0 unsigned long loops_per_sec; @@ -77,6 +76,7 @@ struct cpuinfo_mips { struct cache_desc dcache; /* Primary D or combined I/D cache */ struct cache_desc scache; /* Secondary cache */ struct cache_desc tcache; /* Tertiary/split secondary cache */ + void *data; /* Additional data */ } __attribute__((aligned(SMP_CACHE_BYTES))); extern struct cpuinfo_mips cpu_data[]; @@ -287,4 +287,20 @@ static inline unsigned long long sched_clock(void) return 0ULL; } +#ifdef CONFIG_CPU_HAS_PREFETCH + +#define ARCH_HAS_PREFETCH + +extern inline void prefetch(const void *addr) +{ + __asm__ __volatile__( + " .set mips4 \n" + " pref %0, (%1) \n" + " .set mips0 \n" + : + : "i" (Pref_Load), "r" (addr)); +} + +#endif + #endif /* _ASM_PROCESSOR_H */ diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h index 4711c0e7af43..ae455b04b31a 100644 --- a/include/asm-mips/serial.h +++ b/include/asm-mips/serial.h @@ -233,16 +233,23 @@ #define HUB6_SERIAL_PORT_DFNS #endif -#ifdef CONFIG_MCA -#define MCA_SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, 0x3220, 3, STD_COM_FLAGS }, \ - { 0, BASE_BAUD, 0x3228, 3, STD_COM_FLAGS }, \ - { 0, BASE_BAUD, 0x4220, 3, STD_COM_FLAGS }, \ - { 0, BASE_BAUD, 0x4228, 3, STD_COM_FLAGS }, \ - { 0, BASE_BAUD, 0x5220, 3, STD_COM_FLAGS }, \ - { 0, BASE_BAUD, 0x5228, 3, STD_COM_FLAGS }, +#ifdef CONFIG_MOMENCO_JAGUAR_ATX +/* Ordinary NS16552 duart with a 20MHz crystal. */ +#define JAGUAR_ATX_UART_CLK 20000000 +#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16) + +#define JAGUAR_ATX_SERIAL1_IRQ 6 +#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L + +#define _JAGUAR_ATX_SERIAL_INIT(int, base) \ + { baud_base: JAGUAR_ATX_BASE_BAUD, irq: int, \ + flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ + iomem_base: (u8 *) base, iomem_reg_shift: 2, \ + io_type: SERIAL_IO_MEM } +#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \ + _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE) #else -#define MCA_SERIAL_PORT_DFNS +#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS #endif #ifdef CONFIG_MOMENCO_OCELOT diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h index 7afa8a2501ce..d7b11b6c7c32 100644 --- a/include/asm-mips/sibyte/board.h +++ b/include/asm-mips/sibyte/board.h @@ -56,8 +56,6 @@ #else -void swarm_setup(void); - #ifdef LEDS_PHYS extern void setleds(char *str); #else diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h index 4c9d2618ee8d..4146d42d48fe 100644 --- a/include/asm-mips/smp.h +++ b/include/asm-mips/smp.h @@ -117,6 +117,8 @@ static inline void smp_send_reschedule(int cpu) core_send_ipi(cpu, SMP_RESCHEDULE_YOURSELF); } +extern asmlinkage void smp_call_function_interrupt(void); + #endif /* CONFIG_SMP */ #endif /* __ASM_SMP_H */ diff --git a/include/asm-mips/sn/agent.h b/include/asm-mips/sn/agent.h index 2502069c2a35..d6df13aaed49 100644 --- a/include/asm-mips/sn/agent.h +++ b/include/asm-mips/sn/agent.h @@ -12,9 +12,9 @@ #define _ASM_SGI_SN_AGENT_H #include <linux/config.h> +#include <linux/topology.h> #include <asm/sn/addrs.h> #include <asm/sn/arch.h> -//#include <asm/sn/io.h> #if defined(CONFIG_SGI_IP27) #include <asm/sn/sn0/hub.h> @@ -28,7 +28,7 @@ #if defined(CONFIG_SGI_IP27) #define HUB_NIC_ADDR(_cpuid) \ - REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(_cpuid)), \ + REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)), \ MD_MLAN_CTL) #endif diff --git a/include/asm-mips/sn/arch.h b/include/asm-mips/sn/arch.h index ef03180e2dde..d247a819de7f 100644 --- a/include/asm-mips/sn/arch.h +++ b/include/asm-mips/sn/arch.h @@ -11,38 +11,21 @@ #ifndef _ASM_SN_ARCH_H #define _ASM_SN_ARCH_H -#include <linux/types.h> #include <linux/config.h> - -#if !defined(CONFIG_SGI_IO) +#include <linux/types.h> #include <asm/sn/types.h> +#ifdef CONFIG_SGI_IP27 #include <asm/sn/sn0/arch.h> #endif - -#ifndef __ASSEMBLY__ -#if !defined(CONFIG_SGI_IO) typedef u64 hubreg_t; typedef u64 nic_t; -#endif -#endif - -#ifdef CONFIG_SGI_IP27 -#define CPUS_PER_NODE 2 /* CPUs on a single hub */ -#define CPUS_PER_NODE_SHFT 1 /* Bits to shift in the node number */ -#define CPUS_PER_SUBNODE 2 /* CPUs on a single hub PI */ -#endif -#define CNODE_NUM_CPUS(_cnode) (NODEPDA(_cnode)->node_num_cpus) -#define CNODE_TO_CPU_BASE(_cnode) (NODEPDA(_cnode)->node_first_cpu) -#define cputocnode(cpu) (cpu_data[(cpu)].p_nodeid) #define cputonasid(cpu) (cpu_data[(cpu)].p_nasid) #define cputoslice(cpu) (cpu_data[(cpu)].p_slice) #define makespnum(_nasid, _slice) \ (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice)) -#ifndef __ASSEMBLY__ - #define INVALID_NASID (nasid_t)-1 #define INVALID_CNODEID (cnodeid_t)-1 #define INVALID_PNODEID (pnodeid_t)-1 @@ -72,45 +55,12 @@ extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES]; ((nnode) >> \ (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT)) -#if !defined(_STANDALONE) extern cnodeid_t nasid_to_compact_node[MAX_NASIDS]; extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES]; extern cnodeid_t cpuid_to_compact_node[MAXCPUS]; -#endif - -#if !defined(DEBUG) && (!defined(SABLE) || defined(_STANDALONE)) #define NASID_TO_COMPACT_NODEID(nnode) (nasid_to_compact_node[nnode]) #define COMPACT_TO_NASID_NODEID(cnode) (compact_to_nasid_node[cnode]) #define CPUID_TO_COMPACT_NODEID(cpu) (cpuid_to_compact_node[(cpu)]) -#else - -/* - * These functions can do type checking and fail if they need to return - * a bad nodeid, but they're not as fast so just use 'em for debug kernels. - */ -cnodeid_t nasid_to_compact_nodeid(nasid_t nasid); -nasid_t compact_to_nasid_nodeid(cnodeid_t cnode); - -#define NASID_TO_COMPACT_NODEID(nnode) nasid_to_compact_nodeid(nnode) -#define COMPACT_TO_NASID_NODEID(cnode) compact_to_nasid_nodeid(cnode) -#define CPUID_TO_COMPACT_NODEID(cpu) (cpuid_to_compact_node[(cpu)]) -#endif - -#endif /* !__ASSEMBLY__ */ - -#define SLOT_BITMASK (MAX_MEM_SLOTS - 1) -#define SLOT_SIZE (1LL<<SLOT_SHIFT) -#define node_getnumslots(node) (MAX_MEM_SLOTS) -#define NODE_MAX_MEM_SIZE SLOT_SIZE * MAX_MEM_SLOTS - -/* - * New stuff in here from Irix sys/pfdat.h. - */ -#define SLOT_PFNSHIFT (SLOT_SHIFT - PAGE_SHIFT) -#define PFN_NASIDSHFT (NASID_SHFT - PAGE_SHIFT) -#define mkpfn(nasid, off) (((pfn_t)(nasid) << PFN_NASIDSHFT) | (off)) -#define slot_getbasepfn(node,slot) \ - (mkpfn(COMPACT_TO_NASID_NODEID(node), slot<<SLOT_PFNSHIFT)) #endif /* _ASM_SN_ARCH_H */ diff --git a/include/asm-mips/sn/hub.h b/include/asm-mips/sn/hub.h index 17bfedb6456c..89b92104f97e 100644 --- a/include/asm-mips/sn/hub.h +++ b/include/asm-mips/sn/hub.h @@ -1,15 +1,35 @@ #ifndef __ASM_SN_HUB_H #define __ASM_SN_HUB_H +#include <linux/types.h> +#include <linux/cpumask.h> #include <asm/sn/types.h> #include <asm/sn/io.h> #include <asm/sn/klkernvars.h> +#include <asm/xtalk/xtalk.h> + +#define LEVELS_PER_SLICE 128 + +struct slice_data { + unsigned long irq_alloc_mask[2]; + unsigned long irq_enable_mask[2]; + int level_to_irq[LEVELS_PER_SLICE]; +}; struct hub_data { kern_vars_t kern_vars; + DECLARE_BITMAP (h_bigwin_used, HUB_NUM_BIG_WINDOW); + cpumask_t h_cpus; + unsigned long slice_map; + struct slice_data slice[2]; }; extern struct hub_data *hub_data[]; #define HUB_DATA(n) (hub_data[(n)]) +/* ip27-hubio.c */ +extern unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget, + unsigned long xtalk_addr, size_t size); +extern void hub_pio_init(cnodeid_t cnode); + #endif /* __ASM_SN_HUB_H */ diff --git a/include/asm-mips/sn/intr_public.h b/include/asm-mips/sn/intr_public.h deleted file mode 100644 index 7521889ad4c8..000000000000 --- a/include/asm-mips/sn/intr_public.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997 Silicon Graphics, Inc. - */ -#ifndef __ASM_SN_INTR_PUBLIC_H -#define __ASM_SN_INTR_PUBLIC_H - -#include <asm/sn/arch.h> - -/* - * The following are necessary to create the illusion of a CEL on the SN0 hub. - * We'll add more priority levels soon, but for now, any interrupt in a - * particular band effectively does an spl. These must be in the PDA since - * they're different for each processor. Users of this structure must hold the - * vector_lock in the appropriate vector block before modifying the mask arrays. - * There's only one vector block for each Hub so a lock in the PDA wouldn't be - * adequate. - */ -struct hub_intmasks_s { - /* - * The masks are stored with the lowest-priority (most inclusive) - * in the lowest-numbered masks (i.e., 0, 1, 2...). - */ - hubreg_t intpend0_masks; /* INT_PEND0 */ - hubreg_t intpend1_masks; /* INT_PEND1 */ -}; - -#endif /* __ASM_SN_INTR_PUBLIC_H */ diff --git a/include/asm-mips/sn/io.h b/include/asm-mips/sn/io.h index 2b4eee31e2a4..13326453efc9 100644 --- a/include/asm-mips/sn/io.h +++ b/include/asm-mips/sn/io.h @@ -10,8 +10,10 @@ #define _ASM_SN_IO_H #include <linux/config.h> +#if defined (CONFIG_SGI_IP27) +#include <asm/sn/sn0/hubio.h> +#endif -#ifdef CONFIG_SGI_IO #define IIO_ITTE_BASE 0x400160 /* base of translation table entries */ #define IIO_ITTE(bigwin) (IIO_ITTE_BASE + 8*(bigwin)) @@ -55,14 +57,4 @@ (_x) : \ (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) -#if defined (CONFIG_SGI_IP27) -#include <asm/sn/sn0/hubio.h> -#endif - -#else /* CONFIG_SGI_IO */ - -#include <asm/sn/sn0/addrs.h> - -#endif /* CONFIG_SGI_IO */ - #endif /* _ASM_SN_IO_H */ diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h index a83acb78c3e1..0e00dd474afc 100644 --- a/include/asm-mips/sn/sn0/arch.h +++ b/include/asm-mips/sn/sn0/arch.h @@ -82,4 +82,8 @@ #define SLOT_MIN_MEM_SIZE (32*1024*1024) #endif +#define CPUS_PER_NODE 2 /* CPUs on a single hub */ +#define CPUS_PER_NODE_SHFT 1 /* Bits to shift in the node number */ +#define CPUS_PER_SUBNODE 2 /* CPUs on a single hub PI */ + #endif /* _ASM_SN_SN0_ARCH_H */ diff --git a/include/asm-mips/sn/sn_private.h b/include/asm-mips/sn/sn_private.h index a17c0a0c911e..8229c6e29a91 100644 --- a/include/asm-mips/sn/sn_private.h +++ b/include/asm-mips/sn/sn_private.h @@ -16,5 +16,6 @@ extern void install_ipi(void); extern void setup_replication_mask(int); extern void replicate_kernel_text(int); extern pfn_t node_getfirstfree(cnodeid_t); +extern void mlreset(void); #endif /* __ASM_SN_SN_PRIVATE_H */ diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h index 0b57b65f8f21..d2575ae422f0 100644 --- a/include/asm-mips/spinlock.h +++ b/include/asm-mips/spinlock.h @@ -167,4 +167,28 @@ static inline void _raw_write_unlock(rwlock_t *rw) : "memory"); } +static inline int _raw_write_trylock(rwlock_t *rw) +{ + unsigned int tmp; + int ret; + + __asm__ __volatile__( + ".set\tnoreorder\t\t\t# _raw_write_trylock\n" + "li\t%2, 0\n\t" + "1:\tll\t%1, %3\n\t" + "bnez\t%1, 2f\n\t" + "lui\t%1, 0x8000\n\t" + "sc\t%1, %0\n\t" + "beqz\t%1, 1b\n\t" + "sync\n\t" + "li\t%2, 1\n\t" + ".set\treorder\n" + "2:" + : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) + : "m" (rw->lock) + : "memory"); + + return ret; +} + #endif /* _ASM_SPINLOCK_H */ diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h index e84aed10221b..626a8ab288e1 100644 --- a/include/asm-mips/stackframe.h +++ b/include/asm-mips/stackframe.h @@ -102,17 +102,6 @@ .endm #endif -#ifdef CONFIG_PREEMPT - .macro bump_lock_count - lw t0, TI_PRE_COUNT($28) - addiu t0, t0, 1 - sw t0, TI_PRE_COUNT($28) - .endm -#else - .macro bump_lock_count - .endm -#endif - .macro SAVE_SOME .set push .set reorder @@ -149,7 +138,6 @@ LONG_S $31, PT_R31(sp) ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK - bump_lock_count .set pop .endm diff --git a/include/asm-mips/topology.h b/include/asm-mips/topology.h index 7b18240f0586..0440fb9f2180 100644 --- a/include/asm-mips/topology.h +++ b/include/asm-mips/topology.h @@ -1,15 +1 @@ -#ifndef __ASM_TOPOLOGY_H -#define __ASM_TOPOLOGY_H - -#include <linux/config.h> - -#ifdef CONFIG_SGI_IP27 - -#include <asm/mmzone.h> - -#define cpu_to_node(cpu) (cputocnode(cpu)) -#endif - -#include <asm-generic/topology.h> - -#endif /* __ASM_TOPOLOGY_H */ +#include <topology.h> diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index 2d259ea20d1f..e143e4ec6272 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h @@ -581,6 +581,23 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); #define __copy_in_user(to, from, n) __copy_from_user(to, from, n) +#define copy_in_user(to,from,n) \ +({ \ + void *__cu_to; \ + const void *__cu_from; \ + long __cu_len; \ + \ + might_sleep(); \ + __cu_to = (to); \ + __cu_from = (from); \ + __cu_len = (n); \ + if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) && \ + access_ok(VERIFY_WRITE, __cu_to, __cu_len))) \ + __cu_len = __invoke_copy_from_user(__cu_to, __cu_from, \ + __cu_len); \ + __cu_len; \ +}) + /* * __clear_user: - Zero a block of memory in user space, with less checking. * @to: Destination address, in user space. diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h index df930271836c..8fe42c70e98a 100644 --- a/include/asm-mips/unistd.h +++ b/include/asm-mips/unistd.h @@ -917,7 +917,7 @@ type name(atype a, btype b, ctype c, dtype d) \ return -1; \ } -#if (_MIPS_SIM == _MIPS_SIM_ABIN32) +#if (_MIPS_SIM == _MIPS_SIM_ABI32) /* * Using those means your brain needs more than an oil change ;-) @@ -985,9 +985,9 @@ type name(atype a, btype b, ctype c, dtype d, etype e, ftype f) \ return -1; \ } -#endif /* (_MIPS_SIM == _MIPS_SIM_ABIN32) */ +#endif /* (_MIPS_SIM == _MIPS_SIM_ABI32) */ -#if (_MIPS_SIM == _MIPS_SIM_NABIN32) || (_MIPS_SIM == _MIPS_SIM_ABI64) +#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) #define _syscall5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ type name (atype a,btype b,ctype c,dtype d,etype e) \ @@ -1043,13 +1043,13 @@ type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \ return -1; \ } -#endif /* (_MIPS_SIM == _MIPS_SIM_NABIN32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */ +#endif /* (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64) */ #ifdef __KERNEL_SYSCALLS__ -#include <linux/linkage.h> #include <linux/compiler.h> #include <linux/types.h> +#include <linux/linkage.h> #include <asm/ptrace.h> #include <asm/sim.h> diff --git a/include/asm-mips/vr41xx/e55.h b/include/asm-mips/vr41xx/e55.h index 754b74aa07a9..ea37b56fc66d 100644 --- a/include/asm-mips/vr41xx/e55.h +++ b/include/asm-mips/vr41xx/e55.h @@ -1,17 +1,21 @@ /* - * FILE NAME - * include/asm-mips/vr41xx/e55.h + * e55.h, Include file for CASIO CASSIOPEIA E-10/15/55/65. * - * BRIEF MODULE DESCRIPTION - * Include file for CASIO CASSIOPEIA E-10/15/55/65. + * Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> * - * Copyright 2002 Yoichi Yuasa - * yuasa@hh.iij4u.or.jp + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __CASIO_E55_H #define __CASIO_E55_H @@ -25,13 +29,15 @@ #define VR41XX_ISA_MEM_BASE 0x10000000 #define VR41XX_ISA_MEM_SIZE 0x04000000 -#define VR41XX_ISA_IO_BASE 0x14000000 -#define VR41XX_ISA_IO_SIZE 0x04000000 +/* VR41XX_ISA_IO_BASE includes offset from real base. */ +#define VR41XX_ISA_IO_BASE 0x1400c000 +#define VR41XX_ISA_IO_SIZE 0x03ff4000 + +#define ISA_BUS_IO_BASE 0 +#define ISA_BUS_IO_SIZE VR41XX_ISA_IO_SIZE #define IO_PORT_BASE KSEG1ADDR(VR41XX_ISA_IO_BASE) -#define IO_PORT_RESOURCE_START 0 -#define IO_PORT_RESOURCE_END VR41XX_ISA_IO_SIZE -#define IO_MEM_RESOURCE_START VR41XX_ISA_MEM_BASE -#define IO_MEM_RESOURCE_END (VR41XX_ISA_MEM_BASE + VR41XX_ISA_MEM_SIZE) +#define IO_PORT_RESOURCE_START ISA_BUS_IO_BASE +#define IO_PORT_RESOURCE_END (ISA_BUS_IO_BASE + ISA_BUS_IO_SIZE - 1) #endif /* __CASIO_E55_H */ diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h index f4ab4b029a9c..8d2e1b6dfe56 100644 --- a/include/asm-mips/vr41xx/vr41xx.h +++ b/include/asm-mips/vr41xx/vr41xx.h @@ -7,7 +7,7 @@ * Copyright (C) 2001, 2002 Paul Mundt * Copyright (C) 2002 MontaVista Software, Inc. * Copyright (C) 2002 TimeSys Corp. - * Copyright (C) 2003 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> + * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -43,20 +43,21 @@ #define PRID_VR4133 0x00000c84 /* + * Memory resource + */ +#define IO_MEM_RESOURCE_START 0UL +#define IO_MEM_RESOURCE_END 0x1fffffffUL + +/* * Bus Control Uint */ -extern void vr41xx_bcu_init(void); extern unsigned long vr41xx_get_vtclock_frequency(void); extern unsigned long vr41xx_get_tclock_frequency(void); /* * Clock Mask Unit */ -extern void vr41xx_cmu_init(void); -extern void vr41xx_clock_supply(unsigned int clock); -extern void vr41xx_clock_mask(unsigned int clock); - -enum { +typedef enum { PIU_CLOCK, SIU_CLOCK, AIU_CLOCK, @@ -70,7 +71,10 @@ enum { CEU_CLOCK, ETHER0_CLOCK, ETHER1_CLOCK -}; +} vr41xx_clock_t; + +extern void vr41xx_supply_clock(vr41xx_clock_t clock); +extern void vr41xx_mask_clock(vr41xx_clock_t clock); /* * Interrupt Control Unit @@ -129,14 +133,12 @@ enum { #define GIU_IRQ_LAST GIU_IRQ(31) #define GIU_IRQ_TO_PIN(x) ((x) - GIU_IRQ_BASE) /* Pin 0-31 */ -extern void (*board_irq_init)(void); extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)); /* * Power Management Unit */ -extern void vr41xx_pmu_init(void); /* * RTC @@ -226,10 +228,4 @@ struct vr41xx_pci_address_map { extern void vr41xx_pciu_init(struct vr41xx_pci_address_map *map); -/* - * MISC - */ -extern void vr41xx_time_init(void); -extern void vr41xx_timer_setup(struct irqaction *irq); - #endif /* __NEC_VR41XX_H */ diff --git a/include/asm-mips/vr41xx/workpad.h b/include/asm-mips/vr41xx/workpad.h index c7d27300370d..dfe01b43fb79 100644 --- a/include/asm-mips/vr41xx/workpad.h +++ b/include/asm-mips/vr41xx/workpad.h @@ -1,17 +1,21 @@ /* - * FILE NAME - * include/asm-mips/vr41xx/workpad.h + * workpad.h, Include file for IBM WorkPad z50. * - * BRIEF MODULE DESCRIPTION - * Include file for IBM WorkPad z50. + * Copyright (C) 2002-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> * - * Copyright 2002 Yoichi Yuasa - * yuasa@hh.iij4u.or.jp + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef __IBM_WORKPAD_H #define __IBM_WORKPAD_H @@ -29,10 +33,11 @@ #define VR41XX_ISA_IO_BASE 0x15000000 #define VR41XX_ISA_IO_SIZE 0x03000000 +#define ISA_BUS_IO_BASE 0 +#define ISA_BUS_IO_SIZE VR41XX_ISA_IO_SIZE + #define IO_PORT_BASE KSEG1ADDR(VR41XX_ISA_IO_BASE) -#define IO_PORT_RESOURCE_START 0 -#define IO_PORT_RESOURCE_END VR41XX_ISA_IO_SIZE -#define IO_MEM_RESOURCE_START VR41XX_ISA_MEM_BASE -#define IO_MEM_RESOURCE_END (VR41XX_ISA_MEM_BASE + VR41XX_ISA_MEM_SIZE) +#define IO_PORT_RESOURCE_START ISA_BUS_IO_BASE +#define IO_PORT_RESOURCE_END (ISA_BUS_IO_BASE + ISA_BUS_IO_SIZE - 1) #endif /* __IBM_WORKPAD_H */ diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 36f4ffc8bad8..a6f5c06c70e3 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -169,6 +169,14 @@ #endif /* + * On the RM9000 there is a problem which makes the CreateDirtyExclusive + * cache operation unusable on SMP systems. + */ +#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) +#define RM9000_CDEX_SMP_WAR 1 +#endif + +/* * Workarounds default to off */ #ifndef R4600_V1_INDEX_ICACHEOP_WAR @@ -198,5 +206,8 @@ #ifndef TX49XX_ICACHE_INDEX_INV_WAR #define TX49XX_ICACHE_INDEX_INV_WAR 0 #endif +#ifndef RM9000_CDEX_SMP_WAR +#define RM9000_CDEX_SMP_WAR 0 +#endif #endif /* _ASM_WAR_H */ |