diff options
| author | Linus Torvalds <torvalds@penguin.transmeta.com> | 2002-03-10 22:00:28 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@penguin.transmeta.com> | 2002-03-10 22:00:28 -0800 |
| commit | 71dbc87d1f6fdc795f869d8f77226b1a8b67ac8a (patch) | |
| tree | 7f3bd966f3f89a1c6d859df5cca0512e64fb643a /include | |
| parent | d82d83bbc7e3daaf6456487901a3597139b46731 (diff) | |
| parent | 5dca0cff0762ccbeafc56d4de1c99879b23eee15 (diff) | |
Merge bk://lia64.bkbits.net/to-linus-2.5
into penguin.transmeta.com:/home/penguin/torvalds/repositories/kernel/linux
Diffstat (limited to 'include')
167 files changed, 68760 insertions, 4651 deletions
diff --git a/include/asm-ia64/a.out.h b/include/asm-ia64/a.out.h index 25de011bc7f4..79fa7cf39ffe 100644 --- a/include/asm-ia64/a.out.h +++ b/include/asm-ia64/a.out.h @@ -7,8 +7,8 @@ * probably would be better to clean up binfmt_elf.c so it does not * necessarily depend on there being a.out support. * - * Copyright (C) 1998-2000 Hewlett-Packard Co - * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com> + * Copyright (C) 1998-2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> */ #include <linux/types.h> @@ -31,7 +31,7 @@ struct exec { #ifdef __KERNEL__ # include <asm/page.h> -# define STACK_TOP (0x8000000000000000UL + (1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE) +# define STACK_TOP (0x6000000000000000UL + (1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE) # define IA64_RBS_BOT (STACK_TOP - 0x80000000L + PAGE_SIZE) /* bottom of reg. backing store */ #endif diff --git a/include/asm-ia64/acpi-ext.h b/include/asm-ia64/acpi-ext.h index 70f4073c3eb9..a5e1a2c5fd41 100644 --- a/include/asm-ia64/acpi-ext.h +++ b/include/asm-ia64/acpi-ext.h @@ -13,7 +13,9 @@ * ACPI 2.0 specification */ +#include <linux/config.h> #include <linux/types.h> +#include <linux/mm.h> #pragma pack(1) #define ACPI_RSDP_SIG "RSD PTR " /* Trailing space required */ @@ -24,7 +26,7 @@ typedef struct { char oem_id[6]; u8 revision; u32 rsdt; - u32 lenth; + u32 length; struct acpi_xsdt *xsdt; u8 ext_checksum; u8 reserved[3]; @@ -96,7 +98,7 @@ typedef struct { struct acpi_rsdt *rsdt; } acpi_rsdp_t; -typedef struct { +typedef struct acpi_rsdt { acpi_desc_table_hdr_t header; u8 reserved[4]; unsigned long entry_ptrs[1]; /* Not really . . . */ @@ -151,15 +153,15 @@ typedef struct { #define MADT_PCAT_COMPAT (1<<0) /* acpi 2.0 MADT structure types */ -#define ACPI20_ENTRY_LOCAL_APIC 0 -#define ACPI20_ENTRY_IO_APIC 1 -#define ACPI20_ENTRY_INT_SRC_OVERRIDE 2 -#define ACPI20_ENTRY_NMI_SOURCE 3 -#define ACPI20_ENTRY_LOCAL_APIC_NMI 4 -#define ACPI20_ENTRY_LOCAL_APIC_ADDR_OVERRIDE 5 -#define ACPI20_ENTRY_IO_SAPIC 6 -#define ACPI20_ENTRY_LOCAL_SAPIC 7 -#define ACPI20_ENTRY_PLATFORM_INT_SOURCE 8 +#define ACPI20_ENTRY_LOCAL_APIC 0 +#define ACPI20_ENTRY_IO_APIC 1 +#define ACPI20_ENTRY_INT_SRC_OVERRIDE 2 +#define ACPI20_ENTRY_NMI_SOURCE 3 +#define ACPI20_ENTRY_LOCAL_APIC_NMI 4 +#define ACPI20_ENTRY_LOCAL_APIC_ADDR_OVERRIDE 5 +#define ACPI20_ENTRY_IO_SAPIC 6 +#define ACPI20_ENTRY_LOCAL_SAPIC 7 +#define ACPI20_ENTRY_PLATFORM_INT_SOURCE 8 typedef struct acpi20_entry_lsapic { u8 type; @@ -190,16 +192,132 @@ typedef struct { } acpi20_entry_platform_src_t; /* constants for interrupt routing API for device drivers */ -#define ACPI20_ENTRY_PIS_PMI 1 -#define ACPI20_ENTRY_PIS_INIT 2 -#define ACPI20_ENTRY_PIS_CPEI 3 -#define ACPI_MAX_PLATFORM_IRQS 4 +#define ACPI20_ENTRY_PIS_PMI 1 +#define ACPI20_ENTRY_PIS_INIT 2 +#define ACPI20_ENTRY_PIS_CPEI 3 +#define ACPI_MAX_PLATFORM_IRQS 4 + +#define ACPI_SPCRT_SIG "SPCR" +#define ACPI_SPCRT_SIG_LEN 4 + +#define ACPI_DBGPT_SIG "DBGP" +#define ACPI_DBGPT_SIG_LEN 4 extern int acpi20_parse(acpi20_rsdp_t *); +extern int acpi20_early_parse(acpi20_rsdp_t *); extern int acpi_parse(acpi_rsdp_t *); extern const char *acpi_get_sysname (void); extern int acpi_request_vector(u32 int_type); - extern void (*acpi_idle) (void); /* power-management idle function, if any */ +#ifdef CONFIG_NUMA +extern cnodeid_t paddr_to_nid(unsigned long paddr); +#endif + +/* + * ACPI 2.0 SRAT Table + * http://www.microsoft.com/HWDEV/design/SRAT.htm + */ + +typedef struct acpi_srat { + acpi_desc_table_hdr_t header; + u32 table_revision; + u64 reserved; +} acpi_srat_t; + +typedef struct srat_cpu_affinity { + u8 type; + u8 length; + u8 proximity_domain; + u8 apic_id; + u32 flags; + u8 local_sapic_eid; + u8 reserved[7]; +} srat_cpu_affinity_t; + +typedef struct srat_memory_affinity { + u8 type; + u8 length; + u8 proximity_domain; + u8 reserved[5]; + u32 base_addr_lo; + u32 base_addr_hi; + u32 length_lo; + u32 length_hi; + u32 memory_type; + u32 flags; + u64 reserved2; +} srat_memory_affinity_t; + +/* ACPI 2.0 SRAT structure */ +#define ACPI_SRAT_SIG "SRAT" +#define ACPI_SRAT_SIG_LEN 4 +#define ACPI_SRAT_REVISION 1 + +#define SRAT_CPU_STRUCTURE 0 +#define SRAT_MEMORY_STRUCTURE 1 + +/* Only 1 flag for cpu affinity structure! */ +#define SRAT_CPU_FLAGS_ENABLED 0x00000001 + +#define SRAT_MEMORY_FLAGS_ENABLED 0x00000001 +#define SRAT_MEMORY_FLAGS_HOTREMOVABLE 0x00000002 + +/* ACPI 2.0 address range types */ +#define ACPI_ADDRESS_RANGE_MEMORY 1 +#define ACPI_ADDRESS_RANGE_RESERVED 2 +#define ACPI_ADDRESS_RANGE_ACPI 3 +#define ACPI_ADDRESS_RANGE_NVS 4 + +#define NODE_ARRAY_INDEX(x) ((x) / 8) /* 8 bits/char */ +#define NODE_ARRAY_OFFSET(x) ((x) % 8) /* 8 bits/char */ +#define MAX_PXM_DOMAINS (256) + +#ifdef CONFIG_DISCONTIGMEM +/* + * List of node memory chunks. Filled when parsing SRAT table to + * obtain information about memory nodes. +*/ + +struct node_memory_chunk_s { + unsigned long start_paddr; + unsigned long size; + int pxm; // proximity domain of node + int nid; // which cnode contains this chunk? + int bank; // which mem bank on this node +}; + +extern struct node_memory_chunk_s node_memory_chunk[PLAT_MAXCLUMPS]; // temporary? + +struct node_cpuid_s { + u16 phys_id; /* id << 8 | eid */ + int pxm; // proximity domain of cpu + int nid; +}; +extern struct node_cpuid_s node_cpuid[NR_CPUS]; + +extern int pxm_to_nid_map[MAX_PXM_DOMAINS]; /* _PXM to logical node ID map */ +extern int nid_to_pxm_map[PLAT_MAX_COMPACT_NODES]; /* logical node ID to _PXM map */ +extern int numnodes; /* total number of nodes in system */ +extern int num_memory_chunks; /* total number of memory chunks */ + +/* + * ACPI 2.0 SLIT Table + * http://devresource.hp.com/devresource/Docs/TechPapers/IA64/slit.pdf + */ + +typedef struct acpi_slit { + acpi_desc_table_hdr_t header; + u64 localities; + u8 entries[1]; /* dummy, real size = locality^2 */ +} acpi_slit_t; + +extern u8 acpi20_slit[PLAT_MAX_COMPACT_NODES * PLAT_MAX_COMPACT_NODES]; + +#define ACPI_SLIT_SIG "SLIT" +#define ACPI_SLIT_SIG_LEN 4 +#define ACPI_SLIT_REVISION 1 +#define ACPI_SLIT_LOCAL 10 +#endif /* CONFIG_DISCONTIGMEM */ + #pragma pack() #endif /* _ASM_IA64_ACPI_EXT_H */ diff --git a/include/asm-ia64/asmmacro.h b/include/asm-ia64/asmmacro.h index 45a238dde1a2..010c6fc11a91 100644 --- a/include/asm-ia64/asmmacro.h +++ b/include/asm-ia64/asmmacro.h @@ -3,7 +3,7 @@ /* * Copyright (C) 2000-2001 Hewlett-Packard Co - * Copyright (C) 2000-2001 David Mosberger-Tang <davidm@hpl.hp.com> + * David Mosberger-Tang <davidm@hpl.hp.com> */ #define ENTRY(name) \ diff --git a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h index 6499193f5d82..67e2c61b0f43 100644 --- a/include/asm-ia64/bitops.h +++ b/include/asm-ia64/bitops.h @@ -2,8 +2,11 @@ #define _ASM_IA64_BITOPS_H /* - * Copyright (C) 1998-2001 Hewlett-Packard Co - * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com> + * Copyright (C) 1998-2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> + * + * 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64 O(1) + * scheduler patch */ #include <asm/system.h> @@ -57,10 +60,10 @@ __set_bit (int nr, volatile void *addr) } /* - * clear_bit() doesn't provide any barrier for the compiler. + * clear_bit() has "acquire" semantics. */ #define smp_mb__before_clear_bit() smp_mb() -#define smp_mb__after_clear_bit() smp_mb() +#define smp_mb__after_clear_bit() do { /* skip */; } while (0) /** * clear_bit - Clears a bit in memory @@ -89,6 +92,17 @@ clear_bit (int nr, volatile void *addr) } /** + * __clear_bit - Clears a bit in memory (non-atomic version) + */ +static __inline__ void +__clear_bit (int nr, volatile void *addr) +{ + volatile __u32 *p = (__u32 *) addr + (nr >> 5);; + __u32 m = 1 << (nr & 31); + *p &= ~m; +} + +/** * change_bit - Toggle a bit in memory * @nr: Bit to clear * @addr: Address to start counting from @@ -264,12 +278,11 @@ test_bit (int nr, volatile void *addr) } /** - * ffz - find the first zero bit in a memory region - * @x: The address to start the search at + * ffz - find the first zero bit in a long word + * @x: The long word to find the bit in * - * Returns the bit-number (0..63) of the first (least significant) zero bit, not - * the number of the byte containing a bit. Undefined if no zero exists, so - * code should check against ~0UL first... + * Returns the bit-number (0..63) of the first (least significant) zero bit. Undefined if + * no zero exists, so code should check against ~0UL first... */ static inline unsigned long ffz (unsigned long x) @@ -280,6 +293,21 @@ ffz (unsigned long x) return result; } +/** + * __ffs - find first bit in word. + * @x: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static __inline__ unsigned long +__ffs (unsigned long x) +{ + unsigned long result; + + __asm__ ("popcnt %0=%1" : "=r" (result) : "r" ((x - 1) & ~x)); + return result; +} + #ifdef __KERNEL__ /* @@ -357,6 +385,8 @@ find_next_zero_bit (void *addr, unsigned long size, unsigned long offset) tmp = *p; found_first: tmp |= ~0UL << size; + if (tmp == ~0UL) /* any bits zero? */ + return result + size; /* nope */ found_middle: return result + ffz(tmp); } @@ -366,8 +396,53 @@ found_middle: */ #define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0) +/* + * Find next bit in a bitmap reasonably efficiently.. + */ +static inline int +find_next_bit (void *addr, unsigned long size, unsigned long offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 6); + unsigned long result = offset & ~63UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 63UL; + if (offset) { + tmp = *(p++); + tmp &= ~0UL << offset; + if (size < 64) + goto found_first; + if (tmp) + goto found_middle; + size -= 64; + result += 64; + } + while (size & ~63UL) { + if ((tmp = *(p++))) + goto found_middle; + result += 64; + size -= 64; + } + if (!size) + return result; + tmp = *p; + found_first: + tmp &= ~0UL >> (64-size); + if (tmp == 0UL) /* Are any bits set? */ + return result + size; /* Nope. */ + found_middle: + return result + __ffs(tmp); +} + +#define find_first_bit(addr, size) find_next_bit((addr), (size), 0) + #ifdef __KERNEL__ +#define __clear_bit(nr, addr) clear_bit(nr, addr) + #define ext2_set_bit test_and_set_bit #define ext2_clear_bit test_and_clear_bit #define ext2_test_bit test_bit @@ -381,6 +456,16 @@ found_middle: #define minix_test_bit(nr,addr) test_bit(nr,addr) #define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) +static inline int +sched_find_first_bit (unsigned long *b) +{ + if (unlikely(b[0])) + return __ffs(b[0]); + if (unlikely(b[1])) + return 64 + __ffs(b[1]); + return __ffs(b[2]) + 128; +} + #endif /* __KERNEL__ */ #endif /* _ASM_IA64_BITOPS_H */ diff --git a/include/asm-ia64/checksum.h b/include/asm-ia64/checksum.h index 21325d8d0cb3..1e88743535cf 100644 --- a/include/asm-ia64/checksum.h +++ b/include/asm-ia64/checksum.h @@ -89,11 +89,4 @@ csum_fold (unsigned int sum) return ~sum; } -#define _HAVE_ARCH_IPV6_CSUM -extern unsigned short int csum_ipv6_magic (struct in6_addr *saddr, - struct in6_addr *daddr, - __u16 len, - unsigned short proto, - unsigned int sum); - #endif /* _ASM_IA64_CHECKSUM_H */ diff --git a/include/asm-ia64/current.h b/include/asm-ia64/current.h index 3d4f232f3473..73a5edf825b8 100644 --- a/include/asm-ia64/current.h +++ b/include/asm-ia64/current.h @@ -3,7 +3,7 @@ /* * Copyright (C) 1998-2000 Hewlett-Packard Co - * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com> + * David Mosberger-Tang <davidm@hpl.hp.com> */ /* In kernel mode, thread pointer (r13) is used to point to the diff --git a/include/asm-ia64/elf.h b/include/asm-ia64/elf.h index 149437e8c2e5..219ff6879f15 100644 --- a/include/asm-ia64/elf.h +++ b/include/asm-ia64/elf.h @@ -4,8 +4,8 @@ /* * ELF archtecture specific definitions. * - * Copyright (C) 1998, 1999 Hewlett-Packard Co - * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com> + * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> */ #include <asm/fpu.h> @@ -25,7 +25,10 @@ #define USE_ELF_CORE_DUMP -/* always align to 64KB to allow for future page sizes of up to 64KB: */ +/* Least-significant four bits of ELF header's e_flags are OS-specific. The bits are + interpreted as follows by Linux: */ +#define EF_IA_64_LINUX_EXECUTABLE_STACK 0x1 /* is stack (& heap) executable by default? */ + #define ELF_EXEC_PAGESIZE PAGE_SIZE /* @@ -82,7 +85,9 @@ extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst); #define ELF_PLATFORM 0 #ifdef __KERNEL__ -#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) +struct elf64_hdr; +extern void ia64_set_personality (struct elf64_hdr *elf_ex, int ibcs2_interpreter); +#define SET_PERSONALITY(ex, ibcs2) ia64_set_personality(&(ex), ibcs2) #endif #endif /* _ASM_IA64_ELF_H */ diff --git a/include/asm-ia64/hardirq.h b/include/asm-ia64/hardirq.h index 0328bd3f0d06..417248256272 100644 --- a/include/asm-ia64/hardirq.h +++ b/include/asm-ia64/hardirq.h @@ -25,8 +25,8 @@ #define local_softirq_pending() (local_cpu_data->softirq_pending) #define local_ksoftirqd_task() (local_cpu_data->ksoftirqd) -#define local_irq_count() (local_cpu_data->irq_stat.f.irq_count) -#define local_bh_count() (local_cpu_data->irq_stat.f.bh_count) +#define really_local_irq_count() (local_cpu_data->irq_stat.f.irq_count) /* XXX fix me */ +#define really_local_bh_count() (local_cpu_data->irq_stat.f.bh_count) /* XXX fix me */ #define local_syscall_count() /* unused on IA-64 */ #define local_nmi_count() 0 @@ -38,11 +38,11 @@ #define in_irq() (local_cpu_data->irq_stat.f.irq_count != 0) #ifndef CONFIG_SMP -# define local_hardirq_trylock() (local_irq_count() == 0) +# define local_hardirq_trylock() (really_local_irq_count() == 0) # define local_hardirq_endlock() do { } while (0) -# define local_irq_enter(irq) (local_irq_count()++) -# define local_irq_exit(irq) (local_irq_count()--) +# define local_irq_enter(irq) (really_local_irq_count()++) +# define local_irq_exit(irq) (really_local_irq_count()--) # define synchronize_irq() barrier() #else @@ -70,6 +70,7 @@ release_irqlock (int cpu) /* if we didn't own the irq lock, just ignore.. */ if (global_irq_holder == cpu) { global_irq_holder = NO_PROC_ID; + smp_mb__before_clear_bit(); /* need barrier before releasing lock... */ clear_bit(0,&global_irq_lock); } } @@ -77,7 +78,7 @@ release_irqlock (int cpu) static inline void local_irq_enter (int irq) { - local_irq_count()++; + really_local_irq_count()++; while (test_bit(0,&global_irq_lock)) { /* nothing */; @@ -87,13 +88,13 @@ local_irq_enter (int irq) static inline void local_irq_exit (int irq) { - local_irq_count()--; + really_local_irq_count()--; } static inline int local_hardirq_trylock (void) { - return !local_irq_count() && !test_bit(0,&global_irq_lock); + return !really_local_irq_count() && !test_bit(0,&global_irq_lock); } #define local_hardirq_endlock() do { } while (0) diff --git a/include/asm-ia64/ia32.h b/include/asm-ia64/ia32.h index c088ac4865e7..f1fc560a46ea 100644 --- a/include/asm-ia64/ia32.h +++ b/include/asm-ia64/ia32.h @@ -5,7 +5,7 @@ #ifdef CONFIG_IA32_SUPPORT -#include <linux/param.h> +#include <linux/binfmts.h> /* * 32 bit structures for IA32 support. @@ -475,6 +475,8 @@ struct ia32_modify_ldt_ldt_s { unsigned int useable:1; }; +struct linux_binprm; + extern void ia32_gdt_init (void); extern int ia32_setup_frame1 (int sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *set, struct pt_regs *regs); diff --git a/include/asm-ia64/io.h b/include/asm-ia64/io.h index 9e01f4813285..2c19405ecda0 100644 --- a/include/asm-ia64/io.h +++ b/include/asm-ia64/io.h @@ -69,6 +69,22 @@ phys_to_virt (unsigned long address) */ #define __ia64_mf_a() __asm__ __volatile__ ("mf.a" ::: "memory") +/** + * __ia64_mmiob - I/O space memory barrier + * + * Acts as a memory mapped I/O barrier for platforms that queue writes to + * I/O space. This ensures that subsequent writes to I/O space arrive after + * all previous writes. For most ia64 platforms, this is a simple + * 'mf.a' instruction, so the address is ignored. For other platforms, + * the address may be required to ensure proper ordering of writes to I/O space + * since a 'dummy' read might be necessary to barrier the write operation. + */ +static inline void +__ia64_mmiob (void) +{ + __ia64_mf_a(); +} + static inline const unsigned long __ia64_get_io_port_base (void) { @@ -271,6 +287,7 @@ __outsl (unsigned long port, void *src, unsigned long count) #define __outb platform_outb #define __outw platform_outw #define __outl platform_outl +#define __mmiob platform_mmiob #define inb __inb #define inw __inw @@ -284,6 +301,7 @@ __outsl (unsigned long port, void *src, unsigned long count) #define outsb __outsb #define outsw __outsw #define outsl __outsl +#define mmiob __mmiob /* * The address passed to these functions are ioremap()ped already. @@ -408,5 +426,11 @@ extern void __ia64_memset_c_io (unsigned long, unsigned long, long); #define memset_io(addr,c,len) \ __ia64_memset_c_io((unsigned long)(addr),0x0101010101010101UL*(u8)(c),(len)) + +#define dma_cache_inv(_start,_size) do { } while (0) +#define dma_cache_wback(_start,_size) do { } while (0) +#define dma_cache_wback_inv(_start,_size) do { } while (0) + # endif /* __KERNEL__ */ + #endif /* _ASM_IA64_IO_H */ diff --git a/include/asm-ia64/irq.h b/include/asm-ia64/irq.h index 61bb7aedb75e..4c52ffb49fa2 100644 --- a/include/asm-ia64/irq.h +++ b/include/asm-ia64/irq.h @@ -2,9 +2,9 @@ #define _ASM_IA64_IRQ_H /* - * Copyright (C) 1999-2000 Hewlett-Packard Co - * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com> - * Copyright (C) 1998 Stephane Eranian <eranian@hpl.hp.com> + * Copyright (C) 1999-2000, 2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> + * Stephane Eranian <eranian@hpl.hp.com> * * 11/24/98 S.Eranian updated TIMER_IRQ and irq_cannonicalize * 01/20/99 S.Eranian added keyboard interrupt @@ -27,5 +27,6 @@ irq_cannonicalize (int irq) extern void disable_irq (unsigned int); extern void disable_irq_nosync (unsigned int); extern void enable_irq (unsigned int); +extern void set_irq_affinity_info (int irq, int dest, int redir); #endif /* _ASM_IA64_IRQ_H */ diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h index 2132a2a45dd8..26f3ba521bcd 100644 --- a/include/asm-ia64/machvec.h +++ b/include/asm-ia64/machvec.h @@ -20,6 +20,7 @@ struct scatterlist; struct irq_desc; typedef void ia64_mv_setup_t (char **); +typedef void ia64_mv_cpu_init_t(void); typedef void ia64_mv_irq_init_t (void); typedef void ia64_mv_pci_fixup_t (int); typedef unsigned long ia64_mv_map_nr_t (unsigned long); @@ -59,6 +60,7 @@ typedef unsigned int ia64_mv_inl_t (unsigned long); typedef void ia64_mv_outb_t (unsigned char, unsigned long); typedef void ia64_mv_outw_t (unsigned short, unsigned long); typedef void ia64_mv_outl_t (unsigned int, unsigned long); +typedef void ia64_mv_mmiob_t (void); extern void machvec_noop (void); @@ -77,6 +79,7 @@ extern void machvec_noop (void); # else # define platform_name ia64_mv.name # define platform_setup ia64_mv.setup +# define platform_cpu_init ia64_mv.cpu_init # define platform_irq_init ia64_mv.irq_init # define platform_map_nr ia64_mv.map_nr # define platform_mca_init ia64_mv.mca_init @@ -105,11 +108,13 @@ extern void machvec_noop (void); # define platform_outb ia64_mv.outb # define platform_outw ia64_mv.outw # define platform_outl ia64_mv.outl +# define platofrm_mmiob ia64_mv.mmiob # endif struct ia64_machine_vector { const char *name; ia64_mv_setup_t *setup; + ia64_mv_cpu_init_t *cpu_init; ia64_mv_irq_init_t *irq_init; ia64_mv_pci_fixup_t *pci_fixup; ia64_mv_map_nr_t *map_nr; @@ -137,6 +142,7 @@ struct ia64_machine_vector { ia64_mv_outb_t *outb; ia64_mv_outw_t *outw; ia64_mv_outl_t *outl; + ia64_mv_mmiob_t *mmiob; }; #define MACHVEC_INIT(name) \ @@ -170,7 +176,8 @@ struct ia64_machine_vector { platform_inl, \ platform_outb, \ platform_outw, \ - platform_outl \ + platform_outl, \ + platform_mmiob \ } extern struct ia64_machine_vector ia64_mv; @@ -201,6 +208,9 @@ extern ia64_mv_pci_dma_address swiotlb_dma_address; #ifndef platform_setup # define platform_setup ((ia64_mv_setup_t *) machvec_noop) #endif +#ifndef platform_cpu_init +# define platform_cpu_init ((ia64_mv_cpu_init_t *) machvec_noop) +#endif #ifndef platform_irq_init # define platform_irq_init ((ia64_mv_irq_init_t *) machvec_noop) #endif @@ -282,5 +292,8 @@ extern ia64_mv_pci_dma_address swiotlb_dma_address; #ifndef platform_outl # define platform_outl __ia64_outl #endif +#ifndef platform_mmiob +# define platform_mmiob __ia64_mmiob +#endif #endif /* _ASM_IA64_MACHVEC_H */ diff --git a/include/asm-ia64/machvec_sn1.h b/include/asm-ia64/machvec_sn1.h index c110c56427da..b3cefbff0224 100644 --- a/include/asm-ia64/machvec_sn1.h +++ b/include/asm-ia64/machvec_sn1.h @@ -1,7 +1,40 @@ +/* + * Copyright (c) 2002 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: + * + * http://www.sgi.com + * + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/NoticeExplan + */ + #ifndef _ASM_IA64_MACHVEC_SN1_h #define _ASM_IA64_MACHVEC_SN1_h extern ia64_mv_setup_t sn1_setup; +extern ia64_mv_cpu_init_t sn_cpu_init; extern ia64_mv_irq_init_t sn1_irq_init; extern ia64_mv_map_nr_t sn1_map_nr; extern ia64_mv_send_ipi_t sn1_send_IPI; @@ -13,6 +46,7 @@ extern ia64_mv_inl_t sn1_inl; extern ia64_mv_outb_t sn1_outb; extern ia64_mv_outw_t sn1_outw; extern ia64_mv_outl_t sn1_outl; +extern ia64_mv_mmiob_t sn_mmiob; extern ia64_mv_pci_alloc_consistent sn1_pci_alloc_consistent; extern ia64_mv_pci_free_consistent sn1_pci_free_consistent; extern ia64_mv_pci_map_single sn1_pci_map_single; @@ -32,6 +66,7 @@ extern ia64_mv_pci_dma_address sn1_dma_address; */ #define platform_name "sn1" #define platform_setup sn1_setup +#define platform_cpu_init sn_cpu_init #define platform_irq_init sn1_irq_init #define platform_map_nr sn1_map_nr #define platform_send_ipi sn1_send_IPI @@ -43,6 +78,7 @@ extern ia64_mv_pci_dma_address sn1_dma_address; #define platform_outb sn1_outb #define platform_outw sn1_outw #define platform_outl sn1_outl +#define platform_mmiob sn_mmiob #define platform_pci_dma_init machvec_noop #define platform_pci_alloc_consistent sn1_pci_alloc_consistent #define platform_pci_free_consistent sn1_pci_free_consistent diff --git a/include/asm-ia64/machvec_sn2.h b/include/asm-ia64/machvec_sn2.h new file mode 100644 index 000000000000..d2e34731fc58 --- /dev/null +++ b/include/asm-ia64/machvec_sn2.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2002 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: + * + * http://www.sgi.com + * + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/NoticeExplan + */ + +#ifndef _ASM_IA64_MACHVEC_SN2_H +#define _ASM_IA64_MACHVEC_SN2_H + +extern ia64_mv_setup_t sn1_setup; +extern ia64_mv_cpu_init_t sn_cpu_init; +extern ia64_mv_irq_init_t sn1_irq_init; +extern ia64_mv_map_nr_t sn2_map_nr; +extern ia64_mv_send_ipi_t sn2_send_IPI; +extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge; +extern ia64_mv_irq_desc sn1_irq_desc; +extern ia64_mv_irq_to_vector sn1_irq_to_vector; +extern ia64_mv_local_vector_to_irq sn1_local_vector_to_irq; +extern ia64_mv_valid_irq sn1_valid_irq; +extern ia64_mv_pci_fixup_t sn1_pci_fixup; +#ifdef Colin /* We are using the same is Generic IA64 calls defined in io.h */ +extern ia64_mv_inb_t sn1_inb; +extern ia64_mv_inw_t sn1_inw; +extern ia64_mv_inl_t sn1_inl; +extern ia64_mv_outb_t sn1_outb; +extern ia64_mv_outw_t sn1_outw; +extern ia64_mv_outl_t sn1_outl; +#endif +extern ia64_mv_pci_alloc_consistent sn1_pci_alloc_consistent; +extern ia64_mv_pci_free_consistent sn1_pci_free_consistent; +extern ia64_mv_pci_map_single sn1_pci_map_single; +extern ia64_mv_pci_unmap_single sn1_pci_unmap_single; +extern ia64_mv_pci_map_sg sn1_pci_map_sg; +extern ia64_mv_pci_unmap_sg sn1_pci_unmap_sg; +extern ia64_mv_pci_dma_sync_single sn1_pci_dma_sync_single; +extern ia64_mv_pci_dma_sync_sg sn1_pci_dma_sync_sg; +extern ia64_mv_pci_dma_address sn1_dma_address; + +/* + * This stuff has dual use! + * + * For a generic kernel, the macros are used to initialize the + * platform's machvec structure. When compiling a non-generic kernel, + * the macros are used directly. + */ +#define platform_name "sn2" +#define platform_setup sn1_setup +#define platform_cpu_init sn_cpu_init +#define platform_irq_init sn1_irq_init +#define platform_map_nr sn2_map_nr +#define platform_send_ipi sn2_send_IPI +#define platform_global_tlb_purge sn2_global_tlb_purge +#define platform_pci_fixup sn1_pci_fixup +#ifdef Colin /* We are using the same is Generic IA64 calls defined in io.h */ +#define platform_inb sn1_inb +#define platform_inw sn1_inw +#define platform_inl sn1_inl +#define platform_outb sn1_outb +#define platform_outw sn1_outw +#define platform_outl sn1_outl +#endif +#define platform_irq_desc sn1_irq_desc +#define platform_irq_to_vector sn1_irq_to_vector +#define platform_local_vector_to_irq sn1_local_vector_to_irq +#define platform_valid_irq sn1_valid_irq +#define platform_pci_dma_init machvec_noop +#define platform_pci_alloc_consistent sn1_pci_alloc_consistent +#define platform_pci_free_consistent sn1_pci_free_consistent +#define platform_pci_map_single sn1_pci_map_single +#define platform_pci_unmap_single sn1_pci_unmap_single +#define platform_pci_map_sg sn1_pci_map_sg +#define platform_pci_unmap_sg sn1_pci_unmap_sg +#define platform_pci_dma_sync_single sn1_pci_dma_sync_single +#define platform_pci_dma_sync_sg sn1_pci_dma_sync_sg +#define platform_pci_dma_address sn1_dma_address + +#endif /* _ASM_IA64_MACHVEC_SN2_H */ diff --git a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h index 68fea8565acd..b3ccbc2cd59e 100644 --- a/include/asm-ia64/mca.h +++ b/include/asm-ia64/mca.h @@ -7,9 +7,6 @@ * Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com) */ -/* XXX use this temporary define for MP systems trying to INIT */ -#undef SAL_MPINIT_WORKAROUND - #ifndef _ASM_IA64_MCA_H #define _ASM_IA64_MCA_H @@ -101,12 +98,19 @@ enum { IA64_MCA_HALT = -3 /* System to be halted by SAL */ }; +enum { + IA64_MCA_SAME_CONTEXT = 0x0, /* SAL to return to same context */ + IA64_MCA_NEW_CONTEXT = -1 /* SAL to return to new context */ +}; + typedef struct ia64_mca_os_to_sal_state_s { u64 imots_os_status; /* OS status to SAL as to what happened * with the MCA handling. */ u64 imots_sal_gp; /* GP of the SAL - physical */ - u64 imots_new_min_state; /* Pointer to structure containing + u64 imots_context; /* 0 if return to same context + 1 if return to new context */ + u64 *imots_new_min_state; /* Pointer to structure containing * new values of registers in the min state * save area. */ @@ -127,13 +131,20 @@ extern void ia64_mca_rendez_int_handler(int,void *,struct pt_regs *); extern void ia64_mca_wakeup_int_handler(int,void *,struct pt_regs *); extern void ia64_mca_cmc_int_handler(int,void *,struct pt_regs *); extern void ia64_mca_cpe_int_handler(int,void *,struct pt_regs *); -extern void ia64_log_print(int,prfunc_t); +extern int ia64_log_print(int,prfunc_t); extern void ia64_mca_cmc_vector_setup(void); extern void ia64_mca_check_errors( void ); extern u64 ia64_log_get(int, prfunc_t); #define PLATFORM_CALL(fn, args) printk("Platform call TBD\n") +#define platform_mem_dev_err_print ia64_log_prt_oem_data +#define platform_pci_bus_err_print ia64_log_prt_oem_data +#define platform_pci_comp_err_print ia64_log_prt_oem_data +#define platform_plat_specific_err_print ia64_log_prt_oem_data +#define platform_host_ctlr_err_print ia64_log_prt_oem_data +#define platform_plat_bus_err_print ia64_log_prt_oem_data + #undef MCA_TEST #undef IA64_MCA_DEBUG_INFO diff --git a/include/asm-ia64/mca_asm.h b/include/asm-ia64/mca_asm.h index 2448d64c1fb7..4d41dae31a3e 100644 --- a/include/asm-ia64/mca_asm.h +++ b/include/asm-ia64/mca_asm.h @@ -6,6 +6,8 @@ * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com> * Copyright (C) 2000 Hewlett-Packard Co. * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com> + * Copyright (C) 2002 Intel Corp. + * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com> */ #ifndef _ASM_IA64_MCA_ASM_H #define _ASM_IA64_MCA_ASM_H @@ -24,7 +26,7 @@ * 1. Lop off bits 61 thru 63 in the virtual address */ #define INST_VA_TO_PA(addr) \ - dep addr = 0, addr, 61, 3; + dep addr = 0, addr, 61, 3 /* * This macro converts a data virtual address to a physical address * Right now for simulation purposes the virtual addresses are @@ -32,7 +34,7 @@ * 1. Lop off bits 61 thru 63 in the virtual address */ #define DATA_VA_TO_PA(addr) \ - dep addr = 0, addr, 61, 3; + dep addr = 0, addr, 61, 3 /* * This macro converts a data physical address to a virtual address * Right now for simulation purposes the virtual addresses are @@ -41,7 +43,7 @@ */ #define DATA_PA_TO_VA(addr,temp) \ mov temp = 0x7 ;; \ - dep addr = temp, addr, 61, 3;; + dep addr = temp, addr, 61, 3 /* * This macro jumps to the instruction at the given virtual address @@ -112,8 +114,8 @@ ;; \ mov cr.iip = temp2; \ mov cr.ifs = r0; \ - DATA_VA_TO_PA(sp) \ - DATA_VA_TO_PA(gp) \ + DATA_VA_TO_PA(sp); \ + DATA_VA_TO_PA(gp); \ ;; \ srlz.i; \ ;; \ @@ -130,8 +132,7 @@ * translations turned on. * 1. Get the old saved psr * - * 2. Clear the interrupt enable and interrupt state collection bits - * in the current psr. + * 2. Clear the interrupt state collection bit in the current psr. * * 3. Set the instruction translation bit back in the old psr * Note we have to do this since we are right now saving only the @@ -140,9 +141,11 @@ * * 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1. * - * 5. Set iip to the virtual address of the next instruction bundle. + * 5. Reset the current thread pointer (r13). * - * 6. Do an rfi to move ipsr to psr and iip to ip. + * 6. Set iip to the virtual address of the next instruction bundle. + * + * 7. Do an rfi to move ipsr to psr and iip to ip. */ #define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \ @@ -156,6 +159,10 @@ mov ar.rsc = 0; \ ;; \ srlz.d; \ + mov r13 = ar.k6; \ + ;; \ + DATA_PA_TO_VA(r13,temp1); \ + ;; \ mov temp2 = ar.bspstore; \ ;; \ DATA_PA_TO_VA(temp2,temp1); \ @@ -170,8 +177,6 @@ ;; \ mov temp2 = 1; \ ;; \ - dep temp1 = temp2, temp1, PSR_I, 1; \ - ;; \ dep temp1 = temp2, temp1, PSR_IC, 1; \ ;; \ dep temp1 = temp2, temp1, PSR_IT, 1; \ @@ -195,7 +200,7 @@ nop 1; \ nop 2; \ nop 1; \ - rfi; \ + rfi \ ;; /* diff --git a/include/asm-ia64/mman.h b/include/asm-ia64/mman.h index 7735da36cb27..58db5609867e 100644 --- a/include/asm-ia64/mman.h +++ b/include/asm-ia64/mman.h @@ -2,8 +2,8 @@ #define _ASM_IA64_MMAN_H /* - * Copyright (C) 1998-2000 Hewlett-Packard Co - * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com> + * Copyright (C) 1998-2000, 2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> */ #define PROT_READ 0x1 /* page can be read */ @@ -23,8 +23,6 @@ #define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ #define MAP_LOCKED 0x2000 /* pages are locked */ #define MAP_NORESERVE 0x4000 /* don't check for reservations */ -#define MAP_WRITECOMBINED 0x10000 /* write-combine the area */ -#define MAP_NONCACHED 0x20000 /* don't cache the memory */ #define MS_ASYNC 1 /* sync memory asynchronously */ #define MS_INVALIDATE 2 /* invalidate the caches */ diff --git a/include/asm-ia64/offsets.h b/include/asm-ia64/offsets.h index 076fe962ef56..0c456df266ec 100644 --- a/include/asm-ia64/offsets.h +++ b/include/asm-ia64/offsets.h @@ -7,8 +7,9 @@ * */ #define PT_PTRACED_BIT 0 -#define PT_TRACESYS_BIT 1 -#define IA64_TASK_SIZE 3408 /* 0xd50 */ +#define PT_SYSCALLTRACE_BIT 1 +#define IA64_TASK_SIZE 3936 /* 0xf60 */ +#define IA64_THREAD_INFO_SIZE 24 /* 0x18 */ #define IA64_PT_REGS_SIZE 400 /* 0x190 */ #define IA64_SWITCH_STACK_SIZE 560 /* 0x230 */ #define IA64_SIGINFO_SIZE 128 /* 0x80 */ @@ -16,15 +17,12 @@ #define SIGFRAME_SIZE 2816 /* 0xb00 */ #define UNW_FRAME_INFO_SIZE 448 /* 0x1c0 */ -#define IA64_TASK_PTRACE_OFFSET 48 /* 0x30 */ -#define IA64_TASK_SIGPENDING_OFFSET 16 /* 0x10 */ -#define IA64_TASK_NEED_RESCHED_OFFSET 40 /* 0x28 */ -#define IA64_TASK_PROCESSOR_OFFSET 100 /* 0x64 */ -#define IA64_TASK_THREAD_OFFSET 976 /* 0x3d0 */ -#define IA64_TASK_THREAD_KSP_OFFSET 976 /* 0x3d0 */ -#define IA64_TASK_PFM_MUST_BLOCK_OFFSET 1600 /* 0x640 */ -#define IA64_TASK_PID_OFFSET 220 /* 0xdc */ -#define IA64_TASK_MM_OFFSET 88 /* 0x58 */ +#define IA64_TASK_PTRACE_OFFSET 32 /* 0x20 */ +#define IA64_TASK_THREAD_OFFSET 1472 /* 0x5c0 */ +#define IA64_TASK_THREAD_KSP_OFFSET 1480 /* 0x5c8 */ +#define IA64_TASK_PFM_OVFL_BLOCK_RESET_OFFSET 2096 /* 0x830 */ +#define IA64_TASK_PID_OFFSET 212 /* 0xd4 */ +#define IA64_TASK_MM_OFFSET 136 /* 0x88 */ #define IA64_PT_REGS_CR_IPSR_OFFSET 0 /* 0x0 */ #define IA64_PT_REGS_CR_IIP_OFFSET 8 /* 0x8 */ #define IA64_PT_REGS_CR_IFS_OFFSET 16 /* 0x10 */ diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h index 6594ca710cc2..fe947afbd496 100644 --- a/include/asm-ia64/page.h +++ b/include/asm-ia64/page.h @@ -3,8 +3,8 @@ /* * Pagetable related stuff. * - * Copyright (C) 1998, 1999 Hewlett-Packard Co - * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com> + * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> */ #include <linux/config.h> @@ -41,6 +41,22 @@ extern void clear_page (void *page); extern void copy_page (void *to, void *from); /* + * clear_user_page() and copy_user_page() can't be inline functions because + * flush_dcache_page() can't be defined until later... + */ +#define clear_user_page(addr, vaddr, page) \ +do { \ + clear_page(addr); \ + flush_dcache_page(page); \ +} while (0) + +#define copy_user_page(to, from, vaddr, page) \ +do { \ + copy_page((to), (from)); \ + flush_dcache_page(page); \ +} while (0) + +/* * Note: the MAP_NR_*() macro can't use __pa() because MAP_NR_*(X) MUST * map to something >= max_mapnr if X is outside the identity mapped * kernel space. diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h index f429cdec4ec9..26107d9e1e56 100644 --- a/include/asm-ia64/pal.h +++ b/include/asm-ia64/pal.h @@ -88,10 +88,10 @@ typedef s64 pal_status_t; #define PAL_STATUS_SUCCESS 0 /* No error */ -#define PAL_STATUS_UNIMPLEMENTED -1 /* Unimplemented procedure */ -#define PAL_STATUS_EINVAL -2 /* Invalid argument */ -#define PAL_STATUS_ERROR -3 /* Error */ -#define PAL_STATUS_CACHE_INIT_FAIL -4 /* Could not initialize the +#define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */ +#define PAL_STATUS_EINVAL (-2) /* Invalid argument */ +#define PAL_STATUS_ERROR (-3) /* Error */ +#define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the * specified level and type of * cache without sideeffects * and "restrict" was 1 diff --git a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h index 5be0974304c8..a637cff4ae2d 100644 --- a/include/asm-ia64/pci.h +++ b/include/asm-ia64/pci.h @@ -1,10 +1,11 @@ #ifndef _ASM_IA64_PCI_H #define _ASM_IA64_PCI_H +#include <linux/mm.h> #include <linux/slab.h> +#include <linux/spinlock.h> #include <linux/string.h> #include <linux/types.h> -#include <linux/spinlock.h> #include <asm/io.h> #include <asm/scatterlist.h> @@ -21,6 +22,13 @@ struct pci_dev; +/* + * The PCI address space does equal the physical memory address space. + * The networking and block device layers use this boolean for bounce + * buffer decisions. + */ +#define PCI_DMA_BUS_IS_PHYS (1) + static inline void pcibios_set_master (struct pci_dev *dev) { @@ -79,7 +87,7 @@ pci_dma_supported (struct pci_dev *hwdev, u64 mask) /* The ia64 platform always supports 64-bit addressing. */ #define pci_dac_dma_supported(pci_dev, mask) (1) -#define pci_dac_page_to_dma(dev,pg,off,dir) ((dma64_addr_t) page_to_bus(pg) + (off)) +#define pci_dac_page_to_dma(dev,pg,off,dir) ((dma_addr_t) page_to_bus(pg) + (off)) #define pci_dac_dma_to_page(dev,dma_addr) (virt_to_page(bus_to_virt(dma_addr))) #define pci_dac_dma_to_offset(dev,dma_addr) ((dma_addr) & ~PAGE_MASK) #define pci_dac_dma_sync_single(dev,dma_addr,len,dir) do { /* nothing */ } while (0) diff --git a/include/asm-ia64/perfmon.h b/include/asm-ia64/perfmon.h index 0f3498bc7226..c7083838ddcf 100644 --- a/include/asm-ia64/perfmon.h +++ b/include/asm-ia64/perfmon.h @@ -1,55 +1,177 @@ /* - * Copyright (C) 2001 Hewlett-Packard Co - * Copyright (C) 2001 Stephane Eranian <eranian@hpl.hp.com> + * Copyright (C) 2001-2002 Hewlett-Packard Co + * Stephane Eranian <eranian@hpl.hp.com> */ #ifndef _ASM_IA64_PERFMON_H #define _ASM_IA64_PERFMON_H -#include <linux/types.h> +/* + * perfmon comamnds supported on all CPU models + */ +#define PFM_WRITE_PMCS 0x01 +#define PFM_WRITE_PMDS 0x02 +#define PFM_READ_PMDS 0x03 +#define PFM_STOP 0x04 +#define PFM_START 0x05 +#define PFM_ENABLE 0x06 +#define PFM_DISABLE 0x07 +#define PFM_CREATE_CONTEXT 0x08 +#define PFM_DESTROY_CONTEXT 0x09 +#define PFM_RESTART 0x0a +#define PFM_PROTECT_CONTEXT 0x0b +#define PFM_GET_FEATURES 0x0c +#define PFM_DEBUG 0x0d +#define PFM_UNPROTECT_CONTEXT 0x0e + + +/* + * CPU model specific commands (may not be supported on all models) + */ +#define PFM_WRITE_IBRS 0x20 +#define PFM_WRITE_DBRS 0x21 + +/* + * context flags + */ +#define PFM_FL_INHERIT_NONE 0x00 /* never inherit a context across fork (default) */ +#define PFM_FL_INHERIT_ONCE 0x01 /* clone pfm_context only once across fork() */ +#define PFM_FL_INHERIT_ALL 0x02 /* always clone pfm_context across fork() */ +#define PFM_FL_NOTIFY_BLOCK 0x04 /* block task on user level notifications */ +#define PFM_FL_SYSTEM_WIDE 0x08 /* create a system wide context */ + +/* + * PMC flags + */ +#define PFM_REGFL_OVFL_NOTIFY 0x1 /* send notification on overflow */ + +/* + * PMD/PMC/IBR/DBR return flags (ignored on input) + * + * Those flags are used on output and must be checked in case EAGAIN is returned + * by any of the calls using a pfarg_reg_t or pfarg_dbreg_t structure. + */ +#define PFM_REG_RETFL_NOTAVAIL (1U<<31) /* set if register is implemented but not available */ +#define PFM_REG_RETFL_EINVAL (1U<<30) /* set if register entry is invalid */ +#define PFM_REG_RETFL_MASK (PFM_REG_RETFL_NOTAVAIL|PFM_REG_RETFL_EINVAL) + +#define PFM_REG_HAS_ERROR(flag) (((flag) & PFM_REG_RETFL_MASK) != 0) /* * Request structure used to define a context */ typedef struct { - unsigned long smpl_entries; /* how many entries in sampling buffer */ - unsigned long smpl_regs; /* which pmds to record on overflow */ - void *smpl_vaddr; /* returns address of BTB buffer */ + unsigned long ctx_smpl_entries; /* how many entries in sampling buffer */ + unsigned long ctx_smpl_regs[4]; /* which pmds to record on overflow */ - pid_t notify_pid; /* which process to notify on overflow */ - int notify_sig; /* XXX: not used anymore */ + pid_t ctx_notify_pid; /* which process to notify on overflow */ + int ctx_flags; /* noblock/block, inherit flags */ + void *ctx_smpl_vaddr; /* returns address of BTB buffer */ - int flags; /* NOBLOCK/BLOCK/ INHERIT flags (will replace API flags) */ -} pfreq_context_t; + unsigned long ctx_cpu_mask; /* on which CPU to enable perfmon (systemwide) */ + + unsigned long reserved[8]; /* for future use */ +} pfarg_context_t; /* * Request structure used to write/read a PMC or PMD */ typedef struct { - unsigned long reg_num; /* which register */ + unsigned int reg_num; /* which register */ + unsigned int reg_flags; /* PMC: notify/don't notify. PMD/PMC: return flags */ unsigned long reg_value; /* configuration (PMC) or initial value (PMD) */ - unsigned long reg_smpl_reset; /* reset of sampling buffer overflow (large) */ - unsigned long reg_ovfl_reset; /* reset on counter overflow (small) */ - int reg_flags; /* (PMD): notify/don't notify */ -} pfreq_reg_t; + + unsigned long reg_long_reset; /* reset after sampling buffer overflow (large) */ + unsigned long reg_short_reset;/* reset after counter overflow (small) */ + + unsigned long reg_reset_pmds[4]; /* which other counters to reset on overflow */ + + unsigned long reserved[16]; /* for future use */ +} pfarg_reg_t; + +typedef struct { + unsigned int dbreg_num; /* which register */ + unsigned int dbreg_flags; /* dbregs return flags */ + unsigned long dbreg_value; /* configuration (PMC) or initial value (PMD) */ + unsigned long reserved[6]; +} pfarg_dbreg_t; + +typedef struct { + unsigned int ft_version; /* perfmon: major [16-31], minor [0-15] */ + unsigned int ft_smpl_version;/* sampling format: major [16-31], minor [0-15] */ + unsigned long reserved[4]; /* for future use */ +} pfarg_features_t; + +/* + * This header is at the beginning of the sampling buffer returned to the user. + * It is exported as Read-Only at this point. It is directly followed by the + * first record. + */ +typedef struct { + unsigned int hdr_version; /* contains perfmon version (smpl format diffs) */ + unsigned int reserved; + unsigned long hdr_entry_size; /* size of one entry in bytes */ + unsigned long hdr_count; /* how many valid entries */ + unsigned long hdr_pmds[4]; /* which pmds are recorded */ +} perfmon_smpl_hdr_t; /* - * main request structure passed by user + * Define the version numbers for both perfmon as a whole and the sampling buffer format. */ -typedef union { - pfreq_context_t pfr_ctx; /* request to configure a context */ - pfreq_reg_t pfr_reg; /* request to configure a PMD/PMC */ -} perfmon_req_t; +#define PFM_VERSION_MAJ 1U +#define PFM_VERSION_MIN 0U +#define PFM_VERSION (((PFM_VERSION_MAJ&0xffff)<<16)|(PFM_VERSION_MIN & 0xffff)) + +#define PFM_SMPL_VERSION_MAJ 1U +#define PFM_SMPL_VERSION_MIN 0U +#define PFM_SMPL_VERSION (((PFM_SMPL_VERSION_MAJ&0xffff)<<16)|(PFM_SMPL_VERSION_MIN & 0xffff)) + + +#define PFM_VERSION_MAJOR(x) (((x)>>16) & 0xffff) +#define PFM_VERSION_MINOR(x) ((x) & 0xffff) + +/* + * Entry header in the sampling buffer. + * The header is directly followed with the PMDS saved in increasing index + * order: PMD4, PMD5, .... How many PMDs are present is determined by the + * user program during context creation. + * + * XXX: in this version of the entry, only up to 64 registers can be recorded + * This should be enough for quite some time. Always check sampling format + * before parsing entries! + * + * Inn the case where multiple counters have overflowed at the same time, the + * rate field indicate the initial value of the first PMD, based on the index. + * For instance, if PMD2 and PMD5 have ovewrflowed for this entry, the rate field + * will show the initial value of PMD2. + */ +typedef struct { + int pid; /* identification of process */ + int cpu; /* which cpu was used */ + unsigned long rate; /* initial value of overflowed counter */ + unsigned long stamp; /* timestamp */ + unsigned long ip; /* where did the overflow interrupt happened */ + unsigned long regs; /* bitmask of which registers overflowed */ + unsigned long period; /* sampling period used by overflowed counter (smallest pmd index) */ +} perfmon_smpl_entry_t; + +extern int perfmonctl(pid_t pid, int cmd, void *arg, int narg); #ifdef __KERNEL__ extern void pfm_save_regs (struct task_struct *); extern void pfm_load_regs (struct task_struct *); -extern int pfm_inherit (struct task_struct *, struct pt_regs *); +extern int pfm_inherit (struct task_struct *, struct pt_regs *); extern void pfm_context_exit (struct task_struct *); extern void pfm_flush_regs (struct task_struct *); extern void pfm_cleanup_notifiers (struct task_struct *); +extern void pfm_cleanup_owners (struct task_struct *); +extern int pfm_use_debug_registers(struct task_struct *); +extern int pfm_release_debug_registers(struct task_struct *); +extern int pfm_cleanup_smpl_buf(struct task_struct *); +extern void pfm_syst_wide_update_task(struct task_struct *, int); +extern void pfm_ovfl_block_reset (void); #endif /* __KERNEL__ */ diff --git a/include/asm-ia64/pgalloc.h b/include/asm-ia64/pgalloc.h index 8ed75d3a637f..4e9ebe83bbc2 100644 --- a/include/asm-ia64/pgalloc.h +++ b/include/asm-ia64/pgalloc.h @@ -30,7 +30,6 @@ */ #define pgd_quicklist (local_cpu_data->pgd_quick) #define pmd_quicklist (local_cpu_data->pmd_quick) -#define pte_quicklist (local_cpu_data->pte_quick) #define pgtable_cache_size (local_cpu_data->pgtable_cache_sz) static inline pgd_t* @@ -108,27 +107,29 @@ pmd_free (pmd_t *pmd) } static inline void -pmd_populate (struct mm_struct *mm, pmd_t *pmd_entry, pte_t *pte) +pmd_populate (struct mm_struct *mm, pmd_t *pmd_entry, struct page *pte) +{ + pmd_val(*pmd_entry) = page_to_phys(pte); +} + +static inline void +pmd_populate_kernel (struct mm_struct *mm, pmd_t *pmd_entry, pte_t *pte) { pmd_val(*pmd_entry) = __pa(pte); } -static inline pte_t* -pte_alloc_one_fast (struct mm_struct *mm, unsigned long addr) +static inline struct page * +pte_alloc_one (struct mm_struct *mm, unsigned long addr) { - unsigned long *ret = (unsigned long *)pte_quicklist; + struct page *pte = alloc_pages(GFP_KERNEL, 0); - if (__builtin_expect(ret != NULL, 1)) { - pte_quicklist = (unsigned long *)(*ret); - ret[0] = 0; - --pgtable_cache_size; - } - return (pte_t *)ret; + if (__builtin_expect(pte != NULL, 1)) + clear_page(page_address(pte)); + return pte; } - -static inline pte_t* -pte_alloc_one (struct mm_struct *mm, unsigned long addr) +static inline pte_t * +pte_alloc_one_kernel (struct mm_struct *mm, unsigned long addr) { pte_t *pte = (pte_t *) __get_free_page(GFP_KERNEL); @@ -138,16 +139,45 @@ pte_alloc_one (struct mm_struct *mm, unsigned long addr) } static inline void -pte_free (pte_t *pte) +pte_free (struct page *pte) { - *(unsigned long *)pte = (unsigned long) pte_quicklist; - pte_quicklist = (unsigned long *) pte; - ++pgtable_cache_size; + __free_page(pte); +} + +static inline void +pte_free_kernel (pte_t *pte) +{ + free_page((unsigned long) pte); } extern int do_check_pgt_cache (int, int); /* + * IA-64 doesn't have any external MMU info: the page tables contain all the necessary + * information. However, we use this macro to take care of any (delayed) i-cache flushing + * that may be necessary. + */ +static inline void +update_mmu_cache (struct vm_area_struct *vma, unsigned long vaddr, pte_t pte) +{ + unsigned long addr; + struct page *page; + + if (!pte_exec(pte)) + return; /* not an executable page... */ + + page = pte_page(pte); + /* don't use VADDR: it may not be mapped on this CPU (or may have just been flushed): */ + addr = (unsigned long) page_address(page); + + if (test_bit(PG_arch_1, &page->flags)) + return; /* i-cache is already coherent with d-cache */ + + flush_icache_range(addr, addr + PAGE_SIZE); + set_bit(PG_arch_1, &page->flags); /* mark page as clean */ +} + +/* * Now for some TLB flushing routines. This is the kind of stuff that * can be very expensive, so try to avoid them whenever possible. */ @@ -212,63 +242,4 @@ flush_tlb_pgtables (struct mm_struct *mm, unsigned long start, unsigned long end flush_tlb_range(&vma, ia64_thash(start), ia64_thash(end)); } -/* - * Now for some cache flushing routines. This is the kind of stuff - * that can be very expensive, so try to avoid them whenever possible. - */ - -/* Caches aren't brain-dead on the IA-64. */ -#define flush_cache_all() do { } while (0) -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) do { } while (0) -#define flush_cache_page(vma, vmaddr) do { } while (0) -#define flush_page_to_ram(page) do { } while (0) - -extern void flush_icache_range (unsigned long start, unsigned long end); - -static inline void -flush_dcache_page (struct page *page) -{ - clear_bit(PG_arch_1, &page->flags); -} - -static inline void -clear_user_page (void *addr, unsigned long vaddr, struct page *page) -{ - clear_page(addr); - flush_dcache_page(page); -} - -static inline void -copy_user_page (void *to, void *from, unsigned long vaddr, struct page *page) -{ - copy_page(to, from); - flush_dcache_page(page); -} - -/* - * IA-64 doesn't have any external MMU info: the page tables contain all the necessary - * information. However, we use this macro to take care of any (delayed) i-cache flushing - * that may be necessary. - */ -static inline void -update_mmu_cache (struct vm_area_struct *vma, unsigned long vaddr, pte_t pte) -{ - unsigned long addr; - struct page *page; - - if (!pte_exec(pte)) - return; /* not an executable page... */ - - page = pte_page(pte); - /* don't use VADDR: it may not be mapped on this CPU (or may have just been flushed): */ - addr = (unsigned long) page_address(page); - - if (test_bit(PG_arch_1, &page->flags)) - return; /* i-cache is already coherent with d-cache */ - - flush_icache_range(addr, addr + PAGE_SIZE); - set_bit(PG_arch_1, &page->flags); /* mark page as clean */ -} - #endif /* _ASM_IA64_PGALLOC_H */ diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h index c92025c36304..e086475d50ec 100644 --- a/include/asm-ia64/pgtable.h +++ b/include/asm-ia64/pgtable.h @@ -8,7 +8,7 @@ * This hopefully works with any (fixed) IA-64 page-size, as defined * in <asm/page.h> (currently 8192). * - * Copyright (C) 1998-2001 Hewlett-Packard Co + * Copyright (C) 1998-2002 Hewlett-Packard Co * David Mosberger-Tang <davidm@hpl.hp.com> */ @@ -108,19 +108,15 @@ /* * All the normal masks have the "page accessed" bits on, as any time * they are used, the page is accessed. They are cleared only by the - * page-out routines. On the other hand, we do NOT turn on the - * execute bit on pages that are mapped writable. For those pages, we - * turn on the X bit only when the program attempts to actually - * execute code in such a page (it's a "lazy execute bit", if you - * will). This lets reduce the amount of i-cache flushing we have to - * do for data pages such as stack and heap pages. + * page-out routines. */ #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A) #define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW) #define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) -#define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R) +#define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) #define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX) #define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX) +#define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX) # ifndef __ASSEMBLY__ @@ -152,8 +148,8 @@ #define __S011 PAGE_SHARED #define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX) #define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX) -#define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW) -#define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW) +#define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX) +#define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX) #define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e)) #define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) @@ -161,8 +157,7 @@ /* - * Some definitions to translate between mem_map, PTEs, and page - * addresses: + * Some definitions to translate between mem_map, PTEs, and page addresses: */ @@ -173,6 +168,7 @@ ia64_phys_addr_valid (unsigned long addr) return (addr & (local_cpu_data->unimpl_pa_mask)) == 0; } +#ifndef CONFIG_DISCONTIGMEM /* * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel * memory. For the return value to be meaningful, ADDR must be >= @@ -188,6 +184,8 @@ ia64_phys_addr_valid (unsigned long addr) */ #define kern_addr_valid(addr) (1) +#endif + /* * Now come the defines and routines to manage and access the three-level * page table. @@ -211,12 +209,12 @@ ia64_phys_addr_valid (unsigned long addr) * Conversion functions: convert a page and protection to a page entry, * and a page entry and page directory to the page they refer to. */ -#define mk_pte(page,pgprot) \ -({ \ - pte_t __pte; \ - \ - pte_val(__pte) = ((page - mem_map) << PAGE_SHIFT) | pgprot_val(pgprot); \ - __pte; \ +#define mk_pte(page,pgprot) \ +({ \ + pte_t __pte; \ + \ + pte_val(__pte) = (page_to_phys(page)) | pgprot_val(pgprot); \ + __pte; \ }) /* This takes a physical page address that is used by the remapping functions */ @@ -232,14 +230,17 @@ ia64_phys_addr_valid (unsigned long addr) #define pte_none(pte) (!pte_val(pte)) #define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE)) #define pte_clear(pte) (pte_val(*(pte)) = 0UL) +#ifndef CONFIG_DISCONTIGMEM /* pte_page() returns the "struct page *" corresponding to the PTE: */ -#define pte_page(pte) (mem_map + (unsigned long) ((pte_val(pte) & _PFN_MASK) >> PAGE_SHIFT)) +#define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET)) +#endif #define pmd_none(pmd) (!pmd_val(pmd)) #define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd))) #define pmd_present(pmd) (pmd_val(pmd) != 0UL) #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) -#define pmd_page(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK)) +#define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK)) +#define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET)) #define pgd_none(pgd) (!pgd_val(pgd)) #define pgd_bad(pgd) (!ia64_phys_addr_valid(pgd_val(pgd))) @@ -339,9 +340,16 @@ pgd_offset (struct mm_struct *mm, unsigned long address) #define pmd_offset(dir,addr) \ ((pmd_t *) pgd_page(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))) -/* Find an entry in the third-level page table.. */ -#define pte_offset(dir,addr) \ - ((pte_t *) pmd_page(*(dir)) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) +/* + * Find an entry in the third-level page table. This looks more complicated than it + * should be because some platforms place page tables in high memory. + */ +#define __pte_offset(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define pte_offset_kernel(dir,addr) ((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(addr)) +#define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr) +#define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr) +#define pte_unmap(pte) do { } while (0) +#define pte_unmap_nested(pte) do { } while (0) /* atomic versions of the some PTE manipulations: */ @@ -418,22 +426,6 @@ pte_same (pte_t a, pte_t b) return pte_val(a) == pte_val(b); } -/* - * Macros to check the type of access that triggered a page fault. - */ - -static inline int -is_write_access (int access_type) -{ - return (access_type & 0x2); -} - -static inline int -is_exec_access (int access_type) -{ - return (access_type & 0x4); -} - extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; extern void paging_init (void); @@ -448,6 +440,33 @@ extern void paging_init (void); #define io_remap_page_range remap_page_range /* XXX is this right? */ + +/* + * Now for some cache flushing routines. This is the kind of stuff that can be very + * expensive, so try to avoid them whenever possible. + */ + +/* Caches aren't brain-dead on the IA-64. */ +#define flush_cache_all() do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr) do { } while (0) +#define flush_page_to_ram(page) do { } while (0) +#define flush_icache_page(vma,page) do { } while (0) + +#define flush_dcache_page(page) \ +do { \ + clear_bit(PG_arch_1, &page->flags); \ +} while (0) + +extern void flush_icache_range (unsigned long start, unsigned long end); + +#define flush_icache_user_range(vma, page, user_addr, len) \ +do { \ + unsigned long _addr = page_address(page) + ((user_addr) & ~PAGE_MASK); \ + flush_icache_range(_addr, _addr + (len)); \ +} while (0) + /* * ZERO_PAGE is a global shared page that is always zero: used * for zero-mapped memory areas etc.. diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index 3acfdab97ad3..1b88dcaccd48 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -2,9 +2,9 @@ #define _ASM_IA64_PROCESSOR_H /* - * Copyright (C) 1998-2001 Hewlett-Packard Co - * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com> - * Copyright (C) 1998-2001 Stephane Eranian <eranian@hpl.hp.com> + * Copyright (C) 1998-2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> + * Stephane Eranian <eranian@hpl.hp.com> * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> * @@ -27,7 +27,6 @@ */ #define IA64_NUM_PMC_REGS 32 #define IA64_NUM_PMD_REGS 32 -#define IA64_NUM_PMD_COUNTERS 4 #define DEFAULT_MAP_BASE 0x2000000000000000 #define DEFAULT_TASK_SIZE 0xa000000000000000 @@ -170,6 +169,7 @@ #define IA64_THREAD_KRBS_SYNCED (__IA64_UL(1) << 5) /* krbs synced with process vm? */ #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */ #define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */ +#define IA64_THREAD_XSTACK (__IA64_UL(1) << 8) /* stack executable by default? */ #define IA64_THREAD_UAC_SHIFT 3 #define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS) @@ -187,6 +187,7 @@ #ifndef __ASSEMBLY__ #include <linux/threads.h> +#include <linux/cache.h> #include <asm/fpu.h> #include <asm/offsets.h> @@ -253,7 +254,6 @@ struct cpuinfo_ia64 { __u64 itm_next; /* interval timer mask value to use for next clock tick */ __u64 *pgd_quick; __u64 *pmd_quick; - __u64 *pte_quick; __u64 pgtable_cache_sz; /* CPUID-derived information: */ __u64 ppn; @@ -275,15 +275,23 @@ struct cpuinfo_ia64 { __u32 ptce_stride[2]; struct task_struct *ksoftirqd; /* kernel softirq daemon for this CPU */ #ifdef CONFIG_SMP + int cpu; __u64 loops_per_jiffy; __u64 ipi_count; __u64 prof_counter; __u64 prof_multiplier; - __u64 ipi_operation; + __u32 pfm_syst_wide; + __u32 pfm_dcr_pp; + /* this is written to by *other* CPUs: */ + __u64 ipi_operation ____cacheline_aligned; #endif #ifdef CONFIG_NUMA + void *node_directory; + int numa_node_id; struct cpuinfo_ia64 *cpu_data[NR_CPUS]; #endif + /* Platform specific word. MUST BE LAST IN STRUCT */ + __u64 platform_specific; } __attribute__ ((aligned (PAGE_SIZE))) ; /* @@ -303,7 +311,8 @@ struct cpuinfo_ia64 { * the array. */ #ifdef CONFIG_NUMA -# define cpu_data(cpu) local_cpu_data->cpu_data_ptrs[cpu] +# define cpu_data(cpu) local_cpu_data->cpu_data[cpu] +# define numa_node_id() (local_cpu_data->numa_node_id) #else extern struct cpuinfo_ia64 _cpu_data[NR_CPUS]; # define cpu_data(cpu) (&_cpu_data[cpu]) @@ -343,8 +352,8 @@ typedef struct { struct siginfo; struct thread_struct { + __u64 flags; /* various thread flags (see IA64_THREAD_*) */ __u64 ksp; /* kernel stack pointer */ - unsigned long flags; /* various flags */ __u64 map_base; /* base address for get_unmapped_area() */ __u64 task_size; /* limit for task size */ struct siginfo *siginfo; /* current siginfo struct for ptrace() */ @@ -366,10 +375,12 @@ struct thread_struct { #ifdef CONFIG_PERFMON __u64 pmc[IA64_NUM_PMC_REGS]; __u64 pmd[IA64_NUM_PMD_REGS]; - unsigned long pfm_must_block; /* non-zero if we need to block on overflow */ + unsigned long pfm_ovfl_block_reset;/* non-zero if we need to block or reset regs on ovfl */ void *pfm_context; /* pointer to detailed PMU context */ - atomic_t pfm_notifiers_check; /* indicate if release_thread much check tasklist */ -# define INIT_THREAD_PM {0, }, {0, }, 0, 0, {0}, + atomic_t pfm_notifiers_check; /* when >0, will cleanup ctx_notify_task in tasklist */ + atomic_t pfm_owners_check; /* when >0, will cleanup ctx_owner in tasklist */ + void *pfm_smpl_buf_list; /* list of sampling buffers to vfree */ +# define INIT_THREAD_PM {0, }, {0, }, 0, NULL, {0}, {0}, NULL, #else # define INIT_THREAD_PM #endif @@ -378,17 +389,17 @@ struct thread_struct { struct ia64_fpreg fph[96]; /* saved/loaded on demand */ }; -#define INIT_THREAD { \ - 0, /* ksp */ \ - 0, /* flags */ \ - DEFAULT_MAP_BASE, /* map_base */ \ - DEFAULT_TASK_SIZE, /* task_size */ \ - 0, /* siginfo */ \ - INIT_THREAD_IA32 \ - INIT_THREAD_PM \ - {0, }, /* dbr */ \ - {0, }, /* ibr */ \ - {{{{0}}}, } /* fph */ \ +#define INIT_THREAD { \ + flags: 0, \ + ksp: 0, \ + map_base: DEFAULT_MAP_BASE, \ + task_size: DEFAULT_TASK_SIZE, \ + siginfo: 0, \ + INIT_THREAD_IA32 \ + INIT_THREAD_PM \ + dbr: {0, }, \ + ibr: {0, }, \ + fph: {{{{0}}}, } \ } #define start_thread(regs,new_ip,new_sp) do { \ @@ -398,6 +409,7 @@ struct thread_struct { ia64_psr(regs)->cpl = 3; /* set user mode */ \ ia64_psr(regs)->ri = 0; /* clear return slot number */ \ ia64_psr(regs)->is = 0; /* IA-64 instruction set */ \ + ia64_psr(regs)->sp = 1; /* enforce secure perfmon */ \ regs->cr_iip = new_ip; \ regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \ regs->ar_rnat = 0; \ @@ -542,11 +554,6 @@ extern void ia32_save_state (struct task_struct *task); extern void ia32_load_state (struct task_struct *task); #endif -#ifdef CONFIG_PERFMON -extern void ia64_save_pm_regs (struct task_struct *task); -extern void ia64_load_pm_regs (struct task_struct *task); -#endif - #define ia64_fph_enable() asm volatile (";; rsm psr.dfh;; srlz.d;;" ::: "memory"); #define ia64_fph_disable() asm volatile (";; ssm psr.dfh;; srlz.d;;" ::: "memory"); @@ -808,15 +815,12 @@ ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat) * Note that the only way T can block is through a call to schedule() -> switch_to(). */ static inline unsigned long -thread_saved_pc (struct thread_struct *t) +thread_saved_pc (struct task_struct *t) { struct unw_frame_info info; unsigned long ip; - /* XXX ouch: Linus, please pass the task pointer to thread_saved_pc() instead! */ - struct task_struct *p = (void *) ((unsigned long) t - IA64_TASK_THREAD_OFFSET); - - unw_init_from_blocked_task(&info, p); + unw_init_from_blocked_task(&info, t); if (unw_unwind(&info) < 0) return 0; unw_get_ip(&info, &ip); @@ -829,16 +833,6 @@ thread_saved_pc (struct thread_struct *t) #define current_text_addr() \ ({ void *_pc; asm volatile ("mov %0=ip" : "=r" (_pc)); _pc; }) -#define THREAD_SIZE IA64_STK_OFFSET -/* NOTE: The task struct and the stacks are allocated together. */ -#define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL, IA64_TASK_STRUCT_LOG_NUM_PAGES)) -#define free_task_struct(p) free_pages((unsigned long)(p), IA64_TASK_STRUCT_LOG_NUM_PAGES) -#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count) - -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - /* * Set the correctable machine check vector register */ diff --git a/include/asm-ia64/ptrace.h b/include/asm-ia64/ptrace.h index 5210d2de1df4..844975e0faf4 100644 --- a/include/asm-ia64/ptrace.h +++ b/include/asm-ia64/ptrace.h @@ -2,9 +2,9 @@ #define _ASM_IA64_PTRACE_H /* - * Copyright (C) 1998-2001 Hewlett-Packard Co - * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com> - * Copyright (C) 1998, 1999 Stephane Eranian <eranian@hpl.hp.com> + * Copyright (C) 1998-2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> + * Stephane Eranian <eranian@hpl.hp.com> * * 12/07/98 S. Eranian added pt_regs & switch_stack * 12/21/98 D. Mosberger updated to match latest code @@ -39,7 +39,9 @@ * | (growing upwards) | | * | | | * +----------------------+ | --- IA64_RBS_OFFSET - * | | | ^ + * | struct thread_info | | ^ + * +----------------------+ | | + * | | | | * | struct task_struct | | | * current -> | | | | * +----------------------+ ------- @@ -58,19 +60,19 @@ * (including register backing store and memory stack): */ #if defined(CONFIG_IA64_PAGE_SIZE_4KB) -# define IA64_TASK_STRUCT_LOG_NUM_PAGES 3 +# define KERNEL_STACK_SIZE_ORDER 3 #elif defined(CONFIG_IA64_PAGE_SIZE_8KB) -# define IA64_TASK_STRUCT_LOG_NUM_PAGES 2 +# define KERNEL_STACK_SIZE_ORDER 2 #elif defined(CONFIG_IA64_PAGE_SIZE_16KB) -# define IA64_TASK_STRUCT_LOG_NUM_PAGES 1 +# define KERNEL_STACK_SIZE_ORDER 1 #else -# define IA64_TASK_STRUCT_LOG_NUM_PAGES 0 +# define KERNEL_STACK_SIZE_ORDER 0 #endif -#define IA64_RBS_OFFSET ((IA64_TASK_SIZE + 15) & ~15) -#define IA64_STK_OFFSET ((1 << IA64_TASK_STRUCT_LOG_NUM_PAGES)*PAGE_SIZE) +#define IA64_RBS_OFFSET ((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 15) & ~15) +#define IA64_STK_OFFSET ((1 << KERNEL_STACK_SIZE_ORDER)*PAGE_SIZE) -#define INIT_TASK_SIZE IA64_STK_OFFSET +#define KERNEL_STACK_SIZE IA64_STK_OFFSET #ifndef __ASSEMBLY__ @@ -247,8 +249,34 @@ force_successful_syscall_return (void) #endif /* !__KERNEL__ */ +/* pt_all_user_regs is used for PTRACE_GETREGS PTRACE_SETREGS */ +struct pt_all_user_regs { + unsigned long nat; + unsigned long cr_iip; + unsigned long cfm; + unsigned long cr_ipsr; + unsigned long pr; + + unsigned long gr[32]; + unsigned long br[8]; + unsigned long ar[128]; + struct ia64_fpreg fr[128]; +}; + #endif /* !__ASSEMBLY__ */ +/* indices to application-registers array in pt_all_user_regs */ +#define PT_AUR_RSC 16 +#define PT_AUR_BSP 17 +#define PT_AUR_BSPSTORE 18 +#define PT_AUR_RNAT 19 +#define PT_AUR_CCV 32 +#define PT_AUR_UNAT 36 +#define PT_AUR_FPSR 40 +#define PT_AUR_PFS 64 +#define PT_AUR_LC 65 +#define PT_AUR_EC 66 + /* * The numbers chosen here are somewhat arbitrary but absolutely MUST * not overlap with any of the number assigned in <linux/ptrace.h>. @@ -256,5 +284,12 @@ force_successful_syscall_return (void) #define PTRACE_SINGLEBLOCK 12 /* resume execution until next branch */ #define PTRACE_GETSIGINFO 13 /* get child's siginfo structure */ #define PTRACE_SETSIGINFO 14 /* set child's siginfo structure */ +#define PTRACE_GETREGS 18 /* get all registers (pt_all_user_regs) in one shot */ +#define PTRACE_SETREGS 19 /* set all registers (pt_all_user_regs) in one shot */ + +#define PTRACE_SETOPTIONS 21 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 #endif /* _ASM_IA64_PTRACE_H */ diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h index 904cb502ce68..570fa428ad7e 100644 --- a/include/asm-ia64/sal.h +++ b/include/asm-ia64/sal.h @@ -8,11 +8,14 @@ * Abstraction Layer". * * Copyright (C) 2001 Intel + * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com> * Copyright (C) 2001 Fred Lewis <frederick.v.lewis@intel.com> * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang <davidm@hpl.hp.com> * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com> * + * 02/01/04 J. Hall Updated Error Record Structures to conform to July 2001 + * revision of the SAL spec. * 01/01/03 fvlewis Updated Error Record Structures to conform with Nov. 2000 * revision of the SAL spec. * 99/09/29 davidm Updated for SAL 2.6. @@ -149,6 +152,7 @@ typedef struct ia64_sal_desc_memory { #define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK (1 << 0) #define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT (1 << 1) #define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT (1 << 2) +#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT (1 << 3) typedef struct ia64_sal_desc_platform_feature { u8 type; @@ -227,6 +231,10 @@ enum { SAL_VECTOR_OS_BOOT_RENDEZ = 2 }; +/* Encodings for mca_opt parameter sent to SAL_MC_SET_PARAMS */ +#define SAL_MC_PARAM_RZ_ALWAYS 0x1 +#define SAL_MC_PARAM_BINIT_ESCALATE 0x10 + /* ** Definition of the SAL Error Log from the SAL spec */ @@ -515,12 +523,12 @@ typedef struct sal_log_pci_comp_err_info { u16 vendor_id; u16 device_id; - u16 class_code; + u8 class_code[3]; u8 func_num; u8 dev_num; u8 bus_num; u8 seg_num; - u8 reserved[6]; + u8 reserved[5]; } comp_info; u32 num_mem_regs; u32 num_io_regs; @@ -776,4 +784,6 @@ ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size, return isrv.status; } +extern unsigned long sal_platform_features; + #endif /* _ASM_IA64_PAL_H */ diff --git a/include/asm-ia64/scatterlist.h b/include/asm-ia64/scatterlist.h index 76e9c5ec8985..22da42c46412 100644 --- a/include/asm-ia64/scatterlist.h +++ b/include/asm-ia64/scatterlist.h @@ -2,7 +2,7 @@ #define _ASM_IA64_SCATTERLIST_H /* - * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co + * Copyright (C) 1998-1999, 2001-2002 Hewlett-Packard Co * David Mosberger-Tang <davidm@hpl.hp.com> */ @@ -12,7 +12,6 @@ struct scatterlist { /* These two are only valid if ADDRESS member of this struct is NULL. */ struct page *page; unsigned int offset; - unsigned int length; /* buffer length */ }; diff --git a/include/asm-ia64/sigcontext.h b/include/asm-ia64/sigcontext.h index 4cb91706f27c..1ca82168e487 100644 --- a/include/asm-ia64/sigcontext.h +++ b/include/asm-ia64/sigcontext.h @@ -56,7 +56,9 @@ struct sigcontext { unsigned long sc_rbs_base; /* NULL or new base of sighandler's rbs */ unsigned long sc_loadrs; /* see description above */ - unsigned long sc_rsvd[14]; /* reserved for future use */ + unsigned long sc_ar25; /* rsvd for scratch use */ + unsigned long sc_ar26; /* rsvd for scratch use */ + unsigned long sc_rsvd[12]; /* reserved for future use */ /* * The mask must come last so we can increase _NSIG_WORDS * without breaking binary compatibility. diff --git a/include/asm-ia64/siginfo.h b/include/asm-ia64/siginfo.h index c04493693a80..f75b189ccf0c 100644 --- a/include/asm-ia64/siginfo.h +++ b/include/asm-ia64/siginfo.h @@ -2,8 +2,8 @@ #define _ASM_IA64_SIGINFO_H /* - * Copyright (C) 1998-2001 Hewlett-Packard Co - * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com> + * Copyright (C) 1998-2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> */ #include <linux/types.h> @@ -57,7 +57,7 @@ typedef struct siginfo { struct { void *_addr; /* faulting insn/memory ref. */ int _imm; /* immediate value for "break" */ - int _pad0; + unsigned int _flags; /* see below */ unsigned long _isr; /* isr */ } _sigfault; @@ -70,7 +70,7 @@ typedef struct siginfo { struct { pid_t _pid; /* which child */ uid_t _uid; /* sender's uid */ - unsigned long _pfm_ovfl_counters; /* which PMU counter overflowed */ + unsigned long _pfm_ovfl_counters[4]; /* which PMU counter overflowed */ } _sigprof; } _sifields; } siginfo_t; @@ -88,12 +88,23 @@ typedef struct siginfo { #define si_ptr _sifields._rt._sigval.sival_ptr #define si_addr _sifields._sigfault._addr #define si_imm _sifields._sigfault._imm /* as per UNIX SysV ABI spec */ -#define si_isr _sifields._sigfault._isr /* valid if si_code==FPE_FLTxxx */ +#define si_flags _sifields._sigfault._flags +/* + * si_isr is valid for SIGILL, SIGFPE, SIGSEGV, SIGBUS, and SIGTRAP provided that + * si_code is non-zero and __ISR_VALID is set in si_flags. + */ +#define si_isr _sifields._sigfault._isr #define si_band _sifields._sigpoll._band #define si_fd _sifields._sigpoll._fd #define si_pfm_ovfl _sifields._sigprof._pfm_ovfl_counters /* + * Flag values for si_flags: + */ +#define __ISR_VALID_BIT 0 +#define __ISR_VALID (1 << __ISR_VALID_BIT) + +/* * si_code values * Positive values for kernel-generated signals. */ @@ -119,12 +130,12 @@ typedef struct siginfo { #define SI_USER 0 /* sent by kill, sigsend, raise */ #define SI_KERNEL 0x80 /* sent by the kernel from somewhere */ -#define SI_QUEUE -1 /* sent by sigqueue */ +#define SI_QUEUE (-1) /* sent by sigqueue */ #define SI_TIMER __SI_CODE(__SI_TIMER,-2) /* sent by timer expiration */ -#define SI_MESGQ -3 /* sent by real time mesq state change */ -#define SI_ASYNCIO -4 /* sent by AIO completion */ -#define SI_SIGIO -5 /* sent by queued SIGIO */ -#define SI_TKILL -6 /* sent by tkill system call */ +#define SI_MESGQ (-3) /* sent by real time mesq state change */ +#define SI_ASYNCIO (-4) /* sent by AIO completion */ +#define SI_SIGIO (-5) /* sent by queued SIGIO */ +#define SI_TKILL (-6) /* sent by tkill system call */ #define SI_FROMUSER(siptr) ((siptr)->si_code <= 0) #define SI_FROMKERNEL(siptr) ((siptr)->si_code > 0) diff --git a/include/asm-ia64/signal.h b/include/asm-ia64/signal.h index af34e0074869..d5a61fea037e 100644 --- a/include/asm-ia64/signal.h +++ b/include/asm-ia64/signal.h @@ -115,6 +115,7 @@ #define SA_PROBE SA_ONESHOT #define SA_SAMPLE_RANDOM SA_RESTART #define SA_SHIRQ 0x04000000 +#define SA_PERCPU_IRQ 0x02000000 #endif /* __KERNEL__ */ diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h index 654911d32ab6..b6cde039e126 100644 --- a/include/asm-ia64/smp.h +++ b/include/asm-ia64/smp.h @@ -3,7 +3,7 @@ * * Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> - * Copyright (C) 2001 Hewlett-Packard Co + * Copyright (C) 2001-2002 Hewlett-Packard Co * David Mosberger-Tang <davidm@hpl.hp.com> */ #ifndef _ASM_IA64_SMP_H @@ -27,7 +27,7 @@ #define SMP_IRQ_REDIRECTION (1 << 0) #define SMP_IPI_REDIRECTION (1 << 1) -#define smp_processor_id() (current->processor) +#define smp_processor_id() (current_thread_info()->cpu) extern struct smp_boot_data { int cpu_count; @@ -110,17 +110,13 @@ hard_smp_processor_id (void) #define NO_PROC_ID 0xffffffff /* no processor magic marker */ -/* - * Extra overhead to move a task from one cpu to another (due to TLB and cache misses). - * Expressed in "negative nice value" units (larger number means higher priority/penalty). - */ -#define PROC_CHANGE_PENALTY 20 - extern void __init init_smp_config (void); extern void smp_do_timer (struct pt_regs *regs); extern int smp_call_function_single (int cpuid, void (*func) (void *info), void *info, int retry, int wait); +extern void smp_send_reschedule (int cpu); +extern void smp_send_reschedule_all (void); #endif /* CONFIG_SMP */ diff --git a/include/asm-ia64/smplock.h b/include/asm-ia64/smplock.h index a4b46657293e..f574e418a374 100644 --- a/include/asm-ia64/smplock.h +++ b/include/asm-ia64/smplock.h @@ -20,10 +20,11 @@ extern spinlock_t kernel_flag; static __inline__ void release_kernel_lock(struct task_struct *task, int cpu) { - if (task->lock_depth >= 0) + if (unlikely(task->lock_depth >= 0)) { spin_unlock(&kernel_flag); - release_irqlock(cpu); - __sti(); + if (global_irq_holder == (cpu)) \ + BUG(); \ + } } /* @@ -32,7 +33,7 @@ release_kernel_lock(struct task_struct *task, int cpu) static __inline__ void reacquire_kernel_lock(struct task_struct *task) { - if (task->lock_depth >= 0) + if (unlikely(task->lock_depth >= 0)) spin_lock(&kernel_flag); } diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h index b7ec2a1b18be..8794070da0ab 100644 --- a/include/asm-ia64/sn/addrs.h +++ b/include/asm-ia64/sn/addrs.h @@ -1,40 +1,42 @@ -/* $Id$ + +/* * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. - * Copyright (C) 1999 by Ralf Baechle + * Copyright (c) 1992-1999,2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_ADDRS_H -#define _ASM_SN_ADDRS_H -#include <linux/config.h> -#if _LANGUAGE_C -#include <linux/types.h> -#endif /* _LANGUAGE_C */ +#ifndef _ASM_IA64_SN_ADDRS_H +#define _ASM_IA64_SN_ADDRS_H -#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC) -#include <asm/addrspace.h> -#include <asm/reg.h> -#include <asm/sn/kldir.h> -#endif /* CONFIG_IA64_SGI_SN1 */ +#include <linux/config.h> -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) +#if defined (CONFIG_IA64_SGI_SN1) #include <asm/sn/sn1/addrs.h> -#endif +#elif defined (CONFIG_IA64_SGI_SN2) +#include <asm/sn/sn2/addrs.h> +#else +#error <<<BOMB! addrs.h defined only for SN1, or SN2 >>> +#endif /* !SN1 && !SN2 */ +#ifndef __ASSEMBLY__ +#include <asm/sn/types.h> +#endif -#if _LANGUAGE_C +#ifndef __ASSEMBLY__ #define PS_UINT_CAST (__psunsigned_t) #define UINT64_CAST (uint64_t) - +#ifdef CONFIG_IA64_SGI_SN2 +#define HUBREG_CAST (volatile mmr_t *) +#else #define HUBREG_CAST (volatile hubreg_t *) +#endif -#elif _LANGUAGE_ASSEMBLY +#elif __ASSEMBLY__ #define PS_UINT_CAST #define UINT64_CAST @@ -43,18 +45,6 @@ #endif -#define NASID_GET_META(_n) ((_n) >> NASID_LOCAL_BITS) -#if defined CONFIG_SGI_IP35 || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -#define NASID_GET_LOCAL(_n) ((_n) & 0x7f) -#endif -#define NASID_MAKE(_m, _l) (((_m) << NASID_LOCAL_BITS) | (_l)) - -#define NODE_ADDRSPACE_MASK (NODE_ADDRSPACE_SIZE - 1) -#define TO_NODE_ADDRSPACE(_pa) (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK) - -#define CHANGE_ADDR_NASID(_pa, _nasid) \ - ((UINT64_CAST (_pa) & ~NASID_MASK) | \ - (UINT64_CAST(_nasid) << NASID_SHFT)) /* @@ -62,7 +52,11 @@ * node's address space. */ +#ifdef CONFIG_IA64_SGI_SN2 /* SN2 has an extra AS field between node offset and node id (nasid) */ +#define NODE_OFFSET(_n) (UINT64_CAST (_n) << NASID_SHFT) +#else #define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS) +#endif #define NODE_CAC_BASE(_n) (CAC_BASE + NODE_OFFSET(_n)) #define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n)) @@ -118,11 +112,6 @@ /* * The following define the major position-independent aliases used * in SN. - * UALIAS -- 256MB in size, reads in the UALIAS result in - * uncached references to the memory of the reader's node. - * CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped - * depending on which CPU does the access to provide - * all CPUs with unique uncached memory at low addresses. * LBOOT -- 256MB in size, reads in the LBOOT area result in * uncached references to the local hub's boot prom and * other directory-bus connected devices. @@ -130,17 +119,7 @@ * references to the local hub's registers. */ -#define UALIAS_BASE HSPEC_BASE -#define UALIAS_SIZE 0x10000000 /* 256 Megabytes */ -#define CPU_UALIAS 0x20000 /* 128 Kilobytes */ -#define UALIAS_CPU_SIZE (CPU_UALIAS / CPUS_PER_NODE) -#define UALIAS_LIMIT (UALIAS_BASE + UALIAS_SIZE) - -/* - * The bottom of ualias space is flipped depending on whether you're - * processor 0 or 1 within a node. - */ -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) +#if defined CONFIG_IA64_SGI_SN1 #define LREG_BASE (HSPEC_BASE + 0x10000000) #define LREG_SIZE 0x8000000 /* 128 MB */ #define LREG_LIMIT (LREG_BASE + LREG_SIZE) @@ -151,7 +130,11 @@ #endif #define HUB_REGISTER_WIDGET 1 +#ifdef CONFIG_IA64_SGI_SN2 +#define IALIAS_BASE LOCAL_SWIN_BASE(HUB_REGISTER_WIDGET) +#else #define IALIAS_BASE NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET) +#endif #define IALIAS_SIZE 0x800000 /* 8 Megabytes */ #define IS_IALIAS(_a) (((_a) >= IALIAS_BASE) && \ ((_a) < (IALIAS_BASE + IALIAS_SIZE))) @@ -160,7 +143,7 @@ * Macro for referring to Hub's RBOOT space */ -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) +#if defined CONFIG_IA64_SGI_SN1 #define NODE_LREG_BASE(_n) (NODE_HSPEC_BASE(_n) + 0x30000000) #define NODE_LREG_LIMIT(_n) (NODE_LREG_BASE(_n) + LREG_SIZE) @@ -172,177 +155,45 @@ #endif -/* - * Macros for referring the Hub's back door space - * - * These macros correctly process addresses in any node's space. - * WARNING: They won't work in assembler. - * - * BDDIR_ENTRY_LO returns the address of the low double-word of the dir - * entry corresponding to a physical (Cac or Uncac) address. - * BDDIR_ENTRY_HI returns the address of the high double-word of the entry. - * BDPRT_ENTRY returns the address of the double-word protection entry - * corresponding to the page containing the physical address. - * BDPRT_ENTRY_S Stores the value into the protection entry. - * BDPRT_ENTRY_L Load the value from the protection entry. - * BDECC_ENTRY returns the address of the ECC byte corresponding to a - * double-word at a specified physical address. - * BDECC_ENTRY_H returns the address of the two ECC bytes corresponding to a - * quad-word at a specified physical address. - */ -#define NODE_BDOOR_BASE(_n) (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2)) -#define NODE_BDECC_BASE(_n) (NODE_BDOOR_BASE(_n)) -#define NODE_BDDIR_BASE(_n) (NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4)) -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) /* - * Bedrock's directory entries are a single word: no low/high - */ - -#define BDDIR_ENTRY(_pa) (HSPEC_BASE + \ - NODE_ADDRSPACE_SIZE * 7 / 8 | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 3 & BDDIR_UPPER_MASK) - -#ifdef BRINGUP - /* minimize source changes by mapping *_LO() & *_HI() */ -#define BDDIR_ENTRY_LO(_pa) BDDIR_ENTRY(_pa) -#define BDDIR_ENTRY_HI(_pa) BDDIR_ENTRY(_pa) -#endif /* BRINGUP */ - -#define BDDIR_PAGE_MASK (BDDIR_UPPER_MASK & 0x7ffff << 11) -#define BDDIR_PAGE_BASE_MASK (UINT64_CAST 0xfffffffffffff800) - -#ifdef _LANGUAGE_C - -#define BDPRT_ENTRY_ADDR(_pa, _rgn) ((uint64_t *) ( (HSPEC_BASE + \ - NODE_ADDRSPACE_SIZE * 7 / 8 + 0x408) | \ - (UINT64_CAST (_pa) & NASID_MASK) | \ - (UINT64_CAST (_pa) >> 3 & BDDIR_PAGE_MASK) | \ - (UINT64_CAST (_pa) >> 3 & 0x3 << 4) | \ - ((_rgn) & 0x1e) << 5)) - -static __inline uint64_t BDPRT_ENTRY_L(paddr_t pa,uint32_t rgn) { - uint64_t word=*BDPRT_ENTRY_ADDR(pa,rgn); - - if(rgn&0x20) /*If the region is > 32, move it down*/ - word = word >> 32; - if(rgn&0x1) /*If the region is odd, get that part */ - word = word >> 16; - word = word & 0xffff; /*Get the 16 bits we are interested in*/ - - return word; -} - -static __inline void BDPRT_ENTRY_S(paddr_t pa,uint32_t rgn,uint64_t val) { - uint64_t *addr=(uint64_t *)BDPRT_ENTRY_ADDR(pa,rgn); - uint64_t word,mask; - - word=*addr; - mask=0; - if(rgn&0x1) { - mask|=0x0000ffff0000ffff; - val=val<<16; - } - else - mask|=0xffff0000ffff0000; - if(rgn&0x20) { - mask|=0x00000000ffffffff; - val=val<<32; - } - else - mask|=0xffffffff00000000; - word &= mask; - word |= val; - - *(addr++)=word; - addr++; - *(addr++)=word; - addr++; - *(addr++)=word; - addr++; - *addr=word; -} -#endif /*_LANGUAGE_C*/ - -#define BDCNT_ENTRY(_pa) (HSPEC_BASE + \ - NODE_ADDRSPACE_SIZE * 7 / 8 + 0x8 | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 3 & BDDIR_PAGE_MASK | \ - UINT64_CAST (_pa) >> 3 & 0x3 << 4) - - -#ifdef BRINGUP - /* little endian packing of ecc bytes requires a swizzle */ - /* this is problemmatic for memory_init_ecc */ -#endif /* BRINGUP */ -#define BDECC_ENTRY(_pa) (HSPEC_BASE + \ - NODE_ADDRSPACE_SIZE * 5 / 8 | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK \ - ^ 0x7ULL) - -#define BDECC_SCRUB(_pa) (HSPEC_BASE + \ - NODE_ADDRSPACE_SIZE / 2 | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK \ - ^ 0x7ULL) - - /* address for Halfword backdoor ecc access. Note that */ - /* ecc bytes are packed in little endian order */ -#define BDECC_ENTRY_H(_pa) (HSPEC_BASE + \ - NODE_ADDRSPACE_SIZE * 5 / 8 | \ - UINT64_CAST (_pa) & NASID_MASK | \ - UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK \ - ^ 0x6ULL) - -/* - * Macro to convert a back door directory, protection, page counter, or ecc - * address into the raw physical address of the associated cache line - * or protection page. + * The following macros produce the correct base virtual address for + * the hub registers. The LOCAL_HUB_* macros produce the appropriate + * address for the local registers. The REMOTE_HUB_* macro produce + * the address for the specified hub's registers. The intent is + * that the appropriate PI, MD, NI, or II register would be substituted + * for _x. */ -#define BDDIR_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDDIR_UPPER_MASK) << 3) -#ifdef BRINGUP +#ifdef CONFIG_IA64_SGI_SN2 /* - * This can't be done since there are 4 entries per address so you'd end up - * mapping back to 4 different physical addrs. + * SN2 has II mmr's located inside small window space like SN0 & SN1, + * but has all other non-II mmr's located at the top of big window + * space, unlike SN0 & SN1. */ - -#define BDPRT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDDIR_PAGE_MASK) << 3 | \ - (UINT64_CAST (_ba) & 0x3 << 4) << 3) -#endif - -#define BDCNT_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - (UINT64_CAST (_ba) & BDDIR_PAGE_MASK) << 3 | \ - (UINT64_CAST (_ba) & 0x3 << 4) << 3) +#define LOCAL_HUB_BASE(_x) (LOCAL_MMR_ADDR(_x) | (((~(_x)) & BWIN_TOP)>>8)) +#define REMOTE_HUB_BASE(_x) \ + (UNCACHED | GLOBAL_MMR_SPACE | \ + (((~(_x)) & BWIN_TOP)>>8) | \ + (((~(_x)) & BWIN_TOP)>>9) | (_x)) -#define BDECC_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - ((UINT64_CAST (_ba) ^ 0x7ULL) \ - & BDECC_UPPER_MASK) << 3 ) +#define LOCAL_HUB(_x) (HUBREG_CAST LOCAL_HUB_BASE(_x)) +#define REMOTE_HUB(_n, _x) \ + (HUBREG_CAST (REMOTE_HUB_BASE(_x) | ((((long)(_n))<<NASID_SHFT)))) -#define BDECC_H_TO_MEM(_ba) (UINT64_CAST (_ba) & NASID_MASK | \ - ((UINT64_CAST (_ba) ^ 0x6ULL) \ - & BDECC_UPPER_MASK) << 3 ) +#else /* not CONFIG_IA64_SGI_SN2 */ -#define BDADDR_IS_DIR(_ba) ((UINT64_CAST (_ba) & 0x8) == 0) -#define BDADDR_IS_PRT(_ba) ((UINT64_CAST (_ba) & 0x408) == 0x408) -#define BDADDR_IS_CNT(_ba) ((UINT64_CAST (_ba) & 0x8) == 0x8) - -#endif /* CONFIG_SGI_IP35 */ +#define LOCAL_HUB(_x) (HUBREG_CAST (IALIAS_BASE + (_x))) +#define REMOTE_HUB(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ + 0x800000 + (_x))) +#endif +#ifdef CONFIG_IA64_SGI_SN1 +#define LOCAL_HSPEC(_x) (HUBREG_CAST (LREG_BASE + (_x))) +#define REMOTE_HSPEC(_n, _x) (HUBREG_CAST (RREG_BASE(_n) + (_x))) +#endif /* CONFIG_IA64_SGI_SN1 */ -/* - * The following macros produce the correct base virtual address for - * the hub registers. The LOCAL_HUB_* macros produce the appropriate - * address for the local registers. The REMOTE_HUB_* macro produce - * the address for the specified hub's registers. The intent is - * that the appropriate PI, MD, NI, or II register would be substituted - * for _x. - */ /* * WARNING: @@ -352,17 +203,29 @@ static __inline void BDPRT_ENTRY_S(paddr_t pa,uint32_t rgn,uint64_t val) { * Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S(). * They're always safe. */ +#ifdef CONFIG_IA64_SGI_SN2 +#define LOCAL_HUB_ADDR(_x) \ + (((_x) & BWIN_TOP) ? (HUBREG_CAST (LOCAL_MMR_ADDR(_x))) \ + : (HUBREG_CAST (IALIAS_BASE + (_x)))) +#define REMOTE_HUB_ADDR(_n, _x) \ + (((_x) & BWIN_TOP) ? (HUBREG_CAST (GLOBAL_MMR_ADDR(_n, _x))) \ + : (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + 0x800000 + (_x)))) +#else #define LOCAL_HUB_ADDR(_x) (HUBREG_CAST (IALIAS_BASE + (_x))) #define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ 0x800000 + (_x))) -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) +#endif +#if CONFIG_IA64_SGI_SN1 #define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \ 0x800000 + PIREG(_x, _sn))) +#endif + +#ifdef CONFIG_IA64_SGI_SN1 #define LOCAL_HSPEC_ADDR(_x) (HUBREG_CAST (LREG_BASE + (_x))) #define REMOTE_HSPEC_ADDR(_n, _x) (HUBREG_CAST (RREG_BASE(_n) + (_x))) -#endif /* CONFIG_SGI_IP35 */ +#endif /* CONFIG_IA64_SGI_SN1 */ -#if _LANGUAGE_C +#ifndef __ASSEMBLY__ #define HUB_L(_a) *(_a) #define HUB_S(_a, _d) *(_a) = (_d) @@ -374,14 +237,14 @@ static __inline void BDPRT_ENTRY_S(paddr_t pa,uint32_t rgn,uint64_t val) { #define REMOTE_HUB_PI_L(_n, _sn, _r) HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r))) #define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d)) -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) +#ifdef CONFIG_IA64_SGI_SN1 #define LOCAL_HSPEC_L(_r) HUB_L(LOCAL_HSPEC_ADDR(_r)) #define LOCAL_HSPEC_S(_r, _d) HUB_S(LOCAL_HSPEC_ADDR(_r), (_d)) #define REMOTE_HSPEC_L(_n, _r) HUB_L(REMOTE_HSPEC_ADDR((_n), (_r))) #define REMOTE_HSPEC_S(_n, _r, _d) HUB_S(REMOTE_HSPEC_ADDR((_n), (_r)), (_d)) -#endif /* CONFIG_SGI_IP35 */ +#endif /* CONFIG_IA64_SGI_SN1 */ -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /* * The following macros are used to get to a hub/bridge register, given @@ -410,13 +273,8 @@ static __inline void BDPRT_ENTRY_S(paddr_t pa,uint32_t rgn,uint64_t val) { #define ARCS_SPB_SIZE 0x0400 #define KLDIR_OFFSET 0x2000 -#ifndef __ia64 #define KLDIR_ADDR(nasid) \ - TO_NODE_UNCAC((nasid), KLDIR_OFFSET) -#else -#define KLDIR_ADDR(nasid) \ - TO_NODE_CAC((nasid), KLDIR_OFFSET) -#endif + TO_NODE_CAC((nasid), KLDIR_OFFSET) #define KLDIR_SIZE 0x0400 @@ -439,7 +297,7 @@ static __inline void BDPRT_ENTRY_S(paddr_t pa,uint32_t rgn,uint64_t val) { #define KLI_KERN_XP 8 #define KLI_KERN_PARTID 9 -#if _LANGUAGE_C +#ifndef __ASSEMBLY__ #define KLD_BASE(nasid) ((kldir_ent_t *) KLDIR_ADDR(nasid)) #define KLD_LAUNCH(nasid) (KLD_BASE(nasid) + KLI_LAUNCH) @@ -453,85 +311,23 @@ static __inline void BDPRT_ENTRY_S(paddr_t pa,uint32_t rgn,uint64_t val) { #define KLD_KERN_XP(nasid) (KLD_BASE(nasid) + KLI_KERN_XP) #define KLD_KERN_PARTID(nasid) (KLD_BASE(nasid) + KLI_KERN_PARTID) -#define LAUNCH_OFFSET(nasid, slice) \ - (KLD_LAUNCH(nasid)->offset + \ - KLD_LAUNCH(nasid)->stride * (slice)) -#define LAUNCH_ADDR(nasid, slice) \ - TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice)) -#define LAUNCH_SIZE(nasid) KLD_LAUNCH(nasid)->size - -#define NMI_OFFSET(nasid, slice) \ - (KLD_NMI(nasid)->offset + \ - KLD_NMI(nasid)->stride * (slice)) -#define NMI_ADDR(nasid, slice) \ - TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice)) -#define NMI_SIZE(nasid) KLD_NMI(nasid)->size - +#ifndef CONFIG_IA64_SGI_SN2 #define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset +#else +#define KLCONFIG_OFFSET(nasid) \ + ia64_sn_get_klconfig_addr(nasid) +#endif /* CONFIG_IA64_SGI_SN2 */ + #define KLCONFIG_ADDR(nasid) \ - TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid)) + TO_NODE_CAC((nasid), KLCONFIG_OFFSET(nasid)) #define KLCONFIG_SIZE(nasid) KLD_KLCONFIG(nasid)->size #define GDA_ADDR(nasid) KLD_GDA(nasid)->pointer #define GDA_SIZE(nasid) KLD_GDA(nasid)->size -#define SYMMON_STK_OFFSET(nasid, slice) \ - (KLD_SYMMON_STK(nasid)->offset + \ - KLD_SYMMON_STK(nasid)->stride * (slice)) -#define SYMMON_STK_STRIDE(nasid) KLD_SYMMON_STK(nasid)->stride - -#define SYMMON_STK_ADDR(nasid, slice) \ - TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice)) - -#define SYMMON_STK_SIZE(nasid) KLD_SYMMON_STK(nasid)->stride - -#define SYMMON_STK_END(nasid) (SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size) - -/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a - * relocatable program - */ -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -/* update master.d/sn1_elspec.dbg, SN1/addrs.h/DEBUGUNIX_ADDR, and - * DBGLOADADDR in symmon's Makefile when changing this */ -#define UNIX_DEBUG_LOADADDR 0x310000 -#elif defined(SN0XXL) -#define UNIX_DEBUG_LOADADDR 0x360000 -#else -#define UNIX_DEBUG_LOADADDR 0x300000 -#endif -#define SYMMON_LOADADDR(nasid) \ - TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000)) - -#define FREEMEM_OFFSET(nasid) KLD_FREEMEM(nasid)->offset -#define FREEMEM_ADDR(nasid) SYMMON_STK_END(nasid) -/* - * XXX - * Fix this. FREEMEM_ADDR should be aware of if symmon is loaded. - * Also, it should take into account what prom thinks to be a safe - * address - PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid)) - */ -#define FREEMEM_SIZE(nasid) KLD_FREEMEM(nasid)->size - -#define PI_ERROR_OFFSET(nasid) KLD_PI_ERROR(nasid)->offset -#define PI_ERROR_ADDR(nasid) \ - TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid)) -#define PI_ERROR_SIZE(nasid) KLD_PI_ERROR(nasid)->size - #define NODE_OFFSET_TO_K0(_nasid, _off) \ (PAGE_OFFSET | NODE_OFFSET(_nasid) | (_off)) -#define K0_TO_NODE_OFFSET(_k0addr) \ - ((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK) - -#define KERN_VARS_ADDR(nasid) KLD_KERN_VARS(nasid)->pointer -#define KERN_VARS_SIZE(nasid) KLD_KERN_VARS(nasid)->size - -#define KERN_XP_ADDR(nasid) KLD_KERN_XP(nasid)->pointer -#define KERN_XP_SIZE(nasid) KLD_KERN_XP(nasid)->size - -#define GPDA_ADDR(nasid) TO_NODE_CAC(nasid, GPDA_OFFSET) - -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ -#endif /* _ASM_SN_ADDRS_H */ +#endif /* _ASM_IA64_SN_ADDRS_H */ diff --git a/include/asm-ia64/sn/agent.h b/include/asm-ia64/sn/agent.h deleted file mode 100644 index 8304821484f3..000000000000 --- a/include/asm-ia64/sn/agent.h +++ /dev/null @@ -1,47 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * This file has definitions for the hub and snac interfaces. - * - * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc. - * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) - */ -#ifndef _ASM_SGI_SN_AGENT_H -#define _ASM_SGI_SN_AGENT_H - -#include <linux/config.h> - -#include <asm/sn/addrs.h> -#include <asm/sn/arch.h> -//#include <asm/sn/io.h> - -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -#include <asm/sn/sn1/bedrock.h> -#endif /* CONFIG_SGI_IP35 */ - -/* - * NIC register macros - */ - -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -#define HUB_NIC_ADDR(_cpuid) \ - REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(_cpuid)), \ - LB_MICROLAN_CTL) -#endif - -#define SET_HUB_NIC(_my_cpuid, _val) \ - (HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val))) - -#define SET_MY_HUB_NIC(_v) \ - SET_HUB_NIC(cpuid(), (_v)) - -#define GET_HUB_NIC(_my_cpuid) \ - (HUB_L(HUB_NIC_ADDR(_my_cpuid))) - -#define GET_MY_HUB_NIC() \ - GET_HUB_NIC(cpuid()) - -#endif /* _ASM_SGI_SN_AGENT_H */ diff --git a/include/asm-ia64/sn/alenlist.h b/include/asm-ia64/sn/alenlist.h index 6e66e271145e..81243e7c2445 100644 --- a/include/asm-ia64/sn/alenlist.h +++ b/include/asm-ia64/sn/alenlist.h @@ -4,11 +4,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_ALENLIST_H -#define _ASM_SN_ALENLIST_H +#ifndef _ASM_IA64_SN_ALENLIST_H +#define _ASM_IA64_SN_ALENLIST_H + +#include <linux/types.h> /* Definition of Address/Length List */ @@ -51,7 +52,7 @@ typedef struct external_alenlist *external_alenlist_t; /* Return codes from alenlist routines. */ -#define ALENLIST_FAILURE -1 +#define ALENLIST_FAILURE (-1) #define ALENLIST_SUCCESS 0 @@ -201,4 +202,4 @@ struct alenlist_cursor_s { } #endif -#endif /* _ASM_SN_ALENLIST_H */ +#endif /* _ASM_IA64_SN_ALENLIST_H */ diff --git a/include/asm-ia64/sn/arc/hinv.h b/include/asm-ia64/sn/arc/hinv.h index 685c6bb9d7e3..9ae8feb80de7 100644 --- a/include/asm-ia64/sn/arc/hinv.h +++ b/include/asm-ia64/sn/arc/hinv.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com) + * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. */ diff --git a/include/asm-ia64/sn/arc/types.h b/include/asm-ia64/sn/arc/types.h index 0c8118d81900..53c5d4d8186c 100644 --- a/include/asm-ia64/sn/arc/types.h +++ b/include/asm-ia64/sn/arc/types.h @@ -4,7 +4,7 @@ * for more details. * * Copyright 1999 Ralf Baechle (ralf@gnu.org) - * Copyright 1999 Silicon Graphics, Inc. + * Copyright 1999,2001 Silicon Graphics, Inc. */ #ifndef _ASM_SN_ARC_TYPES_H #define _ASM_SN_ARC_TYPES_H diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h index c30da6e841e0..0feec4e8df6a 100644 --- a/include/asm-ia64/sn/arch.h +++ b/include/asm-ia64/sn/arch.h @@ -6,180 +6,50 @@ * * SGI specific setup. * - * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc. + * Copyright (C) 1995-1997,1999,2001-2002 Silicon Graphics, Inc. All rights reserved. * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org) */ -#ifndef _ASM_SN_ARCH_H -#define _ASM_SN_ARCH_H +#ifndef _ASM_IA64_SN_ARCH_H +#define _ASM_IA64_SN_ARCH_H -#include <linux/types.h> #include <linux/config.h> - +#include <linux/threads.h> +#include <linux/mmzone.h> #include <asm/sn/types.h> -#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_SGI_IP37) || defined(CONFIG_IA64_GENERIC) + +#if defined(CONFIG_IA64_SGI_SN1) #include <asm/sn/sn1/arch.h> +#elif defined(CONFIG_IA64_SGI_SN2) +#include <asm/sn/sn2/arch.h> #endif -#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) +#if defined(CONFIG_IA64_SGI_SN1) +typedef u64 bdrkreg_t; +#elif defined(CONFIG_IA64_SGI_SN2) +typedef u64 shubreg_t; +#endif + typedef u64 hubreg_t; +typedef u64 mmr_t; typedef u64 nic_t; -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -typedef u64 bdrkreg_t; -#endif /* CONFIG_SGI_xxxxx */ -#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */ - -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -#define CPUS_PER_NODE 4 /* CPUs on a single hub */ -#define CPUS_PER_NODE_SHFT 2 /* Bits to shift in the node number */ -#define CPUS_PER_SUBNODE 2 /* CPUs on a single hub PI */ -#endif -#define CNODE_NUM_CPUS(_cnode) (NODEPDA(_cnode)->node_num_cpus) #define CNODE_TO_CPU_BASE(_cnode) (NODEPDA(_cnode)->node_first_cpu) -#define makespnum(_nasid, _slice) \ - (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice)) - -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) - -/* - * There are 2 very similar macros for dealing with "slices". Make sure - * you use the right one. - * Unfortunately, on all platforms except IP35 (currently), the 2 macros - * are interchangible. - * - * On IP35, there are 4 cpus per node. Each cpu is refered to by it's slice. - * The slices are numbered 0 thru 3. - * - * There are also 2 PI interfaces per node. Each PI interface supports 2 cpus. - * The term "local slice" specifies the cpu number relative to the PI. - * - * The cpus on the node are numbered: - * slice localslice - * 0 0 - * 1 1 - * 2 0 - * 3 1 - * - * cputoslice - returns a number 0..3 that is the slice of the specified cpu. - * cputolocalslice - returns a number 0..1 that identifies the local slice of - * the cpu within it's PI interface. - */ -#ifdef LATER - /* These are dummied up for now ..... */ -#define cputocnode(cpu) \ - (pdaindr[(cpu)].p_nodeid) -#define cputonasid(cpu) \ - (pdaindr[(cpu)].p_nasid) -#define cputoslice(cpu) \ - (ASSERT(pdaindr[(cpu)].pda), (pdaindr[(cpu)].pda->p_slice)) -#define cputolocalslice(cpu) \ - (ASSERT(pdaindr[(cpu)].pda), (LOCALCPU(pdaindr[(cpu)].pda->p_slice))) -#define cputosubnode(cpu) \ - (ASSERT(pdaindr[(cpu)].pda), (SUBNODE(pdaindr[(cpu)].pda->p_slice))) -#else -#define cputocnode(cpu) 0 -#define cputonasid(cpu) 0 -#define cputoslice(cpu) 0 -#define cputolocalslice(cpu) 0 -#define cputosubnode(cpu) 0 -#endif /* LATER */ -#endif /* CONFIG_SGI_IP35 */ - -#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) - -#define INVALID_NASID (nasid_t)-1 -#define INVALID_CNODEID (cnodeid_t)-1 -#define INVALID_PNODEID (pnodeid_t)-1 -#define INVALID_MODULE (moduleid_t)-1 -#define INVALID_PARTID (partid_t)-1 - -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -extern int get_slice(void); -extern cpuid_t get_cnode_cpu(cnodeid_t); -extern int get_cpu_slice(cpuid_t); -extern cpuid_t cnodetocpu(cnodeid_t); -// extern cpuid_t cnode_slice_to_cpuid(cnodeid_t, int); - -extern int cnode_exists(cnodeid_t cnode); -extern cnodeid_t cpuid_to_compact_node[MAXCPUS]; -#endif /* CONFIG_IP35 */ - -extern nasid_t get_nasid(void); -extern cnodeid_t get_cpu_cnode(int); -extern int get_cpu_slice(cpuid_t); - -/* - * NO ONE should access these arrays directly. The only reason we refer to - * them here is to avoid the procedure call that would be required in the - * macros below. (Really want private data members here :-) - */ -extern cnodeid_t nasid_to_compact_node[MAX_NASIDS]; -extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES]; - -/* - * These macros are used by various parts of the kernel to convert - * between the three different kinds of node numbering. At least some - * of them may change to procedure calls in the future, but the macros - * will continue to work. Don't use the arrays above directly. - */ - -#define NASID_TO_REGION(nnode) \ - ((nnode) >> \ - (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT)) - -#ifndef __ia64 -extern cnodeid_t nasid_to_compact_node[MAX_NASIDS]; -extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES]; -extern cnodeid_t cpuid_to_compact_node[MAXCPUS]; - -#if !defined(DEBUG) - -#define NASID_TO_COMPACT_NODEID(nnode) (nasid_to_compact_node[nnode]) -#define COMPACT_TO_NASID_NODEID(cnode) (compact_to_nasid_node[cnode]) -#define CPUID_TO_COMPACT_NODEID(cpu) (cpuid_to_compact_node[(cpu)]) -#else - -/* - * These functions can do type checking and fail if they need to return - * a bad nodeid, but they're not as fast so just use 'em for debug kernels. - */ -cnodeid_t nasid_to_compact_nodeid(nasid_t nasid); -nasid_t compact_to_nasid_nodeid(cnodeid_t cnode); - -#define NASID_TO_COMPACT_NODEID(nnode) nasid_to_compact_nodeid(nnode) -#define COMPACT_TO_NASID_NODEID(cnode) compact_to_nasid_nodeid(cnode) -#define CPUID_TO_COMPACT_NODEID(cpu) (cpuid_to_compact_node[(cpu)]) -#endif - -#else - -/* - * IA64 specific nasid and cnode ids. - */ #define NASID_TO_COMPACT_NODEID(nasid) (nasid_to_cnodeid(nasid)) #define COMPACT_TO_NASID_NODEID(cnode) (cnodeid_to_nasid(cnode)) -#define CPUID_TO_COMPACT_NODEID(cpu) (cpuid_to_cnodeid(cpu)) -#endif /* #ifndef __ia64 */ -extern int node_getlastslot(cnodeid_t); +#define INVALID_NASID ((nasid_t)-1) +#define INVALID_CNODEID ((cnodeid_t)-1) +#define INVALID_PNODEID ((pnodeid_t)-1) +#define INVALID_MODULE ((moduleid_t)-1) +#define INVALID_PARTID ((partid_t)-1) -#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */ +extern cpuid_t cnodetocpu(cnodeid_t); +void sn_flush_all_caches(long addr, long bytes); -#define SLOT_BITMASK (MAX_MEM_SLOTS - 1) -#define SLOT_SIZE (1LL<<SLOT_SHIFT) +extern int is_fine_dirmode(void); -#define node_getnumslots(node) (MAX_MEM_SLOTS) -#define NODE_MAX_MEM_SIZE SLOT_SIZE * MAX_MEM_SLOTS -/* - * New stuff in here from Irix sys/pfdat.h. - */ -#define SLOT_PFNSHIFT (SLOT_SHIFT - PAGE_SHIFT) -#define PFN_NASIDSHFT (NASID_SHFT - PAGE_SHIFT) -#define mkpfn(nasid, off) (((pfn_t)(nasid) << PFN_NASIDSHFT) | (off)) -#define slot_getbasepfn(node,slot) \ - (mkpfn(COMPACT_TO_NASID_NODEID(node), slot<<SLOT_PFNSHIFT)) -#endif /* _ASM_SN_ARCH_H */ +#endif /* _ASM_IA64_SN_ARCH_H */ diff --git a/include/asm-ia64/sn/ate_utils.h b/include/asm-ia64/sn/ate_utils.h new file mode 100644 index 000000000000..9cba288cfd3c --- /dev/null +++ b/include/asm-ia64/sn/ate_utils.h @@ -0,0 +1,51 @@ +#ifndef _ASM_IA64_SN_ATE_UTILS_H +#define _ASM_IA64_SN_ATE_UTILS_H + +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + */ + +/* + * struct map X[] .m_size .m_addr + * --- ------------ ----------- + * [0] mapsize(X) unused + * # X[] unused + * [1] map lock * mapwant sv_t * + * map access wait for free map space + * + * mapstart(X)-> [2] # units unit number + * : : : + * [ ] 0 + */ + +#include <linux/types.h> + +#define ulong_t uint64_t + +struct map +{ + unsigned long m_size; /* number of units available */ + unsigned long m_addr; /* address of first available unit */ +}; + +#define mapstart(X) &X[2] /* start of map array */ + +#define mapsize(X) X[0].m_size /* number of empty slots */ + /* remaining in map array */ +#define maplock(X) (((spinlock_t *) X[1].m_size)) + +#define mapout(X) ((sv_t *) X[1].m_addr) + + +extern ulong_t atealloc(struct map *, size_t); +extern struct map *atemapalloc(ulong_t); +extern void atefree(struct map *, size_t, ulong_t); +extern void atemapfree(struct map *); + +#endif /* _ASM_IA64_SN_ATE_UTILS_H */ + diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h new file mode 100644 index 000000000000..3de9f909edac --- /dev/null +++ b/include/asm-ia64/sn/bte.h @@ -0,0 +1,88 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_SN_BTE_H +#define _ASM_IA64_SN_BTE_H + +#ident "$Revision: $" + +#include <linux/spinlock.h> +#include <linux/cache.h> +#include <asm/sn/io.h> + +#define L1_CACHE_MASK (L1_CACHE_BYTES - 1) /* Mask to retrieve + * the offset into this + * cache line.*/ + +/* BTE status register only supports 16 bits for length field */ +#define BTE_LEN_MASK ((1 << 16) - 1) + +/* + * Constants used in determining the best and worst case transfer + * times. To help explain the two, the following graph of transfer + * status vs time may help. + * + * active +------------------:-+ : + * status | : | : + * idle +__________________:_+======= + * 0 Time MaxT MinT + * + * Therefore, MaxT is the maximum thoeretical rate for transfering + * the request block (assuming ideal circumstances) + * + * MinT is the minimum theoretical rate for transferring the + * requested block (assuming maximum link distance and contention) + * + * The following defines are the inverse of the above. They are + * used for calculating the MaxT time and MinT time given the + * number of lines in the transfer. + */ +#define BTE_MAXT_LINES_PER_SECOND 800 +#define BTE_MINT_LINES_PER_SECOND 600 + + +/* Define hardware */ +#define BTES_PER_NODE 2 + +/* Define hardware modes */ +#define BTE_NOTIFY (IBCT_NOTIFY) +#define BTE_NORMAL BTE_NOTIFY +#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE) + +/* Use a reserved bit to let the caller specify a wait for any BTE */ +#define BTE_WACQUIRE (0x4000) + +/* + * Structure defining a bte. An instance of this + * structure is created in the nodepda for each + * bte on that node (as defined by BTES_PER_NODE) + * This structure contains everything necessary + * to work with a BTE. + */ +typedef struct bteinfo_s { + u64 volatile notify ____cacheline_aligned; + char *bte_base_addr ____cacheline_aligned; + spinlock_t spinlock; + u64 idealTransferTimeout; + u64 idealTransferTimeoutReached; + u64 mostRecentSrc; + u64 mostRecentDest; + u64 mostRecentLen; + u64 mostRecentMode; + u64 volatile *mostRecentNotification; +} bteinfo_t; + +/* Possible results from bte_copy and bte_unaligned_copy */ +typedef enum { + BTE_SUCCESS, /* 0 is success */ + BTEFAIL_NOTAVAIL, /* BTE not available */ + BTEFAIL_ERROR, /* Generic error */ + BTEFAIL_DIR /* Diretory error */ +} bte_result_t; + +#endif /* _ASM_IA64_SN_BTE_H */ diff --git a/include/asm-ia64/sn/bte_copy.h b/include/asm-ia64/sn/bte_copy.h new file mode 100644 index 000000000000..10c73231afbe --- /dev/null +++ b/include/asm-ia64/sn/bte_copy.h @@ -0,0 +1,311 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_SN_BTE_COPY_H +#define _ASM_IA64_SN_BTE_COPY_H + +#ident "$Revision: $" + +#include <asm/sn/bte.h> +#include <asm/sn/sgi.h> +#include <asm/sn/pda.h> +#include <asm/delay.h> + +/* + * BTE_LOCKING support - Undefining the following line will + * adapt the bte_copy code to support one bte per cpu in + * synchronous mode. Even if bte_copy is called with a + * notify address, the bte will spin and wait for the transfer + * to complete. By defining the following, spin_locks and + * busy checks are placed around the initiation of a BTE + * transfer and multiple bte's per cpu are supported. + */ +#define CONFIG_IA64_SGI_BTE_LOCKING 1 + +/* + * Some macros to simplify reading. + * + * Start with macros to locate the BTE control registers. + */ + +#define BTEREG_LNSTAT_ADDR (bte->bte_base_addr) +#define BTEREG_SOURCE_ADDR (bte->bte_base_addr + IIO_IBSA0 - IIO_IBLS0) +#define BTEREG_DEST_ADDR (bte->bte_base_addr + IIO_IBDA0 - IIO_IBLS0) +#define BTEREG_CTRL_ADDR (bte->bte_base_addr + IIO_IBCT0 - IIO_IBLS0) +#define BTEREG_NOTIF_ADDR (bte->bte_base_addr + IIO_IBNA0 - IIO_IBLS0) + +/* Some macros to force the IBCT0 value valid. */ + +#define BTE_VALID_MODES BTE_NOTIFY +#define BTE_VLD_MODE(x) (x & BTE_VALID_MODES) + +// #define DEBUG_BTE +// #define DEBUG_BTE_VERBOSE +// #define DEBUG_TIME_BTE + +#ifdef DEBUG_BTE +# define DPRINTK(x) printk x // Terse +# ifdef DEBUG_BTE_VERBOSE +# define DPRINTKV(x) printk x // Verbose +# else +# define DPRINTKV(x) +# endif +#else +# define DPRINTK(x) +# define DPRINTKV(x) +#endif + +#ifdef DEBUG_TIME_BTE +extern u64 BteSetupTime; +extern u64 BteTransferTime; +extern u64 BteTeardownTime; +extern u64 BteExecuteTime; +#endif + +/* + * bte_copy(src, dest, len, mode, notification) + * + * use the block transfer engine to move kernel + * memory from src to dest using the assigned mode. + * + * Paramaters: + * src - physical address of the transfer source. + * dest - physical address of the transfer destination. + * len - number of bytes to transfer from source to dest. + * mode - hardware defined. See reference information + * for IBCT0/1 in the SHUB Programmers Reference + * notification - kernel virtual address of the notification cache + * line. If NULL, the default is used and + * the bte_copy is synchronous. + * + * NOTE: This function requires src, dest, and len to + * be cache line aligned. + */ +extern __inline__ bte_result_t +bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification) +{ +#ifdef CONFIG_IA64_SGI_BTE_LOCKING + int bte_to_use; +#endif + +#ifdef DEBUG_TIME_BTE + u64 invokeTime = 0; + u64 completeTime = 0; + u64 xferStartTime = 0; + u64 xferCompleteTime = 0; +#endif + u64 transferSize; + bteinfo_t *bte; + +#ifdef DEBUG_TIME_BTE + invokeTime = ia64_get_itc(); +#endif + + DPRINTK(("bte_copy (0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)\n", + src, dest, len, mode, notification)); + + if (len == 0) { + return (BTE_SUCCESS); + } + + ASSERT(!((len & L1_CACHE_MASK) || + (src & L1_CACHE_MASK) || (dest & L1_CACHE_MASK))); + + ASSERT(len < ((BTE_LEN_MASK + 1) << L1_CACHE_SHIFT)); + +#ifdef CONFIG_IA64_SGI_BTE_LOCKING + { + bte_to_use = 0; + + /* Attempt to lock one of the BTE interfaces */ + while ((*pda.cpubte[bte_to_use]-> + mostRecentNotification & IBLS_BUSY) + && + (!(spin_trylock + (&(pda.cpubte[bte_to_use]->spinlock)))) + && (bte_to_use < BTES_PER_NODE)) { + bte_to_use++; + } + + if ((bte_to_use >= BTES_PER_NODE) && + !(mode & BTE_WACQUIRE)) { + return (BTEFAIL_NOTAVAIL); + } + + /* Wait until a bte is available. */ + } + while (bte_to_use >= BTES_PER_NODE); + + bte = pda.cpubte[bte_to_use]; + DPRINTKV(("Got a lock on bte %d\n", bte_to_use)); +#else + /* Assuming one BTE per CPU. */ + bte = pda.cpubte[0]; +#endif + + /* + * The following are removed for optimization but is + * available in the event that the SHUB exhibits + * notification problems similar to the hub, bedrock et al. + * + * bte->mostRecentSrc = src; + * bte->mostRecentDest = dest; + * bte->mostRecentLen = len; + * bte->mostRecentMode = mode; + */ + if (notification == NULL) { + /* User does not want to be notified. */ + bte->mostRecentNotification = &bte->notify; + } else { + bte->mostRecentNotification = notification; + } + + /* Calculate the number of cache lines to transfer. */ + transferSize = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK); + + DPRINTKV(("Calculated transfer size of %d cache lines\n", + transferSize)); + + /* Initialize the notification to a known value. */ + *bte->mostRecentNotification = -1L; + + + DPRINTKV(("Before, status is 0x%lx and notify is 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + *bte->mostRecentNotification)); + + /* Set the status reg busy bit and transfer length */ + DPRINTKV(("IBLS - HUB_S(0x%lx, 0x%lx)\n", + BTEREG_LNSTAT_ADDR, IBLS_BUSY | transferSize)); + HUB_S(BTEREG_LNSTAT_ADDR, IBLS_BUSY | transferSize); + + + DPRINTKV(("After setting status, status is 0x%lx and notify is 0x%lx\n", HUB_L(BTEREG_LNSTAT_ADDR), *bte->mostRecentNotification)); + + /* Set the source and destination registers */ + DPRINTKV(("IBSA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_SOURCE_ADDR, + src)); + HUB_S(BTEREG_SOURCE_ADDR, src); + DPRINTKV(("IBDA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_DEST_ADDR, dest)); + HUB_S(BTEREG_DEST_ADDR, dest); + + + /* Set the notification register */ + DPRINTKV(("IBNA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_NOTIF_ADDR, + __pa(bte->mostRecentNotification))); + HUB_S(BTEREG_NOTIF_ADDR, (__pa(bte->mostRecentNotification))); + + + DPRINTKV(("Set Notify, status is 0x%lx and notify is 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + *bte->mostRecentNotification)); + + /* Initiate the transfer */ + DPRINTKV(("IBCT - HUB_S(0x%lx, 0x%lx)\n", BTEREG_CTRL_ADDR, mode)); +#ifdef DEBUG_TIME_BTE + xferStartTime = ia64_get_itc(); +#endif + HUB_S(BTEREG_CTRL_ADDR, BTE_VLD_MODE(mode)); + + DPRINTKV(("Initiated, status is 0x%lx and notify is 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + *bte->mostRecentNotification)); + + // >>> Temporarily work around not getting a notification + // from medusa. + // *bte->mostRecentNotification = HUB_L(bte->bte_base_addr); + + if (notification == NULL) { + /* + * Calculate our timeout + * + * What are we doing here? We are trying to determine + * the fastest time the BTE could have transfered our + * block of data. By takine the clock frequency (ticks/sec) + * divided by the BTE MaxT Transfer Rate (lines/sec) + * times the transfer size (lines), we get a tick + * offset from current time that the transfer should + * complete. + * + * Why do this? We are watching for a notification + * failure from the BTE. This behaviour has been + * seen in the SN0 and SN1 hardware on rare circumstances + * and is expected in SN2. By checking at the + * ideal transfer timeout, we minimize our time + * delay from hardware completing our request and + * our detecting the failure. + */ + bte->idealTransferTimeout = jiffies + + (HZ / BTE_MAXT_LINES_PER_SECOND * transferSize); + + while ((IBLS_BUSY & bte->notify)) { + /* + * Notification Workaround: When the max + * theoretical time has elapsed, read the hub + * status register into the notification area. + * This fakes the shub performing the copy. + */ + if (jiffies > bte->idealTransferTimeout) { + bte->notify = HUB_L(bte->bte_base_addr); + bte->idealTransferTimeoutReached++; + bte->idealTransferTimeout = jiffies + + (HZ / BTE_MAXT_LINES_PER_SECOND * + (bte->notify & BTE_LEN_MASK)); + } + } +#ifdef DEBUG_TIME_BTE + xferCompleteTime = ia64_get_itc(); +#endif + if (bte->notify & IBLS_ERROR) { + /* >>> Need to do real error checking. */ + transferSize = 0; + +#ifdef CONFIG_IA64_SGI_BTE_LOCKING + spin_unlock(&(bte->spinlock)); +#endif + return (BTEFAIL_ERROR); + } + + } +#ifdef CONFIG_IA64_SGI_BTE_LOCKING + spin_unlock(&(bte->spinlock)); +#endif +#ifdef DEBUG_TIME_BTE + completeTime = ia64_get_itc(); + + BteSetupTime = xferStartTime - invokeTime; + BteTransferTime = xferCompleteTime - xferStartTime; + BteTeardownTime = completeTime - xferCompleteTime; + BteExecuteTime = completeTime - invokeTime; +#endif + return (BTE_SUCCESS); +} + +/* + * Define the bte_unaligned_copy as an extern. + */ +extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64, char *); + +/* + * The following is the prefered way of calling bte_unaligned_copy + * If the copy is fully cache line aligned, then bte_copy is + * used instead. Since bte_copy is inlined, this saves a call + * stack. NOTE: bte_copy is called synchronously and does block + * until the transfer is complete. In order to get the asynch + * version of bte_copy, you must perform this check yourself. + */ +#define BTE_UNALIGNED_COPY(src, dest, len, mode, bteBlock) \ + if ((len & L1_CACHE_MASK) || \ + (src & L1_CACHE_MASK) || \ + (dest & L1_CACHE_MASK)) { \ + bte_unaligned_copy (src, dest, len, mode, bteBlock); \ + } else { \ + bte_copy(src, dest, len, mode, NULL); \ + } + +#endif /* _ASM_IA64_SN_BTE_COPY_H */ diff --git a/include/asm-ia64/sn/cdl.h b/include/asm-ia64/sn/cdl.h index 469787461d1b..35c7f8ec37b2 100644 --- a/include/asm-ia64/sn/cdl.h +++ b/include/asm-ia64/sn/cdl.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_CDL_H -#define _ASM_SN_CDL_H +#ifndef _ASM_IA64_SN_CDL_H +#define _ASM_IA64_SN_CDL_H #include <asm/sn/sgi.h> @@ -193,4 +192,4 @@ void async_attach_signal_start(async_attach_t); void async_attach_signal_done(async_attach_t); void async_attach_waitall(async_attach_t); -#endif /* _ASM_SN_CDL_H */ +#endif /* _ASM_IA64_SN_CDL_H */ diff --git a/include/asm-ia64/sn/clksupport.h b/include/asm-ia64/sn/clksupport.h index 6a2d2c009a61..57a7fd97cd87 100644 --- a/include/asm-ia64/sn/clksupport.h +++ b/include/asm-ia64/sn/clksupport.h @@ -4,61 +4,60 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com) + * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. */ - -#ifndef _ASM_KSYS_CLKSUPPORT_H -#define _ASM_KSYS_CLKSUPPORT_H - -/* #include <sys/mips_addrspace.h> */ - -#if SN -#include <asm/sn/agent.h> -#include <asm/sn/intr_public.h> -typedef hubreg_t clkreg_t; -extern nasid_t master_nasid; - -#define GET_LOCAL_RTC (clkreg_t)LOCAL_HUB_L(PI_RT_COUNT) -#define DISABLE_TMO_INTR() if (cpuid_to_localslice(cpuid())) \ - REMOTE_HUB_PI_S(get_nasid(),\ - cputosubnode(cpuid()),\ - PI_RT_COMPARE_B, 0); \ - else \ - REMOTE_HUB_PI_S(get_nasid(),\ - cputosubnode(cpuid()),\ - PI_RT_COMPARE_A, 0); - -/* This is a hack; we really need to figure these values out dynamically */ -/* - * Since 800 ns works very well with various HUB frequencies, such as - * 360, 380, 390 and 400 MHZ, we use 800 ns rtc cycle time. - */ -#define NSEC_PER_CYCLE 800 -#define CYCLE_PER_SEC (NSEC_PER_SEC/NSEC_PER_CYCLE) /* - * Number of cycles per profiling intr + * This file contains definitions for accessing a platform supported high resolution + * clock. The clock is monitonically increasing and can be accessed from any node + * in the system. The clock is synchronized across nodes - all nodes see the + * same value. + * + * RTC_COUNTER_ADDR - contains the address of the counter + * + * GET_RTC_COUNTER() - macro to read the value of the clock + * + * RTC_CYCLES_PER_SEC - clock frequency in ticks per second + * */ -#define CLK_FCLOCK_FAST_FREQ 1250 -#define CLK_FCLOCK_SLOW_FREQ 0 -/* The is the address that the user will use to mmap the cycle counter */ -#define CLK_CYCLE_ADDRESS_FOR_USER LOCAL_HUB_ADDR(PI_RT_COUNT) -#elif IP30 -#include <sys/cpu.h> -typedef heartreg_t clkreg_t; -#define NSEC_PER_CYCLE 80 -#define CYCLE_PER_SEC (NSEC_PER_SEC/NSEC_PER_CYCLE) -#define GET_LOCAL_RTC *((volatile clkreg_t *)PHYS_TO_COMPATK1(HEART_COUNT)) -#define DISABLE_TMO_INTR() -#define CLK_CYCLE_ADDRESS_FOR_USER PHYS_TO_K1(HEART_COUNT) -#define CLK_FCLOCK_SLOW_FREQ (CYCLE_PER_SEC / HZ) +#ifndef _ASM_IA64_SN_CLKSUPPORT_H +#define _ASM_IA64_SN_CLKSUPPORT_H + +#include <linux/config.h> +#include <asm/sn/arch.h> +#include <asm/sn/addrs.h> + +typedef long clkreg_t; +extern long sn_rtc_cycles_per_second; + + +#if defined(CONFIG_IA64_SGI_SN1) +#include <asm/sn/sn1/bedrock.h> +#include <asm/sn/sn1/hubpi_next.h> +/* clocks are not synchronized yet on SN1 - used node 0 (problem if no NASID 0) */ +#define RTC_COUNTER_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COUNTER)) +#define RTC_COMPARE_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COMPARE_A)) +#define RTC_COMPARE_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COMPARE_B)) +#define RTC_INT_PENDING_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_PEND_A)) +#define RTC_INT_PENDING_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_PEND_B)) +#define RTC_INT_ENABLED_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_EN_A)) +#define RTC_INT_ENABLED_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_EN_B)) +#else +#include <asm/sn/sn2/shub_mmr.h> +#define RTC_COUNTER_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) +#define RTC_COMPARE_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) +#define RTC_COMPARE_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) +#define RTC_INT_PENDING_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) +#define RTC_INT_PENDING_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) +#define RTC_INT_ENABLED_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) +#define RTC_INT_ENABLED_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #endif -/* Prototypes */ -extern void init_timebase(void); -extern void fastick_maint(struct eframe_s *); -extern int audioclock; -extern int prfclk_enabled_cnt; -#endif /* _ASM_KSYS_CLKSUPPORT_H */ + +#define GET_RTC_COUNTER() (*RTC_COUNTER_ADDR) +#define rtc_time() GET_RTC_COUNTER() + +#define RTC_CYCLES_PER_SEC sn_rtc_cycles_per_second + +#endif /* _ASM_IA64_SN_CLKSUPPORT_H */ diff --git a/include/asm-ia64/sn/dmamap.h b/include/asm-ia64/sn/dmamap.h index 7aae769f8ac6..6f56cac7f86a 100644 --- a/include/asm-ia64/sn/dmamap.h +++ b/include/asm-ia64/sn/dmamap.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_DMAMAP_H -#define _ASM_SN_DMAMAP_H +#ifndef _ASM_IA64_SN_DMAMAP_H +#define _ASM_IA64_SN_DMAMAP_H #include <asm/sn/sv.h> @@ -70,7 +69,6 @@ extern struct map *a32map[]; extern int a24_mapsize; extern int a32_mapsize; -extern lock_t dmamaplock; extern sv_t dmamapout; #ifdef __cplusplus @@ -87,4 +85,4 @@ extern sv_t dmamapout; #define DMAMAP_FLAGS 0x7 -#endif /* _ASM_SN_DMAMAP_H */ +#endif /* _ASM_IA64_SN_DMAMAP_H */ diff --git a/include/asm-ia64/sn/driver.h b/include/asm-ia64/sn/driver.h index f71f4348b37c..17a76381d6b7 100644 --- a/include/asm-ia64/sn/driver.h +++ b/include/asm-ia64/sn/driver.h @@ -4,11 +4,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_DRIVER_H -#define _ASM_SN_DRIVER_H +#ifndef _ASM_IA64_SN_DRIVER_H +#define _ASM_IA64_SN_DRIVER_H + +#include <linux/devfs_fs_kernel.h> +#include <asm/types.h> /* ** Interface for device driver handle management. @@ -18,133 +20,77 @@ */ typedef struct device_driver_s *device_driver_t; -#define DEVICE_DRIVER_NONE (device_driver_t)NULL /* == Driver thread priority support == */ typedef int ilvl_t; -/* default driver thread priority level */ -#define DRIVER_THREAD_PRI_DEFAULT (ilvl_t)230 -/* invalid driver thread priority level */ -#define DRIVER_THREAD_PRI_INVALID (ilvl_t)-1 - -/* Associate a thread priority with a driver */ -extern int device_driver_thread_pri_set(device_driver_t driver, - ilvl_t pri); - -/* Get the thread priority associated with the driver */ -extern ilvl_t device_driver_thread_pri_get(device_driver_t driver); - -/* Get the thread priority for a driver from the sysgen paramters */ -extern ilvl_t device_driver_sysgen_thread_pri_get(char *driver_prefix); - -/* Initialize device driver functions. */ -extern void device_driver_init(void); - - -/* Allocate a driver handle */ -extern device_driver_t device_driver_alloc(char *prefix); +#ifdef __cplusplus +extern "C" { +#endif -/* Free a driver handle */ -extern void device_driver_free(device_driver_t driver); +struct eframe_s; +struct piomap; +struct dmamap; +typedef __psunsigned_t iobush_t; -/* Given a device driver prefix, return a handle to the driver. */ -extern device_driver_t device_driver_get(char *prefix); +/* interrupt function */ +typedef void *intr_arg_t; +typedef void intr_func_f(intr_arg_t); +typedef intr_func_f *intr_func_t; -/* Given a device, return a handle to the driver. */ -extern device_driver_t device_driver_getbydev(devfs_handle_t device); +#define INTR_ARG(n) ((intr_arg_t)(__psunsigned_t)(n)) -struct cdevsw; -struct bdevsw; +/* system interrupt resource handle -- returned from intr_alloc */ +typedef struct intr_s *intr_t; +#define INTR_HANDLE_NONE ((intr_t)0) -/* Associate a driver with bdevsw/cdevsw pointers. */ -extern int -device_driver_devsw_put(device_driver_t driver, - struct bdevsw *my_bdevsw, - struct cdevsw *my_cdevsw); - - -/* Given a driver, return the corresponding bdevsw and cdevsw pointers. */ -extern void -device_driver_devsw_get( device_driver_t driver, - struct bdevsw **bdevswp, - struct cdevsw **cdevswp); - -/* Given a driver, return its name (prefix). */ -extern void device_driver_name_get(device_driver_t driver, char *buffer, int length); +/* + * restore interrupt level value, returned from intr_block_level + * for use with intr_unblock_level. + */ +typedef void *rlvl_t; /* - * A descriptor for every static device driver in the system. - * lboot creates a table of these and places in in master.c. - * device_driver_init runs through this table during initialization - * in order to "register" every static device driver. + * A basic, platform-independent description of I/O requirements for + * a device. This structure is usually formed by lboot based on information + * in configuration files. It contains information about PIO, DMA, and + * interrupt requirements for a specific instance of a device. + * + * The pio description is currently unused. + * + * The dma description describes bandwidth characteristics and bandwidth + * allocation requirements. (TBD) + * + * The Interrupt information describes the priority of interrupt, desired + * destination, policy (TBD), whether this is an error interrupt, etc. + * For now, interrupts are targeted to specific CPUs. */ -typedef struct static_device_driver_desc_s { - char *sdd_prefix; - struct bdevsw *sdd_bdevsw; - struct cdevsw *sdd_cdevsw; -} *static_device_driver_desc_t; - -extern struct static_device_driver_desc_s static_device_driver_table[]; -extern int static_devsw_count; - - -/*====== administration support ========== */ -/* structure of each entry in the table created by lboot for - * device / driver administration -*/ -typedef struct dev_admin_info_s { - char *dai_name; /* name of the device or driver - * prefix - */ - char *dai_param_name; /* device or driver parameter name */ - char *dai_param_val; /* value of the parameter */ -} dev_admin_info_t; - -/* Update all the administrative hints associated with the device */ -extern void device_admin_info_update(devfs_handle_t dev_vhdl); +typedef struct device_desc_s { + /* pio description (currently none) */ -/* Update all the administrative hints associated with the device driver */ -extern void device_driver_admin_info_update(device_driver_t driver); + /* dma description */ + /* TBD: allocated badwidth requirements */ -/* Get a particular administrative hint associated with a device */ -extern char *device_admin_info_get(devfs_handle_t dev_vhdl, - char *info_lbl); + /* interrupt description */ + devfs_handle_t intr_target; /* Hardware locator string */ + int intr_policy; /* TBD */ + ilvl_t intr_swlevel; /* software level for blocking intr */ + char *intr_name; /* name of interrupt, if any */ -/* Associate a particular administrative hint for a device */ -extern int device_admin_info_set(devfs_handle_t dev_vhdl, - char *info_lbl, - char *info_val); + int flags; +} *device_desc_t; -/* Get a particular administrative hint associated with a device driver*/ -extern char *device_driver_admin_info_get(char *driver_prefix, - char *info_name); +/* flag values */ +#define D_INTR_ISERR 0x1 /* interrupt is for error handling */ +#define D_IS_ASSOC 0x2 /* descriptor is associated with a dev */ +#define D_INTR_NOTHREAD 0x4 /* Interrupt handler isn't threaded. */ -/* Associate a particular administrative hint for a device driver*/ -extern int device_driver_admin_info_set(char *driver_prefix, - char *driver_info_lbl, - char *driver_info_val); - -/* Initialize the extended device administrative hint table */ -extern void device_admin_table_init(void); - -/* Add a hint corresponding to a device to the extended device administrative - * hint table. - */ -extern void device_admin_table_update(char *dev_name, - char *param_name, - char *param_val); - -/* Initialize the extended device driver administrative hint table */ -extern void device_driver_admin_table_init(void); - -/* Add a hint corresponding to a device to the extended device driver - * administrative hint table. - */ -extern void device_driver_admin_table_update(char *drv_prefix, - char *param_name, - char *param_val); -#endif /* _ASM_SN_DRIVER_H */ +#define INTR_SWLEVEL_NOTHREAD_DEFAULT 0 /* Default + * Interrupt level in case of + * non-threaded interrupt + * handlers + */ +#endif /* _ASM_IA64_SN_DRIVER_H */ diff --git a/include/asm-ia64/sn/eeprom.h b/include/asm-ia64/sn/eeprom.h index 0a6812d91cef..bf481c64d0f9 100644 --- a/include/asm-ia64/sn/eeprom.h +++ b/include/asm-ia64/sn/eeprom.h @@ -6,11 +6,10 @@ * * Public interface for reading Atmel EEPROMs via L1 system controllers * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_EEPROM_H -#define _ASM_SN_EEPROM_H +#ifndef _ASM_IA64_SN_EEPROM_H +#define _ASM_IA64_SN_EEPROM_H #include <asm/sn/sgi.h> #include <asm/sn/vector.h> @@ -385,14 +384,8 @@ int is_iobrick( int nasid, int widget_num ); ( IO_BRICK, NASID_GET((r)), (v), 0 ) \ : nic_bridge_vertex_info((v), (r)) ) -#ifdef BRINGUP /* will we read mfg info from IOC3's that aren't - * part of IO7 cards, or aren't in I/O bricks? */ -#define IOC3_VERTEX_MFG_INFO(v, r, e) \ - eeprom_vertex_info_set( IO_IO7, NASID_GET((r)), (v), 0 ) -#endif /* BRINGUP */ - #define HUB_UID_GET(n,v,p) cbrick_uid_get((n),(p)) #define ROUTER_UID_GET(d,p) rbrick_uid_get(get_nasid(),(d),(p)) #define XBOW_UID_GET(n,p) iobrick_uid_get((n),(p)) -#endif /* _ASM_SN_EEPROM_H */ +#endif /* _ASM_IA64_SN_EEPROM_H */ diff --git a/include/asm-ia64/sn/fetchop.h b/include/asm-ia64/sn/fetchop.h new file mode 100644 index 000000000000..7d43ea29f85e --- /dev/null +++ b/include/asm-ia64/sn/fetchop.h @@ -0,0 +1,40 @@ +/* + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + */ + + +#ifndef _ASM_IA64_SN_FETCHOP_H +#define _ASM_IA64_SN_FETCHOP_H + +#define FETCHOP_BASENAME "sgi_fetchop" +#define FETCHOP_FULLNAME "/dev/sgi_fetchop" + + + +#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */ + +#define FETCHOP_LOAD 0 +#define FETCHOP_INCREMENT 8 +#define FETCHOP_DECREMENT 16 +#define FETCHOP_CLEAR 24 + +#define FETCHOP_STORE 0 +#define FETCHOP_AND 24 +#define FETCHOP_OR 32 + +#define FETCHOP_CLEAR_CACHE 56 + +#define FETCHOP_LOAD_OP(addr, op) ( \ + *(long *)((char*) (addr) + (op))) + +#define FETCHOP_STORE_OP(addr, op, x) ( \ + *(long *)((char*) (addr) + (op)) = \ + (long) (x)) + +#endif /* _ASM_IA64_SN_FETCHOP_H */ + diff --git a/include/asm-ia64/sn/gda.h b/include/asm-ia64/sn/gda.h index 241c295a29b6..d57b89a7e880 100644 --- a/include/asm-ia64/sn/gda.h +++ b/include/asm-ia64/sn/gda.h @@ -6,16 +6,17 @@ * * Derived from IRIX <sys/SN/gda.h>. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. * * gda.h -- Contains the data structure for the global data area, * The GDA contains information communicated between the * PROM, SYMMON, and the kernel. */ -#ifndef _ASM_SN_GDA_H -#define _ASM_SN_GDA_H +#ifndef _ASM_IA64_SN_GDA_H +#define _ASM_IA64_SN_GDA_H #include <asm/sn/addrs.h> +#include <asm/sn/sn_cpuid.h> #define GDA_MAGIC 0x58464552 @@ -42,7 +43,7 @@ #define G_PARTIDOFF 40 #define G_TABLEOFF 128 -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ typedef struct gda { u32 g_magic; /* GDA magic number */ @@ -68,7 +69,7 @@ typedef struct gda { #define GDA ((gda_t*) GDA_ADDR(get_nasid())) -#endif /* __LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /* * Define: PART_GDA_VERSION * Purpose: Define the minimum version of the GDA required, lower @@ -105,4 +106,4 @@ typedef struct gda { #define PROMOP_BIST1 0x0800 /* keep track of which BIST ran */ #define PROMOP_BIST2 0x1000 /* keep track of which BIST ran */ -#endif /* _ASM_SN_GDA_H */ +#endif /* _ASM_IA64_SN_GDA_H */ diff --git a/include/asm-ia64/sn/hack.h b/include/asm-ia64/sn/hack.h index 2bc7b3e1241d..6632872c9b22 100644 --- a/include/asm-ia64/sn/hack.h +++ b/include/asm-ia64/sn/hack.h @@ -4,13 +4,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com) + * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_HACK_H -#define _ASM_SN_HACK_H +#ifndef _ASM_IA64_SN_HACK_H +#define _ASM_IA64_SN_HACK_H #include <asm/sn/types.h> #include <asm/uaccess.h> /* for copy_??_user */ @@ -32,7 +31,6 @@ struct cred { int x; }; #include <linux/devfs_fs_kernel.h> #define DELAY(a) -#define cpuid() 0 /************************************************ * Routines redefined to use linux equivalents. * @@ -59,14 +57,14 @@ typedef int (*splfunc_t)(void); #define spl7 splhi() #define splx(s) -extern void * kmem_alloc_node(register size_t, register int, cnodeid_t); -extern void * kmem_zalloc(size_t, int); -extern void * kmem_zalloc_node(register size_t, register int, cnodeid_t ); -extern void * kmem_zone_alloc(register zone_t *, int); -extern zone_t * kmem_zone_init(register int , char *); -extern void kmem_zone_free(register zone_t *, void *); +extern void * snia_kmem_alloc_node(register size_t, register int, cnodeid_t); +extern void * snia_kmem_zalloc(size_t, int); +extern void * snia_kmem_zalloc_node(register size_t, register int, cnodeid_t ); +extern void * snia_kmem_zone_alloc(register zone_t *, int); +extern zone_t * snia_kmem_zone_init(register int , char *); +extern void snia_kmem_zone_free(register zone_t *, void *); extern int is_specified(char *); extern int cap_able(uint64_t); extern int compare_and_swap_ptr(void **, void *, void *); -#endif /* _ASM_SN_HACK_H */ +#endif /* _ASM_IA64_SN_HACK_H */ diff --git a/include/asm-ia64/sn/hcl.h b/include/asm-ia64/sn/hcl.h index 3aeb2f9a1f76..2c91163420d2 100644 --- a/include/asm-ia64/sn/hcl.h +++ b/include/asm-ia64/sn/hcl.h @@ -4,13 +4,15 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_HCL_H -#define _ASM_SN_HCL_H +#ifndef _ASM_IA64_SN_HCL_H +#define _ASM_IA64_SN_HCL_H + +#include <asm/sn/sgi.h> +#include <asm/sn/invent.h> +#include <linux/devfs_fs_kernel.h> -extern spinlock_t hcl_spinlock; extern devfs_handle_t hcl_handle; /* HCL driver */ extern devfs_handle_t hwgraph_root; extern devfs_handle_t linux_busnum; @@ -93,7 +95,6 @@ extern devfs_handle_t hwgraph_block_device_get(devfs_handle_t); extern devfs_handle_t hwgraph_char_device_get(devfs_handle_t); extern graph_error_t hwgraph_char_device_add(devfs_handle_t, char *, char *, devfs_handle_t *); extern int hwgraph_path_add(devfs_handle_t, char *, devfs_handle_t *); -extern struct file_operations * hwgraph_bdevsw_get(devfs_handle_t); extern int hwgraph_info_add_LBL(devfs_handle_t, char *, arbitrary_info_t); extern int hwgraph_info_get_LBL(devfs_handle_t, char *, arbitrary_info_t *); extern int hwgraph_info_replace_LBL(devfs_handle_t, char *, arbitrary_info_t, @@ -111,4 +112,4 @@ extern graph_error_t hwgraph_vertex_unref(devfs_handle_t); -#endif /* _ASM_SN_HCL_H */ +#endif /* _ASM_IA64_SN_HCL_H */ diff --git a/include/asm-ia64/sn/hcl_util.h b/include/asm-ia64/sn/hcl_util.h index 2c7794d2fcc6..781b4ccbec0e 100644 --- a/include/asm-ia64/sn/hcl_util.h +++ b/include/asm-ia64/sn/hcl_util.h @@ -4,12 +4,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_HCL_UTIL_H -#define _ASM_SN_HCL_UTIL_H +#ifndef _ASM_IA64_SN_HCL_UTIL_H +#define _ASM_IA64_SN_HCL_UTIL_H + +#include <linux/devfs_fs_kernel.h> extern char * dev_to_name(devfs_handle_t, char *, uint); extern int device_master_set(devfs_handle_t, devfs_handle_t); @@ -17,8 +18,5 @@ extern devfs_handle_t device_master_get(devfs_handle_t); extern cnodeid_t master_node_get(devfs_handle_t); extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t); extern void mark_nodevertex_as_node(devfs_handle_t, cnodeid_t); -extern void device_info_set(devfs_handle_t, void *); -extern void *device_info_get(devfs_handle_t); - -#endif _ASM_SN_HCL_UTIL_H +#endif /* _ASM_IA64_SN_HCL_UTIL_H */ diff --git a/include/asm-ia64/sn/hires_clock.h b/include/asm-ia64/sn/hires_clock.h new file mode 100644 index 000000000000..d85f8547bbd1 --- /dev/null +++ b/include/asm-ia64/sn/hires_clock.h @@ -0,0 +1,52 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved. + * + * SGI Hi Resolution Clock + * + * SGI SN platforms provide a high resolution clock that is + * synchronized across all nodes. The clock can be memory mapped + * and directly read from user space. + * + * Access to the clock is thru the following: + * (error checking not shown) + * + * (Note: should library routines be provided to encapsulate this??) + * + * int fd: + * volatile long *clk; + * + * fd = open (HIRES_FULLNAME, O_RDONLY); + * clk = mmap(0, getpagesize(), PROT_READ, MAP_SHARED, fd, 0); + * clk += ioctl(fd, HIRES_IOCQGETOFFSET, 0); + * + * At this point, clk is a pointer to the high resolution clock. + * + * The clock period can be obtained via: + * + * long picosec_per_tick; + * picosec_per_tick = ioctl(fd, HIRES_IOCQGETPICOSEC, 0); + */ + +#ifndef _ASM_IA64_SN_HIRES_CLOCK_H +#define _ASM_IA64_SN_HIRES_CLOCK_H + + +#define HIRES_BASENAME "sgi_hires_clock" +#define HIRES_FULLNAME "/dev/sgi_hires_clock" +#define HIRES_IOC_BASE 's' + + +/* Get page offset of hires timer */ +#define HIRES_IOCQGETOFFSET _IO( HIRES_IOC_BASE, 0 ) + +/* get clock period in picoseconds per tick */ +#define HIRES_IOCQGETPICOSEC _IO( HIRES_IOC_BASE, 1 ) + +/* get number of significant bits in clock counter */ +#define HIRES_IOCQGETCLOCKBITS _IO( HIRES_IOC_BASE, 2 ) + +#endif /* _ASM_IA64_SN_HIRES_CLOCK_H */ diff --git a/include/asm-ia64/sn/idle.h b/include/asm-ia64/sn/idle.h new file mode 100644 index 000000000000..cc0c84d36869 --- /dev/null +++ b/include/asm-ia64/sn/idle.h @@ -0,0 +1,54 @@ +#ifndef _ASM_IA64_SN_IDLE_H +#define _ASM_IA64_SN_IDLE_H + +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + */ + +#include <linux/config.h> +#include <asm/sn/leds.h> +#include <asm/sn/simulator.h> + +static __inline__ void +snidle(void) { + +#ifdef CONFIG_IA64_SGI_AUTOTEST + { + extern int autotest_enabled; + if (autotest_enabled) { + extern void llsc_main(int, long, long); + llsc_main(smp_processor_id(), 0xe000000000000000LL, 0xe000000001000000LL); + } + } +#endif + + if (pda.idle_flag == 0) { + /* + * Turn the activity LED off. + */ + set_led_bits(0, LED_CPU_ACTIVITY); + } + +#ifdef CONFIG_IA64_SGI_SN_SIM + if (IS_RUNNING_ON_SIMULATOR()) + SIMULATOR_SLEEP(); +#endif + + pda.idle_flag = 1; +} + +static __inline__ void +snidleoff(void) { + /* + * Turn the activity LED on. + */ + set_led_bits(LED_CPU_ACTIVITY, LED_CPU_ACTIVITY); + + pda.idle_flag = 0; +} + +#endif /* _ASM_IA64_SN_IDLE_H */ diff --git a/include/asm-ia64/sn/ifconfig_net.h b/include/asm-ia64/sn/ifconfig_net.h new file mode 100644 index 000000000000..8eb976c35fd9 --- /dev/null +++ b/include/asm-ia64/sn/ifconfig_net.h @@ -0,0 +1,32 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_SN_IFCONFIG_NET_H +#define _ASM_IA64_SN_IFCONFIG_NET_H + +#define NETCONFIG_FILE "/tmp/ifconfig_net" +#define POUND_CHAR '#' +#define MAX_LINE_LEN 128 +#define MAXPATHLEN 128 + +struct ifname_num { + long next_eth; + long next_fddi; + long next_hip; + long next_tr; + long next_fc; + long size; +}; + +struct ifname_MAC { + char name[16]; + unsigned char dev_addr[7]; + unsigned char addr_len; /* hardware address length */ +}; + +#endif /* _ASM_IA64_SN_IFCONFIG_NET_H */ diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h index 19cc2c457033..89fe0da603d9 100644 --- a/include/asm-ia64/sn/intr.h +++ b/include/asm-ia64/sn/intr.h @@ -4,250 +4,17 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_INTR_H -#define _ASM_SN_INTR_H - -/* Subnode wildcard */ -#define SUBNODE_ANY -1 - -/* Number of interrupt levels associated with each interrupt register. */ -#define N_INTPEND_BITS 64 - -#define INT_PEND0_BASELVL 0 -#define INT_PEND1_BASELVL 64 - -#define N_INTPENDJUNK_BITS 8 -#define INTPENDJUNK_CLRBIT 0x80 +#ifndef _ASM_IA64_SN_INTR_H +#define _ASM_IA64_SN_INTR_H #include <linux/config.h> -#include <asm/sn/intr_public.h> - -#if LANGUAGE_C - -#define II_NAMELEN 24 - -/* - * Dispatch table entry - contains information needed to call an interrupt - * routine. - */ -typedef struct intr_vector_s { - intr_func_t iv_func; /* Interrupt handler function */ - intr_func_t iv_prefunc; /* Interrupt handler prologue func */ - void *iv_arg; /* Argument to pass to handler */ -#ifdef LATER - thd_int_t iv_tinfo; /* Thread info */ -#endif - cpuid_t iv_mustruncpu; /* Where we must run. */ -} intr_vector_t; - -/* Interrupt information table. */ -typedef struct intr_info_s { - xtalk_intr_setfunc_t ii_setfunc; /* Function to set the interrupt - * destination and level register. - * It returns 0 (success) or an - * error code. - */ - void *ii_cookie; /* arg passed to setfunc */ - devfs_handle_t ii_owner_dev; /* device that owns this intr */ - char ii_name[II_NAMELEN]; /* Name of this intr. */ - int ii_flags; /* informational flags */ -} intr_info_t; - -#define iv_tflags iv_tinfo.thd_flags -#define iv_isync iv_tinfo.thd_isync -#define iv_lat iv_tinfo.thd_latstats -#define iv_thread iv_tinfo.thd_ithread -#define iv_pri iv_tinfo.thd_pri - -#define THD_CREATED 0x00000001 /* - * We've created a thread for this - * interrupt. - */ - -/* - * Bits for ii_flags: - */ -#define II_UNRESERVE 0 -#define II_RESERVE 1 /* Interrupt reserved. */ -#define II_INUSE 2 /* Interrupt connected */ -#define II_ERRORINT 4 /* INterrupt is an error condition */ -#define II_THREADED 8 /* Interrupt handler is threaded. */ - -/* - * Interrupt level wildcard - */ -#define INTRCONNECT_ANYBIT -1 - -/* - * This structure holds information needed both to call and to maintain - * interrupts. The two are in separate arrays for the locality benefits. - * Since there's only one set of vectors per hub chip (but more than one - * CPU, the lock to change the vector tables must be here rather than in - * the PDA. - */ - -typedef struct intr_vecblk_s { - intr_vector_t vectors[N_INTPEND_BITS]; /* information needed to - call an intr routine. */ - intr_info_t info[N_INTPEND_BITS]; /* information needed only - to maintain interrupts. */ - spinlock_t vector_lock; /* Lock for this and the - masks in the PDA. */ - splfunc_t vector_spl; /* vector_lock req'd spl */ - int vector_state; /* Initialized to zero. - Set to INTR_INITED - by hubintr_init. - */ - int vector_count; /* Number of vectors - * reserved. - */ - int cpu_count[CPUS_PER_SUBNODE]; /* How many interrupts are - * connected to each CPU - */ - int ithreads_enabled; /* Are interrupt threads - * initialized on this node. - * and block? - */ -} intr_vecblk_t; - -/* Possible values for vector_state: */ -#define VECTOR_UNINITED 0 -#define VECTOR_INITED 1 -#define VECTOR_SET 2 - -#define hub_intrvect0 private.p_intmasks.dispatch0->vectors -#define hub_intrvect1 private.p_intmasks.dispatch1->vectors -#define hub_intrinfo0 private.p_intmasks.dispatch0->info -#define hub_intrinfo1 private.p_intmasks.dispatch1->info - -/* - * Macros to manipulate the interrupt register on the calling hub chip. - */ - -#define LOCAL_HUB_SEND_INTR(_level) LOCAL_HUB_S(PI_INT_PEND_MOD, \ - (0x100|(_level))) -#define REMOTE_HUB_PI_SEND_INTR(_hub, _sn, _level) \ - REMOTE_HUB_PI_S((_hub), _sn, PI_INT_PEND_MOD, (0x100|(_level))) - -#define REMOTE_CPU_SEND_INTR(_cpuid, _level) \ - REMOTE_HUB_PI_S(cputonasid(_cpuid), \ - SUBNODE(cputoslice(_cpuid)), \ - PI_INT_PEND_MOD, (0x100|(_level))) - -/* - * When clearing the interrupt, make sure this clear does make it - * to the hub. Otherwise we could end up losing interrupts. - * We do an uncached load of the int_pend0 register to ensure this. - */ - -#define LOCAL_HUB_CLR_INTR(_level) \ - LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)), \ - LOCAL_HUB_L(PI_INT_PEND0) -#define REMOTE_HUB_PI_CLR_INTR(_hub, _sn, _level) \ - REMOTE_HUB_PI_S((_hub), (_sn), PI_INT_PEND_MOD, (_level)), \ - REMOTE_HUB_PI_L((_hub), (_sn), PI_INT_PEND0) - -/* Special support for use by gfx driver only. Supports special gfx hub interrupt. */ -extern void install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg); - -void setrtvector(intr_func_t func); - -/* - * Interrupt blocking - */ -extern void intr_block_bit(cpuid_t cpu, int bit); -extern void intr_unblock_bit(cpuid_t cpu, int bit); - -#endif /* LANGUAGE_C */ - -/* - * Hard-coded interrupt levels: - */ - -/* - * L0 = SW1 - * L1 = SW2 - * L2 = INT_PEND0 - * L3 = INT_PEND1 - * L4 = RTC - * L5 = Profiling Timer - * L6 = Hub Errors - * L7 = Count/Compare (T5 counters) - */ - - -/* INT_PEND0 hard-coded bits. */ -#ifdef DEBUG_INTR_TSTAMP -/* hard coded interrupt level for interrupt latency test interrupt */ -#define CPU_INTRLAT_B 62 -#define CPU_INTRLAT_A 61 -#endif - -/* Hardcoded bits required by software. */ -#define MSC_MESG_INTR 9 -#define CPU_ACTION_B 8 -#define CPU_ACTION_A 7 - -/* These are determined by hardware: */ -#define CC_PEND_B 6 -#define CC_PEND_A 5 -#define UART_INTR 4 -#define PG_MIG_INTR 3 -#define GFX_INTR_B 2 -#define GFX_INTR_A 1 -#define RESERVED_INTR 0 - -/* INT_PEND1 hard-coded bits: */ -#define MSC_PANIC_INTR 63 -#define NI_ERROR_INTR 62 -#define MD_COR_ERR_INTR 61 -#define COR_ERR_INTR_B 60 -#define COR_ERR_INTR_A 59 -#define CLK_ERR_INTR 58 - -#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC -# define NACK_INT_B 57 -# define NACK_INT_A 56 -# define LB_ERROR 55 -# define XB_ERROR 54 -#else - << BOMB! >> Must define IP27 or IP35 or IP37 -#endif - -#define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch Bridge Errors */ - -#define IP27_INTR_0 52 /* Reserved for PROM use */ -#define IP27_INTR_1 51 /* (do not use in Kernel) */ -#define IP27_INTR_2 50 -#define IP27_INTR_3 49 -#define IP27_INTR_4 48 -#define IP27_INTR_5 47 -#define IP27_INTR_6 46 -#define IP27_INTR_7 45 - -#define TLB_INTR_B 44 /* used for tlb flush random */ -#define TLB_INTR_A 43 - -#define LLP_PFAIL_INTR_B 42 /* see ml/SN/SN0/sysctlr.c */ -#define LLP_PFAIL_INTR_A 41 - -#define NI_BRDCAST_ERR_B 40 -#define NI_BRDCAST_ERR_A 39 - -#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC -# define IO_ERROR_INTR 38 /* set up by prom */ -# define DEBUG_INTR_B 37 /* used by symmon to stop all cpus */ -# define DEBUG_INTR_A 36 -#endif -#ifdef CONFIG_IA64_SGI_SN1 -// These aren't strictly accurate or complete. See the -// Synergy Spec. for details. -#define SGI_UART_IRQ (65) -#define SGI_HUB_ERROR_IRQ (182) +#if defined(CONFIG_IA64_SGI_SN1) +#include <asm/sn/sn1/intr.h> +#elif defined(CONFIG_IA64_SGI_SN2) +#include <asm/sn/sn2/intr.h> #endif -#endif /* _ASM_SN_INTR_H */ +#endif /* _ASM_IA64_SN_INTR_H */ diff --git a/include/asm-ia64/sn/intr_public.h b/include/asm-ia64/sn/intr_public.h index 2cc3fba3149e..44367a4580cf 100644 --- a/include/asm-ia64/sn/intr_public.h +++ b/include/asm-ia64/sn/intr_public.h @@ -4,56 +4,16 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_INTR_PUBLIC_H__ -#define _ASM_SN_INTR_PUBLIC_H__ +#ifndef _ASM_IA64_SN_INTR_PUBLIC_H +#define _ASM_IA64_SN_INTR_PUBLIC_H #include <linux/config.h> -/* REMEMBER: If you change these, the whole world needs to be recompiled. - * It would also require changing the hubspl.s code and SN0/intr.c - * Currently, the spl code has no support for multiple INTPEND1 masks. - */ - -#define N_INTPEND0_MASKS 1 -#define N_INTPEND1_MASKS 1 - -#define INTPEND0_MAXMASK (N_INTPEND0_MASKS - 1) -#define INTPEND1_MAXMASK (N_INTPEND1_MASKS - 1) - -#if _LANGUAGE_C -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -#include <asm/sn/sn1/arch.h> +#if defined(CONFIG_IA64_SGI_SN1) +#include <asm/sn/sn1/intr_public.h> +#elif defined(CONFIG_IA64_SGI_SN2) #endif -#include <asm/sn/arch.h> - -struct intr_vecblk_s; /* defined in asm/sn/intr.h */ - -/* - * The following are necessary to create the illusion of a CEL - * on the IP27 hub. We'll add more priority levels soon, but for - * now, any interrupt in a particular band effectively does an spl. - * These must be in the PDA since they're different for each processor. - * Users of this structure must hold the vector_lock in the appropriate vector - * block before modifying the mask arrays. There's only one vector block - * for each Hub so a lock in the PDA wouldn't be adequate. - */ -typedef struct hub_intmasks_s { - /* - * The masks are stored with the lowest-priority (most inclusive) - * in the lowest-numbered masks (i.e., 0, 1, 2...). - */ - /* INT_PEND0: */ - hubreg_t intpend0_masks[N_INTPEND0_MASKS]; - /* INT_PEND1: */ - hubreg_t intpend1_masks[N_INTPEND1_MASKS]; - /* INT_PEND0: */ - struct intr_vecblk_s *dispatch0; - /* INT_PEND1: */ - struct intr_vecblk_s *dispatch1; -} hub_intmasks_t; -#endif /* _LANGUAGE_C */ -#endif /* _ASM_SN_INTR_PUBLIC_H__ */ +#endif /* _ASM_IA64_SN_INTR_PUBLIC_H */ diff --git a/include/asm-ia64/sn/invent.h b/include/asm-ia64/sn/invent.h index 6dbe43ac210c..e75c156d843b 100644 --- a/include/asm-ia64/sn/invent.h +++ b/include/asm-ia64/sn/invent.h @@ -4,11 +4,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_INVENT_H -#define _ASM_SN_INVENT_H +#ifndef _ASM_IA64_SN_INVENT_H +#define _ASM_IA64_SN_INVENT_H + +#include <linux/types.h> +#include <linux/devfs_fs_kernel.h> /* * sys/sn/invent.h -- Kernel Hardware Inventory @@ -743,4 +745,4 @@ extern void device_controller_num_set( devfs_handle_t, int); extern int device_controller_num_get( devfs_handle_t); #endif /* __KERNEL__ */ -#endif /* _ASM_SN_INVENT_H */ +#endif /* _ASM_IA64_SN_INVENT_H */ diff --git a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h index c9bffd085c0c..9f8b1e6c8ffe 100644 --- a/include/asm-ia64/sn/io.h +++ b/include/asm-ia64/sn/io.h @@ -1,21 +1,17 @@ - -/* $Id: io.h,v 1.2 2000/02/02 16:35:57 ralf Exp $ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2000 Ralf Baechle - * Copyright (C) 2000 Silicon Graphics, Inc. + * Copyright (C) 2000-2001 Silicon Graphics, Inc. */ -#ifndef _ASM_SN_IO_H -#define _ASM_SN_IO_H +#ifndef _ASM_IA64_SN_IO_H +#define _ASM_IA64_SN_IO_H #include <linux/config.h> -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -#include <asm/sn/sn1/addrs.h> -#endif +#include <asm/sn/addrs.h> /* Because we only have PCI I/O ports. */ #define IIO_ITTE_BASE 0x400160 /* base of translation table entries */ @@ -51,17 +47,35 @@ #define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin)) /* - * Macro which takes the widget number, and returns the + * Macro which takes the widget number, and returns the * IO PRB address of that widget. - * value _x is expected to be a widget number in the range + * value _x is expected to be a widget number in the range * 0, 8 - 0xF */ #define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ (_x) : \ (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) +#if defined(CONFIG_IA64_SGI_SN1) +#include <asm/sn/sn1/bedrock.h> #include <asm/sn/sn1/hubio.h> +#include <asm/sn/sn1/hubio_next.h> +#include <asm/sn/sn1/hubmd.h> +#include <asm/sn/sn1/hubmd_next.h> +#include <asm/sn/sn1/hubpi.h> +#include <asm/sn/sn1/hubpi_next.h> +#include <asm/sn/sn1/hublb.h> +#include <asm/sn/sn1/hublb_next.h> +#include <asm/sn/sn1/hubni.h> +#include <asm/sn/sn1/hubni_next.h> +#include <asm/sn/sn1/hubxb.h> +#include <asm/sn/sn1/hubxb_next.h> +#include <asm/sn/sn1/hubstat.h> +#include <asm/sn/sn1/hubdev.h> +#include <asm/sn/sn1/synergy.h> +#elif defined(CONFIG_IA64_SGI_SN2) +#include <asm/sn/sn2/shub.h> +#include <asm/sn/sn2/shubio.h> #endif -#endif /* _ASM_SN_IO_H */ +#endif /* _ASM_IA64_SN_IO_H */ diff --git a/include/asm-ia64/sn/iobus.h b/include/asm-ia64/sn/iobus.h deleted file mode 100644 index d710578ccefd..000000000000 --- a/include/asm-ia64/sn/iobus.h +++ /dev/null @@ -1,185 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam - */ -#ifndef _ASM_SN_IOBUS_H -#define _ASM_SN_IOBUS_H - -#ifdef __cplusplus -extern "C" { -#endif - -struct eframe_s; -struct piomap; -struct dmamap; - - -/* for ilvl_t interrupt level, for use with intr_block_level. Can't - * typedef twice without causing warnings, and some users of this header - * file do not already include driver.h, but expect ilvl_t to be defined, - * while others include both, leading to the warning ... - */ - -#include <asm/types.h> -#include <asm/sn/driver.h> - - -typedef __psunsigned_t iobush_t; - -#if __KERNEL__ -/* adapter handle */ -typedef devfs_handle_t adap_t; -#endif - - -/* interrupt function */ -typedef void *intr_arg_t; -typedef void intr_func_f(intr_arg_t); -typedef intr_func_f *intr_func_t; - -#define INTR_ARG(n) ((intr_arg_t)(__psunsigned_t)(n)) - -/* system interrupt resource handle -- returned from intr_alloc */ -typedef struct intr_s *intr_t; -#define INTR_HANDLE_NONE ((intr_t)0) - -/* - * restore interrupt level value, returned from intr_block_level - * for use with intr_unblock_level. - */ -typedef void *rlvl_t; - - -/* - * A basic, platform-independent description of I/O requirements for - * a device. This structure is usually formed by lboot based on information - * in configuration files. It contains information about PIO, DMA, and - * interrupt requirements for a specific instance of a device. - * - * The pio description is currently unused. - * - * The dma description describes bandwidth characteristics and bandwidth - * allocation requirements. (TBD) - * - * The Interrupt information describes the priority of interrupt, desired - * destination, policy (TBD), whether this is an error interrupt, etc. - * For now, interrupts are targeted to specific CPUs. - */ - -typedef struct device_desc_s { - /* pio description (currently none) */ - - /* dma description */ - /* TBD: allocated badwidth requirements */ - - /* interrupt description */ - devfs_handle_t intr_target; /* Hardware locator string */ - int intr_policy; /* TBD */ - ilvl_t intr_swlevel; /* software level for blocking intr */ - char *intr_name; /* name of interrupt, if any */ - - int flags; -} *device_desc_t; - -/* flag values */ -#define D_INTR_ISERR 0x1 /* interrupt is for error handling */ -#define D_IS_ASSOC 0x2 /* descriptor is associated with a dev */ -#define D_INTR_NOTHREAD 0x4 /* Interrupt handler isn't threaded. */ - -#define INTR_SWLEVEL_NOTHREAD_DEFAULT 0 /* Default - * Interrupt level in case of - * non-threaded interrupt - * handlers - */ -/* - * Drivers use these interfaces to manage device descriptors. - * - * To examine defaults: - * desc = device_desc_default_get(dev); - * device_desc_*_get(desc); - * - * To modify defaults: - * desc = device_desc_default_get(dev); - * device_desc_*_set(desc); - * - * To eliminate defaults: - * device_desc_default_set(dev, NULL); - * - * To override defaults: - * desc = device_desc_dup(dev); - * device_desc_*_set(desc,...); - * use device_desc in calls - * device_desc_free(desc); - * - * Software must not set or eliminate default device descriptors for a device while - * concurrently get'ing, dup'ing or using them. Default device descriptors can be - * changed only for a device that is quiescent. In general, device drivers have no - * need to permanently change defaults anyway -- they just override defaults, when - * necessary. - */ -extern device_desc_t device_desc_dup(devfs_handle_t dev); -extern void device_desc_free(device_desc_t device_desc); -extern device_desc_t device_desc_default_get(devfs_handle_t dev); -extern void device_desc_default_set(devfs_handle_t dev, device_desc_t device_desc); - -extern devfs_handle_t device_desc_intr_target_get(device_desc_t device_desc); -extern int device_desc_intr_policy_get(device_desc_t device_desc); -extern ilvl_t device_desc_intr_swlevel_get(device_desc_t device_desc); -extern char * device_desc_intr_name_get(device_desc_t device_desc); -extern int device_desc_flags_get(device_desc_t device_desc); - -extern void device_desc_intr_target_set(device_desc_t device_desc, devfs_handle_t target); -extern void device_desc_intr_policy_set(device_desc_t device_desc, int policy); -extern void device_desc_intr_swlevel_set(device_desc_t device_desc, ilvl_t swlevel); -extern void device_desc_intr_name_set(device_desc_t device_desc, char *name); -extern void device_desc_flags_set(device_desc_t device_desc, int flags); - - -/* IO state */ -#ifdef COMMENT -#define IO_STATE_EMPTY 0x01 /* non-existent */ -#define IO_STATE_INITIALIZING 0x02 /* being initialized */ -#define IO_STATE_ATTACHING 0x04 /* becoming active */ -#define IO_STATE_ACTIVE 0x08 /* active */ -#define IO_STATE_DETACHING 0x10 /* becoming inactive */ -#define IO_STATE_INACTIVE 0x20 /* not in use */ -#define IO_STATE_ERROR 0x40 /* problems */ -#define IO_STATE_BAD_HARDWARE 0x80 /* broken hardware */ -#endif - -struct edt; - - -/* return codes */ -#define RC_OK 0 -#define RC_ERROR 1 - -/* bus configuration management op code */ -#define IOBUS_CONFIG_ATTACH 0 /* vary on */ -#define IOBUS_CONFIG_DETACH 1 /* vary off */ -#define IOBUS_CONFIG_RECOVER 2 /* clear error then vary on */ - -/* get low-level PIO handle */ -extern int pio_geth(struct piomap*, int bus, int bus_id, int subtype, - iopaddr_t addr, int size); - -/* get low-level DMA handle */ -extern int dma_geth(struct dmamap*, int bus_type, int bus_id, int dma_type, - int npages, int page_size, int flags); - -#ifdef __cplusplus -} -#endif - -/* - * Macros for page number and page offsets, using ps as page size - */ -#define x_pnum(addr, ps) ((__psunsigned_t)(addr) / (__psunsigned_t)(ps)) -#define x_poff(addr, ps) ((__psunsigned_t)(addr) & ((__psunsigned_t)(ps) - 1)) - -#endif /* _ASM_SN_IOBUS_H */ diff --git a/include/asm-ia64/sn/ioc3.h b/include/asm-ia64/sn/ioc3.h index e407a3f7a15f..26afbf127cdf 100644 --- a/include/asm-ia64/sn/ioc3.h +++ b/include/asm-ia64/sn/ioc3.h @@ -1,10 +1,44 @@ +/* + * Copyright (c) 2002 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: + * + * http://www.sgi.com + * + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/NoticeExplan + */ + /* $Id: ioc3.h,v 1.2 2000/11/16 19:49:17 pfg Exp $ * * Copyright (C) 1999 Ralf Baechle * This file is part of the Linux driver for the SGI IOC3. */ -#ifndef IOC3_H -#define IOC3_H +#ifndef _ASM_IA64_SN_IOC3_H +#define _ASM_IA64_SN_IOC3_H + +#include <asm/types.h> /* SUPERIO uart register map */ typedef volatile struct ioc3_uartregs { @@ -668,4 +702,4 @@ typedef enum ioc3_subdevs_e { #define IOC3_VENDOR_ID_NUM 0x10A9 #define IOC3_DEVICE_ID_NUM 0x0003 -#endif /* IOC3_H */ +#endif /* _ASM_IA64_SN_IOC3_H */ diff --git a/include/asm-ia64/sn/ioerror.h b/include/asm-ia64/sn/ioerror.h index 8f87af4d147d..b44b035d8316 100644 --- a/include/asm-ia64/sn/ioerror.h +++ b/include/asm-ia64/sn/ioerror.h @@ -4,13 +4,15 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_IOERROR_H -#define _ASM_SN_IOERROR_H +#ifndef _ASM_IA64_SN_IOERROR_H +#define _ASM_IA64_SN_IOERROR_H -#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) +#ifndef __ASSEMBLY__ + +#include <linux/types.h> +#include <asm/sn/types.h> /* * Macros defining the various Errors to be handled as part of @@ -162,7 +164,6 @@ typedef struct io_error_s { #define IOERROR_FIELDVALID(e,f) (((e)->ie_v.iev_b.ievb_ ## f) != 0) #define IOERROR_GETVALUE(e,f) (ASSERT(IOERROR_FIELDVALID(e,f)),((e)->ie_ ## f)) -#if IP27 || IP35 /* hub code likes to call the SysAD address "hubaddr" ... */ #define ie_hubaddr ie_sysioaddr #define ievb_hubaddr ievb_sysioaddr @@ -178,7 +179,6 @@ typedef enum { MODE_DEVREENABLE /* Reenable pass */ } ioerror_mode_t; -#endif /* C || C++ */ typedef int error_handler_f(void *, int, ioerror_mode_t, ioerror_t *); typedef void *error_handler_arg_t; @@ -193,4 +193,4 @@ extern void ioerror_dump(char *, int, int, ioerror_t *); #define IOERR_PRINTF(x) #endif /* ERROR_DEBUG */ -#endif /* _ASM_SN_IOERROR_H */ +#endif /* _ASM_IA64_SN_IOERROR_H */ diff --git a/include/asm-ia64/sn/ioerror_handling.h b/include/asm-ia64/sn/ioerror_handling.h index 18e2e6aa91d8..401aaf362596 100644 --- a/include/asm-ia64/sn/ioerror_handling.h +++ b/include/asm-ia64/sn/ioerror_handling.h @@ -1,16 +1,17 @@ -/* $Id$ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_IOERROR_HANDLING_H -#define _ASM_SN_IOERROR_HANDLING_H +#ifndef _ASM_IA64_SN_IOERROR_HANDLING_H +#define _ASM_IA64_SN_IOERROR_HANDLING_H #include <linux/config.h> +#include <linux/types.h> +#include <linux/devfs_fs_kernel.h> +#include <asm/sn/sgi.h> #if __KERNEL__ @@ -264,7 +265,7 @@ error_skip_point_mark(devfs_handle_t v) * one. */ if (v_error_skip_env_get(v, error_env) != GRAPH_SUCCESS) { - error_env = kmem_zalloc(sizeof(label_t), KM_NOSLEEP); + error_env = snia_kmem_zalloc(sizeof(label_t), KM_NOSLEEP); /* Unable to allocate memory for jum buffer. This should * be a very rare occurrence. */ @@ -302,4 +303,4 @@ extern boolean_t is_device_shutdown(devfs_handle_t); #endif #endif /* __KERNEL__ */ -#endif /* _ASM_SN_IOERROR_HANDLING_H */ +#endif /* _ASM_IA64_SN_IOERROR_HANDLING_H */ diff --git a/include/asm-ia64/sn/iograph.h b/include/asm-ia64/sn/iograph.h index 6df46ca32926..046d6cd5e7a7 100644 --- a/include/asm-ia64/sn/iograph.h +++ b/include/asm-ia64/sn/iograph.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_IOGRAPH_H -#define _ASM_SN_IOGRAPH_H +#ifndef _ASM_IA64_SN_IOGRAPH_H +#define _ASM_IA64_SN_IOGRAPH_H /* * During initialization, platform-dependent kernel code establishes some @@ -68,6 +67,7 @@ #define EDGE_LBL_HPC "hpc" #define EDGE_LBL_GFX "gfx" #define EDGE_LBL_HUB "hub" /* For SN0 */ +#define EDGE_LBL_SYNERGY "synergy" /* For SNIA only */ #define EDGE_LBL_IBUS "ibus" /* For EVEREST */ #define EDGE_LBL_INTERCONNECT "link" #define EDGE_LBL_IO "io" @@ -216,4 +216,4 @@ struct io_brick_map_s { }; -#endif /* _ASM_SN_IOGRAPH_H */ +#endif /* _ASM_IA64_SN_IOGRAPH_H */ diff --git a/include/asm-ia64/sn/klclock.h b/include/asm-ia64/sn/klclock.h new file mode 100644 index 000000000000..5244401ef708 --- /dev/null +++ b/include/asm-ia64/sn/klclock.h @@ -0,0 +1,60 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1996, 2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2001 by Ralf Baechle + */ +#ifndef _ASM_IA64_SN_KLCLOCK_H +#define _ASM_IA64_SN_KLCLOCK_H + +#include <asm/sn/ioc3.h> + +#define RTC_BASE_ADDR (unsigned char *)(nvram_base) + +/* Defines for the SGS-Thomson M48T35 clock */ +#define RTC_SGS_WRITE_ENABLE 0x80 +#define RTC_SGS_READ_PROTECT 0x40 +#define RTC_SGS_YEAR_ADDR (RTC_BASE_ADDR + 0x7fffL) +#define RTC_SGS_MONTH_ADDR (RTC_BASE_ADDR + 0x7ffeL) +#define RTC_SGS_DATE_ADDR (RTC_BASE_ADDR + 0x7ffdL) +#define RTC_SGS_DAY_ADDR (RTC_BASE_ADDR + 0x7ffcL) +#define RTC_SGS_HOUR_ADDR (RTC_BASE_ADDR + 0x7ffbL) +#define RTC_SGS_MIN_ADDR (RTC_BASE_ADDR + 0x7ffaL) +#define RTC_SGS_SEC_ADDR (RTC_BASE_ADDR + 0x7ff9L) +#define RTC_SGS_CONTROL_ADDR (RTC_BASE_ADDR + 0x7ff8L) + +/* Defines for the Dallas DS1386 */ +#define RTC_DAL_UPDATE_ENABLE 0x80 +#define RTC_DAL_UPDATE_DISABLE 0x00 +#define RTC_DAL_YEAR_ADDR (RTC_BASE_ADDR + 0xaL) +#define RTC_DAL_MONTH_ADDR (RTC_BASE_ADDR + 0x9L) +#define RTC_DAL_DATE_ADDR (RTC_BASE_ADDR + 0x8L) +#define RTC_DAL_DAY_ADDR (RTC_BASE_ADDR + 0x6L) +#define RTC_DAL_HOUR_ADDR (RTC_BASE_ADDR + 0x4L) +#define RTC_DAL_MIN_ADDR (RTC_BASE_ADDR + 0x2L) +#define RTC_DAL_SEC_ADDR (RTC_BASE_ADDR + 0x1L) +#define RTC_DAL_CONTROL_ADDR (RTC_BASE_ADDR + 0xbL) +#define RTC_DAL_USER_ADDR (RTC_BASE_ADDR + 0xeL) + +/* Defines for the Dallas DS1742 */ +#define RTC_DS1742_WRITE_ENABLE 0x80 +#define RTC_DS1742_READ_ENABLE 0x40 +#define RTC_DS1742_UPDATE_DISABLE 0x00 +#define RTC_DS1742_YEAR_ADDR (RTC_BASE_ADDR + 0x7ffL) +#define RTC_DS1742_MONTH_ADDR (RTC_BASE_ADDR + 0x7feL) +#define RTC_DS1742_DATE_ADDR (RTC_BASE_ADDR + 0x7fdL) +#define RTC_DS1742_DAY_ADDR (RTC_BASE_ADDR + 0x7fcL) +#define RTC_DS1742_HOUR_ADDR (RTC_BASE_ADDR + 0x7fbL) +#define RTC_DS1742_MIN_ADDR (RTC_BASE_ADDR + 0x7faL) +#define RTC_DS1742_SEC_ADDR (RTC_BASE_ADDR + 0x7f9L) +#define RTC_DS1742_CONTROL_ADDR (RTC_BASE_ADDR + 0x7f8L) +#define RTC_DS1742_USER_ADDR (RTC_BASE_ADDR + 0x0L) + +#define BCD_TO_INT(x) (((x>>4) * 10) + (x & 0xf)) +#define INT_TO_BCD(x) (((x / 10)<<4) + (x % 10)) + +#define YRREF 1970 + +#endif /* _ASM_IA64_SN_KLCLOCK_H */ diff --git a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h index 1063042a41d0..733ed89a4325 100644 --- a/include/asm-ia64/sn/klconfig.h +++ b/include/asm-ia64/sn/klconfig.h @@ -6,11 +6,11 @@ * * Derived from IRIX <sys/SN/klconfig.h>. * - * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. + * Copyright (C) 1992-1997,1999,2001-2002 Silicon Graphics, Inc. All Rights Reserved. * Copyright (C) 1999 by Ralf Baechle */ -#ifndef _ASM_SN_KLCONFIG_H -#define _ASM_SN_KLCONFIG_H +#ifndef _ASM_IA64_SN_KLCONFIG_H +#define _ASM_IA64_SN_KLCONFIG_H #include <linux/config.h> @@ -38,20 +38,22 @@ #include <asm/sn/types.h> #include <asm/sn/slotnum.h> #include <asm/sn/router.h> -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) #include <asm/sn/sgi.h> -#include <asm/sn/sn1/addrs.h> +#include <asm/sn/addrs.h> #include <asm/sn/vector.h> -#include <asm/sn/agent.h> -// #include <sys/graph.h> -// #include <asm/sn/arc/types.h> #include <asm/sn/arc/hinv.h> #include <asm/sn/xtalk/xbow.h> #include <asm/sn/xtalk/xtalk.h> #include <asm/sn/kldir.h> #include <asm/sn/sn_fru.h> -#endif /* CONFIG_SGI_IP35 ... */ +#ifdef CONFIG_IA64_SGI_SN1 +#include <asm/sn/sn1/hubmd_next.h> +#endif + +#ifdef CONFIG_IA64_SGI_SN2 +#include <asm/sn/sn2/shub_md.h> +#endif #define KLCFGINFO_MAGIC 0xbeedbabe @@ -59,19 +61,11 @@ typedef s32 klconf_off_t; #define MAX_MODULE_ID 255 #define SIZE_PAD 4096 /* 4k padding for structures */ -#if (defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)) && defined(BRINGUP) /* MAX_SLOTS_PER_NODE??? */ /* * 1 NODE brick, 3 Router bricks (1 local, 1 meta, 1 repeater), * 6 XIO Widgets, 1 Xbow, 1 gfx */ #define MAX_SLOTS_PER_NODE (1 + 3 + 6 + 1 + 1) -#else -/* - * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets, - * 2 Midplanes assuming no pci card cages - */ -#define MAX_SLOTS_PER_NODE (1 + 2 + 6 + 2) -#endif /* XXX if each node is guranteed to have some memory */ @@ -349,7 +343,7 @@ typedef struct kl_config_hdr { #define KLCLASS(_x) ((_x) & KLCLASS_MASK) /* - * IP27 board types + * board types */ #define KLTYPE_MASK 0x0f @@ -357,11 +351,7 @@ typedef struct kl_config_hdr { #define KLTYPE_EMPTY 0x00 #define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0) -#define KLTYPE_IP27 (KLCLASS_CPU | 0x1) /* 2 CPUs(R10K) per board */ -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -#define KLTYPE_IP35 KLTYPE_IP27 -#define KLTYPE_IP37 KLTYPE_IP35 -#endif +#define KLTYPE_SNIA (KLCLASS_CPU | 0x1) #define KLTYPE_WEIRDIO (KLCLASS_IO | 0x0) #define KLTYPE_BASEIO (KLCLASS_IO | 0x1) /* IOC3, SuperIO, Bridge, SCSI */ @@ -949,7 +939,6 @@ extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, ch extern int config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**); extern int config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**); extern int config_find_xbow(nasid_t, lboard_t **, klxbow_t**); -extern klcpu_t *get_cpuinfo(cpuid_t cpu); extern int update_klcfg_cpuinfo(nasid_t, int); extern void board_to_path(lboard_t *brd, char *path); extern moduleid_t get_module_id(nasid_t nasid); @@ -963,4 +952,4 @@ extern int is_master_baseio(nasid_t,moduleid_t,slotid_t); extern nasid_t get_actual_nasid(lboard_t *brd) ; extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int); -#endif /* _ASM_SN_KLCONFIG_H */ +#endif /* _ASM_IA64_SN_KLCONFIG_H */ diff --git a/include/asm-ia64/sn/kldir.h b/include/asm-ia64/sn/kldir.h index debb8ae61d6b..2f6f644a2090 100644 --- a/include/asm-ia64/sn/kldir.h +++ b/include/asm-ia64/sn/kldir.h @@ -1,18 +1,16 @@ -/* $Id$ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Derived from IRIX <sys/SN/kldir.h>, revision 1.21. * - * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. + * Copyright (C) 1992-1997,1999,2001-2002 Silicon Graphics, Inc. All Rights Reserved. * Copyright (C) 1999 by Ralf Baechle */ -#ifndef _ASM_SN_KLDIR_H -#define _ASM_SN_KLDIR_H +#ifndef _ASM_IA64_SN_KLDIR_H +#define _ASM_IA64_SN_KLDIR_H -#include <linux/config.h> #include <asm/sn/sgi.h> /* @@ -125,16 +123,16 @@ * 0x0 (0K) +-----------------------------------------+ */ -#ifdef LANGUAGE_ASSEMBLY +#ifdef __ASSEMBLY__ #define KLDIR_OFF_MAGIC 0x00 #define KLDIR_OFF_OFFSET 0x08 #define KLDIR_OFF_POINTER 0x10 #define KLDIR_OFF_SIZE 0x18 #define KLDIR_OFF_COUNT 0x20 #define KLDIR_OFF_STRIDE 0x28 -#endif /* LANGUAGE_ASSEMBLY */ +#endif /* __ASSEMBLY__ */ -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ typedef struct kldir_ent_s { u64 magic; /* Indicates validity of entry */ off_t offset; /* Offset from start of node space */ @@ -146,19 +144,220 @@ typedef struct kldir_ent_s { /* NOTE: These 16 bytes are used in the Partition KLDIR entry to store partition info. Refer to klpart.h for this. */ } kldir_ent_t; -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ #define KLDIR_ENT_SIZE 0x40 #define KLDIR_MAX_ENTRIES (0x400 / 0x40) + + /* - * The actual offsets of each memory area are machine-dependent + * The upper portion of the memory map applies during boot + * only and is overwritten by IRIX/SYMMON. The minimum memory bank + * size on IP35 is 64M, which provides a limit on the amount of space + * the PROM can assume it has available. + * + * Most of the addresses below are defined as macros in this file, or + * in SN/addrs.h or SN/SN1/addrs.h. + * + * MEMORY MAP PER NODE + * + * 0x4000000 (64M) +-----------------------------------------+ + * | | + * | | + * | IO7 TEXT/DATA/BSS/stack | + * 0x3000000 (48M) +-----------------------------------------+ + * | Free | + * 0x2102000 (>33M) +-----------------------------------------+ + * | IP35 Topology (PCFG) + misc data | + * 0x2000000 (32M) +-----------------------------------------+ + * | IO7 BUFFERS FOR FLASH ENET IOC3 | + * 0x1F80000 (31.5M) +-----------------------------------------+ + * | Free | + * 0x1C00000 (28M) +-----------------------------------------+ + * | IP35 PROM TEXT/DATA/BSS/stack | + * 0x1A00000 (26M) +-----------------------------------------+ + * | Routing temp. space | + * 0x1800000 (24M) +-----------------------------------------+ + * | Diagnostics temp. space | + * 0x1500000 (21M) +-----------------------------------------+ + * | Free | + * 0x1400000 (20M) +-----------------------------------------+ + * | IO7 PROM temporary copy | + * 0x1300000 (19M) +-----------------------------------------+ + * | | + * | Free | + * | (UNIX DATA starts above 0x1000000) | + * | | + * +-----------------------------------------+ + * | UNIX DEBUG Version | + * 0x0310000 (3.1M) +-----------------------------------------+ + * | SYMMON, loaded just below UNIX | + * | (For UNIX Debug only) | + * | | + * | | + * 0x006C000 (432K) +-----------------------------------------+ + * | SYMMON STACK [NUM_CPU_PER_NODE] | + * | (For UNIX Debug only) | + * 0x004C000 (304K) +-----------------------------------------+ + * | | + * | | + * | UNIX NON-DEBUG Version | + * 0x0040000 (256K) +-----------------------------------------+ + * + * + * The lower portion of the memory map contains information that is + * permanent and is used by the IP35PROM, IO7PROM and IRIX. + * + * 0x40000 (256K) +-----------------------------------------+ + * | | + * | KLCONFIG (64K) | + * | | + * 0x30000 (192K) +-----------------------------------------+ + * | | + * | PI Error Spools (64K) | + * | | + * 0x20000 (128K) +-----------------------------------------+ + * | | + * | Unused | + * | | + * 0x19000 (100K) +-----------------------------------------+ + * | Early cache Exception stack (CPU 3)| + * 0x18800 (98K) +-----------------------------------------+ + * | cache error eframe (CPU 3) | + * 0x18400 (97K) +-----------------------------------------+ + * | Exception Handlers (CPU 3) | + * 0x18000 (96K) +-----------------------------------------+ + * | | + * | Unused | + * | | + * 0x13c00 (79K) +-----------------------------------------+ + * | GPDA (8k) | + * 0x11c00 (71K) +-----------------------------------------+ + * | Early cache Exception stack (CPU 2)| + * 0x10800 (66k) +-----------------------------------------+ + * | cache error eframe (CPU 2) | + * 0x10400 (65K) +-----------------------------------------+ + * | Exception Handlers (CPU 2) | + * 0x10000 (64K) +-----------------------------------------+ + * | | + * | Unused | + * | | + * 0x0b400 (45K) +-----------------------------------------+ + * | GDA (1k) | + * 0x0b000 (44K) +-----------------------------------------+ + * | NMI Eframe areas (4) | + * 0x0a000 (40K) +-----------------------------------------+ + * | NMI Register save areas (4) | + * 0x09000 (36K) +-----------------------------------------+ + * | Early cache Exception stack (CPU 1)| + * 0x08800 (34K) +-----------------------------------------+ + * | cache error eframe (CPU 1) | + * 0x08400 (33K) +-----------------------------------------+ + * | Exception Handlers (CPU 1) | + * 0x08000 (32K) +-----------------------------------------+ + * | | + * | | + * | Unused | + * | | + * | | + * 0x04000 (16K) +-----------------------------------------+ + * | NMI Handler (Protected Page) | + * 0x03000 (12K) +-----------------------------------------+ + * | ARCS PVECTORS (master node only) | + * 0x02c00 (11K) +-----------------------------------------+ + * | ARCS TVECTORS (master node only) | + * 0x02800 (10K) +-----------------------------------------+ + * | LAUNCH [NUM_CPU] | + * 0x02400 (9K) +-----------------------------------------+ + * | Low memory directory (KLDIR) | + * 0x02000 (8K) +-----------------------------------------+ + * | ARCS SPB (1K) | + * 0x01000 (4K) +-----------------------------------------+ + * | Early cache Exception stack (CPU 0)| + * 0x00800 (2k) +-----------------------------------------+ + * | cache error eframe (CPU 0) | + * 0x00400 (1K) +-----------------------------------------+ + * | Exception Handlers (CPU 0) | + * 0x00000 (0K) +-----------------------------------------+ + */ + +/* + * NOTE: To change the kernel load address, you must update: + * - the appropriate elspec files in irix/kern/master.d + * - NODEBUGUNIX_ADDR in SN/SN1/addrs.h + * - IP27_FREEMEM_OFFSET below + * - KERNEL_START_OFFSET below (if supporting cells) */ -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -#include <asm/sn/sn1/kldir.h> -#else -#error "kldir.h is currently defined for IP27 and IP35 platforms only" -#endif -#endif /* _ASM_SN_KLDIR_H */ + +/* + * This is defined here because IP27_SYMMON_STK_SIZE must be at least what + * we define here. Since it's set up in the prom. We can't redefine it later + * and expect more space to be allocated. The way to find out the true size + * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE + * for a particular node. + */ +#define SYMMON_STACK_SIZE 0x8000 + +#if defined (PROM) || defined (SABLE) + +/* + * These defines are prom version dependent. No code other than the IP35 + * prom should attempt to use these values. + */ +#define IP27_LAUNCH_OFFSET 0x2400 +#define IP27_LAUNCH_SIZE 0x400 +#define IP27_LAUNCH_COUNT 4 +#define IP27_LAUNCH_STRIDE 0x100 /* could be as small as 0x80 */ + +#define IP27_KLCONFIG_OFFSET 0x30000 +#define IP27_KLCONFIG_SIZE 0x10000 +#define IP27_KLCONFIG_COUNT 1 +#define IP27_KLCONFIG_STRIDE 0 + +#define IP27_NMI_OFFSET 0x3000 +#define IP27_NMI_SIZE 0x100 +#define IP27_NMI_COUNT 4 +#define IP27_NMI_STRIDE 0x40 + +#define IP27_PI_ERROR_OFFSET 0x20000 +#define IP27_PI_ERROR_SIZE 0x10000 +#define IP27_PI_ERROR_COUNT 1 +#define IP27_PI_ERROR_STRIDE 0 + +#define IP27_SYMMON_STK_OFFSET 0x4c000 +#define IP27_SYMMON_STK_SIZE 0x20000 +#define IP27_SYMMON_STK_COUNT 4 +/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */ +#define IP27_SYMMON_STK_STRIDE 0x8000 + +#define IP27_FREEMEM_OFFSET 0x40000 +#define IP27_FREEMEM_SIZE (-1) +#define IP27_FREEMEM_COUNT 1 +#define IP27_FREEMEM_STRIDE 0 + +#endif /* PROM || SABLE*/ +/* + * There will be only one of these in a partition so the IO7 must set it up. + */ +#define IO6_GDA_OFFSET 0xb000 +#define IO6_GDA_SIZE 0x400 +#define IO6_GDA_COUNT 1 +#define IO6_GDA_STRIDE 0 + +/* + * save area of kernel nmi regs in the prom format + */ +#define IP27_NMI_KREGS_OFFSET 0x9000 +#define IP27_NMI_KREGS_CPU_SIZE 0x400 +/* + * save area of kernel nmi regs in eframe format + */ +#define IP27_NMI_EFRAME_OFFSET 0xa000 +#define IP27_NMI_EFRAME_SIZE 0x400 + +#define GPDA_OFFSET 0x11c00 + +#endif /* _ASM_IA64_SN_KLDIR_H */ diff --git a/include/asm-ia64/sn/ksys/elsc.h b/include/asm-ia64/sn/ksys/elsc.h index eb9d9db894e8..bfe6430a93d3 100644 --- a/include/asm-ia64/sn/ksys/elsc.h +++ b/include/asm-ia64/sn/ksys/elsc.h @@ -4,36 +4,16 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_KSYS_ELSC_H #define _ASM_SN_KSYS_ELSC_H -#include <linux/config.h> - -#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) #include <asm/sn/ksys/l1.h> -#endif - -// #include <asm/sn/ksys/i2c.h> -#define ELSC_I2C_ADDR 0x08 -#define ELSC_I2C_HUB0 0x09 -#define ELSC_I2C_HUB1 0x0a -#define ELSC_I2C_HUB2 0x0b -#define ELSC_I2C_HUB3 0x0c - -#define ELSC_PACKET_MAX 96 #define ELSC_ACP_MAX 86 /* 84+cr+lf */ #define ELSC_LINE_MAX (ELSC_ACP_MAX - 2) -/* - * ELSC character queue type for I/O - */ - -#define ELSC_QSIZE 128 /* Power of 2 is more efficient */ - typedef sc_cq_t elsc_cq_t; /* @@ -49,14 +29,11 @@ int elsc_msg_check(elsc_t *e, char *msg, int msg_max); int elsc_msg_callback(elsc_t *e, void (*callback)(void *callback_data, char *msg), void *callback_data); -#ifdef LATER char *elsc_errmsg(int code); int elsc_nvram_write(elsc_t *e, int addr, char *buf, int len); int elsc_nvram_read(elsc_t *e, int addr, char *buf, int len); int elsc_nvram_magic(elsc_t *e); -#endif - int elsc_command(elsc_t *e, int only_if_message); int elsc_parse(elsc_t *e, char *p1, char *p2, char *p3); int elsc_ust_write(elsc_t *e, uchar_t c); @@ -69,10 +46,8 @@ int elsc_ust_read(elsc_t *e, char *c); */ int elsc_version(elsc_t *e, char *result); -#ifdef LATER int elsc_debug_set(elsc_t *e, u_char byte1, u_char byte2); int elsc_debug_get(elsc_t *e, u_char *byte1, u_char *byte2); -#endif int elsc_module_set(elsc_t *e, int module); int elsc_module_get(elsc_t *e); int elsc_partition_set(elsc_t *e, int partition); @@ -85,13 +60,10 @@ int elsc_cell_set(elsc_t *e, int cell); int elsc_cell_get(elsc_t *e); int elsc_bist_set(elsc_t *e, char bist_status); char elsc_bist_get(elsc_t *e); -int elsc_lock(elsc_t *e, - int retry_interval_usec, - int timeout_usec, u_char lock_val); +int elsc_lock(elsc_t *e, int retry_interval_usec, int timeout_usec, u_char lock_val); int elsc_unlock(elsc_t *e); int elsc_display_char(elsc_t *e, int led, int chr); int elsc_display_digit(elsc_t *e, int led, int num, int l_case); -#ifdef LATER int elsc_display_mesg(elsc_t *e, char *chr); /* 8-char input */ int elsc_password_set(elsc_t *e, char *password); /* 4-char input */ int elsc_password_get(elsc_t *e, char *password); /* 4-char output */ @@ -102,7 +74,6 @@ int elsc_power_cycle(elsc_t *e); int elsc_system_reset(elsc_t *e); int elsc_dip_switches(elsc_t *e); int elsc_nic_get(elsc_t *e, uint64_t *nic, int verbose); -#endif int _elsc_hbt(elsc_t *e, int ival, int rdly); @@ -110,29 +81,8 @@ int _elsc_hbt(elsc_t *e, int ival, int rdly); #define elsc_hbt_disable(e) _elsc_hbt(e, 0, 0) #define elsc_hbt_send(e) _elsc_hbt(e, 0, 1) -/* - * Routines for using the ELSC as a UART. There's a version of each - * routine that takes a pointer to an elsc_t, and another version that - * gets the pointer by calling a user-supplied global routine "get_elsc". - * The latter version is useful when the elsc is employed for stdio. - */ - -#define ELSCUART_FLASH 0x3c /* LED pattern */ - elsc_t *get_elsc(void); -int elscuart_probe(void); -void elscuart_init(void *); -int elscuart_poll(void); -int elscuart_readc(void); -int elscuart_getc(void); -int elscuart_putc(int); -int elscuart_puts(char *); -char *elscuart_gets(char *, int); -int elscuart_flush(void); - - - /* * Error codes * @@ -142,23 +92,23 @@ int elscuart_flush(void); #define ELSC_ERROR_NONE 0 -#define ELSC_ERROR_CMD_SEND -100 /* Error sending command */ -#define ELSC_ERROR_CMD_CHECKSUM -101 /* Command checksum bad */ -#define ELSC_ERROR_CMD_UNKNOWN -102 /* Unknown command */ -#define ELSC_ERROR_CMD_ARGS -103 /* Invalid argument(s) */ -#define ELSC_ERROR_CMD_PERM -104 /* Permission denied */ -#define ELSC_ERROR_CMD_STATE -105 /* not allowed in this state*/ - -#define ELSC_ERROR_RESP_TIMEOUT -110 /* ELSC response timeout */ -#define ELSC_ERROR_RESP_CHECKSUM -111 /* Response checksum bad */ -#define ELSC_ERROR_RESP_FORMAT -112 /* Response format error */ -#define ELSC_ERROR_RESP_DIR -113 /* Response direction error */ - -#define ELSC_ERROR_MSG_LOST -120 /* Queue full; msg. lost */ -#define ELSC_ERROR_LOCK_TIMEOUT -121 /* ELSC response timeout */ -#define ELSC_ERROR_DATA_SEND -122 /* Error sending data */ -#define ELSC_ERROR_NIC -123 /* NIC processing error */ -#define ELSC_ERROR_NVMAGIC -124 /* Bad magic no. in NVRAM */ -#define ELSC_ERROR_MODULE -125 /* Moduleid processing err */ +#define ELSC_ERROR_CMD_SEND (-100) /* Error sending command */ +#define ELSC_ERROR_CMD_CHECKSUM (-101) /* Command checksum bad */ +#define ELSC_ERROR_CMD_UNKNOWN (-102) /* Unknown command */ +#define ELSC_ERROR_CMD_ARGS (-103) /* Invalid argument(s) */ +#define ELSC_ERROR_CMD_PERM (-104) /* Permission denied */ +#define ELSC_ERROR_CMD_STATE (-105) /* not allowed in this state*/ + +#define ELSC_ERROR_RESP_TIMEOUT (-110) /* ELSC response timeout */ +#define ELSC_ERROR_RESP_CHECKSUM (-111) /* Response checksum bad */ +#define ELSC_ERROR_RESP_FORMAT (-112) /* Response format error */ +#define ELSC_ERROR_RESP_DIR (-113) /* Response direction error */ + +#define ELSC_ERROR_MSG_LOST (-120) /* Queue full; msg. lost */ +#define ELSC_ERROR_LOCK_TIMEOUT (-121) /* ELSC response timeout */ +#define ELSC_ERROR_DATA_SEND (-122) /* Error sending data */ +#define ELSC_ERROR_NIC (-123) /* NIC processing error */ +#define ELSC_ERROR_NVMAGIC (-124) /* Bad magic no. in NVRAM */ +#define ELSC_ERROR_MODULE (-125) /* Moduleid processing err */ #endif /* _ASM_SN_KSYS_ELSC_H */ diff --git a/include/asm-ia64/sn/ksys/i2c.h b/include/asm-ia64/sn/ksys/i2c.h deleted file mode 100644 index f350d218697c..000000000000 --- a/include/asm-ia64/sn/ksys/i2c.h +++ /dev/null @@ -1,77 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam - */ -#ifndef _ASM_SN_KSYS_I2C_H -#define _ASM_SN_KSYS_I2C_H - -#if _STANDALONE -# include "rtc.h" -#else -# define rtc_time() (GET_LOCAL_RTC * NSEC_PER_CYCLE / 1000) -# define rtc_sleep us_delay -# define rtc_time_t uint64_t -#endif - -typedef u_char i2c_addr_t; /* 7-bit address */ - -int i2c_init(nasid_t); - -int i2c_probe(nasid_t nasid, rtc_time_t timeout); - -int i2c_arb(nasid_t, rtc_time_t timeout, rtc_time_t *token_start); - -int i2c_master_xmit(nasid_t, - i2c_addr_t addr, - u_char *buf, - int len_max, - int *len_ptr, - rtc_time_t timeout, - int only_if_message); - -int i2c_master_recv(nasid_t, - i2c_addr_t addr, - u_char *buf, - int len_max, - int *len_ptr, - int emblen, - rtc_time_t timeout, - int only_if_message); - -int i2c_master_xmit_recv(nasid_t, - i2c_addr_t addr, - u_char *xbuf, - int xlen_max, - int *xlen_ptr, - u_char *rbuf, - int rlen_max, - int *rlen_ptr, - int emblen, - rtc_time_t timeout, - int only_if_message); - -char *i2c_errmsg(int code); - -/* - * Error codes - */ - -#define I2C_ERROR_NONE 0 -#define I2C_ERROR_INIT -1 /* Initialization error */ -#define I2C_ERROR_STATE -2 /* Unexpected chip state */ -#define I2C_ERROR_NAK -3 /* Addressed slave not responding */ -#define I2C_ERROR_TO_ARB -4 /* Timeout waiting for sysctlr arb */ -#define I2C_ERROR_TO_BUSY -5 /* Timeout waiting for busy bus */ -#define I2C_ERROR_TO_SENDA -6 /* Timeout sending address byte */ -#define I2C_ERROR_TO_SENDD -7 /* Timeout sending data byte */ -#define I2C_ERROR_TO_RECVA -8 /* Timeout receiving address byte */ -#define I2C_ERROR_TO_RECVD -9 /* Timeout receiving data byte */ -#define I2C_ERROR_NO_MESSAGE -10 /* No message was waiting */ -#define I2C_ERROR_NO_ELSC -11 /* ELSC is disabled for access */ - -#endif /* _ASM_SN_KSYS_I2C_H */ diff --git a/include/asm-ia64/sn/ksys/l1.h b/include/asm-ia64/sn/ksys/l1.h index b0cf6f935c49..f4b3fe5b80fe 100644 --- a/include/asm-ia64/sn/ksys/l1.h +++ b/include/asm-ia64/sn/ksys/l1.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_KSYS_L1_H @@ -13,7 +12,8 @@ #include <asm/sn/vector.h> #include <asm/sn/addrs.h> -#include <asm/sn/sn1/bedrock.h> +#include <asm/atomic.h> +#include <asm/sn/sv.h> #define BRL1_QSIZE 128 /* power of 2 is more efficient */ #define BRL1_BUFSZ 264 /* needs to be large enough @@ -39,7 +39,7 @@ typedef struct sc_cq_s { * This value can't be confused with a network vector because the least- * significant nibble of a network vector cannot be greater than 8. */ -#define BRL1_LOCALUART ((net_vec_t)0xf) +#define BRL1_LOCALHUB_UART ((net_vec_t)0xf) /* L1<->Bedrock reserved subchannels */ @@ -71,7 +71,14 @@ typedef struct sc_cq_s { struct l1sc_s; -typedef void (*brl1_notif_t)(struct l1sc_s *, int); +/* Saved off interrupt frame */ +typedef struct brl1_intr_frame { + int bf_irq; /* irq received */ + void *bf_dev_id; /* device information */ + struct pt_regs *bf_regs; /* register frame */ +} brl1_intr_frame_t; + +typedef void (*brl1_notif_t)(int, void *, struct pt_regs *, struct l1sc_s *, int); typedef int (*brl1_uartf_t)(struct l1sc_s *); /* structure for controlling a subchannel */ @@ -90,6 +97,7 @@ typedef struct brl1_sch_s { * continue */ brl1_notif_t rx_notify; /* notify higher layer that a packet has been * received */ + brl1_intr_frame_t irq_frame; /* saved off irq information */ } brl1_sch_t; /* br<->l1 protocol states */ @@ -101,7 +109,7 @@ typedef struct brl1_sch_s { #define BRL1_RESET 7 -#ifndef _LANGUAGE_ASSEMBLY +#ifndef __ASSEMBLY__ /* * l1sc_t structure-- tracks protocol state, open subchannels, etc. @@ -118,6 +126,8 @@ typedef struct l1sc_s { brl1_uartf_t putc_f; /* pointer to UART putc function */ brl1_uartf_t getc_f; /* pointer to UART getc function */ + spinlock_t send_lock; /* arbitrates send synchronization */ + spinlock_t recv_lock; /* arbitrates uart receive access */ spinlock_t subch_lock; /* arbitrates subchannel allocation */ cpuid_t intr_cpu; /* cpu that receives L1 interrupts */ @@ -327,15 +337,6 @@ int sc_poll( l1sc_t *sc, int ch ); void sc_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart ); void sc_intr_enable( l1sc_t *sc ); -int _elscuart_putc( l1sc_t *sc, int c ); -int _elscuart_getc( l1sc_t *sc ); -int _elscuart_poll( l1sc_t *sc ); -int _elscuart_readc( l1sc_t *sc ); -int _elscuart_flush( l1sc_t *sc ); -int _elscuart_probe( l1sc_t *sc ); -void _elscuart_init( l1sc_t *sc ); -void elscuart_syscon_listen( l1sc_t *sc ); - int elsc_rack_bay_get(l1sc_t *e, uint *rack, uint *bay); int elsc_rack_bay_type_get(l1sc_t *e, uint *rack, uint *bay, uint *brick_type); @@ -357,5 +358,5 @@ int iobrick_pci_bus_pwr( l1sc_t *sc, int bus, int up ); int iobrick_sc_version( l1sc_t *sc, char *result ); -#endif /* !_LANGUAGE_ASSEMBLY */ +#endif /* !__ASSEMBLY__ */ #endif /* _ASM_SN_KSYS_L1_H */ diff --git a/include/asm-ia64/sn/labelcl.h b/include/asm-ia64/sn/labelcl.h index 902ae2203c67..b08f52a4e627 100644 --- a/include/asm-ia64/sn/labelcl.h +++ b/include/asm-ia64/sn/labelcl.h @@ -4,15 +4,16 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_LABELCL_H -#define _ASM_SN_LABELCL_H +#ifndef _ASM_IA64_SN_LABELCL_H +#define _ASM_IA64_SN_LABELCL_H + +#include <asm/sn/hcl.h> #define LABELCL_MAGIC 0x4857434c /* 'HWLC' */ #define LABEL_LENGTH_MAX 256 /* Includes NULL char */ -#define INFO_DESC_PRIVATE -1 /* default */ +#define INFO_DESC_PRIVATE (-1) /* default */ #define INFO_DESC_EXPORT 0 /* export info itself */ /* @@ -90,4 +91,4 @@ extern int labelcl_info_connectpt_set(struct devfs_entry *, struct devfs_entry * extern int labelcl_info_get_IDX(struct devfs_entry *, int, arbitrary_info_t *); extern struct devfs_entry *device_info_connectpt_get(struct devfs_entry *); -#endif /* _ASM_SN_LABELCL_H */ +#endif /* _ASM_IA64_SN_LABELCL_H */ diff --git a/include/asm-ia64/sn/leds.h b/include/asm-ia64/sn/leds.h new file mode 100644 index 000000000000..7e87077d3ee6 --- /dev/null +++ b/include/asm-ia64/sn/leds.h @@ -0,0 +1,42 @@ +#ifndef _ASM_IA64_SN_LEDS_H +#define _ASM_IA64_SN_LEDS_H + +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. + */ + +#include <linux/config.h> +#include <asm/smp.h> +#include <asm/sn/addrs.h> +#include <asm/sn/sn_cpuid.h> +#include <asm/sn/pda.h> + +#ifdef CONFIG_IA64_SGI_SN1 +#define LED0 0xc0000b00100000c0LL /* ZZZ fixme */ +#define LED_CPU_SHIFT 3 +#else +#include <asm/sn/sn2/shub.h> +#define LED0 (LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0)) +#define LED_CPU_SHIFT 16 +#endif + +#define LED_CPU_HEARTBEAT 0x01 +#define LED_CPU_ACTIVITY 0x02 +#define LED_MASK_AUTOTEST 0xfe + +/* + * Basic macros for flashing the LEDS on an SGI, SN1. + */ + +static __inline__ void +set_led_bits(u8 value, u8 mask) +{ + pda.led_state = (pda.led_state & ~mask) | (value & mask); + *pda.led_address = (long) pda.led_state; +} + +#endif /* _ASM_IA64_SN_LEDS_H */ + diff --git a/include/asm-ia64/sn/mca.h b/include/asm-ia64/sn/mca.h new file mode 100644 index 000000000000..4c17af4701a9 --- /dev/null +++ b/include/asm-ia64/sn/mca.h @@ -0,0 +1,128 @@ +/* + * File: mca.h + * Purpose: Machine check handling specific to the SN platform defines + * + * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: + * + * http://www.sgi.com + * + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/NoticeExplan + */ + +#include <linux/config.h> +#include <linux/types.h> +#include <asm/sal.h> +#include <asm/mca.h> + +#ifdef CONFIG_IA64_SGI_SN + +typedef u64 __uint64_t; + +typedef struct { + __uint64_t sh_event_occurred; + __uint64_t sh_first_error; + __uint64_t sh_event_overflow; + __uint64_t sh_pi_first_error; + __uint64_t sh_pi_error_summary; + __uint64_t sh_pi_error_overflow; + __uint64_t sh_pi_error_detail_1; + __uint64_t sh_pi_error_detail_2; + __uint64_t sh_pi_hw_time_stamp; + __uint64_t sh_pi_uncorrected_detail_1; + __uint64_t sh_pi_uncorrected_detail_2; + __uint64_t sh_pi_uncorrected_detail_3; + __uint64_t sh_pi_uncorrected_detail_4; + __uint64_t sh_pi_uncor_time_stamp; + __uint64_t sh_pi_corrected_detail_1; + __uint64_t sh_pi_corrected_detail_2; + __uint64_t sh_pi_corrected_detail_3; + __uint64_t sh_pi_corrected_detail_4; + __uint64_t sh_pi_cor_time_stamp; + __uint64_t sh_mem_error_summary; + __uint64_t sh_mem_error_overflow; + __uint64_t sh_misc_err_hdr_lower; + __uint64_t sh_misc_err_hdr_upper; + __uint64_t sh_dir_uc_err_hdr_lower; + __uint64_t sh_dir_uc_err_hdr_upper; + __uint64_t sh_dir_cor_err_hdr_lower; + __uint64_t sh_dir_cor_err_hdr_upper; + __uint64_t sh_mem_error_mask; + __uint64_t sh_md_uncor_time_stamp; + __uint64_t sh_md_cor_time_stamp; + __uint64_t sh_md_hw_time_stamp; + __uint64_t sh_xn_error_summary; + __uint64_t sh_xn_first_error; + __uint64_t sh_xn_error_overflow; + __uint64_t sh_xniilb_error_summary; + __uint64_t sh_xniilb_first_error; + __uint64_t sh_xniilb_error_overflow; + __uint64_t sh_xniilb_error_detail_1; + __uint64_t sh_xniilb_error_detail_2; + __uint64_t sh_xniilb_error_detail_3; + __uint64_t sh_xnpi_error_summary; + __uint64_t sh_xnpi_first_error; + __uint64_t sh_xnpi_error_overflow; + __uint64_t sh_xnpi_error_detail_1; + __uint64_t sh_xnmd_error_summary; + __uint64_t sh_xnmd_first_error; + __uint64_t sh_xnmd_error_overflow; + __uint64_t sh_xnmd_ecc_err_report; + __uint64_t sh_xnmd_error_detail_1; + __uint64_t sh_lb_error_summary; + __uint64_t sh_lb_first_error; + __uint64_t sh_lb_error_overflow; + __uint64_t sh_lb_error_detail_1; + __uint64_t sh_lb_error_detail_2; + __uint64_t sh_lb_error_detail_3; + __uint64_t sh_lb_error_detail_4; + __uint64_t sh_lb_error_detail_5; +} sal_log_shub_state_t; + +typedef struct { +sal_log_section_hdr_t header; + struct + { + __uint64_t err_status : 1, + guid : 1, + oem_data : 1, + reserved : 61; + } valid; + __uint64_t err_status; + efi_guid_t guid; + __uint64_t shub_nic; + sal_log_shub_state_t shub_state; +} sal_log_plat_info_t; + + +extern void sal_log_plat_print(int header_len, int sect_len, u8 *p_data, prfunc_t prfunc); + +#ifdef platform_plat_specific_err_print +#undef platform_plat_specific_err_print +#endif +#define platform_plat_specific_err_print sal_log_plat_print + +#endif /* CONFIG_IA64_SGI_SN */ diff --git a/include/asm-ia64/sn/mmtimer_private.h b/include/asm-ia64/sn/mmtimer_private.h new file mode 100644 index 000000000000..72ead52c7eb4 --- /dev/null +++ b/include/asm-ia64/sn/mmtimer_private.h @@ -0,0 +1,42 @@ +/* + * Intel Multimedia Timer device interface + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + * + * Helper file for the SN implementation of mmtimers + * + * 11/01/01 - jbarnes - initial revision + */ + +#ifndef _SN_MMTIMER_PRIVATE_H + +#define RTC_BITS 55 /* 55 bits for this implementation */ +#define NUM_COMPARATORS 2 /* two comparison registers in SN1 */ + +/* + * Check for an interrupt and clear the pending bit if + * one is waiting. + */ +#define MMTIMER_INT_PENDING(x) (x ? *(RTC_INT_PENDING_B_ADDR) : *(RTC_INT_PENDING_A_ADDR)) + +/* + * Set interrupts on RTC 'x' to 'v' (true or false) + */ +#define MMTIMER_SET_INT(x,v) (x ? (*(RTC_INT_ENABLED_B_ADDR) = (unsigned long)(v)) : (*(RTC_INT_ENABLED_A_ADDR) = (unsigned long)(v))) + +#define MMTIMER_ENABLE_INT(x) MMTIMER_SET_INT(x, 1) +#define MMTIMER_DISABLE_INT(x) MMTIMER_SET_INT(x, 0) + +typedef struct mmtimer { + spinlock_t timer_lock; + unsigned long periodic; + int signo; + volatile unsigned long *compare; + struct task_struct *process; +} mmtimer_t; + +#endif /* _SN_LINUX_MMTIMER_PRIVATE_H */ diff --git a/include/asm-ia64/sn/mmzone.h b/include/asm-ia64/sn/mmzone.h deleted file mode 100644 index 53740a95de0f..000000000000 --- a/include/asm-ia64/sn/mmzone.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Written by Kanoj Sarcar (kanoj@sgi.com) Jan 2000 - * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com - */ -#ifndef _LINUX_ASM_SN_MMZONE_H -#define _LINUX_ASM_SN_MMZONE_H - -#include <linux/config.h> - -#include <asm/sn/mmzone_sn1.h> -#include <asm/sn/sn_cpuid.h> - -/* - * Memory is conceptually divided into chunks. A chunk is either - * completely present, or else the kernel assumes it is completely - * absent. Each node consists of a number of contiguous chunks. - */ - -#define CHUNKMASK (~(CHUNKSZ - 1)) -#define CHUNKNUM(vaddr) (__pa(vaddr) >> CHUNKSHIFT) -#define PCHUNKNUM(paddr) ((paddr) >> CHUNKSHIFT) - -#define MAXCHUNKS (MAXNODES * MAX_CHUNKS_PER_NODE) - -extern int chunktonid[]; -#define CHUNKTONID(cnum) (chunktonid[cnum]) - -typedef struct plat_pglist_data { - pg_data_t gendata; /* try to keep this first. */ - unsigned long virtstart; - unsigned long size; -} plat_pg_data_t; - -extern plat_pg_data_t plat_node_data[]; - -extern int numa_debug(void); - -/* - * The foll two will move into linux/mmzone.h RSN. - */ -#define NODE_START(n) plat_node_data[(n)].virtstart -#define NODE_SIZE(n) plat_node_data[(n)].size - -#define KVADDR_TO_NID(kaddr) \ - ((CHUNKTONID(CHUNKNUM((kaddr))) != -1) ? (CHUNKTONID(CHUNKNUM((kaddr)))) : \ - (printk("DISCONTIGBUG: %s line %d addr 0x%lx", __FILE__, __LINE__, \ - (unsigned long)(kaddr)), numa_debug())) -#if 0 -#define KVADDR_TO_NID(kaddr) CHUNKTONID(CHUNKNUM((kaddr))) -#endif - -/* These 2 macros should never be used if KVADDR_TO_NID(kaddr) is -1 */ -/* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and returns the mem_map of that node. - */ -#define ADDR_TO_MAPBASE(kaddr) \ - NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr))) - -/* - * Given a kaddr, LOCAL_BASE_ADDR finds the owning node of the memory - * and returns the kaddr corresponding to first physical page in the - * node's mem_map. - */ -#define LOCAL_BASE_ADDR(kaddr) NODE_START(KVADDR_TO_NID(kaddr)) - -#ifdef CONFIG_DISCONTIGMEM - -/* - * Return a pointer to the node data for node n. - * Assume that n is the compact node id. - */ -#define NODE_DATA(n) (&((plat_node_data + (n))->gendata)) - -/* - * NODE_MEM_MAP gives the kaddr for the mem_map of the node. - */ -#define NODE_MEM_MAP(nid) (NODE_DATA((nid))->node_mem_map) - -/* This macro should never be used if KVADDR_TO_NID(kaddr) is -1 */ -#define LOCAL_MAP_NR(kvaddr) \ - (((unsigned long)(kvaddr)-LOCAL_BASE_ADDR((kvaddr))) >> PAGE_SHIFT) -#define MAP_NR_SN1(kaddr) (LOCAL_MAP_NR((kaddr)) + \ - (((unsigned long)ADDR_TO_MAPBASE((kaddr)) - PAGE_OFFSET) / \ - sizeof(mem_map_t))) -#if 0 -#define MAP_NR_VALID(kaddr) (LOCAL_MAP_NR((kaddr)) + \ - (((unsigned long)ADDR_TO_MAPBASE((kaddr)) - PAGE_OFFSET) / \ - sizeof(mem_map_t))) -#define MAP_NR_SN1(kaddr) ((KVADDR_TO_NID(kaddr) == -1) ? (max_mapnr + 1) :\ - MAP_NR_VALID(kaddr)) -#endif - -/* FIXME */ -#define sn1_pte_pagenr(x) MAP_NR_SN1(PAGE_OFFSET + (unsigned long)((pte_val(x)&_PFN_MASK) & PAGE_MASK)) -#define pte_page(pte) (mem_map + sn1_pte_pagenr(pte)) -/* FIXME */ - -#define kern_addr_valid(addr) ((KVADDR_TO_NID((unsigned long)addr) >= \ - numnodes) ? 0 : (test_bit(LOCAL_MAP_NR((addr)), \ - NODE_DATA(KVADDR_TO_NID((unsigned long)addr))->valid_addr_bitmap))) - -#define virt_to_page(kaddr) (mem_map + MAP_NR_SN1(kaddr)) - -#else /* CONFIG_DISCONTIGMEM */ - -#define MAP_NR_SN1(addr) (((unsigned long) (addr) - PAGE_OFFSET) >> PAGE_SHIFT) - -#endif /* CONFIG_DISCONTIGMEM */ - -#define numa_node_id() cpuid_to_cnodeid(smp_processor_id()) - -#endif /* !_LINUX_ASM_SN_MMZONE_H */ diff --git a/include/asm-ia64/sn/mmzone_default.h b/include/asm-ia64/sn/mmzone_default.h deleted file mode 100644 index 084c33d7a956..000000000000 --- a/include/asm-ia64/sn/mmzone_default.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com - */ - -#define MAXNODES 16 -#define MAXNASIDS 16 - -#define CHUNKSZ (8*1024*1024) -#define CHUNKSHIFT 23 /* 2 ^^ CHUNKSHIFT == CHUNKSZ */ - -#define CNODEID_TO_NASID(n) n -#define NASID_TO_CNODEID(n) n - -#define MAX_CHUNKS_PER_NODE 8 - diff --git a/include/asm-ia64/sn/mmzone_sn1.h b/include/asm-ia64/sn/mmzone_sn1.h deleted file mode 100644 index fe19411574e7..000000000000 --- a/include/asm-ia64/sn/mmzone_sn1.h +++ /dev/null @@ -1,105 +0,0 @@ -#ifndef _ASM_IA64_MMZONE_SN1_H -#define _ASM_IA64_MMZONE_SN1_H - -#include <linux/config.h> - -/* - * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com - */ -/* Maximum configuration supported by SNIA hardware. There are other - * restrictions that may limit us to a smaller max configuration. - */ -#define MAXNODES 128 -#define MAXNASIDS 128 - -#define CHUNKSZ (64*1024*1024) -#define CHUNKSHIFT 26 /* 2 ^^ CHUNKSHIFT == CHUNKSZ */ - -extern int cnodeid_map[] ; -extern int nasid_map[] ; - -#define CNODEID_TO_NASID(n) (cnodeid_map[(n)]) -#define NASID_TO_CNODEID(n) (nasid_map[(n)]) - -#define MAX_CHUNKS_PER_NODE 128 - - -/* - * These are a bunch of sn1 hw specific defines. For now, keep it - * in this file. If it gets too diverse we may want to create a - * mmhwdefs_sn1.h - */ - -/* - * Structure of the mem config of the node as a SN1 MI reg - * Medusa supports this reg config. - */ - -typedef struct node_memmap_s -{ - unsigned int b0 :1, /* 0 bank 0 present */ - b1 :1, /* 1 bank 1 present */ - r01 :2, /* 2-3 reserved */ - b01size :4, /* 4-7 Size of bank 0 and 1 */ - b2 :1, /* 8 bank 2 present */ - b3 :1, /* 9 bank 3 present */ - r23 :2, /* 10-11 reserved */ - b23size :4, /* 12-15 Size of bank 2 and 3 */ - b4 :1, /* 16 bank 4 present */ - b5 :1, /* 17 bank 5 present */ - r45 :2, /* 18-19 reserved */ - b45size :4, /* 20-23 Size of bank 4 and 5 */ - b6 :1, /* 24 bank 6 present */ - b7 :1, /* 25 bank 7 present */ - r67 :2, /* 26-27 reserved */ - b67size :4; /* 28-31 Size of bank 6 and 7 */ -} node_memmap_t ; - -#define GBSHIFT 30 -#define MBSHIFT 20 - -/* - * SN1 Arch defined values - */ -#define SN1_MAX_BANK_PER_NODE 8 -#define SN1_BANK_PER_NODE_SHIFT 3 /* derived from SN1_MAX_BANK_PER_NODE */ -#define SN1_NODE_ADDR_SHIFT (GBSHIFT+3) /* 8GB */ -#define SN1_BANK_ADDR_SHIFT (SN1_NODE_ADDR_SHIFT-SN1_BANK_PER_NODE_SHIFT) - -#define SN1_BANK_SIZE_SHIFT (MBSHIFT+6) /* 64 MB */ -#define SN1_MIN_BANK_SIZE_SHIFT SN1_BANK_SIZE_SHIFT - -/* - * BankSize nibble to bank size mapping - * - * 1 - 64 MB - * 2 - 128 MB - * 3 - 256 MB - * 4 - 512 MB - * 5 - 1024 MB (1GB) - */ - -/* fixme - this macro breaks for bsize 6-8 and 0 */ - -#ifdef CONFIG_IA64_SGI_SN1_SIM -/* Support the medusa hack for 8M/16M/32M nodes */ -#define BankSizeBytes(bsize) ((bsize<6) ? (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT)) :\ - (1<<((bsize-9)+MBSHIFT))) -#else -#define BankSizeBytes(bsize) (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT)) -#endif - -#define BankSizeToEFIPages(bsize) ((BankSizeBytes(bsize)) >> 12) - -#define GetPhysAddr(n,b) (((u64)n<<SN1_NODE_ADDR_SHIFT) | \ - ((u64)b<<SN1_BANK_ADDR_SHIFT)) - -#define GetNasId(paddr) ((u64)(paddr) >> SN1_NODE_ADDR_SHIFT) - -#define GetBankId(paddr) \ - (((u64)(paddr) >> SN1_BANK_ADDR_SHIFT) & 7) - -#define SN1_MAX_BANK_SIZE ((u64)BankSizeBytes(5)) -#define SN1_BANK_SIZE_MASK (~(SN1_MAX_BANK_SIZE-1)) - -#endif /* _ASM_IA64_MMZONE_SN1_H */ diff --git a/include/asm-ia64/sn/module.h b/include/asm-ia64/sn/module.h index 81466a222515..18481374b2a8 100644 --- a/include/asm-ia64/sn/module.h +++ b/include/asm-ia64/sn/module.h @@ -1,31 +1,24 @@ -/* $Id$ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_MODULE_H -#define _ASM_SN_MODULE_H +#ifndef _ASM_IA64_SN_MODULE_H +#define _ASM_IA64_SN_MODULE_H #ifdef __cplusplus extern "C" { #endif -#include <linux/config.h> #include <asm/sn/systeminfo.h> #include <asm/sn/klconfig.h> #include <asm/sn/ksys/elsc.h> -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -#ifdef BRINGUP /* max. number of modules? Should be about 300.*/ -#define MODULE_MAX 56 -#endif /* BRINGUP */ +#define MODULE_MAX 128 #define MODULE_MAX_NODES 1 -#endif /* CONFIG_SGI_IP35 */ #define MODULE_HIST_CNT 16 #define MAX_MODULE_LEN 16 @@ -39,8 +32,6 @@ extern "C" { #define MODULE_FORMAT_LONG 2 -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) - /* * Module id format * @@ -134,17 +125,6 @@ extern char brick_types[]; ((_m2)&(MODULE_RACK_MASK|MODULE_BPOS_MASK))) #define MODULE_MATCH(_m1, _m2) (MODULE_CMP((_m1),(_m2)) == 0) -#else - -/* - * Some code that uses this macro will not be conditionally compiled. - */ -#define MODULE_GET_BTCHAR(_m) ('?') -#define MODULE_CMP(_m1, _m2) ((_m1) - (_m2)) -#define MODULE_MATCH(_m1, _m2) (MODULE_CMP((_m1),(_m2)) == 0) - -#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */ - typedef struct module_s module_t; struct module_s { @@ -205,4 +185,4 @@ extern int parse_module_id(char *buffer); } #endif -#endif /* _ASM_SN_MODULE_H */ +#endif /* _ASM_IA64_SN_MODULE_H */ diff --git a/include/asm-ia64/sn/nag.h b/include/asm-ia64/sn/nag.h new file mode 100644 index 000000000000..f1380f7c7873 --- /dev/null +++ b/include/asm-ia64/sn/nag.h @@ -0,0 +1,32 @@ +/* + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2001 Silicon Graphics, Inc. All rights reserved. +*/ + + +#ifndef _ASM_IA64_SN_NAG_H +#define _ASM_IA64_SN_NAG_H + + +#define NAG(mesg...) \ +do { \ + static unsigned int how_broken = 1; \ + static unsigned int threshold = 1; \ + if (how_broken == threshold) { \ + if (threshold < 10000) \ + threshold *= 10; \ + if (how_broken > 1) \ + printk(KERN_WARNING "%u times: ", how_broken); \ + else \ + printk(KERN_WARNING); \ + printk(mesg); \ + } \ + how_broken++; \ +} while (0) + + +#endif /* _ASM_IA64_SN_NAG_H */ diff --git a/include/asm-ia64/sn/nic.h b/include/asm-ia64/sn/nic.h index 09370cb942c1..44eedb02f7da 100644 --- a/include/asm-ia64/sn/nic.h +++ b/include/asm-ia64/sn/nic.h @@ -4,13 +4,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_NIC_H -#define _ASM_SN_NIC_H +#ifndef _ASM_IA64_SN_NIC_H +#define _ASM_IA64_SN_NIC_H #include <asm/types.h> +#include <asm/sn/types.h> +#include <linux/devfs_fs_kernel.h> #define MCR_DATA(x) ((int) ((x) & 1)) #define MCR_DONE(x) ((x) & 2) @@ -125,4 +126,4 @@ extern char *nic_hub_vertex_info(devfs_handle_t vertex); extern nic_vmce_t nic_vmc_add(char *, nic_vmc_func *); extern void nic_vmc_del(nic_vmce_t); -#endif /* _ASM_SN_NIC_H */ +#endif /* _ASM_IA64_SN_NIC_H */ diff --git a/include/asm-ia64/sn/nodemask.h b/include/asm-ia64/sn/nodemask.h deleted file mode 100644 index 8aca79ad88b4..000000000000 --- a/include/asm-ia64/sn/nodemask.h +++ /dev/null @@ -1,330 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam - */ -#ifndef _ASM_SN_NODEMASK_H -#define _ASM_SN_NODEMASK_H - -#if defined(__KERNEL__) || defined(_KMEMUSER) - -#include <linux/config.h> - -#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC -#include <asm/sn/sn1/arch.h> /* needed for MAX_COMPACT_NODES */ -#endif - -#define CNODEMASK_BOOTED_MASK boot_cnodemask -#define CNODEMASK_BIPW 64 - -#if !defined(SN0XXL) && !defined(CONFIG_SGI_IP35) && !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC) - /* MAXCPUS 128p (64 nodes) or less */ - -#define CNODEMASK_SIZE 1 -typedef uint64_t cnodemask_t; - -#define CNODEMASK_WORD(p,w) (p) -#define CNODEMASK_SET_WORD(p,w,val) (p) = val -#define CNODEMASK_CLRALL(p) (p) = 0 -#define CNODEMASK_SETALL(p) (p) = ~((cnodemask_t)0) -#define CNODEMASK_IS_ZERO(p) ((p) == 0) -#define CNODEMASK_IS_NONZERO(p) ((p) != 0) -#define CNODEMASK_NOTEQ(p, q) ((p) != (q)) -#define CNODEMASK_EQ(p, q) ((p) == (q)) -#define CNODEMASK_LSB_ISONE(p) ((p) & 0x1ULL) - -#define CNODEMASK_ZERO() ((cnodemask_t)0) -#define CNODEMASK_CVTB(bit) (1ULL << (bit)) -#define CNODEMASK_SETB(p, bit) ((p) |= 1ULL << (bit)) -#define CNODEMASK_CLRB(p, bit) ((p) &= ~(1ULL << (bit))) -#define CNODEMASK_TSTB(p, bit) ((p) & (1ULL << (bit))) - -#define CNODEMASK_SETM(p, q) ((p) |= (q)) -#define CNODEMASK_CLRM(p, q) ((p) &= ~(q)) -#define CNODEMASK_ANDM(p, q) ((p) &= (q)) -#define CNODEMASK_TSTM(p, q) ((p) & (q)) - -#define CNODEMASK_CPYNOTM(p, q) ((p) = ~(q)) -#define CNODEMASK_CPY(p, q) ((p) = (q)) -#define CNODEMASK_ORNOTM(p, q) ((p) |= ~(q)) -#define CNODEMASK_SHIFTL(p) ((p) <<= 1) -#define CNODEMASK_SHIFTR(p) ((p) >>= 1) -#define CNODEMASK_SHIFTL_PTR(p) (*(p) <<= 1) -#define CNODEMASK_SHIFTR_PTR(p) (*(p) >>= 1) - -/* Atomically set or clear a particular bit */ -#define CNODEMASK_ATOMSET_BIT(p, bit) atomicSetUlong((cnodemask_t *)&(p), (1ULL<<(bit))) -#define CNODEMASK_ATOMCLR_BIT(p, bit) atomicClearUlong((cnodemask_t *)&(p), (1ULL<<(bit))) - -/* Atomically set or clear a collection of bits */ -#define CNODEMASK_ATOMSET(p, q) atomicSetUlong((cnodemask_t *)&(p), q) -#define CNODEMASK_ATOMCLR(p, q) atomicClearUlong((cnodemask_t *)&(p), q) - -/* Atomically set or clear a collection of bits, returning the old value */ -#define CNODEMASK_ATOMSET_MASK(__old, p, q) { \ - (__old) = atomicSetUlong((cnodemask_t *)&(p), q); \ -} -#define CNODEMASK_ATOMCLR_MASK(__old, p, q) { \ - (__old) = atomicClearUlong((cnodemask_t *)&(p),q); \ -} - -#define CNODEMASK_FROM_NUMNODES(n) ((~(cnodemask_t)0)>>(CNODEMASK_BIPW-(n))) - -#else /* SN0XXL || SN1 - MAXCPUS > 128 */ - -#define CNODEMASK_SIZE (MAX_COMPACT_NODES / CNODEMASK_BIPW) - -typedef struct { - uint64_t _bits[CNODEMASK_SIZE]; -} cnodemask_t; - -#define CNODEMASK_WORD(p,w) \ - ((w >= 0 && w < CNODEMASK_SIZE) ? (p)._bits[(w)] : 0) -#define CNODEMASK_SET_WORD(p,w,val) { \ - if (w >= 0 && w < CNODEMASK_SIZE) \ - (p)._bits[(w)] = val; \ -} - -#define CNODEMASK_CLRALL(p) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) \ - (p)._bits[i] = 0; \ -} - -#define CNODEMASK_SETALL(p) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) \ - (p)._bits[i] = ~(0); \ -} - -#define CNODEMASK_LSB_ISONE(p) ((p)._bits[0] & 0x1ULL) - - -#define CNODEMASK_SETM(p,q) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) \ - (p)._bits[i] |= ((q)._bits[i]); \ -} - -#define CNODEMASK_CLRM(p,q) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) \ - (p)._bits[i] &= ~((q)._bits[i]); \ -} - -#define CNODEMASK_ANDM(p,q) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) \ - (p)._bits[i] &= ((q)._bits[i]); \ -} - -#define CNODEMASK_CPY(p, q) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) \ - (p)._bits[i] = (q)._bits[i]; \ -} - -#define CNODEMASK_CPYNOTM(p,q) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) \ - (p)._bits[i] = ~((q)._bits[i]); \ -} - -#define CNODEMASK_ORNOTM(p,q) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) \ - (p)._bits[i] |= ~((q)._bits[i]); \ -} - -#define CNODEMASK_INDEX(bit) ((bit) >> 6) -#define CNODEMASK_SHFT(bit) ((bit) & 0x3f) - - -#define CNODEMASK_SETB(p, bit) \ - (p)._bits[CNODEMASK_INDEX(bit)] |= (1ULL << CNODEMASK_SHFT(bit)) - - -#define CNODEMASK_CLRB(p, bit) \ - (p)._bits[CNODEMASK_INDEX(bit)] &= ~(1ULL << CNODEMASK_SHFT(bit)) - - -#define CNODEMASK_TSTB(p, bit) \ - ((p)._bits[CNODEMASK_INDEX(bit)] & (1ULL << CNODEMASK_SHFT(bit))) - -/** Probably should add atomic update for entire cnodemask_t struct **/ - -/* Atomically set or clear a particular bit */ -#define CNODEMASK_ATOMSET_BIT(p, bit) \ - (atomicSetUlong((unsigned long *)&(p)._bits[CNODEMASK_INDEX(bit)], (1ULL << CNODEMASK_SHFT(bit)))); -#define CNODEMASK_ATOMCLR_BIT(__old, p, bit) \ - (atomicClearUlong((unsigned long *)&(p)._bits[CNODEMASK_INDEX(bit)], (1ULL << CNODEMASK_SHFT(bit)))); - -/* Atomically set or clear a collection of bits */ -#define CNODEMASK_ATOMSET(p, q) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) { \ - atomicSetUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]); \ - } \ -} -#define CNODEMASK_ATOMCLR(p, q) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) { \ - atomicClearUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]); \ - } \ -} - -/* Atomically set or clear a collection of bits, returning the old value */ -#define CNODEMASK_ATOMSET_MASK(__old, p, q) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) { \ - (__old)._bits[i] = \ - atomicSetUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]); \ - } \ -} -#define CNODEMASK_ATOMCLR_MASK(__old, p, q) { \ - int i; \ - \ - for (i = 0 ; i < CNODEMASK_SIZE ; i++) { \ - (__old)._bits[i] = \ - atomicClearUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]); \ - } \ -} - -__inline static cnodemask_t CNODEMASK_CVTB(int bit) -{ - cnodemask_t __tmp; - CNODEMASK_CLRALL(__tmp); - CNODEMASK_SETB(__tmp,bit); - return(__tmp); -} - - -__inline static cnodemask_t CNODEMASK_ZERO(void) -{ - cnodemask_t __tmp; - CNODEMASK_CLRALL(__tmp); - return(__tmp); -} - -__inline static int CNODEMASK_IS_ZERO (cnodemask_t p) -{ - int i; - - for (i = 0 ; i < CNODEMASK_SIZE ; i++) - if (p._bits[i] != 0) - return 0; - return 1; -} - -__inline static int CNODEMASK_IS_NONZERO (cnodemask_t p) -{ - int i; - - for (i = 0 ; i < CNODEMASK_SIZE ; i++) - if (p._bits[i] != 0) - return 1; - return 0; -} - -__inline static int CNODEMASK_NOTEQ (cnodemask_t p, cnodemask_t q) -{ - int i; - - for (i = 0 ; i < CNODEMASK_SIZE ; i++) - if (p._bits[i] != q._bits[i]) - return 1; - return 0; -} - -__inline static int CNODEMASK_EQ (cnodemask_t p, cnodemask_t q) -{ - int i; - - for (i = 0 ; i < CNODEMASK_SIZE ; i++) - if (p._bits[i] != q._bits[i]) - return 0; - return 1; -} - - -__inline static int CNODEMASK_TSTM (cnodemask_t p, cnodemask_t q) -{ - int i; - - for (i = 0 ; i < CNODEMASK_SIZE ; i++) - if (p._bits[i] & q._bits[i]) - return 1; - return 0; -} - -__inline static void CNODEMASK_SHIFTL_PTR (cnodemask_t *p) -{ - int i; - uint64_t upper; - - /* - * shift words starting with the last word - * of the vector and work backward to the first - * word updating the low order bits with the - * high order bit of the prev word. - */ - for (i=(CNODEMASK_SIZE-1); i > 0; --i) { - upper = (p->_bits[i-1] & (1ULL<<(CNODEMASK_BIPW-1))) ? 1 : 0; - p->_bits[i] <<= 1; - p->_bits[i] |= upper; - } - p->_bits[i] <<= 1; -} - -__inline static void CNODEMASK_SHIFTR_PTR (cnodemask_t *p) -{ - int i; - uint64_t lower; - - /* - * shift words starting with the first word - * of the vector and work forward to the last - * word updating the high order bit with the - * low order bit of the next word. - */ - for (i=0; i < (CNODEMASK_SIZE-2); ++i) { - lower = (p->_bits[i+1] & (0x1)) ? 1 : 0; - p->_bits[i] >>= 1; - p->_bits[i] |= (lower<<((CNODEMASK_BIPW-1))); - } - p->_bits[i] >>= 1; -} - -__inline static cnodemask_t CNODEMASK_FROM_NUMNODES(int n) -{ - cnodemask_t __tmp; - int i; - CNODEMASK_CLRALL(__tmp); - for (i=0; i<n; i++) { - CNODEMASK_SETB(__tmp, i); - } - return(__tmp); -} - -#endif /* SN0XXL || SN1 */ - -extern cnodemask_t boot_cnodemask; - -#endif /* __KERNEL__ || _KMEMUSER */ - -#endif /* _ASM_SN_NODEMASK_H */ diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h index 320e88871b06..b999dbd8451d 100644 --- a/include/asm-ia64/sn/nodepda.h +++ b/include/asm-ia64/sn/nodepda.h @@ -1,32 +1,28 @@ -/* $Id$ - * +/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_NODEPDA_H -#define _ASM_SN_NODEPDA_H +#ifndef _ASM_IA64_SN_NODEPDA_H +#define _ASM_IA64_SN_NODEPDA_H -#ifdef __cplusplus -extern "C" { -#endif #include <linux/config.h> - -#include <asm/sn/agent.h> +#include <asm/irq.h> #include <asm/sn/intr.h> #include <asm/sn/router.h> -#include <asm/sn/synergy.h> -/* #include <SN/klkernvars.h> */ -#ifdef LATER -typedef struct module_s module_t; /* Avoids sys/SN/module.h */ -#else +#if defined(CONFIG_IA64_SGI_SN1) +#include <asm/sn/sn1/synergy.h> +#endif +#include <asm/sn/pda.h> #include <asm/sn/module.h> +#include <asm/sn/bte.h> + +#if defined(CONFIG_IA64_SGI_SN1) +#include <asm/sn/sn1/hubstat.h> #endif -/* #include <SN/slotnum.h> */ /* * NUMA Node-Specific Data structures are defined in this file. @@ -37,26 +33,16 @@ typedef struct module_s module_t; /* Avoids sys/SN/module.h */ /* * Subnode PDA structures. Each node needs a few data structures that * correspond to the PIs on the HUB chip that supports the node. - * - * WARNING!!!! 6.5.x compatibility requirements prevent us from - * changing or reordering fields in the following structure for IP27. - * It is essential that the data mappings not change for IP27 platforms. - * It is OK to add fields that are IP35 specific if they are under #ifdef IP35. */ +#if defined(CONFIG_IA64_SGI_SN1) struct subnodepda_s { intr_vecblk_t intr_dispatch0; intr_vecblk_t intr_dispatch1; - uint64_t next_prof_timeout; - int prof_count; }; - typedef struct subnodepda_s subnode_pda_t; -struct ptpool_s; - -#if defined(CONFIG_IA64_SGI_SYNERGY_PERF) struct synergy_perf_s; #endif @@ -65,8 +51,6 @@ struct synergy_perf_s; * Node-specific data structure. * * One of these structures is allocated on each node of a NUMA system. - * Non-NUMA systems are considered to be systems with one node, and - * hence there will be one of this structure for the entire system. * * This structure provides a convenient way of keeping together * all per-node data structures. @@ -74,119 +58,13 @@ struct synergy_perf_s; -#ifdef LATER -/* - * The following structure is contained in the nodepda & contains - * a lock & queue-head for sanon pages that belong to the node. - * See the anon manager for more details. - */ -typedef struct { - lock_t sal_lock; - plist_t sal_listhead; -} sanon_list_head_t; -#endif struct nodepda_s { -#ifdef NUMA_BASE - - /* - * Pointer to this node's copy of Nodepdaindr - */ - struct nodepda_s **pernode_pdaindr; - - /* - * Data used for migration control - */ - struct migr_control_data_s *mcd; - - /* - * Data used for replication control - */ - struct repl_control_data_s *rcd; - - /* - * Numa statistics - */ - struct numa_stats_s *numa_stats; - - /* - * Load distribution - */ - uint memfit_assign; - - /* - * New extended memory reference counters - */ - void *migr_refcnt_counterbase; - void *migr_refcnt_counterbuffer; - size_t migr_refcnt_cbsize; - int migr_refcnt_numsets; - - /* - * mem_tick quiescing lock - */ - uint mem_tick_lock; - - /* - * Migration candidate set - * by migration prologue intr handler - */ - uint64_t migr_candidate; - - /* - * Each node gets its own syswait counter to remove contention - * on the global one. - */ -#ifdef LATER - struct syswait syswait; -#endif - -#endif /* NUMA_BASE */ - /* - * Node-specific Zone structures. - */ -#ifdef LATER - zoneset_element_t node_zones; - pg_data_t node_pg_data; /* VM page data structures */ - plist_t error_discard_plist; -#endif - uint error_discard_count; - uint error_page_count; - uint error_cleaned_count; - spinlock_t error_discard_lock; - /* Information needed for SN Hub chip interrupt handling. */ - subnode_pda_t snpda[NUM_SUBNODES]; - /* Distributed kernel support */ -#ifdef LATER - kern_vars_t kern_vars; -#endif - /* Vector operation support */ - /* Change this to a sleep lock? */ - spinlock_t vector_lock; - /* State of the vector unit for this node */ - char vector_unit_busy; cpuid_t node_first_cpu; /* Starting cpu number for node */ - ushort node_num_cpus; /* Number of cpus present */ - - /* node utlbmiss info */ - spinlock_t node_utlbswitchlock; - volatile cpumask_t node_utlbmiss_flush; - volatile signed char node_need_utlbmiss_patch; - volatile char node_utlbmiss_patched; - nodepda_router_info_t *npda_rip_first; - nodepda_router_info_t **npda_rip_last; - int dependent_routers; - -#if defined(CONFIG_IA64_SGI_SYNERGY_PERF) - int synergy_perf_enabled; - int synergy_perf_freq; - spinlock_t synergy_perf_lock; - uint64_t synergy_inactive_intervals; - uint64_t synergy_active_intervals; - struct synergy_perf_s *synergy_perf_data; - struct synergy_perf_s *synergy_perf_first; /* reporting consistency .. */ -#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */ + /* WARNING: no guarantee that */ + /* the second cpu on a node is */ + /* node_first_cpu+1. */ devfs_handle_t xbow_vhdl; nasid_t xbow_peer; /* NASID of our peer hub on xbow */ @@ -194,84 +72,67 @@ struct nodepda_s { slotid_t slotdesc; moduleid_t module_id; /* Module ID (redundant local copy) */ module_t *module; /* Pointer to containing module */ - int hub_chip_rev; /* Rev of my Hub chip */ - char nasid_mask[NASID_MASK_BYTES]; - /* Need a copy of the nasid mask - * on every node */ xwidgetnum_t basew_id; devfs_handle_t basew_xc; - spinlock_t fprom_lock; - char ni_error_print; /* For printing ni error state - * only once during system panic - */ -#ifdef LATER - md_perf_monitor_t node_md_perfmon; - hubstat_t hubstats; int hubticks; - sbe_info_t *sbe_info; /* ECC single-bit error statistics */ -#endif /* LATER */ - int huberror_ticks; - - router_queue_t *visited_router_q; - router_queue_t *bfs_router_q; - /* Used for router traversal */ -#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) - router_map_ent_t router_map[MAX_RTR_BREADTH]; -#endif - int num_routers; /* Total routers in the system */ + int num_routers; /* XXX not setup! Total routers in the system */ - char membank_flavor; - /* Indicates what sort of memory - * banks are present on this node - */ char *hwg_node_name; /* hwgraph node name */ - - struct widget_info_t *widget_info; /* Node as xtalk widget */ devfs_handle_t node_vertex; /* Hwgraph vertex for this node */ void *pdinfo; /* Platform-dependent per-node info */ - uint64_t *dump_stack; /* Dump stack during nmi handling */ - int dump_count; /* To allow only one cpu-per-node */ -#ifdef LATER - io_perf_monitor_t node_io_perfmon; -#endif - /* - * Each node gets its own pdcount counter to remove contention - * on the global one. - */ - - int pdcount; /* count of pdinserted pages */ -#ifdef NUMA_BASE - void *cached_global_pool; /* pointer to cached vmpool */ -#endif /* NUMA_BASE */ + nodepda_router_info_t *npda_rip_first; + nodepda_router_info_t **npda_rip_last; -#ifdef LATER - sanon_list_head_t sanon_list_head; /* head for sanon pages */ -#endif -#ifdef NUMA_BASE - struct ptpool_s *ptpool; /* ptpool for this node */ -#endif /* NUMA_BASE */ /* * The BTEs on this node are shared by the local cpus */ -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) -#ifdef LATER - bteinfo_t *node_bte_info[BTES_PER_NODE]; -#endif -#endif + bteinfo_t node_bte_info[BTES_PER_NODE]; + +#if defined(CONFIG_IA64_SGI_SN1) + subnode_pda_t snpda[NUM_SUBNODES]; + /* + * New extended memory reference counters + */ + void *migr_refcnt_counterbase; + void *migr_refcnt_counterbuffer; + size_t migr_refcnt_cbsize; + int migr_refcnt_numsets; + hubstat_t hubstats; + int synergy_perf_enabled; + int synergy_perf_freq; + spinlock_t synergy_perf_lock; + uint64_t synergy_inactive_intervals; + uint64_t synergy_active_intervals; + struct synergy_perf_s *synergy_perf_data; + struct synergy_perf_s *synergy_perf_first; /* reporting consistency .. */ +#endif /* CONFIG_IA64_SGI_SN1 */ + + /* + * Array of pointers to the nodepdas for each node. + */ + struct nodepda_s *pernode_pdaindr[MAX_COMPACT_NODES]; + }; typedef struct nodepda_s nodepda_t; +#ifdef CONFIG_IA64_SGI_SN2 +struct irqpda_s { + int num_irq_used; + char irq_flags[NR_IRQS]; +}; + +typedef struct irqpda_s irqpda_t; + +#endif /* CONFIG_IA64_SGI_SN2 */ + -#define NODE_MODULEID(_node) (NODEPDA(_node)->module_id) -#define NODE_SLOTID(_node) (NODEPDA(_node)->slotdesc) -#ifdef NUMA_BASE /* * Access Functions for node PDA. * Since there is one nodepda for each node, we need a convenient mechanism @@ -279,180 +140,49 @@ typedef struct nodepda_s nodepda_t; * The next set of definitions provides this. * Routines are expected to use * - * nodepda -> to access PDA for the node on which code is running - * subnodepda -> to access subnode PDA for the node on which code is running + * nodepda -> to access node PDA for the node on which code is running + * subnodepda -> to access subnode PDA for the subnode on which code is running * - * NODEPDA(x) -> to access node PDA for cnodeid 'x' - * SUBNODEPDA(x,s) -> to access subnode PDA for cnodeid/slice 'x' - */ - -#ifdef LATER -#define nodepda private.p_nodepda /* Ptr to this node's PDA */ -#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC -#define subnodepda private.p_subnodepda /* Ptr to this node's subnode PDA */ -#endif - -#else -/* - * Until we have a shared node local area defined, do it this way .. - * like in Caliase space. See above. - */ -extern nodepda_t *nodepda; -extern subnode_pda_t *subnodepda; -#endif - -/* - * Nodepdaindr[] - * This is a private data structure for use only in early initialization. - * All users of nodepda should use the macro NODEPDA(nodenum) to get - * the suitable nodepda structure. - * This macro has the advantage of not requiring #ifdefs for NUMA and - * non-NUMA code. - */ -extern nodepda_t *Nodepdaindr[]; -/* - * NODEPDA_GLOBAL(x) macro should ONLY be used during early initialization. - * Once meminit is complete, NODEPDA(x) is ready to use. - * During early init, the system fills up Nodepdaindr. By the time we - * are in meminit(), all nodepdas are initialized, and hence - * we can fill up the node_pdaindr array in each nodepda structure. + * NODEPDA(cnode) -> to access node PDA for cnodeid + * SUBNODEPDA(cnode,sn) -> to access subnode PDA for cnodeid/subnode */ -#define NODEPDA_GLOBAL(x) Nodepdaindr[x] -/* - * Returns a pointer to a given node's nodepda. - */ -#define NODEPDA(x) (nodepda->pernode_pdaindr[x]) +#define nodepda pda.p_nodepda /* Ptr to this node's PDA */ +#define NODEPDA(cnode) (nodepda->pernode_pdaindr[cnode]) -/* - * Returns a pointer to a given node/slice's subnodepda. - * SUBNODEPDA(cnode, subnode) - uses cnode as first arg - * SNPDA(npda, subnode) - uses pointer to nodepda as first arg - */ -#define SUBNODEPDA(x,sn) (&nodepda->pernode_pdaindr[x]->snpda[sn]) +#if defined(CONFIG_IA64_SGI_SN1) +#define subnodepda pda.p_subnodepda /* Ptr to this node's subnode PDA */ +#define SUBNODEPDA(cnode,sn) (&(NODEPDA(cnode)->snpda[sn])) #define SNPDA(npda,sn) (&(npda)->snpda[sn]) +#endif -#define NODEPDA_ERROR_FOOTPRINT(node, cpu) \ - (&(NODEPDA(node)->error_stamp[cpu])) -#define NODEPDA_MDP_MON(node) (&(NODEPDA(node)->node_md_perfmon)) -#define NODEPDA_IOP_MON(node) (&(NODEPDA(node)->node_io_perfmon)) /* * Macros to access data structures inside nodepda */ -#if NUMA_MIGR_CONTROL -#define NODEPDA_MCD(node) (NODEPDA(node)->mcd) -#endif /* NUMA_MIGR_CONTROL */ - -#if NUMA_REPL_CONTROL -#define NODEPDA_RCD(node) (NODEPDA(node)->rcd) -#endif /* NUMA_REPL_CONTROL */ +#define NODE_MODULEID(cnode) (NODEPDA(cnode)->module_id) +#define NODE_SLOTID(cnode) (NODEPDA(cnode)->slotdesc) -#if (NUMA_MIGR_CONTROL || NUMA_REPL_CONTROL) -#define NODEPDA_LRS(node) (NODEPDA(node)->lrs) -#endif /* (NUMA_MIGR_CONTROL || NUMA_REPL_CONTROL) */ -/* - * Exported functions - */ -extern nodepda_t *nodepda_alloc(void); - -#else /* !NUMA_BASE */ /* - * For a single-node system we will just have one global nodepda pointer - * allocated at startup. The global nodepda will point to this nodepda - * structure. + * Quickly convert a compact node ID into a hwgraph vertex */ -extern nodepda_t *Nodepdaindr; +#define cnodeid_to_vertex(cnodeid) (NODEPDA(cnodeid)->node_vertex) -/* - * On non-NUMA systems, NODEPDA_GLOBAL and NODEPDA macros collapse to - * be the same. - */ -#define NODEPDA_GLOBAL(x) Nodepdaindr /* - * Returns a pointer to a given node's nodepda. + * Check if given a compact node id the corresponding node has all the + * cpus disabled. */ -#define NODEPDA(x) Nodepdaindr +#define is_headless_node(cnode) ((cnode == CNODEID_NONE) || \ + (node_data(cnode)->active_cpu_count == 0)) /* - * nodepda can also be defined as private.p_nodepda. - * But on non-NUMA systems, there is only one nodepda, and there is - * no reason to go through the PDA to access this pointer. - * Hence nodepda aliases to the global nodepda directly. - * - * Routines should use nodepda to access the local node's PDA. - */ -#define nodepda (Nodepdaindr) - -#endif /* NUMA_BASE */ - -/* Quickly convert a compact node ID into a hwgraph vertex */ -#define cnodeid_to_vertex(cnodeid) (NODEPDA(cnodeid)->node_vertex) - - -/* Check if given a compact node id the corresponding node has all the - * cpus disabled. - */ -#define is_headless_node(_cnode) ((_cnode == CNODEID_NONE) || \ - (CNODE_NUM_CPUS(_cnode) == 0)) -/* Check if given a node vertex handle the corresponding node has all the + * Check if given a node vertex handle the corresponding node has all the * cpus disabled. */ #define is_headless_node_vertex(_nodevhdl) \ is_headless_node(nodevertex_to_cnodeid(_nodevhdl)) -#ifdef __cplusplus -} -#endif -#ifdef NUMA_BASE -/* - * To remove contention on the global syswait counter each node will have - * its own. Each clock tick the clock cpu will re-calculate the global - * syswait counter by summing from each of the nodes. The other cpus will - * continue to read the global one during their clock ticks. This does - * present a problem when a thread increments the count on one node and wakes - * up on a different node and decrements it there. Eventually the count could - * overflow if this happens continually for a long period. To prevent this - * second_thread() periodically preserves the current syswait state and - * resets the counters. - */ -#define ADD_SYSWAIT(_field) atomicAddInt(&nodepda->syswait._field, 1) -#define SUB_SYSWAIT(_field) atomicAddInt(&nodepda->syswait._field, -1) -#else -#define ADD_SYSWAIT(_field) \ -{ \ - ASSERT(syswait._field >= 0); \ - atomicAddInt(&syswait._field, 1); \ -} -#define SUB_SYSWAIT(_field) \ -{ \ - ASSERT(syswait._field > 0); \ - atomicAddInt(&syswait._field, -1); \ -} -#endif /* NUMA_BASE */ - -#ifdef NUMA_BASE -/* - * Another global variable to remove contention from: pdcount. - * See above comments for SYSWAIT. - */ -#define ADD_PDCOUNT(_n) \ -{ \ - atomicAddInt(&nodepda->pdcount, _n); \ - if (_n > 0 && !pdflag) \ - pdflag = 1; \ -} -#else -#define ADD_PDCOUNT(_n) \ -{ \ - ASSERT(&pdcount >= 0); \ - atomicAddInt(&pdcount, _n); \ - if (_n > 0 && !pdflag) \ - pdflag = 1; \ -} -#endif /* NUMA_BASE */ - -#endif /* _ASM_SN_NODEPDA_H */ +#endif /* _ASM_IA64_SN_NODEPDA_H */ diff --git a/include/asm-ia64/sn/pci/bridge.h b/include/asm-ia64/sn/pci/bridge.h index a83d90ee67fe..4982e75f0107 100644 --- a/include/asm-ia64/sn/pci/bridge.h +++ b/include/asm-ia64/sn/pci/bridge.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_BRIDGE_H #define _ASM_SN_PCI_BRIDGE_H @@ -53,7 +52,7 @@ * Bridge address map */ -#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) +#ifndef __ASSEMBLY__ #ifdef __cplusplus extern "C" { @@ -373,7 +372,7 @@ typedef struct bridge_err_cmdword_s { ds:2, /* Data size */ gbr:1, /* GBR enable */ vbpm:1, /* VBPM message */ - error:1, /* Error occurred */ + error:1, /* Error occurred */ barr:1, /* Barrier op */ rsvd:8; } berr_st; @@ -638,7 +637,7 @@ typedef volatile struct bridge_s { #define berr_field berr_un.berr_st -#endif /* LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /* * The values of these macros can and should be crosschecked @@ -903,10 +902,10 @@ typedef volatile struct bridge_s { #define BRIDGE_DEVIO_2MB 0x00200000 /* Device IO Offset (0..1) */ #define BRIDGE_DEVIO_1MB 0x00100000 /* Device IO Offset (2..7) */ -#if LANGUAGE_C +#ifndef __ASSEMBLY__ #define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB) -#endif /* LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ #define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */ @@ -971,6 +970,10 @@ typedef volatile struct bridge_s { #define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11) #define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10) #define BRIDGE_CTRL_SYS_END (0x1 << 9) +#define BRIDGE_CTRL_BUS_SPEED(n) ((n) << 4) +#define BRIDGE_CTRL_BUS_SPEED_MASK (BRIDGE_CTRL_BUS_SPEED(0x3)) +#define BRIDGE_CTRL_BUS_SPEED_33 0x00 +#define BRIDGE_CTRL_BUS_SPEED_66 0x10 #define BRIDGE_CTRL_MAX_TRANS(n) ((n) << 4) #define BRIDGE_CTRL_MAX_TRANS_MASK (BRIDGE_CTRL_MAX_TRANS(0x1f)) #define BRIDGE_CTRL_WIDGET_ID(n) ((n) << 0) @@ -1296,14 +1299,14 @@ typedef volatile struct bridge_s { #define PCI32_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE #define PCI32_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE -#if LANGUAGE_C +#ifndef __ASSEMBLY__ #define IS_PCI32_LOCAL(x) ((uint64_t)(x) < PCI32_MAPPED_BASE) #define IS_PCI32_MAPPED(x) ((uint64_t)(x) < PCI32_DIRECT_BASE && \ (uint64_t)(x) >= PCI32_MAPPED_BASE) #define IS_PCI32_DIRECT(x) ((uint64_t)(x) >= PCI32_MAPPED_BASE) #define IS_PCI64(x) ((uint64_t)(x) >= PCI64_BASE) -#endif /* LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /* * The GIO address space. @@ -1318,13 +1321,13 @@ typedef volatile struct bridge_s { #define GIO_MAPPED_BASE BRIDGE_DMA_MAPPED_BASE #define GIO_DIRECT_BASE BRIDGE_DMA_DIRECT_BASE -#if LANGUAGE_C +#ifndef __ASSEMBLY__ #define IS_GIO_LOCAL(x) ((uint64_t)(x) < GIO_MAPPED_BASE) #define IS_GIO_MAPPED(x) ((uint64_t)(x) < GIO_DIRECT_BASE && \ (uint64_t)(x) >= GIO_MAPPED_BASE) #define IS_GIO_DIRECT(x) ((uint64_t)(x) >= GIO_MAPPED_BASE) -#endif /* LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /* PCI to xtalk mapping */ @@ -1347,7 +1350,7 @@ typedef volatile struct bridge_s { #define PCI64_ATTR_RMF_MASK 0x00ff000000000000 #define PCI64_ATTR_RMF_SHFT 48 -#if LANGUAGE_C +#ifndef __ASSEMBLY__ /* Address translation entry for mapped pci32 accesses */ typedef union ate_u { uint64_t ent; @@ -1375,7 +1378,7 @@ typedef union ate_u { uint64_t valid:1; } field; } ate_t; -#endif /* LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ #define ATE_V (1 << 0) #define ATE_CO (1 << 1) @@ -1401,7 +1404,7 @@ typedef union ate_u { #define is_xbridge(bridge) \ (XWIDGET_PART_NUM(bridge->b_wid_id) == XBRIDGE_WIDGET_PART_NUM) -#if LANGUAGE_C +#ifndef __ASSEMBLY__ /* ======================================================================== */ diff --git a/include/asm-ia64/sn/pci/pci_bus_cvlink.h b/include/asm-ia64/sn/pci/pci_bus_cvlink.h index 5b4f2129d5be..d99ba4b0d4e8 100644 --- a/include/asm-ia64/sn/pci/pci_bus_cvlink.h +++ b/include/asm-ia64/sn/pci/pci_bus_cvlink.h @@ -4,12 +4,36 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_CVLINK_H #define _ASM_SN_PCI_CVLINK_H +#include <asm/sn/types.h> +#include <asm/sn/hack.h> +#include <asm/sn/sgi.h> +#include <asm/sn/driver.h> +#include <asm/sn/iograph.h> +#include <asm/param.h> +#include <asm/sn/pio.h> +#include <asm/sn/xtalk/xwidget.h> +#include <asm/sn/sn_private.h> +#include <asm/sn/addrs.h> +#include <asm/sn/invent.h> +#include <asm/sn/hcl.h> +#include <asm/sn/hcl_util.h> +#include <asm/sn/intr.h> +#include <asm/sn/xtalk/xtalkaddrs.h> +#include <asm/sn/klconfig.h> +#include <asm/sn/io.h> + +#include <asm/sn/pci/pciio.h> +#include <asm/sn/pci/pcibr.h> +#include <asm/sn/pci/pcibr_private.h> + +#define MAX_PCI_XWIDGET 256 +#define MAX_ATE_MAPS 1024 + #define SET_PCIA64(dev) \ (((struct sn1_device_sysdata *)((dev)->sysdata))->isa64) = 1 #define IS_PCIA64(dev) (((dev)->dma_mask == 0xffffffffffffffffUL) || \ @@ -17,6 +41,12 @@ #define IS_PCI32G(dev) ((dev)->dma_mask >= 0xffffffff) #define IS_PCI32L(dev) ((dev)->dma_mask < 0xffffffff) +#define PCIDEV_VERTEX(pci_dev) \ + (((struct sn1_device_sysdata *)((pci_dev)->sysdata))->vhdl) + +#define PCIBUS_VERTEX(pci_bus) \ + (((struct sn1_widget_sysdata *)((pci_bus)->sysdata))->vhdl) + struct sn1_widget_sysdata { devfs_handle_t vhdl; }; @@ -24,6 +54,8 @@ struct sn1_widget_sysdata { struct sn1_device_sysdata { devfs_handle_t vhdl; int isa64; + volatile unsigned int *dma_buf_sync; + volatile unsigned int *xbow_buf_sync; }; struct sn1_dma_maps_s{ diff --git a/include/asm-ia64/sn/pci/pci_defs.h b/include/asm-ia64/sn/pci/pci_defs.h index d12ad0d5827a..963aed2b7050 100644 --- a/include/asm-ia64/sn/pci/pci_defs.h +++ b/include/asm-ia64/sn/pci/pci_defs.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCI_DEFS_H #define _ASM_SN_PCI_PCI_DEFS_H diff --git a/include/asm-ia64/sn/pci/pciba.h b/include/asm-ia64/sn/pci/pciba.h index 3a5dbc4d14ba..e7acd399b6ba 100644 --- a/include/asm-ia64/sn/pci/pciba.h +++ b/include/asm-ia64/sn/pci/pciba.h @@ -1,24 +1,33 @@ -/* $Id$ +/* + * This file is subject to the terms and conditions of the GNU General + * Public License. See the file "COPYING" in the main directory of + * this archive for more details. * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * Copyright (C) 1997, 2001 Silicon Graphics, Inc. All rights reserved. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam */ + #ifndef _ASM_SN_PCI_PCIBA_H #define _ASM_SN_PCI_PCIBA_H -/* - * These are all the HACKS from ioccom.h .. - */ -#define IOCPARM_MASK 0xff /* parameters must be < 256 bytes */ -#define IOC_VOID 0x20000000 /* no parameters */ +#include <linux/ioctl.h> +#include <linux/types.h> +#include <linux/pci.h> + +/* for application compatibility with IRIX (why do I bother?) */ + +#ifndef __KERNEL__ +typedef u_int8_t uint8_t; +typedef u_int16_t uint16_t; +typedef u_int32_t uint32_t; +#endif + +#define PCI_CFG_VENDOR_ID PCI_VENDOR_ID +#define PCI_CFG_COMMAND PCI_COMMAND +#define PCI_CFG_REV_ID PCI_REVISION_ID +#define PCI_CFG_HEADER_TYPE PCI_HEADER_TYPE +#define PCI_CFG_BASE_ADDR(n) PCI_BASE_ADDRESS_##n -/* - * The above needs to be modified and follow LINUX ... - */ /* /hw/.../pci/[slot]/config accepts ioctls to read * and write specific registers as follows: @@ -69,18 +78,11 @@ /* PCIIOCGETBASE(n): arg is ptr to a 32-bit int, * which will get the value of the BASE<n> register. */ + +/* FIXME chadt: this doesn't tell me whether or not this will work + with non-constant 'n.' */ #define PCIIOCGETBASE(n) PCIIOCCFGRD(uint32_t,PCI_CFG_BASE_ADDR(n)) -/* /hw/.../pci/[slot]/intr accepts an ioctl to - * set up user level interrupt handling as follows: - * - * "n" is a bitmap of which of the four PCI interrupt - * lines are of interest, using PCIIO_INTR_LINE_[ABCD]. - */ -#define PCIIOCSETULI(n) _IOWR(1,n,struct uliargs) -#if _KERNEL -#define PCIIOCSETULI32(n) _IOWR(1,n,struct uliargs32) -#endif /* /hw/.../pci/[slot]/dma accepts ioctls to allocate * and free physical memory for use in user-triggered @@ -93,11 +95,20 @@ * both the size of the request and the flag values * to be used in setting up the DMA. * + +FIXME chadt: gonna have to revisit this: what flags would an IRIXer like to + have available? + * Any flags normally useful in pciio_dmamap - * or pciio_dmatrans function calls can6 be used here. - */ + * or pciio_dmatrans function calls can6 be used here. */ #define PCIIOCDMAALLOC_REQUEST_PACK(flags,size) \ ((((uint64_t)(flags))<<32)| \ (((uint64_t)(size))&0xFFFFFFFF)) + +#ifdef __KERNEL__ +extern int pciba_init(void); +#endif + + #endif /* _ASM_SN_PCI_PCIBA_H */ diff --git a/include/asm-ia64/sn/pci/pcibr.h b/include/asm-ia64/sn/pci/pcibr.h index af9643fbbddf..b834fed50f1a 100644 --- a/include/asm-ia64/sn/pci/pcibr.h +++ b/include/asm-ia64/sn/pci/pcibr.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIBR_H #define _ASM_SN_PCI_PCIBR_H @@ -13,7 +12,7 @@ #if defined(__KERNEL__) #include <asm/sn/dmamap.h> -#include <asm/sn/iobus.h> +#include <asm/sn/driver.h> #include <asm/sn/pio.h> #include <asm/sn/pci/pciio.h> @@ -31,7 +30,7 @@ #define PCIBR_INTR_BLOCKED 0x40000000 #define PCIBR_INTR_BUSY 0x80000000 -#if LANGUAGE_C +#ifndef __ASSEMBLY__ /* ===================================================================== * opaque types used by pcibr's xtalk bus provider @@ -183,10 +182,7 @@ extern pcibr_intr_t pcibr_intr_alloc(devfs_handle_t dev, extern void pcibr_intr_free(pcibr_intr_t intr); -extern int pcibr_intr_connect(pcibr_intr_t intr, - intr_func_t intr_func, - intr_arg_t intr_arg, - void *thread); +extern int pcibr_intr_connect(pcibr_intr_t intr); extern void pcibr_intr_disconnect(pcibr_intr_t intr); @@ -349,7 +345,7 @@ extern void pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *); extern int pcibr_asic_rev(devfs_handle_t); -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ #endif /* #if defined(__KERNEL__) */ /* * Some useful ioctls into the pcibr driver @@ -390,10 +386,34 @@ extern int pcibr_asic_rev(devfs_handle_t); /* * Structures for requesting PCI bridge information and receiving a response */ -typedef struct pcibr_slot_info_req_s *pcibr_slot_info_req_t; +typedef struct pcibr_slot_req_s *pcibr_slot_req_t; +typedef struct pcibr_slot_up_resp_s *pcibr_slot_up_resp_t; +typedef struct pcibr_slot_down_resp_s *pcibr_slot_down_resp_t; typedef struct pcibr_slot_info_resp_s *pcibr_slot_info_resp_t; typedef struct pcibr_slot_func_info_resp_s *pcibr_slot_func_info_resp_t; +#define L1_QSIZE 128 /* our L1 message buffer size */ +struct pcibr_slot_req_s { + int req_slot; + union { + pcibr_slot_up_resp_t up; + pcibr_slot_down_resp_t down; + pcibr_slot_info_resp_t query; + void *any; + } req_respp; + int req_size; +}; + +struct pcibr_slot_up_resp_s { + int resp_sub_errno; + char resp_l1_msg[L1_QSIZE + 1]; +}; + +struct pcibr_slot_down_resp_s { + int resp_sub_errno; + char resp_l1_msg[L1_QSIZE + 1]; +}; + struct pcibr_slot_info_req_s { int req_slot; pcibr_slot_info_resp_t req_respp; @@ -454,7 +474,40 @@ struct pcibr_slot_info_resp_s { int resp_f_att_det_error; } resp_func[8]; - }; + +/* + * PCI specific errors, interpreted by pciconfig command + */ + +/* EPERM 1 */ +#define PCI_SLOT_ALREADY_UP 2 /* slot already up */ +#define PCI_SLOT_ALREADY_DOWN 3 /* slot already down */ +#define PCI_IS_SYS_CRITICAL 4 /* slot is system critical */ +/* EIO 5 */ +/* ENXIO 6 */ +#define PCI_L1_ERR 7 /* L1 console command error */ +#define PCI_NOT_A_BRIDGE 8 /* device is not a bridge */ +#define PCI_SLOT_IN_SHOEHORN 9 /* slot is in a shorhorn */ +#define PCI_NOT_A_SLOT 10 /* slot is invalid */ +#define PCI_RESP_AREA_TOO_SMALL 11 /* slot is invalid */ +/* ENOMEM 12 */ +#define PCI_NO_DRIVER 13 /* no driver for device */ +/* EFAULT 14 */ +#define PCI_EMPTY_33MHZ 15 /* empty 33 MHz bus */ +/* EBUSY 16 */ +#define PCI_SLOT_RESET_ERR 17 /* slot reset error */ +#define PCI_SLOT_INFO_INIT_ERR 18 /* slot info init error */ +/* ENODEV 19 */ +#define PCI_SLOT_ADDR_INIT_ERR 20 /* slot addr space init error */ +#define PCI_SLOT_DEV_INIT_ERR 21 /* slot device init error */ +/* EINVAL 22 */ +#define PCI_SLOT_GUEST_INIT_ERR 23 /* slot guest info init error */ +#define PCI_SLOT_RRB_ALLOC_ERR 24 /* slot initial rrb alloc error */ +#define PCI_SLOT_DRV_ATTACH_ERR 25 /* driver attach error */ +#define PCI_SLOT_DRV_DETACH_ERR 26 /* driver detach error */ +/* ERANGE 34 */ +/* EUNATCH 42 */ + #endif /* _ASM_SN_PCI_PCIBR_H */ diff --git a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h index 271d868703d4..c44ff76dce77 100644 --- a/include/asm-ia64/sn/pci/pcibr_private.h +++ b/include/asm-ia64/sn/pci/pcibr_private.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIBR_PRIVATE_H #define _ASM_SN_PCI_PCIBR_PRIVATE_H @@ -16,6 +15,7 @@ * should ever peek into this file. */ +#include <asm/sn/pci/pcibr.h> #include <asm/sn/pci/pciio_private.h> #include <asm/sn/ksys/l1.h> @@ -100,9 +100,6 @@ struct pcibr_intr_s { #define bi_flags bi_pi.pi_flags /* PCIBR_INTR flags */ #define bi_dev bi_pi.pi_dev /* associated pci card */ #define bi_lines bi_pi.pi_lines /* which PCI interrupt line(s) */ -#define bi_func bi_pi.pi_func /* handler function (when connected) */ -#define bi_arg bi_pi.pi_arg /* handler parameter (when connected) */ -#define bi_tinfo bi_pi.pi_tinfo /* Thread info (when connected) */ #define bi_mustruncpu bi_pi.pi_mustruncpu /* Where we must run. */ #define bi_irq bi_pi.pi_irq /* IRQ assigned. */ #define bi_cpu bi_pi.pi_cpu /* cpu assigned. */ @@ -173,14 +170,17 @@ struct pcibr_intr_wrap_s { */ struct pcibr_soft_s { - devfs_handle_t bs_conn; /* xtalk connection point */ - devfs_handle_t bs_vhdl; /* vertex owned by pcibr */ + devfs_handle_t bs_conn; /* xtalk connection point */ + devfs_handle_t bs_vhdl; /* vertex owned by pcibr */ int bs_int_enable; /* Mask of enabled intrs */ - bridge_t *bs_base; /* PIO pointer to Bridge chip */ - char *bs_name; /* hw graph name */ - xwidgetnum_t bs_xid; /* Bridge's xtalk ID number */ - devfs_handle_t bs_master; /* xtalk master vertex */ - xwidgetnum_t bs_mxid; /* master's xtalk ID number */ + bridge_t *bs_base; /* PIO pointer to Bridge chip */ + char *bs_name; /* hw graph name */ + xwidgetnum_t bs_xid; /* Bridge's xtalk ID number */ + devfs_handle_t bs_master; /* xtalk master vertex */ + xwidgetnum_t bs_mxid; /* master's xtalk ID number */ + pciio_slot_t bs_first_slot; /* first existing slot */ + pciio_slot_t bs_last_slot; /* last existing slot */ + iopaddr_t bs_dir_xbase; /* xtalk address for 32-bit PCI direct map */ xwidgetnum_t bs_dir_xport; /* xtalk port for 32-bit PCI direct map */ @@ -190,7 +190,7 @@ struct pcibr_soft_s { short bs_int_ate_size; /* number of internal ates */ short bs_xbridge; /* if 1 then xbridge */ - int bs_rev_num; /* revision number of Bridge */ + int bs_rev_num; /* revision number of Bridge */ unsigned bs_dma_flags; /* revision-implied DMA flags */ @@ -253,6 +253,7 @@ struct pcibr_soft_s { struct { pciio_space_t bssd_space; iopaddr_t bssd_base; + int bssd_ref_cnt; } bss_devio; /* Shadow value for Device(x) register, @@ -312,7 +313,9 @@ struct pcibr_soft_s { int bs_rrb_fixed; int bs_rrb_avail[2]; int bs_rrb_res[8]; - int bs_rrb_valid[16]; + int bs_rrb_res_dflt[8]; + int bs_rrb_valid[16]; + int bs_rrb_valid_dflt[16]; struct { /* Each Bridge interrupt bit has a single XIO @@ -434,4 +437,41 @@ extern int pcibr_prefetch_enable_rev, pcibr_wg_enable_rev; #define pcibr_soft_get(v) ((pcibr_soft_t)hwgraph_fastinfo_get((v))) #define pcibr_soft_set(v,i) (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i))) +/* Use io spin locks. This ensures that all the PIO writes from a particular + * CPU to a particular IO device are synched before the start of the next + * set of PIO operations to the same device. + */ +#define pcibr_lock(pcibr_soft) io_splock(&pcibr_soft->bs_lock) +#define pcibr_unlock(pcibr_soft,s) io_spunlock(&pcibr_soft->bs_lock,s) + +/* + * mem alloc/free macros + */ +#define NEWAf(ptr,n,f) (ptr = snia_kmem_zalloc((n)*sizeof (*(ptr)), (f&PCIIO_NOSLEEP)?KM_NOSLEEP:KM_SLEEP)) +#define NEWA(ptr,n) (ptr = snia_kmem_zalloc((n)*sizeof (*(ptr)), KM_SLEEP)) +#define DELA(ptr,n) (kfree(ptr)) + +#define NEWf(ptr,f) NEWAf(ptr,1,f) +#define NEW(ptr) NEWA(ptr,1) +#define DEL(ptr) DELA(ptr,1) + +typedef volatile unsigned *cfg_p; +typedef volatile bridgereg_t *reg_p; + +#define PCIBR_RRB_SLOT_VIRTUAL 8 +#define PCIBR_VALID_SLOT(s) (s < 8) +#define PCIBR_D64_BASE_UNSET (0xFFFFFFFFFFFFFFFF) +#define PCIBR_D32_BASE_UNSET (0xFFFFFFFF) +#define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev" + +#define PCIBR_SOFT_LIST 1 +#if PCIBR_SOFT_LIST +typedef struct pcibr_list_s *pcibr_list_p; +struct pcibr_list_s { + pcibr_list_p bl_next; + pcibr_soft_t bl_soft; + devfs_handle_t bl_vhdl; +}; +#endif /* PCIBR_SOFT_LIST */ + #endif /* _ASM_SN_PCI_PCIBR_PRIVATE_H */ diff --git a/include/asm-ia64/sn/pci/pciio.h b/include/asm-ia64/sn/pci/pciio.h index 9afc5b6afd75..43e610545424 100644 --- a/include/asm-ia64/sn/pci/pciio.h +++ b/include/asm-ia64/sn/pci/pciio.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIIO_H #define _ASM_SN_PCI_PCIIO_H @@ -15,25 +14,22 @@ */ #include <asm/sn/ioerror.h> -#include <asm/sn/iobus.h> +#include <asm/sn/driver.h> +#include <asm/sn/hcl.h> -#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) +#ifndef __ASSEMBLY__ #include <asm/sn/dmamap.h> #include <asm/sn/alenlist.h> -#ifdef __cplusplus -extern "C" { -#endif - typedef int pciio_vendor_id_t; -#define PCIIO_VENDOR_ID_NONE -1 +#define PCIIO_VENDOR_ID_NONE (-1) typedef int pciio_device_id_t; -#define PCIIO_DEVICE_ID_NONE -1 +#define PCIIO_DEVICE_ID_NONE (-1) typedef uint8_t pciio_bus_t; /* PCI bus number (0..255) */ typedef uint8_t pciio_slot_t; /* PCI slot number (0..31, 255) */ @@ -387,10 +383,7 @@ typedef void pciio_intr_free_f (pciio_intr_t intr_hdl); typedef int -pciio_intr_connect_f (pciio_intr_t intr_hdl, /* pciio intr resource handle */ - intr_func_t intr_func, /* pciio intr handler */ - intr_arg_t intr_arg, /* arg to intr handler */ - void *thread); /* intr thread to use */ +pciio_intr_connect_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */ typedef void pciio_intr_disconnect_f (pciio_intr_t intr_hdl); @@ -729,8 +722,5 @@ extern size_t pciio_info_rom_size_get(pciio_info_t); extern int pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *); extern int pciio_dma_enabled(devfs_handle_t); -#ifdef __cplusplus -}; -#endif #endif /* C or C++ */ #endif /* _ASM_SN_PCI_PCIIO_H */ diff --git a/include/asm-ia64/sn/pci/pciio_private.h b/include/asm-ia64/sn/pci/pciio_private.h index 217782dbed8c..54cc4e35fefe 100644 --- a/include/asm-ia64/sn/pci/pciio_private.h +++ b/include/asm-ia64/sn/pci/pciio_private.h @@ -4,12 +4,13 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_SN_PCI_PCIIO_PRIVATE_H #define _ASM_SN_PCI_PCIIO_PRIVATE_H +#include <asm/sn/pci/pciio.h> + /* * pciio_private.h -- private definitions for pciio * PCI drivers should NOT include this file. @@ -48,11 +49,6 @@ struct pciio_intr_s { devfs_handle_t pi_dev; /* associated pci card */ device_desc_t pi_dev_desc; /* override device descriptor */ pciio_intr_line_t pi_lines; /* which interrupt line(s) */ - intr_func_t pi_func; /* handler function (when connected) */ - intr_arg_t pi_arg; /* handler parameter (when connected) */ -#ifdef LATER - thd_int_t pi_tinfo; /* Thread info (when connected) */ -#endif cpuid_t pi_mustruncpu; /* Where we must run. */ int pi_irq; /* IRQ assigned */ int pi_cpu; /* cpu assigned */ @@ -84,6 +80,8 @@ struct pciio_info_s { pciio_space_t w_space; iopaddr_t w_base; size_t w_size; + int w_devio_index; /* DevIO[] register used to + access this window */ } c_window[6]; unsigned c_rbase; /* EXPANSION ROM base addr */ diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h new file mode 100644 index 000000000000..c7f433de0b47 --- /dev/null +++ b/include/asm-ia64/sn/pda.h @@ -0,0 +1,80 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + */ +#ifndef _ASM_IA64_SN_PDA_H +#define _ASM_IA64_SN_PDA_H + +#include <linux/config.h> +#include <linux/cache.h> +#include <asm/system.h> +#include <asm/processor.h> +#include <asm/page.h> +#include <asm/sn/bte.h> + + +/* + * CPU-specific data structure. + * + * One of these structures is allocated for each cpu of a NUMA system. + * + * This structure provides a convenient way of keeping together + * all SN per-cpu data structures. + */ + + + +typedef struct pda_s { + + /* Having a pointer in the begining of PDA tends to increase + * the chance of having this pointer in cache. (Yes something + * else gets pushed out). Doing this reduces the number of memory + * access to all nodepda variables to be one + */ + struct nodepda_s *p_nodepda; /* Pointer to Per node PDA */ + struct subnodepda_s *p_subnodepda; /* Pointer to CPU subnode PDA */ + + /* + * Support for blinking SN LEDs + */ + long *led_address; + u8 led_state; + char hb_state; /* supports blinking heartbeat leds */ + unsigned int hb_count; + + unsigned int idle_flag; + +#ifdef CONFIG_IA64_SGI_SN2 + struct irqpda_s *p_irqpda; /* Pointer to CPU irq data */ +#endif + volatile unsigned long *bedrock_rev_id; + volatile unsigned long *pio_write_status_addr; + + bteinfo_t *cpubte[BTES_PER_NODE]; +} pda_t; + + +#define CACHE_ALIGN(x) (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1)) + +/* + * PDA + * Per-cpu private data area for each cpu. The PDA is located immediately after + * the IA64 cpu_data area. A full page is allocated for the cp_data area for each + * cpu but only a small amout of the page is actually used. We put the SNIA PDA + * in the same page as the cpu_data area. Note that there is a check in the setup + * code to verify that we dont overflow the page. + * + * Seems like we should should cache-line align the pda so that any changes in the + * size of the cpu_data area dont change cache layout. Should we align to 32, 64, 128 + * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later. + */ +#define CPU_DATA_END CACHE_ALIGN((long)&(((struct cpuinfo_ia64*)0)->platform_specific)) +#define PDAADDR (PERCPU_ADDR+CPU_DATA_END) + +#define pda (*((pda_t *) PDAADDR)) + + +#endif /* _ASM_IA64_SN_PDA_H */ diff --git a/include/asm-ia64/sn/pio.h b/include/asm-ia64/sn/pio.h index 86e79768e303..b1a0402972ce 100644 --- a/include/asm-ia64/sn/pio.h +++ b/include/asm-ia64/sn/pio.h @@ -4,15 +4,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_PIO_H -#define _ASM_SN_PIO_H +#ifndef _ASM_IA64_SN_PIO_H +#define _ASM_IA64_SN_PIO_H #include <linux/types.h> #include <asm/sn/sgi.h> -#include <asm/sn/iobus.h> +#include <asm/sn/driver.h> /* * pioaddr_t - The kernel virtual address that a PIO can be done upon. @@ -143,7 +142,7 @@ extern void andw_rmw(volatile void*, unsigned int); #define LAN_RAM 2 #define LAN_IO 3 -#define PIOREG_NULL -1 +#define PIOREG_NULL (-1) /* standard flags values for pio_map routines, * including {xtalk,pciio}_piomap calls. @@ -156,4 +155,4 @@ extern void andw_rmw(volatile void*, unsigned int); #define PIOMAP_FLAGS 0x7 -#endif /* _ASM_SN_PIO_H */ +#endif /* _ASM_IA64_SN_PIO_H */ diff --git a/include/asm-ia64/sn/pio_flush.h b/include/asm-ia64/sn/pio_flush.h new file mode 100644 index 000000000000..194348c75c36 --- /dev/null +++ b/include/asm-ia64/sn/pio_flush.h @@ -0,0 +1,65 @@ +/* + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved. + */ + + +#include <linux/config.h> + +#ifndef _ASM_IA64_PIO_FLUSH_H +#define _ASM_IA64_PIO_FLUSH_H + +/* + * This macro flushes all outstanding PIOs performed by this cpu to the + * intended destination SHUB. This in essence ensures that all PIO's + * issues by this cpu has landed at it's destination. + * + * This macro expects the caller: + * 1. The thread is locked. + * 2. All prior PIO operations has been fenced. + * + */ + +#if defined (CONFIG_IA64_SGI_SN) + +#include <asm/sn/pda.h> + +#if defined (CONFIG_IA64_SGI_SN2) + +#define PIO_FLUSH() \ + { \ + while ( !((volatile unsigned long) (*pda.pio_write_status_addr)) & 0x8000000000000000) { \ + udelay(5); \ + } \ + __ia64_mf_a(); \ + } + +#elif defined (CONFIG_IA64_SGI_SN1) + +/* + * For SN1 we need to first read any local Bedrock's MMR and then poll on the + * Synergy MMR. + */ +#define PIO_FLUSH() \ + { \ + (volatile unsigned long) (*pda.bedrock_rev_id); \ + while (!(volatile unsigned long) (*pda.pio_write_status_addr)) { \ + udelay(5); \ + } \ + __ia64_mf_a(); \ + } +#endif +#else +/* + * For all ARCHITECTURE type, this is a NOOP. + */ + +#define PIO_FLUSH() + +#endif + +#endif /* _ASM_IA64_PIO_FLUSH_H */ diff --git a/include/asm-ia64/sn/prio.h b/include/asm-ia64/sn/prio.h index 1651390e0a49..d1f24449e676 100644 --- a/include/asm-ia64/sn/prio.h +++ b/include/asm-ia64/sn/prio.h @@ -4,11 +4,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_PRIO_H -#define _ASM_SN_PRIO_H +#ifndef _ASM_IA64_SN_PRIO_H +#define _ASM_IA64_SN_PRIO_H + +#include <linux/types.h> /* * Priority I/O function prototypes and macro definitions @@ -33,6 +34,6 @@ extern int prioUnlock (void); /* Error returns */ #define PRIO_SUCCESS 0 -#define PRIO_FAIL -1 +#define PRIO_FAIL (-1) -#endif /* _ASM_SN_PRIO_H */ +#endif /* _ASM_IA64_SN_PRIO_H */ diff --git a/include/asm-ia64/sn/router.h b/include/asm-ia64/sn/router.h index 309eb95dd338..43a520fcba2a 100644 --- a/include/asm-ia64/sn/router.h +++ b/include/asm-ia64/sn/router.h @@ -1,19 +1,665 @@ + /* $Id$ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_SN_ROUTER_H +#define _ASM_IA64_SN_ROUTER_H + +/* + * Router Register definitions + * + * Macro argument _L always stands for a link number (1 to 8, inclusive). + */ + +#ifndef __ASSEMBLY__ + +#include <linux/devfs_fs_kernel.h> +#include <asm/sn/vector.h> +#include <asm/sn/slotnum.h> +#include <asm/sn/arch.h> + +typedef uint64_t router_reg_t; + +#define MAX_ROUTERS 64 + +#define MAX_ROUTER_PATH 80 + +#define ROUTER_REG_CAST (volatile router_reg_t *) +#define PS_UINT_CAST (__psunsigned_t) +#define UINT64_CAST (uint64_t) +typedef signed char port_no_t; /* Type for router port number */ + +#else + +#define ROUTERREG_CAST +#define PS_UINT_CAST +#define UINT64_CAST + +#endif /* __ASSEMBLY__ */ + +#define MAX_ROUTER_PORTS (8) /* Max. number of ports on a router */ + +#define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1) /* for 0 based references */ + +#define PORT_INVALID (-1) /* Invalid port number */ + +#define IS_META(_rp) ((_rp)->flags & PCFG_ROUTER_META) + +#define IS_REPEATER(_rp)((_rp)->flags & PCFG_ROUTER_REPEATER) + +/* + * RR_TURN makes a given number of clockwise turns (0 to 7) from an inport + * port to generate an output port. + * + * RR_DISTANCE returns the number of turns necessary (0 to 7) to go from + * an input port (_L1 = 1 to 8) to an output port ( _L2 = 1 to 8). + * + * These are written to work on unsigned data. */ -#ifndef _ASM_SN_ROUTER_H -#define _ASM_SN_ROUTER_H -#include <linux/config.h> +#define RR_TURN(_L, count) ((_L) + (count) > MAX_ROUTER_PORTS ? \ + (_L) + (count) - MAX_ROUTER_PORTS : \ + (_L) + (count)) + +#define RR_DISTANCE(_LS, _LD) ((_LD) >= (_LS) ? \ + (_LD) - (_LS) : \ + (_LD) + MAX_ROUTER_PORTS - (_LS)) + +/* Router register addresses */ + +#define RR_STATUS_REV_ID 0x00000 /* Status register and Revision ID */ +#define RR_PORT_RESET 0x00008 /* Multiple port reset */ +#define RR_PROT_CONF 0x00010 /* Inter-partition protection conf. */ +#define RR_GLOBAL_PORT_DEF 0x00018 /* Global Port definitions */ +#define RR_GLOBAL_PARMS0 0x00020 /* Parameters shared by all 8 ports */ +#define RR_GLOBAL_PARMS1 0x00028 /* Parameters shared by all 8 ports */ +#define RR_DIAG_PARMS 0x00030 /* Parameters for diag. testing */ +#define RR_DEBUG_ADDR 0x00038 /* Debug address select - debug port*/ +#define RR_LB_TO_L2 0x00040 /* Local Block to L2 cntrl intf reg */ +#define RR_L2_TO_LB 0x00048 /* L2 cntrl intf to Local Block reg */ +#define RR_JBUS_CONTROL 0x00050 /* read/write timing for JBUS intf */ + +#define RR_SCRATCH_REG0 0x00100 /* Scratch 0 is 64 bits */ +#define RR_SCRATCH_REG1 0x00108 /* Scratch 1 is 64 bits */ +#define RR_SCRATCH_REG2 0x00110 /* Scratch 2 is 64 bits */ +#define RR_SCRATCH_REG3 0x00118 /* Scratch 3 is 1 bit */ +#define RR_SCRATCH_REG4 0x00120 /* Scratch 4 is 1 bit */ + +#define RR_JBUS0(_D) (((_D) & 0x7) << 3 | 0x00200) /* JBUS0 addresses */ +#define RR_JBUS1(_D) (((_D) & 0x7) << 3 | 0x00240) /* JBUS1 addresses */ + +#define RR_SCRATCH_REG0_WZ 0x00500 /* Scratch 0 is 64 bits */ +#define RR_SCRATCH_REG1_WZ 0x00508 /* Scratch 1 is 64 bits */ +#define RR_SCRATCH_REG2_WZ 0x00510 /* Scratch 2 is 64 bits */ +#define RR_SCRATCH_REG3_SZ 0x00518 /* Scratch 3 is 1 bit */ +#define RR_SCRATCH_REG4_SZ 0x00520 /* Scratch 4 is 1 bit */ + +#define RR_VECTOR_HW_BAR(context) (0x08000 | (context)<<3) /* barrier config registers */ +/* Port-specific registers (_L is the link number from 1 to 8) */ + +#define RR_PORT_PARMS(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0000) /* LLP parameters */ +#define RR_STATUS_ERROR(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0008) /* Port-related errs */ +#define RR_CHANNEL_TEST(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0010) /* Port LLP chan test */ +#define RR_RESET_MASK(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0018) /* Remote reset mask */ +#define RR_HISTOGRAM0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0020) /* Port usage histgrm */ +#define RR_HISTOGRAM1(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0028) /* Port usage histgrm */ +#define RR_HISTOGRAM0_WC(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0030) /* Port usage histgrm */ +#define RR_HISTOGRAM1_WC(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0038) /* Port usage histgrm */ +#define RR_ERROR_CLEAR(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0088) /* Read/clear errors */ +#define RR_GLOBAL_TABLE0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0100) /* starting address of global table for this port */ +#define RR_GLOBAL_TABLE(_L, _x) (RR_GLOBAL_TABLE0(_L) + ((_x) << 3)) +#define RR_LOCAL_TABLE0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0200) /* starting address of local table for this port */ +#define RR_LOCAL_TABLE(_L, _x) (RR_LOCAL_TABLE0(_L) + ((_x) << 3)) + +#define RR_META_ENTRIES 16 + +#define RR_LOCAL_ENTRIES 128 + +/* + * RR_STATUS_REV_ID mask and shift definitions + */ + +#define RSRI_INPORT_SHFT 52 +#define RSRI_INPORT_MASK (UINT64_CAST 0xf << 52) +#define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L)) +#define RSRI_LINKWORKING(_L) (UINT64_CAST 1 << (35 + 2 * (_L))) +#define RSRI_LINKRESETFAIL(_L) (UINT64_CAST 1 << (34 + 2 * (_L))) +#define RSRI_LSTAT_SHFT(_L) (34 + 2 * (_L)) +#define RSRI_LSTAT_MASK(_L) (UINT64_CAST 0x3 << 34 + 2 * (_L)) +#define RSRI_LOCALSBERROR (UINT64_CAST 1 << 35) +#define RSRI_LOCALSTUCK (UINT64_CAST 1 << 34) +#define RSRI_LOCALBADVEC (UINT64_CAST 1 << 33) +#define RSRI_LOCALTAILERR (UINT64_CAST 1 << 32) +#define RSRI_LOCAL_SHFT 32 +#define RSRI_LOCAL_MASK (UINT64_CAST 0xf << 32) +#define RSRI_CHIPREV_SHFT 28 +#define RSRI_CHIPREV_MASK (UINT64_CAST 0xf << 28) +#define RSRI_CHIPID_SHFT 12 +#define RSRI_CHIPID_MASK (UINT64_CAST 0xffff << 12) +#define RSRI_MFGID_SHFT 1 +#define RSRI_MFGID_MASK (UINT64_CAST 0x7ff << 1) + +#define RSRI_LSTAT_WENTDOWN 0 +#define RSRI_LSTAT_RESETFAIL 1 +#define RSRI_LSTAT_LINKUP 2 +#define RSRI_LSTAT_NOTUSED 3 + +/* + * RR_PORT_RESET mask definitions + */ + +#define RPRESET_WARM (UINT64_CAST 1 << 9) +#define RPRESET_LINK(_L) (UINT64_CAST 1 << (_L)) +#define RPRESET_LOCAL (UINT64_CAST 1) + +/* + * RR_PROT_CONF mask and shift definitions + */ + +#define RPCONF_DIRCMPDIS_SHFT 13 +#define RPCONF_DIRCMPDIS_MASK (UINT64_CAST 1 << 13) +#define RPCONF_FORCELOCAL (UINT64_CAST 1 << 12) +#define RPCONF_FLOCAL_SHFT 12 +#define RPCONF_METAID_SHFT 8 +#define RPCONF_METAID_MASK (UINT64_CAST 0xf << 8) +#define RPCONF_RESETOK(_L) (UINT64_CAST 1 << ((_L) - 1)) + +/* + * RR_GLOBAL_PORT_DEF mask and shift definitions + */ + +#define RGPD_MGLBLNHBR_ID_SHFT 12 /* -global neighbor ID */ +#define RGPD_MGLBLNHBR_ID_MASK (UINT64_CAST 0xf << 12) +#define RGPD_MGLBLNHBR_VLD_SHFT 11 /* -global neighbor Valid */ +#define RGPD_MGLBLNHBR_VLD_MASK (UINT64_CAST 0x1 << 11) +#define RGPD_MGLBLPORT_SHFT 8 /* -global neighbor Port */ +#define RGPD_MGLBLPORT_MASK (UINT64_CAST 0x7 << 8) +#define RGPD_PGLBLNHBR_ID_SHFT 4 /* +global neighbor ID */ +#define RGPD_PGLBLNHBR_ID_MASK (UINT64_CAST 0xf << 4) +#define RGPD_PGLBLNHBR_VLD_SHFT 3 /* +global neighbor Valid */ +#define RGPD_PGLBLNHBR_VLD_MASK (UINT64_CAST 0x1 << 3) +#define RGPD_PGLBLPORT_SHFT 0 /* +global neighbor Port */ +#define RGPD_PGLBLPORT_MASK (UINT64_CAST 0x7 << 0) + +#define GLBL_PARMS_REGS 2 /* Two Global Parms registers */ + +/* + * RR_GLOBAL_PARMS0 mask and shift definitions + */ + +#define RGPARM0_ARB_VALUE_SHFT 54 /* Local Block Arbitration State */ +#define RGPARM0_ARB_VALUE_MASK (UINT64_CAST 0x7 << 54) +#define RGPARM0_ROTATEARB_SHFT 53 /* Rotate Local Block Arbitration */ +#define RGPARM0_ROTATEARB_MASK (UINT64_CAST 0x1 << 53) +#define RGPARM0_FAIREN_SHFT 52 /* Fairness logic Enable */ +#define RGPARM0_FAIREN_MASK (UINT64_CAST 0x1 << 52) +#define RGPARM0_LOCGNTTO_SHFT 40 /* Local grant timeout */ +#define RGPARM0_LOCGNTTO_MASK (UINT64_CAST 0xfff << 40) +#define RGPARM0_DATELINE_SHFT 38 /* Dateline crossing router */ +#define RGPARM0_DATELINE_MASK (UINT64_CAST 0x1 << 38) +#define RGPARM0_MAXRETRY_SHFT 28 /* Max retry count */ +#define RGPARM0_MAXRETRY_MASK (UINT64_CAST 0x3ff << 28) +#define RGPARM0_URGWRAP_SHFT 20 /* Urgent wrap */ +#define RGPARM0_URGWRAP_MASK (UINT64_CAST 0xff << 20) +#define RGPARM0_DEADLKTO_SHFT 16 /* Deadlock timeout */ +#define RGPARM0_DEADLKTO_MASK (UINT64_CAST 0xf << 16) +#define RGPARM0_URGVAL_SHFT 12 /* Urgent value */ +#define RGPARM0_URGVAL_MASK (UINT64_CAST 0xf << 12) +#define RGPARM0_VCHSELEN_SHFT 11 /* VCH_SEL_EN */ +#define RGPARM0_VCHSELEN_MASK (UINT64_CAST 0x1 << 11) +#define RGPARM0_LOCURGTO_SHFT 9 /* Local urgent timeout */ +#define RGPARM0_LOCURGTO_MASK (UINT64_CAST 0x3 << 9) +#define RGPARM0_TAILVAL_SHFT 5 /* Tail value */ +#define RGPARM0_TAILVAL_MASK (UINT64_CAST 0xf << 5) +#define RGPARM0_CLOCK_SHFT 1 /* Global clock select */ +#define RGPARM0_CLOCK_MASK (UINT64_CAST 0xf << 1) +#define RGPARM0_BYPEN_SHFT 0 +#define RGPARM0_BYPEN_MASK (UINT64_CAST 1) /* Bypass enable */ + +/* + * RR_GLOBAL_PARMS1 shift and mask definitions + */ + +#define RGPARM1_TTOWRAP_SHFT 12 /* Tail timeout wrap */ +#define RGPARM1_TTOWRAP_MASK (UINT64_CAST 0xfffff << 12) +#define RGPARM1_AGERATE_SHFT 8 /* Age rate */ +#define RGPARM1_AGERATE_MASK (UINT64_CAST 0xf << 8) +#define RGPARM1_JSWSTAT_SHFT 0 /* JTAG Sw Register bits */ +#define RGPARM1_JSWSTAT_MASK (UINT64_CAST 0xff << 0) + +/* + * RR_DIAG_PARMS mask and shift definitions + */ + +#define RDPARM_ABSHISTOGRAM (UINT64_CAST 1 << 17) /* Absolute histgrm */ +#define RDPARM_DEADLOCKRESET (UINT64_CAST 1 << 16) /* Reset on deadlck */ +#define RDPARM_DISABLE(_L) (UINT64_CAST 1 << ((_L) + 7)) +#define RDPARM_SENDERROR(_L) (UINT64_CAST 1 << ((_L) - 1)) + +/* + * RR_DEBUG_ADDR mask and shift definitions + */ + +#define RDA_DATA_SHFT 10 /* Observed debug data */ +#define RDA_DATA_MASK (UINT64_CAST 0xffff << 10) +#define RDA_ADDR_SHFT 0 /* debug address for data */ +#define RDA_ADDR_MASK (UINT64_CAST 0x3ff << 0) + +/* + * RR_LB_TO_L2 mask and shift definitions + */ + +#define RLBTOL2_DATA_VLD_SHFT 32 /* data is valid for JTAG controller */ +#define RLBTOL2_DATA_VLD_MASK (UINT64_CAST 0x1 << 32) +#define RLBTOL2_DATA_SHFT 0 /* data bits for JTAG controller */ +#define RLBTOL2_DATA_MASK (UINT64_CAST 0xffffffff) + +/* + * RR_L2_TO_LB mask and shift definitions + */ + +#define RL2TOLB_DATA_VLD_SHFT 33 /* data is valid from JTAG controller */ +#define RL2TOLB_DATA_VLD_MASK (UINT64_CAST 0x1 << 33) +#define RL2TOLB_PARITY_SHFT 32 /* sw implemented parity for data */ +#define RL2TOLB_PARITY_MASK (UINT64_CAST 0x1 << 32) +#define RL2TOLB_DATA_SHFT 0 /* data bits from JTAG controller */ +#define RL2TOLB_DATA_MASK (UINT64_CAST 0xffffffff) + +/* + * RR_JBUS_CONTROL mask and shift definitions + */ -#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC -#include <asm/sn/sn1/router.h> +#define RJC_POS_BITS_SHFT 20 /* Router position bits */ +#define RJC_POS_BITS_MASK (UINT64_CAST 0xf << 20) +#define RJC_RD_DATA_STROBE_SHFT 16 /* count when read data is strobed in */ +#define RJC_RD_DATA_STROBE_MASK (UINT64_CAST 0xf << 16) +#define RJC_WE_OE_HOLD_SHFT 8 /* time OE or WE is held */ +#define RJC_WE_OE_HOLD_MASK (UINT64_CAST 0xff << 8) +#define RJC_ADDR_SET_HLD_SHFT 0 /* time address driven around OE/WE */ +#define RJC_ADDR_SET_HLD_MASK (UINT64_CAST 0xff) + +/* + * RR_SCRATCH_REGx mask and shift definitions + * note: these fields represent a software convention, and are not + * understood/interpreted by the hardware. + */ + +#define RSCR0_BOOTED_SHFT 63 +#define RSCR0_BOOTED_MASK (UINT64_CAST 0x1 << RSCR0_BOOTED_SHFT) +#define RSCR0_LOCALID_SHFT 56 +#define RSCR0_LOCALID_MASK (UINT64_CAST 0x7f << RSCR0_LOCALID_SHFT) +#define RSCR0_UNUSED_SHFT 48 +#define RSCR0_UNUSED_MASK (UINT64_CAST 0xff << RSCR0_UNUSED_SHFT) +#define RSCR0_NIC_SHFT 0 +#define RSCR0_NIC_MASK (UINT64_CAST 0xffffffffffff) + +#define RSCR1_MODID_SHFT 0 +#define RSCR1_MODID_MASK (UINT64_CAST 0xffff) + +/* + * RR_VECTOR_HW_BAR mask and shift definitions + */ + +#define BAR_TX_SHFT 27 /* Barrier in trans(m)it when read */ +#define BAR_TX_MASK (UINT64_CAST 1 << BAR_TX_SHFT) +#define BAR_VLD_SHFT 26 /* Valid Configuration */ +#define BAR_VLD_MASK (UINT64_CAST 1 << BAR_VLD_SHFT) +#define BAR_SEQ_SHFT 24 /* Sequence number */ +#define BAR_SEQ_MASK (UINT64_CAST 3 << BAR_SEQ_SHFT) +#define BAR_LEAFSTATE_SHFT 18 /* Leaf State */ +#define BAR_LEAFSTATE_MASK (UINT64_CAST 0x3f << BAR_LEAFSTATE_SHFT) +#define BAR_PARENT_SHFT 14 /* Parent Port */ +#define BAR_PARENT_MASK (UINT64_CAST 0xf << BAR_PARENT_SHFT) +#define BAR_CHILDREN_SHFT 6 /* Child Select port bits */ +#define BAR_CHILDREN_MASK (UINT64_CAST 0xff << BAR_CHILDREN_SHFT) +#define BAR_LEAFCOUNT_SHFT 0 /* Leaf Count to trigger parent */ +#define BAR_LEAFCOUNT_MASK (UINT64_CAST 0x3f) + +/* + * RR_PORT_PARMS(_L) mask and shift definitions + */ + +#define RPPARM_MIPRESETEN_SHFT 29 /* Message In Progress reset enable */ +#define RPPARM_MIPRESETEN_MASK (UINT64_CAST 0x1 << 29) +#define RPPARM_UBAREN_SHFT 28 /* Enable user barrier requests */ +#define RPPARM_UBAREN_MASK (UINT64_CAST 0x1 << 28) +#define RPPARM_OUTPDTO_SHFT 24 /* Output Port Deadlock TO value */ +#define RPPARM_OUTPDTO_MASK (UINT64_CAST 0xf << 24) +#define RPPARM_PORTMATE_SHFT 21 /* Port Mate for the port */ +#define RPPARM_PORTMATE_MASK (UINT64_CAST 0x7 << 21) +#define RPPARM_HISTEN_SHFT 20 /* Histogram counter enable */ +#define RPPARM_HISTEN_MASK (UINT64_CAST 0x1 << 20) +#define RPPARM_HISTSEL_SHFT 18 +#define RPPARM_HISTSEL_MASK (UINT64_CAST 0x3 << 18) +#define RPPARM_DAMQHS_SHFT 16 +#define RPPARM_DAMQHS_MASK (UINT64_CAST 0x3 << 16) +#define RPPARM_NULLTO_SHFT 10 +#define RPPARM_NULLTO_MASK (UINT64_CAST 0x3f << 10) +#define RPPARM_MAXBURST_SHFT 0 +#define RPPARM_MAXBURST_MASK (UINT64_CAST 0x3ff) + +/* + * NOTE: Normally the kernel tracks only UTILIZATION statistics. + * The other 2 should not be used, except during any experimentation + * with the router. + */ +#define RPPARM_HISTSEL_AGE 0 /* Histogram age characterization. */ +#define RPPARM_HISTSEL_UTIL 1 /* Histogram link utilization */ +#define RPPARM_HISTSEL_DAMQ 2 /* Histogram DAMQ characterization. */ + +/* + * RR_STATUS_ERROR(_L) and RR_ERROR_CLEAR(_L) mask and shift definitions + */ +#define RSERR_POWERNOK (UINT64_CAST 1 << 38) +#define RSERR_PORT_DEADLOCK (UINT64_CAST 1 << 37) +#define RSERR_WARMRESET (UINT64_CAST 1 << 36) +#define RSERR_LINKRESET (UINT64_CAST 1 << 35) +#define RSERR_RETRYTIMEOUT (UINT64_CAST 1 << 34) +#define RSERR_FIFOOVERFLOW (UINT64_CAST 1 << 33) +#define RSERR_ILLEGALPORT (UINT64_CAST 1 << 32) +#define RSERR_DEADLOCKTO_SHFT 28 +#define RSERR_DEADLOCKTO_MASK (UINT64_CAST 0xf << 28) +#define RSERR_RECVTAILTO_SHFT 24 +#define RSERR_RECVTAILTO_MASK (UINT64_CAST 0xf << 24) +#define RSERR_RETRYCNT_SHFT 16 +#define RSERR_RETRYCNT_MASK (UINT64_CAST 0xff << 16) +#define RSERR_CBERRCNT_SHFT 8 +#define RSERR_CBERRCNT_MASK (UINT64_CAST 0xff << 8) +#define RSERR_SNERRCNT_SHFT 0 +#define RSERR_SNERRCNT_MASK (UINT64_CAST 0xff << 0) + + +#define PORT_STATUS_UP (1 << 0) /* Router link up */ +#define PORT_STATUS_FENCE (1 << 1) /* Router link fenced */ +#define PORT_STATUS_RESETFAIL (1 << 2) /* Router link didnot + * come out of reset */ +#define PORT_STATUS_DISCFAIL (1 << 3) /* Router link failed after + * out of reset but before + * router tables were + * programmed + */ +#define PORT_STATUS_KERNFAIL (1 << 4) /* Router link failed + * after reset and the + * router tables were + * programmed + */ +#define PORT_STATUS_UNDEF (1 << 5) /* Unable to pinpoint + * why the router link + * went down + */ +#define PROBE_RESULT_BAD (-1) /* Set if any of the router + * links failed after reset + */ +#define PROBE_RESULT_GOOD (0) /* Set if all the router links + * which came out of reset + * are up + */ + +/* Should be enough for 256 CPUs */ +#define MAX_RTR_BREADTH 64 /* Max # of routers possible */ + +/* Get the require set of bits in a var. corr to a sequence of bits */ +#define GET_FIELD(var, fname) \ + ((var) >> fname##_SHFT & fname##_MASK >> fname##_SHFT) +/* Set the require set of bits in a var. corr to a sequence of bits */ +#define SET_FIELD(var, fname, fval) \ + ((var) = (var) & ~fname##_MASK | (uint64_t) (fval) << fname##_SHFT) + + +#ifndef __ASSEMBLY__ + +typedef struct router_map_ent_s { + uint64_t nic; + moduleid_t module; + slotid_t slot; +} router_map_ent_t; + +struct rr_status_error_fmt { + uint64_t rserr_unused : 30, + rserr_fifooverflow : 1, + rserr_illegalport : 1, + rserr_deadlockto : 4, + rserr_recvtailto : 4, + rserr_retrycnt : 8, + rserr_cberrcnt : 8, + rserr_snerrcnt : 8; +}; + +/* + * This type is used to store "absolute" counts of router events + */ +typedef int router_count_t; + +/* All utilizations are on a scale from 0 - 1023. */ +#define RP_BYPASS_UTIL 0 +#define RP_RCV_UTIL 1 +#define RP_SEND_UTIL 2 +#define RP_TOTAL_PKTS 3 /* Free running clock/packet counter */ + +#define RP_NUM_UTILS 3 + +#define RP_HIST_REGS 2 +#define RP_NUM_BUCKETS 4 +#define RP_HIST_TYPES 3 + +#define RP_AGE0 0 +#define RP_AGE1 1 +#define RP_AGE2 2 +#define RP_AGE3 3 + + +#define RR_UTIL_SCALE 1024 + +/* + * Router port-oriented information + */ +typedef struct router_port_info_s { + router_reg_t rp_histograms[RP_HIST_REGS];/* Port usage info */ + router_reg_t rp_port_error; /* Port error info */ + router_count_t rp_retry_errors; /* Total retry errors */ + router_count_t rp_sn_errors; /* Total sn errors */ + router_count_t rp_cb_errors; /* Total cb errors */ + int rp_overflows; /* Total count overflows */ + int rp_excess_err; /* Port has excessive errors */ + ushort rp_util[RP_NUM_BUCKETS];/* Port utilization */ +} router_port_info_t; + +#define ROUTER_INFO_VERSION 7 + +struct lboard_s; + +/* + * Router information + */ +typedef struct router_info_s { + char ri_version; /* structure version */ + cnodeid_t ri_cnode; /* cnode of its legal guardian hub */ + nasid_t ri_nasid; /* Nasid of same */ + char ri_ledcache; /* Last LED bitmap */ + char ri_leds; /* Current LED bitmap */ + char ri_portmask; /* Active port bitmap */ + router_reg_t ri_stat_rev_id; /* Status rev ID value */ + net_vec_t ri_vector; /* vector from guardian to router */ + int ri_writeid; /* router's vector write ID */ + int64_t ri_timebase; /* Time of first sample */ + int64_t ri_timestamp; /* Time of last sample */ + router_port_info_t ri_port[MAX_ROUTER_PORTS]; /* per port info */ + moduleid_t ri_module; /* Which module are we in? */ + slotid_t ri_slotnum; /* Which slot are we in? */ + router_reg_t ri_glbl_parms[GLBL_PARMS_REGS]; + /* Global parms0&1 register contents*/ + devfs_handle_t ri_vertex; /* hardware graph vertex */ + router_reg_t ri_prot_conf; /* protection config. register */ + int64_t ri_per_minute; /* Ticks per minute */ + + /* + * Everything below here is for kernel use only and may change at + * at any time with or without a change in teh revision number + * + * Any pointers or things that come and go with DEBUG must go at + * the bottom of the structure, below the user stuff. + */ + char ri_hist_type; /* histogram type */ + devfs_handle_t ri_guardian; /* guardian node for the router */ + int64_t ri_last_print; /* When did we last print */ + char ri_print; /* Should we print */ + char ri_just_blink; /* Should we blink the LEDs */ + +#ifdef DEBUG + int64_t ri_deltatime; /* Time it took to sample */ #endif + spinlock_t ri_lock; /* Lock for access to router info */ + net_vec_t *ri_vecarray; /* Pointer to array of vectors */ + struct lboard_s *ri_brd; /* Pointer to board structure */ + char * ri_name; /* This board's hwg path */ + unsigned char ri_port_maint[MAX_ROUTER_PORTS]; /* should we send a + message to availmon */ +} router_info_t; + + +/* Router info location specifiers */ + +#define RIP_PROMLOG 2 /* Router info in promlog */ +#define RIP_CONSOLE 4 /* Router info on console */ + +#define ROUTER_INFO_PRINT(_rip,_where) (_rip->ri_print |= _where) + /* Set the field used to check if a + * router info can be printed + */ +#define IS_ROUTER_INFO_PRINTED(_rip,_where) \ + (_rip->ri_print & _where) + /* Was the router info printed to + * the given location (_where) ? + * Mainly used to prevent duplicate + * router error states. + */ +#define ROUTER_INFO_LOCK(_rip,_s) _s = mutex_spinlock(&(_rip->ri_lock)) + /* Take the lock on router info + * to gain exclusive access + */ +#define ROUTER_INFO_UNLOCK(_rip,_s) mutex_spinunlock(&(_rip->ri_lock),_s) + /* Release the lock on router info */ +/* + * Router info hanging in the nodepda + */ +typedef struct nodepda_router_info_s { + devfs_handle_t router_vhdl; /* vertex handle of the router */ + short router_port; /* port thru which we entered */ + short router_portmask; + moduleid_t router_module; /* module in which router is there */ + slotid_t router_slot; /* router slot */ + unsigned char router_type; /* kind of router */ + net_vec_t router_vector; /* vector from the guardian node */ + + router_info_t *router_infop; /* info hanging off the hwg vertex */ + struct nodepda_router_info_s *router_next; + /* pointer to next element */ +} nodepda_router_info_t; + +#define ROUTER_NAME_SIZE 20 /* Max size of a router name */ + +#define NORMAL_ROUTER_NAME "normal_router" +#define NULL_ROUTER_NAME "null_router" +#define META_ROUTER_NAME "meta_router" +#define REPEATER_ROUTER_NAME "repeater_router" +#define UNKNOWN_ROUTER_NAME "unknown_router" + +/* The following definitions are needed by the router traversing + * code either using the hardware graph or using vector operations. + */ +/* Structure of the router queue element */ +typedef struct router_elt_s { + union { + /* queue element structure during router probing */ + struct { + /* number-in-a-can (unique) for the router */ + nic_t nic; + /* vector route from the master hub to + * this router. + */ + net_vec_t vec; + /* port status */ + uint64_t status; + char port_status[MAX_ROUTER_PORTS + 1]; + } r_elt; + /* queue element structure during router guardian + * assignment + */ + struct { + /* vertex handle for the router */ + devfs_handle_t vhdl; + /* guardian for this router */ + devfs_handle_t guard; + /* vector router from the guardian to the router */ + net_vec_t vec; + } k_elt; + } u; + /* easy to use port status interpretation */ +} router_elt_t; + +/* structure of the router queue */ + +typedef struct router_queue_s { + char head; /* Point where a queue element is inserted */ + char tail; /* Point where a queue element is removed */ + int type; + router_elt_t array[MAX_RTR_BREADTH]; + /* Entries for queue elements */ +} router_queue_t; + + +#endif /* __ASSEMBLY__ */ + +/* + * RR_HISTOGRAM(_L) mask and shift definitions + * There are two 64 bit histogram registers, so the following macros take + * into account dealing with an array of 4 32 bit values indexed by _x + */ + +#define RHIST_BUCKET_SHFT(_x) (32 * ((_x) & 0x1)) +#define RHIST_BUCKET_MASK(_x) (UINT64_CAST 0xffffffff << RHIST_BUCKET_SHFT((_x) & 0x1)) +#define RHIST_GET_BUCKET(_x, _reg) \ + ((RHIST_BUCKET_MASK(_x) & ((_reg)[(_x) >> 1])) >> RHIST_BUCKET_SHFT(_x)) + +/* + * RR_RESET_MASK(_L) mask and shift definitions + */ + +#define RRM_RESETOK(_L) (UINT64_CAST 1 << ((_L) - 1)) +#define RRM_RESETOK_ALL ALL_PORTS + +/* + * RR_META_TABLE(_x) and RR_LOCAL_TABLE(_x) mask and shift definitions + */ + +#define RTABLE_SHFT(_L) (4 * ((_L) - 1)) +#define RTABLE_MASK(_L) (UINT64_CAST 0x7 << RTABLE_SHFT(_L)) + + +#define ROUTERINFO_STKSZ 4096 + +#ifndef __ASSEMBLY__ + +int router_reg_read(router_info_t *rip, int regno, router_reg_t *val); +int router_reg_write(router_info_t *rip, int regno, router_reg_t val); +int router_get_info(devfs_handle_t routerv, router_info_t *, int); +int router_init(cnodeid_t cnode,int writeid, nodepda_router_info_t *npda_rip); +int router_set_leds(router_info_t *rip); +void router_print_state(router_info_t *rip, int level, + void (*pf)(int, char *, ...),int print_where); +void capture_router_stats(router_info_t *rip); + + +int probe_routers(void); +void get_routername(unsigned char brd_type,char *rtrname); +void router_guardians_set(devfs_handle_t hwgraph_root); +int router_hist_reselect(router_info_t *, int64_t); +#endif /* __ASSEMBLY__ */ -#endif /* _ASM_SN_ROUTER_H */ +#endif /* _ASM_IA64_SN_ROUTER_H */ diff --git a/include/asm-ia64/sn/sgi.h b/include/asm-ia64/sn/sgi.h index 7202c2e80395..8e8d3d4dd875 100644 --- a/include/asm-ia64/sn/sgi.h +++ b/include/asm-ia64/sn/sgi.h @@ -4,13 +4,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com) + * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SGI_H -#define _ASM_SN_SGI_H +#ifndef _ASM_IA64_SN_SGI_H +#define _ASM_IA64_SN_SGI_H #include <linux/config.h> @@ -95,9 +94,6 @@ struct devfs_entry bigger. This is NULL-terminated */ }; -#define MIN(_a,_b) ((_a)<(_b)?(_a):(_b)) - -typedef uint32_t app32_ptr_t; /* needed by edt.h */ typedef int64_t __psint_t; /* needed by klgraph.c */ typedef enum { B_FALSE, B_TRUE } boolean_t; @@ -105,8 +101,6 @@ typedef enum { B_FALSE, B_TRUE } boolean_t; #define ctob(x) ((uint64_t)(x)*NBPC) #define btoc(x) (((uint64_t)(x)+(NBPC-1))/NBPC) -typedef __psunsigned_t nic_data_t; - /* ** Possible return values from graph routines. @@ -129,10 +123,6 @@ typedef enum graph_error_e { * calls */ #define XG_WIDGET_PART_NUM 0xC102 /* KONA/xt_regs.h XG_XT_PART_NUM_VALUE */ -#ifndef TO_PHYS_MASK -#define TO_PHYS_MASK 0x0000000fffffffff -#endif - typedef uint64_t vhandl_t; @@ -159,7 +149,7 @@ typedef uint64_t vhandl_t; typedef uint64_t mrlock_t; /* needed by devsupport.c */ #define HUB_PIO_CONVEYOR 0x1 -#define CNODEID_NONE (cnodeid_t)-1 +#define CNODEID_NONE ((cnodeid_t)-1) #define XTALK_PCI_PART_NUM "030-1275-" #define kdebug 0 @@ -177,7 +167,7 @@ typedef uint64_t mrlock_t; /* needed by devsupport.c */ #define kern_free(x) kfree(x) typedef cpuid_t cpu_cookie_t; -#define CPU_NONE -1 +#define CPU_NONE (-1) /* * mutext support mapping @@ -225,9 +215,6 @@ mutex_spinlock(spinlock_t *sem) { } } while(0) #endif /* DISABLE_ASSERT */ -#define PRINT_WARNING(x...) do { printk("WARNING : "); printk(x); } while(0) -#define PRINT_NOTICE(x...) do { printk("NOTICE : "); printk(x); } while(0) -#define PRINT_ALERT(x...) do { printk("ALERT : "); printk(x); } while(0) #define PRINT_PANIC panic #ifdef CONFIG_SMP @@ -238,4 +225,4 @@ mutex_spinlock(spinlock_t *sem) { #include <asm/sn/hack.h> /* for now */ -#endif /* _ASM_SN_SGI_H */ +#endif /* _ASM_IA64_SN_SGI_H */ diff --git a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h new file mode 100644 index 000000000000..b66624df6493 --- /dev/null +++ b/include/asm-ia64/sn/simulator.h @@ -0,0 +1,27 @@ +#ifndef _ASM_IA64_SN_SIMULATOR_H +#define _ASM_IA64_SN_SIMULATOR_H + +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. + */ + +#include <linux/config.h> + +#ifdef CONFIG_IA64_SGI_SN_SIM + +#define SNMAGIC 0xaeeeeeee8badbeefL +#define IS_RUNNING_ON_SIMULATOR() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;}) + +#define SIMULATOR_SLEEP() asm("nop.i 0x8beef") + +#else + +#define IS_RUNNING_ON_SIMULATOR() (0) +#define SIMULATOR_SLEEP() + +#endif + +#endif /* _ASM_IA64_SN_SIMULATOR_H */ diff --git a/include/asm-ia64/sn/slotnum.h b/include/asm-ia64/sn/slotnum.h index 2f8a6aea24ea..680ae79fb94f 100644 --- a/include/asm-ia64/sn/slotnum.h +++ b/include/asm-ia64/sn/slotnum.h @@ -4,22 +4,23 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SLOTNUM_H -#define _ASM_SN_SLOTNUM_H +#ifndef _ASM_IA64_SN_SLOTNUM_H +#define _ASM_IA64_SN_SLOTNUM_H #include <linux/config.h> typedef unsigned char slotid_t; -#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) +#if defined (CONFIG_IA64_SGI_SN1) #include <asm/sn/sn1/slotnum.h> +#elif defined (CONFIG_IA64_SGI_SN2) +#include <asm/sn/sn2/slotnum.h> #else #error <<BOMB! slotnum defined only for SN0 and SN1 >> -#endif /* !CONFIG_SGI_IP35 && !CONFIG_IA64_SGI_SN1 */ +#endif /* !CONFIG_IA64_SGI_SN1 */ -#endif /* _ASM_SN_SLOTNUM_H */ +#endif /* _ASM_IA64_SN_SLOTNUM_H */ diff --git a/include/asm-ia64/sn/sn1/addrs.h b/include/asm-ia64/sn/sn1/addrs.h index 46079ec9b5e9..a7055a03400b 100644 --- a/include/asm-ia64/sn/sn1/addrs.h +++ b/include/asm-ia64/sn/sn1/addrs.h @@ -4,19 +4,21 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_ADDRS_H -#define _ASM_SN_SN1_ADDRS_H +#ifndef _ASM_IA64_SN_SN1_ADDRS_H +#define _ASM_IA64_SN_SN1_ADDRS_H +#include <linux/config.h> + +#ifdef CONFIG_IA64_SGI_SN1 /* - * IP35 (on a TRex) Address map + * SN1 (on a TRex) Address map * * This file contains a set of definitions and macros which are used * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC, - * and UNCAC) used by the IP35 architecture. It also contains addresses + * and UNCAC) used by the SN1 architecture. It also contains addresses * for "major" statically locatable PROM/Kernel data structures, such as * the partition table, the configuration data structure, etc. * We make an implicit assumption that the processor using this file @@ -32,7 +34,6 @@ * appropriately. */ -#include <linux/config.h> /* * Some of the macros here need to be casted to appropriate types when used @@ -40,22 +41,14 @@ * use some new ANSI preprocessor stuff to paste these on where needed. */ -#if defined(_RUN_UNCACHED) -#define CAC_BASE 0x9600000000000000 -#else -#ifndef __ia64 -#define CAC_BASE 0xa800000000000000 -#else #define CAC_BASE 0xe000000000000000 -#endif -#endif - #define HSPEC_BASE 0xc0000b0000000000 #define HSPEC_SWIZ_BASE 0xc000030000000000 #define IO_BASE 0xc0000a0000000000 #define IO_SWIZ_BASE 0xc000020000000000 -#define MSPEC_BASE 0xc000000000000000 +#define MSPEC_BASE 0xc000090000000000 #define UNCAC_BASE 0xc000000000000000 +#define TO_PHYS_MASK 0x000000ffffffffff #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) @@ -109,18 +102,14 @@ #define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ NASID_SHFT) & NASID_BITMASK) -#if _LANGUAGE_C && !defined(_STANDALONE) -#ifndef REAL_HARDWARE -#define NODE_SWIN_BASE(nasid, widget) RAW_NODE_SWIN_BASE(nasid, widget) -#else +#ifndef __ASSEMBLY__ #define NODE_SWIN_BASE(nasid, widget) \ ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ : RAW_NODE_SWIN_BASE(nasid, widget)) -#endif #else #define NODE_SWIN_BASE(nasid, widget) \ (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /* * The following definitions pertain to the IO special address @@ -155,7 +144,7 @@ /* * The following define the major position-independent aliases used - * in IP27. + * in SN1. * CALIAS -- Varies in size, points to the first n bytes of memory * on the reader's node. */ @@ -169,11 +158,6 @@ #define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) -#if _LANGUAGE_C -#define KERN_NMI_ADDR(nasid, slice) \ - TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \ - (IP27_NMI_KREGS_CPU_SIZE * (slice))) -#endif /* _LANGUAGE_C */ /* @@ -197,7 +181,7 @@ #define KL_UART_CMD LOCAL_HSPEC(HSPEC_UART_0) /* UART command reg */ #define KL_UART_DATA LOCAL_HSPEC(HSPEC_UART_1) /* UART data reg */ -#if !_LANGUAGE_ASSEMBLY +#if !__ASSEMBLY__ /* Address 0x400 to 0x1000 ualias points to cache error eframe + misc * CACHE_ERR_SP_PTR could either contain an address to the stack, or * the stack could start at CACHE_ERR_SP_PTR @@ -210,28 +194,9 @@ #define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16) #define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME) -#endif /* !_LANGUAGE_ASSEMBLY */ +#endif /* !__ASSEMBLY__ */ + -/* Each CPU accesses UALIAS at a different physaddr, on 32k boundaries - * This determines the locations of the exception vectors - */ -#define UALIAS_FLIP_BASE UALIAS_BASE -#define UALIAS_FLIP_SHIFT 15 -#define UALIAS_FLIP_ADDR(_x) ((_x) ^ (cputoslice(getcpuid())<<UALIAS_FLIP_SHIFT)) - -#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC) -#define EX_HANDLER_OFFSET(slice) ((slice) << UALIAS_FLIP_SHIFT) -#endif -#define EX_HANDLER_ADDR(nasid, slice) \ - PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice)) -#define EX_HANDLER_SIZE 0x0400 - -#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC) -#define EX_FRAME_OFFSET(slice) ((slice) << UALIAS_FLIP_SHIFT | 0x400) -#endif -#define EX_FRAME_ADDR(nasid, slice) \ - PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice)) -#define EX_FRAME_SIZE 0x0c00 #define _ARCSPROM @@ -241,7 +206,7 @@ * The PROM needs to pass the device base address and the * device pci cfg space address to the device drivers during * install. The COMPONENT->Key field is used for this purpose. - * Macros needed by IP27 device drivers to convert the + * Macros needed by SN1 device drivers to convert the * COMPONENT->Key field to the respective base address. * Key field looks as follows: * @@ -256,7 +221,7 @@ * is in place. */ -#if _LANGUAGE_C +#ifndef __ASSEMBLY__ #define uchar unsigned char @@ -301,8 +266,9 @@ #define PUT_INSTALL_STATUS(c,s) c->Revision = s #define GET_INSTALL_STATUS(c) c->Revision -#endif /* LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ #endif /* _STANDALONE */ +#endif /* CONFIG_IA64_SGI_SN1 */ -#endif /* _ASM_SN_SN1_ADDRS_H */ +#endif /* _ASM_IA64_SN_SN1_ADDRS_H */ diff --git a/include/asm-ia64/sn/sn1/arch.h b/include/asm-ia64/sn/sn1/arch.h index 94458112d848..a91b4bcbee14 100644 --- a/include/asm-ia64/sn/sn1/arch.h +++ b/include/asm-ia64/sn/sn1/arch.h @@ -4,29 +4,29 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_ARCH_H -#define _ASM_SN_SN1_ARCH_H +#ifndef _ASM_IA64_SN_SN1_ARCH_H +#define _ASM_IA64_SN_SN1_ARCH_H #if defined(N_MODE) #error "ERROR constants defined only for M-mode" #endif +#include <linux/threads.h> +#include <asm/types.h> + +#define CPUS_PER_NODE 4 /* CPUs on a single hub */ +#define CPUS_PER_SUBNODE 2 /* CPUs on a single hub PI */ + /* * This is the maximum number of NASIDS that can be present in a system. + * This include ALL nodes in ALL partitions connected via NUMALINK. * (Highest NASID plus one.) */ #define MAX_NASIDS 128 /* - * MAXCPUS refers to the maximum number of CPUs in a single kernel. - * This is not necessarily the same as MAXNODES * CPUS_PER_NODE - */ -#define MAXCPUS 512 - -/* * This is the maximum number of nodes that can be part of a kernel. * Effectively, it's the maximum number of compact node ids (cnodeid_t). * This is not necessarily the same as MAX_NASIDS. @@ -40,6 +40,19 @@ #define MAX_NONPREMIUM_REGIONS 16 #define MAX_PREMIUM_REGIONS MAX_REGIONS +/* + * Slot constants for IP35 + */ + +#define MAX_MEM_SLOTS 8 /* max slots per node */ + +#if defined(N_MODE) +#error "N-mode not supported" +#endif + +#define SLOT_SHIFT (30) +#define SLOT_MIN_MEM_SIZE (64*1024*1024) + /* * MAX_PARITIONS refers to the maximum number of logically defined @@ -51,17 +64,14 @@ #define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8) /* - * Slot constants for IP35 + * New stuff in here from Irix sys/pfdat.h. */ +#define SLOT_PFNSHIFT (SLOT_SHIFT - PAGE_SHIFT) +#define PFN_NASIDSHFT (NASID_SHFT - PAGE_SHIFT) +#define slot_getbasepfn(node,slot) (mkpfn(COMPACT_TO_NASID_NODEID(node), slot<<SLOT_PFNSHIFT)) +#define mkpfn(nasid, off) (((pfn_t)(nasid) << PFN_NASIDSHFT) | (off)) -#define MAX_MEM_SLOTS 8 /* max slots per node */ - -#if defined(N_MODE) -#error "N-mode not supported" -#endif -#define SLOT_SHIFT (30) -#define SLOT_MIN_MEM_SIZE (64*1024*1024) /* * two PIs per bedrock, two CPUs per PI @@ -76,4 +86,4 @@ #define TO_SLICE(subn, local) (((subn) << SUBNODE_SHFT) | \ ((local) << LOCALCPU_SHFT)) -#endif /* _ASM_SN_SN1_ARCH_H */ +#endif /* _ASM_IA64_SN_SN1_ARCH_H */ diff --git a/include/asm-ia64/sn/sn1/bedrock.h b/include/asm-ia64/sn/sn1/bedrock.h index 5490125ffcaa..d2e8e0407964 100644 --- a/include/asm-ia64/sn/sn1/bedrock.h +++ b/include/asm-ia64/sn/sn1/bedrock.h @@ -4,14 +4,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_BEDROCK_H -#define _ASM_SN_SN1_BEDROCK_H +#ifndef _ASM_IA64_SN_SN1_BEDROCK_H +#define _ASM_IA64_SN_SN1_BEDROCK_H -#include <linux/config.h> /* The secret password; used to release protection */ #define HUB_PASSWORD 0x53474972756c6573ull @@ -24,7 +22,6 @@ #define MAX_HUB_PATH 80 -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) #include <asm/sn/arch.h> #include <asm/sn/sn1/addrs.h> #include <asm/sn/sn1/hubpi.h> @@ -40,19 +37,13 @@ #include <asm/sn/sn1/hublb_next.h> #include <asm/sn/sn1/hubxb_next.h> -#else /* ! CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */ - -<< BOMB! CONFIG_SGI_IP35 is only defined for IP35 >> - -#endif /* defined(CONFIG_SGI_IP35) */ - /* Translation of uncached attributes */ #define UATTR_HSPEC 0 #define UATTR_IO 1 #define UATTR_MSPEC 2 #define UATTR_UNCAC 3 -#if _LANGUAGE_ASSEMBLY +#if __ASSEMBLY__ /* * Get nasid into register, r (uses at) @@ -63,9 +54,9 @@ and r, LRI_NODEID_MASK; \ dsrl r, LRI_NODEID_SHFT -#endif /* _LANGUAGE_ASSEMBLY */ +#endif /* __ASSEMBLY__ */ -#if _LANGUAGE_C +#ifndef __ASSEMBLY__ #include <asm/sn/xtalk/xwidget.h> @@ -78,6 +69,6 @@ int hub_check_pci_equiv(void *addra, void *addrb); void capture_hub_stats(cnodeid_t, struct nodepda_s *); void init_hub_stats(cnodeid_t, struct nodepda_s *); -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ -#endif /* _ASM_SN_SN1_BEDROCK_H */ +#endif /* _ASM_IA64_SN_SN1_BEDROCK_H */ diff --git a/include/asm-ia64/sn/sn1/hubdev.h b/include/asm-ia64/sn/sn1/hubdev.h index 63aecadf9253..d2108402ea95 100644 --- a/include/asm-ia64/sn/sn1/hubdev.h +++ b/include/asm-ia64/sn/sn1/hubdev.h @@ -4,12 +4,11 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_HUBDEV_H -#define _ASM_SN_SN1_HUBDEV_H +#ifndef _ASM_IA64_SN_SN1_HUBDEV_H +#define _ASM_IA64_SN_SN1_HUBDEV_H extern void hubdev_init(void); extern void hubdev_register(int (*attach_method)(devfs_handle_t)); @@ -19,4 +18,4 @@ extern int hubdev_docallouts(devfs_handle_t hub); extern caddr_t hubdev_prombase_get(devfs_handle_t hub); extern cnodeid_t hubdev_cnodeid_get(devfs_handle_t hub); -#endif /* _ASM_SN_SN1_HUBDEV_H */ +#endif /* _ASM_IA64_SN_SN1_HUBDEV_H */ diff --git a/include/asm-ia64/sn/sn1/hubio.h b/include/asm-ia64/sn/sn1/hubio.h index 523741108d1d..7851fe4f7aac 100644 --- a/include/asm-ia64/sn/sn1/hubio.h +++ b/include/asm-ia64/sn/sn1/hubio.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ /************************************************************************ @@ -20,8 +19,8 @@ ************************************************************************/ -#ifndef _ASM_SN_SN1_HUBIO_H -#define _ASM_SN_SN1_HUBIO_H +#ifndef _ASM_IA64_SN_SN1_HUBIO_H +#define _ASM_IA64_SN_SN1_HUBIO_H #define IIO_WID 0x00400000 /* @@ -762,7 +761,7 @@ -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /************************************************************************ * * @@ -2942,15 +2941,15 @@ typedef union ii_ixss_u { typedef union ii_ilct_u { bdrkreg_t ii_ilct_regval; struct { - bdrkreg_t i_rsvd : 9; - bdrkreg_t i_test_err_capture : 1; - bdrkreg_t i_test_clear : 1; - bdrkreg_t i_test_flit : 3; - bdrkreg_t i_test_cberr : 1; - bdrkreg_t i_test_valid : 1; - bdrkreg_t i_test_data : 20; - bdrkreg_t i_test_mask : 8; - bdrkreg_t i_test_seed : 20; + bdrkreg_t i_test_seed : 20; + bdrkreg_t i_test_mask : 8; + bdrkreg_t i_test_data : 20; + bdrkreg_t i_test_valid : 1; + bdrkreg_t i_test_cberr : 1; + bdrkreg_t i_test_flit : 3; + bdrkreg_t i_test_clear : 1; + bdrkreg_t i_test_err_capture : 1; + bdrkreg_t i_rsvd : 9; } ii_ilct_fld_s; } ii_ilct_u_t; @@ -4935,7 +4934,7 @@ typedef union ii_ippr_u { -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /************************************************************************ * * @@ -5014,4 +5013,4 @@ typedef union ii_ippr_u { -#endif /* _ASM_SN_SN1_HUBIO_H */ +#endif /* _ASM_IA64_SN_SN1_HUBIO_H */ diff --git a/include/asm-ia64/sn/sn1/hubio_next.h b/include/asm-ia64/sn/sn1/hubio_next.h index 9d9a0c63ef81..037d3bae307d 100644 --- a/include/asm-ia64/sn/sn1/hubio_next.h +++ b/include/asm-ia64/sn/sn1/hubio_next.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_HUBIO_NEXT_H -#define _ASM_SN_SN1_HUBIO_NEXT_H +#ifndef _ASM_IA64_SN_SN1_HUBIO_NEXT_H +#define _ASM_IA64_SN_SN1_HUBIO_NEXT_H /* * Slightly friendlier names for some common registers. @@ -64,7 +63,7 @@ #define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ #define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ #define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ -#define IIO_BTE_OFF_1 IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */ +#define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */ /* BTE register offsets from base */ #define BTEOFF_STAT 0 @@ -78,11 +77,16 @@ /* names used in hub_diags.c; carried over from SN0 */ #define IIO_BASE_BTE0 IIO_IBLS_0 #define IIO_BASE_BTE1 IIO_IBLS_1 -#if 0 -#define IIO_BASE IIO_WID -#define IIO_BASE_PERF IIO_IPCR /* IO Performance Control */ -#define IIO_PERF_CNT IIO_IPPR /* IO Performance Profiling */ -#endif + +/* + * Macro which takes the widget number, and returns the + * IO PRB address of that widget. + * value _x is expected to be a widget number in the range + * 0, 8 - 0xF + */ +#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ + (_x) : \ + (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) /* GFX Flow Control Node/Widget Register */ @@ -139,7 +143,7 @@ * redefined big window 7 as small window 0. XXX does this still apply for SN1?? */ -#define HUB_NUM_BIG_WINDOW IIO_NUM_ITTES - 1 +#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) /* * Use the top big window as a surrogate for the first small window @@ -343,7 +347,7 @@ * CRBs. */ -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /* * Easy access macros for CRBs, all 4 registers (A-D) @@ -389,7 +393,7 @@ typedef ii_icrb0_d_u_t icrbd_t; #define icrbd_context ii_icrb0_d_fld_s.id_context #define d_regvalue ii_icrb0_d_regval -#endif /* LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /* Number of widgets supported by hub */ #define HUB_NUM_WIDGET 9 @@ -399,7 +403,7 @@ typedef ii_icrb0_d_u_t icrbd_t; #define HUB_WIDGET_PART_NUM 0xc110 #define MAX_HUBS_PER_XBOW 2 -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /* A few more #defines for backwards compatibility */ #define iprb_t ii_iprb0_u_t #define iprb_regval ii_iprb0_regval @@ -430,11 +434,11 @@ typedef ii_icrb0_d_u_t icrbd_t; #define IO_PERF_SETS 32 #if __KERNEL__ -#if _LANGUAGE_C +#ifndef __ASSEMBLY__ /* XXX moved over from SN/SN0/hubio.h -- each should be checked for SN1 */ #include <asm/sn/alenlist.h> #include <asm/sn/dmamap.h> -#include <asm/sn/iobus.h> +#include <asm/sn/driver.h> #include <asm/sn/xtalk/xtalk.h> /* Bit for the widget in inbound access register */ @@ -699,12 +703,9 @@ hub_intr_free(hub_intr_t intr_hdl); extern int hub_intr_connect( hub_intr_t intr_hdl, /* xtalk intr resource hndl */ - intr_func_t intr_func, /* xtalk intr handler */ - void *intr_arg, /* arg to intr handler */ xtalk_intr_setfunc_t setfunc, /* func to set intr hw */ - void *setfunc_arg, /* arg to setfunc */ - void *thread); /* intr thread to use */ + void *setfunc_arg); /* arg to setfunc */ extern void hub_intr_disconnect(hub_intr_t intr_hdl); @@ -756,6 +757,6 @@ extern void hub_widgetdev_enable(devfs_handle_t, int); extern void hub_widgetdev_shutdown(devfs_handle_t, int); extern int hub_dma_enabled(devfs_handle_t); -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ #endif /* _KERNEL */ -#endif /* _ASM_SN_SN1_HUBIO_NEXT_H */ +#endif /* _ASM_IA64_SN_SN1_HUBIO_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hublb.h b/include/asm-ia64/sn/sn1/hublb.h index 692eeab44b39..60082cafac5d 100644 --- a/include/asm-ia64/sn/sn1/hublb.h +++ b/include/asm-ia64/sn/sn1/hublb.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ /************************************************************************ @@ -20,8 +19,8 @@ ************************************************************************/ -#ifndef _ASM_SN_SN1_HUBLB_H -#define _ASM_SN_SN1_HUBLB_H +#ifndef _ASM_IA64_SN_SN1_HUBLB_H +#define _ASM_IA64_SN_SN1_HUBLB_H #define LB_REV_ID 0x00600000 /* @@ -251,7 +250,7 @@ -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /************************************************************************ * * @@ -1593,7 +1592,7 @@ typedef union lb_vector_status_clear_u { -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /************************************************************************ * * @@ -1605,4 +1604,4 @@ typedef union lb_vector_status_clear_u { -#endif /* _ASM_SN_SN1_HUBLB_H */ +#endif /* _ASM_IA64_SN_SN1_HUBLB_H */ diff --git a/include/asm-ia64/sn/sn1/hublb_next.h b/include/asm-ia64/sn/sn1/hublb_next.h index a0c8430f1e05..5b14992fc6d2 100644 --- a/include/asm-ia64/sn/sn1/hublb_next.h +++ b/include/asm-ia64/sn/sn1/hublb_next.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_HUBLB_NEXT_H -#define _ASM_SN_SN1_HUBLB_NEXT_H +#ifndef _ASM_IA64_SN_SN1_HUBLB_NEXT_H +#define _ASM_IA64_SN_SN1_HUBLB_NEXT_H /********************************************************************** @@ -107,4 +106,4 @@ #define PIOTYPE_PROT_ERR 6 /* VECTOR_STATUS only */ #define PIOTYPE_UNKNOWN 7 /* VECTOR_STATUS only */ -#endif /* _ASM_SN_SN1_HUBLB_NEXT_H */ +#endif /* _ASM_IA64_SN_SN1_HUBLB_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hubmd.h b/include/asm-ia64/sn/sn1/hubmd.h index 681e2fb4285d..09001472d71d 100644 --- a/include/asm-ia64/sn/sn1/hubmd.h +++ b/include/asm-ia64/sn/sn1/hubmd.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_HUBMD_H -#define _ASM_SN_SN1_HUBMD_H +#ifndef _ASM_IA64_SN_SN1_HUBMD_H +#define _ASM_IA64_SN_SN1_HUBMD_H /************************************************************************ @@ -315,7 +314,7 @@ -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /************************************************************************ * * @@ -2140,7 +2139,7 @@ typedef union md_mb_ecc_config_u { * corresponds to the valid bit, and bit 1 of each two-bit field * * corresponds to the overrun bit. * * The rule for the valid bit is that it gets set whenever that error * - * occurs, regardless of whether a higher priority error has occurred. * + * occurs, regardless of whether a higher priority error has occurred. * * The rule for the overrun bit is that it gets set whenever we are * * unable to record the address information for this particular * * error, due to a previous error of the same or higher priority. * @@ -2463,7 +2462,7 @@ typedef union md_mb_debug_u { -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /************************************************************************ * * @@ -2474,4 +2473,4 @@ typedef union md_mb_debug_u { -#endif /* _ASM_SN_SN1_HUBMD_H */ +#endif /* _ASM_IA64_SN_SN1_HUBMD_H */ diff --git a/include/asm-ia64/sn/sn1/hubmd_next.h b/include/asm-ia64/sn/sn1/hubmd_next.h index da8e587596a3..263dc66e78f2 100644 --- a/include/asm-ia64/sn/sn1/hubmd_next.h +++ b/include/asm-ia64/sn/sn1/hubmd_next.h @@ -4,13 +4,11 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_HUBMD_NEXT_H -#define _ASM_SN_SN1_HUBMD_NEXT_H +#ifndef _ASM_IA64_SN_SN1_HUBMD_NEXT_H +#define _ASM_IA64_SN_SN1_HUBMD_NEXT_H -#ifdef BRINGUP /* XXX moved over from SN/SN0/hubmd.h -- each should be checked for SN1 */ /* In fact, most of this stuff is wrong. Some is correct, such as * MD_PAGE_SIZE and MD_PAGE_NUM_SHFT. @@ -147,7 +145,7 @@ #define MD_SPROT_REFCNT_GET(value) ( \ ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT) -#if _LANGUAGE_C +#ifndef __ASSEMBLY__ #ifdef LITTLE_ENDIAN typedef union md_perf_sel { @@ -171,9 +169,8 @@ typedef union md_perf_sel { } md_perf_sel_t; #endif -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ -#endif /* BRINGUP */ /* Like SN0, SN1 supports a mostly-flat address space with 8 CPU-visible, evenly spaced, contiguous regions, or "software @@ -300,7 +297,7 @@ typedef union md_perf_sel { ***********************************************************************/ -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /* Standard Directory Entries */ @@ -533,7 +530,7 @@ typedef union md_pdir { struct md_pdir_sparse_fmt pds_fmt; } md_pdir_t; -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /********************************************************************** @@ -568,7 +565,7 @@ typedef union md_pdir { #define MD_DIR_WAIT (UINT64_CAST 0x6) /* ptr format, hw-defined */ #define MD_DIR_POISONED (UINT64_CAST 0x7) /* ptr format, hw-defined */ -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /* Convert format and state fields into a single "cacheline state" value, defined above */ @@ -578,7 +575,7 @@ typedef union md_pdir { MD_DIR_SHARED) #define MD_DIR_STATE(x) MD_FMT_ST_TO_STATE(MD_DIR_FORMAT(x), MD_DIR_STVAL(x)) -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ @@ -812,4 +809,4 @@ typedef union md_pdir { #define MFC_ADDR_SHFT 6 -#endif /* _ASM_SN_SN1_HUBMD_NEXT_H */ +#endif /* _ASM_IA64_SN_SN1_HUBMD_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hubni.h b/include/asm-ia64/sn/sn1/hubni.h index 018aa9de6e9d..6bfc241fac8f 100644 --- a/include/asm-ia64/sn/sn1/hubni.h +++ b/include/asm-ia64/sn/sn1/hubni.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_HUBNI_H -#define _ASM_SN_SN1_HUBNI_H +#ifndef _ASM_IA64_SN_SN1_HUBNI_H +#define _ASM_IA64_SN_SN1_HUBNI_H /************************************************************************ @@ -1000,7 +999,7 @@ -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /************************************************************************ * * @@ -1615,7 +1614,7 @@ typedef union ni_global_table_u { -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /************************************************************************ * * @@ -1779,4 +1778,4 @@ typedef union ni_global_table_u { -#endif /* _ASM_SN_SN1_HUBNI_H */ +#endif /* _ASM_IA64_SN_SN1_HUBNI_H */ diff --git a/include/asm-ia64/sn/sn1/hubni_next.h b/include/asm-ia64/sn/sn1/hubni_next.h index 3d0dbed4c932..ebee5b7ad973 100644 --- a/include/asm-ia64/sn/sn1/hubni_next.h +++ b/include/asm-ia64/sn/sn1/hubni_next.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_HUBNI_NEXT_H -#define _ASM_SN_SN1_HUBNI_NEXT_H +#ifndef _ASM_IA64_SN_SN1_HUBNI_NEXT_H +#define _ASM_IA64_SN_SN1_HUBNI_NEXT_H #define NI_LOCAL_ENTRIES 128 #define NI_META_ENTRIES 1 @@ -67,7 +66,7 @@ NPE_EXTLONG_MASK | NPE_EXTSHORT_MASK |\ NPE_FIFOOVFLOW_MASK | NPE_TAILTO_MASK) -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /* NI_PORT_HEADER[AB] registers (not automatically generated) */ #ifdef LITTLE_ENDIAN @@ -172,4 +171,4 @@ typedef union ni_port_header_b_u { 0x6 << NPP_NULL_TIMEOUT_SHFT | \ 0x3f0 << NPP_MAX_BURST_SHFT) -#endif /* _ASM_SN_SN1_HUBNI_NEXT_H */ +#endif /* _ASM_IA64_SN_SN1_HUBNI_NEXT_H */ diff --git a/include/asm-ia64/sn/sn1/hubpi.h b/include/asm-ia64/sn/sn1/hubpi.h index 4b81ca32be43..7c698412621a 100644 --- a/include/asm-ia64/sn/sn1/hubpi.h +++ b/include/asm-ia64/sn/sn1/hubpi.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_HUBPI_H -#define _ASM_SN_SN1_HUBPI_H +#ifndef _ASM_IA64_SN_SN1_HUBPI_H +#define _ASM_IA64_SN_SN1_HUBPI_H /************************************************************************ * * @@ -551,7 +550,7 @@ -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /************************************************************************ * * @@ -4248,7 +4247,7 @@ typedef union pi_perf_cntr1_b_u { -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /************************************************************************ * * @@ -4261,4 +4260,4 @@ typedef union pi_perf_cntr1_b_u { #define PI_GFX_PAGE_ENABLE 0x0000010000000000LL -#endif /* _ASM_SN_SN1_HUBPI_H */ +#endif /* _ASM_IA64_SN_SN1_HUBPI_H */ diff --git a/include/asm-ia64/sn/sn1/hubpi_next.h b/include/asm-ia64/sn/sn1/hubpi_next.h index 628b0ec1abc5..a4ea9f3277ba 100644 --- a/include/asm-ia64/sn/sn1/hubpi_next.h +++ b/include/asm-ia64/sn/sn1/hubpi_next.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_HUBPI_NEXT_H -#define _ASM_SN_SN1_HUBPI_NEXT_H +#ifndef _ASM_IA64_SN_SN1_HUBPI_NEXT_H +#define _ASM_IA64_SN_SN1_HUBPI_NEXT_H /* define for remote PI_1 space. It is always half of a node_addressspace @@ -54,7 +53,7 @@ ((sts) & (PI_CRB_STS_I | PI_CRB_STS_H) | \ ((sts) & (PI_CRB_STS_A | PI_CRB_STS_R)) >> 1) -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /* * format of error stack and error status registers. */ @@ -329,4 +328,4 @@ typedef union pi_err_stat1 { /* Error stack address shift, for use with pi_stk_fmt.sk_addr */ #define ERR_STK_ADDR_SHFT 3 -#endif /* _ASM_SN_SN1_HUBPI_NEXT_H */ +#endif /* _ASM_IA64_SN_SN1_HUBPI_NEXT_H */ diff --git a/include/asm-ia64/sn/hubspc.h b/include/asm-ia64/sn/sn1/hubspc.h index 9241ab516824..c0af0b6de551 100644 --- a/include/asm-ia64/sn/hubspc.h +++ b/include/asm-ia64/sn/sn1/hubspc.h @@ -1,14 +1,13 @@ -/* $Id$ +/* * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_HUBSPC_H -#define _ASM_SN_HUBSPC_H +#ifndef _ASM_IA64_SN_SN1_HUBSPC_H +#define _ASM_IA64_SN_SN1_HUBSPC_H typedef enum { HUBSPC_REFCOUNTERS, @@ -22,4 +21,4 @@ typedef enum { extern int refcounters_attach(devfs_handle_t hub); -#endif /* _ASM_SN_HUBSPC_H */ +#endif /* _ASM_IA64_SN_SN1_HUBSPC_H */ diff --git a/include/asm-ia64/sn/sn1/hubstat.h b/include/asm-ia64/sn/sn1/hubstat.h new file mode 100644 index 000000000000..ddf3626243d0 --- /dev/null +++ b/include/asm-ia64/sn/sn1/hubstat.h @@ -0,0 +1,56 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 - 2001 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_SN_SN1_HUBSTAT_H +#define _ASM_IA64_SN_SN1_HUBSTAT_H + +typedef int64_t hub_count_t; + +#define HUBSTAT_VERSION 1 + +typedef struct hubstat_s { + char hs_version; /* structure version */ + cnodeid_t hs_cnode; /* cnode of this hub */ + nasid_t hs_nasid; /* Nasid of same */ + int64_t hs_timebase; /* Time of first sample */ + int64_t hs_timestamp; /* Time of last sample */ + int64_t hs_per_minute; /* Ticks per minute */ + + union { + hubreg_t hs_niu_stat_rev_id; /* SN0: Status rev ID */ + hubreg_t hs_niu_port_status; /* SN1: Port status */ + } hs_niu; + + hub_count_t hs_ni_retry_errors; /* Total retry errors */ + hub_count_t hs_ni_sn_errors; /* Total sn errors */ + hub_count_t hs_ni_cb_errors; /* Total cb errors */ + int hs_ni_overflows; /* NI count overflows */ + hub_count_t hs_ii_sn_errors; /* Total sn errors */ + hub_count_t hs_ii_cb_errors; /* Total cb errors */ + int hs_ii_overflows; /* II count overflows */ + + /* + * Anything below this comment is intended for kernel internal-use + * only and may be changed at any time. + * + * Any members that contain pointers or are conditionally compiled + * need to be below here also. + */ + int64_t hs_last_print; /* When we last printed */ + char hs_print; /* Should we print */ + + char *hs_name; /* This hub's name */ + unsigned char hs_maint; /* Should we print to availmon */ +} hubstat_t; + +#define hs_ni_stat_rev_id hs_niu.hs_niu_stat_rev_id +#define hs_ni_port_status hs_niu.hs_niu_port_status + +extern struct file_operations hub_mon_fops; + +#endif /* _ASM_IA64_SN_SN1_HUBSTAT_H */ diff --git a/include/asm-ia64/sn/sn1/hubxb.h b/include/asm-ia64/sn/sn1/hubxb.h index 21044fdfd107..8a9ee36ae312 100644 --- a/include/asm-ia64/sn/sn1/hubxb.h +++ b/include/asm-ia64/sn/sn1/hubxb.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_HUBXB_H -#define _ASM_SN_SN1_HUBXB_H +#ifndef _ASM_IA64_SN_SN1_HUBXB_H +#define _ASM_IA64_SN_SN1_HUBXB_H /************************************************************************ * * @@ -273,7 +272,7 @@ -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /************************************************************************ * * @@ -1247,7 +1246,7 @@ typedef union xb_first_error_clear_u { -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ /************************************************************************ * * @@ -1286,4 +1285,4 @@ typedef union xb_first_error_clear_u { -#endif /* _ASM_SN_SN1_HUBXB_H */ +#endif /* _ASM_IA64_SN_SN1_HUBXB_H */ diff --git a/include/asm-ia64/sn/sn1/hubxb_next.h b/include/asm-ia64/sn/sn1/hubxb_next.h index d17e45ecd0af..b9df887b9373 100644 --- a/include/asm-ia64/sn/sn1/hubxb_next.h +++ b/include/asm-ia64/sn/sn1/hubxb_next.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_HUBXB_NEXT_H -#define _ASM_SN_SN1_HUBXB_NEXT_H +#ifndef _ASM_IA64_SN_SN1_HUBXB_NEXT_H +#define _ASM_IA64_SN_SN1_HUBXB_NEXT_H /* XB_FIRST_ERROR fe_source field encoding */ #define XVE_SOURCE_POQ0 0xf /* 1111 */ @@ -30,4 +29,4 @@ #define XBP_RESET_DEFAULTS 0x0008000080000021LL #define XBP_ACTIVE_DEFAULTS 0x00080000fffff021LL -#endif /* _ASM_SN_SN1_HUBXB_NEXT_H */ +#endif /* _ASM_IA64_SN_SN1_HUBXB_NEXT_H */ diff --git a/include/asm-ia64/sn/hwcntrs.h b/include/asm-ia64/sn/sn1/hwcntrs.h index 2febee93e60d..0ec78e887ab5 100644 --- a/include/asm-ia64/sn/hwcntrs.h +++ b/include/asm-ia64/sn/sn1/hwcntrs.h @@ -1,14 +1,13 @@ -/* $Id$ +/* * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_HWCNTRS_H -#define _ASM_SN_HWCNTRS_H +#ifndef _ASM_IA64_SN_SN1_HWCNTRS_H +#define _ASM_IA64_SN_SN1_HWCNTRS_H typedef uint64_t refcnt_t; @@ -49,7 +48,7 @@ typedef struct rcb_info { uint64_t rcb_len; /* total refcnt buffer len in bytes */ int rcb_sw_sets; /* number of sw counter sets in buffer */ - int rcb_sw_counters_per_set; /* sw counters per set -- numnodes */ + int rcb_sw_counters_per_set; /* sw counters per set -- num_compact_nodes */ int rcb_sw_counter_size; /* sizeof(refcnt_t) -- size of sw cntr */ int rcb_base_pages; /* number of base pages in node */ @@ -94,4 +93,4 @@ extern int migr_refcnt_enabled(void); #endif /* __KERNEL__ */ -#endif /* _ASM_SN_HWCNTRS_H */ +#endif /* _ASM_IA64_SN_SN1_HWCNTRS_H */ diff --git a/include/asm-ia64/sn/sn1/intr.h b/include/asm-ia64/sn/sn1/intr.h new file mode 100644 index 000000000000..8a46d66e20ab --- /dev/null +++ b/include/asm-ia64/sn/sn1/intr.h @@ -0,0 +1,237 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + */ +#ifndef _ASM_IA64_SN_SN1_INTR_H +#define _ASM_IA64_SN_SN1_INTR_H + +/* Subnode wildcard */ +#define SUBNODE_ANY (-1) + +/* Number of interrupt levels associated with each interrupt register. */ +#define N_INTPEND_BITS 64 + +#define INT_PEND0_BASELVL 0 +#define INT_PEND1_BASELVL 64 + +#define N_INTPENDJUNK_BITS 8 +#define INTPENDJUNK_CLRBIT 0x80 + +#include <asm/sn/intr_public.h> +#include <asm/sn/driver.h> +#include <asm/sn/xtalk/xtalk.h> +#include <asm/sn/hack.h> + +#ifndef __ASSEMBLY__ +#define II_NAMELEN 24 + +/* + * Dispatch table entry - contains information needed to call an interrupt + * routine. + */ +typedef struct intr_vector_s { + intr_func_t iv_func; /* Interrupt handler function */ + intr_func_t iv_prefunc; /* Interrupt handler prologue func */ + void *iv_arg; /* Argument to pass to handler */ + cpuid_t iv_mustruncpu; /* Where we must run. */ +} intr_vector_t; + +/* Interrupt information table. */ +typedef struct intr_info_s { + xtalk_intr_setfunc_t ii_setfunc; /* Function to set the interrupt + * destination and level register. + * It returns 0 (success) or an + * error code. + */ + void *ii_cookie; /* arg passed to setfunc */ + devfs_handle_t ii_owner_dev; /* device that owns this intr */ + char ii_name[II_NAMELEN]; /* Name of this intr. */ + int ii_flags; /* informational flags */ +} intr_info_t; + + +#define THD_CREATED 0x00000001 /* + * We've created a thread for this + * interrupt. + */ + +/* + * Bits for ii_flags: + */ +#define II_UNRESERVE 0 +#define II_RESERVE 1 /* Interrupt reserved. */ +#define II_INUSE 2 /* Interrupt connected */ +#define II_ERRORINT 4 /* INterrupt is an error condition */ +#define II_THREADED 8 /* Interrupt handler is threaded. */ + +/* + * Interrupt level wildcard + */ +#define INTRCONNECT_ANYBIT (-1) + +/* + * This structure holds information needed both to call and to maintain + * interrupts. The two are in separate arrays for the locality benefits. + * Since there's only one set of vectors per hub chip (but more than one + * CPU, the lock to change the vector tables must be here rather than in + * the PDA. + */ + +typedef struct intr_vecblk_s { + intr_vector_t vectors[N_INTPEND_BITS]; /* information needed to + call an intr routine. */ + intr_info_t info[N_INTPEND_BITS]; /* information needed only + to maintain interrupts. */ + spinlock_t vector_lock; /* Lock for this and the + masks in the PDA. */ + splfunc_t vector_spl; /* vector_lock req'd spl */ + int vector_state; /* Initialized to zero. + Set to INTR_INITED + by hubintr_init. + */ + int vector_count; /* Number of vectors + * reserved. + */ + int cpu_count[CPUS_PER_SUBNODE]; /* How many interrupts are + * connected to each CPU + */ + int ithreads_enabled; /* Are interrupt threads + * initialized on this node. + * and block? + */ +} intr_vecblk_t; + +/* Possible values for vector_state: */ +#define VECTOR_UNINITED 0 +#define VECTOR_INITED 1 +#define VECTOR_SET 2 + +#define hub_intrvect0 private.p_intmasks.dispatch0->vectors +#define hub_intrvect1 private.p_intmasks.dispatch1->vectors +#define hub_intrinfo0 private.p_intmasks.dispatch0->info +#define hub_intrinfo1 private.p_intmasks.dispatch1->info + +/* + * Macros to manipulate the interrupt register on the calling hub chip. + */ + +#define LOCAL_HUB_SEND_INTR(_level) LOCAL_HUB_S(PI_INT_PEND_MOD, \ + (0x100|(_level))) +#define REMOTE_HUB_PI_SEND_INTR(_hub, _sn, _level) \ + REMOTE_HUB_PI_S((_hub), _sn, PI_INT_PEND_MOD, (0x100|(_level))) + +#define REMOTE_CPU_SEND_INTR(_cpuid, _level) \ + REMOTE_HUB_PI_S(cpuid_to_nasid(_cpuid), \ + SUBNODE(cpuid_to_slice(_cpuid)), \ + PI_INT_PEND_MOD, (0x100|(_level))) + +/* + * When clearing the interrupt, make sure this clear does make it + * to the hub. Otherwise we could end up losing interrupts. + * We do an uncached load of the int_pend0 register to ensure this. + */ + +#define LOCAL_HUB_CLR_INTR(_level) \ + LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)), \ + LOCAL_HUB_L(PI_INT_PEND0) +#define REMOTE_HUB_PI_CLR_INTR(_hub, _sn, _level) \ + REMOTE_HUB_PI_S((_hub), (_sn), PI_INT_PEND_MOD, (_level)), \ + REMOTE_HUB_PI_L((_hub), (_sn), PI_INT_PEND0) + +/* Special support for use by gfx driver only. Supports special gfx hub interrupt. */ +extern void install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg); + +void setrtvector(intr_func_t func); + +/* + * Interrupt blocking + */ +extern void intr_block_bit(cpuid_t cpu, int bit); +extern void intr_unblock_bit(cpuid_t cpu, int bit); + +#endif /* __ASSEMBLY__ */ + +/* + * Hard-coded interrupt levels: + */ + +/* + * L0 = SW1 + * L1 = SW2 + * L2 = INT_PEND0 + * L3 = INT_PEND1 + * L4 = RTC + * L5 = Profiling Timer + * L6 = Hub Errors + * L7 = Count/Compare (T5 counters) + */ + + +/* INT_PEND0 hard-coded bits. */ +#ifdef DEBUG_INTR_TSTAMP +/* hard coded interrupt level for interrupt latency test interrupt */ +#define CPU_INTRLAT_B 62 +#define CPU_INTRLAT_A 61 +#endif + +/* Hardcoded bits required by software. */ +#define MSC_MESG_INTR 9 +#define CPU_ACTION_B 8 +#define CPU_ACTION_A 7 + +/* These are determined by hardware: */ +#define CC_PEND_B 6 +#define CC_PEND_A 5 +#define UART_INTR 4 +#define PG_MIG_INTR 3 +#define GFX_INTR_B 2 +#define GFX_INTR_A 1 +#define RESERVED_INTR 0 + +/* INT_PEND1 hard-coded bits: */ +#define MSC_PANIC_INTR 63 +#define NI_ERROR_INTR 62 +#define MD_COR_ERR_INTR 61 +#define COR_ERR_INTR_B 60 +#define COR_ERR_INTR_A 59 +#define CLK_ERR_INTR 58 + +# define NACK_INT_B 57 +# define NACK_INT_A 56 +# define LB_ERROR 55 +# define XB_ERROR 54 + +#define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch Bridge Errors */ + +#define IP27_INTR_0 52 /* Reserved for PROM use */ +#define IP27_INTR_1 51 /* (do not use in Kernel) */ +#define IP27_INTR_2 50 +#define IP27_INTR_3 49 +#define IP27_INTR_4 48 +#define IP27_INTR_5 47 +#define IP27_INTR_6 46 +#define IP27_INTR_7 45 + +#define TLB_INTR_B 44 /* used for tlb flush random */ +#define TLB_INTR_A 43 + +#define LLP_PFAIL_INTR_B 42 /* see ml/SN/SN0/sysctlr.c */ +#define LLP_PFAIL_INTR_A 41 + +#define NI_BRDCAST_ERR_B 40 +#define NI_BRDCAST_ERR_A 39 + +# define IO_ERROR_INTR 38 /* set up by prom */ +# define DEBUG_INTR_B 37 /* used by symmon to stop all cpus */ +# define DEBUG_INTR_A 36 + +// These aren't strictly accurate or complete. See the +// Synergy Spec. for details. +#define SGI_UART_IRQ (65) +#define SGI_HUB_ERROR_IRQ (182) + +#endif /* _ASM_IA64_SN_SN1_INTR_H */ diff --git a/include/asm-ia64/sn/sn1/intr_public.h b/include/asm-ia64/sn/sn1/intr_public.h new file mode 100644 index 000000000000..d75df99de88c --- /dev/null +++ b/include/asm-ia64/sn/sn1/intr_public.h @@ -0,0 +1,53 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + */ +#ifndef _ASM_IA64_SN_SN1_INTR_PUBLIC_H +#define _ASM_IA64_SN_SN1_INTR_PUBLIC_H + +/* REMEMBER: If you change these, the whole world needs to be recompiled. + * It would also require changing the hubspl.s code and SN0/intr.c + * Currently, the spl code has no support for multiple INTPEND1 masks. + */ + +#define N_INTPEND0_MASKS 1 +#define N_INTPEND1_MASKS 1 + +#define INTPEND0_MAXMASK (N_INTPEND0_MASKS - 1) +#define INTPEND1_MAXMASK (N_INTPEND1_MASKS - 1) + +#ifndef __ASSEMBLY__ +#include <asm/sn/arch.h> + +struct intr_vecblk_s; /* defined in asm/sn/intr.h */ + +/* + * The following are necessary to create the illusion of a CEL + * on the IP27 hub. We'll add more priority levels soon, but for + * now, any interrupt in a particular band effectively does an spl. + * These must be in the PDA since they're different for each processor. + * Users of this structure must hold the vector_lock in the appropriate vector + * block before modifying the mask arrays. There's only one vector block + * for each Hub so a lock in the PDA wouldn't be adequate. + */ +typedef struct hub_intmasks_s { + /* + * The masks are stored with the lowest-priority (most inclusive) + * in the lowest-numbered masks (i.e., 0, 1, 2...). + */ + /* INT_PEND0: */ + hubreg_t intpend0_masks[N_INTPEND0_MASKS]; + /* INT_PEND1: */ + hubreg_t intpend1_masks[N_INTPEND1_MASKS]; + /* INT_PEND0: */ + struct intr_vecblk_s *dispatch0; + /* INT_PEND1: */ + struct intr_vecblk_s *dispatch1; +} hub_intmasks_t; + +#endif /* __ASSEMBLY__ */ +#endif /* _ASM_IA64_SN_SN1_INTR_PUBLIC_H */ diff --git a/include/asm-ia64/sn/sn1/ip27config.h b/include/asm-ia64/sn/sn1/ip27config.h index 6767b999d234..71b92c46697a 100644 --- a/include/asm-ia64/sn/sn1/ip27config.h +++ b/include/asm-ia64/sn/sn1/ip27config.h @@ -4,12 +4,11 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_IP27CONFIG_H -#define _ASM_SN_SN1_IP27CONFIG_H +#ifndef _ASM_IA64_SN_SN1_IP27CONFIG_H +#define _ASM_IA64_SN_SN1_IP27CONFIG_H /* @@ -50,7 +49,7 @@ */ #define IP27_RTC_FREQ 1250 /* 800ns cycle time */ -#if _LANGUAGE_C +#ifndef __ASSEMBLY__ typedef struct ip27config_s { /* KEEP IN SYNC w/ start.s & below */ uint time_const; /* Time constant */ @@ -110,9 +109,9 @@ typedef struct { */ #define CONFIG_12P4I_NODE(n) (0) -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ -#if _LANGUAGE_ASSEMBLY +#if __ASSEMBLY__ .struct 0 /* KEEP IN SYNC WITH C structure */ ip27c_time_const: .word 0 @@ -137,7 +136,7 @@ ip27c_pvers_vers: .word 0 ip27c_pvers_rev: .word 0 ip27c_config_type: .word 0 /* To recognize special configs */ -#endif /* _LANGUAGE_ASSEMBLY */ +#endif /* __ASSEMBLY__ */ /* * R10000 Configuration Cycle - These define the SYSAD values used @@ -245,7 +244,7 @@ ip27c_config_type: .word 0 /* To recognize special configs */ #define CONFIG_FREQ_RTC IP27C_KHZ(IP27_RTC_FREQ) -#if _LANGUAGE_C +#ifndef __ASSEMBLY__ /* we are going to define all the known configs is a table * for building hex images we will pull out the particular @@ -258,7 +257,7 @@ ip27c_config_type: .word 0 /* To recognize special configs */ */ /* these numbers are as the are ordered in the table below */ -#define IP27_CONFIG_UNKNOWN -1 +#define IP27_CONFIG_UNKNOWN (-1) #define IP27_CONFIG_SN1_1MB_200_400_200_TABLE 0 #define IP27_CONFIG_SN00_4MB_100_200_133_TABLE 1 #define IP27_CONFIG_SN1_4MB_200_400_267_TABLE 2 @@ -500,9 +499,9 @@ extern config_modifiable_t ip_config_table[]; #define CONFIG_FPROM_WR ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_wr #endif /* IP27_CONFIG_SN1_4MB_180_360_240 */ -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ -#if _LANGUAGE_ASSEMBLY +#if __ASSEMBLY__ /* these need to be in here since we need assembly definitions * for building hex images (as required by start.s) @@ -653,6 +652,6 @@ extern config_modifiable_t ip_config_table[]; #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE #endif /* IP27_CONFIG_SN1_4MB_180_360_240 */ -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ -#endif /* _ASM_SN_SN1_IP27CONFIG_H */ +#endif /* _ASM_IA64_SN_SN1_IP27CONFIG_H */ diff --git a/include/asm-ia64/sn/sn1/kldir.h b/include/asm-ia64/sn/sn1/kldir.h deleted file mode 100644 index e8d4935d86f3..000000000000 --- a/include/asm-ia64/sn/sn1/kldir.h +++ /dev/null @@ -1,222 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam - */ - -#ifndef _ASM_SN_SN1_KLDIR_H -#define _ASM_SN_SN1_KLDIR_H - -/* - * The upper portion of the memory map applies during boot - * only and is overwritten by IRIX/SYMMON. The minimum memory bank - * size on IP35 is 64M, which provides a limit on the amount of space - * the PROM can assume it has available. - * - * Most of the addresses below are defined as macros in this file, or - * in SN/addrs.h or SN/SN1/addrs.h. - * - * MEMORY MAP PER NODE - * - * 0x4000000 (64M) +-----------------------------------------+ - * | | - * | | - * | IO7 TEXT/DATA/BSS/stack | - * 0x3000000 (48M) +-----------------------------------------+ - * | Free | - * 0x2102000 (>33M) +-----------------------------------------+ - * | IP35 Topology (PCFG) + misc data | - * 0x2000000 (32M) +-----------------------------------------+ - * | IO7 BUFFERS FOR FLASH ENET IOC3 | - * 0x1F80000 (31.5M) +-----------------------------------------+ - * | Free | - * 0x1C00000 (28M) +-----------------------------------------+ - * | IP35 PROM TEXT/DATA/BSS/stack | - * 0x1A00000 (26M) +-----------------------------------------+ - * | Routing temp. space | - * 0x1800000 (24M) +-----------------------------------------+ - * | Diagnostics temp. space | - * 0x1500000 (21M) +-----------------------------------------+ - * | Free | - * 0x1400000 (20M) +-----------------------------------------+ - * | IO7 PROM temporary copy | - * 0x1300000 (19M) +-----------------------------------------+ - * | | - * | Free | - * | (UNIX DATA starts above 0x1000000) | - * | | - * +-----------------------------------------+ - * | UNIX DEBUG Version | - * 0x0310000 (3.1M) +-----------------------------------------+ - * | SYMMON, loaded just below UNIX | - * | (For UNIX Debug only) | - * | | - * | | - * 0x006C000 (432K) +-----------------------------------------+ - * | SYMMON STACK [NUM_CPU_PER_NODE] | - * | (For UNIX Debug only) | - * 0x004C000 (304K) +-----------------------------------------+ - * | | - * | | - * | UNIX NON-DEBUG Version | - * 0x0040000 (256K) +-----------------------------------------+ - * - * - * The lower portion of the memory map contains information that is - * permanent and is used by the IP35PROM, IO7PROM and IRIX. - * - * 0x40000 (256K) +-----------------------------------------+ - * | | - * | KLCONFIG (64K) | - * | | - * 0x30000 (192K) +-----------------------------------------+ - * | | - * | PI Error Spools (64K) | - * | | - * 0x20000 (128K) +-----------------------------------------+ - * | | - * | Unused | - * | | - * 0x19000 (100K) +-----------------------------------------+ - * | Early cache Exception stack (CPU 3)| - * 0x18800 (98K) +-----------------------------------------+ - * | cache error eframe (CPU 3) | - * 0x18400 (97K) +-----------------------------------------+ - * | Exception Handlers (CPU 3) | - * 0x18000 (96K) +-----------------------------------------+ - * | | - * | Unused | - * | | - * 0x13c00 (79K) +-----------------------------------------+ - * | GPDA (8k) | - * 0x11c00 (71K) +-----------------------------------------+ - * | Early cache Exception stack (CPU 2)| - * 0x10800 (66k) +-----------------------------------------+ - * | cache error eframe (CPU 2) | - * 0x10400 (65K) +-----------------------------------------+ - * | Exception Handlers (CPU 2) | - * 0x10000 (64K) +-----------------------------------------+ - * | | - * | Unused | - * | | - * 0x0b400 (45K) +-----------------------------------------+ - * | GDA (1k) | - * 0x0b000 (44K) +-----------------------------------------+ - * | NMI Eframe areas (4) | - * 0x0a000 (40K) +-----------------------------------------+ - * | NMI Register save areas (4) | - * 0x09000 (36K) +-----------------------------------------+ - * | Early cache Exception stack (CPU 1)| - * 0x08800 (34K) +-----------------------------------------+ - * | cache error eframe (CPU 1) | - * 0x08400 (33K) +-----------------------------------------+ - * | Exception Handlers (CPU 1) | - * 0x08000 (32K) +-----------------------------------------+ - * | | - * | | - * | Unused | - * | | - * | | - * 0x04000 (16K) +-----------------------------------------+ - * | NMI Handler (Protected Page) | - * 0x03000 (12K) +-----------------------------------------+ - * | ARCS PVECTORS (master node only) | - * 0x02c00 (11K) +-----------------------------------------+ - * | ARCS TVECTORS (master node only) | - * 0x02800 (10K) +-----------------------------------------+ - * | LAUNCH [NUM_CPU] | - * 0x02400 (9K) +-----------------------------------------+ - * | Low memory directory (KLDIR) | - * 0x02000 (8K) +-----------------------------------------+ - * | ARCS SPB (1K) | - * 0x01000 (4K) +-----------------------------------------+ - * | Early cache Exception stack (CPU 0)| - * 0x00800 (2k) +-----------------------------------------+ - * | cache error eframe (CPU 0) | - * 0x00400 (1K) +-----------------------------------------+ - * | Exception Handlers (CPU 0) | - * 0x00000 (0K) +-----------------------------------------+ - */ - -/* - * NOTE: To change the kernel load address, you must update: - * - the appropriate elspec files in irix/kern/master.d - * - NODEBUGUNIX_ADDR in SN/SN1/addrs.h - * - IP27_FREEMEM_OFFSET below - * - KERNEL_START_OFFSET below (if supporting cells) - */ - - -/* - * This is defined here because IP27_SYMMON_STK_SIZE must be at least what - * we define here. Since it's set up in the prom. We can't redefine it later - * and expect more space to be allocated. The way to find out the true size - * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE - * for a particular node. - */ -#define SYMMON_STACK_SIZE 0x8000 - -#if defined (PROM) || defined (SABLE) - -/* - * These defines are prom version dependent. No code other than the IP35 - * prom should attempt to use these values. - */ -#define IP27_LAUNCH_OFFSET 0x2400 -#define IP27_LAUNCH_SIZE 0x400 -#define IP27_LAUNCH_COUNT 4 -#define IP27_LAUNCH_STRIDE 0x100 /* could be as small as 0x80 */ - -#define IP27_KLCONFIG_OFFSET 0x30000 -#define IP27_KLCONFIG_SIZE 0x10000 -#define IP27_KLCONFIG_COUNT 1 -#define IP27_KLCONFIG_STRIDE 0 - -#define IP27_NMI_OFFSET 0x3000 -#define IP27_NMI_SIZE 0x100 -#define IP27_NMI_COUNT 4 -#define IP27_NMI_STRIDE 0x40 - -#define IP27_PI_ERROR_OFFSET 0x20000 -#define IP27_PI_ERROR_SIZE 0x10000 -#define IP27_PI_ERROR_COUNT 1 -#define IP27_PI_ERROR_STRIDE 0 - -#define IP27_SYMMON_STK_OFFSET 0x4c000 -#define IP27_SYMMON_STK_SIZE 0x20000 -#define IP27_SYMMON_STK_COUNT 4 -/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */ -#define IP27_SYMMON_STK_STRIDE 0x8000 - -#define IP27_FREEMEM_OFFSET 0x40000 -#define IP27_FREEMEM_SIZE -1 -#define IP27_FREEMEM_COUNT 1 -#define IP27_FREEMEM_STRIDE 0 - -#endif /* PROM || SABLE*/ -/* - * There will be only one of these in a partition so the IO7 must set it up. - */ -#define IO6_GDA_OFFSET 0xb000 -#define IO6_GDA_SIZE 0x400 -#define IO6_GDA_COUNT 1 -#define IO6_GDA_STRIDE 0 - -/* - * save area of kernel nmi regs in the prom format - */ -#define IP27_NMI_KREGS_OFFSET 0x9000 -#define IP27_NMI_KREGS_CPU_SIZE 0x400 -/* - * save area of kernel nmi regs in eframe format - */ -#define IP27_NMI_EFRAME_OFFSET 0xa000 -#define IP27_NMI_EFRAME_SIZE 0x400 - -#define GPDA_OFFSET 0x11c00 - -#endif /* _ASM_SN_SN1_KLDIR_H */ diff --git a/include/asm-ia64/sn/sn1/leds.h b/include/asm-ia64/sn/sn1/leds.h deleted file mode 100644 index 88decf34c87f..000000000000 --- a/include/asm-ia64/sn/sn1/leds.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef _ASM_SN_SN1_LED_H -#define _ASM_SN_SN1_LED_H - -/* - * Copyright (C) 2000 Silicon Graphics, Inc - * Copyright (C) 2000 Jack Steiner (steiner@sgi.com) - */ - -#include <asm/smp.h> - -#define LED0 0xc0000b00100000c0LL /* ZZZ fixme */ - - - -#define LED_AP_START 0x01 /* AP processor started */ -#define LED_AP_IDLE 0x01 - -/* - * Basic macros for flashing the LEDS on an SGI, SN1. - */ - -extern __inline__ void -HUB_SET_LED(int val) -{ - long *ledp; - int eid; - - eid = hard_smp_processor_id() & 3; - ledp = (long*) (LED0 + (eid<<3)); - *ledp = val; -} - - -#endif /* _ASM_SN_SN1_LED_H */ - diff --git a/include/asm-ia64/sn/mem_refcnt.h b/include/asm-ia64/sn/sn1/mem_refcnt.h index e75986fdecfe..80acfffd4999 100644 --- a/include/asm-ia64/sn/mem_refcnt.h +++ b/include/asm-ia64/sn/sn1/mem_refcnt.h @@ -1,14 +1,13 @@ -/* $Id$ +/* * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_MEM_REFCNT_H -#define _ASM_SN_MEM_REFCNT_H +#ifndef _ASM_IA64_SN_SN1_MEM_REFCNT_H +#define _ASM_IA64_SN_SN1_MEM_REFCNT_H extern int mem_refcnt_attach(devfs_handle_t hub); extern int mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp); @@ -23,4 +22,4 @@ extern int mem_refcnt_ioctl(devfs_handle_t dev, int *rvalp); -#endif /* _ASM_SN_MEM_REFCNT_H */ +#endif /* _ASM_IA64_SN_SN1_MEM_REFCNT_H */ diff --git a/include/asm-ia64/sn/sn1/mmzone_sn1.h b/include/asm-ia64/sn/sn1/mmzone_sn1.h new file mode 100644 index 000000000000..769aa51f1040 --- /dev/null +++ b/include/asm-ia64/sn/sn1/mmzone_sn1.h @@ -0,0 +1,149 @@ +#ifndef _ASM_IA64_SN_MMZONE_SN1_H +#define _ASM_IA64_SN_MMZONE_SN1_H + +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2000-2002 Silicon Graphics, Inc. All rights reserved. + */ + +#include <linux/config.h> + + +/* + * SGI SN1 Arch defined values + * + * An SN1 physical address is broken down as follows: + * + * +-----------------------------------------+ + * | | | | node offset | + * | unused | AS | node |-------------------| + * | | | | cn | clump offset | + * +-----------------------------------------+ + * 6 4 4 4 3 3 3 3 2 0 + * 3 4 3 0 9 3 2 0 9 0 + * + * bits 63-44 Unused - must be zero + * bits 43-40 Address space ID. Cached memory has a value of 0. + * Chipset & IO addresses have non-zero values. + * bits 39-33 Node number. Note that some configurations do NOT + * have a node zero. + * bits 32-0 Node offset. + * + * The node offset can be further broken down as: + * bits 32-30 Clump (bank) number. + * bits 29-0 Clump (bank) offset. + * + * A node consists of up to 8 clumps (banks) of memory. A clump may be empty, or may be + * populated with a single contiguous block of memory starting at clump + * offset 0. The size of the block is (2**n) * 64MB, where 0<n<5. + * + * + * NOTE: This file exports symbols prefixed with "PLAT_". Symbols prefixed with + * "SN_" are intended for internal use only and should not be used in + * any platform independent code. + * + * This file is also responsible for exporting the following definitions: + * cnodeid_t Define a compact node id. + */ + +typedef signed short cnodeid_t; + +#define SN1_BANKS_PER_NODE 8 +#define SN1_NODE_SIZE (8UL*1024*1024*1024) /* 8 GB per node */ +#define SN1_BANK_SIZE (SN1_NODE_SIZE/SN1_BANKS_PER_NODE) +#define SN1_NODE_SHIFT 33 +#define SN1_NODE_MASK 0x7fUL +#define SN1_NODE_OFFSET_MASK (SN1_NODE_SIZE-1) +#define SN1_NODE_NUMBER(addr) (((unsigned long)(addr) >> SN1_NODE_SHIFT) & SN1_NODE_MASK) +#define SN1_NODE_CLUMP_NUMBER(addr) (((unsigned long)(addr) >>30) & 7) +#define SN1_NODE_OFFSET(addr) (((unsigned long)(addr)) & SN1_NODE_OFFSET_MASK) +#define SN1_KADDR(nasid, offset) (((unsigned long)(nasid)<<SN1_NODE_SHIFT) | (offset) | PAGE_OFFSET) + + +#define PLAT_MAX_NODE_NUMBER 128 /* Maximum node number +1 */ +#define PLAT_MAX_COMPACT_NODES 128 /* Maximum number of nodes in SSI */ + +#define PLAT_MAX_PHYS_MEMORY (1UL << 40) + + + +/* + * On the SN platforms, a clump is the same as a memory bank. + */ +#define PLAT_CLUMPS_PER_NODE SN1_BANKS_PER_NODE +#define PLAT_CLUMP_OFFSET(addr) ((unsigned long)(addr) & 0x3fffffffUL) +#define PLAT_CLUMPSIZE (SN1_NODE_SIZE/PLAT_CLUMPS_PER_NODE) +#define PLAT_MAXCLUMPS (PLAT_CLUMPS_PER_NODE*PLAT_MAX_COMPACT_NODES) + + + + +/* + * PLAT_VALID_MEM_KADDR returns a boolean to indicate if a kaddr is potentially a + * valid cacheable identity mapped RAM memory address. + * Note that the RAM may or may not actually be present!! + */ +#define SN1_VALID_KERN_ADDR_MASK 0xffffff0000000000UL +#define SN1_VALID_KERN_ADDR_VALUE 0xe000000000000000UL +#define PLAT_VALID_MEM_KADDR(kaddr) (((unsigned long)(kaddr) & SN1_VALID_KERN_ADDR_MASK) == SN1_VALID_KERN_ADDR_VALUE) + + + +/* + * Memory is conceptually divided into chunks. A chunk is either + * completely present, or else the kernel assumes it is completely + * absent. Each node consists of a number of possibly discontiguous chunks. + */ +#define SN1_CHUNKSHIFT 26 /* 64 MB */ +#define SN1_CHUNKSIZE (1UL << SN1_CHUNKSHIFT) +#define PLAT_CHUNKNUM(addr) (((addr) & (PLAT_MAX_PHYS_MEMORY-1)) >> SN1_CHUNKSHIFT) + + +/* + * Given a kaddr, find the nid (compact nodeid) + */ +#ifdef CONFIG_IA64_SGI_SN_DEBUG +#define DISCONBUG(kaddr) panic("DISCONTIG BUG: line %d, %s. kaddr 0x%lx", \ + __LINE__, __FILE__, (long)(kaddr)) + +#define KVADDR_TO_NID(kaddr) ({long _ktn=(long)(kaddr); \ + kern_addr_valid(_ktn) ? \ + local_node_data->physical_node_map[SN1_NODE_NUMBER(_ktn)] :\ + (DISCONBUG(_ktn), 0UL);}) +#else +#define KVADDR_TO_NID(kaddr) (local_node_data->physical_node_map[SN1_NODE_NUMBER(kaddr)]) +#endif + + + +/* + * Given a kaddr, find the index into the clump_mem_map_base array of the page struct entry + * for the first page of the clump. + */ +#define PLAT_CLUMP_MEM_MAP_INDEX(kaddr) ({long _kmmi=(long)(kaddr); \ + KVADDR_TO_NID(_kmmi) * PLAT_CLUMPS_PER_NODE + \ + SN1_NODE_CLUMP_NUMBER(_kmmi);}) + + +/* + * Calculate a "goal" value to be passed to __alloc_bootmem_node for allocating structures on + * nodes so that they dont alias to the same line in the cache as the previous allocated structure. + * This macro takes an address of the end of previous allocation, rounds it to a page boundary & + * changes the node number. + */ +#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) SN1_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnodeid]), \ + (SN1_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT) + + + + +/* + * Convert a proximity domain number (from the ACPI tables) into a physical node number. + */ + +#define PLAT_PXM_TO_PHYS_NODE_NUMBER(pxm) (pxm) + +#endif /* _ASM_IA64_SN_MMZONE_SN1_H */ diff --git a/include/asm-ia64/sn/sn1/promlog.h b/include/asm-ia64/sn/sn1/promlog.h deleted file mode 100644 index 4c4b9f2e91cb..000000000000 --- a/include/asm-ia64/sn/sn1/promlog.h +++ /dev/null @@ -1,85 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam - */ - -#ifndef _ASM_SN_SN1_PROMLOG_H -#define _ASM_SN_SN1_PROMLOG_H - -#include <asm/sn/fprom.h> - -#define PROMLOG_MAGIC 0x504c4f49 -#define PROMLOG_VERSION 1 - -#define PROMLOG_OFFSET_MAGIC 0x10 -#define PROMLOG_OFFSET_VERSION 0x14 -#define PROMLOG_OFFSET_SEQUENCE 0x18 -#define PROMLOG_OFFSET_ENTRY0 0x100 - -#define PROMLOG_ERROR_NONE 0 -#define PROMLOG_ERROR_PROM -1 -#define PROMLOG_ERROR_MAGIC -2 -#define PROMLOG_ERROR_CORRUPT -3 -#define PROMLOG_ERROR_BOL -4 -#define PROMLOG_ERROR_EOL -5 -#define PROMLOG_ERROR_POS -6 -#define PROMLOG_ERROR_REPLACE -7 -#define PROMLOG_ERROR_COMPACT -8 -#define PROMLOG_ERROR_FULL -9 -#define PROMLOG_ERROR_ARG -10 -#define PROMLOG_ERROR_UNUSED -11 - -#define PROMLOG_TYPE_UNUSED 0xf -#define PROMLOG_TYPE_LOG 3 -#define PROMLOG_TYPE_LIST 2 -#define PROMLOG_TYPE_VAR 1 -#define PROMLOG_TYPE_DELETED 0 - -#define PROMLOG_TYPE_ANY 98 -#define PROMLOG_TYPE_INVALID 99 - -#define PROMLOG_KEY_MAX 14 -#define PROMLOG_VALUE_MAX 47 -#define PROMLOG_CPU_MAX 4 - -typedef struct promlog_header_s { - unsigned int unused[4]; - unsigned int magic; - unsigned int version; - unsigned int sequence; -} promlog_header_t; - -typedef unsigned int promlog_pos_t; - -typedef struct promlog_ent_s { /* PROM individual entry */ - uint type : 4; - uint cpu_num : 4; - char key[PROMLOG_KEY_MAX + 1]; - - char value[PROMLOG_VALUE_MAX + 1]; - -} promlog_ent_t; - -typedef struct promlog_s { /* Activation handle */ - fprom_t f; - int sector_base; - int cpu_num; - - int active; /* Active sector, 0 or 1 */ - - promlog_pos_t log_start; - promlog_pos_t log_end; - - promlog_pos_t alt_start; - promlog_pos_t alt_end; - - promlog_pos_t pos; - promlog_ent_t ent; -} promlog_t; - -#endif /* _ASM_SN_SN1_PROMLOG_H */ diff --git a/include/asm-ia64/sn/sn1/router.h b/include/asm-ia64/sn/sn1/router.h deleted file mode 100644 index 597d40f13c0f..000000000000 --- a/include/asm-ia64/sn/sn1/router.h +++ /dev/null @@ -1,670 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam - */ - -#ifndef _ASM_SN_SN1_ROUTER_H -#define _ASM_SN_SN1_ROUTER_H - -/* - * Router Register definitions - * - * Macro argument _L always stands for a link number (1 to 8, inclusive). - */ - -#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) - -#include <asm/sn/vector.h> -#include <asm/sn/slotnum.h> -#include <asm/sn/arch.h> - -typedef uint64_t router_reg_t; - -#define MAX_ROUTERS 64 - -#define MAX_ROUTER_PATH 80 - -#define ROUTER_REG_CAST (volatile router_reg_t *) -#define PS_UINT_CAST (__psunsigned_t) -#define UINT64_CAST (uint64_t) -typedef signed char port_no_t; /* Type for router port number */ - -#elif _LANGUAGE_ASSEMBLY - -#define ROUTERREG_CAST -#define PS_UINT_CAST -#define UINT64_CAST - -#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */ - -#define MAX_ROUTER_PORTS (8) /* Max. number of ports on a router */ - -#define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1) /* for 0 based references */ - -#define PORT_INVALID (-1) /* Invalid port number */ - -#define IS_META(_rp) ((_rp)->flags & PCFG_ROUTER_META) - -#define IS_REPEATER(_rp)((_rp)->flags & PCFG_ROUTER_REPEATER) - -/* - * RR_TURN makes a given number of clockwise turns (0 to 7) from an inport - * port to generate an output port. - * - * RR_DISTANCE returns the number of turns necessary (0 to 7) to go from - * an input port (_L1 = 1 to 8) to an output port ( _L2 = 1 to 8). - * - * These are written to work on unsigned data. - */ - -#define RR_TURN(_L, count) ((_L) + (count) > MAX_ROUTER_PORTS ? \ - (_L) + (count) - MAX_ROUTER_PORTS : \ - (_L) + (count)) - -#define RR_DISTANCE(_LS, _LD) ((_LD) >= (_LS) ? \ - (_LD) - (_LS) : \ - (_LD) + MAX_ROUTER_PORTS - (_LS)) - -/* Router register addresses */ - -#define RR_STATUS_REV_ID 0x00000 /* Status register and Revision ID */ -#define RR_PORT_RESET 0x00008 /* Multiple port reset */ -#define RR_PROT_CONF 0x00010 /* Inter-partition protection conf. */ -#define RR_GLOBAL_PORT_DEF 0x00018 /* Global Port definitions */ -#define RR_GLOBAL_PARMS0 0x00020 /* Parameters shared by all 8 ports */ -#define RR_GLOBAL_PARMS1 0x00028 /* Parameters shared by all 8 ports */ -#define RR_DIAG_PARMS 0x00030 /* Parameters for diag. testing */ -#define RR_DEBUG_ADDR 0x00038 /* Debug address select - debug port*/ -#define RR_LB_TO_L2 0x00040 /* Local Block to L2 cntrl intf reg */ -#define RR_L2_TO_LB 0x00048 /* L2 cntrl intf to Local Block reg */ -#define RR_JBUS_CONTROL 0x00050 /* read/write timing for JBUS intf */ - -#define RR_SCRATCH_REG0 0x00100 /* Scratch 0 is 64 bits */ -#define RR_SCRATCH_REG1 0x00108 /* Scratch 1 is 64 bits */ -#define RR_SCRATCH_REG2 0x00110 /* Scratch 2 is 64 bits */ -#define RR_SCRATCH_REG3 0x00118 /* Scratch 3 is 1 bit */ -#define RR_SCRATCH_REG4 0x00120 /* Scratch 4 is 1 bit */ - -#define RR_JBUS0(_D) (((_D) & 0x7) << 3 | 0x00200) /* JBUS0 addresses */ -#define RR_JBUS1(_D) (((_D) & 0x7) << 3 | 0x00240) /* JBUS1 addresses */ - -#define RR_SCRATCH_REG0_WZ 0x00500 /* Scratch 0 is 64 bits */ -#define RR_SCRATCH_REG1_WZ 0x00508 /* Scratch 1 is 64 bits */ -#define RR_SCRATCH_REG2_WZ 0x00510 /* Scratch 2 is 64 bits */ -#define RR_SCRATCH_REG3_SZ 0x00518 /* Scratch 3 is 1 bit */ -#define RR_SCRATCH_REG4_SZ 0x00520 /* Scratch 4 is 1 bit */ - -#define RR_VECTOR_HW_BAR(context) (0x08000 | (context)<<3) /* barrier config registers */ -/* Port-specific registers (_L is the link number from 1 to 8) */ - -#define RR_PORT_PARMS(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0000) /* LLP parameters */ -#define RR_STATUS_ERROR(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0008) /* Port-related errs */ -#define RR_CHANNEL_TEST(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0010) /* Port LLP chan test */ -#define RR_RESET_MASK(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0018) /* Remote reset mask */ -#define RR_HISTOGRAM0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0020) /* Port usage histgrm */ -#define RR_HISTOGRAM1(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0028) /* Port usage histgrm */ -#define RR_HISTOGRAM0_WC(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0030) /* Port usage histgrm */ -#define RR_HISTOGRAM1_WC(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0038) /* Port usage histgrm */ -#define RR_ERROR_CLEAR(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0088) /* Read/clear errors */ -#define RR_GLOBAL_TABLE0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0100) /* starting address of global table for this port */ -#define RR_GLOBAL_TABLE(_L, _x) (RR_GLOBAL_TABLE0(_L) + ((_x) << 3)) -#define RR_LOCAL_TABLE0(_L) (((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0200) /* starting address of local table for this port */ -#define RR_LOCAL_TABLE(_L, _x) (RR_LOCAL_TABLE0(_L) + ((_x) << 3)) - -#define RR_META_ENTRIES 16 - -#define RR_LOCAL_ENTRIES 128 - -/* - * RR_STATUS_REV_ID mask and shift definitions - */ - -#define RSRI_INPORT_SHFT 52 -#define RSRI_INPORT_MASK (UINT64_CAST 0xf << 52) -#define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L)) -#define RSRI_LINKWORKING(_L) (UINT64_CAST 1 << (35 + 2 * (_L))) -#define RSRI_LINKRESETFAIL(_L) (UINT64_CAST 1 << (34 + 2 * (_L))) -#define RSRI_LSTAT_SHFT(_L) (34 + 2 * (_L)) -#define RSRI_LSTAT_MASK(_L) (UINT64_CAST 0x3 << 34 + 2 * (_L)) -#define RSRI_LOCALSBERROR (UINT64_CAST 1 << 35) -#define RSRI_LOCALSTUCK (UINT64_CAST 1 << 34) -#define RSRI_LOCALBADVEC (UINT64_CAST 1 << 33) -#define RSRI_LOCALTAILERR (UINT64_CAST 1 << 32) -#define RSRI_LOCAL_SHFT 32 -#define RSRI_LOCAL_MASK (UINT64_CAST 0xf << 32) -#define RSRI_CHIPREV_SHFT 28 -#define RSRI_CHIPREV_MASK (UINT64_CAST 0xf << 28) -#define RSRI_CHIPID_SHFT 12 -#define RSRI_CHIPID_MASK (UINT64_CAST 0xffff << 12) -#define RSRI_MFGID_SHFT 1 -#define RSRI_MFGID_MASK (UINT64_CAST 0x7ff << 1) - -#define RSRI_LSTAT_WENTDOWN 0 -#define RSRI_LSTAT_RESETFAIL 1 -#define RSRI_LSTAT_LINKUP 2 -#define RSRI_LSTAT_NOTUSED 3 - -/* - * RR_PORT_RESET mask definitions - */ - -#define RPRESET_WARM (UINT64_CAST 1 << 9) -#define RPRESET_LINK(_L) (UINT64_CAST 1 << (_L)) -#define RPRESET_LOCAL (UINT64_CAST 1) - -/* - * RR_PROT_CONF mask and shift definitions - */ - -#define RPCONF_DIRCMPDIS_SHFT 13 -#define RPCONF_DIRCMPDIS_MASK (UINT64_CAST 1 << 13) -#define RPCONF_FORCELOCAL (UINT64_CAST 1 << 12) -#define RPCONF_FLOCAL_SHFT 12 -#define RPCONF_METAID_SHFT 8 -#define RPCONF_METAID_MASK (UINT64_CAST 0xf << 8) -#define RPCONF_RESETOK(_L) (UINT64_CAST 1 << ((_L) - 1)) - -/* - * RR_GLOBAL_PORT_DEF mask and shift definitions - */ - -#define RGPD_MGLBLNHBR_ID_SHFT 12 /* -global neighbor ID */ -#define RGPD_MGLBLNHBR_ID_MASK (UINT64_CAST 0xf << 12) -#define RGPD_MGLBLNHBR_VLD_SHFT 11 /* -global neighbor Valid */ -#define RGPD_MGLBLNHBR_VLD_MASK (UINT64_CAST 0x1 << 11) -#define RGPD_MGLBLPORT_SHFT 8 /* -global neighbor Port */ -#define RGPD_MGLBLPORT_MASK (UINT64_CAST 0x7 << 8) -#define RGPD_PGLBLNHBR_ID_SHFT 4 /* +global neighbor ID */ -#define RGPD_PGLBLNHBR_ID_MASK (UINT64_CAST 0xf << 4) -#define RGPD_PGLBLNHBR_VLD_SHFT 3 /* +global neighbor Valid */ -#define RGPD_PGLBLNHBR_VLD_MASK (UINT64_CAST 0x1 << 3) -#define RGPD_PGLBLPORT_SHFT 0 /* +global neighbor Port */ -#define RGPD_PGLBLPORT_MASK (UINT64_CAST 0x7 << 0) - -#define GLBL_PARMS_REGS 2 /* Two Global Parms registers */ - -/* - * RR_GLOBAL_PARMS0 mask and shift definitions - */ - -#define RGPARM0_ARB_VALUE_SHFT 54 /* Local Block Arbitration State */ -#define RGPARM0_ARB_VALUE_MASK (UINT64_CAST 0x7 << 54) -#define RGPARM0_ROTATEARB_SHFT 53 /* Rotate Local Block Arbitration */ -#define RGPARM0_ROTATEARB_MASK (UINT64_CAST 0x1 << 53) -#define RGPARM0_FAIREN_SHFT 52 /* Fairness logic Enable */ -#define RGPARM0_FAIREN_MASK (UINT64_CAST 0x1 << 52) -#define RGPARM0_LOCGNTTO_SHFT 40 /* Local grant timeout */ -#define RGPARM0_LOCGNTTO_MASK (UINT64_CAST 0xfff << 40) -#define RGPARM0_DATELINE_SHFT 38 /* Dateline crossing router */ -#define RGPARM0_DATELINE_MASK (UINT64_CAST 0x1 << 38) -#define RGPARM0_MAXRETRY_SHFT 28 /* Max retry count */ -#define RGPARM0_MAXRETRY_MASK (UINT64_CAST 0x3ff << 28) -#define RGPARM0_URGWRAP_SHFT 20 /* Urgent wrap */ -#define RGPARM0_URGWRAP_MASK (UINT64_CAST 0xff << 20) -#define RGPARM0_DEADLKTO_SHFT 16 /* Deadlock timeout */ -#define RGPARM0_DEADLKTO_MASK (UINT64_CAST 0xf << 16) -#define RGPARM0_URGVAL_SHFT 12 /* Urgent value */ -#define RGPARM0_URGVAL_MASK (UINT64_CAST 0xf << 12) -#define RGPARM0_VCHSELEN_SHFT 11 /* VCH_SEL_EN */ -#define RGPARM0_VCHSELEN_MASK (UINT64_CAST 0x1 << 11) -#define RGPARM0_LOCURGTO_SHFT 9 /* Local urgent timeout */ -#define RGPARM0_LOCURGTO_MASK (UINT64_CAST 0x3 << 9) -#define RGPARM0_TAILVAL_SHFT 5 /* Tail value */ -#define RGPARM0_TAILVAL_MASK (UINT64_CAST 0xf << 5) -#define RGPARM0_CLOCK_SHFT 1 /* Global clock select */ -#define RGPARM0_CLOCK_MASK (UINT64_CAST 0xf << 1) -#define RGPARM0_BYPEN_SHFT 0 -#define RGPARM0_BYPEN_MASK (UINT64_CAST 1) /* Bypass enable */ - -/* - * RR_GLOBAL_PARMS1 shift and mask definitions - */ - -#define RGPARM1_TTOWRAP_SHFT 12 /* Tail timeout wrap */ -#define RGPARM1_TTOWRAP_MASK (UINT64_CAST 0xfffff << 12) -#define RGPARM1_AGERATE_SHFT 8 /* Age rate */ -#define RGPARM1_AGERATE_MASK (UINT64_CAST 0xf << 8) -#define RGPARM1_JSWSTAT_SHFT 0 /* JTAG Sw Register bits */ -#define RGPARM1_JSWSTAT_MASK (UINT64_CAST 0xff << 0) - -/* - * RR_DIAG_PARMS mask and shift definitions - */ - -#define RDPARM_ABSHISTOGRAM (UINT64_CAST 1 << 17) /* Absolute histgrm */ -#define RDPARM_DEADLOCKRESET (UINT64_CAST 1 << 16) /* Reset on deadlck */ -#define RDPARM_DISABLE(_L) (UINT64_CAST 1 << ((_L) + 7)) -#define RDPARM_SENDERROR(_L) (UINT64_CAST 1 << ((_L) - 1)) - -/* - * RR_DEBUG_ADDR mask and shift definitions - */ - -#define RDA_DATA_SHFT 10 /* Observed debug data */ -#define RDA_DATA_MASK (UINT64_CAST 0xffff << 10) -#define RDA_ADDR_SHFT 0 /* debug address for data */ -#define RDA_ADDR_MASK (UINT64_CAST 0x3ff << 0) - -/* - * RR_LB_TO_L2 mask and shift definitions - */ - -#define RLBTOL2_DATA_VLD_SHFT 32 /* data is valid for JTAG controller */ -#define RLBTOL2_DATA_VLD_MASK (UINT64_CAST 0x1 << 32) -#define RLBTOL2_DATA_SHFT 0 /* data bits for JTAG controller */ -#define RLBTOL2_DATA_MASK (UINT64_CAST 0xffffffff) - -/* - * RR_L2_TO_LB mask and shift definitions - */ - -#define RL2TOLB_DATA_VLD_SHFT 33 /* data is valid from JTAG controller */ -#define RL2TOLB_DATA_VLD_MASK (UINT64_CAST 0x1 << 33) -#define RL2TOLB_PARITY_SHFT 32 /* sw implemented parity for data */ -#define RL2TOLB_PARITY_MASK (UINT64_CAST 0x1 << 32) -#define RL2TOLB_DATA_SHFT 0 /* data bits from JTAG controller */ -#define RL2TOLB_DATA_MASK (UINT64_CAST 0xffffffff) - -/* - * RR_JBUS_CONTROL mask and shift definitions - */ - -#define RJC_POS_BITS_SHFT 20 /* Router position bits */ -#define RJC_POS_BITS_MASK (UINT64_CAST 0xf << 20) -#define RJC_RD_DATA_STROBE_SHFT 16 /* count when read data is strobed in */ -#define RJC_RD_DATA_STROBE_MASK (UINT64_CAST 0xf << 16) -#define RJC_WE_OE_HOLD_SHFT 8 /* time OE or WE is held */ -#define RJC_WE_OE_HOLD_MASK (UINT64_CAST 0xff << 8) -#define RJC_ADDR_SET_HLD_SHFT 0 /* time address driven around OE/WE */ -#define RJC_ADDR_SET_HLD_MASK (UINT64_CAST 0xff) - -/* - * RR_SCRATCH_REGx mask and shift definitions - * note: these fields represent a software convention, and are not - * understood/interpreted by the hardware. - */ - -#define RSCR0_BOOTED_SHFT 63 -#define RSCR0_BOOTED_MASK (UINT64_CAST 0x1 << RSCR0_BOOTED_SHFT) -#define RSCR0_LOCALID_SHFT 56 -#define RSCR0_LOCALID_MASK (UINT64_CAST 0x7f << RSCR0_LOCALID_SHFT) -#define RSCR0_UNUSED_SHFT 48 -#define RSCR0_UNUSED_MASK (UINT64_CAST 0xff << RSCR0_UNUSED_SHFT) -#define RSCR0_NIC_SHFT 0 -#define RSCR0_NIC_MASK (UINT64_CAST 0xffffffffffff) - -#define RSCR1_MODID_SHFT 0 -#define RSCR1_MODID_MASK (UINT64_CAST 0xffff) - -/* - * RR_VECTOR_HW_BAR mask and shift definitions - */ - -#define BAR_TX_SHFT 27 /* Barrier in trans(m)it when read */ -#define BAR_TX_MASK (UINT64_CAST 1 << BAR_TX_SHFT) -#define BAR_VLD_SHFT 26 /* Valid Configuration */ -#define BAR_VLD_MASK (UINT64_CAST 1 << BAR_VLD_SHFT) -#define BAR_SEQ_SHFT 24 /* Sequence number */ -#define BAR_SEQ_MASK (UINT64_CAST 3 << BAR_SEQ_SHFT) -#define BAR_LEAFSTATE_SHFT 18 /* Leaf State */ -#define BAR_LEAFSTATE_MASK (UINT64_CAST 0x3f << BAR_LEAFSTATE_SHFT) -#define BAR_PARENT_SHFT 14 /* Parent Port */ -#define BAR_PARENT_MASK (UINT64_CAST 0xf << BAR_PARENT_SHFT) -#define BAR_CHILDREN_SHFT 6 /* Child Select port bits */ -#define BAR_CHILDREN_MASK (UINT64_CAST 0xff << BAR_CHILDREN_SHFT) -#define BAR_LEAFCOUNT_SHFT 0 /* Leaf Count to trigger parent */ -#define BAR_LEAFCOUNT_MASK (UINT64_CAST 0x3f) - -/* - * RR_PORT_PARMS(_L) mask and shift definitions - */ - -#define RPPARM_MIPRESETEN_SHFT 29 /* Message In Progress reset enable */ -#define RPPARM_MIPRESETEN_MASK (UINT64_CAST 0x1 << 29) -#define RPPARM_UBAREN_SHFT 28 /* Enable user barrier requests */ -#define RPPARM_UBAREN_MASK (UINT64_CAST 0x1 << 28) -#define RPPARM_OUTPDTO_SHFT 24 /* Output Port Deadlock TO value */ -#define RPPARM_OUTPDTO_MASK (UINT64_CAST 0xf << 24) -#define RPPARM_PORTMATE_SHFT 21 /* Port Mate for the port */ -#define RPPARM_PORTMATE_MASK (UINT64_CAST 0x7 << 21) -#define RPPARM_HISTEN_SHFT 20 /* Histogram counter enable */ -#define RPPARM_HISTEN_MASK (UINT64_CAST 0x1 << 20) -#define RPPARM_HISTSEL_SHFT 18 -#define RPPARM_HISTSEL_MASK (UINT64_CAST 0x3 << 18) -#define RPPARM_DAMQHS_SHFT 16 -#define RPPARM_DAMQHS_MASK (UINT64_CAST 0x3 << 16) -#define RPPARM_NULLTO_SHFT 10 -#define RPPARM_NULLTO_MASK (UINT64_CAST 0x3f << 10) -#define RPPARM_MAXBURST_SHFT 0 -#define RPPARM_MAXBURST_MASK (UINT64_CAST 0x3ff) - -/* - * NOTE: Normally the kernel tracks only UTILIZATION statistics. - * The other 2 should not be used, except during any experimentation - * with the router. - */ -#define RPPARM_HISTSEL_AGE 0 /* Histogram age characterization. */ -#define RPPARM_HISTSEL_UTIL 1 /* Histogram link utilization */ -#define RPPARM_HISTSEL_DAMQ 2 /* Histogram DAMQ characterization. */ - -/* - * RR_STATUS_ERROR(_L) and RR_ERROR_CLEAR(_L) mask and shift definitions - */ -#define RSERR_POWERNOK (UINT64_CAST 1 << 38) -#define RSERR_PORT_DEADLOCK (UINT64_CAST 1 << 37) -#define RSERR_WARMRESET (UINT64_CAST 1 << 36) -#define RSERR_LINKRESET (UINT64_CAST 1 << 35) -#define RSERR_RETRYTIMEOUT (UINT64_CAST 1 << 34) -#define RSERR_FIFOOVERFLOW (UINT64_CAST 1 << 33) -#define RSERR_ILLEGALPORT (UINT64_CAST 1 << 32) -#define RSERR_DEADLOCKTO_SHFT 28 -#define RSERR_DEADLOCKTO_MASK (UINT64_CAST 0xf << 28) -#define RSERR_RECVTAILTO_SHFT 24 -#define RSERR_RECVTAILTO_MASK (UINT64_CAST 0xf << 24) -#define RSERR_RETRYCNT_SHFT 16 -#define RSERR_RETRYCNT_MASK (UINT64_CAST 0xff << 16) -#define RSERR_CBERRCNT_SHFT 8 -#define RSERR_CBERRCNT_MASK (UINT64_CAST 0xff << 8) -#define RSERR_SNERRCNT_SHFT 0 -#define RSERR_SNERRCNT_MASK (UINT64_CAST 0xff << 0) - - -#define PORT_STATUS_UP (1 << 0) /* Router link up */ -#define PORT_STATUS_FENCE (1 << 1) /* Router link fenced */ -#define PORT_STATUS_RESETFAIL (1 << 2) /* Router link didnot - * come out of reset */ -#define PORT_STATUS_DISCFAIL (1 << 3) /* Router link failed after - * out of reset but before - * router tables were - * programmed - */ -#define PORT_STATUS_KERNFAIL (1 << 4) /* Router link failed - * after reset and the - * router tables were - * programmed - */ -#define PORT_STATUS_UNDEF (1 << 5) /* Unable to pinpoint - * why the router link - * went down - */ -#define PROBE_RESULT_BAD (-1) /* Set if any of the router - * links failed after reset - */ -#define PROBE_RESULT_GOOD (0) /* Set if all the router links - * which came out of reset - * are up - */ - -/* Should be enough for 256 CPUs */ -#define MAX_RTR_BREADTH 64 /* Max # of routers possible */ - -/* Get the require set of bits in a var. corr to a sequence of bits */ -#define GET_FIELD(var, fname) \ - ((var) >> fname##_SHFT & fname##_MASK >> fname##_SHFT) -/* Set the require set of bits in a var. corr to a sequence of bits */ -#define SET_FIELD(var, fname, fval) \ - ((var) = (var) & ~fname##_MASK | (uint64_t) (fval) << fname##_SHFT) - - -#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) - -typedef struct router_map_ent_s { - uint64_t nic; - moduleid_t module; - slotid_t slot; -} router_map_ent_t; - -struct rr_status_error_fmt { - uint64_t rserr_unused : 30, - rserr_fifooverflow : 1, - rserr_illegalport : 1, - rserr_deadlockto : 4, - rserr_recvtailto : 4, - rserr_retrycnt : 8, - rserr_cberrcnt : 8, - rserr_snerrcnt : 8; -}; - -/* - * This type is used to store "absolute" counts of router events - */ -typedef int router_count_t; - -/* All utilizations are on a scale from 0 - 1023. */ -#define RP_BYPASS_UTIL 0 -#define RP_RCV_UTIL 1 -#define RP_SEND_UTIL 2 -#define RP_TOTAL_PKTS 3 /* Free running clock/packet counter */ - -#define RP_NUM_UTILS 3 - -#define RP_HIST_REGS 2 -#define RP_NUM_BUCKETS 4 -#define RP_HIST_TYPES 3 - -#define RP_AGE0 0 -#define RP_AGE1 1 -#define RP_AGE2 2 -#define RP_AGE3 3 - - -#define RR_UTIL_SCALE 1024 - -/* - * Router port-oriented information - */ -typedef struct router_port_info_s { - router_reg_t rp_histograms[RP_HIST_REGS];/* Port usage info */ - router_reg_t rp_port_error; /* Port error info */ - router_count_t rp_retry_errors; /* Total retry errors */ - router_count_t rp_sn_errors; /* Total sn errors */ - router_count_t rp_cb_errors; /* Total cb errors */ - int rp_overflows; /* Total count overflows */ - int rp_excess_err; /* Port has excessive errors */ - ushort rp_util[RP_NUM_BUCKETS];/* Port utilization */ -} router_port_info_t; - -#define ROUTER_INFO_VERSION 7 - -struct lboard_s; - -/* - * Router information - */ -typedef struct router_info_s { - char ri_version; /* structure version */ - cnodeid_t ri_cnode; /* cnode of its legal guardian hub */ - nasid_t ri_nasid; /* Nasid of same */ - char ri_ledcache; /* Last LED bitmap */ - char ri_leds; /* Current LED bitmap */ - char ri_portmask; /* Active port bitmap */ - router_reg_t ri_stat_rev_id; /* Status rev ID value */ - net_vec_t ri_vector; /* vector from guardian to router */ - int ri_writeid; /* router's vector write ID */ - int64_t ri_timebase; /* Time of first sample */ - int64_t ri_timestamp; /* Time of last sample */ - router_port_info_t ri_port[MAX_ROUTER_PORTS]; /* per port info */ - moduleid_t ri_module; /* Which module are we in? */ - slotid_t ri_slotnum; /* Which slot are we in? */ - router_reg_t ri_glbl_parms[GLBL_PARMS_REGS]; - /* Global parms0&1 register contents*/ - devfs_handle_t ri_vertex; /* hardware graph vertex */ - router_reg_t ri_prot_conf; /* protection config. register */ - int64_t ri_per_minute; /* Ticks per minute */ - - /* - * Everything below here is for kernel use only and may change at - * at any time with or without a change in teh revision number - * - * Any pointers or things that come and go with DEBUG must go at - * the bottom of the structure, below the user stuff. - */ - char ri_hist_type; /* histogram type */ - devfs_handle_t ri_guardian; /* guardian node for the router */ - int64_t ri_last_print; /* When did we last print */ - char ri_print; /* Should we print */ - char ri_just_blink; /* Should we blink the LEDs */ - -#ifdef DEBUG - int64_t ri_deltatime; /* Time it took to sample */ -#endif - spinlock_t ri_lock; /* Lock for access to router info */ - net_vec_t *ri_vecarray; /* Pointer to array of vectors */ - struct lboard_s *ri_brd; /* Pointer to board structure */ - char * ri_name; /* This board's hwg path */ - unsigned char ri_port_maint[MAX_ROUTER_PORTS]; /* should we send a - message to availmon */ -} router_info_t; - - -/* Router info location specifiers */ - -#define RIP_PROMLOG 2 /* Router info in promlog */ -#define RIP_CONSOLE 4 /* Router info on console */ - -#define ROUTER_INFO_PRINT(_rip,_where) (_rip->ri_print |= _where) - /* Set the field used to check if a - * router info can be printed - */ -#define IS_ROUTER_INFO_PRINTED(_rip,_where) \ - (_rip->ri_print & _where) - /* Was the router info printed to - * the given location (_where) ? - * Mainly used to prevent duplicate - * router error states. - */ -#define ROUTER_INFO_LOCK(_rip,_s) _s = mutex_spinlock(&(_rip->ri_lock)) - /* Take the lock on router info - * to gain exclusive access - */ -#define ROUTER_INFO_UNLOCK(_rip,_s) mutex_spinunlock(&(_rip->ri_lock),_s) - /* Release the lock on router info */ -/* - * Router info hanging in the nodepda - */ -typedef struct nodepda_router_info_s { - devfs_handle_t router_vhdl; /* vertex handle of the router */ - short router_port; /* port thru which we entered */ - short router_portmask; - moduleid_t router_module; /* module in which router is there */ - slotid_t router_slot; /* router slot */ - unsigned char router_type; /* kind of router */ - net_vec_t router_vector; /* vector from the guardian node */ - - router_info_t *router_infop; /* info hanging off the hwg vertex */ - struct nodepda_router_info_s *router_next; - /* pointer to next element */ -} nodepda_router_info_t; - -#define ROUTER_NAME_SIZE 20 /* Max size of a router name */ - -#define NORMAL_ROUTER_NAME "normal_router" -#define NULL_ROUTER_NAME "null_router" -#define META_ROUTER_NAME "meta_router" -#define REPEATER_ROUTER_NAME "repeater_router" -#define UNKNOWN_ROUTER_NAME "unknown_router" - -/* The following definitions are needed by the router traversing - * code either using the hardware graph or using vector operations. - */ -/* Structure of the router queue element */ -typedef struct router_elt_s { - union { - /* queue element structure during router probing */ - struct { - /* number-in-a-can (unique) for the router */ - nic_t nic; - /* vector route from the master hub to - * this router. - */ - net_vec_t vec; - /* port status */ - uint64_t status; - char port_status[MAX_ROUTER_PORTS + 1]; - } r_elt; - /* queue element structure during router guardian - * assignment - */ - struct { - /* vertex handle for the router */ - devfs_handle_t vhdl; - /* guardian for this router */ - devfs_handle_t guard; - /* vector router from the guardian to the router */ - net_vec_t vec; - } k_elt; - } u; - /* easy to use port status interpretation */ -} router_elt_t; - -/* structure of the router queue */ - -typedef struct router_queue_s { - char head; /* Point where a queue element is inserted */ - char tail; /* Point where a queue element is removed */ - int type; - router_elt_t array[MAX_RTR_BREADTH]; - /* Entries for queue elements */ -} router_queue_t; - - -#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */ - -/* - * RR_HISTOGRAM(_L) mask and shift definitions - * There are two 64 bit histogram registers, so the following macros take - * into account dealing with an array of 4 32 bit values indexed by _x - */ - -#define RHIST_BUCKET_SHFT(_x) (32 * ((_x) & 0x1)) -#define RHIST_BUCKET_MASK(_x) (UINT64_CAST 0xffffffff << RHIST_BUCKET_SHFT((_x) & 0x1)) -#define RHIST_GET_BUCKET(_x, _reg) \ - ((RHIST_BUCKET_MASK(_x) & ((_reg)[(_x) >> 1])) >> RHIST_BUCKET_SHFT(_x)) - -/* - * RR_RESET_MASK(_L) mask and shift definitions - */ - -#define RRM_RESETOK(_L) (UINT64_CAST 1 << ((_L) - 1)) -#define RRM_RESETOK_ALL ALL_PORTS - -/* - * RR_META_TABLE(_x) and RR_LOCAL_TABLE(_x) mask and shift definitions - */ - -#define RTABLE_SHFT(_L) (4 * ((_L) - 1)) -#define RTABLE_MASK(_L) (UINT64_CAST 0x7 << RTABLE_SHFT(_L)) - - -#define ROUTERINFO_STKSZ 4096 - -#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) -#if defined(_LANGUAGE_C_PLUS_PLUS) -extern "C" { -#endif - -int router_reg_read(router_info_t *rip, int regno, router_reg_t *val); -int router_reg_write(router_info_t *rip, int regno, router_reg_t val); -int router_get_info(devfs_handle_t routerv, router_info_t *, int); -int router_init(cnodeid_t cnode,int writeid, nodepda_router_info_t *npda_rip); -int router_set_leds(router_info_t *rip); -void router_print_state(router_info_t *rip, int level, - void (*pf)(int, char *, ...),int print_where); -void capture_router_stats(router_info_t *rip); - - -int probe_routers(void); -void get_routername(unsigned char brd_type,char *rtrname); -void router_guardians_set(devfs_handle_t hwgraph_root); -int router_hist_reselect(router_info_t *, int64_t); -#if defined(_LANGUAGE_C_PLUS_PLUS) -} -#endif -#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */ - -#endif /* _ASM_SN_SN1_ROUTER_H */ diff --git a/include/asm-ia64/sn/sn1/slotnum.h b/include/asm-ia64/sn/sn1/slotnum.h index e88466adf8c0..1d5f05a70e53 100644 --- a/include/asm-ia64/sn/sn1/slotnum.h +++ b/include/asm-ia64/sn/sn1/slotnum.h @@ -4,12 +4,11 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_SLOTNUM_H -#define _ASM_SN_SN1_SLOTNUM_H +#ifndef _ASM_IA64_SN_SN1_SLOTNUM_H +#define _ASM_IA64_SN_SN1_SLOTNUM_H #define SLOTNUM_MAXLENGTH 16 @@ -85,4 +84,4 @@ extern int slot_to_widget(int) ; #endif /* __KERNEL__ */ -#endif /* _ASM_SN_SN1_SLOTNUM_H */ +#endif /* _ASM_IA64_SN_SN1_SLOTNUM_H */ diff --git a/include/asm-ia64/sn/sn1/sn1.h b/include/asm-ia64/sn/sn1/sn1.h deleted file mode 100644 index e03c2847a808..000000000000 --- a/include/asm-ia64/sn/sn1/sn1.h +++ /dev/null @@ -1,34 +0,0 @@ -/* $Id$ - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam - */ - -/* - * sn1.h -- hardware specific defines for sn1 boards - * The defines used here are used to limit the size of - * various datastructures in the PROM. eg. KLCFGINFO, MPCONF etc. - */ - -#ifndef _ASM_SN_SN1_SN1_H -#define _ASM_SN_SN1_SN1_H - -extern xwidgetnum_t hub_widget_id(nasid_t); -extern nasid_t get_nasid(void); -extern int get_slice(void); -extern int is_fine_dirmode(void); -extern hubreg_t get_hub_chiprev(nasid_t nasid); -extern hubreg_t get_region(cnodeid_t); -extern hubreg_t nasid_to_region(nasid_t); -extern int verify_snchip_rev(void); -extern void ni_reset_port(void); - -#ifdef SN1_USE_POISON_BITS -extern int hub_bte_poison_ok(void); -#endif /* SN1_USE_POISON_BITS */ - -#endif /* _ASM_SN_SN1_SN1_H */ diff --git a/include/asm-ia64/sn/sn1/sn_private.h b/include/asm-ia64/sn/sn1/sn_private.h new file mode 100644 index 000000000000..a88646e6528a --- /dev/null +++ b/include/asm-ia64/sn/sn1/sn_private.h @@ -0,0 +1,292 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + */ +#ifndef _ASM_IA64_SN_SN1_SN_PRIVATE_H +#define _ASM_IA64_SN_SN1_SN_PRIVATE_H + +#include <asm/sn/nodepda.h> +#include <asm/sn/xtalk/xwidget.h> +#include <asm/sn/xtalk/xtalk_private.h> + +extern nasid_t master_nasid; + +/* promif.c */ +#ifdef LATER +extern cpuid_t cpu_node_probe(cpumask_t *cpumask, int *numnodes); +#endif +extern void he_arcs_set_vectors(void); +extern void mem_init(void); +#ifdef LATER +extern int cpu_enabled(cpuid_t); +#endif +extern void cpu_unenable(cpuid_t); +extern nasid_t get_lowest_nasid(void); +extern __psunsigned_t get_master_bridge_base(void); +extern void set_master_bridge_base(void); +extern int check_nasid_equiv(nasid_t, nasid_t); +extern nasid_t get_console_nasid(void); +extern char get_console_pcislot(void); +#ifdef LATER +extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int); +#endif + +extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid); + +/* memsupport.c */ +extern void poison_state_alter_range(__psunsigned_t start, int len, int poison); +extern int memory_present(paddr_t); +extern int memory_read_accessible(paddr_t); +extern int memory_write_accessible(paddr_t); +extern void memory_set_access(paddr_t, int, int); +extern void show_dir_state(paddr_t, void (*)(char *, ...)); +extern void check_dir_state(nasid_t, int, void (*)(char *, ...)); +extern void set_dir_owner(paddr_t, int); +extern void set_dir_state(paddr_t, int); +extern void set_dir_state_POISONED(paddr_t); +extern void set_dir_state_UNOWNED(paddr_t); +extern int is_POISONED_dir_state(paddr_t); +extern int is_UNOWNED_dir_state(paddr_t); +extern void get_dir_ent(paddr_t paddr, int *state, + uint64_t *vec_ptr, hubreg_t *elo); + +/* intr.c */ +extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name); +extern void intr_unreserve_level(cpuid_t cpu, int level); +extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, + intr_func_t intr_prefunc); +extern int intr_disconnect_level(cpuid_t cpu, int bit); +extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc, + int req_bit,int intr_resflags,devfs_handle_t owner_dev, + char *intr_name,int *resp_bit); +extern void intr_block_bit(cpuid_t cpu, int bit); +extern void intr_unblock_bit(cpuid_t cpu, int bit); +extern void setrtvector(intr_func_t); +extern void install_cpuintr(cpuid_t cpu); +extern void install_dbgintr(cpuid_t cpu); +extern void install_tlbintr(cpuid_t cpu); +extern void hub_migrintr_init(cnodeid_t /*cnode*/); +extern int cause_intr_connect(int level, intr_func_t handler, uint intr_spl_mask); +extern int cause_intr_disconnect(int level); +extern void intr_reserve_hardwired(cnodeid_t); +extern void intr_clear_all(nasid_t); +extern void intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...)); + +/* error_dump.c */ +extern char *hub_rrb_err_type[]; +extern char *hub_wrb_err_type[]; + +void nmi_dump(void); +void install_cpu_nmi_handler(int slice); + +/* klclock.c */ +extern void hub_rtc_init(cnodeid_t); + +/* bte.c */ +void bte_lateinit(void); +void bte_wait_for_xfer_completion(void *); + +/* klgraph.c */ +void klhwg_add_all_nodes(devfs_handle_t); +void klhwg_add_all_modules(devfs_handle_t); + +/* klidbg.c */ +void install_klidbg_functions(void); + +/* klnuma.c */ +extern void replicate_kernel_text(int numnodes); +extern __psunsigned_t get_freemem_start(cnodeid_t cnode); +extern void setup_replication_mask(int maxnodes); + +/* init.c */ +extern cnodeid_t get_compact_nodeid(void); /* get compact node id */ +extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node); +extern void init_platform_pda(cpuid_t cpu); +extern void per_cpu_init(void); +#ifdef LATER +extern cpumask_t boot_cpumask; +#endif +extern int is_fine_dirmode(void); +extern void update_node_information(cnodeid_t); + +#ifdef LATER +/* clksupport.c */ +extern void early_counter_intr(eframe_t *); +#endif + +/* hubio.c */ +extern void hubio_init(void); +extern void hub_merge_clean(nasid_t nasid); +extern void hub_set_piomode(nasid_t nasid, int conveyor); + +/* huberror.c */ +extern void hub_error_init(cnodeid_t); +extern void dump_error_spool(cpuid_t cpu, void (*pf)(char *, ...)); +extern void hubni_error_handler(char *, int); +extern int check_ni_errors(void); + +/* Used for debugger to signal upper software a breakpoint has taken place */ + +extern void *debugger_update; +extern __psunsigned_t debugger_stopped; + +/* + * IP27 piomap, created by hub_pio_alloc. + * xtalk_info MUST BE FIRST, since this structure is cast to a + * xtalk_piomap_s by generic xtalk routines. + */ +struct hub_piomap_s { + struct xtalk_piomap_s hpio_xtalk_info;/* standard crosstalk pio info */ + devfs_handle_t hpio_hub; /* which hub's mapping registers are set up */ + short hpio_holdcnt; /* count of current users of bigwin mapping */ + char hpio_bigwin_num;/* if big window map, which one */ + int hpio_flags; /* defined below */ +}; +/* hub_piomap flags */ +#define HUB_PIOMAP_IS_VALID 0x1 +#define HUB_PIOMAP_IS_BIGWINDOW 0x2 +#define HUB_PIOMAP_IS_FIXED 0x4 + +#define hub_piomap_xt_piomap(hp) (&hp->hpio_xtalk_info) +#define hub_piomap_hub_v(hp) (hp->hpio_hub) +#define hub_piomap_winnum(hp) (hp->hpio_bigwin_num) + +#if TBD + /* Ensure that hpio_xtalk_info is first */ + #assert (&(((struct hub_piomap_s *)0)->hpio_xtalk_info) == 0) +#endif + + +/* + * IP27 dmamap, created by hub_pio_alloc. + * xtalk_info MUST BE FIRST, since this structure is cast to a + * xtalk_dmamap_s by generic xtalk routines. + */ +struct hub_dmamap_s { + struct xtalk_dmamap_s hdma_xtalk_info;/* standard crosstalk dma info */ + devfs_handle_t hdma_hub; /* which hub we go through */ + int hdma_flags; /* defined below */ +}; +/* hub_dmamap flags */ +#define HUB_DMAMAP_IS_VALID 0x1 +#define HUB_DMAMAP_USED 0x2 +#define HUB_DMAMAP_IS_FIXED 0x4 + +#if TBD + /* Ensure that hdma_xtalk_info is first */ + #assert (&(((struct hub_dmamap_s *)0)->hdma_xtalk_info) == 0) +#endif + +/* + * IP27 interrupt handle, created by hub_intr_alloc. + * xtalk_info MUST BE FIRST, since this structure is cast to a + * xtalk_intr_s by generic xtalk routines. + */ +struct hub_intr_s { + struct xtalk_intr_s i_xtalk_info; /* standard crosstalk intr info */ + ilvl_t i_swlevel; /* software level for blocking intr */ + cpuid_t i_cpuid; /* which cpu */ + int i_bit; /* which bit */ + int i_flags; +}; +/* flag values */ +#define HUB_INTR_IS_ALLOCED 0x1 /* for debug: allocated */ +#define HUB_INTR_IS_CONNECTED 0x4 /* for debug: connected to a software driver */ + +#if TBD + /* Ensure that i_xtalk_info is first */ + #assert (&(((struct hub_intr_s *)0)->i_xtalk_info) == 0) +#endif + + +/* IP27 hub-specific information stored under INFO_LBL_HUB_INFO */ +/* TBD: IP27-dependent stuff currently in nodepda.h should be here */ +typedef struct hubinfo_s { + nodepda_t *h_nodepda; /* pointer to node's private data area */ + cnodeid_t h_cnodeid; /* compact nodeid */ + nasid_t h_nasid; /* nasid */ + + /* structures for PIO management */ + xwidgetnum_t h_widgetid; /* my widget # (as viewed from xbow) */ + struct hub_piomap_s h_small_window_piomap[HUB_WIDGET_ID_MAX+1]; + sv_t h_bwwait; /* wait for big window to free */ + spinlock_t h_bwlock; /* guard big window piomap's */ + spinlock_t h_crblock; /* gaurd CRB error handling */ + int h_num_big_window_fixed; /* count number of FIXED maps */ + struct hub_piomap_s h_big_window_piomap[HUB_NUM_BIG_WINDOW]; + hub_intr_t hub_ii_errintr; +} *hubinfo_t; + +#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \ + (vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr)) + +#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \ + (vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr) + +#define hubinfo_to_hubv(hinfo, hub_v) (hinfo->h_nodepda->node_vertex) + +/* + * Hub info PIO map access functions. + */ +#define hubinfo_bwin_piomap_get(hinfo, win) \ + (&hinfo->h_big_window_piomap[win]) +#define hubinfo_swin_piomap_get(hinfo, win) \ + (&hinfo->h_small_window_piomap[win]) + +/* IP27 cpu-specific information stored under INFO_LBL_CPU_INFO */ +/* TBD: IP27-dependent stuff currently in pda.h should be here */ +typedef struct cpuinfo_s { +#ifdef LATER + pda_t *ci_cpupda; /* pointer to CPU's private data area */ +#endif + cpuid_t ci_cpuid; /* CPU ID */ +} *cpuinfo_t; + +#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \ + (vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr)) + +#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \ + (vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr) + +/* Special initialization function for xswitch vertices created during startup. */ +extern void xswitch_vertex_init(devfs_handle_t xswitch); + +extern xtalk_provider_t hub_provider; + +/* du.c */ +int ducons_write(char *buf, int len); + +/* memerror.c */ + +extern void install_eccintr(cpuid_t cpu); +extern void memerror_get_stats(cnodeid_t cnode, + int *bank_stats, int *bank_stats_max); +extern void probe_md_errors(nasid_t); +/* sysctlr.c */ +extern void sysctlr_init(void); +extern void sysctlr_power_off(int sdonly); +extern void sysctlr_keepalive(void); + +#define valid_cpuid(_x) (((_x) >= 0) && ((_x) < maxcpus)) + +/* Useful definitions to get the memory dimm given a physical + * address. + */ +#define paddr_dimm(_pa) ((_pa & MD_BANK_MASK) >> MD_BANK_SHFT) +#define paddr_cnode(_pa) (NASID_TO_COMPACT_NODEID(NASID_GET(_pa))) +extern void membank_pathname_get(paddr_t,char *); + +/* To redirect the output into the error buffer */ +#define errbuf_print(_s) printf("#%s",_s) + +extern void crbx(nasid_t nasid, void (*pf)(char *, ...)); +void bootstrap(void); + +/* sndrv.c */ +extern int sndrv_attach(devfs_handle_t vertex); + +#endif /* _ASM_IA64_SN_SN1_SN_PRIVATE_H */ diff --git a/include/asm-ia64/sn/synergy.h b/include/asm-ia64/sn/sn1/synergy.h index 2e52ccf29c77..c4bf26cd1458 100644 --- a/include/asm-ia64/sn/synergy.h +++ b/include/asm-ia64/sn/sn1/synergy.h @@ -1,11 +1,10 @@ -#ifndef ASM_IA64_SN_SYNERGY_H -#define ASM_IA64_SN_SYNERGY_H +#ifndef _ASM_IA64_SN_SN1_SYNERGY_H +#define _ASM_IA64_SN_SN1_SYNERGY_H -#include <linux/config.h> - -#include "asm/io.h" -#include "asm/sn/nodepda.h" -#include "asm/sn/intr_public.h" +#include <asm/io.h> +#include <asm/sn/hcl.h> +#include <asm/sn/addrs.h> +#include <asm/sn/intr_public.h> /* @@ -13,12 +12,21 @@ * * These are for SGI platforms only. * - * Copyright (C) 2000 Silicon Graphics, Inc - * Copyright (C) 2000 Alan Mayer (ajm@sgi.com) + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#define SSPEC_BASE (0xe0000000000) +#define SYNERGY_L4_BYTES (64UL*1024*1024) +#define SYNERGY_L4_WAYS 8 +#define SYNERGY_L4_BYTES_PER_WAY (SYNERGY_L4_BYTES/SYNERGY_L4_WAYS) +#define SYNERGY_BLOCK_SIZE 512UL + + +#define SSPEC_BASE (0xe0000000000UL) #define LB_REG_BASE (SSPEC_BASE + 0x0) #define VEC_MASK3A_ADDR (0x2a0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) @@ -41,9 +49,11 @@ #define VEC_MASK0A (0x2d0) #define VEC_MASK0B (0x2d8) +#define GBL_PERF_A_ADDR (0x330 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) +#define GBL_PERF_B_ADDR (0x338 + LB_REG_BASE + __IA64_UNCACHED_OFFSET) + #define WRITE_LOCAL_SYNERGY_REG(addr, value) __synergy_out(addr, value) -#define HUBREG_CAST (volatile hubreg_t *) #define HUB_L(_a) *(_a) #define HUB_S(_a, _d) *(_a) = (_d) @@ -63,13 +73,15 @@ #define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS) #define NODE_SIZE_BITS 33 +#define SYN_TAG_DISABLE_WAY (SSPEC_BASE+0xae0) + #define RSYN_REG_OFFSET(fsb, reg) (((fsb) ? HSPEC_SYNERGY1_0 : HSPEC_SYNERGY0_0) | (reg)) #define REMOTE_SYNERGY_LOAD(nasid, fsb, reg) __remote_synergy_in(nasid, fsb, reg) #define REMOTE_SYNERGY_STORE(nasid, fsb, reg, val) __remote_synergy_out(nasid, fsb, reg, val) -extern inline uint64_t +static inline uint64_t __remote_synergy_in(int nasid, int fsb, uint64_t reg) { volatile uint64_t *addr; @@ -77,7 +89,7 @@ __remote_synergy_in(int nasid, int fsb, uint64_t reg) { return (*addr); } -extern inline void +static inline void __remote_synergy_out(int nasid, int fsb, uint64_t reg, uint64_t value) { volatile uint64_t *addr; @@ -90,7 +102,7 @@ __remote_synergy_out(int nasid, int fsb, uint64_t reg, uint64_t value) { } /* XX this doesn't make a lot of sense. Which fsb? */ -extern inline void +static inline void __synergy_out(unsigned long addr, unsigned long value) { volatile unsigned long *adr = (unsigned long *) @@ -103,7 +115,7 @@ __synergy_out(unsigned long addr, unsigned long value) #define READ_LOCAL_SYNERGY_REG(addr) __synergy_in(addr) /* XX this doesn't make a lot of sense. Which fsb? */ -extern inline unsigned long +static inline unsigned long __synergy_in(unsigned long addr) { unsigned long ret, *adr = (unsigned long *) @@ -130,11 +142,19 @@ struct sn1_cnode_action_list { struct sn1_intr_action *action_list; }; -#if defined(CONFIG_IA64_SGI_SYNERGY_PERF) +/* + * ioctl cmds for node/hub/synergy/[01]/mon for synergy + * perf monitoring are defined in sndrv.h + */ /* multiplex the counters every 10 timer interrupts */ #define SYNERGY_PERF_FREQ_DEFAULT 10 +/* macros for synergy "mon" device ioctl handler */ +#define SYNERGY_PERF_INFO(_s, _f) (arbitrary_info_t)(((_s) << 16)|(_f)) +#define SYNERGY_PERF_INFO_CNODE(_x) (cnodeid_t)(((uint64_t)_x) >> 16) +#define SYNERGY_PERF_INFO_FSB(_x) (((uint64_t)_x) & 1) + /* synergy perf control registers */ #define PERF_CNTL0_A 0xab0UL /* control A on FSB0 */ #define PERF_CNTL0_B 0xab8UL /* control B on FSB0 */ @@ -150,6 +170,7 @@ struct sn1_cnode_action_list { /* Synergy perf data. Each nodepda keeps a list of these */ struct synergy_perf_s { uint64_t intervals; /* count of active intervals for this event */ + uint64_t total_intervals;/* snapshot of total intervals */ uint64_t modesel; /* mode and sel bits, both A and B registers */ struct synergy_perf_s *next; /* next in circular linked list */ uint64_t counts[2]; /* [0] is synergy-A counter, [1] synergy-B counter */ @@ -157,12 +178,10 @@ struct synergy_perf_s { typedef struct synergy_perf_s synergy_perf_t; +typedef struct synergy_info_s synergy_info_t; + extern void synergy_perf_init(void); extern void synergy_perf_update(int); +extern struct file_operations synergy_mon_fops; -#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */ - - -/* Temporary defintions for testing: */ - -#endif ASM_IA64_SN_SYNERGY_H +#endif /* _ASM_IA64_SN_SN1_SYNERGY_H */ diff --git a/include/asm-ia64/sn/sn2/addrs.h b/include/asm-ia64/sn/sn2/addrs.h new file mode 100644 index 000000000000..e5f31b0776f8 --- /dev/null +++ b/include/asm-ia64/sn/sn2/addrs.h @@ -0,0 +1,153 @@ +/* + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2001 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_SN_SN2_ADDRS_H +#define _ASM_IA64_SN_SN2_ADDRS_H + +/* McKinley Address Format: + * + * 4 4 3 3 3 3 + * 9 8 8 7 6 5 0 + * +-+---------+----+--------------+ + * |0| Node ID | AS | Node Offset | + * +-+---------+----+--------------+ + * + * Node ID: If bit 38 = 1, is ICE, else is SHUB + * AS: Address Space Identifier. Used only if bit 38 = 0. + * b'00: Local Resources and MMR space + * bit 35 + * 0: Local resources space + * node id: + * 0: IA64/NT compatibility space + * 2: Local MMR Space + * 4: Local memory, regardless of local node id + * 1: Global MMR space + * b'01: GET space. + * b'10: AMO space. + * b'11: Cacheable memory space. + * + * NodeOffset: byte offset + */ + +#ifndef __ASSEMBLY__ +typedef union ia64_sn2_pa { + struct { + unsigned long off : 36; + unsigned long as : 2; + unsigned long nasid: 11; + unsigned long fill : 15; + } f; + unsigned long l; + void *p; +} ia64_sn2_pa_t; +#endif + +#define TO_PHYS_MASK 0x0001ffcfffffffff /* Note - clear AS bits */ + + +/* Regions determined by AS */ +#define LOCAL_MMR_SPACE 0xc000008000000000 /* Local MMR space */ +#define LOCAL_MEM_SPACE 0xc000010000000000 /* Local Memory space */ +#define GLOBAL_MMR_SPACE 0xc000000800000000 /* Global MMR space */ +#define GET_SPACE 0xc000001000000000 /* GET space */ +#define AMO_SPACE 0xc000002000000000 /* AMO space */ +#define CACHEABLE_MEM_SPACE 0xe000003000000000 /* Cacheable memory space */ +#define UNCACHED 0xc000000000000000 /* UnCacheable memory space */ + +/* SN2 address macros */ +#define NID_SHFT 38 +#define LOCAL_MMR_ADDR(a) (UNCACHED | LOCAL_MMR_SPACE | (a)) +#define LOCAL_MEM_ADDR(a) (LOCAL_MEM_SPACE | (a)) +#define REMOTE_ADDR(n,a) ((((unsigned long)(n))<<NID_SHFT) | (a)) +#define GLOBAL_MMR_ADDR(n,a) (UNCACHED | GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a)) +#define GET_ADDR(n,a) (GET_SPACE | REMOTE_ADDR(n,a)) +#define AMO_ADDR(n,a) (UNCACHED | AMO_SPACE | REMOTE_ADDR(n,a)) +#define GLOBAL_MEM_ADDR(n,a) (CACHEABLE_MEM_SPACE | REMOTE_ADDR(n,a)) + +/* non-II mmr's start at top of big window space (4G) */ +#define BWIN_TOP 0x0000000100000000 + +/* + * general address defines - for code common to SN0/SN1/SN2 + */ +#define CAC_BASE CACHEABLE_MEM_SPACE /* cacheable memory space */ +#define IO_BASE (UNCACHED | GLOBAL_MMR_SPACE) /* lower 4G maps II's XIO space */ +#define AMO_BASE (UNCACHED | AMO_SPACE) /* fetch & op space */ +#define MSPEC_BASE AMO_BASE /* fetch & op space */ +#define UNCAC_BASE (UNCACHED | CACHEABLE_MEM_SPACE) /* uncached global memory */ +#define GET_BASE GET_SPACE /* momentarily coherent remote mem. */ +#define CALIAS_BASE LOCAL_CACHEABLE_BASE /* cached node-local memory */ +#define UALIAS_BASE (UNCACHED | LOCAL_CACHEABLE_BASE) /* uncached node-local memory */ + +#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) +#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_GET(x) (GET_BASE | ((x) & TO_PHYS_MASK)) +#define TO_CALIAS(x) (CALIAS_BASE | TO_NODE_ADDRSPACE(x)) +#define TO_UALIAS(x) (UALIAS_BASE | TO_NODE_ADDRSPACE(x)) +#define NODE_SIZE_BITS 36 /* node offset : bits <35:0> */ +#define BWIN_SIZE_BITS 29 /* big window size: 512M */ +#define NASID_BITS 11 /* bits <48:38> */ +#define NASID_BITMASK (0x7ffULL) +#define NASID_SHFT NID_SHFT +#define NASID_META_BITS 0 /* ???? */ +#define NASID_LOCAL_BITS 7 /* same router as SN1 */ + +#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) +#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT) +#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ + NASID_SHFT) & NASID_BITMASK) + +#define CHANGE_NASID(n,x) ({ia64_sn2_pa_t _v; _v.l = (long) (x); _v.f.nasid = n; _v.p;}) + +#ifndef __ASSEMBLY__ +#define NODE_SWIN_BASE(nasid, widget) \ + ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ + : RAW_NODE_SWIN_BASE(nasid, widget)) +#else +#define NODE_SWIN_BASE(nasid, widget) \ + (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) +#define LOCAL_SWIN_BASE(widget) \ + (UNCACHED | LOCAL_MMR_SPACE | ((UINT64_CAST (widget) << SWIN_SIZE_BITS))) +#endif /* __ASSEMBLY__ */ + +/* + * The following definitions pertain to the IO special address + * space. They define the location of the big and little windows + * of any given node. + */ + +#define BWIN_INDEX_BITS 3 +#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS) +#define BWIN_SIZEMASK (BWIN_SIZE - 1) +#define BWIN_WIDGET_MASK 0x7 +#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) +#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ + (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) + +#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) +#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) + +/* + * Verify if addr belongs to large window address of node with "nasid" + * + * + * NOTE: "addr" is expected to be XKPHYS address, and NOT physical + * address + * + * + */ + +#define NODE_BWIN_ADDR(nasid, addr) \ + (((addr) >= NODE_BWIN_BASE0(nasid)) && \ + ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ + BWIN_SIZE))) + +#endif /* _ASM_IA64_SN_SN2_ADDRS_H */ diff --git a/include/asm-ia64/sn/sn2/arch.h b/include/asm-ia64/sn/sn2/arch.h new file mode 100644 index 000000000000..3dafe8e05851 --- /dev/null +++ b/include/asm-ia64/sn/sn2/arch.h @@ -0,0 +1,66 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + */ +#ifndef _ASM_IA64_SN_SN2_ARCH_H +#define _ASM_IA64_SN_SN2_ARCH_H + +#include <asm/types.h> + + +#define CPUS_PER_NODE 4 /* CPUs on a single hub */ +#define CPUS_PER_SUBNODE 4 /* CPUs on a single hub PI */ + + +/* + * This is the maximum number of NASIDS that can be present in a system. + * (Highest NASID plus one.) + */ +#define MAX_NASIDS 2048 + + +/* + * This is the maximum number of nodes that can be part of a kernel. + * Effectively, it's the maximum number of compact node ids (cnodeid_t). + * This is not necessarily the same as MAX_NASIDS. + */ +#define MAX_COMPACT_NODES 128 + +/* + * MAX_REGIONS refers to the maximum number of hardware partitioned regions. + */ +#define MAX_REGIONS 64 +#define MAX_NONPREMIUM_REGIONS 16 +#define MAX_PREMIUM_REGIONS MAX_REGIONS + + +/* + * MAX_PARITIONS refers to the maximum number of logically defined + * partitions the system can support. + */ +#define MAX_PARTITIONS MAX_REGIONS + + +#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8) + + +/* + * 1 FSB per SHUB, with up to 4 cpus per FSB. + */ +#define NUM_SUBNODES 1 +#define SUBNODE_SHFT 0 +#define SUBNODE_MASK (0x0 << SUBNODE_SHFT) +#define LOCALCPU_SHFT 0 +#define LOCALCPU_MASK (0x3 << LOCALCPU_SHFT) +#define SUBNODE(slice) (((slice) & SUBNODE_MASK) >> SUBNODE_SHFT) +#define LOCALCPU(slice) (((slice) & LOCALCPU_MASK) >> LOCALCPU_SHFT) +#define TO_SLICE(subn, local) (((subn) << SUBNODE_SHFT) | \ + ((local) << LOCALCPU_SHFT)) + +typedef u64 mmr_t; + +#endif /* _ASM_IA64_SN_SN2_ARCH_H */ diff --git a/include/asm-ia64/sn/sn2/intr.h b/include/asm-ia64/sn/sn2/intr.h new file mode 100644 index 000000000000..1fee72e396ce --- /dev/null +++ b/include/asm-ia64/sn/sn2/intr.h @@ -0,0 +1,25 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + */ +#ifndef _ASM_IA64_SN_SN2_INTR_H +#define _ASM_IA64_SN_SN2_INTR_H + +#define SGI_UART_VECTOR (0xe9) +#define SGI_SHUB_ERROR_VECTOR (0xea) + +// These two IRQ's are used by partitioning. +#define SGI_XPC_NOTIFY (0xe7) +#define SGI_XPART_ACTIVATE (0x30) + +#define IA64_SN2_FIRST_DEVICE_VECTOR (0x31) +#define IA64_SN2_LAST_DEVICE_VECTOR (0xe6) + +#define SN2_IRQ_RESERVED (0x1) +#define SN2_IRQ_CONNECTED (0x2) + +#endif /* _ASM_IA64_SN_SN2_INTR_H */ diff --git a/include/asm-ia64/sn/sn2/mmzone_sn2.h b/include/asm-ia64/sn/sn2/mmzone_sn2.h new file mode 100644 index 000000000000..0f5fec8bee96 --- /dev/null +++ b/include/asm-ia64/sn/sn2/mmzone_sn2.h @@ -0,0 +1,165 @@ +#ifndef _ASM_IA64_SN_MMZONE_SN2_H +#define _ASM_IA64_SN_MMZONE_SN2_H + +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2000-2002 Silicon Graphics, Inc. All rights reserved. + */ + +#include <linux/config.h> + + +/* + * SGI SN2 Arch defined values + * + * An SN2 physical address is broken down as follows: + * + * +-----------------------------------------+ + * | | | | node offset | + * | unused | node | AS |-------------------| + * | | | | cn | clump offset | + * +-----------------------------------------+ + * 6 4 4 3 3 3 3 3 3 0 + * 3 9 8 8 7 6 5 4 3 0 + * + * bits 63-49 Unused - must be zero + * bits 48-38 Node number. Note that some configurations do NOT + * have a node zero. + * bits 37-36 Address space ID. Cached memory has a value of 3 (!!!). + * Chipset & IO addresses have other values. + * (Yikes!! The hardware folks hate us...) + * bits 35-0 Node offset. + * + * The node offset can be further broken down as: + * bits 35-34 Clump (bank) number. + * bits 33-0 Clump (bank) offset. + * + * A node consists of up to 4 clumps (banks) of memory. A clump may be empty, or may be + * populated with a single contiguous block of memory starting at clump + * offset 0. The size of the block is (2**n) * 64MB, where 0<n<9. + * + * Important notes: + * - IO space addresses are embedded with the range of valid memory addresses. + * - All cached memory addresses have bits 36 & 37 set to 1's. + * - There is no physical address 0. + * + * NOTE: This file exports symbols prefixed with "PLAT_". Symbols prefixed with + * "SN_" are intended for internal use only and should not be used in + * any platform independent code. + * + * This file is also responsible for exporting the following definitions: + * cnodeid_t Define a compact node id. + */ + +typedef signed short cnodeid_t; + +#define SN2_BANKS_PER_NODE 4 +#define SN2_NODE_SIZE (64UL*1024*1024*1024) /* 64GB per node */ +#define SN2_BANK_SIZE (SN2_NODE_SIZE/SN2_BANKS_PER_NODE) +#define SN2_NODE_SHIFT 38 +#define SN2_NODE_MASK 0x7ffUL +#define SN2_NODE_OFFSET_MASK (SN2_NODE_SIZE-1) +#define SN2_NODE_NUMBER(addr) (((unsigned long)(addr) >> SN2_NODE_SHIFT) & SN2_NODE_MASK) +#define SN2_NODE_CLUMP_NUMBER(kaddr) (((unsigned long)(kaddr) >>34) & 3) +#define SN2_NODE_OFFSET(addr) (((unsigned long)(addr)) & SN2_NODE_OFFSET_MASK) +#define SN2_KADDR(nasid, offset) (((unsigned long)(nasid)<<SN2_NODE_SHIFT) | (offset) | SN2_PAGE_OFFSET) +#define SN2_PAGE_OFFSET 0xe000003000000000UL /* Cacheable memory space */ + + +#define PLAT_MAX_NODE_NUMBER 2048 /* Maximum node number + 1 */ +#define PLAT_MAX_COMPACT_NODES 128 /* Maximum number of nodes in SSI system */ + +#define PLAT_MAX_PHYS_MEMORY (1UL << 49) + + + +/* + * On the SN platforms, a clump is the same as a memory bank. + */ +#define PLAT_CLUMPS_PER_NODE SN2_BANKS_PER_NODE +#define PLAT_CLUMP_OFFSET(addr) ((unsigned long)(addr) & 0x3ffffffffUL) +#define PLAT_CLUMPSIZE (SN2_NODE_SIZE/PLAT_CLUMPS_PER_NODE) +#define PLAT_MAXCLUMPS (PLAT_CLUMPS_PER_NODE * PLAT_MAX_COMPACT_NODES) + + + +/* + * PLAT_VALID_MEM_KADDR returns a boolean to indicate if a kaddr is potentially a + * valid cacheable identity mapped RAM memory address. + * Note that the RAM may or may not actually be present!! + */ +#define SN2_VALID_KERN_ADDR_MASK 0xffff003000000000UL +#define SN2_VALID_KERN_ADDR_VALUE 0xe000003000000000UL +#define PLAT_VALID_MEM_KADDR(kaddr) (((unsigned long)(kaddr) & SN2_VALID_KERN_ADDR_MASK) == SN2_VALID_KERN_ADDR_VALUE) + + + +/* + * Memory is conceptually divided into chunks. A chunk is either + * completely present, or else the kernel assumes it is completely + * absent. Each node consists of a number of possibly contiguous chunks. + */ +#define SN2_CHUNKSHIFT 25 /* 32 MB */ +#define SN2_CHUNKSIZE (1UL << SN2_CHUNKSHIFT) +#define PLAT_CHUNKNUM(addr) ({unsigned long _p=(unsigned long)(addr); \ + (((_p&SN2_NODE_MASK)>>2) | \ + (_p&SN2_NODE_OFFSET_MASK)) >>SN2_CHUNKSHIFT;}) + +/* + * Given a kaddr, find the nid (compact nodeid) + */ +#ifdef CONFIG_IA64_SGI_SN_DEBUG +#define DISCONBUG(kaddr) panic("DISCONTIG BUG: line %d, %s. kaddr 0x%lx", \ + __LINE__, __FILE__, (long)(kaddr)) + +#define KVADDR_TO_NID(kaddr) ({long _ktn=(long)(kaddr); \ + kern_addr_valid(_ktn) ? \ + local_node_data->physical_node_map[SN2_NODE_NUMBER(_ktn)] : \ + (DISCONBUG(_ktn), 0UL);}) +#else +#define KVADDR_TO_NID(kaddr) (local_node_data->physical_node_map[SN2_NODE_NUMBER(kaddr)]) +#endif + + + +/* + * Given a kaddr, find the index into the clump_mem_map_base array of the page struct entry + * for the first page of the clump. + */ +#define PLAT_CLUMP_MEM_MAP_INDEX(kaddr) ({long _kmmi=(long)(kaddr); \ + KVADDR_TO_NID(_kmmi) * PLAT_CLUMPS_PER_NODE + \ + SN2_NODE_CLUMP_NUMBER(_kmmi);}) + + + +/* + * Calculate a "goal" value to be passed to __alloc_bootmem_node for allocating structures on + * nodes so that they dont alias to the same line in the cache as the previous allocated structure. + * This macro takes an address of the end of previous allocation, rounds it to a page boundary & + * changes the node number. + */ +#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) SN2_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnodeid]), \ + (SN2_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT) + + + + +/* + * Convert a proximity domain number (from the ACPI tables) into a physical node number. + * Note: on SN2, the promity domain number is the same as bits [8:1] of the NASID. The following + * algorithm relies on: + * - bit 0 of the NASID for cpu nodes is always 0 + * - bits [10:9] of all NASIDs in a partition are always the same + * - hard_smp_processor_id return the SAPIC of the current cpu & + * bits 0..11 contain the NASID. + * + * All of this complexity is because MS architectually limited proximity domain numbers to + * 8 bits. + */ + +#define PLAT_PXM_TO_PHYS_NODE_NUMBER(pxm) (((pxm)<<1) | (hard_smp_processor_id() & 0x300)) + +#endif /* _ASM_IA64_SN_MMZONE_SN2_H */ diff --git a/include/asm-ia64/sn/sn2/shub.h b/include/asm-ia64/sn/sn2/shub.h new file mode 100644 index 000000000000..2c6719107c83 --- /dev/null +++ b/include/asm-ia64/sn/sn2/shub.h @@ -0,0 +1,44 @@ +/* + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2001 Silicon Graphics, Inc. All rights reserved. + */ + + +#ifndef _ASM_IA64_SN_SN2_SHUB_H +#define _ASM_IA64_SN_SN2_SHUB_H + +#include <asm/sn/sn2/shub_mmr.h> /* shub mmr addresses and formats */ +#include <asm/sn/sn2/shub_md.h> +#include <asm/sn/sn2/shubio.h> +#ifndef __ASSEMBLY__ +#include <asm/sn/sn2/shub_mmr_t.h> /* shub mmr struct defines */ +#endif + +/* + * Junk Bus Address Space + * The junk bus is used to access the PROM, LED's, and UART. It's + * accessed through the local block MMR space. The data path is + * 16 bits wide. This space requires address bits 31-27 to be set, and + * is further divided by address bits 26:15. + * The LED addresses are write-only. To read the LEDs, you need to use + * SH_JUNK_BUS_LED0-3, defined in shub_mmr.h + * + */ +#define SH_REAL_JUNK_BUS_LED0 0x7fed00000 +#define SH_REAL_JUNK_BUS_LED1 0x7fed10000 +#define SH_REAL_JUNK_BUS_LED2 0x7fed20000 +#define SH_REAL_JUNK_BUS_LED3 0x7fed30000 +#define SH_JUNK_BUS_UART0 0x7fed40000 +#define SH_JUNK_BUS_UART1 0x7fed40008 +#define SH_JUNK_BUS_UART2 0x7fed40010 +#define SH_JUNK_BUS_UART3 0x7fed40018 +#define SH_JUNK_BUS_UART4 0x7fed40020 +#define SH_JUNK_BUS_UART5 0x7fed40028 +#define SH_JUNK_BUS_UART6 0x7fed40030 +#define SH_JUNK_BUS_UART7 0x7fed40038 + +#endif /* _ASM_IA64_SN_SN2_SHUB_H */ diff --git a/include/asm-ia64/sn/sn2/shub_md.h b/include/asm-ia64/sn/sn2/shub_md.h new file mode 100644 index 000000000000..d13b112e526b --- /dev/null +++ b/include/asm-ia64/sn/sn2/shub_md.h @@ -0,0 +1,278 @@ +/************************************************************************** + * * + * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved. * + * * + * These coded instructions, statements, and computer programs contain * + * unpublished proprietary information of Silicon Graphics, Inc., and * + * are protected by Federal copyright law. They may not be disclosed * + * to third parties or copied or duplicated in any form, in whole or * + * in part, without the prior written consent of Silicon Graphics, Inc. * + * * + **************************************************************************/ + +#ifndef _SHUB_MD_H +#define _SHUB_MD_H + +/* SN2 supports a mostly-flat address space with 4 CPU-visible, evenly spaced, + contiguous regions, or "software banks". On SN2, software bank n begins at + addresses n * 16GB, 0 <= n < 4. Each bank has a 16GB address space. If + the 4 dimms do not use up this space there will be holes between the + banks. Even with these holes the whole memory space within a bank is + not addressable address space. The top 1/32 of each bank is directory + memory space and is accessible through bist only. + + Physically a SN2 node board contains 2 daughter cards with 8 dimm sockets + each. A total of 16 dimm sockets arranged as 4 "DIMM banks" of 4 dimms + each. The data is stripped across the 4 memory busses so all dimms within + a dimm bank must have identical capacity dimms. Memory is increased or + decreased in sets of 4. Each dimm bank has 2 dimms on each side. + + Physical Dimm Bank layout. + DTR Card0 + ------------ + Dimm Bank 3 | MemYL3 | CS 3 + | MemXL3 | + |----------| + Dimm Bank 2 | MemYL2 | CS 2 + | MemXL2 | + |----------| + Dimm Bank 1 | MemYL1 | CS 1 + | MemXL1 | + |----------| + Dimm Bank 0 | MemYL0 | CS 0 + | MemXL0 | + ------------ + | | + BUS BUS + XL YL + | | + ------------ + | SHUB | + | MD | + ------------ + | | + BUS BUS + XR YR + | | + ------------ + Dimm Bank 0 | MemXR0 | CS 0 + | MemYR0 | + |----------| + Dimm Bank 1 | MemXR1 | CS 1 + | MemYR1 | + |----------| + Dimm Bank 2 | MemXR2 | CS 2 + | MemYR2 | + |----------| + Dimm Bank 3 | MemXR3 | CS 3 + | MemYR3 | + ------------ + DTR Card1 + + The dimms can be 1 or 2 sided dimms. The size and bankness is defined + separately for each dimm bank in the sh_[x,y,jnr]_dimm_cfg MMR register. + + Normally software bank 0 would map directly to physical dimm bank 0. The + software banks can map to the different physical dimm banks via the + DIMM[0-3]_CS field in SH_[x,y,jnr]_DIMM_CFG for each dimm slot. + + All the PROM's data structures (promlog variables, klconfig, etc.) + track memory by the physical dimm bank number. The kernel usually + tracks memory by the software bank number. + + */ + + +/* Preprocessor macros */ +#define MD_MEM_BANKS 4 +#define MD_PHYS_BANKS_PER_DIMM 2 /* dimms may be 2 sided. */ +#define MD_NUM_PHYS_BANKS (MD_MEM_BANKS * MD_PHYS_BANKS_PER_DIMM) +#define MD_DIMMS_IN_SLOT 4 /* 4 dimms in each dimm bank. aka slot */ + +/* Address bits 35,34 control dimm bank access. */ +#define MD_BANK_SHFT 34 +#define MD_BANK_MASK (UINT64_CAST 0x3 << MD_BANK_SHFT ) +#define MD_BANK_GET(addr) (((addr) & MD_BANK_MASK) >> MD_BANK_SHFT) +#define MD_BANK_SIZE (UINT64_CAST 0x1 << MD_BANK_SHFT ) /* 16 gb */ +#define MD_BANK_OFFSET(_b) (UINT64_CAST (_b) << MD_BANK_SHFT) + +/*Address bit 12 selects side of dimm if 2bnk dimms present. */ +#define MD_PHYS_BANK_SEL_SHFT 12 +#define MD_PHYS_BANK_SEL_MASK (UINT64_CAST 0x1 << MD_PHYS_BANK_SEL_SHFT) + +/* Address bit 7 determines if data resides on X or Y memory system. + * If addr Bit 7 is set the data resides on Y memory system and + * the corresponing directory entry reside on the X. + */ +#define MD_X_OR_Y_SEL_SHFT 7 +#define MD_X_OR_Y_SEL_MASK (1 << MD_X_OR_Y_SEL_SHFT) + +/* Address bit 8 determines which directory entry of the pair the address + * corresponds to. If addr Bit 8 is set DirB corresponds to the memory address. + */ +#define MD_DIRA_OR_DIRB_SEL_SHFT 8 +#define MD_DIRA_OR_DIRB_SEL_MASK (1 << MD_DIRA_OR_DIRB_SEL_SHFT) + +/* Address bit 11 determines if corresponding directory entry resides + * on Left or Right memory bus. If addr Bit 11 is set the corresponding + * directory entry resides on Right memory bus. + */ +#define MD_L_OR_R_SEL_SHFT 11 +#define MD_L_OR_R_SEL_MASK (1 << MD_L_OR_R_SEL_SHFT) + +/* DRAM sizes. */ +#define MD_SZ_64_Mb 0x0 +#define MD_SZ_128_Mb 0x1 +#define MD_SZ_256_Mb 0x2 +#define MD_SZ_512_Mb 0x3 +#define MD_SZ_1024_Mb 0x4 +#define MD_SZ_2048_Mb 0x5 +#define MD_SZ_UNUSED 0x7 + +#define MD_DIMM_SIZE_BYTES(_size, _2bk) ( \ + ( (_size) == 7 ? 0 : ( 0x4000000L << (_size)) << (_2bk)))\ + +#define MD_DIMM_SIZE_MBYTES(_size, _2bk) ( \ + ( (_size) == 7 ? 0 : ( 0x40L << (_size) ) << (_2bk))) \ + +/* The top 1/32 of each bank is directory memory, and not accessable + * via normal reads and writes */ +#define MD_DIMM_USER_SIZE(_size) ((_size) * 31 / 32) + +/* Minimum size of a populated bank is 64M (62M usable) */ +#define MIN_BANK_SIZE MD_DIMM_USER_SIZE((64 * 0x100000)) +#define MIN_BANK_STRING "62" + + +/*Possible values for FREQ field in sh_[x,y,jnr]_dimm_cfg regs */ +#define MD_DIMM_100_CL2_0 0x0 +#define MD_DIMM_133_CL2_0 0x1 +#define MD_DIMM_133_CL2_5 0x2 +#define MD_DIMM_160_CL2_0 0x3 +#define MD_DIMM_160_CL2_5 0x4 +#define MD_DIMM_160_CL3_0 0x5 +#define MD_DIMM_200_CL2_0 0x6 +#define MD_DIMM_200_CL2_5 0x7 +#define MD_DIMM_200_CL3_0 0x8 + +/* DIMM_CFG fields */ +#define MD_DIMM_SHFT(_dimm) ((_dimm) << 3) +#define MD_DIMM_SIZE_MASK(_dimm) \ + (SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK << \ + (MD_DIMM_SHFT(_dimm))) + +#define MD_DIMM_2BK_MASK(_dimm) \ + (SH_JNR_DIMM_CFG_DIMM0_2BK_MASK << \ + MD_DIMM_SHFT(_dimm)) + +#define MD_DIMM_REV_MASK(_dimm) \ + (SH_JNR_DIMM_CFG_DIMM0_REV_MASK << \ + MD_DIMM_SHFT(_dimm)) + +#define MD_DIMM_CS_MASK(_dimm) \ + (SH_JNR_DIMM_CFG_DIMM0_CS_MASK << \ + MD_DIMM_SHFT(_dimm)) + +#define MD_DIMM_SIZE(_dimm, _cfg) \ + (((_cfg) & MD_DIMM_SIZE_MASK(_dimm)) \ + >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT)) + +#define MD_DIMM_TWO_SIDED(_dimm,_cfg) \ + ( ((_cfg) & MD_DIMM_2BK_MASK(_dimm)) \ + >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT)) + +#define MD_DIMM_REVERSED(_dimm,_cfg) \ + (((_cfg) & MD_DIMM_REV_MASK(_dimm)) \ + >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_REV_SHFT)) + +#define MD_DIMM_CS(_dimm,_cfg) \ + (((_cfg) & MD_DIMM_CS_MASK(_dimm)) \ + >> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_CS_SHFT)) + + + +/* Macros to set MMRs that must be set identically to others. */ +#define MD_SET_DIMM_CFG(_n, _value) { \ + REMOTE_HUB_S(_n, SH_X_DIMM_CFG,_value); \ + REMOTE_HUB_S(_n, SH_Y_DIMM_CFG, _value); \ + REMOTE_HUB_S(_n, SH_JNR_DIMM_CFG, _value);} + +#define MD_SET_DQCT_CFG(_n, _value) { \ + REMOTE_HUB_S(_n, SH_X_DQCT_CFG,_value); \ + REMOTE_HUB_S(_n, SH_Y_DQCT_CFG,_value); } + +#define MD_SET_CFG(_n, _value) { \ + REMOTE_HUB_S(_n, SH_X_CFG,_value); \ + REMOTE_HUB_S(_n, SH_Y_CFG,_value);} + +#define MD_SET_REFRESH_CONTROL(_n, _value) { \ + REMOTE_HUB_S(_n, SH_X_REFRESH_CONTROL, _value); \ + REMOTE_HUB_S(_n, SH_Y_REFRESH_CONTROL, _value);} + +#define MD_SET_DQ_MMR_DIR_COFIG(_n, _value) { \ + REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_CONFIG, _value); \ + REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_CONFIG, _value);} + +#define MD_SET_PIOWD_DIR_ENTRYS(_n, _value) { \ + REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY, _value);\ + REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY, _value);} + +/* + * There are 12 Node Presence MMRs, 4 in each primary DQ and 4 in the + * LB. The data in the left and right DQ MMRs and the LB must match. + */ +#define MD_SET_PRESENT_VEC(_n, _vec, _value) { \ + REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRESVEC0+((_vec)*0x10),\ + _value); \ + REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRESVEC0+((_vec)*0x10),\ + _value); \ + REMOTE_HUB_S(_n, SH_SHUBS_PRESENT0+((_vec)*0x80), _value);} +/* + * There are 16 Privilege Vector MMRs, 8 in each primary DQ. The data + * in the corresponding left and right DQ MMRs must match. Each MMR + * pair is used for a single partition. + */ +#define MD_SET_PRI_VEC(_n, _vec, _value) { \ + REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRIVEC0+((_vec)*0x10),\ + _value); \ + REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRIVEC0+((_vec)*0x10),\ + _value);} +/* + * There are 16 Local/Remote MMRs, 8 in each primary DQ. The data in + * the corresponding left and right DQ MMRs must match. Each MMR pair + * is used for a single partition. + */ +#define MD_SET_LOC_VEC(_n, _vec, _value) { \ + REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_LOCVEC0+((_vec)*0x10),\ + _value); \ + REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_LOCVEC0+((_vec)*0x10),\ + _value);} + +/* Memory BIST CMDS */ +#define MD_DIMM_INIT_MODE_SET 0x0 +#define MD_DIMM_INIT_REFRESH 0x1 +#define MD_DIMM_INIT_PRECHARGE 0x2 +#define MD_DIMM_INIT_BURST_TERM 0x6 +#define MD_DIMM_INIT_NOP 0x7 +#define MD_DIMM_BIST_READ 0x10 +#define MD_FILL_DIR 0x20 +#define MD_FILL_DATA 0x30 +#define MD_FILL_DIR_ACCESS 0X40 +#define MD_READ_DIR_PAIR 0x50 +#define MD_READ_DIR_TAG 0x60 + +/* SH_MMRBIST_CTL macros */ +#define MD_BIST_FAIL(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \ + SH_MMRBIST_CTL_FAIL_MASK) + +#define MD_BIST_IN_PROGRESS(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \ + SH_MMRBIST_CTL_IN_PROGRESS_MASK) + +#define MD_BIST_MEM_IDLE(_n); (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & \ + SH_MMRBIST_CTL_MEM_IDLE_MASK) + +/* SH_MMRBIST_ERR macros */ +#define MD_BIST_MISCOMPARE(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_ERR) & \ + SH_MMRBIST_ERR_DETECTED_MASK) + +#endif /* _SHUB_MD_H */ diff --git a/include/asm-ia64/sn/sn2/shub_mmr.h b/include/asm-ia64/sn/sn2/shub_mmr.h new file mode 100644 index 000000000000..74ea3a961ad7 --- /dev/null +++ b/include/asm-ia64/sn/sn2/shub_mmr.h @@ -0,0 +1,31597 @@ +/* + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2001 Silicon Graphics, Inc. All rights reserved. + */ + + +#ifndef _ASM_IA64_SN_SN2_SHUB_MMR_H +#define _ASM_IA64_SN_SN2_SHUB_MMR_H + +/* ==================================================================== */ +/* Register "SH_FSB_BINIT_CONTROL" */ +/* FSB BINIT# Control */ +/* ==================================================================== */ + +#define SH_FSB_BINIT_CONTROL 0x0000000120010000 +#define SH_FSB_BINIT_CONTROL_MASK 0x0000000000000001 +#define SH_FSB_BINIT_CONTROL_INIT 0x0000000000000000 + +/* SH_FSB_BINIT_CONTROL_BINIT */ +/* Description: Assert the FSB's BINIT# Signal */ +#define SH_FSB_BINIT_CONTROL_BINIT_SHFT 0 +#define SH_FSB_BINIT_CONTROL_BINIT_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_FSB_RESET_CONTROL" */ +/* FSB Reset Control */ +/* ==================================================================== */ + +#define SH_FSB_RESET_CONTROL 0x0000000120010080 +#define SH_FSB_RESET_CONTROL_MASK 0x0000000000000001 +#define SH_FSB_RESET_CONTROL_INIT 0x0000000000000000 + +/* SH_FSB_RESET_CONTROL_RESET */ +/* Description: Assert the FSB's RESET# Signal */ +#define SH_FSB_RESET_CONTROL_RESET_SHFT 0 +#define SH_FSB_RESET_CONTROL_RESET_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_FSB_SYSTEM_AGENT_CONFIG" */ +/* FSB System Agent Configuration */ +/* ==================================================================== */ + +#define SH_FSB_SYSTEM_AGENT_CONFIG 0x0000000120010100 +#define SH_FSB_SYSTEM_AGENT_CONFIG_MASK 0x00003fff0187fff9 +#define SH_FSB_SYSTEM_AGENT_CONFIG_INIT 0x0000000000000000 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN */ +/* Description: RCNT/SCNT Assertion Enabled */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_SHFT 0 +#define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_MASK 0x0000000000000001 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN */ +/* Description: BERR Assertion Enabled for Bus Errors */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_SHFT 3 +#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_MASK 0x0000000000000008 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN */ +/* Description: BERR Sampling Enabled */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_SHFT 4 +#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_MASK 0x0000000000000010 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN */ +/* Description: BINIT Assertion Enabled */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_SHFT 5 +#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_MASK 0x0000000000000020 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN */ +/* Description: stutter FSB request assertion */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_SHFT 6 +#define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_MASK 0x0000000000000040 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN */ +/* Description: use short duration hang timeout */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_SHFT 7 +#define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_MASK 0x0000000000000080 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA */ +/* Description: Interrupt Acknowledge Response Data */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_SHFT 8 +#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_MASK 0x000000000000ff00 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP */ +/* Description: IO Transaction Response */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_SHFT 16 +#define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_MASK 0x0000000000010000 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP */ +/* Description: External Task Priority Register (xTPR) Transaction */ +/* Response */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_SHFT 17 +#define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_MASK 0x0000000000020000 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP */ +/* Description: Interrupt Acknowledge Transaction Response */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_SHFT 18 +#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_MASK 0x0000000000040000 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_TDOT */ +/* Description: Throttle Data-bus Ownership Transitions */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_SHFT 23 +#define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_MASK 0x0000000000800000 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN */ +/* Description: serialize processor transactions */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_SHFT 24 +#define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_MASK 0x0000000001000000 + +/* SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES */ +/* Description: FSB error binit enables */ +#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_SHFT 32 +#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_MASK 0x00003fff00000000 + +/* ==================================================================== */ +/* Register "SH_FSB_VGA_REMAP" */ +/* FSB VGA Address Space Remap */ +/* ==================================================================== */ + +#define SH_FSB_VGA_REMAP 0x0000000120010180 +#define SH_FSB_VGA_REMAP_MASK 0x4001fffffffe0000 +#define SH_FSB_VGA_REMAP_INIT 0x0000000000000000 + +/* SH_FSB_VGA_REMAP_OFFSET */ +/* Description: VGA Remap Node Offset */ +#define SH_FSB_VGA_REMAP_OFFSET_SHFT 17 +#define SH_FSB_VGA_REMAP_OFFSET_MASK 0x0000000ffffe0000 + +/* SH_FSB_VGA_REMAP_ASID */ +/* Description: VGA Remap Address Space ID */ +#define SH_FSB_VGA_REMAP_ASID_SHFT 36 +#define SH_FSB_VGA_REMAP_ASID_MASK 0x0000003000000000 + +/* SH_FSB_VGA_REMAP_NID */ +/* Description: VGA Remap Node ID */ +#define SH_FSB_VGA_REMAP_NID_SHFT 38 +#define SH_FSB_VGA_REMAP_NID_MASK 0x0001ffc000000000 + +/* SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED */ +/* Description: VGA Remapping Enabled */ +#define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_SHFT 62 +#define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_FSB_RESET_STATUS" */ +/* FSB Reset Status */ +/* ==================================================================== */ + +#define SH_FSB_RESET_STATUS 0x0000000120020000 +#define SH_FSB_RESET_STATUS_MASK 0x0000000000000001 +#define SH_FSB_RESET_STATUS_INIT 0x0000000000000000 + +/* SH_FSB_RESET_STATUS_RESET_IN_PROGRESS */ +/* Description: Reset in Progress */ +#define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_SHFT 0 +#define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_FSB_SYMMETRIC_AGENT_STATUS" */ +/* FSB Symmetric Agent Status */ +/* ==================================================================== */ + +#define SH_FSB_SYMMETRIC_AGENT_STATUS 0x0000000120020080 +#define SH_FSB_SYMMETRIC_AGENT_STATUS_MASK 0x0000000000000007 +#define SH_FSB_SYMMETRIC_AGENT_STATUS_INIT 0x0000000000000000 + +/* SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE */ +/* Description: CPU 0 Active. */ +#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_SHFT 0 +#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_MASK 0x0000000000000001 + +/* SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE */ +/* Description: CPU 1 Active. */ +#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_SHFT 1 +#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_MASK 0x0000000000000002 + +/* SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY */ +/* Description: The Processors are Ready */ +#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_SHFT 2 +#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_MASK 0x0000000000000004 + +/* ==================================================================== */ +/* Register "SH_GFX_CREDIT_COUNT_0" */ +/* Graphics-write Credit Count for CPU 0 */ +/* ==================================================================== */ + +#define SH_GFX_CREDIT_COUNT_0 0x0000000120030000 +#define SH_GFX_CREDIT_COUNT_0_MASK 0x80000000000fffff +#define SH_GFX_CREDIT_COUNT_0_INIT 0x000000000000003f + +/* SH_GFX_CREDIT_COUNT_0_COUNT */ +/* Description: Credit Count */ +#define SH_GFX_CREDIT_COUNT_0_COUNT_SHFT 0 +#define SH_GFX_CREDIT_COUNT_0_COUNT_MASK 0x00000000000fffff + +/* SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE */ +/* Description: Reset GFX state */ +#define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_SHFT 63 +#define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_GFX_CREDIT_COUNT_1" */ +/* Graphics-write Credit Count for CPU 1 */ +/* ==================================================================== */ + +#define SH_GFX_CREDIT_COUNT_1 0x0000000120030080 +#define SH_GFX_CREDIT_COUNT_1_MASK 0x80000000000fffff +#define SH_GFX_CREDIT_COUNT_1_INIT 0x000000000000003f + +/* SH_GFX_CREDIT_COUNT_1_COUNT */ +/* Description: Credit Count */ +#define SH_GFX_CREDIT_COUNT_1_COUNT_SHFT 0 +#define SH_GFX_CREDIT_COUNT_1_COUNT_MASK 0x00000000000fffff + +/* SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE */ +/* Description: Reset GFX state */ +#define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_SHFT 63 +#define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_GFX_MODE_CNTRL_0" */ +/* Graphics credit mode amd message ordering for CPU 0 */ +/* ==================================================================== */ + +#define SH_GFX_MODE_CNTRL_0 0x0000000120030100 +#define SH_GFX_MODE_CNTRL_0_MASK 0x0000000000000007 +#define SH_GFX_MODE_CNTRL_0_INIT 0x0000000000000003 + +/* SH_GFX_MODE_CNTRL_0_DWORD_CREDITS */ +/* Description: GFX credits are tracked by D-words */ +#define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_SHFT 0 +#define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_MASK 0x0000000000000001 + +/* SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS */ +/* Description: GFX credits are tracked by D-words and messages */ +#define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_SHFT 1 +#define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_MASK 0x0000000000000002 + +/* SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING */ +/* Description: GFX message routing order */ +#define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_SHFT 2 +#define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_MASK 0x0000000000000004 + +/* ==================================================================== */ +/* Register "SH_GFX_MODE_CNTRL_1" */ +/* Graphics credit mode amd message ordering for CPU 1 */ +/* ==================================================================== */ + +#define SH_GFX_MODE_CNTRL_1 0x0000000120030180 +#define SH_GFX_MODE_CNTRL_1_MASK 0x0000000000000007 +#define SH_GFX_MODE_CNTRL_1_INIT 0x0000000000000003 + +/* SH_GFX_MODE_CNTRL_1_DWORD_CREDITS */ +/* Description: GFX credits are tracked by D-words */ +#define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_SHFT 0 +#define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_MASK 0x0000000000000001 + +/* SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS */ +/* Description: GFX credits are tracked by D-words and messages */ +#define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_SHFT 1 +#define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_MASK 0x0000000000000002 + +/* SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING */ +/* Description: GFX message routing order */ +#define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_SHFT 2 +#define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_MASK 0x0000000000000004 + +/* ==================================================================== */ +/* Register "SH_GFX_SKID_CREDIT_COUNT_0" */ +/* Graphics-write Skid Credit Count for CPU 0 */ +/* ==================================================================== */ + +#define SH_GFX_SKID_CREDIT_COUNT_0 0x0000000120030200 +#define SH_GFX_SKID_CREDIT_COUNT_0_MASK 0x00000000000fffff +#define SH_GFX_SKID_CREDIT_COUNT_0_INIT 0x0000000000000030 + +/* SH_GFX_SKID_CREDIT_COUNT_0_SKID */ +/* Description: Skid Credit Count */ +#define SH_GFX_SKID_CREDIT_COUNT_0_SKID_SHFT 0 +#define SH_GFX_SKID_CREDIT_COUNT_0_SKID_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_GFX_SKID_CREDIT_COUNT_1" */ +/* Graphics-write Skid Credit Count for CPU 1 */ +/* ==================================================================== */ + +#define SH_GFX_SKID_CREDIT_COUNT_1 0x0000000120030280 +#define SH_GFX_SKID_CREDIT_COUNT_1_MASK 0x00000000000fffff +#define SH_GFX_SKID_CREDIT_COUNT_1_INIT 0x0000000000000030 + +/* SH_GFX_SKID_CREDIT_COUNT_1_SKID */ +/* Description: Skid Credit Count */ +#define SH_GFX_SKID_CREDIT_COUNT_1_SKID_SHFT 0 +#define SH_GFX_SKID_CREDIT_COUNT_1_SKID_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_GFX_STALL_LIMIT_0" */ +/* Graphics-write Stall Limit for CPU 0 */ +/* ==================================================================== */ + +#define SH_GFX_STALL_LIMIT_0 0x0000000120030300 +#define SH_GFX_STALL_LIMIT_0_MASK 0x0000000003ffffff +#define SH_GFX_STALL_LIMIT_0_INIT 0x0000000000010000 + +/* SH_GFX_STALL_LIMIT_0_LIMIT */ +/* Description: Graphics Stall Limit for CPU 0 */ +#define SH_GFX_STALL_LIMIT_0_LIMIT_SHFT 0 +#define SH_GFX_STALL_LIMIT_0_LIMIT_MASK 0x0000000003ffffff + +/* ==================================================================== */ +/* Register "SH_GFX_STALL_LIMIT_1" */ +/* Graphics-write Stall Limit for CPU 1 */ +/* ==================================================================== */ + +#define SH_GFX_STALL_LIMIT_1 0x0000000120030380 +#define SH_GFX_STALL_LIMIT_1_MASK 0x0000000003ffffff +#define SH_GFX_STALL_LIMIT_1_INIT 0x0000000000010000 + +/* SH_GFX_STALL_LIMIT_1_LIMIT */ +/* Description: Graphics Stall Limit for CPU 1 */ +#define SH_GFX_STALL_LIMIT_1_LIMIT_SHFT 0 +#define SH_GFX_STALL_LIMIT_1_LIMIT_MASK 0x0000000003ffffff + +/* ==================================================================== */ +/* Register "SH_GFX_STALL_TIMER_0" */ +/* Graphics-write Stall Timer for CPU 0 */ +/* ==================================================================== */ + +#define SH_GFX_STALL_TIMER_0 0x0000000120030400 +#define SH_GFX_STALL_TIMER_0_MASK 0x0000000003ffffff +#define SH_GFX_STALL_TIMER_0_INIT 0x0000000000000000 + +/* SH_GFX_STALL_TIMER_0_TIMER_VALUE */ +/* Description: Timer Value */ +#define SH_GFX_STALL_TIMER_0_TIMER_VALUE_SHFT 0 +#define SH_GFX_STALL_TIMER_0_TIMER_VALUE_MASK 0x0000000003ffffff + +/* ==================================================================== */ +/* Register "SH_GFX_STALL_TIMER_1" */ +/* Graphics-write Stall Timer for CPU 1 */ +/* ==================================================================== */ + +#define SH_GFX_STALL_TIMER_1 0x0000000120030480 +#define SH_GFX_STALL_TIMER_1_MASK 0x0000000003ffffff +#define SH_GFX_STALL_TIMER_1_INIT 0x0000000000000000 + +/* SH_GFX_STALL_TIMER_1_TIMER_VALUE */ +/* Description: Timer Value */ +#define SH_GFX_STALL_TIMER_1_TIMER_VALUE_SHFT 0 +#define SH_GFX_STALL_TIMER_1_TIMER_VALUE_MASK 0x0000000003ffffff + +/* ==================================================================== */ +/* Register "SH_GFX_WINDOW_0" */ +/* Graphics-write Window for CPU 0 */ +/* ==================================================================== */ + +#define SH_GFX_WINDOW_0 0x0000000120030500 +#define SH_GFX_WINDOW_0_MASK 0x8000000fff000000 +#define SH_GFX_WINDOW_0_INIT 0x0000000000000000 + +/* SH_GFX_WINDOW_0_BASE_ADDR */ +/* Description: Base Address for CPU 0's 16 MB Graphics Window */ +#define SH_GFX_WINDOW_0_BASE_ADDR_SHFT 24 +#define SH_GFX_WINDOW_0_BASE_ADDR_MASK 0x0000000fff000000 + +/* SH_GFX_WINDOW_0_GFX_WINDOW_EN */ +/* Description: Graphics Window Enabled */ +#define SH_GFX_WINDOW_0_GFX_WINDOW_EN_SHFT 63 +#define SH_GFX_WINDOW_0_GFX_WINDOW_EN_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_GFX_WINDOW_1" */ +/* Graphics-write Window for CPU 1 */ +/* ==================================================================== */ + +#define SH_GFX_WINDOW_1 0x0000000120030580 +#define SH_GFX_WINDOW_1_MASK 0x8000000fff000000 +#define SH_GFX_WINDOW_1_INIT 0x0000000000000000 + +/* SH_GFX_WINDOW_1_BASE_ADDR */ +/* Description: Base Address for CPU 1's 16 MB Graphics Window */ +#define SH_GFX_WINDOW_1_BASE_ADDR_SHFT 24 +#define SH_GFX_WINDOW_1_BASE_ADDR_MASK 0x0000000fff000000 + +/* SH_GFX_WINDOW_1_GFX_WINDOW_EN */ +/* Description: Graphics Window Enabled */ +#define SH_GFX_WINDOW_1_GFX_WINDOW_EN_SHFT 63 +#define SH_GFX_WINDOW_1_GFX_WINDOW_EN_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0" */ +/* Graphics-write Interrupt Limit for CPU 0 */ +/* ==================================================================== */ + +#define SH_GFX_INTERRUPT_TIMER_LIMIT_0 0x0000000120030600 +#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_MASK 0x00000000000000ff +#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INIT 0x0000000000000040 + +/* SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT */ +/* Description: GFX Interrupt Timer Limit */ +#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_SHFT 0 +#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1" */ +/* Graphics-write Interrupt Limit for CPU 1 */ +/* ==================================================================== */ + +#define SH_GFX_INTERRUPT_TIMER_LIMIT_1 0x0000000120030680 +#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_MASK 0x00000000000000ff +#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INIT 0x0000000000000040 + +/* SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT */ +/* Description: GFX Interrupt Timer Limit */ +#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_SHFT 0 +#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_GFX_WRITE_STATUS_0" */ +/* Graphics Write Status for CPU 0 */ +/* ==================================================================== */ + +#define SH_GFX_WRITE_STATUS_0 0x0000000120040000 +#define SH_GFX_WRITE_STATUS_0_MASK 0x8000000000000001 +#define SH_GFX_WRITE_STATUS_0_INIT 0x0000000000000000 + +/* SH_GFX_WRITE_STATUS_0_BUSY */ +/* Description: Busy */ +#define SH_GFX_WRITE_STATUS_0_BUSY_SHFT 0 +#define SH_GFX_WRITE_STATUS_0_BUSY_MASK 0x0000000000000001 + +/* SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL */ +/* Description: Re-enable GFX stall logic for this processor */ +#define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_SHFT 63 +#define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_GFX_WRITE_STATUS_1" */ +/* Graphics Write Status for CPU 1 */ +/* ==================================================================== */ + +#define SH_GFX_WRITE_STATUS_1 0x0000000120040080 +#define SH_GFX_WRITE_STATUS_1_MASK 0x8000000000000001 +#define SH_GFX_WRITE_STATUS_1_INIT 0x0000000000000000 + +/* SH_GFX_WRITE_STATUS_1_BUSY */ +/* Description: Busy */ +#define SH_GFX_WRITE_STATUS_1_BUSY_SHFT 0 +#define SH_GFX_WRITE_STATUS_1_BUSY_MASK 0x0000000000000001 + +/* SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL */ +/* Description: Re-enable GFX stall logic for this processor */ +#define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_SHFT 63 +#define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_II_INT0" */ +/* SHub II Interrupt 0 Registers */ +/* ==================================================================== */ + +#define SH_II_INT0 0x0000000110000000 +#define SH_II_INT0_MASK 0x00000000000001ff +#define SH_II_INT0_INIT 0x0000000000000000 + +/* SH_II_INT0_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_II_INT0_IDX_SHFT 0 +#define SH_II_INT0_IDX_MASK 0x00000000000000ff + +/* SH_II_INT0_SEND */ +/* Description: Send Interrupt Message to PI, This generates a puls */ +#define SH_II_INT0_SEND_SHFT 8 +#define SH_II_INT0_SEND_MASK 0x0000000000000100 + +/* ==================================================================== */ +/* Register "SH_II_INT0_CONFIG" */ +/* SHub II Interrupt 0 Config Registers */ +/* ==================================================================== */ + +#define SH_II_INT0_CONFIG 0x0000000110000080 +#define SH_II_INT0_CONFIG_MASK 0x0003ffffffefffff +#define SH_II_INT0_CONFIG_INIT 0x0000000000000000 + +/* SH_II_INT0_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_II_INT0_CONFIG_TYPE_SHFT 0 +#define SH_II_INT0_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_II_INT0_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_II_INT0_CONFIG_AGT_SHFT 3 +#define SH_II_INT0_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_II_INT0_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_II_INT0_CONFIG_PID_SHFT 4 +#define SH_II_INT0_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_II_INT0_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_II_INT0_CONFIG_BASE_SHFT 21 +#define SH_II_INT0_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* ==================================================================== */ +/* Register "SH_II_INT0_ENABLE" */ +/* SHub II Interrupt 0 Enable Registers */ +/* ==================================================================== */ + +#define SH_II_INT0_ENABLE 0x0000000110000200 +#define SH_II_INT0_ENABLE_MASK 0x0000000000000001 +#define SH_II_INT0_ENABLE_INIT 0x0000000000000000 + +/* SH_II_INT0_ENABLE_II_ENABLE */ +/* Description: Enable II Interrupt */ +#define SH_II_INT0_ENABLE_II_ENABLE_SHFT 0 +#define SH_II_INT0_ENABLE_II_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_II_INT1" */ +/* SHub II Interrupt 1 Registers */ +/* ==================================================================== */ + +#define SH_II_INT1 0x0000000110000100 +#define SH_II_INT1_MASK 0x00000000000001ff +#define SH_II_INT1_INIT 0x0000000000000000 + +/* SH_II_INT1_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_II_INT1_IDX_SHFT 0 +#define SH_II_INT1_IDX_MASK 0x00000000000000ff + +/* SH_II_INT1_SEND */ +/* Description: Send Interrupt Message to PI, This generates a puls */ +#define SH_II_INT1_SEND_SHFT 8 +#define SH_II_INT1_SEND_MASK 0x0000000000000100 + +/* ==================================================================== */ +/* Register "SH_II_INT1_CONFIG" */ +/* SHub II Interrupt 1 Config Registers */ +/* ==================================================================== */ + +#define SH_II_INT1_CONFIG 0x0000000110000180 +#define SH_II_INT1_CONFIG_MASK 0x0003ffffffefffff +#define SH_II_INT1_CONFIG_INIT 0x0000000000000000 + +/* SH_II_INT1_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_II_INT1_CONFIG_TYPE_SHFT 0 +#define SH_II_INT1_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_II_INT1_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_II_INT1_CONFIG_AGT_SHFT 3 +#define SH_II_INT1_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_II_INT1_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_II_INT1_CONFIG_PID_SHFT 4 +#define SH_II_INT1_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_II_INT1_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_II_INT1_CONFIG_BASE_SHFT 21 +#define SH_II_INT1_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* ==================================================================== */ +/* Register "SH_II_INT1_ENABLE" */ +/* SHub II Interrupt 1 Enable Registers */ +/* ==================================================================== */ + +#define SH_II_INT1_ENABLE 0x0000000110000280 +#define SH_II_INT1_ENABLE_MASK 0x0000000000000001 +#define SH_II_INT1_ENABLE_INIT 0x0000000000000000 + +/* SH_II_INT1_ENABLE_II_ENABLE */ +/* Description: Enable II 1 Interrupt */ +#define SH_II_INT1_ENABLE_II_ENABLE_SHFT 0 +#define SH_II_INT1_ENABLE_II_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_INT_NODE_ID_CONFIG" */ +/* SHub Interrupt Node ID Configuration */ +/* ==================================================================== */ + +#define SH_INT_NODE_ID_CONFIG 0x0000000110000300 +#define SH_INT_NODE_ID_CONFIG_MASK 0x0000000000000fff +#define SH_INT_NODE_ID_CONFIG_INIT 0x0000000000000000 + +/* SH_INT_NODE_ID_CONFIG_NODE_ID */ +/* Description: Node ID for interrupt messages */ +#define SH_INT_NODE_ID_CONFIG_NODE_ID_SHFT 0 +#define SH_INT_NODE_ID_CONFIG_NODE_ID_MASK 0x00000000000007ff + +/* SH_INT_NODE_ID_CONFIG_ID_SEL */ +/* Description: Select node id for interrupt messages */ +#define SH_INT_NODE_ID_CONFIG_ID_SEL_SHFT 11 +#define SH_INT_NODE_ID_CONFIG_ID_SEL_MASK 0x0000000000000800 + +/* ==================================================================== */ +/* Register "SH_IPI_INT" */ +/* SHub Inter-Processor Interrupt Registers */ +/* ==================================================================== */ + +#define SH_IPI_INT 0x0000000110000380 +#define SH_IPI_INT_MASK 0x8ff3ffffffefffff +#define SH_IPI_INT_INIT 0x0000000000000000 + +/* SH_IPI_INT_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_IPI_INT_TYPE_SHFT 0 +#define SH_IPI_INT_TYPE_MASK 0x0000000000000007 + +/* SH_IPI_INT_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_IPI_INT_AGT_SHFT 3 +#define SH_IPI_INT_AGT_MASK 0x0000000000000008 + +/* SH_IPI_INT_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_IPI_INT_PID_SHFT 4 +#define SH_IPI_INT_PID_MASK 0x00000000000ffff0 + +/* SH_IPI_INT_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_IPI_INT_BASE_SHFT 21 +#define SH_IPI_INT_BASE_MASK 0x0003ffffffe00000 + +/* SH_IPI_INT_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_IPI_INT_IDX_SHFT 52 +#define SH_IPI_INT_IDX_MASK 0x0ff0000000000000 + +/* SH_IPI_INT_SEND */ +/* Description: Send Interrupt Message to PI, This generates a puls */ +#define SH_IPI_INT_SEND_SHFT 63 +#define SH_IPI_INT_SEND_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_IPI_INT_ENABLE" */ +/* SHub Inter-Processor Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_IPI_INT_ENABLE 0x0000000110000400 +#define SH_IPI_INT_ENABLE_MASK 0x0000000000000001 +#define SH_IPI_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_IPI_INT_ENABLE_PIO_ENABLE */ +/* Description: Enable PIO Interrupt */ +#define SH_IPI_INT_ENABLE_PIO_ENABLE_SHFT 0 +#define SH_IPI_INT_ENABLE_PIO_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT0_CONFIG" */ +/* SHub Local Interrupt 0 Registers */ +/* ==================================================================== */ + +#define SH_LOCAL_INT0_CONFIG 0x0000000110000480 +#define SH_LOCAL_INT0_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_LOCAL_INT0_CONFIG_INIT 0x0000000000000000 + +/* SH_LOCAL_INT0_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_LOCAL_INT0_CONFIG_TYPE_SHFT 0 +#define SH_LOCAL_INT0_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_LOCAL_INT0_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_LOCAL_INT0_CONFIG_AGT_SHFT 3 +#define SH_LOCAL_INT0_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT0_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_LOCAL_INT0_CONFIG_PID_SHFT 4 +#define SH_LOCAL_INT0_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_LOCAL_INT0_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_LOCAL_INT0_CONFIG_BASE_SHFT 21 +#define SH_LOCAL_INT0_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_LOCAL_INT0_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_LOCAL_INT0_CONFIG_IDX_SHFT 52 +#define SH_LOCAL_INT0_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT0_ENABLE" */ +/* SHub Local Interrupt 0 Enable */ +/* ==================================================================== */ + +#define SH_LOCAL_INT0_ENABLE 0x0000000110000500 +#define SH_LOCAL_INT0_ENABLE_MASK 0x000000000000f7ff +#define SH_LOCAL_INT0_ENABLE_INIT 0x0000000000000000 + +/* SH_LOCAL_INT0_ENABLE_PI_HW_INT */ +/* Description: Enable PI Hardware interrupt */ +#define SH_LOCAL_INT0_ENABLE_PI_HW_INT_SHFT 0 +#define SH_LOCAL_INT0_ENABLE_PI_HW_INT_MASK 0x0000000000000001 + +/* SH_LOCAL_INT0_ENABLE_MD_HW_INT */ +/* Description: Enable MD Hardware interrupt */ +#define SH_LOCAL_INT0_ENABLE_MD_HW_INT_SHFT 1 +#define SH_LOCAL_INT0_ENABLE_MD_HW_INT_MASK 0x0000000000000002 + +/* SH_LOCAL_INT0_ENABLE_XN_HW_INT */ +/* Description: Enable XN Hardware interrupt */ +#define SH_LOCAL_INT0_ENABLE_XN_HW_INT_SHFT 2 +#define SH_LOCAL_INT0_ENABLE_XN_HW_INT_MASK 0x0000000000000004 + +/* SH_LOCAL_INT0_ENABLE_LB_HW_INT */ +/* Description: Enable LB Hardware interrupt */ +#define SH_LOCAL_INT0_ENABLE_LB_HW_INT_SHFT 3 +#define SH_LOCAL_INT0_ENABLE_LB_HW_INT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT0_ENABLE_II_HW_INT */ +/* Description: Enable II wrapper Hardware interrupt */ +#define SH_LOCAL_INT0_ENABLE_II_HW_INT_SHFT 4 +#define SH_LOCAL_INT0_ENABLE_II_HW_INT_MASK 0x0000000000000010 + +/* SH_LOCAL_INT0_ENABLE_PI_CE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT0_ENABLE_PI_CE_INT_SHFT 5 +#define SH_LOCAL_INT0_ENABLE_PI_CE_INT_MASK 0x0000000000000020 + +/* SH_LOCAL_INT0_ENABLE_MD_CE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT0_ENABLE_MD_CE_INT_SHFT 6 +#define SH_LOCAL_INT0_ENABLE_MD_CE_INT_MASK 0x0000000000000040 + +/* SH_LOCAL_INT0_ENABLE_XN_CE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT0_ENABLE_XN_CE_INT_SHFT 7 +#define SH_LOCAL_INT0_ENABLE_XN_CE_INT_MASK 0x0000000000000080 + +/* SH_LOCAL_INT0_ENABLE_PI_UCE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_SHFT 8 +#define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 + +/* SH_LOCAL_INT0_ENABLE_MD_UCE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_SHFT 9 +#define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 + +/* SH_LOCAL_INT0_ENABLE_XN_UCE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_SHFT 10 +#define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 + +/* SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT */ +/* Description: Enable System Shutdown Interrupt */ +#define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 +#define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 + +/* SH_LOCAL_INT0_ENABLE_UART_INT */ +/* Description: Enable Junk Bus UART Interrupt */ +#define SH_LOCAL_INT0_ENABLE_UART_INT_SHFT 13 +#define SH_LOCAL_INT0_ENABLE_UART_INT_MASK 0x0000000000002000 + +/* SH_LOCAL_INT0_ENABLE_L1_NMI_INT */ +/* Description: Enable L1 Controller NMI Interrupt */ +#define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 14 +#define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 + +/* SH_LOCAL_INT0_ENABLE_STOP_CLOCK */ +/* Description: Stop Clock Interrupt */ +#define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 15 +#define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT1_CONFIG" */ +/* SHub Local Interrupt 1 Registers */ +/* ==================================================================== */ + +#define SH_LOCAL_INT1_CONFIG 0x0000000110000580 +#define SH_LOCAL_INT1_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_LOCAL_INT1_CONFIG_INIT 0x0000000000000000 + +/* SH_LOCAL_INT1_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_LOCAL_INT1_CONFIG_TYPE_SHFT 0 +#define SH_LOCAL_INT1_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_LOCAL_INT1_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_LOCAL_INT1_CONFIG_AGT_SHFT 3 +#define SH_LOCAL_INT1_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT1_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_LOCAL_INT1_CONFIG_PID_SHFT 4 +#define SH_LOCAL_INT1_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_LOCAL_INT1_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_LOCAL_INT1_CONFIG_BASE_SHFT 21 +#define SH_LOCAL_INT1_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_LOCAL_INT1_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_LOCAL_INT1_CONFIG_IDX_SHFT 52 +#define SH_LOCAL_INT1_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT1_ENABLE" */ +/* SHub Local Interrupt 1 Enable */ +/* ==================================================================== */ + +#define SH_LOCAL_INT1_ENABLE 0x0000000110000600 +#define SH_LOCAL_INT1_ENABLE_MASK 0x000000000000f7ff +#define SH_LOCAL_INT1_ENABLE_INIT 0x0000000000000000 + +/* SH_LOCAL_INT1_ENABLE_PI_HW_INT */ +/* Description: Enable PI Hardware interrupt */ +#define SH_LOCAL_INT1_ENABLE_PI_HW_INT_SHFT 0 +#define SH_LOCAL_INT1_ENABLE_PI_HW_INT_MASK 0x0000000000000001 + +/* SH_LOCAL_INT1_ENABLE_MD_HW_INT */ +/* Description: Enable MD Hardware interrupt */ +#define SH_LOCAL_INT1_ENABLE_MD_HW_INT_SHFT 1 +#define SH_LOCAL_INT1_ENABLE_MD_HW_INT_MASK 0x0000000000000002 + +/* SH_LOCAL_INT1_ENABLE_XN_HW_INT */ +/* Description: Enable XN Hardware interrupt */ +#define SH_LOCAL_INT1_ENABLE_XN_HW_INT_SHFT 2 +#define SH_LOCAL_INT1_ENABLE_XN_HW_INT_MASK 0x0000000000000004 + +/* SH_LOCAL_INT1_ENABLE_LB_HW_INT */ +/* Description: Enable LB Hardware interrupt */ +#define SH_LOCAL_INT1_ENABLE_LB_HW_INT_SHFT 3 +#define SH_LOCAL_INT1_ENABLE_LB_HW_INT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT1_ENABLE_II_HW_INT */ +/* Description: Enable II wrapper Hardware interrupt */ +#define SH_LOCAL_INT1_ENABLE_II_HW_INT_SHFT 4 +#define SH_LOCAL_INT1_ENABLE_II_HW_INT_MASK 0x0000000000000010 + +/* SH_LOCAL_INT1_ENABLE_PI_CE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT1_ENABLE_PI_CE_INT_SHFT 5 +#define SH_LOCAL_INT1_ENABLE_PI_CE_INT_MASK 0x0000000000000020 + +/* SH_LOCAL_INT1_ENABLE_MD_CE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT1_ENABLE_MD_CE_INT_SHFT 6 +#define SH_LOCAL_INT1_ENABLE_MD_CE_INT_MASK 0x0000000000000040 + +/* SH_LOCAL_INT1_ENABLE_XN_CE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT1_ENABLE_XN_CE_INT_SHFT 7 +#define SH_LOCAL_INT1_ENABLE_XN_CE_INT_MASK 0x0000000000000080 + +/* SH_LOCAL_INT1_ENABLE_PI_UCE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_SHFT 8 +#define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 + +/* SH_LOCAL_INT1_ENABLE_MD_UCE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_SHFT 9 +#define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 + +/* SH_LOCAL_INT1_ENABLE_XN_UCE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_SHFT 10 +#define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 + +/* SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT */ +/* Description: Enable System Shutdown Interrupt */ +#define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 +#define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 + +/* SH_LOCAL_INT1_ENABLE_UART_INT */ +/* Description: Enable Junk Bus UART Interrupt */ +#define SH_LOCAL_INT1_ENABLE_UART_INT_SHFT 13 +#define SH_LOCAL_INT1_ENABLE_UART_INT_MASK 0x0000000000002000 + +/* SH_LOCAL_INT1_ENABLE_L1_NMI_INT */ +/* Description: Enable L1 Controller NMI Interrupt */ +#define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_SHFT 14 +#define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 + +/* SH_LOCAL_INT1_ENABLE_STOP_CLOCK */ +/* Description: Stop Clock Interrupt */ +#define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_SHFT 15 +#define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT2_CONFIG" */ +/* SHub Local Interrupt 2 Registers */ +/* ==================================================================== */ + +#define SH_LOCAL_INT2_CONFIG 0x0000000110000680 +#define SH_LOCAL_INT2_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_LOCAL_INT2_CONFIG_INIT 0x0000000000000000 + +/* SH_LOCAL_INT2_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_LOCAL_INT2_CONFIG_TYPE_SHFT 0 +#define SH_LOCAL_INT2_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_LOCAL_INT2_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_LOCAL_INT2_CONFIG_AGT_SHFT 3 +#define SH_LOCAL_INT2_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT2_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_LOCAL_INT2_CONFIG_PID_SHFT 4 +#define SH_LOCAL_INT2_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_LOCAL_INT2_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_LOCAL_INT2_CONFIG_BASE_SHFT 21 +#define SH_LOCAL_INT2_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_LOCAL_INT2_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_LOCAL_INT2_CONFIG_IDX_SHFT 52 +#define SH_LOCAL_INT2_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT2_ENABLE" */ +/* SHub Local Interrupt 2 Enable */ +/* ==================================================================== */ + +#define SH_LOCAL_INT2_ENABLE 0x0000000110000700 +#define SH_LOCAL_INT2_ENABLE_MASK 0x000000000000f7ff +#define SH_LOCAL_INT2_ENABLE_INIT 0x0000000000000000 + +/* SH_LOCAL_INT2_ENABLE_PI_HW_INT */ +/* Description: Enable PI Hardware interrupt */ +#define SH_LOCAL_INT2_ENABLE_PI_HW_INT_SHFT 0 +#define SH_LOCAL_INT2_ENABLE_PI_HW_INT_MASK 0x0000000000000001 + +/* SH_LOCAL_INT2_ENABLE_MD_HW_INT */ +/* Description: Enable MD Hardware interrupt */ +#define SH_LOCAL_INT2_ENABLE_MD_HW_INT_SHFT 1 +#define SH_LOCAL_INT2_ENABLE_MD_HW_INT_MASK 0x0000000000000002 + +/* SH_LOCAL_INT2_ENABLE_XN_HW_INT */ +/* Description: Enable XN Hardware interrupt */ +#define SH_LOCAL_INT2_ENABLE_XN_HW_INT_SHFT 2 +#define SH_LOCAL_INT2_ENABLE_XN_HW_INT_MASK 0x0000000000000004 + +/* SH_LOCAL_INT2_ENABLE_LB_HW_INT */ +/* Description: Enable LB Hardware interrupt */ +#define SH_LOCAL_INT2_ENABLE_LB_HW_INT_SHFT 3 +#define SH_LOCAL_INT2_ENABLE_LB_HW_INT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT2_ENABLE_II_HW_INT */ +/* Description: Enable II wrapper Hardware interrupt */ +#define SH_LOCAL_INT2_ENABLE_II_HW_INT_SHFT 4 +#define SH_LOCAL_INT2_ENABLE_II_HW_INT_MASK 0x0000000000000010 + +/* SH_LOCAL_INT2_ENABLE_PI_CE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT2_ENABLE_PI_CE_INT_SHFT 5 +#define SH_LOCAL_INT2_ENABLE_PI_CE_INT_MASK 0x0000000000000020 + +/* SH_LOCAL_INT2_ENABLE_MD_CE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT2_ENABLE_MD_CE_INT_SHFT 6 +#define SH_LOCAL_INT2_ENABLE_MD_CE_INT_MASK 0x0000000000000040 + +/* SH_LOCAL_INT2_ENABLE_XN_CE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT2_ENABLE_XN_CE_INT_SHFT 7 +#define SH_LOCAL_INT2_ENABLE_XN_CE_INT_MASK 0x0000000000000080 + +/* SH_LOCAL_INT2_ENABLE_PI_UCE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_SHFT 8 +#define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 + +/* SH_LOCAL_INT2_ENABLE_MD_UCE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_SHFT 9 +#define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 + +/* SH_LOCAL_INT2_ENABLE_XN_UCE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_SHFT 10 +#define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 + +/* SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT */ +/* Description: Enable System Shutdown Interrupt */ +#define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 +#define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 + +/* SH_LOCAL_INT2_ENABLE_UART_INT */ +/* Description: Enable Junk Bus UART Interrupt */ +#define SH_LOCAL_INT2_ENABLE_UART_INT_SHFT 13 +#define SH_LOCAL_INT2_ENABLE_UART_INT_MASK 0x0000000000002000 + +/* SH_LOCAL_INT2_ENABLE_L1_NMI_INT */ +/* Description: Enable L1 Controller NMI Interrupt */ +#define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_SHFT 14 +#define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 + +/* SH_LOCAL_INT2_ENABLE_STOP_CLOCK */ +/* Description: Stop Clock Interrupt */ +#define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_SHFT 15 +#define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT3_CONFIG" */ +/* SHub Local Interrupt 3 Registers */ +/* ==================================================================== */ + +#define SH_LOCAL_INT3_CONFIG 0x0000000110000780 +#define SH_LOCAL_INT3_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_LOCAL_INT3_CONFIG_INIT 0x0000000000000000 + +/* SH_LOCAL_INT3_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_LOCAL_INT3_CONFIG_TYPE_SHFT 0 +#define SH_LOCAL_INT3_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_LOCAL_INT3_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_LOCAL_INT3_CONFIG_AGT_SHFT 3 +#define SH_LOCAL_INT3_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT3_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_LOCAL_INT3_CONFIG_PID_SHFT 4 +#define SH_LOCAL_INT3_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_LOCAL_INT3_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_LOCAL_INT3_CONFIG_BASE_SHFT 21 +#define SH_LOCAL_INT3_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_LOCAL_INT3_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_LOCAL_INT3_CONFIG_IDX_SHFT 52 +#define SH_LOCAL_INT3_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT3_ENABLE" */ +/* SHub Local Interrupt 3 Enable */ +/* ==================================================================== */ + +#define SH_LOCAL_INT3_ENABLE 0x0000000110000800 +#define SH_LOCAL_INT3_ENABLE_MASK 0x000000000000f7ff +#define SH_LOCAL_INT3_ENABLE_INIT 0x0000000000000000 + +/* SH_LOCAL_INT3_ENABLE_PI_HW_INT */ +/* Description: Enable PI Hardware interrupt */ +#define SH_LOCAL_INT3_ENABLE_PI_HW_INT_SHFT 0 +#define SH_LOCAL_INT3_ENABLE_PI_HW_INT_MASK 0x0000000000000001 + +/* SH_LOCAL_INT3_ENABLE_MD_HW_INT */ +/* Description: Enable MD Hardware interrupt */ +#define SH_LOCAL_INT3_ENABLE_MD_HW_INT_SHFT 1 +#define SH_LOCAL_INT3_ENABLE_MD_HW_INT_MASK 0x0000000000000002 + +/* SH_LOCAL_INT3_ENABLE_XN_HW_INT */ +/* Description: Enable XN Hardware interrupt */ +#define SH_LOCAL_INT3_ENABLE_XN_HW_INT_SHFT 2 +#define SH_LOCAL_INT3_ENABLE_XN_HW_INT_MASK 0x0000000000000004 + +/* SH_LOCAL_INT3_ENABLE_LB_HW_INT */ +/* Description: Enable LB Hardware interrupt */ +#define SH_LOCAL_INT3_ENABLE_LB_HW_INT_SHFT 3 +#define SH_LOCAL_INT3_ENABLE_LB_HW_INT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT3_ENABLE_II_HW_INT */ +/* Description: Enable II wrapper Hardware interrupt */ +#define SH_LOCAL_INT3_ENABLE_II_HW_INT_SHFT 4 +#define SH_LOCAL_INT3_ENABLE_II_HW_INT_MASK 0x0000000000000010 + +/* SH_LOCAL_INT3_ENABLE_PI_CE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT3_ENABLE_PI_CE_INT_SHFT 5 +#define SH_LOCAL_INT3_ENABLE_PI_CE_INT_MASK 0x0000000000000020 + +/* SH_LOCAL_INT3_ENABLE_MD_CE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT3_ENABLE_MD_CE_INT_SHFT 6 +#define SH_LOCAL_INT3_ENABLE_MD_CE_INT_MASK 0x0000000000000040 + +/* SH_LOCAL_INT3_ENABLE_XN_CE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT3_ENABLE_XN_CE_INT_SHFT 7 +#define SH_LOCAL_INT3_ENABLE_XN_CE_INT_MASK 0x0000000000000080 + +/* SH_LOCAL_INT3_ENABLE_PI_UCE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_SHFT 8 +#define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 + +/* SH_LOCAL_INT3_ENABLE_MD_UCE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_SHFT 9 +#define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 + +/* SH_LOCAL_INT3_ENABLE_XN_UCE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_SHFT 10 +#define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 + +/* SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT */ +/* Description: Enable System Shutdown Interrupt */ +#define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 +#define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 + +/* SH_LOCAL_INT3_ENABLE_UART_INT */ +/* Description: Enable Junk Bus UART Interrupt */ +#define SH_LOCAL_INT3_ENABLE_UART_INT_SHFT 13 +#define SH_LOCAL_INT3_ENABLE_UART_INT_MASK 0x0000000000002000 + +/* SH_LOCAL_INT3_ENABLE_L1_NMI_INT */ +/* Description: Enable L1 Controller NMI Interrupt */ +#define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_SHFT 14 +#define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 + +/* SH_LOCAL_INT3_ENABLE_STOP_CLOCK */ +/* Description: Stop Clock Interrupt */ +#define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_SHFT 15 +#define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT4_CONFIG" */ +/* SHub Local Interrupt 4 Registers */ +/* ==================================================================== */ + +#define SH_LOCAL_INT4_CONFIG 0x0000000110000880 +#define SH_LOCAL_INT4_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_LOCAL_INT4_CONFIG_INIT 0x0000000000000000 + +/* SH_LOCAL_INT4_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_LOCAL_INT4_CONFIG_TYPE_SHFT 0 +#define SH_LOCAL_INT4_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_LOCAL_INT4_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_LOCAL_INT4_CONFIG_AGT_SHFT 3 +#define SH_LOCAL_INT4_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT4_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_LOCAL_INT4_CONFIG_PID_SHFT 4 +#define SH_LOCAL_INT4_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_LOCAL_INT4_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_LOCAL_INT4_CONFIG_BASE_SHFT 21 +#define SH_LOCAL_INT4_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_LOCAL_INT4_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_LOCAL_INT4_CONFIG_IDX_SHFT 52 +#define SH_LOCAL_INT4_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT4_ENABLE" */ +/* SHub Local Interrupt 4 Enable */ +/* ==================================================================== */ + +#define SH_LOCAL_INT4_ENABLE 0x0000000110000900 +#define SH_LOCAL_INT4_ENABLE_MASK 0x000000000000f7ff +#define SH_LOCAL_INT4_ENABLE_INIT 0x0000000000000000 + +/* SH_LOCAL_INT4_ENABLE_PI_HW_INT */ +/* Description: Enable PI Hardware interrupt */ +#define SH_LOCAL_INT4_ENABLE_PI_HW_INT_SHFT 0 +#define SH_LOCAL_INT4_ENABLE_PI_HW_INT_MASK 0x0000000000000001 + +/* SH_LOCAL_INT4_ENABLE_MD_HW_INT */ +/* Description: Enable MD Hardware interrupt */ +#define SH_LOCAL_INT4_ENABLE_MD_HW_INT_SHFT 1 +#define SH_LOCAL_INT4_ENABLE_MD_HW_INT_MASK 0x0000000000000002 + +/* SH_LOCAL_INT4_ENABLE_XN_HW_INT */ +/* Description: Enable XN Hardware interrupt */ +#define SH_LOCAL_INT4_ENABLE_XN_HW_INT_SHFT 2 +#define SH_LOCAL_INT4_ENABLE_XN_HW_INT_MASK 0x0000000000000004 + +/* SH_LOCAL_INT4_ENABLE_LB_HW_INT */ +/* Description: Enable LB Hardware interrupt */ +#define SH_LOCAL_INT4_ENABLE_LB_HW_INT_SHFT 3 +#define SH_LOCAL_INT4_ENABLE_LB_HW_INT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT4_ENABLE_II_HW_INT */ +/* Description: Enable II wrapper Hardware interrupt */ +#define SH_LOCAL_INT4_ENABLE_II_HW_INT_SHFT 4 +#define SH_LOCAL_INT4_ENABLE_II_HW_INT_MASK 0x0000000000000010 + +/* SH_LOCAL_INT4_ENABLE_PI_CE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT4_ENABLE_PI_CE_INT_SHFT 5 +#define SH_LOCAL_INT4_ENABLE_PI_CE_INT_MASK 0x0000000000000020 + +/* SH_LOCAL_INT4_ENABLE_MD_CE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT4_ENABLE_MD_CE_INT_SHFT 6 +#define SH_LOCAL_INT4_ENABLE_MD_CE_INT_MASK 0x0000000000000040 + +/* SH_LOCAL_INT4_ENABLE_XN_CE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT4_ENABLE_XN_CE_INT_SHFT 7 +#define SH_LOCAL_INT4_ENABLE_XN_CE_INT_MASK 0x0000000000000080 + +/* SH_LOCAL_INT4_ENABLE_PI_UCE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_SHFT 8 +#define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 + +/* SH_LOCAL_INT4_ENABLE_MD_UCE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_SHFT 9 +#define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 + +/* SH_LOCAL_INT4_ENABLE_XN_UCE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_SHFT 10 +#define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 + +/* SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT */ +/* Description: Enable System Shutdown Interrupt */ +#define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 +#define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 + +/* SH_LOCAL_INT4_ENABLE_UART_INT */ +/* Description: Enable Junk Bus UART Interrupt */ +#define SH_LOCAL_INT4_ENABLE_UART_INT_SHFT 13 +#define SH_LOCAL_INT4_ENABLE_UART_INT_MASK 0x0000000000002000 + +/* SH_LOCAL_INT4_ENABLE_L1_NMI_INT */ +/* Description: Enable L1 Controller NMI Interrupt */ +#define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_SHFT 14 +#define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 + +/* SH_LOCAL_INT4_ENABLE_STOP_CLOCK */ +/* Description: Stop Clock Interrupt */ +#define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_SHFT 15 +#define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT5_CONFIG" */ +/* SHub Local Interrupt 5 Registers */ +/* ==================================================================== */ + +#define SH_LOCAL_INT5_CONFIG 0x0000000110000980 +#define SH_LOCAL_INT5_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_LOCAL_INT5_CONFIG_INIT 0x0000000000000000 + +/* SH_LOCAL_INT5_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_LOCAL_INT5_CONFIG_TYPE_SHFT 0 +#define SH_LOCAL_INT5_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_LOCAL_INT5_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_LOCAL_INT5_CONFIG_AGT_SHFT 3 +#define SH_LOCAL_INT5_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT5_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_LOCAL_INT5_CONFIG_PID_SHFT 4 +#define SH_LOCAL_INT5_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_LOCAL_INT5_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_LOCAL_INT5_CONFIG_BASE_SHFT 21 +#define SH_LOCAL_INT5_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_LOCAL_INT5_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_LOCAL_INT5_CONFIG_IDX_SHFT 52 +#define SH_LOCAL_INT5_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT5_ENABLE" */ +/* SHub Local Interrupt 5 Enable */ +/* ==================================================================== */ + +#define SH_LOCAL_INT5_ENABLE 0x0000000110000a00 +#define SH_LOCAL_INT5_ENABLE_MASK 0x000000000000f7ff +#define SH_LOCAL_INT5_ENABLE_INIT 0x0000000000000000 + +/* SH_LOCAL_INT5_ENABLE_PI_HW_INT */ +/* Description: Enable PI Hardware interrupt */ +#define SH_LOCAL_INT5_ENABLE_PI_HW_INT_SHFT 0 +#define SH_LOCAL_INT5_ENABLE_PI_HW_INT_MASK 0x0000000000000001 + +/* SH_LOCAL_INT5_ENABLE_MD_HW_INT */ +/* Description: Enable MD Hardware interrupt */ +#define SH_LOCAL_INT5_ENABLE_MD_HW_INT_SHFT 1 +#define SH_LOCAL_INT5_ENABLE_MD_HW_INT_MASK 0x0000000000000002 + +/* SH_LOCAL_INT5_ENABLE_XN_HW_INT */ +/* Description: Enable XN Hardware interrupt */ +#define SH_LOCAL_INT5_ENABLE_XN_HW_INT_SHFT 2 +#define SH_LOCAL_INT5_ENABLE_XN_HW_INT_MASK 0x0000000000000004 + +/* SH_LOCAL_INT5_ENABLE_LB_HW_INT */ +/* Description: Enable LB Hardware interrupt */ +#define SH_LOCAL_INT5_ENABLE_LB_HW_INT_SHFT 3 +#define SH_LOCAL_INT5_ENABLE_LB_HW_INT_MASK 0x0000000000000008 + +/* SH_LOCAL_INT5_ENABLE_II_HW_INT */ +/* Description: Enable II wrapper Hardware interrupt */ +#define SH_LOCAL_INT5_ENABLE_II_HW_INT_SHFT 4 +#define SH_LOCAL_INT5_ENABLE_II_HW_INT_MASK 0x0000000000000010 + +/* SH_LOCAL_INT5_ENABLE_PI_CE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT5_ENABLE_PI_CE_INT_SHFT 5 +#define SH_LOCAL_INT5_ENABLE_PI_CE_INT_MASK 0x0000000000000020 + +/* SH_LOCAL_INT5_ENABLE_MD_CE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT5_ENABLE_MD_CE_INT_SHFT 6 +#define SH_LOCAL_INT5_ENABLE_MD_CE_INT_MASK 0x0000000000000040 + +/* SH_LOCAL_INT5_ENABLE_XN_CE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT5_ENABLE_XN_CE_INT_SHFT 7 +#define SH_LOCAL_INT5_ENABLE_XN_CE_INT_MASK 0x0000000000000080 + +/* SH_LOCAL_INT5_ENABLE_PI_UCE_INT */ +/* Description: Enable PI Correctable Error Interrupt */ +#define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_SHFT 8 +#define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_MASK 0x0000000000000100 + +/* SH_LOCAL_INT5_ENABLE_MD_UCE_INT */ +/* Description: Enable MD Correctable Error Interrupt */ +#define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_SHFT 9 +#define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_MASK 0x0000000000000200 + +/* SH_LOCAL_INT5_ENABLE_XN_UCE_INT */ +/* Description: Enable XN Correctable Error Interrupt */ +#define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_SHFT 10 +#define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_MASK 0x0000000000000400 + +/* SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT */ +/* Description: Enable System Shutdown Interrupt */ +#define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12 +#define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000 + +/* SH_LOCAL_INT5_ENABLE_UART_INT */ +/* Description: Enable Junk Bus UART Interrupt */ +#define SH_LOCAL_INT5_ENABLE_UART_INT_SHFT 13 +#define SH_LOCAL_INT5_ENABLE_UART_INT_MASK 0x0000000000002000 + +/* SH_LOCAL_INT5_ENABLE_L1_NMI_INT */ +/* Description: Enable L1 Controller NMI Interrupt */ +#define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_SHFT 14 +#define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_MASK 0x0000000000004000 + +/* SH_LOCAL_INT5_ENABLE_STOP_CLOCK */ +/* Description: Stop Clock Interrupt */ +#define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_SHFT 15 +#define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_MASK 0x0000000000008000 + +/* ==================================================================== */ +/* Register "SH_PROC0_ERR_INT_CONFIG" */ +/* SHub Processor 0 Error Interrupt Registers */ +/* ==================================================================== */ + +#define SH_PROC0_ERR_INT_CONFIG 0x0000000110000a80 +#define SH_PROC0_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_PROC0_ERR_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_PROC0_ERR_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_PROC0_ERR_INT_CONFIG_TYPE_SHFT 0 +#define SH_PROC0_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_PROC0_ERR_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_PROC0_ERR_INT_CONFIG_AGT_SHFT 3 +#define SH_PROC0_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_PROC0_ERR_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_PROC0_ERR_INT_CONFIG_PID_SHFT 4 +#define SH_PROC0_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_PROC0_ERR_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_PROC0_ERR_INT_CONFIG_BASE_SHFT 21 +#define SH_PROC0_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_PROC0_ERR_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_PROC0_ERR_INT_CONFIG_IDX_SHFT 52 +#define SH_PROC0_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC1_ERR_INT_CONFIG" */ +/* SHub Processor 1 Error Interrupt Registers */ +/* ==================================================================== */ + +#define SH_PROC1_ERR_INT_CONFIG 0x0000000110000b00 +#define SH_PROC1_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_PROC1_ERR_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_PROC1_ERR_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_PROC1_ERR_INT_CONFIG_TYPE_SHFT 0 +#define SH_PROC1_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_PROC1_ERR_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_PROC1_ERR_INT_CONFIG_AGT_SHFT 3 +#define SH_PROC1_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_PROC1_ERR_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_PROC1_ERR_INT_CONFIG_PID_SHFT 4 +#define SH_PROC1_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_PROC1_ERR_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_PROC1_ERR_INT_CONFIG_BASE_SHFT 21 +#define SH_PROC1_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_PROC1_ERR_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_PROC1_ERR_INT_CONFIG_IDX_SHFT 52 +#define SH_PROC1_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC2_ERR_INT_CONFIG" */ +/* SHub Processor 2 Error Interrupt Registers */ +/* ==================================================================== */ + +#define SH_PROC2_ERR_INT_CONFIG 0x0000000110000b80 +#define SH_PROC2_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_PROC2_ERR_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_PROC2_ERR_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_PROC2_ERR_INT_CONFIG_TYPE_SHFT 0 +#define SH_PROC2_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_PROC2_ERR_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_PROC2_ERR_INT_CONFIG_AGT_SHFT 3 +#define SH_PROC2_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_PROC2_ERR_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_PROC2_ERR_INT_CONFIG_PID_SHFT 4 +#define SH_PROC2_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_PROC2_ERR_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_PROC2_ERR_INT_CONFIG_BASE_SHFT 21 +#define SH_PROC2_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_PROC2_ERR_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_PROC2_ERR_INT_CONFIG_IDX_SHFT 52 +#define SH_PROC2_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC3_ERR_INT_CONFIG" */ +/* SHub Processor 3 Error Interrupt Registers */ +/* ==================================================================== */ + +#define SH_PROC3_ERR_INT_CONFIG 0x0000000110000c00 +#define SH_PROC3_ERR_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_PROC3_ERR_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_PROC3_ERR_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_PROC3_ERR_INT_CONFIG_TYPE_SHFT 0 +#define SH_PROC3_ERR_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_PROC3_ERR_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_PROC3_ERR_INT_CONFIG_AGT_SHFT 3 +#define SH_PROC3_ERR_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_PROC3_ERR_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_PROC3_ERR_INT_CONFIG_PID_SHFT 4 +#define SH_PROC3_ERR_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_PROC3_ERR_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_PROC3_ERR_INT_CONFIG_BASE_SHFT 21 +#define SH_PROC3_ERR_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_PROC3_ERR_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_PROC3_ERR_INT_CONFIG_IDX_SHFT 52 +#define SH_PROC3_ERR_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC0_ADV_INT_CONFIG" */ +/* SHub Processor 0 Advisory Interrupt Registers */ +/* ==================================================================== */ + +#define SH_PROC0_ADV_INT_CONFIG 0x0000000110000c80 +#define SH_PROC0_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_PROC0_ADV_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_PROC0_ADV_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_PROC0_ADV_INT_CONFIG_TYPE_SHFT 0 +#define SH_PROC0_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_PROC0_ADV_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_PROC0_ADV_INT_CONFIG_AGT_SHFT 3 +#define SH_PROC0_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_PROC0_ADV_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_PROC0_ADV_INT_CONFIG_PID_SHFT 4 +#define SH_PROC0_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_PROC0_ADV_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_PROC0_ADV_INT_CONFIG_BASE_SHFT 21 +#define SH_PROC0_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_PROC0_ADV_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_PROC0_ADV_INT_CONFIG_IDX_SHFT 52 +#define SH_PROC0_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC1_ADV_INT_CONFIG" */ +/* SHub Processor 1 Advisory Interrupt Registers */ +/* ==================================================================== */ + +#define SH_PROC1_ADV_INT_CONFIG 0x0000000110000d00 +#define SH_PROC1_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_PROC1_ADV_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_PROC1_ADV_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_PROC1_ADV_INT_CONFIG_TYPE_SHFT 0 +#define SH_PROC1_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_PROC1_ADV_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_PROC1_ADV_INT_CONFIG_AGT_SHFT 3 +#define SH_PROC1_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_PROC1_ADV_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_PROC1_ADV_INT_CONFIG_PID_SHFT 4 +#define SH_PROC1_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_PROC1_ADV_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_PROC1_ADV_INT_CONFIG_BASE_SHFT 21 +#define SH_PROC1_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_PROC1_ADV_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_PROC1_ADV_INT_CONFIG_IDX_SHFT 52 +#define SH_PROC1_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC2_ADV_INT_CONFIG" */ +/* SHub Processor 2 Advisory Interrupt Registers */ +/* ==================================================================== */ + +#define SH_PROC2_ADV_INT_CONFIG 0x0000000110000d80 +#define SH_PROC2_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_PROC2_ADV_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_PROC2_ADV_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_PROC2_ADV_INT_CONFIG_TYPE_SHFT 0 +#define SH_PROC2_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_PROC2_ADV_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_PROC2_ADV_INT_CONFIG_AGT_SHFT 3 +#define SH_PROC2_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_PROC2_ADV_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_PROC2_ADV_INT_CONFIG_PID_SHFT 4 +#define SH_PROC2_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_PROC2_ADV_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_PROC2_ADV_INT_CONFIG_BASE_SHFT 21 +#define SH_PROC2_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_PROC2_ADV_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_PROC2_ADV_INT_CONFIG_IDX_SHFT 52 +#define SH_PROC2_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC3_ADV_INT_CONFIG" */ +/* SHub Processor 3 Advisory Interrupt Registers */ +/* ==================================================================== */ + +#define SH_PROC3_ADV_INT_CONFIG 0x0000000110000e00 +#define SH_PROC3_ADV_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_PROC3_ADV_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_PROC3_ADV_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_PROC3_ADV_INT_CONFIG_TYPE_SHFT 0 +#define SH_PROC3_ADV_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_PROC3_ADV_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_PROC3_ADV_INT_CONFIG_AGT_SHFT 3 +#define SH_PROC3_ADV_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_PROC3_ADV_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_PROC3_ADV_INT_CONFIG_PID_SHFT 4 +#define SH_PROC3_ADV_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_PROC3_ADV_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_PROC3_ADV_INT_CONFIG_BASE_SHFT 21 +#define SH_PROC3_ADV_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_PROC3_ADV_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_PROC3_ADV_INT_CONFIG_IDX_SHFT 52 +#define SH_PROC3_ADV_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC0_ERR_INT_ENABLE" */ +/* SHub Processor 0 Error Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_PROC0_ERR_INT_ENABLE 0x0000000110000e80 +#define SH_PROC0_ERR_INT_ENABLE_MASK 0x0000000000000001 +#define SH_PROC0_ERR_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE */ +/* Description: Enable Processor 0 Error Interrupt */ +#define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_SHFT 0 +#define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_PROC1_ERR_INT_ENABLE" */ +/* SHub Processor 1 Error Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_PROC1_ERR_INT_ENABLE 0x0000000110000f00 +#define SH_PROC1_ERR_INT_ENABLE_MASK 0x0000000000000001 +#define SH_PROC1_ERR_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE */ +/* Description: Enable Processor 1 Error Interrupt */ +#define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_SHFT 0 +#define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_PROC2_ERR_INT_ENABLE" */ +/* SHub Processor 2 Error Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_PROC2_ERR_INT_ENABLE 0x0000000110000f80 +#define SH_PROC2_ERR_INT_ENABLE_MASK 0x0000000000000001 +#define SH_PROC2_ERR_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE */ +/* Description: Enable Processor 2 Error Interrupt */ +#define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_SHFT 0 +#define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_PROC3_ERR_INT_ENABLE" */ +/* SHub Processor 3 Error Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_PROC3_ERR_INT_ENABLE 0x0000000110001000 +#define SH_PROC3_ERR_INT_ENABLE_MASK 0x0000000000000001 +#define SH_PROC3_ERR_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE */ +/* Description: Enable Processor 3 Error Interrupt */ +#define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_SHFT 0 +#define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_PROC0_ADV_INT_ENABLE" */ +/* SHub Processor 0 Advisory Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_PROC0_ADV_INT_ENABLE 0x0000000110001080 +#define SH_PROC0_ADV_INT_ENABLE_MASK 0x0000000000000001 +#define SH_PROC0_ADV_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE */ +/* Description: Enable Processor 0 Advisory Interrupt */ +#define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_SHFT 0 +#define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_PROC1_ADV_INT_ENABLE" */ +/* SHub Processor 1 Advisory Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_PROC1_ADV_INT_ENABLE 0x0000000110001100 +#define SH_PROC1_ADV_INT_ENABLE_MASK 0x0000000000000001 +#define SH_PROC1_ADV_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE */ +/* Description: Enable Processor 1 Advisory Interrupt */ +#define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_SHFT 0 +#define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_PROC2_ADV_INT_ENABLE" */ +/* SHub Processor 2 Advisory Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_PROC2_ADV_INT_ENABLE 0x0000000110001180 +#define SH_PROC2_ADV_INT_ENABLE_MASK 0x0000000000000001 +#define SH_PROC2_ADV_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE */ +/* Description: Enable Processor 2 Advisory Interrupt */ +#define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_SHFT 0 +#define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_PROC3_ADV_INT_ENABLE" */ +/* SHub Processor 3 Advisory Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_PROC3_ADV_INT_ENABLE 0x0000000110001200 +#define SH_PROC3_ADV_INT_ENABLE_MASK 0x0000000000000001 +#define SH_PROC3_ADV_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE */ +/* Description: Enable Processor 3 Advisory Interrupt */ +#define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_SHFT 0 +#define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_PROFILE_INT_CONFIG" */ +/* SHub Profile Interrupt Configuration Registers */ +/* ==================================================================== */ + +#define SH_PROFILE_INT_CONFIG 0x0000000110001280 +#define SH_PROFILE_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_PROFILE_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_PROFILE_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_PROFILE_INT_CONFIG_TYPE_SHFT 0 +#define SH_PROFILE_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_PROFILE_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_PROFILE_INT_CONFIG_AGT_SHFT 3 +#define SH_PROFILE_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_PROFILE_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_PROFILE_INT_CONFIG_PID_SHFT 4 +#define SH_PROFILE_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_PROFILE_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_PROFILE_INT_CONFIG_BASE_SHFT 21 +#define SH_PROFILE_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_PROFILE_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_PROFILE_INT_CONFIG_IDX_SHFT 52 +#define SH_PROFILE_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_PROFILE_INT_ENABLE" */ +/* SHub Profile Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_PROFILE_INT_ENABLE 0x0000000110001300 +#define SH_PROFILE_INT_ENABLE_MASK 0x0000000000000001 +#define SH_PROFILE_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_PROFILE_INT_ENABLE_PROFILE_ENABLE */ +/* Description: Enable Profile Interrupt */ +#define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_SHFT 0 +#define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_RTC0_INT_CONFIG" */ +/* SHub RTC 0 Interrupt Config Registers */ +/* ==================================================================== */ + +#define SH_RTC0_INT_CONFIG 0x0000000110001380 +#define SH_RTC0_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_RTC0_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_RTC0_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_RTC0_INT_CONFIG_TYPE_SHFT 0 +#define SH_RTC0_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_RTC0_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_RTC0_INT_CONFIG_AGT_SHFT 3 +#define SH_RTC0_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_RTC0_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_RTC0_INT_CONFIG_PID_SHFT 4 +#define SH_RTC0_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_RTC0_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_RTC0_INT_CONFIG_BASE_SHFT 21 +#define SH_RTC0_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_RTC0_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_RTC0_INT_CONFIG_IDX_SHFT 52 +#define SH_RTC0_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_RTC0_INT_ENABLE" */ +/* SHub RTC 0 Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_RTC0_INT_ENABLE 0x0000000110001400 +#define SH_RTC0_INT_ENABLE_MASK 0x0000000000000001 +#define SH_RTC0_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_RTC0_INT_ENABLE_RTC0_ENABLE */ +/* Description: Enable RTC 0 Interrupt */ +#define SH_RTC0_INT_ENABLE_RTC0_ENABLE_SHFT 0 +#define SH_RTC0_INT_ENABLE_RTC0_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_RTC1_INT_CONFIG" */ +/* SHub RTC 1 Interrupt Config Registers */ +/* ==================================================================== */ + +#define SH_RTC1_INT_CONFIG 0x0000000110001480 +#define SH_RTC1_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_RTC1_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_RTC1_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_RTC1_INT_CONFIG_TYPE_SHFT 0 +#define SH_RTC1_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_RTC1_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_RTC1_INT_CONFIG_AGT_SHFT 3 +#define SH_RTC1_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_RTC1_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_RTC1_INT_CONFIG_PID_SHFT 4 +#define SH_RTC1_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_RTC1_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_RTC1_INT_CONFIG_BASE_SHFT 21 +#define SH_RTC1_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_RTC1_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_RTC1_INT_CONFIG_IDX_SHFT 52 +#define SH_RTC1_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_RTC1_INT_ENABLE" */ +/* SHub RTC 1 Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_RTC1_INT_ENABLE 0x0000000110001500 +#define SH_RTC1_INT_ENABLE_MASK 0x0000000000000001 +#define SH_RTC1_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_RTC1_INT_ENABLE_RTC1_ENABLE */ +/* Description: Enable RTC 1 Interrupt */ +#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT 0 +#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_RTC2_INT_CONFIG" */ +/* SHub RTC 2 Interrupt Config Registers */ +/* ==================================================================== */ + +#define SH_RTC2_INT_CONFIG 0x0000000110001580 +#define SH_RTC2_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_RTC2_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_RTC2_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_RTC2_INT_CONFIG_TYPE_SHFT 0 +#define SH_RTC2_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_RTC2_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_RTC2_INT_CONFIG_AGT_SHFT 3 +#define SH_RTC2_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_RTC2_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_RTC2_INT_CONFIG_PID_SHFT 4 +#define SH_RTC2_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_RTC2_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_RTC2_INT_CONFIG_BASE_SHFT 21 +#define SH_RTC2_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_RTC2_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_RTC2_INT_CONFIG_IDX_SHFT 52 +#define SH_RTC2_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_RTC2_INT_ENABLE" */ +/* SHub RTC 2 Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_RTC2_INT_ENABLE 0x0000000110001600 +#define SH_RTC2_INT_ENABLE_MASK 0x0000000000000001 +#define SH_RTC2_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_RTC2_INT_ENABLE_RTC2_ENABLE */ +/* Description: Enable RTC 2 Interrupt */ +#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT 0 +#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_RTC3_INT_CONFIG" */ +/* SHub RTC 3 Interrupt Config Registers */ +/* ==================================================================== */ + +#define SH_RTC3_INT_CONFIG 0x0000000110001680 +#define SH_RTC3_INT_CONFIG_MASK 0x0ff3ffffffefffff +#define SH_RTC3_INT_CONFIG_INIT 0x0000000000000000 + +/* SH_RTC3_INT_CONFIG_TYPE */ +/* Description: Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT */ +#define SH_RTC3_INT_CONFIG_TYPE_SHFT 0 +#define SH_RTC3_INT_CONFIG_TYPE_MASK 0x0000000000000007 + +/* SH_RTC3_INT_CONFIG_AGT */ +/* Description: Agent, must be 0 for SHub */ +#define SH_RTC3_INT_CONFIG_AGT_SHFT 3 +#define SH_RTC3_INT_CONFIG_AGT_MASK 0x0000000000000008 + +/* SH_RTC3_INT_CONFIG_PID */ +/* Description: Processor ID, same setting as on targeted McKinley */ +#define SH_RTC3_INT_CONFIG_PID_SHFT 4 +#define SH_RTC3_INT_CONFIG_PID_MASK 0x00000000000ffff0 + +/* SH_RTC3_INT_CONFIG_BASE */ +/* Description: Optional interrupt vector area, 2MB aligned */ +#define SH_RTC3_INT_CONFIG_BASE_SHFT 21 +#define SH_RTC3_INT_CONFIG_BASE_MASK 0x0003ffffffe00000 + +/* SH_RTC3_INT_CONFIG_IDX */ +/* Description: Targeted McKinley interrupt vector */ +#define SH_RTC3_INT_CONFIG_IDX_SHFT 52 +#define SH_RTC3_INT_CONFIG_IDX_MASK 0x0ff0000000000000 + +/* ==================================================================== */ +/* Register "SH_RTC3_INT_ENABLE" */ +/* SHub RTC 3 Interrupt Enable Registers */ +/* ==================================================================== */ + +#define SH_RTC3_INT_ENABLE 0x0000000110001700 +#define SH_RTC3_INT_ENABLE_MASK 0x0000000000000001 +#define SH_RTC3_INT_ENABLE_INIT 0x0000000000000000 + +/* SH_RTC3_INT_ENABLE_RTC3_ENABLE */ +/* Description: Enable RTC 3 Interrupt */ +#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT 0 +#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_EVENT_OCCURRED" */ +/* SHub Interrupt Event Occurred */ +/* ==================================================================== */ + +#define SH_EVENT_OCCURRED 0x0000000110010000 +#define SH_EVENT_OCCURRED_MASK 0x000000007fffffff +#define SH_EVENT_OCCURRED_INIT 0x0000000000000000 + +/* SH_EVENT_OCCURRED_PI_HW_INT */ +/* Description: Pending PI Hardware interrupt */ +#define SH_EVENT_OCCURRED_PI_HW_INT_SHFT 0 +#define SH_EVENT_OCCURRED_PI_HW_INT_MASK 0x0000000000000001 + +/* SH_EVENT_OCCURRED_MD_HW_INT */ +/* Description: Pending MD Hardware interrupt */ +#define SH_EVENT_OCCURRED_MD_HW_INT_SHFT 1 +#define SH_EVENT_OCCURRED_MD_HW_INT_MASK 0x0000000000000002 + +/* SH_EVENT_OCCURRED_XN_HW_INT */ +/* Description: Pending XN Hardware interrupt */ +#define SH_EVENT_OCCURRED_XN_HW_INT_SHFT 2 +#define SH_EVENT_OCCURRED_XN_HW_INT_MASK 0x0000000000000004 + +/* SH_EVENT_OCCURRED_LB_HW_INT */ +/* Description: Pending LB Hardware interrupt */ +#define SH_EVENT_OCCURRED_LB_HW_INT_SHFT 3 +#define SH_EVENT_OCCURRED_LB_HW_INT_MASK 0x0000000000000008 + +/* SH_EVENT_OCCURRED_II_HW_INT */ +/* Description: Pending II wrapper Hardware interrupt */ +#define SH_EVENT_OCCURRED_II_HW_INT_SHFT 4 +#define SH_EVENT_OCCURRED_II_HW_INT_MASK 0x0000000000000010 + +/* SH_EVENT_OCCURRED_PI_CE_INT */ +/* Description: Pending PI Correctable Error Interrupt */ +#define SH_EVENT_OCCURRED_PI_CE_INT_SHFT 5 +#define SH_EVENT_OCCURRED_PI_CE_INT_MASK 0x0000000000000020 + +/* SH_EVENT_OCCURRED_MD_CE_INT */ +/* Description: Pending MD Correctable Error Interrupt */ +#define SH_EVENT_OCCURRED_MD_CE_INT_SHFT 6 +#define SH_EVENT_OCCURRED_MD_CE_INT_MASK 0x0000000000000040 + +/* SH_EVENT_OCCURRED_XN_CE_INT */ +/* Description: Pending XN Correctable Error Interrupt */ +#define SH_EVENT_OCCURRED_XN_CE_INT_SHFT 7 +#define SH_EVENT_OCCURRED_XN_CE_INT_MASK 0x0000000000000080 + +/* SH_EVENT_OCCURRED_PI_UCE_INT */ +/* Description: Pending PI Correctable Error Interrupt */ +#define SH_EVENT_OCCURRED_PI_UCE_INT_SHFT 8 +#define SH_EVENT_OCCURRED_PI_UCE_INT_MASK 0x0000000000000100 + +/* SH_EVENT_OCCURRED_MD_UCE_INT */ +/* Description: Pending MD Correctable Error Interrupt */ +#define SH_EVENT_OCCURRED_MD_UCE_INT_SHFT 9 +#define SH_EVENT_OCCURRED_MD_UCE_INT_MASK 0x0000000000000200 + +/* SH_EVENT_OCCURRED_XN_UCE_INT */ +/* Description: Pending XN Correctable Error Interrupt */ +#define SH_EVENT_OCCURRED_XN_UCE_INT_SHFT 10 +#define SH_EVENT_OCCURRED_XN_UCE_INT_MASK 0x0000000000000400 + +/* SH_EVENT_OCCURRED_PROC0_ADV_INT */ +/* Description: Pending Processor 0 Advisory Interrupt */ +#define SH_EVENT_OCCURRED_PROC0_ADV_INT_SHFT 11 +#define SH_EVENT_OCCURRED_PROC0_ADV_INT_MASK 0x0000000000000800 + +/* SH_EVENT_OCCURRED_PROC1_ADV_INT */ +/* Description: Pending Processor 1 Advisory Interrupt */ +#define SH_EVENT_OCCURRED_PROC1_ADV_INT_SHFT 12 +#define SH_EVENT_OCCURRED_PROC1_ADV_INT_MASK 0x0000000000001000 + +/* SH_EVENT_OCCURRED_PROC2_ADV_INT */ +/* Description: Pending Processor 2 Advisory Interrupt */ +#define SH_EVENT_OCCURRED_PROC2_ADV_INT_SHFT 13 +#define SH_EVENT_OCCURRED_PROC2_ADV_INT_MASK 0x0000000000002000 + +/* SH_EVENT_OCCURRED_PROC3_ADV_INT */ +/* Description: Pending Processor 3 Advisory Interrupt */ +#define SH_EVENT_OCCURRED_PROC3_ADV_INT_SHFT 14 +#define SH_EVENT_OCCURRED_PROC3_ADV_INT_MASK 0x0000000000004000 + +/* SH_EVENT_OCCURRED_PROC0_ERR_INT */ +/* Description: Pending Processor 0 Error Interrupt */ +#define SH_EVENT_OCCURRED_PROC0_ERR_INT_SHFT 15 +#define SH_EVENT_OCCURRED_PROC0_ERR_INT_MASK 0x0000000000008000 + +/* SH_EVENT_OCCURRED_PROC1_ERR_INT */ +/* Description: Pending Processor 1 Error Interrupt */ +#define SH_EVENT_OCCURRED_PROC1_ERR_INT_SHFT 16 +#define SH_EVENT_OCCURRED_PROC1_ERR_INT_MASK 0x0000000000010000 + +/* SH_EVENT_OCCURRED_PROC2_ERR_INT */ +/* Description: Pending Processor 2 Error Interrupt */ +#define SH_EVENT_OCCURRED_PROC2_ERR_INT_SHFT 17 +#define SH_EVENT_OCCURRED_PROC2_ERR_INT_MASK 0x0000000000020000 + +/* SH_EVENT_OCCURRED_PROC3_ERR_INT */ +/* Description: Pending Processor 3 Error Interrupt */ +#define SH_EVENT_OCCURRED_PROC3_ERR_INT_SHFT 18 +#define SH_EVENT_OCCURRED_PROC3_ERR_INT_MASK 0x0000000000040000 + +/* SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT */ +/* Description: Pending System Shutdown Interrupt */ +#define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_SHFT 19 +#define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000 + +/* SH_EVENT_OCCURRED_UART_INT */ +/* Description: Pending Junk Bus UART Interrupt */ +#define SH_EVENT_OCCURRED_UART_INT_SHFT 20 +#define SH_EVENT_OCCURRED_UART_INT_MASK 0x0000000000100000 + +/* SH_EVENT_OCCURRED_L1_NMI_INT */ +/* Description: Pending L1 Controller NMI Interrupt */ +#define SH_EVENT_OCCURRED_L1_NMI_INT_SHFT 21 +#define SH_EVENT_OCCURRED_L1_NMI_INT_MASK 0x0000000000200000 + +/* SH_EVENT_OCCURRED_STOP_CLOCK */ +/* Description: Pending Stop Clock Interrupt */ +#define SH_EVENT_OCCURRED_STOP_CLOCK_SHFT 22 +#define SH_EVENT_OCCURRED_STOP_CLOCK_MASK 0x0000000000400000 + +/* SH_EVENT_OCCURRED_RTC0_INT */ +/* Description: Pending RTC 0 Interrupt */ +#define SH_EVENT_OCCURRED_RTC0_INT_SHFT 23 +#define SH_EVENT_OCCURRED_RTC0_INT_MASK 0x0000000000800000 + +/* SH_EVENT_OCCURRED_RTC1_INT */ +/* Description: Pending RTC 1 Interrupt */ +#define SH_EVENT_OCCURRED_RTC1_INT_SHFT 24 +#define SH_EVENT_OCCURRED_RTC1_INT_MASK 0x0000000001000000 + +/* SH_EVENT_OCCURRED_RTC2_INT */ +/* Description: Pending RTC 2 Interrupt */ +#define SH_EVENT_OCCURRED_RTC2_INT_SHFT 25 +#define SH_EVENT_OCCURRED_RTC2_INT_MASK 0x0000000002000000 + +/* SH_EVENT_OCCURRED_RTC3_INT */ +/* Description: Pending RTC 3 Interrupt */ +#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26 +#define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 + +/* SH_EVENT_OCCURRED_PROFILE_INT */ +/* Description: Pending Profile Interrupt */ +#define SH_EVENT_OCCURRED_PROFILE_INT_SHFT 27 +#define SH_EVENT_OCCURRED_PROFILE_INT_MASK 0x0000000008000000 + +/* SH_EVENT_OCCURRED_IPI_INT */ +/* Description: Pending IPI Interrupt */ +#define SH_EVENT_OCCURRED_IPI_INT_SHFT 28 +#define SH_EVENT_OCCURRED_IPI_INT_MASK 0x0000000010000000 + +/* SH_EVENT_OCCURRED_II_INT0 */ +/* Description: Pending II 0 Interrupt */ +#define SH_EVENT_OCCURRED_II_INT0_SHFT 29 +#define SH_EVENT_OCCURRED_II_INT0_MASK 0x0000000020000000 + +/* SH_EVENT_OCCURRED_II_INT1 */ +/* Description: Pending II 1 Interrupt */ +#define SH_EVENT_OCCURRED_II_INT1_SHFT 30 +#define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 + +/* ==================================================================== */ +/* Register "SH_EVENT_OCCURRED_ALIAS" */ +/* SHub Interrupt Event Occurred Alias */ +/* ==================================================================== */ + +#define SH_EVENT_OCCURRED_ALIAS 0x0000000110010008 + +/* ==================================================================== */ +/* Register "SH_EVENT_OVERFLOW" */ +/* SHub Interrupt Event Occurred Overflow */ +/* ==================================================================== */ + +#define SH_EVENT_OVERFLOW 0x0000000110010080 +#define SH_EVENT_OVERFLOW_MASK 0x000000000fffffff +#define SH_EVENT_OVERFLOW_INIT 0x0000000000000000 + +/* SH_EVENT_OVERFLOW_PI_HW_INT */ +/* Description: Pending PI Hardware interrupt */ +#define SH_EVENT_OVERFLOW_PI_HW_INT_SHFT 0 +#define SH_EVENT_OVERFLOW_PI_HW_INT_MASK 0x0000000000000001 + +/* SH_EVENT_OVERFLOW_MD_HW_INT */ +/* Description: Pending MD Hardware interrupt */ +#define SH_EVENT_OVERFLOW_MD_HW_INT_SHFT 1 +#define SH_EVENT_OVERFLOW_MD_HW_INT_MASK 0x0000000000000002 + +/* SH_EVENT_OVERFLOW_XN_HW_INT */ +/* Description: Pending XN Hardware interrupt */ +#define SH_EVENT_OVERFLOW_XN_HW_INT_SHFT 2 +#define SH_EVENT_OVERFLOW_XN_HW_INT_MASK 0x0000000000000004 + +/* SH_EVENT_OVERFLOW_LB_HW_INT */ +/* Description: Pending LB Hardware interrupt */ +#define SH_EVENT_OVERFLOW_LB_HW_INT_SHFT 3 +#define SH_EVENT_OVERFLOW_LB_HW_INT_MASK 0x0000000000000008 + +/* SH_EVENT_OVERFLOW_II_HW_INT */ +/* Description: Pending II wrapper Hardware interrupt */ +#define SH_EVENT_OVERFLOW_II_HW_INT_SHFT 4 +#define SH_EVENT_OVERFLOW_II_HW_INT_MASK 0x0000000000000010 + +/* SH_EVENT_OVERFLOW_PI_CE_INT */ +/* Description: Pending PI Correctable Error Interrupt */ +#define SH_EVENT_OVERFLOW_PI_CE_INT_SHFT 5 +#define SH_EVENT_OVERFLOW_PI_CE_INT_MASK 0x0000000000000020 + +/* SH_EVENT_OVERFLOW_MD_CE_INT */ +/* Description: Pending MD Correctable Error Interrupt */ +#define SH_EVENT_OVERFLOW_MD_CE_INT_SHFT 6 +#define SH_EVENT_OVERFLOW_MD_CE_INT_MASK 0x0000000000000040 + +/* SH_EVENT_OVERFLOW_XN_CE_INT */ +/* Description: Pending XN Correctable Error Interrupt */ +#define SH_EVENT_OVERFLOW_XN_CE_INT_SHFT 7 +#define SH_EVENT_OVERFLOW_XN_CE_INT_MASK 0x0000000000000080 + +/* SH_EVENT_OVERFLOW_PI_UCE_INT */ +/* Description: Pending PI Correctable Error Interrupt */ +#define SH_EVENT_OVERFLOW_PI_UCE_INT_SHFT 8 +#define SH_EVENT_OVERFLOW_PI_UCE_INT_MASK 0x0000000000000100 + +/* SH_EVENT_OVERFLOW_MD_UCE_INT */ +/* Description: Pending MD Correctable Error Interrupt */ +#define SH_EVENT_OVERFLOW_MD_UCE_INT_SHFT 9 +#define SH_EVENT_OVERFLOW_MD_UCE_INT_MASK 0x0000000000000200 + +/* SH_EVENT_OVERFLOW_XN_UCE_INT */ +/* Description: Pending XN Correctable Error Interrupt */ +#define SH_EVENT_OVERFLOW_XN_UCE_INT_SHFT 10 +#define SH_EVENT_OVERFLOW_XN_UCE_INT_MASK 0x0000000000000400 + +/* SH_EVENT_OVERFLOW_PROC0_ADV_INT */ +/* Description: Pending Processor 0 Advisory Interrupt */ +#define SH_EVENT_OVERFLOW_PROC0_ADV_INT_SHFT 11 +#define SH_EVENT_OVERFLOW_PROC0_ADV_INT_MASK 0x0000000000000800 + +/* SH_EVENT_OVERFLOW_PROC1_ADV_INT */ +/* Description: Pending Processor 1 Advisory Interrupt */ +#define SH_EVENT_OVERFLOW_PROC1_ADV_INT_SHFT 12 +#define SH_EVENT_OVERFLOW_PROC1_ADV_INT_MASK 0x0000000000001000 + +/* SH_EVENT_OVERFLOW_PROC2_ADV_INT */ +/* Description: Pending Processor 2 Advisory Interrupt */ +#define SH_EVENT_OVERFLOW_PROC2_ADV_INT_SHFT 13 +#define SH_EVENT_OVERFLOW_PROC2_ADV_INT_MASK 0x0000000000002000 + +/* SH_EVENT_OVERFLOW_PROC3_ADV_INT */ +/* Description: Pending Processor 3 Advisory Interrupt */ +#define SH_EVENT_OVERFLOW_PROC3_ADV_INT_SHFT 14 +#define SH_EVENT_OVERFLOW_PROC3_ADV_INT_MASK 0x0000000000004000 + +/* SH_EVENT_OVERFLOW_PROC0_ERR_INT */ +/* Description: Pending Processor 0 Error Interrupt */ +#define SH_EVENT_OVERFLOW_PROC0_ERR_INT_SHFT 15 +#define SH_EVENT_OVERFLOW_PROC0_ERR_INT_MASK 0x0000000000008000 + +/* SH_EVENT_OVERFLOW_PROC1_ERR_INT */ +/* Description: Pending Processor 1 Error Interrupt */ +#define SH_EVENT_OVERFLOW_PROC1_ERR_INT_SHFT 16 +#define SH_EVENT_OVERFLOW_PROC1_ERR_INT_MASK 0x0000000000010000 + +/* SH_EVENT_OVERFLOW_PROC2_ERR_INT */ +/* Description: Pending Processor 2 Error Interrupt */ +#define SH_EVENT_OVERFLOW_PROC2_ERR_INT_SHFT 17 +#define SH_EVENT_OVERFLOW_PROC2_ERR_INT_MASK 0x0000000000020000 + +/* SH_EVENT_OVERFLOW_PROC3_ERR_INT */ +/* Description: Pending Processor 3 Error Interrupt */ +#define SH_EVENT_OVERFLOW_PROC3_ERR_INT_SHFT 18 +#define SH_EVENT_OVERFLOW_PROC3_ERR_INT_MASK 0x0000000000040000 + +/* SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT */ +/* Description: Pending System Shutdown Interrupt */ +#define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_SHFT 19 +#define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000 + +/* SH_EVENT_OVERFLOW_UART_INT */ +/* Description: Pending Junk Bus UART Interrupt */ +#define SH_EVENT_OVERFLOW_UART_INT_SHFT 20 +#define SH_EVENT_OVERFLOW_UART_INT_MASK 0x0000000000100000 + +/* SH_EVENT_OVERFLOW_L1_NMI_INT */ +/* Description: Pending L1 Controller NMI Interrupt */ +#define SH_EVENT_OVERFLOW_L1_NMI_INT_SHFT 21 +#define SH_EVENT_OVERFLOW_L1_NMI_INT_MASK 0x0000000000200000 + +/* SH_EVENT_OVERFLOW_STOP_CLOCK */ +/* Description: Pending Stop Clock Interrupt */ +#define SH_EVENT_OVERFLOW_STOP_CLOCK_SHFT 22 +#define SH_EVENT_OVERFLOW_STOP_CLOCK_MASK 0x0000000000400000 + +/* SH_EVENT_OVERFLOW_RTC0_INT */ +/* Description: Pending RTC 0 Interrupt */ +#define SH_EVENT_OVERFLOW_RTC0_INT_SHFT 23 +#define SH_EVENT_OVERFLOW_RTC0_INT_MASK 0x0000000000800000 + +/* SH_EVENT_OVERFLOW_RTC1_INT */ +/* Description: Pending RTC 1 Interrupt */ +#define SH_EVENT_OVERFLOW_RTC1_INT_SHFT 24 +#define SH_EVENT_OVERFLOW_RTC1_INT_MASK 0x0000000001000000 + +/* SH_EVENT_OVERFLOW_RTC2_INT */ +/* Description: Pending RTC 2 Interrupt */ +#define SH_EVENT_OVERFLOW_RTC2_INT_SHFT 25 +#define SH_EVENT_OVERFLOW_RTC2_INT_MASK 0x0000000002000000 + +/* SH_EVENT_OVERFLOW_RTC3_INT */ +/* Description: Pending RTC 3 Interrupt */ +#define SH_EVENT_OVERFLOW_RTC3_INT_SHFT 26 +#define SH_EVENT_OVERFLOW_RTC3_INT_MASK 0x0000000004000000 + +/* SH_EVENT_OVERFLOW_PROFILE_INT */ +/* Description: Pending Profile Interrupt */ +#define SH_EVENT_OVERFLOW_PROFILE_INT_SHFT 27 +#define SH_EVENT_OVERFLOW_PROFILE_INT_MASK 0x0000000008000000 + +/* ==================================================================== */ +/* Register "SH_EVENT_OVERFLOW_ALIAS" */ +/* SHub Interrupt Event Occurred Overflow Alias */ +/* ==================================================================== */ + +#define SH_EVENT_OVERFLOW_ALIAS 0x0000000110010088 + +/* ==================================================================== */ +/* Register "SH_JUNK_BUS_TIME" */ +/* Junk Bus Timing */ +/* ==================================================================== */ + +#define SH_JUNK_BUS_TIME 0x0000000110020000 +#define SH_JUNK_BUS_TIME_MASK 0x00000000ffffffff +#define SH_JUNK_BUS_TIME_INIT 0x0000000040404040 + +/* SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD */ +/* Description: Fprom_Setup_Hold */ +#define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_SHFT 0 +#define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_MASK 0x00000000000000ff + +/* SH_JUNK_BUS_TIME_FPROM_ENABLE */ +/* Description: Fprom_Enable */ +#define SH_JUNK_BUS_TIME_FPROM_ENABLE_SHFT 8 +#define SH_JUNK_BUS_TIME_FPROM_ENABLE_MASK 0x000000000000ff00 + +/* SH_JUNK_BUS_TIME_UART_SETUP_HOLD */ +/* Description: Uart_Setup_Hold */ +#define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_SHFT 16 +#define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_MASK 0x0000000000ff0000 + +/* SH_JUNK_BUS_TIME_UART_ENABLE */ +/* Description: Uart_Enable */ +#define SH_JUNK_BUS_TIME_UART_ENABLE_SHFT 24 +#define SH_JUNK_BUS_TIME_UART_ENABLE_MASK 0x00000000ff000000 + +/* ==================================================================== */ +/* Register "SH_JUNK_LATCH_TIME" */ +/* Junk Bus Latch Timing */ +/* ==================================================================== */ + +#define SH_JUNK_LATCH_TIME 0x0000000110020080 +#define SH_JUNK_LATCH_TIME_MASK 0x0000000000000007 +#define SH_JUNK_LATCH_TIME_INIT 0x0000000000000002 + +/* SH_JUNK_LATCH_TIME_SETUP_HOLD */ +/* Description: Setup and Hold Time */ +#define SH_JUNK_LATCH_TIME_SETUP_HOLD_SHFT 0 +#define SH_JUNK_LATCH_TIME_SETUP_HOLD_MASK 0x0000000000000007 + +/* ==================================================================== */ +/* Register "SH_JUNK_NACK_RESET" */ +/* Junk Bus Nack Counter Reset */ +/* ==================================================================== */ + +#define SH_JUNK_NACK_RESET 0x0000000110020100 +#define SH_JUNK_NACK_RESET_MASK 0x0000000000000001 +#define SH_JUNK_NACK_RESET_INIT 0x0000000000000000 + +/* SH_JUNK_NACK_RESET_PULSE */ +/* Description: Junk bus nack counter reset */ +#define SH_JUNK_NACK_RESET_PULSE_SHFT 0 +#define SH_JUNK_NACK_RESET_PULSE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_JUNK_BUS_LED0" */ +/* Junk Bus LED0 */ +/* ==================================================================== */ + +#define SH_JUNK_BUS_LED0 0x0000000110030000 +#define SH_JUNK_BUS_LED0_MASK 0x00000000000000ff +#define SH_JUNK_BUS_LED0_INIT 0x0000000000000000 + +/* SH_JUNK_BUS_LED0_LED0_DATA */ +/* Description: LED0_data */ +#define SH_JUNK_BUS_LED0_LED0_DATA_SHFT 0 +#define SH_JUNK_BUS_LED0_LED0_DATA_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_JUNK_BUS_LED1" */ +/* Junk Bus LED1 */ +/* ==================================================================== */ + +#define SH_JUNK_BUS_LED1 0x0000000110030080 +#define SH_JUNK_BUS_LED1_MASK 0x00000000000000ff +#define SH_JUNK_BUS_LED1_INIT 0x0000000000000000 + +/* SH_JUNK_BUS_LED1_LED1_DATA */ +/* Description: LED1_data */ +#define SH_JUNK_BUS_LED1_LED1_DATA_SHFT 0 +#define SH_JUNK_BUS_LED1_LED1_DATA_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_JUNK_BUS_LED2" */ +/* Junk Bus LED2 */ +/* ==================================================================== */ + +#define SH_JUNK_BUS_LED2 0x0000000110030100 +#define SH_JUNK_BUS_LED2_MASK 0x00000000000000ff +#define SH_JUNK_BUS_LED2_INIT 0x0000000000000000 + +/* SH_JUNK_BUS_LED2_LED2_DATA */ +/* Description: LED2_data */ +#define SH_JUNK_BUS_LED2_LED2_DATA_SHFT 0 +#define SH_JUNK_BUS_LED2_LED2_DATA_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_JUNK_BUS_LED3" */ +/* Junk Bus LED3 */ +/* ==================================================================== */ + +#define SH_JUNK_BUS_LED3 0x0000000110030180 +#define SH_JUNK_BUS_LED3_MASK 0x00000000000000ff +#define SH_JUNK_BUS_LED3_INIT 0x0000000000000000 + +/* SH_JUNK_BUS_LED3_LED3_DATA */ +/* Description: LED3_data */ +#define SH_JUNK_BUS_LED3_LED3_DATA_SHFT 0 +#define SH_JUNK_BUS_LED3_LED3_DATA_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_JUNK_ERROR_STATUS" */ +/* Junk Bus Error Status */ +/* ==================================================================== */ + +#define SH_JUNK_ERROR_STATUS 0x0000000110030200 +#define SH_JUNK_ERROR_STATUS_MASK 0x1fff7fffffffffff +#define SH_JUNK_ERROR_STATUS_INIT 0x0000000000000000 + +/* SH_JUNK_ERROR_STATUS_ADDRESS */ +/* Description: Failing junk bus address */ +#define SH_JUNK_ERROR_STATUS_ADDRESS_SHFT 0 +#define SH_JUNK_ERROR_STATUS_ADDRESS_MASK 0x00007fffffffffff + +/* SH_JUNK_ERROR_STATUS_CMD */ +/* Description: Junk bus command */ +#define SH_JUNK_ERROR_STATUS_CMD_SHFT 48 +#define SH_JUNK_ERROR_STATUS_CMD_MASK 0x00ff000000000000 + +/* SH_JUNK_ERROR_STATUS_MODE */ +/* Description: Mode */ +#define SH_JUNK_ERROR_STATUS_MODE_SHFT 56 +#define SH_JUNK_ERROR_STATUS_MODE_MASK 0x0100000000000000 + +/* SH_JUNK_ERROR_STATUS_STATUS */ +/* Description: Status */ +#define SH_JUNK_ERROR_STATUS_STATUS_SHFT 57 +#define SH_JUNK_ERROR_STATUS_STATUS_MASK 0x1e00000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_STAT" */ +/* This register describes the LLP status. */ +/* ==================================================================== */ + +#define SH_NI0_LLP_STAT 0x0000000150000000 +#define SH_NI0_LLP_STAT_MASK 0x000000000000000f +#define SH_NI0_LLP_STAT_INIT 0x0000000000000000 + +/* SH_NI0_LLP_STAT_LINK_RESET_STATE */ +/* Description: Status of LLP link. */ +#define SH_NI0_LLP_STAT_LINK_RESET_STATE_SHFT 0 +#define SH_NI0_LLP_STAT_LINK_RESET_STATE_MASK 0x000000000000000f + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_RESET" */ +/* Writing issues a reset to the network interface */ +/* ==================================================================== */ + +#define SH_NI0_LLP_RESET 0x0000000150000008 +#define SH_NI0_LLP_RESET_MASK 0x0000000000000003 +#define SH_NI0_LLP_RESET_INIT 0x0000000000000000 + +/* SH_NI0_LLP_RESET_LINK */ +/* Description: Send Link Reset. Generates a pulse. */ +#define SH_NI0_LLP_RESET_LINK_SHFT 0 +#define SH_NI0_LLP_RESET_LINK_MASK 0x0000000000000001 + +/* SH_NI0_LLP_RESET_WARM */ +/* Description: Send Warm Reset. Generates a pulse. */ +#define SH_NI0_LLP_RESET_WARM_SHFT 1 +#define SH_NI0_LLP_RESET_WARM_MASK 0x0000000000000002 + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_RESET_EN" */ +/* Controls LLP warm reset propagation */ +/* ==================================================================== */ + +#define SH_NI0_LLP_RESET_EN 0x0000000150000010 +#define SH_NI0_LLP_RESET_EN_MASK 0x0000000000000001 +#define SH_NI0_LLP_RESET_EN_INIT 0x0000000000000001 + +/* SH_NI0_LLP_RESET_EN_OK */ +/* Description: Allow LLP warm reset to reset SHUB */ +#define SH_NI0_LLP_RESET_EN_OK_SHFT 0 +#define SH_NI0_LLP_RESET_EN_OK_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_CHAN_MODE" */ +/* Sets the signaling mode of LLP and channel */ +/* ==================================================================== */ + +#define SH_NI0_LLP_CHAN_MODE 0x0000000150000018 +#define SH_NI0_LLP_CHAN_MODE_MASK 0x000000000000001f +#define SH_NI0_LLP_CHAN_MODE_INIT 0x0000000000000000 + +/* SH_NI0_LLP_CHAN_MODE_BITMODE32 */ +/* Description: Enables 32-bit (plus sideband) channel phits */ +#define SH_NI0_LLP_CHAN_MODE_BITMODE32_SHFT 0 +#define SH_NI0_LLP_CHAN_MODE_BITMODE32_MASK 0x0000000000000001 + +/* SH_NI0_LLP_CHAN_MODE_AC_ENCODE */ +/* Description: Enables nearly dc-free encoding for AC-coupling */ +#define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_SHFT 1 +#define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_MASK 0x0000000000000002 + +/* SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING */ +/* Description: Enables automatic tuning of channel skew. */ +#define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_SHFT 2 +#define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_MASK 0x0000000000000004 + +/* SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD */ +/* Description: Enables remote fine tune updates */ +#define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3 +#define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008 + +/* SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD */ +/* Description: Enables quadrature clock in the pfssd */ +#define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4 +#define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010 + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_CONFIG" */ +/* Sets the configuration of LLP and channel */ +/* ==================================================================== */ + +#define SH_NI0_LLP_CONFIG 0x0000000150000020 +#define SH_NI0_LLP_CONFIG_MASK 0x0000003fffffffff +#define SH_NI0_LLP_CONFIG_INIT 0x00000007fc6ffd00 + +/* SH_NI0_LLP_CONFIG_MAXBURST */ +#define SH_NI0_LLP_CONFIG_MAXBURST_SHFT 0 +#define SH_NI0_LLP_CONFIG_MAXBURST_MASK 0x00000000000003ff + +/* SH_NI0_LLP_CONFIG_MAXRETRY */ +#define SH_NI0_LLP_CONFIG_MAXRETRY_SHFT 10 +#define SH_NI0_LLP_CONFIG_MAXRETRY_MASK 0x00000000000ffc00 + +/* SH_NI0_LLP_CONFIG_NULLTIMEOUT */ +#define SH_NI0_LLP_CONFIG_NULLTIMEOUT_SHFT 20 +#define SH_NI0_LLP_CONFIG_NULLTIMEOUT_MASK 0x0000000003f00000 + +/* SH_NI0_LLP_CONFIG_FTU_TIME */ +#define SH_NI0_LLP_CONFIG_FTU_TIME_SHFT 26 +#define SH_NI0_LLP_CONFIG_FTU_TIME_MASK 0x0000003ffc000000 + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_TEST_CTL" */ +/* ==================================================================== */ + +#define SH_NI0_LLP_TEST_CTL 0x0000000150000028 +#define SH_NI0_LLP_TEST_CTL_MASK 0x7ff3f3ffffffffff +#define SH_NI0_LLP_TEST_CTL_INIT 0x000000000a5fffff + +/* SH_NI0_LLP_TEST_CTL_PATTERN */ +/* Description: Send channel data pattern */ +#define SH_NI0_LLP_TEST_CTL_PATTERN_SHFT 0 +#define SH_NI0_LLP_TEST_CTL_PATTERN_MASK 0x000000ffffffffff + +/* SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE */ +/* Description: Enables continuous send of data */ +#define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_SHFT 40 +#define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_MASK 0x0000030000000000 + +/* SH_NI0_LLP_TEST_CTL_WIRE_SEL */ +#define SH_NI0_LLP_TEST_CTL_WIRE_SEL_SHFT 44 +#define SH_NI0_LLP_TEST_CTL_WIRE_SEL_MASK 0x0003f00000000000 + +/* SH_NI0_LLP_TEST_CTL_LFSR_MODE */ +#define SH_NI0_LLP_TEST_CTL_LFSR_MODE_SHFT 52 +#define SH_NI0_LLP_TEST_CTL_LFSR_MODE_MASK 0x0030000000000000 + +/* SH_NI0_LLP_TEST_CTL_NOISE_MODE */ +#define SH_NI0_LLP_TEST_CTL_NOISE_MODE_SHFT 54 +#define SH_NI0_LLP_TEST_CTL_NOISE_MODE_MASK 0x00c0000000000000 + +/* SH_NI0_LLP_TEST_CTL_ARMCAPTURE */ +/* Description: Enable Capture of Next MicroPacket */ +#define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_SHFT 56 +#define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_MASK 0x0100000000000000 + +/* SH_NI0_LLP_TEST_CTL_CAPTURECBONLY */ +/* Description: Only capture a micropacket with a Check Byte error */ +#define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_SHFT 57 +#define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_MASK 0x0200000000000000 + +/* SH_NI0_LLP_TEST_CTL_SENDCBERROR */ +/* Description: Sends a single error */ +#define SH_NI0_LLP_TEST_CTL_SENDCBERROR_SHFT 58 +#define SH_NI0_LLP_TEST_CTL_SENDCBERROR_MASK 0x0400000000000000 + +/* SH_NI0_LLP_TEST_CTL_SENDSNERROR */ +/* Description: Sends a single sequence number error */ +#define SH_NI0_LLP_TEST_CTL_SENDSNERROR_SHFT 59 +#define SH_NI0_LLP_TEST_CTL_SENDSNERROR_MASK 0x0800000000000000 + +/* SH_NI0_LLP_TEST_CTL_FAKESNERROR */ +/* Description: Causes receiver to pretend it saw a sn error */ +#define SH_NI0_LLP_TEST_CTL_FAKESNERROR_SHFT 60 +#define SH_NI0_LLP_TEST_CTL_FAKESNERROR_MASK 0x1000000000000000 + +/* SH_NI0_LLP_TEST_CTL_CAPTURED */ +/* Description: Indicates a Valid Micropacket was captured */ +#define SH_NI0_LLP_TEST_CTL_CAPTURED_SHFT 61 +#define SH_NI0_LLP_TEST_CTL_CAPTURED_MASK 0x2000000000000000 + +/* SH_NI0_LLP_TEST_CTL_CBERROR */ +/* Description: Indicates a Micropacket with a CB error was capture */ +#define SH_NI0_LLP_TEST_CTL_CBERROR_SHFT 62 +#define SH_NI0_LLP_TEST_CTL_CBERROR_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_CAPT_WD1" */ +/* low order 64-bit captured word */ +/* ==================================================================== */ + +#define SH_NI0_LLP_CAPT_WD1 0x0000000150000030 +#define SH_NI0_LLP_CAPT_WD1_MASK 0xffffffffffffffff +#define SH_NI0_LLP_CAPT_WD1_INIT 0x0000000000000000 + +/* SH_NI0_LLP_CAPT_WD1_DATA */ +/* Description: low order 64-bit captured word */ +#define SH_NI0_LLP_CAPT_WD1_DATA_SHFT 0 +#define SH_NI0_LLP_CAPT_WD1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_CAPT_WD2" */ +/* high order 64-bit captured word */ +/* ==================================================================== */ + +#define SH_NI0_LLP_CAPT_WD2 0x0000000150000038 +#define SH_NI0_LLP_CAPT_WD2_MASK 0xffffffffffffffff +#define SH_NI0_LLP_CAPT_WD2_INIT 0x0000000000000000 + +/* SH_NI0_LLP_CAPT_WD2_DATA */ +/* Description: high order 64-bit captured word */ +#define SH_NI0_LLP_CAPT_WD2_DATA_SHFT 0 +#define SH_NI0_LLP_CAPT_WD2_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_CAPT_SBCB" */ +/* captured sideband, sequence, and CRC */ +/* ==================================================================== */ + +#define SH_NI0_LLP_CAPT_SBCB 0x0000000150000040 +#define SH_NI0_LLP_CAPT_SBCB_MASK 0x0000001fffffffff +#define SH_NI0_LLP_CAPT_SBCB_INIT 0x0000000000000000 + +/* SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN */ +/* Description: sideband and sequence */ +#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0 +#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff + +/* SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC */ +/* Description: CRC */ +#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16 +#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000 + +/* SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS */ +/* Description: All CB errors have been sent */ +#define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32 +#define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000 + +/* SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS */ +/* Description: All SN errors have been sent */ +#define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33 +#define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000 + +/* SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS */ +/* Description: All faked SN errors have been sent */ +#define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34 +#define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000 + +/* SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW */ +/* Description: wire charge counter overflowed, valid if llp_mode e */ +#define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35 +#define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000 + +/* SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW */ +/* Description: wire charge counter underflowed, valid if llp_mode */ +/* enabled */ +#define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36 +#define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_ERR" */ +/* ==================================================================== */ + +#define SH_NI0_LLP_ERR 0x0000000150000048 +#define SH_NI0_LLP_ERR_MASK 0x001fffffffffffff +#define SH_NI0_LLP_ERR_INIT 0x0000000000000000 + +/* SH_NI0_LLP_ERR_RX_SN_ERR_COUNT */ +/* Description: Counts the sequence number errors received */ +#define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_SHFT 0 +#define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_MASK 0x00000000000000ff + +/* SH_NI0_LLP_ERR_RX_CB_ERR_COUNT */ +/* Description: Counts the check byte errors received */ +#define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_SHFT 8 +#define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_MASK 0x000000000000ff00 + +/* SH_NI0_LLP_ERR_RETRY_COUNT */ +/* Description: Counts the retries */ +#define SH_NI0_LLP_ERR_RETRY_COUNT_SHFT 16 +#define SH_NI0_LLP_ERR_RETRY_COUNT_MASK 0x0000000000ff0000 + +/* SH_NI0_LLP_ERR_RETRY_TIMEOUT */ +/* Description: Indicates a retry timeout has occured */ +#define SH_NI0_LLP_ERR_RETRY_TIMEOUT_SHFT 24 +#define SH_NI0_LLP_ERR_RETRY_TIMEOUT_MASK 0x0000000001000000 + +/* SH_NI0_LLP_ERR_RCV_LINK_RESET */ +/* Description: Indicates a link reset has been received */ +#define SH_NI0_LLP_ERR_RCV_LINK_RESET_SHFT 25 +#define SH_NI0_LLP_ERR_RCV_LINK_RESET_MASK 0x0000000002000000 + +/* SH_NI0_LLP_ERR_SQUASH */ +/* Description: Indicates a micropacket was squashed */ +#define SH_NI0_LLP_ERR_SQUASH_SHFT 26 +#define SH_NI0_LLP_ERR_SQUASH_MASK 0x0000000004000000 + +/* SH_NI0_LLP_ERR_POWER_NOT_OK */ +/* Description: Detects and traps a loss of power_OK */ +#define SH_NI0_LLP_ERR_POWER_NOT_OK_SHFT 27 +#define SH_NI0_LLP_ERR_POWER_NOT_OK_MASK 0x0000000008000000 + +/* SH_NI0_LLP_ERR_WIRE_CNT */ +/* Description: counts the errors detected on a single wire test */ +#define SH_NI0_LLP_ERR_WIRE_CNT_SHFT 28 +#define SH_NI0_LLP_ERR_WIRE_CNT_MASK 0x000ffffff0000000 + +/* SH_NI0_LLP_ERR_WIRE_OVERFLOW */ +/* Description: wire_error_cnt has overflowed */ +#define SH_NI0_LLP_ERR_WIRE_OVERFLOW_SHFT 52 +#define SH_NI0_LLP_ERR_WIRE_OVERFLOW_MASK 0x0010000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_STAT" */ +/* This register describes the LLP status. */ +/* ==================================================================== */ + +#define SH_NI1_LLP_STAT 0x0000000150002000 +#define SH_NI1_LLP_STAT_MASK 0x000000000000000f +#define SH_NI1_LLP_STAT_INIT 0x0000000000000000 + +/* SH_NI1_LLP_STAT_LINK_RESET_STATE */ +/* Description: Status of LLP link. */ +#define SH_NI1_LLP_STAT_LINK_RESET_STATE_SHFT 0 +#define SH_NI1_LLP_STAT_LINK_RESET_STATE_MASK 0x000000000000000f + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_RESET" */ +/* Writing issues a reset to the network interface */ +/* ==================================================================== */ + +#define SH_NI1_LLP_RESET 0x0000000150002008 +#define SH_NI1_LLP_RESET_MASK 0x0000000000000003 +#define SH_NI1_LLP_RESET_INIT 0x0000000000000000 + +/* SH_NI1_LLP_RESET_LINK */ +/* Description: Send Link Reset. Generates a pulse. */ +#define SH_NI1_LLP_RESET_LINK_SHFT 0 +#define SH_NI1_LLP_RESET_LINK_MASK 0x0000000000000001 + +/* SH_NI1_LLP_RESET_WARM */ +/* Description: Send Warm Reset. Generates a pulse. */ +#define SH_NI1_LLP_RESET_WARM_SHFT 1 +#define SH_NI1_LLP_RESET_WARM_MASK 0x0000000000000002 + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_RESET_EN" */ +/* Controls LLP warm reset propagation */ +/* ==================================================================== */ + +#define SH_NI1_LLP_RESET_EN 0x0000000150002010 +#define SH_NI1_LLP_RESET_EN_MASK 0x0000000000000001 +#define SH_NI1_LLP_RESET_EN_INIT 0x0000000000000001 + +/* SH_NI1_LLP_RESET_EN_OK */ +/* Description: Allow LLP warm reset to reset SHUB */ +#define SH_NI1_LLP_RESET_EN_OK_SHFT 0 +#define SH_NI1_LLP_RESET_EN_OK_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_CHAN_MODE" */ +/* Sets the signaling mode of LLP and channel */ +/* ==================================================================== */ + +#define SH_NI1_LLP_CHAN_MODE 0x0000000150002018 +#define SH_NI1_LLP_CHAN_MODE_MASK 0x000000000000001f +#define SH_NI1_LLP_CHAN_MODE_INIT 0x0000000000000000 + +/* SH_NI1_LLP_CHAN_MODE_BITMODE32 */ +/* Description: Enables 32-bit (plus sideband) channel phits */ +#define SH_NI1_LLP_CHAN_MODE_BITMODE32_SHFT 0 +#define SH_NI1_LLP_CHAN_MODE_BITMODE32_MASK 0x0000000000000001 + +/* SH_NI1_LLP_CHAN_MODE_AC_ENCODE */ +/* Description: Enables nearly dc-free encoding for AC-coupling */ +#define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_SHFT 1 +#define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_MASK 0x0000000000000002 + +/* SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING */ +/* Description: Enables automatic tuning of channel skew. */ +#define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_SHFT 2 +#define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_MASK 0x0000000000000004 + +/* SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD */ +/* Description: Enables remote fine tune updates */ +#define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3 +#define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008 + +/* SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD */ +/* Description: Enables quadrature clock in the pfssd */ +#define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4 +#define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010 + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_CONFIG" */ +/* Sets the configuration of LLP and channel */ +/* ==================================================================== */ + +#define SH_NI1_LLP_CONFIG 0x0000000150002020 +#define SH_NI1_LLP_CONFIG_MASK 0x0000003fffffffff +#define SH_NI1_LLP_CONFIG_INIT 0x00000007fc6ffd00 + +/* SH_NI1_LLP_CONFIG_MAXBURST */ +#define SH_NI1_LLP_CONFIG_MAXBURST_SHFT 0 +#define SH_NI1_LLP_CONFIG_MAXBURST_MASK 0x00000000000003ff + +/* SH_NI1_LLP_CONFIG_MAXRETRY */ +#define SH_NI1_LLP_CONFIG_MAXRETRY_SHFT 10 +#define SH_NI1_LLP_CONFIG_MAXRETRY_MASK 0x00000000000ffc00 + +/* SH_NI1_LLP_CONFIG_NULLTIMEOUT */ +#define SH_NI1_LLP_CONFIG_NULLTIMEOUT_SHFT 20 +#define SH_NI1_LLP_CONFIG_NULLTIMEOUT_MASK 0x0000000003f00000 + +/* SH_NI1_LLP_CONFIG_FTU_TIME */ +#define SH_NI1_LLP_CONFIG_FTU_TIME_SHFT 26 +#define SH_NI1_LLP_CONFIG_FTU_TIME_MASK 0x0000003ffc000000 + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_TEST_CTL" */ +/* ==================================================================== */ + +#define SH_NI1_LLP_TEST_CTL 0x0000000150002028 +#define SH_NI1_LLP_TEST_CTL_MASK 0x7ff3f3ffffffffff +#define SH_NI1_LLP_TEST_CTL_INIT 0x000000000a5fffff + +/* SH_NI1_LLP_TEST_CTL_PATTERN */ +/* Description: Send channel data pattern */ +#define SH_NI1_LLP_TEST_CTL_PATTERN_SHFT 0 +#define SH_NI1_LLP_TEST_CTL_PATTERN_MASK 0x000000ffffffffff + +/* SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE */ +/* Description: Enables continuous send of data */ +#define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_SHFT 40 +#define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_MASK 0x0000030000000000 + +/* SH_NI1_LLP_TEST_CTL_WIRE_SEL */ +#define SH_NI1_LLP_TEST_CTL_WIRE_SEL_SHFT 44 +#define SH_NI1_LLP_TEST_CTL_WIRE_SEL_MASK 0x0003f00000000000 + +/* SH_NI1_LLP_TEST_CTL_LFSR_MODE */ +#define SH_NI1_LLP_TEST_CTL_LFSR_MODE_SHFT 52 +#define SH_NI1_LLP_TEST_CTL_LFSR_MODE_MASK 0x0030000000000000 + +/* SH_NI1_LLP_TEST_CTL_NOISE_MODE */ +#define SH_NI1_LLP_TEST_CTL_NOISE_MODE_SHFT 54 +#define SH_NI1_LLP_TEST_CTL_NOISE_MODE_MASK 0x00c0000000000000 + +/* SH_NI1_LLP_TEST_CTL_ARMCAPTURE */ +/* Description: Enable Capture of Next MicroPacket */ +#define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_SHFT 56 +#define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_MASK 0x0100000000000000 + +/* SH_NI1_LLP_TEST_CTL_CAPTURECBONLY */ +/* Description: Only capture a micropacket with a Check Byte error */ +#define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_SHFT 57 +#define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_MASK 0x0200000000000000 + +/* SH_NI1_LLP_TEST_CTL_SENDCBERROR */ +/* Description: Sends a single error */ +#define SH_NI1_LLP_TEST_CTL_SENDCBERROR_SHFT 58 +#define SH_NI1_LLP_TEST_CTL_SENDCBERROR_MASK 0x0400000000000000 + +/* SH_NI1_LLP_TEST_CTL_SENDSNERROR */ +/* Description: Sends a single sequence number error */ +#define SH_NI1_LLP_TEST_CTL_SENDSNERROR_SHFT 59 +#define SH_NI1_LLP_TEST_CTL_SENDSNERROR_MASK 0x0800000000000000 + +/* SH_NI1_LLP_TEST_CTL_FAKESNERROR */ +/* Description: Causes receiver to pretend it saw a sn error */ +#define SH_NI1_LLP_TEST_CTL_FAKESNERROR_SHFT 60 +#define SH_NI1_LLP_TEST_CTL_FAKESNERROR_MASK 0x1000000000000000 + +/* SH_NI1_LLP_TEST_CTL_CAPTURED */ +/* Description: Indicates a Valid Micropacket was captured */ +#define SH_NI1_LLP_TEST_CTL_CAPTURED_SHFT 61 +#define SH_NI1_LLP_TEST_CTL_CAPTURED_MASK 0x2000000000000000 + +/* SH_NI1_LLP_TEST_CTL_CBERROR */ +/* Description: Indicates a Micropacket with a CB error was capture */ +#define SH_NI1_LLP_TEST_CTL_CBERROR_SHFT 62 +#define SH_NI1_LLP_TEST_CTL_CBERROR_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_CAPT_WD1" */ +/* low order 64-bit captured word */ +/* ==================================================================== */ + +#define SH_NI1_LLP_CAPT_WD1 0x0000000150002030 +#define SH_NI1_LLP_CAPT_WD1_MASK 0xffffffffffffffff +#define SH_NI1_LLP_CAPT_WD1_INIT 0x0000000000000000 + +/* SH_NI1_LLP_CAPT_WD1_DATA */ +/* Description: low order 64-bit captured word */ +#define SH_NI1_LLP_CAPT_WD1_DATA_SHFT 0 +#define SH_NI1_LLP_CAPT_WD1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_CAPT_WD2" */ +/* high order 64-bit captured word */ +/* ==================================================================== */ + +#define SH_NI1_LLP_CAPT_WD2 0x0000000150002038 +#define SH_NI1_LLP_CAPT_WD2_MASK 0xffffffffffffffff +#define SH_NI1_LLP_CAPT_WD2_INIT 0x0000000000000000 + +/* SH_NI1_LLP_CAPT_WD2_DATA */ +/* Description: high order 64-bit captured word */ +#define SH_NI1_LLP_CAPT_WD2_DATA_SHFT 0 +#define SH_NI1_LLP_CAPT_WD2_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_CAPT_SBCB" */ +/* captured sideband, sequence, and CRC */ +/* ==================================================================== */ + +#define SH_NI1_LLP_CAPT_SBCB 0x0000000150002040 +#define SH_NI1_LLP_CAPT_SBCB_MASK 0x0000001fffffffff +#define SH_NI1_LLP_CAPT_SBCB_INIT 0x0000000000000000 + +/* SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN */ +/* Description: sideband and sequence */ +#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0 +#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff + +/* SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC */ +/* Description: CRC */ +#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16 +#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000 + +/* SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS */ +/* Description: All CB errors have been sent */ +#define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32 +#define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000 + +/* SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS */ +/* Description: All SN errors have been sent */ +#define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33 +#define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000 + +/* SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS */ +/* Description: All faked SN errors have been sent */ +#define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34 +#define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000 + +/* SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW */ +/* Description: wire charge counter overflowed, valid if llp_mode e */ +#define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35 +#define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000 + +/* SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW */ +/* Description: wire charge counter underflowed, valid if llp_mode */ +/* enabled */ +#define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36 +#define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_ERR" */ +/* ==================================================================== */ + +#define SH_NI1_LLP_ERR 0x0000000150002048 +#define SH_NI1_LLP_ERR_MASK 0x001fffffffffffff +#define SH_NI1_LLP_ERR_INIT 0x0000000000000000 + +/* SH_NI1_LLP_ERR_RX_SN_ERR_COUNT */ +/* Description: Counts the sequence number errors received */ +#define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_SHFT 0 +#define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_MASK 0x00000000000000ff + +/* SH_NI1_LLP_ERR_RX_CB_ERR_COUNT */ +/* Description: Counts the check byte errors received */ +#define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_SHFT 8 +#define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_MASK 0x000000000000ff00 + +/* SH_NI1_LLP_ERR_RETRY_COUNT */ +/* Description: Counts the retries */ +#define SH_NI1_LLP_ERR_RETRY_COUNT_SHFT 16 +#define SH_NI1_LLP_ERR_RETRY_COUNT_MASK 0x0000000000ff0000 + +/* SH_NI1_LLP_ERR_RETRY_TIMEOUT */ +/* Description: Indicates a retry timeout has occured */ +#define SH_NI1_LLP_ERR_RETRY_TIMEOUT_SHFT 24 +#define SH_NI1_LLP_ERR_RETRY_TIMEOUT_MASK 0x0000000001000000 + +/* SH_NI1_LLP_ERR_RCV_LINK_RESET */ +/* Description: Indicates a link reset has been received */ +#define SH_NI1_LLP_ERR_RCV_LINK_RESET_SHFT 25 +#define SH_NI1_LLP_ERR_RCV_LINK_RESET_MASK 0x0000000002000000 + +/* SH_NI1_LLP_ERR_SQUASH */ +/* Description: Indicates a micropacket was squashed */ +#define SH_NI1_LLP_ERR_SQUASH_SHFT 26 +#define SH_NI1_LLP_ERR_SQUASH_MASK 0x0000000004000000 + +/* SH_NI1_LLP_ERR_POWER_NOT_OK */ +/* Description: Detects and traps a loss of power_OK */ +#define SH_NI1_LLP_ERR_POWER_NOT_OK_SHFT 27 +#define SH_NI1_LLP_ERR_POWER_NOT_OK_MASK 0x0000000008000000 + +/* SH_NI1_LLP_ERR_WIRE_CNT */ +/* Description: counts the errors detected on a single wire test */ +#define SH_NI1_LLP_ERR_WIRE_CNT_SHFT 28 +#define SH_NI1_LLP_ERR_WIRE_CNT_MASK 0x000ffffff0000000 + +/* SH_NI1_LLP_ERR_WIRE_OVERFLOW */ +/* Description: wire_error_cnt has overflowed */ +#define SH_NI1_LLP_ERR_WIRE_OVERFLOW_SHFT 52 +#define SH_NI1_LLP_ERR_WIRE_OVERFLOW_MASK 0x0010000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_LLP_TO_FIFO02_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_LLP_TO_FIFO02_FLOW 0x0000000150001010 +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_MASK 0x3f3f003f3f00bfbf +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 + +/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 + +/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 + +/* SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_LLP_TO_FIFO13_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_LLP_TO_FIFO13_FLOW 0x0000000150001020 +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_MASK 0x3f3f003f3f00bfbf +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 + +/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 + +/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 + +/* SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_LLP_DEBIT_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_LLP_DEBIT_FLOW 0x0000000150001030 +#define SH_XNNI0_LLP_DEBIT_FLOW_MASK 0x1f1f1f1f1f1f1f1f +#define SH_XNNI0_LLP_DEBIT_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0 +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f + +/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8 +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00 + +/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN */ +/* Description: vc1 debit dynamic value */ +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16 +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000 + +/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP */ +/* Description: vc1 debit captured value */ +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24 +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000 + +/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32 +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000 + +/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40 +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000 + +/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN */ +/* Description: vc3 debit dynamic value */ +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48 +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000 + +/* SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP */ +/* Description: vc3 debit captured value */ +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56 +#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_LINK_0_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_LINK_0_FLOW 0x0000000150001040 +#define SH_XNNI0_LINK_0_FLOW_MASK 0x000000007f7f7fbf +#define SH_XNNI0_LINK_0_FLOW_INIT 0x0000000000001800 + +/* SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on vc0 from debit cntr */ +#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 Limit Test */ +#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8 +#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00 + +/* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN */ +/* Description: Dynamic vc0 credit value */ +#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16 +#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000 + +/* SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP */ +/* Description: Captured vc0 credit */ +#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24 +#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_LINK_1_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_LINK_1_FLOW 0x0000000150001050 +#define SH_XNNI0_LINK_1_FLOW_MASK 0x000000007f7f7fbf +#define SH_XNNI0_LINK_1_FLOW_INIT 0x0000000000001800 + +/* SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD */ +/* Description: vc1 withhold */ +#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 +#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED */ +/* Description: Force Credit on vc1 from debit cntr */ +#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 +#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST */ +/* Description: vc1 Limit Test */ +#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8 +#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00 + +/* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN */ +/* Description: Dynamic vc1 credit value */ +#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16 +#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000 + +/* SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP */ +/* Description: Captured vc1 credit */ +#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24 +#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_LINK_2_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_LINK_2_FLOW 0x0000000150001060 +#define SH_XNNI0_LINK_2_FLOW_MASK 0x000000007f7f7fbf +#define SH_XNNI0_LINK_2_FLOW_INIT 0x0000000000001800 + +/* SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 +#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on vc2 from debit cntr */ +#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 +#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 Limit Test */ +#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8 +#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00 + +/* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN */ +/* Description: Dynamic vc2 credit value */ +#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16 +#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000 + +/* SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP */ +/* Description: Captured vc2 credit */ +#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24 +#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_LINK_3_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_LINK_3_FLOW 0x0000000150001070 +#define SH_XNNI0_LINK_3_FLOW_MASK 0x000000007f7f7fbf +#define SH_XNNI0_LINK_3_FLOW_INIT 0x0000000000001800 + +/* SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD */ +/* Description: vc3 withhold */ +#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 +#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED */ +/* Description: Force Credit on vc3 from debit cntr */ +#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 +#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST */ +/* Description: vc3 Limit Test */ +#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8 +#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00 + +/* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN */ +/* Description: Dynamic vc3 credit value */ +#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16 +#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000 + +/* SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP */ +/* Description: Captured vc3 credit */ +#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24 +#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_LLP_TO_FIFO02_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_LLP_TO_FIFO02_FLOW 0x0000000150003010 +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_MASK 0x3f3f003f3f00bfbf +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 + +/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 + +/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 + +/* SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_LLP_TO_FIFO13_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_LLP_TO_FIFO13_FLOW 0x0000000150003020 +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_MASK 0x3f3f003f3f00bfbf +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 + +/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 + +/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 + +/* SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_LLP_DEBIT_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_LLP_DEBIT_FLOW 0x0000000150003030 +#define SH_XNNI1_LLP_DEBIT_FLOW_MASK 0x1f1f1f1f1f1f1f1f +#define SH_XNNI1_LLP_DEBIT_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0 +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f + +/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8 +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00 + +/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN */ +/* Description: vc1 debit dynamic value */ +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16 +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000 + +/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP */ +/* Description: vc1 debit captured value */ +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24 +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000 + +/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32 +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000 + +/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40 +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000 + +/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN */ +/* Description: vc3 debit dynamic value */ +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48 +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000 + +/* SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP */ +/* Description: vc3 debit captured value */ +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56 +#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_LINK_0_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_LINK_0_FLOW 0x0000000150003040 +#define SH_XNNI1_LINK_0_FLOW_MASK 0x000000007f7f7fbf +#define SH_XNNI1_LINK_0_FLOW_INIT 0x0000000000001800 + +/* SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on vc0 from debit cntr */ +#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 Limit Test */ +#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8 +#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00 + +/* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN */ +/* Description: Dynamic vc0 credit value */ +#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16 +#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000 + +/* SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP */ +/* Description: Captured vc0 credit */ +#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24 +#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_LINK_1_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_LINK_1_FLOW 0x0000000150003050 +#define SH_XNNI1_LINK_1_FLOW_MASK 0x000000007f7f7fbf +#define SH_XNNI1_LINK_1_FLOW_INIT 0x0000000000001800 + +/* SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD */ +/* Description: vc1 withhold */ +#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 +#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED */ +/* Description: Force Credit on vc1 from debit cntr */ +#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 +#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST */ +/* Description: vc1 Limit Test */ +#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8 +#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00 + +/* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN */ +/* Description: Dynamic vc1 credit value */ +#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16 +#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000 + +/* SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP */ +/* Description: Captured vc1 credit */ +#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24 +#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_LINK_2_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_LINK_2_FLOW 0x0000000150003060 +#define SH_XNNI1_LINK_2_FLOW_MASK 0x000000007f7f7fbf +#define SH_XNNI1_LINK_2_FLOW_INIT 0x0000000000001800 + +/* SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 +#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on vc2 from debit cntr */ +#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 +#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 Limit Test */ +#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8 +#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00 + +/* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN */ +/* Description: Dynamic vc2 credit value */ +#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16 +#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000 + +/* SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP */ +/* Description: Captured vc2 credit */ +#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24 +#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_LINK_3_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_LINK_3_FLOW 0x0000000150003070 +#define SH_XNNI1_LINK_3_FLOW_MASK 0x000000007f7f7fbf +#define SH_XNNI1_LINK_3_FLOW_INIT 0x0000000000001800 + +/* SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD */ +/* Description: vc3 withhold */ +#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 +#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED */ +/* Description: Force Credit on vc3 from debit cntr */ +#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 +#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST */ +/* Description: vc3 Limit Test */ +#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8 +#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00 + +/* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN */ +/* Description: Dynamic vc3 credit value */ +#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16 +#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000 + +/* SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP */ +/* Description: Captured vc3 credit */ +#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24 +#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000 + +/* ==================================================================== */ +/* Register "SH_IILB_LOCAL_TABLE" */ +/* local lookup table */ +/* ==================================================================== */ + +#define SH_IILB_LOCAL_TABLE 0x0000000150020000 +#define SH_IILB_LOCAL_TABLE_MASK 0x800000000000003f +#define SH_IILB_LOCAL_TABLE_MEMDEPTH 128 +#define SH_IILB_LOCAL_TABLE_INIT 0x0000000000000000 + +/* SH_IILB_LOCAL_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_IILB_LOCAL_TABLE_DIR0_SHFT 0 +#define SH_IILB_LOCAL_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_IILB_LOCAL_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_IILB_LOCAL_TABLE_V0_SHFT 4 +#define SH_IILB_LOCAL_TABLE_V0_MASK 0x0000000000000010 + +/* SH_IILB_LOCAL_TABLE_NI_SEL0 */ +/* Description: ni select for requests */ +#define SH_IILB_LOCAL_TABLE_NI_SEL0_SHFT 5 +#define SH_IILB_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020 + +/* SH_IILB_LOCAL_TABLE_VALID */ +/* Description: Indicates that this entry is valid */ +#define SH_IILB_LOCAL_TABLE_VALID_SHFT 63 +#define SH_IILB_LOCAL_TABLE_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_IILB_GLOBAL_TABLE" */ +/* global lookup table */ +/* ==================================================================== */ + +#define SH_IILB_GLOBAL_TABLE 0x0000000150020400 +#define SH_IILB_GLOBAL_TABLE_MASK 0x800000000000003f +#define SH_IILB_GLOBAL_TABLE_MEMDEPTH 16 +#define SH_IILB_GLOBAL_TABLE_INIT 0x0000000000000000 + +/* SH_IILB_GLOBAL_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_IILB_GLOBAL_TABLE_DIR0_SHFT 0 +#define SH_IILB_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_IILB_GLOBAL_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_IILB_GLOBAL_TABLE_V0_SHFT 4 +#define SH_IILB_GLOBAL_TABLE_V0_MASK 0x0000000000000010 + +/* SH_IILB_GLOBAL_TABLE_NI_SEL0 */ +/* Description: ni select for requests */ +#define SH_IILB_GLOBAL_TABLE_NI_SEL0_SHFT 5 +#define SH_IILB_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020 + +/* SH_IILB_GLOBAL_TABLE_VALID */ +/* Description: Indicates that this entry is valid */ +#define SH_IILB_GLOBAL_TABLE_VALID_SHFT 63 +#define SH_IILB_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_IILB_OVER_RIDE_TABLE" */ +/* If enabled, bypass the Global/Local tables */ +/* ==================================================================== */ + +#define SH_IILB_OVER_RIDE_TABLE 0x0000000150020480 +#define SH_IILB_OVER_RIDE_TABLE_MASK 0x800000000000003f +#define SH_IILB_OVER_RIDE_TABLE_INIT 0x8000000000000000 + +/* SH_IILB_OVER_RIDE_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_IILB_OVER_RIDE_TABLE_DIR0_SHFT 0 +#define SH_IILB_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_IILB_OVER_RIDE_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_IILB_OVER_RIDE_TABLE_V0_SHFT 4 +#define SH_IILB_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 + +/* SH_IILB_OVER_RIDE_TABLE_NI_SEL0 */ +/* Description: ni select */ +#define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_SHFT 5 +#define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020 + +/* SH_IILB_OVER_RIDE_TABLE_ENABLE */ +/* Description: Indicates that this entry is enabled */ +#define SH_IILB_OVER_RIDE_TABLE_ENABLE_SHFT 63 +#define SH_IILB_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_IILB_RSP_PLANE_HINT" */ +/* If enabled, invert incoming response only plane hint bit before lo */ +/* ==================================================================== */ + +#define SH_IILB_RSP_PLANE_HINT 0x0000000150020488 +#define SH_IILB_RSP_PLANE_HINT_MASK 0x0000000000000000 +#define SH_IILB_RSP_PLANE_HINT_INIT 0x0000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_LOCAL_TABLE" */ +/* local lookup table */ +/* ==================================================================== */ + +#define SH_PI_LOCAL_TABLE 0x0000000150021000 +#define SH_PI_LOCAL_TABLE_MASK 0x8000000000003f3f +#define SH_PI_LOCAL_TABLE_MEMDEPTH 128 +#define SH_PI_LOCAL_TABLE_INIT 0x0000000000000000 + +/* SH_PI_LOCAL_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_PI_LOCAL_TABLE_DIR0_SHFT 0 +#define SH_PI_LOCAL_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_PI_LOCAL_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_PI_LOCAL_TABLE_V0_SHFT 4 +#define SH_PI_LOCAL_TABLE_V0_MASK 0x0000000000000010 + +/* SH_PI_LOCAL_TABLE_NI_SEL0 */ +/* Description: ni select for requests */ +#define SH_PI_LOCAL_TABLE_NI_SEL0_SHFT 5 +#define SH_PI_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020 + +/* SH_PI_LOCAL_TABLE_DIR1 */ +#define SH_PI_LOCAL_TABLE_DIR1_SHFT 8 +#define SH_PI_LOCAL_TABLE_DIR1_MASK 0x0000000000000f00 + +/* SH_PI_LOCAL_TABLE_V1 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_PI_LOCAL_TABLE_V1_SHFT 12 +#define SH_PI_LOCAL_TABLE_V1_MASK 0x0000000000001000 + +/* SH_PI_LOCAL_TABLE_NI_SEL1 */ +/* Description: ni select for plane-hint 1 */ +#define SH_PI_LOCAL_TABLE_NI_SEL1_SHFT 13 +#define SH_PI_LOCAL_TABLE_NI_SEL1_MASK 0x0000000000002000 + +/* SH_PI_LOCAL_TABLE_VALID */ +/* Description: Indicates that this entry is valid */ +#define SH_PI_LOCAL_TABLE_VALID_SHFT 63 +#define SH_PI_LOCAL_TABLE_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_GLOBAL_TABLE" */ +/* global lookup table */ +/* ==================================================================== */ + +#define SH_PI_GLOBAL_TABLE 0x0000000150021400 +#define SH_PI_GLOBAL_TABLE_MASK 0x8000000000003f3f +#define SH_PI_GLOBAL_TABLE_MEMDEPTH 16 +#define SH_PI_GLOBAL_TABLE_INIT 0x0000000000000000 + +/* SH_PI_GLOBAL_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_PI_GLOBAL_TABLE_DIR0_SHFT 0 +#define SH_PI_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_PI_GLOBAL_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_PI_GLOBAL_TABLE_V0_SHFT 4 +#define SH_PI_GLOBAL_TABLE_V0_MASK 0x0000000000000010 + +/* SH_PI_GLOBAL_TABLE_NI_SEL0 */ +/* Description: ni select for requests */ +#define SH_PI_GLOBAL_TABLE_NI_SEL0_SHFT 5 +#define SH_PI_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020 + +/* SH_PI_GLOBAL_TABLE_DIR1 */ +#define SH_PI_GLOBAL_TABLE_DIR1_SHFT 8 +#define SH_PI_GLOBAL_TABLE_DIR1_MASK 0x0000000000000f00 + +/* SH_PI_GLOBAL_TABLE_V1 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_PI_GLOBAL_TABLE_V1_SHFT 12 +#define SH_PI_GLOBAL_TABLE_V1_MASK 0x0000000000001000 + +/* SH_PI_GLOBAL_TABLE_NI_SEL1 */ +/* Description: ni select for plane-hint 1 */ +#define SH_PI_GLOBAL_TABLE_NI_SEL1_SHFT 13 +#define SH_PI_GLOBAL_TABLE_NI_SEL1_MASK 0x0000000000002000 + +/* SH_PI_GLOBAL_TABLE_VALID */ +/* Description: Indicates that this entry is valid */ +#define SH_PI_GLOBAL_TABLE_VALID_SHFT 63 +#define SH_PI_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_OVER_RIDE_TABLE" */ +/* If enabled, bypass the Global/Local tables */ +/* ==================================================================== */ + +#define SH_PI_OVER_RIDE_TABLE 0x0000000150021480 +#define SH_PI_OVER_RIDE_TABLE_MASK 0x8000000000003f3f +#define SH_PI_OVER_RIDE_TABLE_INIT 0x8000000000002000 + +/* SH_PI_OVER_RIDE_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_PI_OVER_RIDE_TABLE_DIR0_SHFT 0 +#define SH_PI_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_PI_OVER_RIDE_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_PI_OVER_RIDE_TABLE_V0_SHFT 4 +#define SH_PI_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 + +/* SH_PI_OVER_RIDE_TABLE_NI_SEL0 */ +/* Description: ni select */ +#define SH_PI_OVER_RIDE_TABLE_NI_SEL0_SHFT 5 +#define SH_PI_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020 + +/* SH_PI_OVER_RIDE_TABLE_DIR1 */ +#define SH_PI_OVER_RIDE_TABLE_DIR1_SHFT 8 +#define SH_PI_OVER_RIDE_TABLE_DIR1_MASK 0x0000000000000f00 + +/* SH_PI_OVER_RIDE_TABLE_V1 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_PI_OVER_RIDE_TABLE_V1_SHFT 12 +#define SH_PI_OVER_RIDE_TABLE_V1_MASK 0x0000000000001000 + +/* SH_PI_OVER_RIDE_TABLE_NI_SEL1 */ +/* Description: ni select */ +#define SH_PI_OVER_RIDE_TABLE_NI_SEL1_SHFT 13 +#define SH_PI_OVER_RIDE_TABLE_NI_SEL1_MASK 0x0000000000002000 + +/* SH_PI_OVER_RIDE_TABLE_ENABLE */ +/* Description: Indicates that this entry is enabled */ +#define SH_PI_OVER_RIDE_TABLE_ENABLE_SHFT 63 +#define SH_PI_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_RSP_PLANE_HINT" */ +/* If enabled, invert incoming response only plane hint bit before lo */ +/* ==================================================================== */ + +#define SH_PI_RSP_PLANE_HINT 0x0000000150021488 +#define SH_PI_RSP_PLANE_HINT_MASK 0x0000000000000001 +#define SH_PI_RSP_PLANE_HINT_INIT 0x0000000000000000 + +/* SH_PI_RSP_PLANE_HINT_INVERT */ +/* Description: Invert Response Plane Hint */ +#define SH_PI_RSP_PLANE_HINT_INVERT_SHFT 0 +#define SH_PI_RSP_PLANE_HINT_INVERT_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_NI0_LOCAL_TABLE" */ +/* local lookup table */ +/* ==================================================================== */ + +#define SH_NI0_LOCAL_TABLE 0x0000000150022000 +#define SH_NI0_LOCAL_TABLE_MASK 0x800000000000001f +#define SH_NI0_LOCAL_TABLE_MEMDEPTH 128 +#define SH_NI0_LOCAL_TABLE_INIT 0x0000000000000000 + +/* SH_NI0_LOCAL_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_NI0_LOCAL_TABLE_DIR0_SHFT 0 +#define SH_NI0_LOCAL_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_NI0_LOCAL_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_NI0_LOCAL_TABLE_V0_SHFT 4 +#define SH_NI0_LOCAL_TABLE_V0_MASK 0x0000000000000010 + +/* SH_NI0_LOCAL_TABLE_VALID */ +/* Description: Indicates that this entry is valid */ +#define SH_NI0_LOCAL_TABLE_VALID_SHFT 63 +#define SH_NI0_LOCAL_TABLE_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_GLOBAL_TABLE" */ +/* global lookup table */ +/* ==================================================================== */ + +#define SH_NI0_GLOBAL_TABLE 0x0000000150022400 +#define SH_NI0_GLOBAL_TABLE_MASK 0x800000000000001f +#define SH_NI0_GLOBAL_TABLE_MEMDEPTH 16 +#define SH_NI0_GLOBAL_TABLE_INIT 0x0000000000000000 + +/* SH_NI0_GLOBAL_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_NI0_GLOBAL_TABLE_DIR0_SHFT 0 +#define SH_NI0_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_NI0_GLOBAL_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_NI0_GLOBAL_TABLE_V0_SHFT 4 +#define SH_NI0_GLOBAL_TABLE_V0_MASK 0x0000000000000010 + +/* SH_NI0_GLOBAL_TABLE_VALID */ +/* Description: Indicates that this entry is valid */ +#define SH_NI0_GLOBAL_TABLE_VALID_SHFT 63 +#define SH_NI0_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_OVER_RIDE_TABLE" */ +/* If enabled, bypass the Global/Local tables */ +/* ==================================================================== */ + +#define SH_NI0_OVER_RIDE_TABLE 0x0000000150022480 +#define SH_NI0_OVER_RIDE_TABLE_MASK 0x800000000000001f +#define SH_NI0_OVER_RIDE_TABLE_INIT 0x8000000000000000 + +/* SH_NI0_OVER_RIDE_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_NI0_OVER_RIDE_TABLE_DIR0_SHFT 0 +#define SH_NI0_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_NI0_OVER_RIDE_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_NI0_OVER_RIDE_TABLE_V0_SHFT 4 +#define SH_NI0_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 + +/* SH_NI0_OVER_RIDE_TABLE_ENABLE */ +/* Description: Indicates that this entry is enabled */ +#define SH_NI0_OVER_RIDE_TABLE_ENABLE_SHFT 63 +#define SH_NI0_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_RSP_PLANE_HINT" */ +/* If enabled, invert incoming response only plane hint bit before lo */ +/* ==================================================================== */ + +#define SH_NI0_RSP_PLANE_HINT 0x0000000150022488 +#define SH_NI0_RSP_PLANE_HINT_MASK 0x0000000000000000 +#define SH_NI0_RSP_PLANE_HINT_INIT 0x0000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_LOCAL_TABLE" */ +/* local lookup table */ +/* ==================================================================== */ + +#define SH_NI1_LOCAL_TABLE 0x0000000150023000 +#define SH_NI1_LOCAL_TABLE_MASK 0x800000000000001f +#define SH_NI1_LOCAL_TABLE_MEMDEPTH 128 +#define SH_NI1_LOCAL_TABLE_INIT 0x0000000000000000 + +/* SH_NI1_LOCAL_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_NI1_LOCAL_TABLE_DIR0_SHFT 0 +#define SH_NI1_LOCAL_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_NI1_LOCAL_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_NI1_LOCAL_TABLE_V0_SHFT 4 +#define SH_NI1_LOCAL_TABLE_V0_MASK 0x0000000000000010 + +/* SH_NI1_LOCAL_TABLE_VALID */ +/* Description: Indicates that this entry is valid */ +#define SH_NI1_LOCAL_TABLE_VALID_SHFT 63 +#define SH_NI1_LOCAL_TABLE_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_GLOBAL_TABLE" */ +/* global lookup table */ +/* ==================================================================== */ + +#define SH_NI1_GLOBAL_TABLE 0x0000000150023400 +#define SH_NI1_GLOBAL_TABLE_MASK 0x800000000000001f +#define SH_NI1_GLOBAL_TABLE_MEMDEPTH 16 +#define SH_NI1_GLOBAL_TABLE_INIT 0x0000000000000000 + +/* SH_NI1_GLOBAL_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_NI1_GLOBAL_TABLE_DIR0_SHFT 0 +#define SH_NI1_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_NI1_GLOBAL_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_NI1_GLOBAL_TABLE_V0_SHFT 4 +#define SH_NI1_GLOBAL_TABLE_V0_MASK 0x0000000000000010 + +/* SH_NI1_GLOBAL_TABLE_VALID */ +/* Description: Indicates that this entry is valid */ +#define SH_NI1_GLOBAL_TABLE_VALID_SHFT 63 +#define SH_NI1_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_OVER_RIDE_TABLE" */ +/* If enabled, bypass the Global/Local tables */ +/* ==================================================================== */ + +#define SH_NI1_OVER_RIDE_TABLE 0x0000000150023480 +#define SH_NI1_OVER_RIDE_TABLE_MASK 0x800000000000001f +#define SH_NI1_OVER_RIDE_TABLE_INIT 0x8000000000000000 + +/* SH_NI1_OVER_RIDE_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_NI1_OVER_RIDE_TABLE_DIR0_SHFT 0 +#define SH_NI1_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_NI1_OVER_RIDE_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_NI1_OVER_RIDE_TABLE_V0_SHFT 4 +#define SH_NI1_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 + +/* SH_NI1_OVER_RIDE_TABLE_ENABLE */ +/* Description: Indicates that this entry is enabled */ +#define SH_NI1_OVER_RIDE_TABLE_ENABLE_SHFT 63 +#define SH_NI1_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_RSP_PLANE_HINT" */ +/* If enabled, invert incoming response only plane hint bit before lo */ +/* ==================================================================== */ + +#define SH_NI1_RSP_PLANE_HINT 0x0000000150023488 +#define SH_NI1_RSP_PLANE_HINT_MASK 0x0000000000000000 +#define SH_NI1_RSP_PLANE_HINT_INIT 0x0000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_LOCAL_TABLE" */ +/* local lookup table */ +/* ==================================================================== */ + +#define SH_MD_LOCAL_TABLE 0x0000000150024000 +#define SH_MD_LOCAL_TABLE_MASK 0x8000000000003f3f +#define SH_MD_LOCAL_TABLE_MEMDEPTH 128 +#define SH_MD_LOCAL_TABLE_INIT 0x0000000000000000 + +/* SH_MD_LOCAL_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_MD_LOCAL_TABLE_DIR0_SHFT 0 +#define SH_MD_LOCAL_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_MD_LOCAL_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_MD_LOCAL_TABLE_V0_SHFT 4 +#define SH_MD_LOCAL_TABLE_V0_MASK 0x0000000000000010 + +/* SH_MD_LOCAL_TABLE_NI_SEL0 */ +/* Description: ni select for requests */ +#define SH_MD_LOCAL_TABLE_NI_SEL0_SHFT 5 +#define SH_MD_LOCAL_TABLE_NI_SEL0_MASK 0x0000000000000020 + +/* SH_MD_LOCAL_TABLE_DIR1 */ +#define SH_MD_LOCAL_TABLE_DIR1_SHFT 8 +#define SH_MD_LOCAL_TABLE_DIR1_MASK 0x0000000000000f00 + +/* SH_MD_LOCAL_TABLE_V1 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_MD_LOCAL_TABLE_V1_SHFT 12 +#define SH_MD_LOCAL_TABLE_V1_MASK 0x0000000000001000 + +/* SH_MD_LOCAL_TABLE_NI_SEL1 */ +/* Description: ni select for plane-hint 1 */ +#define SH_MD_LOCAL_TABLE_NI_SEL1_SHFT 13 +#define SH_MD_LOCAL_TABLE_NI_SEL1_MASK 0x0000000000002000 + +/* SH_MD_LOCAL_TABLE_VALID */ +/* Description: Indicates that this entry is valid */ +#define SH_MD_LOCAL_TABLE_VALID_SHFT 63 +#define SH_MD_LOCAL_TABLE_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_GLOBAL_TABLE" */ +/* global lookup table */ +/* ==================================================================== */ + +#define SH_MD_GLOBAL_TABLE 0x0000000150024400 +#define SH_MD_GLOBAL_TABLE_MASK 0x8000000000003f3f +#define SH_MD_GLOBAL_TABLE_MEMDEPTH 16 +#define SH_MD_GLOBAL_TABLE_INIT 0x0000000000000000 + +/* SH_MD_GLOBAL_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_MD_GLOBAL_TABLE_DIR0_SHFT 0 +#define SH_MD_GLOBAL_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_MD_GLOBAL_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_MD_GLOBAL_TABLE_V0_SHFT 4 +#define SH_MD_GLOBAL_TABLE_V0_MASK 0x0000000000000010 + +/* SH_MD_GLOBAL_TABLE_NI_SEL0 */ +/* Description: ni select for requests */ +#define SH_MD_GLOBAL_TABLE_NI_SEL0_SHFT 5 +#define SH_MD_GLOBAL_TABLE_NI_SEL0_MASK 0x0000000000000020 + +/* SH_MD_GLOBAL_TABLE_DIR1 */ +#define SH_MD_GLOBAL_TABLE_DIR1_SHFT 8 +#define SH_MD_GLOBAL_TABLE_DIR1_MASK 0x0000000000000f00 + +/* SH_MD_GLOBAL_TABLE_V1 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_MD_GLOBAL_TABLE_V1_SHFT 12 +#define SH_MD_GLOBAL_TABLE_V1_MASK 0x0000000000001000 + +/* SH_MD_GLOBAL_TABLE_NI_SEL1 */ +/* Description: ni select for plane-hint 1 */ +#define SH_MD_GLOBAL_TABLE_NI_SEL1_SHFT 13 +#define SH_MD_GLOBAL_TABLE_NI_SEL1_MASK 0x0000000000002000 + +/* SH_MD_GLOBAL_TABLE_VALID */ +/* Description: Indicates that this entry is valid */ +#define SH_MD_GLOBAL_TABLE_VALID_SHFT 63 +#define SH_MD_GLOBAL_TABLE_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_OVER_RIDE_TABLE" */ +/* If enabled, bypass the Global/Local tables */ +/* ==================================================================== */ + +#define SH_MD_OVER_RIDE_TABLE 0x0000000150024480 +#define SH_MD_OVER_RIDE_TABLE_MASK 0x8000000000003f3f +#define SH_MD_OVER_RIDE_TABLE_INIT 0x8000000000002000 + +/* SH_MD_OVER_RIDE_TABLE_DIR0 */ +/* Description: Direction field for next chip */ +#define SH_MD_OVER_RIDE_TABLE_DIR0_SHFT 0 +#define SH_MD_OVER_RIDE_TABLE_DIR0_MASK 0x000000000000000f + +/* SH_MD_OVER_RIDE_TABLE_V0 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_MD_OVER_RIDE_TABLE_V0_SHFT 4 +#define SH_MD_OVER_RIDE_TABLE_V0_MASK 0x0000000000000010 + +/* SH_MD_OVER_RIDE_TABLE_NI_SEL0 */ +/* Description: ni select */ +#define SH_MD_OVER_RIDE_TABLE_NI_SEL0_SHFT 5 +#define SH_MD_OVER_RIDE_TABLE_NI_SEL0_MASK 0x0000000000000020 + +/* SH_MD_OVER_RIDE_TABLE_DIR1 */ +#define SH_MD_OVER_RIDE_TABLE_DIR1_SHFT 8 +#define SH_MD_OVER_RIDE_TABLE_DIR1_MASK 0x0000000000000f00 + +/* SH_MD_OVER_RIDE_TABLE_V1 */ +/* Description: Low bit of virtual channel for next chip */ +#define SH_MD_OVER_RIDE_TABLE_V1_SHFT 12 +#define SH_MD_OVER_RIDE_TABLE_V1_MASK 0x0000000000001000 + +/* SH_MD_OVER_RIDE_TABLE_NI_SEL1 */ +/* Description: ni select */ +#define SH_MD_OVER_RIDE_TABLE_NI_SEL1_SHFT 13 +#define SH_MD_OVER_RIDE_TABLE_NI_SEL1_MASK 0x0000000000002000 + +/* SH_MD_OVER_RIDE_TABLE_ENABLE */ +/* Description: Indicates that this entry is enabled */ +#define SH_MD_OVER_RIDE_TABLE_ENABLE_SHFT 63 +#define SH_MD_OVER_RIDE_TABLE_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_RSP_PLANE_HINT" */ +/* If enabled, invert incoming response only plane hint bit before lo */ +/* ==================================================================== */ + +#define SH_MD_RSP_PLANE_HINT 0x0000000150024488 +#define SH_MD_RSP_PLANE_HINT_MASK 0x0000000000000001 +#define SH_MD_RSP_PLANE_HINT_INIT 0x0000000000000000 + +/* SH_MD_RSP_PLANE_HINT_INVERT */ +/* Description: Invert Response Plane Hint */ +#define SH_MD_RSP_PLANE_HINT_INVERT_SHFT 0 +#define SH_MD_RSP_PLANE_HINT_INVERT_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_LB_LIQ_CTL" */ +/* Local Block LIQ Control */ +/* ==================================================================== */ + +#define SH_LB_LIQ_CTL 0x0000000110040000 +#define SH_LB_LIQ_CTL_MASK 0x0000000000070f1f +#define SH_LB_LIQ_CTL_INIT 0x0000000000000000 + +/* SH_LB_LIQ_CTL_LIQ_REQ_CTL */ +/* Description: LIQ Request Control */ +#define SH_LB_LIQ_CTL_LIQ_REQ_CTL_SHFT 0 +#define SH_LB_LIQ_CTL_LIQ_REQ_CTL_MASK 0x000000000000001f + +/* SH_LB_LIQ_CTL_LIQ_RPL_CTL */ +/* Description: LIQ Reply Control */ +#define SH_LB_LIQ_CTL_LIQ_RPL_CTL_SHFT 8 +#define SH_LB_LIQ_CTL_LIQ_RPL_CTL_MASK 0x0000000000000f00 + +/* SH_LB_LIQ_CTL_FORCE_RQ_CREDIT */ +/* Description: Force request credit */ +#define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_SHFT 16 +#define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_MASK 0x0000000000010000 + +/* SH_LB_LIQ_CTL_FORCE_RP_CREDIT */ +/* Description: Force reply credit */ +#define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_SHFT 17 +#define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_MASK 0x0000000000020000 + +/* SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT */ +/* Description: Force linvv credit */ +#define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_SHFT 18 +#define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_MASK 0x0000000000040000 + +/* ==================================================================== */ +/* Register "SH_LB_LOQ_CTL" */ +/* Local Block LOQ Control */ +/* ==================================================================== */ + +#define SH_LB_LOQ_CTL 0x0000000110040080 +#define SH_LB_LOQ_CTL_MASK 0x0000000000000003 +#define SH_LB_LOQ_CTL_INIT 0x0000000000000000 + +/* SH_LB_LOQ_CTL_LOQ_REQ_CTL */ +/* Description: LOQ Request Control */ +#define SH_LB_LOQ_CTL_LOQ_REQ_CTL_SHFT 0 +#define SH_LB_LOQ_CTL_LOQ_REQ_CTL_MASK 0x0000000000000001 + +/* SH_LB_LOQ_CTL_LOQ_RPL_CTL */ +/* Description: LOQ Reply Control */ +#define SH_LB_LOQ_CTL_LOQ_RPL_CTL_SHFT 1 +#define SH_LB_LOQ_CTL_LOQ_RPL_CTL_MASK 0x0000000000000002 + +/* ==================================================================== */ +/* Register "SH_LB_MAX_REP_CREDIT_CNT" */ +/* Maximum number of reply credits from XN */ +/* ==================================================================== */ + +#define SH_LB_MAX_REP_CREDIT_CNT 0x0000000110040100 +#define SH_LB_MAX_REP_CREDIT_CNT_MASK 0x000000000000001f +#define SH_LB_MAX_REP_CREDIT_CNT_INIT 0x000000000000001f + +/* SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT */ +/* Description: Max reply credits */ +#define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_SHFT 0 +#define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_MASK 0x000000000000001f + +/* ==================================================================== */ +/* Register "SH_LB_MAX_REQ_CREDIT_CNT" */ +/* Maximum number of request credits from XN */ +/* ==================================================================== */ + +#define SH_LB_MAX_REQ_CREDIT_CNT 0x0000000110040180 +#define SH_LB_MAX_REQ_CREDIT_CNT_MASK 0x000000000000001f +#define SH_LB_MAX_REQ_CREDIT_CNT_INIT 0x000000000000001f + +/* SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT */ +/* Description: Max request credits */ +#define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_SHFT 0 +#define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_MASK 0x000000000000001f + +/* ==================================================================== */ +/* Register "SH_PIO_TIME_OUT" */ +/* Local Block PIO time out value */ +/* ==================================================================== */ + +#define SH_PIO_TIME_OUT 0x0000000110040200 +#define SH_PIO_TIME_OUT_MASK 0x000000000000ffff +#define SH_PIO_TIME_OUT_INIT 0x0000000000000400 + +/* SH_PIO_TIME_OUT_VALUE */ +/* Description: PIO time out value */ +#define SH_PIO_TIME_OUT_VALUE_SHFT 0 +#define SH_PIO_TIME_OUT_VALUE_MASK 0x000000000000ffff + +/* ==================================================================== */ +/* Register "SH_PIO_NACK_RESET" */ +/* Local Block PIO Reset for nack counters */ +/* ==================================================================== */ + +#define SH_PIO_NACK_RESET 0x0000000110040280 +#define SH_PIO_NACK_RESET_MASK 0x0000000000000001 +#define SH_PIO_NACK_RESET_INIT 0x0000000000000000 + +/* SH_PIO_NACK_RESET_PULSE */ +/* Description: PIO nack counter reset */ +#define SH_PIO_NACK_RESET_PULSE_SHFT 0 +#define SH_PIO_NACK_RESET_PULSE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_CONVEYOR_BELT_TIME_OUT" */ +/* Local Block conveyor belt time out value */ +/* ==================================================================== */ + +#define SH_CONVEYOR_BELT_TIME_OUT 0x0000000110040300 +#define SH_CONVEYOR_BELT_TIME_OUT_MASK 0x0000000000000fff +#define SH_CONVEYOR_BELT_TIME_OUT_INIT 0x0000000000000000 + +/* SH_CONVEYOR_BELT_TIME_OUT_VALUE */ +/* Description: Conveyor belt time out value */ +#define SH_CONVEYOR_BELT_TIME_OUT_VALUE_SHFT 0 +#define SH_CONVEYOR_BELT_TIME_OUT_VALUE_MASK 0x0000000000000fff + +/* ==================================================================== */ +/* Register "SH_LB_CREDIT_STATUS" */ +/* Credit Counter Status Register */ +/* ==================================================================== */ + +#define SH_LB_CREDIT_STATUS 0x0000000110050000 +#define SH_LB_CREDIT_STATUS_MASK 0x000000000ffff3df +#define SH_LB_CREDIT_STATUS_INIT 0x0000000000000000 + +/* SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT */ +/* Description: LIQ request queue credit counter */ +#define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_SHFT 0 +#define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_MASK 0x000000000000001f + +/* SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT */ +/* Description: LIQ reply queue credit counter */ +#define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_SHFT 6 +#define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_MASK 0x00000000000003c0 + +/* SH_LB_CREDIT_STATUS_LINVV_CREDIT */ +/* Description: LINVV credit counter */ +#define SH_LB_CREDIT_STATUS_LINVV_CREDIT_SHFT 12 +#define SH_LB_CREDIT_STATUS_LINVV_CREDIT_MASK 0x000000000003f000 + +/* SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT */ +/* Description: LOQ request queue credit counter */ +#define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_SHFT 18 +#define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_MASK 0x00000000007c0000 + +/* SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT */ +/* Description: LOQ reply queue credit counter */ +#define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_SHFT 23 +#define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_MASK 0x000000000f800000 + +/* ==================================================================== */ +/* Register "SH_LB_DEBUG_LOCAL_SEL" */ +/* LB Debug Port Select */ +/* ==================================================================== */ + +#define SH_LB_DEBUG_LOCAL_SEL 0x0000000110050080 +#define SH_LB_DEBUG_LOCAL_SEL_MASK 0xf777777777777777 +#define SH_LB_DEBUG_LOCAL_SEL_INIT 0x0000000000000000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL */ +/* Description: Nibble 0 Chiplet select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL */ +/* Description: Nibble 1 Chiplet select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL */ +/* Description: Nibble 2 Chiplet select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL */ +/* Description: Nibble 3 Chiplet select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL */ +/* Description: Nibble 4 Chiplet select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL */ +/* Description: Nibble 5 Chiplet select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL */ +/* Description: Nibble 6 Chiplet select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL */ +/* Description: Nibble 7 Chiplet select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 + +/* SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE */ +/* Description: Enable trigger on bit 32 of Analyzer data */ +#define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_SHFT 63 +#define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_LB_DEBUG_PERF_SEL" */ +/* LB Debug Port Performance Select */ +/* ==================================================================== */ + +#define SH_LB_DEBUG_PERF_SEL 0x0000000110050100 +#define SH_LB_DEBUG_PERF_SEL_MASK 0x7777777777777777 +#define SH_LB_DEBUG_PERF_SEL_INIT 0x0000000000000000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL */ +/* Description: Nibble 0 Chiplet select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL */ +/* Description: Nibble 1 Chiplet select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL */ +/* Description: Nibble 2 Chiplet select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL */ +/* Description: Nibble 3 Chiplet select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL */ +/* Description: Nibble 4 Chiplet select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL */ +/* Description: Nibble 5 Chiplet select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL */ +/* Description: Nibble 6 Chiplet select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL */ +/* Description: Nibble 7 Chiplet select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 + +/* SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_LB_DEBUG_TRIG_SEL" */ +/* LB Debug Trigger Select */ +/* ==================================================================== */ + +#define SH_LB_DEBUG_TRIG_SEL 0x0000000110050180 +#define SH_LB_DEBUG_TRIG_SEL_MASK 0x7777777777777777 +#define SH_LB_DEBUG_TRIG_SEL_INIT 0x0000000000000000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL */ +/* Description: Nibble 0 Chiplet select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_SHFT 0 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL */ +/* Description: Nibble 1 Chiplet select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_SHFT 8 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL */ +/* Description: Nibble 2 Chiplet select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_SHFT 16 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL */ +/* Description: Nibble 3 Chiplet select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_SHFT 24 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL */ +/* Description: Nibble 4 Chiplet select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_SHFT 32 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL */ +/* Description: Nibble 5 Chiplet select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_SHFT 40 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL */ +/* Description: Nibble 6 Chiplet select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_SHFT 48 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL */ +/* Description: Nibble 7 Chiplet select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_SHFT 56 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 + +/* SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60 +#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_DETAIL_1" */ +/* LB Error capture information: HDR1 */ +/* ==================================================================== */ + +#define SH_LB_ERROR_DETAIL_1 0x0000000110050200 +#define SH_LB_ERROR_DETAIL_1_MASK 0x8003073fff3fffff +#define SH_LB_ERROR_DETAIL_1_INIT 0x0000000000000000 + +/* SH_LB_ERROR_DETAIL_1_COMMAND */ +/* Description: COMMAND */ +#define SH_LB_ERROR_DETAIL_1_COMMAND_SHFT 0 +#define SH_LB_ERROR_DETAIL_1_COMMAND_MASK 0x00000000000000ff + +/* SH_LB_ERROR_DETAIL_1_SUPPL */ +/* Description: SUPPLMENTAL */ +#define SH_LB_ERROR_DETAIL_1_SUPPL_SHFT 8 +#define SH_LB_ERROR_DETAIL_1_SUPPL_MASK 0x00000000003fff00 + +/* SH_LB_ERROR_DETAIL_1_SOURCE */ +/* Description: SOURCE */ +#define SH_LB_ERROR_DETAIL_1_SOURCE_SHFT 24 +#define SH_LB_ERROR_DETAIL_1_SOURCE_MASK 0x0000003fff000000 + +/* SH_LB_ERROR_DETAIL_1_DEST */ +/* Description: DEST */ +#define SH_LB_ERROR_DETAIL_1_DEST_SHFT 40 +#define SH_LB_ERROR_DETAIL_1_DEST_MASK 0x0000070000000000 + +/* SH_LB_ERROR_DETAIL_1_HDR_ERR */ +/* Description: HDR_ERR */ +#define SH_LB_ERROR_DETAIL_1_HDR_ERR_SHFT 48 +#define SH_LB_ERROR_DETAIL_1_HDR_ERR_MASK 0x0001000000000000 + +/* SH_LB_ERROR_DETAIL_1_DATA_ERR */ +/* Description: DATA_ERR */ +#define SH_LB_ERROR_DETAIL_1_DATA_ERR_SHFT 49 +#define SH_LB_ERROR_DETAIL_1_DATA_ERR_MASK 0x0002000000000000 + +/* SH_LB_ERROR_DETAIL_1_VALID */ +/* Description: VALID */ +#define SH_LB_ERROR_DETAIL_1_VALID_SHFT 63 +#define SH_LB_ERROR_DETAIL_1_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_DETAIL_2" */ +/* LB Error Bits */ +/* ==================================================================== */ + +#define SH_LB_ERROR_DETAIL_2 0x0000000110050280 +#define SH_LB_ERROR_DETAIL_2_MASK 0x00007fffffffffff +#define SH_LB_ERROR_DETAIL_2_INIT 0x0000000000000000 + +/* SH_LB_ERROR_DETAIL_2_ADDRESS */ +/* Description: ADDRESS */ +#define SH_LB_ERROR_DETAIL_2_ADDRESS_SHFT 0 +#define SH_LB_ERROR_DETAIL_2_ADDRESS_MASK 0x00007fffffffffff + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_DETAIL_3" */ +/* LB Error Bits */ +/* ==================================================================== */ + +#define SH_LB_ERROR_DETAIL_3 0x0000000110050300 +#define SH_LB_ERROR_DETAIL_3_MASK 0xffffffffffffffff +#define SH_LB_ERROR_DETAIL_3_INIT 0x0000000000000000 + +/* SH_LB_ERROR_DETAIL_3_DATA */ +/* Description: DATA */ +#define SH_LB_ERROR_DETAIL_3_DATA_SHFT 0 +#define SH_LB_ERROR_DETAIL_3_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_DETAIL_4" */ +/* LB Error Bits */ +/* ==================================================================== */ + +#define SH_LB_ERROR_DETAIL_4 0x0000000110050380 +#define SH_LB_ERROR_DETAIL_4_MASK 0xffffffffffffffff +#define SH_LB_ERROR_DETAIL_4_INIT 0x0000000000000000 + +/* SH_LB_ERROR_DETAIL_4_ROUTE */ +/* Description: ROUTE */ +#define SH_LB_ERROR_DETAIL_4_ROUTE_SHFT 0 +#define SH_LB_ERROR_DETAIL_4_ROUTE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_DETAIL_5" */ +/* LB Error Bits */ +/* ==================================================================== */ + +#define SH_LB_ERROR_DETAIL_5 0x0000000110050400 +#define SH_LB_ERROR_DETAIL_5_MASK 0x000000000000007f +#define SH_LB_ERROR_DETAIL_5_INIT 0x0000000000000000 + +/* SH_LB_ERROR_DETAIL_5_READ_RETRY */ +/* Description: Read retry error */ +#define SH_LB_ERROR_DETAIL_5_READ_RETRY_SHFT 0 +#define SH_LB_ERROR_DETAIL_5_READ_RETRY_MASK 0x0000000000000001 + +/* SH_LB_ERROR_DETAIL_5_PTC1_WRITE */ +/* Description: PTC1 write error */ +#define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_SHFT 1 +#define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_MASK 0x0000000000000002 + +/* SH_LB_ERROR_DETAIL_5_WRITE_RETRY */ +/* Description: Write retry error */ +#define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_SHFT 2 +#define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_MASK 0x0000000000000004 + +/* SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW */ +/* Description: Nack A counter overflow error */ +#define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_SHFT 3 +#define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_MASK 0x0000000000000008 + +/* SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW */ +/* Description: Nack B counter overflow error */ +#define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_SHFT 4 +#define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_MASK 0x0000000000000010 + +/* SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT */ +/* Description: Nack A counter timeout error */ +#define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_SHFT 5 +#define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_MASK 0x0000000000000020 + +/* SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT */ +/* Description: Nack B counter timeout error */ +#define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_SHFT 6 +#define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_MASK 0x0000000000000040 + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_MASK" */ +/* LB Error Mask */ +/* ==================================================================== */ + +#define SH_LB_ERROR_MASK 0x0000000110050480 +#define SH_LB_ERROR_MASK_MASK 0x00000000007fffff +#define SH_LB_ERROR_MASK_INIT 0x00000000007fffff + +/* SH_LB_ERROR_MASK_RQ_BAD_CMD */ +/* Description: RQ_BAD_CMD */ +#define SH_LB_ERROR_MASK_RQ_BAD_CMD_SHFT 0 +#define SH_LB_ERROR_MASK_RQ_BAD_CMD_MASK 0x0000000000000001 + +/* SH_LB_ERROR_MASK_RP_BAD_CMD */ +/* Description: RP_BAD_CMD */ +#define SH_LB_ERROR_MASK_RP_BAD_CMD_SHFT 1 +#define SH_LB_ERROR_MASK_RP_BAD_CMD_MASK 0x0000000000000002 + +/* SH_LB_ERROR_MASK_RQ_SHORT */ +/* Description: RQ_SHORT */ +#define SH_LB_ERROR_MASK_RQ_SHORT_SHFT 2 +#define SH_LB_ERROR_MASK_RQ_SHORT_MASK 0x0000000000000004 + +/* SH_LB_ERROR_MASK_RP_SHORT */ +/* Description: RP_SHORT */ +#define SH_LB_ERROR_MASK_RP_SHORT_SHFT 3 +#define SH_LB_ERROR_MASK_RP_SHORT_MASK 0x0000000000000008 + +/* SH_LB_ERROR_MASK_RQ_LONG */ +/* Description: RQ_LONG */ +#define SH_LB_ERROR_MASK_RQ_LONG_SHFT 4 +#define SH_LB_ERROR_MASK_RQ_LONG_MASK 0x0000000000000010 + +/* SH_LB_ERROR_MASK_RP_LONG */ +/* Description: RP_LONG */ +#define SH_LB_ERROR_MASK_RP_LONG_SHFT 5 +#define SH_LB_ERROR_MASK_RP_LONG_MASK 0x0000000000000020 + +/* SH_LB_ERROR_MASK_RQ_BAD_DATA */ +/* Description: RQ_BAD_DATA */ +#define SH_LB_ERROR_MASK_RQ_BAD_DATA_SHFT 6 +#define SH_LB_ERROR_MASK_RQ_BAD_DATA_MASK 0x0000000000000040 + +/* SH_LB_ERROR_MASK_RP_BAD_DATA */ +/* Description: RP_BAD_DATA */ +#define SH_LB_ERROR_MASK_RP_BAD_DATA_SHFT 7 +#define SH_LB_ERROR_MASK_RP_BAD_DATA_MASK 0x0000000000000080 + +/* SH_LB_ERROR_MASK_RQ_BAD_ADDR */ +/* Description: RQ_BAD_ADDR */ +#define SH_LB_ERROR_MASK_RQ_BAD_ADDR_SHFT 8 +#define SH_LB_ERROR_MASK_RQ_BAD_ADDR_MASK 0x0000000000000100 + +/* SH_LB_ERROR_MASK_RQ_TIME_OUT */ +/* Description: RQ_TIME_OUT */ +#define SH_LB_ERROR_MASK_RQ_TIME_OUT_SHFT 9 +#define SH_LB_ERROR_MASK_RQ_TIME_OUT_MASK 0x0000000000000200 + +/* SH_LB_ERROR_MASK_LINVV_OVERFLOW */ +/* Description: LINVV_OVERFLOW */ +#define SH_LB_ERROR_MASK_LINVV_OVERFLOW_SHFT 10 +#define SH_LB_ERROR_MASK_LINVV_OVERFLOW_MASK 0x0000000000000400 + +/* SH_LB_ERROR_MASK_UNEXPECTED_LINV */ +/* Description: UNEXPECTED_LINV */ +#define SH_LB_ERROR_MASK_UNEXPECTED_LINV_SHFT 11 +#define SH_LB_ERROR_MASK_UNEXPECTED_LINV_MASK 0x0000000000000800 + +/* SH_LB_ERROR_MASK_PTC_1_TIMEOUT */ +/* Description: PTC_1 Time out */ +#define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_SHFT 12 +#define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_MASK 0x0000000000001000 + +/* SH_LB_ERROR_MASK_JUNK_BUS_ERR */ +/* Description: Junk Bus error */ +#define SH_LB_ERROR_MASK_JUNK_BUS_ERR_SHFT 13 +#define SH_LB_ERROR_MASK_JUNK_BUS_ERR_MASK 0x0000000000002000 + +/* SH_LB_ERROR_MASK_PIO_CB_ERR */ +/* Description: PIO Conveyor Belt operation error */ +#define SH_LB_ERROR_MASK_PIO_CB_ERR_SHFT 14 +#define SH_LB_ERROR_MASK_PIO_CB_ERR_MASK 0x0000000000004000 + +/* SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR */ +/* Description: Vector request Route data was invalid */ +#define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_SHFT 15 +#define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000 + +/* SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR */ +/* Description: Vector reply Route data was invalid */ +#define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_SHFT 16 +#define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000 + +/* SH_LB_ERROR_MASK_GCLK_DROP */ +/* Description: Gclk drop error */ +#define SH_LB_ERROR_MASK_GCLK_DROP_SHFT 17 +#define SH_LB_ERROR_MASK_GCLK_DROP_MASK 0x0000000000020000 + +/* SH_LB_ERROR_MASK_RQ_FIFO_ERROR */ +/* Description: Request queue FIFO error */ +#define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_SHFT 18 +#define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_MASK 0x0000000000040000 + +/* SH_LB_ERROR_MASK_RP_FIFO_ERROR */ +/* Description: Reply queue FIFO error */ +#define SH_LB_ERROR_MASK_RP_FIFO_ERROR_SHFT 19 +#define SH_LB_ERROR_MASK_RP_FIFO_ERROR_MASK 0x0000000000080000 + +/* SH_LB_ERROR_MASK_UNEXP_VALID */ +/* Description: Unexpected valid error */ +#define SH_LB_ERROR_MASK_UNEXP_VALID_SHFT 20 +#define SH_LB_ERROR_MASK_UNEXP_VALID_MASK 0x0000000000100000 + +/* SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW */ +/* Description: Request queue credit overflow */ +#define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_SHFT 21 +#define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000 + +/* SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW */ +/* Description: Reply queue credit overflow */ +#define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_SHFT 22 +#define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000 + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_OVERFLOW" */ +/* LB Error Overflow */ +/* ==================================================================== */ + +#define SH_LB_ERROR_OVERFLOW 0x0000000110050500 +#define SH_LB_ERROR_OVERFLOW_MASK 0x00000000007fffff +#define SH_LB_ERROR_OVERFLOW_INIT 0x0000000000000000 + +/* SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL */ +/* Description: RQ_BAD_CMD_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_SHFT 0 +#define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_MASK 0x0000000000000001 + +/* SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL */ +/* Description: RP_BAD_CMD_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_SHFT 1 +#define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_MASK 0x0000000000000002 + +/* SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL */ +/* Description: RQ_SHORT_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_SHFT 2 +#define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_MASK 0x0000000000000004 + +/* SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL */ +/* Description: RP_SHORT_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_SHFT 3 +#define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_MASK 0x0000000000000008 + +/* SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL */ +/* Description: RQ_LONG_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_SHFT 4 +#define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_MASK 0x0000000000000010 + +/* SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL */ +/* Description: RP_LONG_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_SHFT 5 +#define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_MASK 0x0000000000000020 + +/* SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL */ +/* Description: RQ_BAD_DATA_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_SHFT 6 +#define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_MASK 0x0000000000000040 + +/* SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL */ +/* Description: RP_BAD_DATA_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_SHFT 7 +#define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_MASK 0x0000000000000080 + +/* SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL */ +/* Description: RQ_BAD_ADDR_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_SHFT 8 +#define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_MASK 0x0000000000000100 + +/* SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL */ +/* Description: RQ_TIME_OUT_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_SHFT 9 +#define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_MASK 0x0000000000000200 + +/* SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL */ +/* Description: LINVV_OVERFLOW_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_SHFT 10 +#define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_MASK 0x0000000000000400 + +/* SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL */ +/* Description: UNEXPECTED_LINV_OVRFL */ +#define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_SHFT 11 +#define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_MASK 0x0000000000000800 + +/* SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL */ +/* Description: PTC_1 Time out overflow */ +#define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_SHFT 12 +#define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_MASK 0x0000000000001000 + +/* SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL */ +/* Description: Junk Bus error overflow */ +#define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_SHFT 13 +#define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_MASK 0x0000000000002000 + +/* SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL */ +/* Description: PIO Conveyor Belt operation error overflow */ +#define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_SHFT 14 +#define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_MASK 0x0000000000004000 + +/* SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL */ +/* Description: Vector request Route data was invalid overflow */ +#define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_SHFT 15 +#define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_MASK 0x0000000000008000 + +/* SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL */ +/* Description: Vector reply Route data was invalid overflow */ +#define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_SHFT 16 +#define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_MASK 0x0000000000010000 + +/* SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL */ +/* Description: Gclk drop error overflow */ +#define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_SHFT 17 +#define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_MASK 0x0000000000020000 + +/* SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL */ +/* Description: Request queue FIFO error overflow */ +#define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_SHFT 18 +#define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_MASK 0x0000000000040000 + +/* SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL */ +/* Description: Reply queue FIFO error overflow */ +#define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_SHFT 19 +#define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_MASK 0x0000000000080000 + +/* SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL */ +/* Description: Unexpected valid error overflow */ +#define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_SHFT 20 +#define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_MASK 0x0000000000100000 + +/* SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL */ +/* Description: Request queue credit overflow */ +#define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_SHFT 21 +#define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000200000 + +/* SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL */ +/* Description: Reply queue credit overflow */ +#define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_SHFT 22 +#define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000400000 + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_OVERFLOW_ALIAS" */ +/* LB Error Overflow */ +/* ==================================================================== */ + +#define SH_LB_ERROR_OVERFLOW_ALIAS 0x0000000110050508 + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_SUMMARY" */ +/* LB Error Bits */ +/* ==================================================================== */ + +#define SH_LB_ERROR_SUMMARY 0x0000000110050580 +#define SH_LB_ERROR_SUMMARY_MASK 0x00000000007fffff +#define SH_LB_ERROR_SUMMARY_INIT 0x0000000000000000 + +/* SH_LB_ERROR_SUMMARY_RQ_BAD_CMD */ +/* Description: RQ_BAD_CMD */ +#define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_SHFT 0 +#define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_MASK 0x0000000000000001 + +/* SH_LB_ERROR_SUMMARY_RP_BAD_CMD */ +/* Description: RP_BAD_CMD */ +#define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_SHFT 1 +#define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_MASK 0x0000000000000002 + +/* SH_LB_ERROR_SUMMARY_RQ_SHORT */ +/* Description: RQ_SHORT */ +#define SH_LB_ERROR_SUMMARY_RQ_SHORT_SHFT 2 +#define SH_LB_ERROR_SUMMARY_RQ_SHORT_MASK 0x0000000000000004 + +/* SH_LB_ERROR_SUMMARY_RP_SHORT */ +/* Description: RP_SHORT */ +#define SH_LB_ERROR_SUMMARY_RP_SHORT_SHFT 3 +#define SH_LB_ERROR_SUMMARY_RP_SHORT_MASK 0x0000000000000008 + +/* SH_LB_ERROR_SUMMARY_RQ_LONG */ +/* Description: RQ_LONG */ +#define SH_LB_ERROR_SUMMARY_RQ_LONG_SHFT 4 +#define SH_LB_ERROR_SUMMARY_RQ_LONG_MASK 0x0000000000000010 + +/* SH_LB_ERROR_SUMMARY_RP_LONG */ +/* Description: RP_LONG */ +#define SH_LB_ERROR_SUMMARY_RP_LONG_SHFT 5 +#define SH_LB_ERROR_SUMMARY_RP_LONG_MASK 0x0000000000000020 + +/* SH_LB_ERROR_SUMMARY_RQ_BAD_DATA */ +/* Description: RQ_BAD_DATA */ +#define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_SHFT 6 +#define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_MASK 0x0000000000000040 + +/* SH_LB_ERROR_SUMMARY_RP_BAD_DATA */ +/* Description: RP_BAD_DATA */ +#define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_SHFT 7 +#define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_MASK 0x0000000000000080 + +/* SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR */ +/* Description: RQ_BAD_ADDR */ +#define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_SHFT 8 +#define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_MASK 0x0000000000000100 + +/* SH_LB_ERROR_SUMMARY_RQ_TIME_OUT */ +/* Description: RQ_TIME_OUT */ +#define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_SHFT 9 +#define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_MASK 0x0000000000000200 + +/* SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW */ +/* Description: LINVV_OVERFLOW */ +#define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_SHFT 10 +#define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_MASK 0x0000000000000400 + +/* SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV */ +/* Description: UNEXPECTED_LINV */ +#define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_SHFT 11 +#define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_MASK 0x0000000000000800 + +/* SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT */ +/* Description: PTC_1 Time out */ +#define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_SHFT 12 +#define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_MASK 0x0000000000001000 + +/* SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR */ +/* Description: Junk Bus error */ +#define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_SHFT 13 +#define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_MASK 0x0000000000002000 + +/* SH_LB_ERROR_SUMMARY_PIO_CB_ERR */ +/* Description: PIO Conveyor Belt operation error */ +#define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_SHFT 14 +#define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_MASK 0x0000000000004000 + +/* SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR */ +/* Description: Vector request Route data was invalid */ +#define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_SHFT 15 +#define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000 + +/* SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR */ +/* Description: Vector reply Route data was invalid */ +#define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_SHFT 16 +#define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000 + +/* SH_LB_ERROR_SUMMARY_GCLK_DROP */ +/* Description: Gclk drop error */ +#define SH_LB_ERROR_SUMMARY_GCLK_DROP_SHFT 17 +#define SH_LB_ERROR_SUMMARY_GCLK_DROP_MASK 0x0000000000020000 + +/* SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR */ +/* Description: Request queue FIFO error */ +#define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_SHFT 18 +#define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_MASK 0x0000000000040000 + +/* SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR */ +/* Description: Reply queue FIFO error */ +#define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_SHFT 19 +#define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_MASK 0x0000000000080000 + +/* SH_LB_ERROR_SUMMARY_UNEXP_VALID */ +/* Description: Unexpected valid error */ +#define SH_LB_ERROR_SUMMARY_UNEXP_VALID_SHFT 20 +#define SH_LB_ERROR_SUMMARY_UNEXP_VALID_MASK 0x0000000000100000 + +/* SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW */ +/* Description: Request queue credit overflow */ +#define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_SHFT 21 +#define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000 + +/* SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW */ +/* Description: Reply queue credit overflow */ +#define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_SHFT 22 +#define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000 + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_SUMMARY_ALIAS" */ +/* LB Error Bits Alias */ +/* ==================================================================== */ + +#define SH_LB_ERROR_SUMMARY_ALIAS 0x0000000110050588 + +/* ==================================================================== */ +/* Register "SH_LB_FIRST_ERROR" */ +/* LB First Error */ +/* ==================================================================== */ + +#define SH_LB_FIRST_ERROR 0x0000000110050600 +#define SH_LB_FIRST_ERROR_MASK 0x00000000007fffff +#define SH_LB_FIRST_ERROR_INIT 0x0000000000000000 + +/* SH_LB_FIRST_ERROR_RQ_BAD_CMD */ +/* Description: RQ_BAD_CMD */ +#define SH_LB_FIRST_ERROR_RQ_BAD_CMD_SHFT 0 +#define SH_LB_FIRST_ERROR_RQ_BAD_CMD_MASK 0x0000000000000001 + +/* SH_LB_FIRST_ERROR_RP_BAD_CMD */ +/* Description: RP_BAD_CMD */ +#define SH_LB_FIRST_ERROR_RP_BAD_CMD_SHFT 1 +#define SH_LB_FIRST_ERROR_RP_BAD_CMD_MASK 0x0000000000000002 + +/* SH_LB_FIRST_ERROR_RQ_SHORT */ +/* Description: RQ_SHORT */ +#define SH_LB_FIRST_ERROR_RQ_SHORT_SHFT 2 +#define SH_LB_FIRST_ERROR_RQ_SHORT_MASK 0x0000000000000004 + +/* SH_LB_FIRST_ERROR_RP_SHORT */ +/* Description: RP_SHORT */ +#define SH_LB_FIRST_ERROR_RP_SHORT_SHFT 3 +#define SH_LB_FIRST_ERROR_RP_SHORT_MASK 0x0000000000000008 + +/* SH_LB_FIRST_ERROR_RQ_LONG */ +/* Description: RQ_LONG */ +#define SH_LB_FIRST_ERROR_RQ_LONG_SHFT 4 +#define SH_LB_FIRST_ERROR_RQ_LONG_MASK 0x0000000000000010 + +/* SH_LB_FIRST_ERROR_RP_LONG */ +/* Description: RP_LONG */ +#define SH_LB_FIRST_ERROR_RP_LONG_SHFT 5 +#define SH_LB_FIRST_ERROR_RP_LONG_MASK 0x0000000000000020 + +/* SH_LB_FIRST_ERROR_RQ_BAD_DATA */ +/* Description: RQ_BAD_DATA */ +#define SH_LB_FIRST_ERROR_RQ_BAD_DATA_SHFT 6 +#define SH_LB_FIRST_ERROR_RQ_BAD_DATA_MASK 0x0000000000000040 + +/* SH_LB_FIRST_ERROR_RP_BAD_DATA */ +/* Description: RP_BAD_DATA */ +#define SH_LB_FIRST_ERROR_RP_BAD_DATA_SHFT 7 +#define SH_LB_FIRST_ERROR_RP_BAD_DATA_MASK 0x0000000000000080 + +/* SH_LB_FIRST_ERROR_RQ_BAD_ADDR */ +/* Description: RQ_BAD_ADDR */ +#define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_SHFT 8 +#define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_MASK 0x0000000000000100 + +/* SH_LB_FIRST_ERROR_RQ_TIME_OUT */ +/* Description: RQ_TIME_OUT */ +#define SH_LB_FIRST_ERROR_RQ_TIME_OUT_SHFT 9 +#define SH_LB_FIRST_ERROR_RQ_TIME_OUT_MASK 0x0000000000000200 + +/* SH_LB_FIRST_ERROR_LINVV_OVERFLOW */ +/* Description: LINVV_OVERFLOW */ +#define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_SHFT 10 +#define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_MASK 0x0000000000000400 + +/* SH_LB_FIRST_ERROR_UNEXPECTED_LINV */ +/* Description: UNEXPECTED_LINV */ +#define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_SHFT 11 +#define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_MASK 0x0000000000000800 + +/* SH_LB_FIRST_ERROR_PTC_1_TIMEOUT */ +/* Description: PTC_1 Time out */ +#define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_SHFT 12 +#define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_MASK 0x0000000000001000 + +/* SH_LB_FIRST_ERROR_JUNK_BUS_ERR */ +/* Description: Junk Bus error */ +#define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_SHFT 13 +#define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_MASK 0x0000000000002000 + +/* SH_LB_FIRST_ERROR_PIO_CB_ERR */ +/* Description: PIO Conveyor Belt operation error */ +#define SH_LB_FIRST_ERROR_PIO_CB_ERR_SHFT 14 +#define SH_LB_FIRST_ERROR_PIO_CB_ERR_MASK 0x0000000000004000 + +/* SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR */ +/* Description: Vector request Route data was invalid */ +#define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_SHFT 15 +#define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000 + +/* SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR */ +/* Description: Vector reply Route data was invalid */ +#define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_SHFT 16 +#define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000 + +/* SH_LB_FIRST_ERROR_GCLK_DROP */ +/* Description: Gclk drop error */ +#define SH_LB_FIRST_ERROR_GCLK_DROP_SHFT 17 +#define SH_LB_FIRST_ERROR_GCLK_DROP_MASK 0x0000000000020000 + +/* SH_LB_FIRST_ERROR_RQ_FIFO_ERROR */ +/* Description: Request queue FIFO error */ +#define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_SHFT 18 +#define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_MASK 0x0000000000040000 + +/* SH_LB_FIRST_ERROR_RP_FIFO_ERROR */ +/* Description: Reply queue FIFO error */ +#define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_SHFT 19 +#define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_MASK 0x0000000000080000 + +/* SH_LB_FIRST_ERROR_UNEXP_VALID */ +/* Description: Unexpected valid error */ +#define SH_LB_FIRST_ERROR_UNEXP_VALID_SHFT 20 +#define SH_LB_FIRST_ERROR_UNEXP_VALID_MASK 0x0000000000100000 + +/* SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW */ +/* Description: Request queue credit overflow */ +#define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_SHFT 21 +#define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000 + +/* SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW */ +/* Description: Reply queue credit overflow */ +#define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_SHFT 22 +#define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000 + +/* ==================================================================== */ +/* Register "SH_LB_LAST_CREDIT" */ +/* Credit counter status register */ +/* ==================================================================== */ + +#define SH_LB_LAST_CREDIT 0x0000000110050680 +#define SH_LB_LAST_CREDIT_MASK 0x000000000ffff3df +#define SH_LB_LAST_CREDIT_INIT 0x0000000000000000 + +/* SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT */ +/* Description: LIQ request queue credit counter */ +#define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_SHFT 0 +#define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_MASK 0x000000000000001f + +/* SH_LB_LAST_CREDIT_LIQ_RP_CREDIT */ +/* Description: LIQ reply queue credit counter */ +#define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_SHFT 6 +#define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_MASK 0x00000000000003c0 + +/* SH_LB_LAST_CREDIT_LINVV_CREDIT */ +/* Description: LINVV credit counter */ +#define SH_LB_LAST_CREDIT_LINVV_CREDIT_SHFT 12 +#define SH_LB_LAST_CREDIT_LINVV_CREDIT_MASK 0x000000000003f000 + +/* SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT */ +/* Description: LOQ request queue credit counter */ +#define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_SHFT 18 +#define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_MASK 0x00000000007c0000 + +/* SH_LB_LAST_CREDIT_LOQ_RP_CREDIT */ +/* Description: LOQ reply queue credit counter */ +#define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_SHFT 23 +#define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_MASK 0x000000000f800000 + +/* ==================================================================== */ +/* Register "SH_LB_NACK_STATUS" */ +/* Nack Counter Status Register */ +/* ==================================================================== */ + +#define SH_LB_NACK_STATUS 0x0000000110050700 +#define SH_LB_NACK_STATUS_MASK 0x3fffffff0fff0fff +#define SH_LB_NACK_STATUS_INIT 0x0000000000000000 + +/* SH_LB_NACK_STATUS_PIO_NACK_A */ +/* Description: PIO nackA counter */ +#define SH_LB_NACK_STATUS_PIO_NACK_A_SHFT 0 +#define SH_LB_NACK_STATUS_PIO_NACK_A_MASK 0x0000000000000fff + +/* SH_LB_NACK_STATUS_PIO_NACK_B */ +/* Description: PIO nackA counter */ +#define SH_LB_NACK_STATUS_PIO_NACK_B_SHFT 16 +#define SH_LB_NACK_STATUS_PIO_NACK_B_MASK 0x000000000fff0000 + +/* SH_LB_NACK_STATUS_JUNK_NACK */ +/* Description: Junk bus nack counter */ +#define SH_LB_NACK_STATUS_JUNK_NACK_SHFT 32 +#define SH_LB_NACK_STATUS_JUNK_NACK_MASK 0x0000ffff00000000 + +/* SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT */ +/* Description: Conveyor belt time out counter */ +#define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_SHFT 48 +#define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_MASK 0x0fff000000000000 + +/* SH_LB_NACK_STATUS_CB_STATE */ +/* Description: Conveyor belt state */ +#define SH_LB_NACK_STATUS_CB_STATE_SHFT 60 +#define SH_LB_NACK_STATUS_CB_STATE_MASK 0x3000000000000000 + +/* ==================================================================== */ +/* Register "SH_LB_TRIGGER_COMPARE" */ +/* LB Test-point Trigger Compare */ +/* ==================================================================== */ + +#define SH_LB_TRIGGER_COMPARE 0x0000000110050780 +#define SH_LB_TRIGGER_COMPARE_MASK 0x00000000ffffffff +#define SH_LB_TRIGGER_COMPARE_INIT 0x0000000000000000 + +/* SH_LB_TRIGGER_COMPARE_MASK */ +/* Description: Mask to select Debug bits for trigger generation */ +#define SH_LB_TRIGGER_COMPARE_MASK_SHFT 0 +#define SH_LB_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_LB_TRIGGER_DATA" */ +/* LB Test-point Trigger Compare Data */ +/* ==================================================================== */ + +#define SH_LB_TRIGGER_DATA 0x0000000110050800 +#define SH_LB_TRIGGER_DATA_MASK 0x00000000ffffffff +#define SH_LB_TRIGGER_DATA_INIT 0x00000000ffffffff + +/* SH_LB_TRIGGER_DATA_COMPARE_PATTERN */ +/* Description: debug bit pattern for trigger generation */ +#define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_SHFT 0 +#define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_PI_AEC_CONFIG" */ +/* PI Adaptive Error Correction Configuration */ +/* ==================================================================== */ + +#define SH_PI_AEC_CONFIG 0x0000000120050000 +#define SH_PI_AEC_CONFIG_MASK 0x0000000000000007 +#define SH_PI_AEC_CONFIG_INIT 0x0000000000000000 + +/* SH_PI_AEC_CONFIG_MODE */ +/* Description: AEC Operation Mode */ +#define SH_PI_AEC_CONFIG_MODE_SHFT 0 +#define SH_PI_AEC_CONFIG_MODE_MASK 0x0000000000000007 + +/* ==================================================================== */ +/* Register "SH_PI_AFI_ERROR_MASK" */ +/* PI AFI Error Mask */ +/* ==================================================================== */ + +#define SH_PI_AFI_ERROR_MASK 0x0000000120050080 +#define SH_PI_AFI_ERROR_MASK_MASK 0x00000007ffe00000 +#define SH_PI_AFI_ERROR_MASK_INIT 0x00000007ffe00000 + +/* SH_PI_AFI_ERROR_MASK_HUNG_BUS */ +/* Description: FSB is hung */ +#define SH_PI_AFI_ERROR_MASK_HUNG_BUS_SHFT 21 +#define SH_PI_AFI_ERROR_MASK_HUNG_BUS_MASK 0x0000000000200000 + +/* SH_PI_AFI_ERROR_MASK_RSP_PARITY */ +/* Description: Parity error detecte during response phase */ +#define SH_PI_AFI_ERROR_MASK_RSP_PARITY_SHFT 22 +#define SH_PI_AFI_ERROR_MASK_RSP_PARITY_MASK 0x0000000000400000 + +/* SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN */ +/* Description: Over run error detected on IOQ */ +#define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_SHFT 23 +#define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_MASK 0x0000000000800000 + +/* SH_PI_AFI_ERROR_MASK_REQ_FORMAT */ +/* Description: FSB request format not supported */ +#define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_SHFT 24 +#define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_MASK 0x0000000001000000 + +/* SH_PI_AFI_ERROR_MASK_ADDR_ACCESS */ +/* Description: Access to Address is not supported */ +#define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_SHFT 25 +#define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_MASK 0x0000000002000000 + +/* SH_PI_AFI_ERROR_MASK_REQ_PARITY */ +/* Description: Parity error detected during request phase */ +#define SH_PI_AFI_ERROR_MASK_REQ_PARITY_SHFT 26 +#define SH_PI_AFI_ERROR_MASK_REQ_PARITY_MASK 0x0000000004000000 + +/* SH_PI_AFI_ERROR_MASK_ADDR_PARITY */ +/* Description: Parity error detected on address */ +#define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_SHFT 27 +#define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_MASK 0x0000000008000000 + +/* SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE */ +/* Description: SHUB_FSB_DQE */ +#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_SHFT 28 +#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_MASK 0x0000000010000000 + +/* SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE */ +/* Description: An un-correctable ECC error was detected */ +#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_SHFT 29 +#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_MASK 0x0000000020000000 + +/* SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE */ +/* Description: An correctable ECC error was detected */ +#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_SHFT 30 +#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_MASK 0x0000000040000000 + +/* SH_PI_AFI_ERROR_MASK_LIVELOCK */ +/* Description: AFI livelock error was detected */ +#define SH_PI_AFI_ERROR_MASK_LIVELOCK_SHFT 31 +#define SH_PI_AFI_ERROR_MASK_LIVELOCK_MASK 0x0000000080000000 + +/* SH_PI_AFI_ERROR_MASK_BAD_SNOOP */ +/* Description: AFI bad snoop error was detected */ +#define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_SHFT 32 +#define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_MASK 0x0000000100000000 + +/* SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS */ +/* Description: AFI FSB request table miss error was detected */ +#define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_SHFT 33 +#define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_MASK 0x0000000200000000 + +/* SH_PI_AFI_ERROR_MASK_MSG_LEN */ +/* Description: Runt or Obese message received from SIC */ +#define SH_PI_AFI_ERROR_MASK_MSG_LEN_SHFT 34 +#define SH_PI_AFI_ERROR_MASK_MSG_LEN_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_PI_AFI_TEST_POINT_COMPARE" */ +/* PI AFI Test Point Compare */ +/* ==================================================================== */ + +#define SH_PI_AFI_TEST_POINT_COMPARE 0x0000000120050100 +#define SH_PI_AFI_TEST_POINT_COMPARE_MASK 0xffffffffffffffff +#define SH_PI_AFI_TEST_POINT_COMPARE_INIT 0xffffffff00000000 + +/* SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK */ +/* Description: Mask to select Debug bits for trigger generation */ +#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 +#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff + +/* SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN */ +/* Description: debug bit pattern for trigger generation */ +#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 +#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 + +/* ==================================================================== */ +/* Register "SH_PI_AFI_TEST_POINT_SELECT" */ +/* PI AFI Test Point Select */ +/* ==================================================================== */ + +#define SH_PI_AFI_TEST_POINT_SELECT 0x0000000120050180 +#define SH_PI_AFI_TEST_POINT_SELECT_MASK 0xff7f7f7f7f7f7f7f +#define SH_PI_AFI_TEST_POINT_SELECT_INIT 0x0000000000000000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ +/* Description: Nibble 0: Word Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x000000000000000f + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0: Nibble Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ +/* Description: Nibble 1: Word Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000f00 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1: Nibble Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ +/* Description: Nibble 2: Word Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x00000000000f0000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2: Nibble Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ +/* Description: Nibble 3: Word Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x000000000f000000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3: Nibble Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ +/* Description: Nibble 4: Word Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000f00000000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4: Nibble Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ +/* Description: Nibble 5: Word Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x00000f0000000000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5: Nibble Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ +/* Description: Nibble 6: Word Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x000f000000000000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6: Nibble Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ +/* Description: Nibble 7: Word Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0f00000000000000 + +/* SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7: Nibble Select */ +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE */ +/* Description: Trigger Enabled */ +#define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 +#define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT" */ +/* PI CRBC Test Point Trigger Select */ +/* ==================================================================== */ + +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT 0x0000000120050200 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_MASK 0x7f7f7f7f7f7f7f7f +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ +/* Description: Nibble 0 Chiplet select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x000000000000000f + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ +/* Description: Nibble 1 Chiplet select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000f00 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ +/* Description: Nibble 2 Chiplet select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x00000000000f0000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ +/* Description: Nibble 3 Chiplet select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x000000000f000000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ +/* Description: Nibble 4 Chiplet select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000f00000000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ +/* Description: Nibble 5 Chiplet select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x00000f0000000000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ +/* Description: Nibble 6 Chiplet select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x000f000000000000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ +/* Description: Nibble 7 Chiplet select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0f00000000000000 + +/* SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 +#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_AUTO_REPLY_ENABLE" */ +/* PI Auto Reply Enable */ +/* ==================================================================== */ + +#define SH_PI_AUTO_REPLY_ENABLE 0x0000000120050280 +#define SH_PI_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 +#define SH_PI_AUTO_REPLY_ENABLE_INIT 0x0000000000000000 + +/* SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE */ +/* Description: Auto Reply Enabled */ +#define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_SHFT 0 +#define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_PI_CAM_CONTROL" */ +/* CRB CAM MMR Access Control */ +/* ==================================================================== */ + +#define SH_PI_CAM_CONTROL 0x0000000120050300 +#define SH_PI_CAM_CONTROL_MASK 0x800000000000037f +#define SH_PI_CAM_CONTROL_INIT 0x0000000000000000 + +/* SH_PI_CAM_CONTROL_CAM_INDX */ +/* Description: CRB CAM Index to perform read/write on. */ +#define SH_PI_CAM_CONTROL_CAM_INDX_SHFT 0 +#define SH_PI_CAM_CONTROL_CAM_INDX_MASK 0x000000000000007f + +/* SH_PI_CAM_CONTROL_CAM_WRITE */ +/* Description: Is CRB CAM MMR function a write. */ +#define SH_PI_CAM_CONTROL_CAM_WRITE_SHFT 8 +#define SH_PI_CAM_CONTROL_CAM_WRITE_MASK 0x0000000000000100 + +/* SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR */ +/* Description: Clear RRB read tranfer pending. */ +#define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_SHFT 9 +#define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_MASK 0x0000000000000200 + +/* SH_PI_CAM_CONTROL_START */ +/* Description: Start CRB CAM read/write operation */ +#define SH_PI_CAM_CONTROL_START_SHFT 63 +#define SH_PI_CAM_CONTROL_START_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBC_TEST_POINT_COMPARE" */ +/* PI CRBC Test Point Compare */ +/* ==================================================================== */ + +#define SH_PI_CRBC_TEST_POINT_COMPARE 0x0000000120050380 +#define SH_PI_CRBC_TEST_POINT_COMPARE_MASK 0xffffffffffffffff +#define SH_PI_CRBC_TEST_POINT_COMPARE_INIT 0xffffffff00000000 + +/* SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK */ +/* Description: Mask to select Debug bits for trigger generation */ +#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 +#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff + +/* SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN */ +/* Description: debug bit pattern for trigger generation */ +#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 +#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBC_TEST_POINT_SELECT" */ +/* PI CRBC Test Point Select */ +/* ==================================================================== */ + +#define SH_PI_CRBC_TEST_POINT_SELECT 0x0000000120050400 +#define SH_PI_CRBC_TEST_POINT_SELECT_MASK 0xf777777777777777 +#define SH_PI_CRBC_TEST_POINT_SELECT_INIT 0x0000000000000000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ +/* Description: Nibble 0 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ +/* Description: Nibble 1 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ +/* Description: Nibble 2 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ +/* Description: Nibble 3 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ +/* Description: Nibble 4 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ +/* Description: Nibble 5 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ +/* Description: Nibble 6 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ +/* Description: Nibble 7 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE */ +/* Description: Enable trigger on bit 32 of Analyzer data */ +#define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 +#define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT" */ +/* PI CRBC Test Point Trigger Select */ +/* ==================================================================== */ + +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT 0x0000000120050480 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ +/* Description: Nibble 0 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ +/* Description: Nibble 1 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ +/* Description: Nibble 2 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ +/* Description: Nibble 3 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ +/* Description: Nibble 4 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ +/* Description: Nibble 5 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ +/* Description: Nibble 6 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ +/* Description: Nibble 7 Chiplet select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 + +/* SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 +#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_ERROR_MASK" */ +/* PI CRBP Error Mask */ +/* ==================================================================== */ + +#define SH_PI_CRBP_ERROR_MASK 0x0000000120050500 +#define SH_PI_CRBP_ERROR_MASK_MASK 0x00000000001fffff +#define SH_PI_CRBP_ERROR_MASK_INIT 0x00000000001fffff + +/* SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR */ +/* Description: Mask detection internal protocol table misses */ +#define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_SHFT 0 +#define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_MASK 0x0000000000000001 + +/* SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR */ +/* Description: Mask graphic reply error detection */ +#define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_SHFT 1 +#define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_MASK 0x0000000000000002 + +/* SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR */ +/* Description: Mask detection of external protocol table misses */ +#define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_SHFT 2 +#define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_MASK 0x0000000000000004 + +/* SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR */ +/* Description: Mask memory error reply message detection */ +#define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_SHFT 3 +#define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_MASK 0x0000000000000008 + +/* SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR */ +/* Description: Mask PIO reply error message detection */ +#define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_SHFT 4 +#define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_MASK 0x0000000000000010 + +/* SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR */ +/* Description: Mask memory time-out detection */ +#define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_SHFT 5 +#define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_MASK 0x0000000000000020 + +/* SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR */ +/* Description: Mask PIO time-out detection */ +#define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_SHFT 6 +#define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_MASK 0x0000000000000040 + +/* SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE */ +/* Description: Mask un-correctable ECC error detection */ +#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_SHFT 7 +#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_MASK 0x0000000000000080 + +/* SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE */ +/* Description: Mask correctable ECC error detection */ +#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_SHFT 8 +#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_MASK 0x0000000000000100 + +/* SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR */ +/* Description: Mask detection of color errors */ +#define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_SHFT 9 +#define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_MASK 0x0000000000000200 + +/* SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW */ +/* Description: Mask MD Request input buffer over flow error */ +#define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT 10 +#define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 + +/* SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW */ +/* Description: Mask MD Reply input buffer over flow error */ +#define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_SHFT 11 +#define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_MASK 0x0000000000000800 + +/* SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW */ +/* Description: Mask XN Request input buffer over flow error */ +#define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT 12 +#define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 + +/* SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW */ +/* Description: Mask XN Reply input buffer over flow error */ +#define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_SHFT 13 +#define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_MASK 0x0000000000002000 + +/* SH_PI_CRBP_ERROR_MASK_NACK_OFLOW */ +/* Description: Mask NACK over flow error */ +#define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_SHFT 14 +#define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_MASK 0x0000000000004000 + +/* SH_PI_CRBP_ERROR_MASK_GFX_INT_0 */ +/* Description: Mask GFX transfer interrupt for CPU 0 */ +#define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_SHFT 15 +#define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_MASK 0x0000000000008000 + +/* SH_PI_CRBP_ERROR_MASK_GFX_INT_1 */ +/* Description: Mask GFX transfer interrupt for CPU 1 */ +#define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_SHFT 16 +#define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_MASK 0x0000000000010000 + +/* SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW */ +/* Description: Mask MD Request Credit Overflow Error */ +#define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT 17 +#define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 + +/* SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW */ +/* Description: Mask MD Reply Credit Overflow Error */ +#define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT 18 +#define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 + +/* SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW */ +/* Description: Mask XN Request Credit Overflow Error */ +#define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT 19 +#define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 + +/* SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW */ +/* Description: Mask XN Reply Credit Overflow Error */ +#define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT 20 +#define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_FSB_PIPE_COMPARE" */ +/* CRBP FSB Pipe Compare */ +/* ==================================================================== */ + +#define SH_PI_CRBP_FSB_PIPE_COMPARE 0x0000000120050580 +#define SH_PI_CRBP_FSB_PIPE_COMPARE_MASK 0x001fffffffffffff +#define SH_PI_CRBP_FSB_PIPE_COMPARE_INIT 0x0000000000000000 + +/* SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS */ +/* Description: Address A or B to compare against */ +#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_SHFT 0 +#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_MASK 0x00007fffffffffff + +/* SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ */ +/* Description: REQa or REQb value to compare against */ +#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_SHFT 47 +#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_MASK 0x001f800000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_FSB_PIPE_MASK" */ +/* CRBP Compare Mask */ +/* ==================================================================== */ + +#define SH_PI_CRBP_FSB_PIPE_MASK 0x0000000120050600 +#define SH_PI_CRBP_FSB_PIPE_MASK_MASK 0x001fffffffffffff +#define SH_PI_CRBP_FSB_PIPE_MASK_INIT 0x0000000000000000 + +/* SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK */ +/* Description: Address A or B mask values */ +#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_SHFT 0 +#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff + +/* SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK */ +/* Description: REQa or REQb mask values */ +#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_SHFT 47 +#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_MASK 0x001f800000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_TEST_POINT_COMPARE" */ +/* PI CRBP Test Point Compare */ +/* ==================================================================== */ + +#define SH_PI_CRBP_TEST_POINT_COMPARE 0x0000000120050680 +#define SH_PI_CRBP_TEST_POINT_COMPARE_MASK 0xffffffffffffffff +#define SH_PI_CRBP_TEST_POINT_COMPARE_INIT 0xffffffff00000000 + +/* SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK */ +/* Description: Mask to select Debug bits for trigger generation */ +#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 +#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff + +/* SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN */ +/* Description: debug bit pattern for trigger generation */ +#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 +#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_TEST_POINT_SELECT" */ +/* PI CRBP Test Point Select */ +/* ==================================================================== */ + +#define SH_PI_CRBP_TEST_POINT_SELECT 0x0000000120050700 +#define SH_PI_CRBP_TEST_POINT_SELECT_MASK 0xf777777777777777 +#define SH_PI_CRBP_TEST_POINT_SELECT_INIT 0x0000000000000000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ +/* Description: Nibble 0 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ +/* Description: Nibble 1 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ +/* Description: Nibble 2 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ +/* Description: Nibble 3 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ +/* Description: Nibble 4 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ +/* Description: Nibble 5 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ +/* Description: Nibble 6 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ +/* Description: Nibble 7 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE */ +/* Description: Enable trigger on bit 32 of Analyzer data */ +#define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 +#define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT" */ +/* PI CRBP Test Point Trigger Select */ +/* ==================================================================== */ + +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT 0x0000000120050780 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ +/* Description: Nibble 0 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ +/* Description: Nibble 1 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ +/* Description: Nibble 2 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ +/* Description: Nibble 3 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ +/* Description: Nibble 4 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ +/* Description: Nibble 5 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ +/* Description: Nibble 6 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ +/* Description: Nibble 7 Chiplet select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 + +/* SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 +#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_XB_PIPE_COMPARE_0" */ +/* CRBP XB Pipe Compare */ +/* ==================================================================== */ + +#define SH_PI_CRBP_XB_PIPE_COMPARE_0 0x0000000120050800 +#define SH_PI_CRBP_XB_PIPE_COMPARE_0_MASK 0x007fffffffffffff +#define SH_PI_CRBP_XB_PIPE_COMPARE_0_INIT 0x0000000000000000 + +/* SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS */ +/* Description: Address to compare against */ +#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_SHFT 0 +#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_MASK 0x00007fffffffffff + +/* SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND */ +/* Description: SN2NET Command to compare against */ +#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_SHFT 47 +#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_MASK 0x007f800000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_XB_PIPE_COMPARE_1" */ +/* CRBP XB Pipe Compare */ +/* ==================================================================== */ + +#define SH_PI_CRBP_XB_PIPE_COMPARE_1 0x0000000120050880 +#define SH_PI_CRBP_XB_PIPE_COMPARE_1_MASK 0x000001ff3fff3fff +#define SH_PI_CRBP_XB_PIPE_COMPARE_1_INIT 0x0000000000000000 + +/* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE */ +/* Description: Source to compare against */ +#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_SHFT 0 +#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_MASK 0x0000000000003fff + +/* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL */ +/* Description: Supplemental to compare against */ +#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_SHFT 16 +#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_MASK 0x000000003fff0000 + +/* SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO */ +/* Description: Echo to compare against */ +#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_SHFT 32 +#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_MASK 0x000001ff00000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_XB_PIPE_MASK_0" */ +/* CRBP Compare Mask Register 1 */ +/* ==================================================================== */ + +#define SH_PI_CRBP_XB_PIPE_MASK_0 0x0000000120050900 +#define SH_PI_CRBP_XB_PIPE_MASK_0_MASK 0x007fffffffffffff +#define SH_PI_CRBP_XB_PIPE_MASK_0_INIT 0x0000000000000000 + +/* SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK */ +/* Description: Address to compare against */ +#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_SHFT 0 +#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff + +/* SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK */ +/* Description: SN2NET Command to compare against */ +#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_SHFT 47 +#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_MASK 0x007f800000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_XB_PIPE_MASK_1" */ +/* CRBP XB Pipe Compare Mask Register 1 */ +/* ==================================================================== */ + +#define SH_PI_CRBP_XB_PIPE_MASK_1 0x0000000120050980 +#define SH_PI_CRBP_XB_PIPE_MASK_1_MASK 0x000001ff3fff3fff +#define SH_PI_CRBP_XB_PIPE_MASK_1_INIT 0x0000000000000000 + +/* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK */ +/* Description: Source to compare against */ +#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_SHFT 0 +#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_MASK 0x0000000000003fff + +/* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK */ +/* Description: Supplemental to compare against */ +#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_SHFT 16 +#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_MASK 0x000000003fff0000 + +/* SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK */ +/* Description: Echo to compare against */ +#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_SHFT 32 +#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_MASK 0x000001ff00000000 + +/* ==================================================================== */ +/* Register "SH_PI_DPC_QUEUE_CONFIG" */ +/* DPC Queue Configuration */ +/* ==================================================================== */ + +#define SH_PI_DPC_QUEUE_CONFIG 0x0000000120050a00 +#define SH_PI_DPC_QUEUE_CONFIG_MASK 0x000000001f1f1f1f +#define SH_PI_DPC_QUEUE_CONFIG_INIT 0x000000000c010c01 + +/* SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL */ +/* Description: DXB WTL Command Queue Almost Empty Level */ +#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_SHFT 0 +#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_MASK 0x000000000000001f + +/* SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH */ +/* Description: DXB WTL Command Queue Almost Full Threshold */ +#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_SHFT 8 +#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_MASK 0x0000000000001f00 + +/* SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL */ +/* Description: FSB WTL Command Queue Almost Empty Level */ +#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_SHFT 16 +#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_MASK 0x00000000001f0000 + +/* SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH */ +/* Description: FSB WTL Command Queue Almost Full Threshold */ +#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_SHFT 24 +#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_MASK 0x000000001f000000 + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_MASK" */ +/* PI Error Mask */ +/* ==================================================================== */ + +#define SH_PI_ERROR_MASK 0x0000000120050a80 +#define SH_PI_ERROR_MASK_MASK 0x00000007ffffffff +#define SH_PI_ERROR_MASK_INIT 0x00000007ffffffff + +/* SH_PI_ERROR_MASK_FSB_PROTO_ERR */ +/* Description: Mask detection of internal protocol table misses */ +#define SH_PI_ERROR_MASK_FSB_PROTO_ERR_SHFT 0 +#define SH_PI_ERROR_MASK_FSB_PROTO_ERR_MASK 0x0000000000000001 + +/* SH_PI_ERROR_MASK_GFX_RP_ERR */ +/* Description: Mask graphic reply error message error detection */ +#define SH_PI_ERROR_MASK_GFX_RP_ERR_SHFT 1 +#define SH_PI_ERROR_MASK_GFX_RP_ERR_MASK 0x0000000000000002 + +/* SH_PI_ERROR_MASK_XB_PROTO_ERR */ +/* Description: Mask detection of external protocol table misses */ +#define SH_PI_ERROR_MASK_XB_PROTO_ERR_SHFT 2 +#define SH_PI_ERROR_MASK_XB_PROTO_ERR_MASK 0x0000000000000004 + +/* SH_PI_ERROR_MASK_MEM_RP_ERR */ +/* Description: Mask memory reply error detection */ +#define SH_PI_ERROR_MASK_MEM_RP_ERR_SHFT 3 +#define SH_PI_ERROR_MASK_MEM_RP_ERR_MASK 0x0000000000000008 + +/* SH_PI_ERROR_MASK_PIO_RP_ERR */ +/* Description: Mask PIO reply error detection */ +#define SH_PI_ERROR_MASK_PIO_RP_ERR_SHFT 4 +#define SH_PI_ERROR_MASK_PIO_RP_ERR_MASK 0x0000000000000010 + +/* SH_PI_ERROR_MASK_MEM_TO_ERR */ +/* Description: Mask CRB time-out errors */ +#define SH_PI_ERROR_MASK_MEM_TO_ERR_SHFT 5 +#define SH_PI_ERROR_MASK_MEM_TO_ERR_MASK 0x0000000000000020 + +/* SH_PI_ERROR_MASK_PIO_TO_ERR */ +/* Description: Mask PIO time-out errors */ +#define SH_PI_ERROR_MASK_PIO_TO_ERR_SHFT 6 +#define SH_PI_ERROR_MASK_PIO_TO_ERR_MASK 0x0000000000000040 + +/* SH_PI_ERROR_MASK_FSB_SHUB_UCE */ +/* Description: Mask un-correctable ECC error detection */ +#define SH_PI_ERROR_MASK_FSB_SHUB_UCE_SHFT 7 +#define SH_PI_ERROR_MASK_FSB_SHUB_UCE_MASK 0x0000000000000080 + +/* SH_PI_ERROR_MASK_FSB_SHUB_CE */ +/* Description: Mask correctable ECC error detection */ +#define SH_PI_ERROR_MASK_FSB_SHUB_CE_SHFT 8 +#define SH_PI_ERROR_MASK_FSB_SHUB_CE_MASK 0x0000000000000100 + +/* SH_PI_ERROR_MASK_MSG_COLOR_ERR */ +/* Description: Mask message color error detection */ +#define SH_PI_ERROR_MASK_MSG_COLOR_ERR_SHFT 9 +#define SH_PI_ERROR_MASK_MSG_COLOR_ERR_MASK 0x0000000000000200 + +/* SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW */ +/* Description: Mask MD Request input buffer over flow error */ +#define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT 10 +#define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 + +/* SH_PI_ERROR_MASK_MD_RP_Q_OFLOW */ +/* Description: Mask MD Reply input buffer over flow error */ +#define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_SHFT 11 +#define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_MASK 0x0000000000000800 + +/* SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW */ +/* Description: Mask XN Request input buffer over flow error */ +#define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT 12 +#define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 + +/* SH_PI_ERROR_MASK_XN_RP_Q_OFLOW */ +/* Description: Mask XN Reply input buffer over flow error */ +#define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_SHFT 13 +#define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_MASK 0x0000000000002000 + +/* SH_PI_ERROR_MASK_NACK_OFLOW */ +/* Description: Mask NACK over flow error */ +#define SH_PI_ERROR_MASK_NACK_OFLOW_SHFT 14 +#define SH_PI_ERROR_MASK_NACK_OFLOW_MASK 0x0000000000004000 + +/* SH_PI_ERROR_MASK_GFX_INT_0 */ +/* Description: Mask GFX transfer interrupt for CPU 0 */ +#define SH_PI_ERROR_MASK_GFX_INT_0_SHFT 15 +#define SH_PI_ERROR_MASK_GFX_INT_0_MASK 0x0000000000008000 + +/* SH_PI_ERROR_MASK_GFX_INT_1 */ +/* Description: Mask GFX transfer interrupt for CPU 1 */ +#define SH_PI_ERROR_MASK_GFX_INT_1_SHFT 16 +#define SH_PI_ERROR_MASK_GFX_INT_1_MASK 0x0000000000010000 + +/* SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW */ +/* Description: Mask MD Request Credit Overflow Error */ +#define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT 17 +#define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 + +/* SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW */ +/* Description: Mask MD Reply Credit Overflow Error */ +#define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT 18 +#define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 + +/* SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW */ +/* Description: Mask XN Request Credit Overflow Error */ +#define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT 19 +#define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 + +/* SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW */ +/* Description: Mask XN Reply Credit Overflow Error */ +#define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT 20 +#define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 + +/* SH_PI_ERROR_MASK_HUNG_BUS */ +/* Description: Mask FSB hung error */ +#define SH_PI_ERROR_MASK_HUNG_BUS_SHFT 21 +#define SH_PI_ERROR_MASK_HUNG_BUS_MASK 0x0000000000200000 + +/* SH_PI_ERROR_MASK_RSP_PARITY */ +/* Description: Parity error detecte during response phase */ +#define SH_PI_ERROR_MASK_RSP_PARITY_SHFT 22 +#define SH_PI_ERROR_MASK_RSP_PARITY_MASK 0x0000000000400000 + +/* SH_PI_ERROR_MASK_IOQ_OVERRUN */ +/* Description: Over run error detected on IOQ */ +#define SH_PI_ERROR_MASK_IOQ_OVERRUN_SHFT 23 +#define SH_PI_ERROR_MASK_IOQ_OVERRUN_MASK 0x0000000000800000 + +/* SH_PI_ERROR_MASK_REQ_FORMAT */ +/* Description: FSB request format not supported */ +#define SH_PI_ERROR_MASK_REQ_FORMAT_SHFT 24 +#define SH_PI_ERROR_MASK_REQ_FORMAT_MASK 0x0000000001000000 + +/* SH_PI_ERROR_MASK_ADDR_ACCESS */ +/* Description: Access to Address is not supported */ +#define SH_PI_ERROR_MASK_ADDR_ACCESS_SHFT 25 +#define SH_PI_ERROR_MASK_ADDR_ACCESS_MASK 0x0000000002000000 + +/* SH_PI_ERROR_MASK_REQ_PARITY */ +/* Description: Parity error detected during request phase */ +#define SH_PI_ERROR_MASK_REQ_PARITY_SHFT 26 +#define SH_PI_ERROR_MASK_REQ_PARITY_MASK 0x0000000004000000 + +/* SH_PI_ERROR_MASK_ADDR_PARITY */ +/* Description: Parity error detected on address */ +#define SH_PI_ERROR_MASK_ADDR_PARITY_SHFT 27 +#define SH_PI_ERROR_MASK_ADDR_PARITY_MASK 0x0000000008000000 + +/* SH_PI_ERROR_MASK_SHUB_FSB_DQE */ +/* Description: SHUB_FSB_DQE */ +#define SH_PI_ERROR_MASK_SHUB_FSB_DQE_SHFT 28 +#define SH_PI_ERROR_MASK_SHUB_FSB_DQE_MASK 0x0000000010000000 + +/* SH_PI_ERROR_MASK_SHUB_FSB_UCE */ +/* Description: An un-correctable ECC error was detected */ +#define SH_PI_ERROR_MASK_SHUB_FSB_UCE_SHFT 29 +#define SH_PI_ERROR_MASK_SHUB_FSB_UCE_MASK 0x0000000020000000 + +/* SH_PI_ERROR_MASK_SHUB_FSB_CE */ +/* Description: An correctable ECC error was detected */ +#define SH_PI_ERROR_MASK_SHUB_FSB_CE_SHFT 30 +#define SH_PI_ERROR_MASK_SHUB_FSB_CE_MASK 0x0000000040000000 + +/* SH_PI_ERROR_MASK_LIVELOCK */ +/* Description: AFI livelock error was detected */ +#define SH_PI_ERROR_MASK_LIVELOCK_SHFT 31 +#define SH_PI_ERROR_MASK_LIVELOCK_MASK 0x0000000080000000 + +/* SH_PI_ERROR_MASK_BAD_SNOOP */ +/* Description: AFI bad snoop error was detected */ +#define SH_PI_ERROR_MASK_BAD_SNOOP_SHFT 32 +#define SH_PI_ERROR_MASK_BAD_SNOOP_MASK 0x0000000100000000 + +/* SH_PI_ERROR_MASK_FSB_TBL_MISS */ +/* Description: AFI FSB request table miss error was detected */ +#define SH_PI_ERROR_MASK_FSB_TBL_MISS_SHFT 33 +#define SH_PI_ERROR_MASK_FSB_TBL_MISS_MASK 0x0000000200000000 + +/* SH_PI_ERROR_MASK_MSG_LENGTH */ +/* Description: Message length error on received message from SIC */ +#define SH_PI_ERROR_MASK_MSG_LENGTH_SHFT 34 +#define SH_PI_ERROR_MASK_MSG_LENGTH_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_PI_EXPRESS_REPLY_CONFIG" */ +/* PI Express Reply Configuration */ +/* ==================================================================== */ + +#define SH_PI_EXPRESS_REPLY_CONFIG 0x0000000120050b00 +#define SH_PI_EXPRESS_REPLY_CONFIG_MASK 0x0000000000000007 +#define SH_PI_EXPRESS_REPLY_CONFIG_INIT 0x0000000000000001 + +/* SH_PI_EXPRESS_REPLY_CONFIG_MODE */ +/* Description: Express Reply Mode */ +#define SH_PI_EXPRESS_REPLY_CONFIG_MODE_SHFT 0 +#define SH_PI_EXPRESS_REPLY_CONFIG_MODE_MASK 0x0000000000000007 + +/* ==================================================================== */ +/* Register "SH_PI_FSB_COMPARE_VALUE" */ +/* FSB Compare Value */ +/* ==================================================================== */ + +#define SH_PI_FSB_COMPARE_VALUE 0x0000000120050c00 +#define SH_PI_FSB_COMPARE_VALUE_MASK 0xffffffffffffffff +#define SH_PI_FSB_COMPARE_VALUE_INIT 0x0000000000000000 + +/* SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE */ +/* Description: Compare value */ +#define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_SHFT 0 +#define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_PI_FSB_COMPARE_MASK" */ +/* FSB Compare Mask */ +/* ==================================================================== */ + +#define SH_PI_FSB_COMPARE_MASK 0x0000000120050b80 +#define SH_PI_FSB_COMPARE_MASK_MASK 0xffffffffffffffff +#define SH_PI_FSB_COMPARE_MASK_INIT 0x0000000000000000 + +/* SH_PI_FSB_COMPARE_MASK_MASK_VALUE */ +/* Description: Mask value */ +#define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_SHFT 0 +#define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_PI_FSB_ERROR_INJECTION" */ +/* Inject an Error onto the FSB */ +/* ==================================================================== */ + +#define SH_PI_FSB_ERROR_INJECTION 0x0000000120050c80 +#define SH_PI_FSB_ERROR_INJECTION_MASK 0x000000070fff03ff +#define SH_PI_FSB_ERROR_INJECTION_INIT 0x0000000000000000 + +/* SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB */ +/* Description: Inject a RP# Parity Error onto the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_SHFT 0 +#define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_MASK 0x0000000000000001 + +/* SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB */ +/* Description: Inject an AP[0]# Parity Error onto the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_SHFT 1 +#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_MASK 0x0000000000000002 + +/* SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB */ +/* Description: Inject an AP[1]# Parity Error onto the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_SHFT 2 +#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_MASK 0x0000000000000004 + +/* SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB */ +/* Description: Inject a RSP# Parity Error onto the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_SHFT 3 +#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_MASK 0x0000000000000008 + +/* SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB */ +/* Description: Inject a Correctable Error in Doubleword 0 onto the */ +#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_SHFT 4 +#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_MASK 0x0000000000000010 + +/* SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB */ +/* Description: Inject an Uncorrectable Error in Doubleword 0 onto */ +/* the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_SHFT 5 +#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_MASK 0x0000000000000020 + +/* SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB */ +/* Description: Inject a Correctable Error in Doubleword 1 onto the */ +#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_SHFT 6 +#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_MASK 0x0000000000000040 + +/* SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB */ +/* Description: Inject an Uncorrectable Error in Doubleword 1 onto */ +/* the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_SHFT 7 +#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_MASK 0x0000000000000080 + +/* SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB */ +/* Description: Inject an IP[0]# Parity Error onto the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_SHFT 8 +#define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_MASK 0x0000000000000100 + +/* SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB */ +/* Description: Inject an IP[1]# Parity Error onto the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_SHFT 9 +#define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_MASK 0x0000000000000200 + +/* SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB */ +/* Description: Inject a RP# Parity Error When Sampling the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_SHFT 16 +#define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_MASK 0x0000000000010000 + +/* SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB */ +/* Description: Inject an AP[0]# Parity Error When Sampling the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_SHFT 17 +#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_MASK 0x0000000000020000 + +/* SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB */ +/* Description: Inject an AP[1]# Parity Error When Sampling the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_SHFT 18 +#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_MASK 0x0000000000040000 + +/* SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB */ +/* Description: Inject a RSP# Parity Error When Sampling the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_SHFT 19 +#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_MASK 0x0000000000080000 + +/* SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB */ +/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ +/* ata Packet 0 */ +#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_SHFT 20 +#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_MASK 0x0000000000100000 + +/* SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB */ +/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ +/* Data Packet 0 */ +#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_SHFT 21 +#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_MASK 0x0000000000200000 + +/* SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB */ +/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ +/* ata Packet 0 */ +#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_SHFT 22 +#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_MASK 0x0000000000400000 + +/* SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB */ +/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ +/* Data Packet 0 */ +#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_SHFT 23 +#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_MASK 0x0000000000800000 + +/* SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB */ +/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ +/* ata Packet 0 */ +#define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_SHFT 24 +#define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_MASK 0x0000000001000000 + +/* SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB */ +/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ +/* Data Packet 0 */ +#define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_SHFT 25 +#define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_MASK 0x0000000002000000 + +/* SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB */ +/* Description: Inject a Correctable Error in Doubleword 0 of SIC D */ +/* ata Packet 0 */ +#define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_SHFT 26 +#define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_MASK 0x0000000004000000 + +/* SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB */ +/* Description: Inject a Uncorrectable Error in Doubleword 0 of SIC */ +/* Data Packet 0 */ +#define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_SHFT 27 +#define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_MASK 0x0000000008000000 + +/* SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN */ +/* Description: Inject an ioq overrun Error on the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_SHFT 32 +#define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_MASK 0x0000000100000000 + +/* SH_PI_FSB_ERROR_INJECTION_LIVELOCK */ +/* Description: Inject a livelock Error on the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_SHFT 33 +#define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_MASK 0x0000000200000000 + +/* SH_PI_FSB_ERROR_INJECTION_BUS_HANG */ +/* Description: Inject an bus hang on the FSB */ +#define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_SHFT 34 +#define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_PI_MD2PI_REPLY_VC_CONFIG" */ +/* MD-to-PI Reply Virtual Channel Configuration */ +/* ==================================================================== */ + +#define SH_PI_MD2PI_REPLY_VC_CONFIG 0x0000000120050d00 +#define SH_PI_MD2PI_REPLY_VC_CONFIG_MASK 0xc000000000003fff +#define SH_PI_MD2PI_REPLY_VC_CONFIG_INIT 0x000000000000088c + +/* SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH */ +/* Description: Depth of header Buffer */ +#define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0 +#define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f + +/* SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH */ +/* Description: Number of data buffers Available */ +#define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4 +#define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 + +/* SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS */ +/* Description: Maximum credits from sender */ +#define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8 +#define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 + +/* SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT */ +/* Description: Send an extra credit to sender */ +#define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62 +#define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 + +/* SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS */ +/* Description: Capture credit and status information */ +#define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 +#define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_MD2PI_REQUEST_VC_CONFIG" */ +/* MD-to-PI Request Virtual Channel Configuration */ +/* ==================================================================== */ + +#define SH_PI_MD2PI_REQUEST_VC_CONFIG 0x0000000120050d80 +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MASK 0xc000000000003fff +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_INIT 0x000000000000088c + +/* SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH */ +/* Description: Depth of header Buffer */ +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0 +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f + +/* SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH */ +/* Description: Number of data buffers Available */ +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4 +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 + +/* SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS */ +/* Description: Maximum credits from sender */ +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8 +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 + +/* SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT */ +/* Description: Send an extra credit to sender */ +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62 +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 + +/* SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS */ +/* Description: Capture credit and status information */ +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 +#define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_QUEUE_ERROR_INJECTION" */ +/* PI Queue Error Injection */ +/* ==================================================================== */ + +#define SH_PI_QUEUE_ERROR_INJECTION 0x0000000120050e00 +#define SH_PI_QUEUE_ERROR_INJECTION_MASK 0x00000000000000ff +#define SH_PI_QUEUE_ERROR_INJECTION_INIT 0x0000000000000000 + +/* SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q */ +#define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_SHFT 0 +#define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_MASK 0x0000000000000001 + +/* SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q */ +#define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_SHFT 1 +#define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_MASK 0x0000000000000002 + +/* SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q */ +#define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_SHFT 2 +#define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_MASK 0x0000000000000004 + +/* SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR */ +#define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_SHFT 3 +#define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_MASK 0x0000000000000008 + +/* SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR */ +#define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_SHFT 4 +#define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_MASK 0x0000000000000010 + +/* SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q */ +#define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_SHFT 5 +#define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_MASK 0x0000000000000020 + +/* SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q */ +#define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_SHFT 6 +#define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_MASK 0x0000000000000040 + +/* SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR */ +#define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_SHFT 7 +#define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_PI_TEST_POINT_COMPARE" */ +/* PI Test Point Compare */ +/* ==================================================================== */ + +#define SH_PI_TEST_POINT_COMPARE 0x0000000120050e80 +#define SH_PI_TEST_POINT_COMPARE_MASK 0xffffffffffffffff +#define SH_PI_TEST_POINT_COMPARE_INIT 0xffffffff00000000 + +/* SH_PI_TEST_POINT_COMPARE_COMPARE_MASK */ +/* Description: Mask to select test point data for trigger generati */ +#define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0 +#define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff + +/* SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN */ +/* Description: Pattern of test point data to cause trigger */ +#define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32 +#define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000 + +/* ==================================================================== */ +/* Register "SH_PI_TEST_POINT_SELECT" */ +/* PI Test Point Select */ +/* ==================================================================== */ + +#define SH_PI_TEST_POINT_SELECT 0x0000000120050f00 +#define SH_PI_TEST_POINT_SELECT_MASK 0xf777777777777777 +#define SH_PI_TEST_POINT_SELECT_INIT 0x0000000000000000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL */ +/* Description: Nibble 0 data is from Chiplet X */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0 +#define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble X is routed to Nibble 0 */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL */ +/* Description: Nibble 1 data is from Chiplet X */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8 +#define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble X is routed to Nibble 1 */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL */ +/* Description: Nibble 2 data is from Chiplet X */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16 +#define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble X is routed to Nibble 2 */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL */ +/* Description: Nibble 3 data is from Chiplet X */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24 +#define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble X is routed to Nibble 3 */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL */ +/* Description: Nibble 4 data is from Chiplet X */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32 +#define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble X is routed to Nibble 4 */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL */ +/* Description: Nibble 5 data is from Chiplet X */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40 +#define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble X is routed to Nibble 5 */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL */ +/* Description: Nibble 6 data is from Chiplet X */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48 +#define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble X is routed to Nibble 6 */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL */ +/* Description: Nibble 7 data is from Chiplet X */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56 +#define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000 + +/* SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble X is routed to Nibble 7 */ +#define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE */ +/* Description: Enable trigger on bit 32 of Analyzer data */ +#define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63 +#define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_TEST_POINT_TRIGGER_SELECT" */ +/* PI Test Point Trigger Select */ +/* ==================================================================== */ + +#define SH_PI_TEST_POINT_TRIGGER_SELECT 0x0000000120050f80 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL */ +/* Description: Nibble 0 Chiplet select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL */ +/* Description: Nibble 1 Chiplet select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL */ +/* Description: Nibble 2 Chiplet select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL */ +/* Description: Nibble 3 Chiplet select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL */ +/* Description: Nibble 4 Chiplet select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL */ +/* Description: Nibble 5 Chiplet select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL */ +/* Description: Nibble 6 Chiplet select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL */ +/* Description: Nibble 7 Chiplet select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000 + +/* SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60 +#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_XN2PI_REPLY_VC_CONFIG" */ +/* XN-to-PI Reply Virtual Channel Configuration */ +/* ==================================================================== */ + +#define SH_PI_XN2PI_REPLY_VC_CONFIG 0x0000000120051000 +#define SH_PI_XN2PI_REPLY_VC_CONFIG_MASK 0xc000000000003fff +#define SH_PI_XN2PI_REPLY_VC_CONFIG_INIT 0x000000000000068c + +/* SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH */ +/* Description: Depth of header Buffer */ +#define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0 +#define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f + +/* SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH */ +/* Description: Number of data buffers Available */ +#define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4 +#define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 + +/* SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS */ +/* Description: Maximum credits from sender */ +#define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8 +#define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 + +/* SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT */ +/* Description: Send an extra credit to sender */ +#define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62 +#define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 + +/* SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS */ +/* Description: Capture credit and status information */ +#define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 +#define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_XN2PI_REQUEST_VC_CONFIG" */ +/* XN-to-PI Request Virtual Channel Configuration */ +/* ==================================================================== */ + +#define SH_PI_XN2PI_REQUEST_VC_CONFIG 0x0000000120051080 +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MASK 0xc000000000003fff +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_INIT 0x000000000000068c + +/* SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH */ +/* Description: Depth of header Buffer */ +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0 +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f + +/* SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH */ +/* Description: Number of data buffers Available */ +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4 +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0 + +/* SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS */ +/* Description: Maximum credits from sender */ +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8 +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00 + +/* SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT */ +/* Description: Send an extra credit to sender */ +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62 +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000 + +/* SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS */ +/* Description: Capture credit and status information */ +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63 +#define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_AEC_STATUS" */ +/* PI Adaptive Error Correction Status */ +/* ==================================================================== */ + +#define SH_PI_AEC_STATUS 0x0000000120060000 +#define SH_PI_AEC_STATUS_MASK 0x0000000000000007 +#define SH_PI_AEC_STATUS_INIT 0x0000000000000000 + +/* SH_PI_AEC_STATUS_STATE */ +/* Description: AEC State */ +#define SH_PI_AEC_STATUS_STATE_SHFT 0 +#define SH_PI_AEC_STATUS_STATE_MASK 0x0000000000000007 + +/* ==================================================================== */ +/* Register "SH_PI_AFI_FIRST_ERROR" */ +/* PI AFI First Error */ +/* ==================================================================== */ + +#define SH_PI_AFI_FIRST_ERROR 0x0000000120060080 +#define SH_PI_AFI_FIRST_ERROR_MASK 0x00000007ffe00180 +#define SH_PI_AFI_FIRST_ERROR_INIT 0x0000000000000000 + +/* SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE */ +/* Description: An un-correctable ECC error was detected */ +#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7 +#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080 + +/* SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE */ +/* Description: A correctable ECC error was detected */ +#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_SHFT 8 +#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100 + +/* SH_PI_AFI_FIRST_ERROR_HUNG_BUS */ +/* Description: FSB is hung */ +#define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_SHFT 21 +#define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_MASK 0x0000000000200000 + +/* SH_PI_AFI_FIRST_ERROR_RSP_PARITY */ +/* Description: Parity error detecte during response phase */ +#define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_SHFT 22 +#define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_MASK 0x0000000000400000 + +/* SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN */ +/* Description: Over run error detected on IOQ */ +#define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_SHFT 23 +#define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_MASK 0x0000000000800000 + +/* SH_PI_AFI_FIRST_ERROR_REQ_FORMAT */ +/* Description: FSB request format not supported */ +#define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_SHFT 24 +#define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_MASK 0x0000000001000000 + +/* SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS */ +/* Description: Access to Address is not supported */ +#define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_SHFT 25 +#define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_MASK 0x0000000002000000 + +/* SH_PI_AFI_FIRST_ERROR_REQ_PARITY */ +/* Description: Parity error detected during request phase */ +#define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_SHFT 26 +#define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_MASK 0x0000000004000000 + +/* SH_PI_AFI_FIRST_ERROR_ADDR_PARITY */ +/* Description: Parity error detected on address */ +#define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_SHFT 27 +#define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_MASK 0x0000000008000000 + +/* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE */ +/* Description: SHUB_FSB_DQE */ +#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_SHFT 28 +#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_MASK 0x0000000010000000 + +/* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE */ +/* Description: An un-correctable ECC error was detected */ +#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_SHFT 29 +#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_MASK 0x0000000020000000 + +/* SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE */ +/* Description: An correctable ECC error was detected */ +#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_SHFT 30 +#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_MASK 0x0000000040000000 + +/* SH_PI_AFI_FIRST_ERROR_LIVELOCK */ +/* Description: AFI livelock error was detected */ +#define SH_PI_AFI_FIRST_ERROR_LIVELOCK_SHFT 31 +#define SH_PI_AFI_FIRST_ERROR_LIVELOCK_MASK 0x0000000080000000 + +/* SH_PI_AFI_FIRST_ERROR_BAD_SNOOP */ +/* Description: AFI bad snoop error was detected */ +#define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_SHFT 32 +#define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_MASK 0x0000000100000000 + +/* SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS */ +/* Description: AFI FSB request table miss error was detected */ +#define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_SHFT 33 +#define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_MASK 0x0000000200000000 + +/* SH_PI_AFI_FIRST_ERROR_MSG_LEN */ +/* Description: Runt or Obese message received from SIC */ +#define SH_PI_AFI_FIRST_ERROR_MSG_LEN_SHFT 34 +#define SH_PI_AFI_FIRST_ERROR_MSG_LEN_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_PI_CAM_ADDRESS_READ_DATA" */ +/* CRB CAM MMR Address Read Data */ +/* ==================================================================== */ + +#define SH_PI_CAM_ADDRESS_READ_DATA 0x0000000120060100 +#define SH_PI_CAM_ADDRESS_READ_DATA_MASK 0x8000ffffffffffff +#define SH_PI_CAM_ADDRESS_READ_DATA_INIT 0x0000000000000000 + +/* SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR */ +/* Description: CRB CAM Address Read Data. */ +#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_SHFT 0 +#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_MASK 0x0000ffffffffffff + +/* SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL */ +/* Description: CRB CAM Address Read Data Valid. */ +#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_SHFT 63 +#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CAM_LPRA_READ_DATA" */ +/* CRB CAM MMR LPRA Read Data */ +/* ==================================================================== */ + +#define SH_PI_CAM_LPRA_READ_DATA 0x0000000120060180 +#define SH_PI_CAM_LPRA_READ_DATA_MASK 0xffffffffffffffff +#define SH_PI_CAM_LPRA_READ_DATA_INIT 0x0000000000000000 + +/* SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA */ +/* Description: CRB CAM LPRA read data. */ +#define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_SHFT 0 +#define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_PI_CAM_STATE_READ_DATA" */ +/* CRB CAM MMR State Read Data */ +/* ==================================================================== */ + +#define SH_PI_CAM_STATE_READ_DATA 0x0000000120060200 +#define SH_PI_CAM_STATE_READ_DATA_MASK 0x8003ffff0000003f +#define SH_PI_CAM_STATE_READ_DATA_INIT 0x0000000000000000 + +/* SH_PI_CAM_STATE_READ_DATA_CAM_STATE */ +/* Description: CRB CAM State read data. */ +#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_SHFT 0 +#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_MASK 0x000000000000000f + +/* SH_PI_CAM_STATE_READ_DATA_CAM_TO */ +/* Description: CRB CAM Time-out Status. */ +#define SH_PI_CAM_STATE_READ_DATA_CAM_TO_SHFT 4 +#define SH_PI_CAM_STATE_READ_DATA_CAM_TO_MASK 0x0000000000000010 + +/* SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND */ +/* Description: CRB CAM State Read Pending. */ +#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_SHFT 5 +#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_MASK 0x0000000000000020 + +/* SH_PI_CAM_STATE_READ_DATA_CAM_LPRA */ +/* Description: CRB LPRA Overflow Data. */ +#define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_SHFT 32 +#define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_MASK 0x0003ffff00000000 + +/* SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL */ +/* Description: CRB CAM MMR read data is valid. */ +#define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_SHFT 63 +#define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CORRECTED_DETAIL_1" */ +/* PI Corrected Error Detail */ +/* ==================================================================== */ + +#define SH_PI_CORRECTED_DETAIL_1 0x0000000120060280 +#define SH_PI_CORRECTED_DETAIL_1_MASK 0xffffffffffffffff +#define SH_PI_CORRECTED_DETAIL_1_INIT 0x0000000000000000 + +/* SH_PI_CORRECTED_DETAIL_1_ADDRESS */ +/* Description: Address of Message that logged Correctable Error */ +#define SH_PI_CORRECTED_DETAIL_1_ADDRESS_SHFT 0 +#define SH_PI_CORRECTED_DETAIL_1_ADDRESS_MASK 0x0000ffffffffffff + +/* SH_PI_CORRECTED_DETAIL_1_SYNDROME */ +/* Description: Syndrome for double word data with Correctable Erro */ +#define SH_PI_CORRECTED_DETAIL_1_SYNDROME_SHFT 48 +#define SH_PI_CORRECTED_DETAIL_1_SYNDROME_MASK 0x00ff000000000000 + +/* SH_PI_CORRECTED_DETAIL_1_DEP */ +/* Description: DEP code for Double word in error */ +#define SH_PI_CORRECTED_DETAIL_1_DEP_SHFT 56 +#define SH_PI_CORRECTED_DETAIL_1_DEP_MASK 0xff00000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CORRECTED_DETAIL_2" */ +/* PI Corrected Error Detail 2 */ +/* ==================================================================== */ + +#define SH_PI_CORRECTED_DETAIL_2 0x0000000120060300 +#define SH_PI_CORRECTED_DETAIL_2_MASK 0xffffffffffffffff +#define SH_PI_CORRECTED_DETAIL_2_INIT 0x0000000000000000 + +/* SH_PI_CORRECTED_DETAIL_2_DATA */ +/* Description: Double word data in error */ +#define SH_PI_CORRECTED_DETAIL_2_DATA_SHFT 0 +#define SH_PI_CORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_PI_CORRECTED_DETAIL_3" */ +/* PI Corrected Error Detail 3 */ +/* ==================================================================== */ + +#define SH_PI_CORRECTED_DETAIL_3 0x0000000120060380 +#define SH_PI_CORRECTED_DETAIL_3_MASK 0xffffffffffffffff +#define SH_PI_CORRECTED_DETAIL_3_INIT 0x0000000000000000 + +/* SH_PI_CORRECTED_DETAIL_3_ADDRESS */ +/* Description: Address of Message that logged Correctable Error */ +#define SH_PI_CORRECTED_DETAIL_3_ADDRESS_SHFT 0 +#define SH_PI_CORRECTED_DETAIL_3_ADDRESS_MASK 0x0000ffffffffffff + +/* SH_PI_CORRECTED_DETAIL_3_SYNDROME */ +/* Description: Syndrome for double word data with Correctable Erro */ +#define SH_PI_CORRECTED_DETAIL_3_SYNDROME_SHFT 48 +#define SH_PI_CORRECTED_DETAIL_3_SYNDROME_MASK 0x00ff000000000000 + +/* SH_PI_CORRECTED_DETAIL_3_DEP */ +/* Description: DEP code for Double word in error */ +#define SH_PI_CORRECTED_DETAIL_3_DEP_SHFT 56 +#define SH_PI_CORRECTED_DETAIL_3_DEP_MASK 0xff00000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_CORRECTED_DETAIL_4" */ +/* PI Corrected Error Detail 4 */ +/* ==================================================================== */ + +#define SH_PI_CORRECTED_DETAIL_4 0x0000000120060400 +#define SH_PI_CORRECTED_DETAIL_4_MASK 0xffffffffffffffff +#define SH_PI_CORRECTED_DETAIL_4_INIT 0x0000000000000000 + +/* SH_PI_CORRECTED_DETAIL_4_DATA */ +/* Description: Double word data in error */ +#define SH_PI_CORRECTED_DETAIL_4_DATA_SHFT 0 +#define SH_PI_CORRECTED_DETAIL_4_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_FIRST_ERROR" */ +/* PI CRBP First Error */ +/* ==================================================================== */ + +#define SH_PI_CRBP_FIRST_ERROR 0x0000000120060480 +#define SH_PI_CRBP_FIRST_ERROR_MASK 0x00000000001fffff +#define SH_PI_CRBP_FIRST_ERROR_INIT 0x0000000000000000 + +/* SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR */ +/* Description: CRB's FSB pipe detected protocol table miss */ +#define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_SHFT 0 +#define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_MASK 0x0000000000000001 + +/* SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR */ +/* Description: CRB's XB pipe received a GFX error reply */ +#define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_SHFT 1 +#define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_MASK 0x0000000000000002 + +/* SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR */ +/* Description: CRB's XB pipe detected protocol table miss */ +#define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_SHFT 2 +#define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_MASK 0x0000000000000004 + +/* SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR */ +/* Description: CRB's XB pipe received a memory error reply message */ +#define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_SHFT 3 +#define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_MASK 0x0000000000000008 + +/* SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR */ +/* Description: CRB's XB pipe received a PIO error reply message */ +#define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_SHFT 4 +#define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_MASK 0x0000000000000010 + +/* SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR */ +/* Description: CRB's XB pipe detected a CRB time-out */ +#define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_SHFT 5 +#define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_MASK 0x0000000000000020 + +/* SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR */ +/* Description: CRB's XB pipe detected a PIO time-out */ +#define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_SHFT 6 +#define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_MASK 0x0000000000000040 + +/* SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE */ +/* Description: An un-correctable ECC error was detected */ +#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7 +#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080 + +/* SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE */ +/* Description: A correctable ECC error was detected */ +#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_SHFT 8 +#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100 + +/* SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR */ +/* Description: Message color was wrong */ +#define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_SHFT 9 +#define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_MASK 0x0000000000000200 + +/* SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW */ +/* Description: MD Request input buffer over flow error */ +#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT 10 +#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 + +/* SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW */ +/* Description: MD Reply input buffer over flow error */ +#define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT 11 +#define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_MASK 0x0000000000000800 + +/* SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW */ +/* Description: XN Request input buffer over flow error */ +#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT 12 +#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 + +/* SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW */ +/* Description: XN Reply input buffer over flow error */ +#define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT 13 +#define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_MASK 0x0000000000002000 + +/* SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW */ +/* Description: NACK over flow error */ +#define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_SHFT 14 +#define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_MASK 0x0000000000004000 + +/* SH_PI_CRBP_FIRST_ERROR_GFX_INT_0 */ +/* Description: GFX transfer interrupt for CPU 0 */ +#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_SHFT 15 +#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_MASK 0x0000000000008000 + +/* SH_PI_CRBP_FIRST_ERROR_GFX_INT_1 */ +/* Description: GFX transfer interrupt for CPU 1 */ +#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_SHFT 16 +#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_MASK 0x0000000000010000 + +/* SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW */ +/* Description: MD Request Credit Overflow Error */ +#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT 17 +#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 + +/* SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW */ +/* Description: MD Reply Credit Overflow Error */ +#define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT 18 +#define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 + +/* SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW */ +/* Description: XN Request Credit Overflow Error */ +#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT 19 +#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 + +/* SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW */ +/* Description: XN Reply Credit Overflow Error */ +#define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT 20 +#define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_DETAIL_1" */ +/* PI Error Detail 1 */ +/* ==================================================================== */ + +#define SH_PI_ERROR_DETAIL_1 0x0000000120060500 +#define SH_PI_ERROR_DETAIL_1_MASK 0xffffffffffffffff +#define SH_PI_ERROR_DETAIL_1_INIT 0x0000000000000000 + +/* SH_PI_ERROR_DETAIL_1_STATUS */ +/* Description: Error Detail 1 */ +#define SH_PI_ERROR_DETAIL_1_STATUS_SHFT 0 +#define SH_PI_ERROR_DETAIL_1_STATUS_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_DETAIL_2" */ +/* PI Error Detail 2 */ +/* ==================================================================== */ + +#define SH_PI_ERROR_DETAIL_2 0x0000000120060580 +#define SH_PI_ERROR_DETAIL_2_MASK 0xffffffffffffffff +#define SH_PI_ERROR_DETAIL_2_INIT 0x0000000000000000 + +/* SH_PI_ERROR_DETAIL_2_STATUS */ +/* Description: Error Status */ +#define SH_PI_ERROR_DETAIL_2_STATUS_SHFT 0 +#define SH_PI_ERROR_DETAIL_2_STATUS_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_OVERFLOW" */ +/* PI Error Overflow */ +/* ==================================================================== */ + +#define SH_PI_ERROR_OVERFLOW 0x0000000120060600 +#define SH_PI_ERROR_OVERFLOW_MASK 0x00000007ffffffff +#define SH_PI_ERROR_OVERFLOW_INIT 0x0000000000000000 + +/* SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR */ +/* Description: CRB's FSB pipe detected protocol table miss */ +#define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_SHFT 0 +#define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_MASK 0x0000000000000001 + +/* SH_PI_ERROR_OVERFLOW_GFX_RP_ERR */ +/* Description: CRB's XB pipe received another GFX reply error mess */ +#define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_SHFT 1 +#define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_MASK 0x0000000000000002 + +/* SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR */ +/* Description: CRB's XB pipe detected another protocol table miss */ +#define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_SHFT 2 +#define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_MASK 0x0000000000000004 + +/* SH_PI_ERROR_OVERFLOW_MEM_RP_ERR */ +/* Description: CRB's XB pipe received another memory reply error m */ +#define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_SHFT 3 +#define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_MASK 0x0000000000000008 + +/* SH_PI_ERROR_OVERFLOW_PIO_RP_ERR */ +/* Description: CRB's XB pipe received another PIO reply error mess */ +#define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_SHFT 4 +#define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_MASK 0x0000000000000010 + +/* SH_PI_ERROR_OVERFLOW_MEM_TO_ERR */ +/* Description: CRB's XB pipe detected a CRB time-out */ +#define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_SHFT 5 +#define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_MASK 0x0000000000000020 + +/* SH_PI_ERROR_OVERFLOW_PIO_TO_ERR */ +/* Description: CRB's XB pipe detected a PIO time-out */ +#define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_SHFT 6 +#define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_MASK 0x0000000000000040 + +/* SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE */ +/* Description: An un-correctable ECC error was detected */ +#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_SHFT 7 +#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_MASK 0x0000000000000080 + +/* SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE */ +/* Description: An correctable ECC error was detected */ +#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_SHFT 8 +#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_MASK 0x0000000000000100 + +/* SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR */ +/* Description: Message color was not correct */ +#define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_SHFT 9 +#define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_MASK 0x0000000000000200 + +/* SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW */ +/* Description: MD Request input buffer over flow error */ +#define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_SHFT 10 +#define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 + +/* SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW */ +/* Description: MD Reply input buffer over flow error */ +#define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_SHFT 11 +#define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_MASK 0x0000000000000800 + +/* SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW */ +/* Description: XN Request input buffer over flow error */ +#define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_SHFT 12 +#define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 + +/* SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW */ +/* Description: XN Reply input buffer over flow error */ +#define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_SHFT 13 +#define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_MASK 0x0000000000002000 + +/* SH_PI_ERROR_OVERFLOW_NACK_OFLOW */ +/* Description: NACK over flow error */ +#define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_SHFT 14 +#define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_MASK 0x0000000000004000 + +/* SH_PI_ERROR_OVERFLOW_GFX_INT_0 */ +/* Description: GFX transfer interrupt for CPU 0 */ +#define SH_PI_ERROR_OVERFLOW_GFX_INT_0_SHFT 15 +#define SH_PI_ERROR_OVERFLOW_GFX_INT_0_MASK 0x0000000000008000 + +/* SH_PI_ERROR_OVERFLOW_GFX_INT_1 */ +/* Description: GFX transfer interrupt for CPU 1 */ +#define SH_PI_ERROR_OVERFLOW_GFX_INT_1_SHFT 16 +#define SH_PI_ERROR_OVERFLOW_GFX_INT_1_MASK 0x0000000000010000 + +/* SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW */ +/* Description: MD Request Credit Overflow Error */ +#define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_SHFT 17 +#define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 + +/* SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW */ +/* Description: MD Reply Credit Overflow Error */ +#define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_SHFT 18 +#define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 + +/* SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW */ +/* Description: XN Request Credit Overflow Error */ +#define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_SHFT 19 +#define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 + +/* SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW */ +/* Description: XN Reply Credit Overflow Error */ +#define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_SHFT 20 +#define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 + +/* SH_PI_ERROR_OVERFLOW_HUNG_BUS */ +/* Description: FSB is hung */ +#define SH_PI_ERROR_OVERFLOW_HUNG_BUS_SHFT 21 +#define SH_PI_ERROR_OVERFLOW_HUNG_BUS_MASK 0x0000000000200000 + +/* SH_PI_ERROR_OVERFLOW_RSP_PARITY */ +/* Description: Parity error detecte during response phase */ +#define SH_PI_ERROR_OVERFLOW_RSP_PARITY_SHFT 22 +#define SH_PI_ERROR_OVERFLOW_RSP_PARITY_MASK 0x0000000000400000 + +/* SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN */ +/* Description: Over run error detected on IOQ */ +#define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_SHFT 23 +#define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_MASK 0x0000000000800000 + +/* SH_PI_ERROR_OVERFLOW_REQ_FORMAT */ +/* Description: FSB request format not supported */ +#define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_SHFT 24 +#define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_MASK 0x0000000001000000 + +/* SH_PI_ERROR_OVERFLOW_ADDR_ACCESS */ +/* Description: Access to Address is not supported */ +#define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_SHFT 25 +#define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_MASK 0x0000000002000000 + +/* SH_PI_ERROR_OVERFLOW_REQ_PARITY */ +/* Description: Parity error detected during request phase */ +#define SH_PI_ERROR_OVERFLOW_REQ_PARITY_SHFT 26 +#define SH_PI_ERROR_OVERFLOW_REQ_PARITY_MASK 0x0000000004000000 + +/* SH_PI_ERROR_OVERFLOW_ADDR_PARITY */ +/* Description: Parity error detected on address */ +#define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_SHFT 27 +#define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_MASK 0x0000000008000000 + +/* SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE */ +/* Description: SHUB_FSB_DQE */ +#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_SHFT 28 +#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_MASK 0x0000000010000000 + +/* SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE */ +/* Description: An un-correctable ECC error was detected */ +#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_SHFT 29 +#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_MASK 0x0000000020000000 + +/* SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE */ +/* Description: An correctable ECC error was detected */ +#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_SHFT 30 +#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_MASK 0x0000000040000000 + +/* SH_PI_ERROR_OVERFLOW_LIVELOCK */ +/* Description: AFI livelock error was detected */ +#define SH_PI_ERROR_OVERFLOW_LIVELOCK_SHFT 31 +#define SH_PI_ERROR_OVERFLOW_LIVELOCK_MASK 0x0000000080000000 + +/* SH_PI_ERROR_OVERFLOW_BAD_SNOOP */ +/* Description: AFI bad snoop error was detected */ +#define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_SHFT 32 +#define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_MASK 0x0000000100000000 + +/* SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS */ +/* Description: AFI FSB request table miss error was detected */ +#define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_SHFT 33 +#define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_MASK 0x0000000200000000 + +/* SH_PI_ERROR_OVERFLOW_MSG_LENGTH */ +/* Description: Message length error on received message from SIC */ +#define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_SHFT 34 +#define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_OVERFLOW_ALIAS" */ +/* PI Error Overflow Alias */ +/* ==================================================================== */ + +#define SH_PI_ERROR_OVERFLOW_ALIAS 0x0000000120060608 + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_SUMMARY" */ +/* PI Error Summary */ +/* ==================================================================== */ + +#define SH_PI_ERROR_SUMMARY 0x0000000120060680 +#define SH_PI_ERROR_SUMMARY_MASK 0x00000007ffffffff +#define SH_PI_ERROR_SUMMARY_INIT 0x0000000000000000 + +/* SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR */ +/* Description: CRB's FSB pipe detected protocol table miss */ +#define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_SHFT 0 +#define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_MASK 0x0000000000000001 + +/* SH_PI_ERROR_SUMMARY_GFX_RP_ERR */ +/* Description: Graphic reply error message received */ +#define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_SHFT 1 +#define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_MASK 0x0000000000000002 + +/* SH_PI_ERROR_SUMMARY_XB_PROTO_ERR */ +/* Description: CRB's XB pipe detected protocol table miss */ +#define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_SHFT 2 +#define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_MASK 0x0000000000000004 + +/* SH_PI_ERROR_SUMMARY_MEM_RP_ERR */ +/* Description: Memory reply error message received */ +#define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_SHFT 3 +#define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_MASK 0x0000000000000008 + +/* SH_PI_ERROR_SUMMARY_PIO_RP_ERR */ +/* Description: PIO error reply message received */ +#define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_SHFT 4 +#define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_MASK 0x0000000000000010 + +/* SH_PI_ERROR_SUMMARY_MEM_TO_ERR */ +/* Description: CRB's XB pipe detected a CRB time-out */ +#define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_SHFT 5 +#define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_MASK 0x0000000000000020 + +/* SH_PI_ERROR_SUMMARY_PIO_TO_ERR */ +/* Description: CRB's XB pipe detected a PIO time-out */ +#define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_SHFT 6 +#define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_MASK 0x0000000000000040 + +/* SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE */ +/* Description: An un-correctable ECC error was detected */ +#define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_SHFT 7 +#define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_MASK 0x0000000000000080 + +/* SH_PI_ERROR_SUMMARY_FSB_SHUB_CE */ +/* Description: An correctable ECC error was detected */ +#define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_SHFT 8 +#define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_MASK 0x0000000000000100 + +/* SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR */ +/* Description: Message color was wrong */ +#define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_SHFT 9 +#define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_MASK 0x0000000000000200 + +/* SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW */ +/* Description: MD Request input buffer over flow error */ +#define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_SHFT 10 +#define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 + +/* SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW */ +/* Description: MD Reply input buffer over flow error */ +#define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_SHFT 11 +#define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_MASK 0x0000000000000800 + +/* SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW */ +/* Description: XN Request input buffer over flow error */ +#define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_SHFT 12 +#define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 + +/* SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW */ +/* Description: XN Reply input buffer over flow error */ +#define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_SHFT 13 +#define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_MASK 0x0000000000002000 + +/* SH_PI_ERROR_SUMMARY_NACK_OFLOW */ +/* Description: NACK over flow error */ +#define SH_PI_ERROR_SUMMARY_NACK_OFLOW_SHFT 14 +#define SH_PI_ERROR_SUMMARY_NACK_OFLOW_MASK 0x0000000000004000 + +/* SH_PI_ERROR_SUMMARY_GFX_INT_0 */ +/* Description: GFX transfer interrupt for CPU 0 */ +#define SH_PI_ERROR_SUMMARY_GFX_INT_0_SHFT 15 +#define SH_PI_ERROR_SUMMARY_GFX_INT_0_MASK 0x0000000000008000 + +/* SH_PI_ERROR_SUMMARY_GFX_INT_1 */ +/* Description: GFX transfer interrupt for CPU 1 */ +#define SH_PI_ERROR_SUMMARY_GFX_INT_1_SHFT 16 +#define SH_PI_ERROR_SUMMARY_GFX_INT_1_MASK 0x0000000000010000 + +/* SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW */ +/* Description: MD Request Credit Overflow Error */ +#define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_SHFT 17 +#define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 + +/* SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW */ +/* Description: MD Reply Credit Overflow Error */ +#define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_SHFT 18 +#define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 + +/* SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW */ +/* Description: XN Request Credit Overflow Error */ +#define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_SHFT 19 +#define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 + +/* SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW */ +/* Description: XN Reply Credit Overflow Error */ +#define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_SHFT 20 +#define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 + +/* SH_PI_ERROR_SUMMARY_HUNG_BUS */ +/* Description: FSB is hung */ +#define SH_PI_ERROR_SUMMARY_HUNG_BUS_SHFT 21 +#define SH_PI_ERROR_SUMMARY_HUNG_BUS_MASK 0x0000000000200000 + +/* SH_PI_ERROR_SUMMARY_RSP_PARITY */ +/* Description: Parity error detecte during response phase */ +#define SH_PI_ERROR_SUMMARY_RSP_PARITY_SHFT 22 +#define SH_PI_ERROR_SUMMARY_RSP_PARITY_MASK 0x0000000000400000 + +/* SH_PI_ERROR_SUMMARY_IOQ_OVERRUN */ +/* Description: Over run error detected on IOQ */ +#define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_SHFT 23 +#define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_MASK 0x0000000000800000 + +/* SH_PI_ERROR_SUMMARY_REQ_FORMAT */ +/* Description: FSB request format not supported */ +#define SH_PI_ERROR_SUMMARY_REQ_FORMAT_SHFT 24 +#define SH_PI_ERROR_SUMMARY_REQ_FORMAT_MASK 0x0000000001000000 + +/* SH_PI_ERROR_SUMMARY_ADDR_ACCESS */ +/* Description: Access to Address is not supported */ +#define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_SHFT 25 +#define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_MASK 0x0000000002000000 + +/* SH_PI_ERROR_SUMMARY_REQ_PARITY */ +/* Description: Parity error detected during request phase */ +#define SH_PI_ERROR_SUMMARY_REQ_PARITY_SHFT 26 +#define SH_PI_ERROR_SUMMARY_REQ_PARITY_MASK 0x0000000004000000 + +/* SH_PI_ERROR_SUMMARY_ADDR_PARITY */ +/* Description: Parity error detected on address */ +#define SH_PI_ERROR_SUMMARY_ADDR_PARITY_SHFT 27 +#define SH_PI_ERROR_SUMMARY_ADDR_PARITY_MASK 0x0000000008000000 + +/* SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE */ +/* Description: SHUB_FSB_DQE error */ +#define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_SHFT 28 +#define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_MASK 0x0000000010000000 + +/* SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE */ +/* Description: An un-correctable ECC error was detected */ +#define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_SHFT 29 +#define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_MASK 0x0000000020000000 + +/* SH_PI_ERROR_SUMMARY_SHUB_FSB_CE */ +/* Description: An correctable ECC error was detected */ +#define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_SHFT 30 +#define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_MASK 0x0000000040000000 + +/* SH_PI_ERROR_SUMMARY_LIVELOCK */ +/* Description: AFI livelock error was detected */ +#define SH_PI_ERROR_SUMMARY_LIVELOCK_SHFT 31 +#define SH_PI_ERROR_SUMMARY_LIVELOCK_MASK 0x0000000080000000 + +/* SH_PI_ERROR_SUMMARY_BAD_SNOOP */ +/* Description: AFI bad snoop error was detected */ +#define SH_PI_ERROR_SUMMARY_BAD_SNOOP_SHFT 32 +#define SH_PI_ERROR_SUMMARY_BAD_SNOOP_MASK 0x0000000100000000 + +/* SH_PI_ERROR_SUMMARY_FSB_TBL_MISS */ +/* Description: AFI FSB request table miss error was detected */ +#define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_SHFT 33 +#define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_MASK 0x0000000200000000 + +/* SH_PI_ERROR_SUMMARY_MSG_LENGTH */ +/* Description: Message length error on received message from SIC */ +#define SH_PI_ERROR_SUMMARY_MSG_LENGTH_SHFT 34 +#define SH_PI_ERROR_SUMMARY_MSG_LENGTH_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_SUMMARY_ALIAS" */ +/* PI Error Summary Alias */ +/* ==================================================================== */ + +#define SH_PI_ERROR_SUMMARY_ALIAS 0x0000000120060688 + +/* ==================================================================== */ +/* Register "SH_PI_EXPRESS_REPLY_STATUS" */ +/* PI Express Reply Status */ +/* ==================================================================== */ + +#define SH_PI_EXPRESS_REPLY_STATUS 0x0000000120060700 +#define SH_PI_EXPRESS_REPLY_STATUS_MASK 0x0000000000000007 +#define SH_PI_EXPRESS_REPLY_STATUS_INIT 0x0000000000000000 + +/* SH_PI_EXPRESS_REPLY_STATUS_STATE */ +/* Description: Express Reply State */ +#define SH_PI_EXPRESS_REPLY_STATUS_STATE_SHFT 0 +#define SH_PI_EXPRESS_REPLY_STATUS_STATE_MASK 0x0000000000000007 + +/* ==================================================================== */ +/* Register "SH_PI_FIRST_ERROR" */ +/* PI First Error */ +/* ==================================================================== */ + +#define SH_PI_FIRST_ERROR 0x0000000120060780 +#define SH_PI_FIRST_ERROR_MASK 0x00000007ffffffff +#define SH_PI_FIRST_ERROR_INIT 0x0000000000000000 + +/* SH_PI_FIRST_ERROR_FSB_PROTO_ERR */ +/* Description: CRB's FSB pipe detected protocol table miss */ +#define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_SHFT 0 +#define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_MASK 0x0000000000000001 + +/* SH_PI_FIRST_ERROR_GFX_RP_ERR */ +/* Description: Graphics error reply message received */ +#define SH_PI_FIRST_ERROR_GFX_RP_ERR_SHFT 1 +#define SH_PI_FIRST_ERROR_GFX_RP_ERR_MASK 0x0000000000000002 + +/* SH_PI_FIRST_ERROR_XB_PROTO_ERR */ +/* Description: CRB's XB pipe detected protocol table miss */ +#define SH_PI_FIRST_ERROR_XB_PROTO_ERR_SHFT 2 +#define SH_PI_FIRST_ERROR_XB_PROTO_ERR_MASK 0x0000000000000004 + +/* SH_PI_FIRST_ERROR_MEM_RP_ERR */ +/* Description: Memory reply error message received */ +#define SH_PI_FIRST_ERROR_MEM_RP_ERR_SHFT 3 +#define SH_PI_FIRST_ERROR_MEM_RP_ERR_MASK 0x0000000000000008 + +/* SH_PI_FIRST_ERROR_PIO_RP_ERR */ +/* Description: PIO reply error message received */ +#define SH_PI_FIRST_ERROR_PIO_RP_ERR_SHFT 4 +#define SH_PI_FIRST_ERROR_PIO_RP_ERR_MASK 0x0000000000000010 + +/* SH_PI_FIRST_ERROR_MEM_TO_ERR */ +/* Description: CRB's XB pipe detected a CRB time-out */ +#define SH_PI_FIRST_ERROR_MEM_TO_ERR_SHFT 5 +#define SH_PI_FIRST_ERROR_MEM_TO_ERR_MASK 0x0000000000000020 + +/* SH_PI_FIRST_ERROR_PIO_TO_ERR */ +/* Description: CRB's XB pipe detected a PIO time-out */ +#define SH_PI_FIRST_ERROR_PIO_TO_ERR_SHFT 6 +#define SH_PI_FIRST_ERROR_PIO_TO_ERR_MASK 0x0000000000000040 + +/* SH_PI_FIRST_ERROR_FSB_SHUB_UCE */ +/* Description: An un-correctable ECC error was detected */ +#define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7 +#define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080 + +/* SH_PI_FIRST_ERROR_FSB_SHUB_CE */ +/* Description: A correctable ECC error was detected */ +#define SH_PI_FIRST_ERROR_FSB_SHUB_CE_SHFT 8 +#define SH_PI_FIRST_ERROR_FSB_SHUB_CE_MASK 0x0000000000000100 + +/* SH_PI_FIRST_ERROR_MSG_COLOR_ERR */ +/* Description: Message color was wrong */ +#define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_SHFT 9 +#define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_MASK 0x0000000000000200 + +/* SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW */ +/* Description: MD Request input buffer over flow error */ +#define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT 10 +#define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK 0x0000000000000400 + +/* SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW */ +/* Description: MD Reply input buffer over flow error */ +#define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT 11 +#define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_MASK 0x0000000000000800 + +/* SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW */ +/* Description: XN Request input buffer over flow error */ +#define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT 12 +#define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK 0x0000000000001000 + +/* SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW */ +/* Description: XN Reply input buffer over flow error */ +#define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT 13 +#define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_MASK 0x0000000000002000 + +/* SH_PI_FIRST_ERROR_NACK_OFLOW */ +/* Description: NACK over flow error */ +#define SH_PI_FIRST_ERROR_NACK_OFLOW_SHFT 14 +#define SH_PI_FIRST_ERROR_NACK_OFLOW_MASK 0x0000000000004000 + +/* SH_PI_FIRST_ERROR_GFX_INT_0 */ +/* Description: GFX transfer interrupt for CPU 0 */ +#define SH_PI_FIRST_ERROR_GFX_INT_0_SHFT 15 +#define SH_PI_FIRST_ERROR_GFX_INT_0_MASK 0x0000000000008000 + +/* SH_PI_FIRST_ERROR_GFX_INT_1 */ +/* Description: GFX transfer interrupt for CPU 1 */ +#define SH_PI_FIRST_ERROR_GFX_INT_1_SHFT 16 +#define SH_PI_FIRST_ERROR_GFX_INT_1_MASK 0x0000000000010000 + +/* SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW */ +/* Description: MD Request Credit Overflow Error */ +#define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT 17 +#define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000 + +/* SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW */ +/* Description: MD Reply Credit Overflow Error */ +#define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT 18 +#define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK 0x0000000000040000 + +/* SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW */ +/* Description: XN Request Credit Overflow Error */ +#define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT 19 +#define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000 + +/* SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW */ +/* Description: XN Reply Credit Overflow Error */ +#define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT 20 +#define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK 0x0000000000100000 + +/* SH_PI_FIRST_ERROR_HUNG_BUS */ +/* Description: FSB is hung */ +#define SH_PI_FIRST_ERROR_HUNG_BUS_SHFT 21 +#define SH_PI_FIRST_ERROR_HUNG_BUS_MASK 0x0000000000200000 + +/* SH_PI_FIRST_ERROR_RSP_PARITY */ +/* Description: Parity error detecte during response phase */ +#define SH_PI_FIRST_ERROR_RSP_PARITY_SHFT 22 +#define SH_PI_FIRST_ERROR_RSP_PARITY_MASK 0x0000000000400000 + +/* SH_PI_FIRST_ERROR_IOQ_OVERRUN */ +/* Description: Over run error detected on IOQ */ +#define SH_PI_FIRST_ERROR_IOQ_OVERRUN_SHFT 23 +#define SH_PI_FIRST_ERROR_IOQ_OVERRUN_MASK 0x0000000000800000 + +/* SH_PI_FIRST_ERROR_REQ_FORMAT */ +/* Description: FSB request format not supported */ +#define SH_PI_FIRST_ERROR_REQ_FORMAT_SHFT 24 +#define SH_PI_FIRST_ERROR_REQ_FORMAT_MASK 0x0000000001000000 + +/* SH_PI_FIRST_ERROR_ADDR_ACCESS */ +/* Description: Access to Address is not supported */ +#define SH_PI_FIRST_ERROR_ADDR_ACCESS_SHFT 25 +#define SH_PI_FIRST_ERROR_ADDR_ACCESS_MASK 0x0000000002000000 + +/* SH_PI_FIRST_ERROR_REQ_PARITY */ +/* Description: Parity error detected during request phase */ +#define SH_PI_FIRST_ERROR_REQ_PARITY_SHFT 26 +#define SH_PI_FIRST_ERROR_REQ_PARITY_MASK 0x0000000004000000 + +/* SH_PI_FIRST_ERROR_ADDR_PARITY */ +/* Description: Parity error detected on address */ +#define SH_PI_FIRST_ERROR_ADDR_PARITY_SHFT 27 +#define SH_PI_FIRST_ERROR_ADDR_PARITY_MASK 0x0000000008000000 + +/* SH_PI_FIRST_ERROR_SHUB_FSB_DQE */ +/* Description: SHUB_FSB_DQE */ +#define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_SHFT 28 +#define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_MASK 0x0000000010000000 + +/* SH_PI_FIRST_ERROR_SHUB_FSB_UCE */ +/* Description: An un-correctable ECC error was detected */ +#define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_SHFT 29 +#define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_MASK 0x0000000020000000 + +/* SH_PI_FIRST_ERROR_SHUB_FSB_CE */ +/* Description: An correctable ECC error was detected */ +#define SH_PI_FIRST_ERROR_SHUB_FSB_CE_SHFT 30 +#define SH_PI_FIRST_ERROR_SHUB_FSB_CE_MASK 0x0000000040000000 + +/* SH_PI_FIRST_ERROR_LIVELOCK */ +/* Description: AFI livelock error was detected */ +#define SH_PI_FIRST_ERROR_LIVELOCK_SHFT 31 +#define SH_PI_FIRST_ERROR_LIVELOCK_MASK 0x0000000080000000 + +/* SH_PI_FIRST_ERROR_BAD_SNOOP */ +/* Description: AFI bad snoop error was detected */ +#define SH_PI_FIRST_ERROR_BAD_SNOOP_SHFT 32 +#define SH_PI_FIRST_ERROR_BAD_SNOOP_MASK 0x0000000100000000 + +/* SH_PI_FIRST_ERROR_FSB_TBL_MISS */ +/* Description: AFI FSB request table miss error was detected */ +#define SH_PI_FIRST_ERROR_FSB_TBL_MISS_SHFT 33 +#define SH_PI_FIRST_ERROR_FSB_TBL_MISS_MASK 0x0000000200000000 + +/* SH_PI_FIRST_ERROR_MSG_LENGTH */ +/* Description: Message length error on received message from SIC */ +#define SH_PI_FIRST_ERROR_MSG_LENGTH_SHFT 34 +#define SH_PI_FIRST_ERROR_MSG_LENGTH_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_PI_FIRST_ERROR_ALIAS" */ +/* PI First Error Alias */ +/* ==================================================================== */ + +#define SH_PI_FIRST_ERROR_ALIAS 0x0000000120060788 + +/* ==================================================================== */ +/* Register "SH_PI_PI2MD_REPLY_VC_STATUS" */ +/* PI-to-MD Reply Virtual Channel Status */ +/* ==================================================================== */ + +#define SH_PI_PI2MD_REPLY_VC_STATUS 0x0000000120060900 +#define SH_PI_PI2MD_REPLY_VC_STATUS_MASK 0x000000000000003f +#define SH_PI_PI2MD_REPLY_VC_STATUS_INIT 0x0000000000000000 + +/* SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT */ +/* Description: Status of output credits */ +#define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 +#define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f + +/* ==================================================================== */ +/* Register "SH_PI_PI2MD_REQUEST_VC_STATUS" */ +/* PI-to-MD Request Virtual Channel Status */ +/* ==================================================================== */ + +#define SH_PI_PI2MD_REQUEST_VC_STATUS 0x0000000120060980 +#define SH_PI_PI2MD_REQUEST_VC_STATUS_MASK 0x000000000000003f +#define SH_PI_PI2MD_REQUEST_VC_STATUS_INIT 0x0000000000000000 + +/* SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT */ +/* Description: Status of output credits */ +#define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 +#define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f + +/* ==================================================================== */ +/* Register "SH_PI_PI2XN_REPLY_VC_STATUS" */ +/* PI-to-XN Reply Virtual Channel Status */ +/* ==================================================================== */ + +#define SH_PI_PI2XN_REPLY_VC_STATUS 0x0000000120060a00 +#define SH_PI_PI2XN_REPLY_VC_STATUS_MASK 0x000000000000003f +#define SH_PI_PI2XN_REPLY_VC_STATUS_INIT 0x0000000000000000 + +/* SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT */ +/* Description: Status of output credits */ +#define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 +#define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f + +/* ==================================================================== */ +/* Register "SH_PI_PI2XN_REQUEST_VC_STATUS" */ +/* PI-to-XN Request Virtual Channel Status */ +/* ==================================================================== */ + +#define SH_PI_PI2XN_REQUEST_VC_STATUS 0x0000000120060a80 +#define SH_PI_PI2XN_REQUEST_VC_STATUS_MASK 0x000000000000003f +#define SH_PI_PI2XN_REQUEST_VC_STATUS_INIT 0x0000000000000000 + +/* SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT */ +/* Description: Status of output credits */ +#define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0 +#define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f + +/* ==================================================================== */ +/* Register "SH_PI_UNCORRECTED_DETAIL_1" */ +/* PI Uncorrected Error Detail 1 */ +/* ==================================================================== */ + +#define SH_PI_UNCORRECTED_DETAIL_1 0x0000000120060b00 +#define SH_PI_UNCORRECTED_DETAIL_1_MASK 0xffffffffffffffff +#define SH_PI_UNCORRECTED_DETAIL_1_INIT 0x0000000000000000 + +/* SH_PI_UNCORRECTED_DETAIL_1_ADDRESS */ +/* Description: Address of Message that logged Uncorrectable Error */ +#define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_SHFT 0 +#define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_MASK 0x0000ffffffffffff + +/* SH_PI_UNCORRECTED_DETAIL_1_SYNDROME */ +/* Description: Syndrome for double word data with Uncorrectable Er */ +#define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_SHFT 48 +#define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_MASK 0x00ff000000000000 + +/* SH_PI_UNCORRECTED_DETAIL_1_DEP */ +/* Description: DEP for Double word in error */ +#define SH_PI_UNCORRECTED_DETAIL_1_DEP_SHFT 56 +#define SH_PI_UNCORRECTED_DETAIL_1_DEP_MASK 0xff00000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_UNCORRECTED_DETAIL_2" */ +/* PI Uncorrected Error Detail 2 */ +/* ==================================================================== */ + +#define SH_PI_UNCORRECTED_DETAIL_2 0x0000000120060b80 +#define SH_PI_UNCORRECTED_DETAIL_2_MASK 0xffffffffffffffff +#define SH_PI_UNCORRECTED_DETAIL_2_INIT 0x0000000000000000 + +/* SH_PI_UNCORRECTED_DETAIL_2_DATA */ +/* Description: Double word data in error */ +#define SH_PI_UNCORRECTED_DETAIL_2_DATA_SHFT 0 +#define SH_PI_UNCORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_PI_UNCORRECTED_DETAIL_3" */ +/* PI Uncorrected Error Detail 3 */ +/* ==================================================================== */ + +#define SH_PI_UNCORRECTED_DETAIL_3 0x0000000120060c00 +#define SH_PI_UNCORRECTED_DETAIL_3_MASK 0xffffffffffffffff +#define SH_PI_UNCORRECTED_DETAIL_3_INIT 0x0000000000000000 + +/* SH_PI_UNCORRECTED_DETAIL_3_ADDRESS */ +/* Description: Address of Message that logged Uncorrectable Error */ +#define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_SHFT 0 +#define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_MASK 0x0000ffffffffffff + +/* SH_PI_UNCORRECTED_DETAIL_3_SYNDROME */ +/* Description: Syndrome for double word data with Uncorrectable Er */ +#define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_SHFT 48 +#define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_MASK 0x00ff000000000000 + +/* SH_PI_UNCORRECTED_DETAIL_3_DEP */ +/* Description: DCP for Double word in error */ +#define SH_PI_UNCORRECTED_DETAIL_3_DEP_SHFT 56 +#define SH_PI_UNCORRECTED_DETAIL_3_DEP_MASK 0xff00000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_UNCORRECTED_DETAIL_4" */ +/* PI Uncorrected Error Detail 4 */ +/* ==================================================================== */ + +#define SH_PI_UNCORRECTED_DETAIL_4 0x0000000120060c80 +#define SH_PI_UNCORRECTED_DETAIL_4_MASK 0xffffffffffffffff +#define SH_PI_UNCORRECTED_DETAIL_4_INIT 0x0000000000000000 + +/* SH_PI_UNCORRECTED_DETAIL_4_DATA */ +/* Description: Double word data in error */ +#define SH_PI_UNCORRECTED_DETAIL_4_DATA_SHFT 0 +#define SH_PI_UNCORRECTED_DETAIL_4_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_PI_MD2PI_REPLY_VC_STATUS" */ +/* MD-to-PI Reply Virtual Channel Status */ +/* ==================================================================== */ + +#define SH_PI_MD2PI_REPLY_VC_STATUS 0x0000000120060800 +#define SH_PI_MD2PI_REPLY_VC_STATUS_MASK 0x0000000000000fff +#define SH_PI_MD2PI_REPLY_VC_STATUS_INIT 0x0000000000000000 + +/* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT */ +/* Description: Status of input header credits */ +#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 +#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f + +/* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT */ +/* Description: Status of data credits */ +#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 +#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 + +/* SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT */ +/* Description: Status of MD Reply Input Queue */ +#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 +#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 + +/* ==================================================================== */ +/* Register "SH_PI_MD2PI_REQUEST_VC_STATUS" */ +/* MD-to-PI Request Virtual Channel Status */ +/* ==================================================================== */ + +#define SH_PI_MD2PI_REQUEST_VC_STATUS 0x0000000120060880 +#define SH_PI_MD2PI_REQUEST_VC_STATUS_MASK 0x0000000000000fff +#define SH_PI_MD2PI_REQUEST_VC_STATUS_INIT 0x0000000000000000 + +/* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT */ +/* Description: Status of input header credits */ +#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 +#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f + +/* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT */ +/* Description: Status of input data credits */ +#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 +#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 + +/* SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT */ +/* Description: Status of MD Request Input Queue */ +#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 +#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 + +/* ==================================================================== */ +/* Register "SH_PI_XN2PI_REPLY_VC_STATUS" */ +/* XN-to-PI Reply Virtual Channel Status */ +/* ==================================================================== */ + +#define SH_PI_XN2PI_REPLY_VC_STATUS 0x0000000120060d00 +#define SH_PI_XN2PI_REPLY_VC_STATUS_MASK 0x0000000000000fff +#define SH_PI_XN2PI_REPLY_VC_STATUS_INIT 0x0000000000000000 + +/* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT */ +/* Description: Status of input header credits */ +#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 +#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f + +/* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT */ +/* Description: Status of input data credits */ +#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 +#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 + +/* SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT */ +/* Description: Status of XN Reply Input Queue */ +#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 +#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 + +/* ==================================================================== */ +/* Register "SH_PI_XN2PI_REQUEST_VC_STATUS" */ +/* XN-to-PI Request Virtual Channel Status */ +/* ==================================================================== */ + +#define SH_PI_XN2PI_REQUEST_VC_STATUS 0x0000000120060d80 +#define SH_PI_XN2PI_REQUEST_VC_STATUS_MASK 0x0000000000000fff +#define SH_PI_XN2PI_REQUEST_VC_STATUS_INIT 0x0000000000000000 + +/* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT */ +/* Description: Status of input header credits */ +#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0 +#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f + +/* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT */ +/* Description: Status of input data credits */ +#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4 +#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0 + +/* SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT */ +/* Description: Status of XN Request Input Queue */ +#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8 +#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00 + +/* ==================================================================== */ +/* Register "SH_XNPI_SIC_FLOW" */ +/* ==================================================================== */ + +#define SH_XNPI_SIC_FLOW 0x0000000150030000 +#define SH_XNPI_SIC_FLOW_MASK 0x9f1f1f1f1f1f9f9f +#define SH_XNPI_SIC_FLOW_INIT 0x0000080000080000 + +/* SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f + +/* SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00 + +/* SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_SHFT 16 +#define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_MASK 0x00000000001f0000 + +/* SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_MASK 0x000000001f000000 + +/* SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_MASK 0x0000001f00000000 + +/* SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_SHFT 40 +#define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_MASK 0x00001f0000000000 + +/* SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_MASK 0x001f000000000000 + +/* SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_MASK 0x1f00000000000000 + +/* SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT */ +#define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63 +#define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNPI_TO_NI0_PORT_FLOW" */ +/* ==================================================================== */ + +#define SH_XNPI_TO_NI0_PORT_FLOW 0x0000000150030010 +#define SH_XNPI_TO_NI0_PORT_FLOW_MASK 0x3f3f003f3f00bfbf +#define SH_XNPI_TO_NI0_PORT_FLOW_INIT 0x0000000000000000 + +/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 + +/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 + +/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 + +/* SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNPI_TO_NI1_PORT_FLOW" */ +/* ==================================================================== */ + +#define SH_XNPI_TO_NI1_PORT_FLOW 0x0000000150030020 +#define SH_XNPI_TO_NI1_PORT_FLOW_MASK 0x3f3f003f3f00bfbf +#define SH_XNPI_TO_NI1_PORT_FLOW_INIT 0x0000000000000000 + +/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 + +/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 + +/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 + +/* SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNPI_TO_IILB_PORT_FLOW" */ +/* ==================================================================== */ + +#define SH_XNPI_TO_IILB_PORT_FLOW 0x0000000150030030 +#define SH_XNPI_TO_IILB_PORT_FLOW_MASK 0x3f3f003f3f00bfbf +#define SH_XNPI_TO_IILB_PORT_FLOW_INIT 0x0000000000000000 + +/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 + +/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 + +/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 + +/* SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO 0x0000000150030040 +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 + +/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ +/* Description: vc0 fifo entry dynamic value */ +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f + +/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ +/* Description: vc0 fifo entry captured value */ +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 + +/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ +/* Description: vc2 fifo entry dynamic value */ +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 + +/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ +/* Description: vc2 fifo entry captured value */ +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 + +/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ +/* Description: vc0 test credits limit */ +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 + +/* SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ +/* Description: vc2 test credits limit */ +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 +#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO 0x0000000150030050 +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 + +/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ +/* Description: vc0 fifo entry dynamic value */ +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f + +/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ +/* Description: vc0 fifo entry captured value */ +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 + +/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ +/* Description: vc2 fifo entry dynamic value */ +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 + +/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ +/* Description: vc2 fifo entry captured value */ +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 + +/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ +/* Description: vc0 test credits limit */ +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 + +/* SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ +/* Description: vc2 test credits limit */ +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 +#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO 0x0000000150030060 +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 + +/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ +/* Description: vc0 fifo entry dynamic value */ +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f + +/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ +/* Description: vc0 fifo entry captured value */ +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 + +/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ +/* Description: vc2 fifo entry dynamic value */ +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 + +/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ +/* Description: vc2 fifo entry captured value */ +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 + +/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ +/* Description: vc0 test credits limit */ +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 + +/* SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ +/* Description: vc2 test credits limit */ +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 +#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_SIC_FLOW" */ +/* ==================================================================== */ + +#define SH_XNMD_SIC_FLOW 0x0000000150030100 +#define SH_XNMD_SIC_FLOW_MASK 0x9f1f1f1f1f1f9f9f +#define SH_XNMD_SIC_FLOW_INIT 0x0000090000090000 + +/* SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f + +/* SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00 + +/* SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_SHFT 16 +#define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_MASK 0x00000000001f0000 + +/* SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_MASK 0x000000001f000000 + +/* SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_MASK 0x0000001f00000000 + +/* SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_SHFT 40 +#define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_MASK 0x00001f0000000000 + +/* SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_MASK 0x001f000000000000 + +/* SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_MASK 0x1f00000000000000 + +/* SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT */ +#define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63 +#define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_TO_NI0_PORT_FLOW" */ +/* ==================================================================== */ + +#define SH_XNMD_TO_NI0_PORT_FLOW 0x0000000150030110 +#define SH_XNMD_TO_NI0_PORT_FLOW_MASK 0x3f3f003f3f00bfbf +#define SH_XNMD_TO_NI0_PORT_FLOW_INIT 0x0000000000000000 + +/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 + +/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 + +/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 + +/* SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_TO_NI1_PORT_FLOW" */ +/* ==================================================================== */ + +#define SH_XNMD_TO_NI1_PORT_FLOW 0x0000000150030120 +#define SH_XNMD_TO_NI1_PORT_FLOW_MASK 0x3f3f003f3f00bfbf +#define SH_XNMD_TO_NI1_PORT_FLOW_INIT 0x0000000000000000 + +/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 + +/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 + +/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 + +/* SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_TO_IILB_PORT_FLOW" */ +/* ==================================================================== */ + +#define SH_XNMD_TO_IILB_PORT_FLOW 0x0000000150030130 +#define SH_XNMD_TO_IILB_PORT_FLOW_MASK 0x3f3f003f3f00bfbf +#define SH_XNMD_TO_IILB_PORT_FLOW_INIT 0x0000000000000000 + +/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000 + +/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000 + +/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000 + +/* SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO 0x0000000150030140 +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 + +/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ +/* Description: vc0 fifo entry dynamic value */ +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f + +/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ +/* Description: vc0 fifo entry captured value */ +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 + +/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ +/* Description: vc2 fifo entry dynamic value */ +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 + +/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ +/* Description: vc2 fifo entry captured value */ +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 + +/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ +/* Description: vc0 test credits limit */ +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 + +/* SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ +/* Description: vc2 test credits limit */ +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 +#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO 0x0000000150030150 +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 + +/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ +/* Description: vc0 fifo entry dynamic value */ +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f + +/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ +/* Description: vc0 fifo entry captured value */ +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 + +/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ +/* Description: vc2 fifo entry dynamic value */ +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 + +/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ +/* Description: vc2 fifo entry captured value */ +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 + +/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ +/* Description: vc0 test credits limit */ +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 + +/* SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ +/* Description: vc2 test credits limit */ +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 +#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO 0x0000000150030160 +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_MASK 0x00001f1f3f3f3f3f +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_INIT 0x00000c0c00000000 + +/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN */ +/* Description: vc0 fifo entry dynamic value */ +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0 +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f + +/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP */ +/* Description: vc0 fifo entry captured value */ +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8 +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00 + +/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN */ +/* Description: vc2 fifo entry dynamic value */ +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16 +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000 + +/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP */ +/* Description: vc2 fifo entry captured value */ +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24 +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000 + +/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST */ +/* Description: vc0 test credits limit */ +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32 +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000 + +/* SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST */ +/* Description: vc2 test credits limit */ +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40 +#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNII_INTRA_FLOW" */ +/* ==================================================================== */ + +#define SH_XNII_INTRA_FLOW 0x0000000150030200 +#define SH_XNII_INTRA_FLOW_MASK 0x7f7f7f7f7f7fbfbf +#define SH_XNII_INTRA_FLOW_INIT 0x00003f00003f0000 + +/* SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 16 +#define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x00000000007f0000 + +/* SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 40 +#define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x00007f0000000000 + +/* SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNLB_INTRA_FLOW" */ +/* ==================================================================== */ + +#define SH_XNLB_INTRA_FLOW 0x0000000150030210 +#define SH_XNLB_INTRA_FLOW_MASK 0xff7f7f7f7f7fbfbf +#define SH_XNLB_INTRA_FLOW_INIT 0x0000080000100000 + +/* SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 16 +#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x00000000007f0000 + +/* SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 24 +#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 32 +#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 40 +#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x00007f0000000000 + +/* SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 48 +#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 56 +#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x7f00000000000000 + +/* SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN */ +#define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_SHFT 63 +#define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT 0x0000000150030220 +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 + +/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 +#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT 0x0000000150030230 +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 + +/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 +#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030240 +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 + +/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 +#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030250 +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 + +/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 +#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030260 +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 + +/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 +#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT 0x0000000150030270 +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c + +/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f + +/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 + +/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 + +/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 + +/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 + +/* SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 +#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT 0x0000000150030280 +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c + +/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f + +/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 + +/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 + +/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 + +/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 + +/* SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 +#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030290 +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c + +/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f + +/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 + +/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 + +/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 + +/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 + +/* SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 +#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT 0x00000001500302a0 +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c + +/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f + +/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 + +/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 + +/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 + +/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 + +/* SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 +#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT 0x00000001500302b0 +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c + +/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f + +/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 + +/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 + +/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 + +/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 + +/* SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 +#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030300 +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 + +/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 +#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030310 +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 + +/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 +#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030320 +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 + +/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 +#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT 0x0000000150030330 +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c + +/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f + +/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 + +/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 + +/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 + +/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 + +/* SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 +#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030340 +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c + +/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f + +/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 + +/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 + +/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 + +/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 + +/* SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 +#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT 0x0000000150030350 +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c + +/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f + +/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 + +/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 + +/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 + +/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 + +/* SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 +#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_0_INTRANI_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_0_INTRANI_FLOW 0x0000000150030360 +#define SH_XNNI0_0_INTRANI_FLOW_MASK 0x00000000000000bf +#define SH_XNNI0_0_INTRANI_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_XNNI0_1_INTRANI_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_1_INTRANI_FLOW 0x0000000150030370 +#define SH_XNNI0_1_INTRANI_FLOW_MASK 0x00000000000000bf +#define SH_XNNI0_1_INTRANI_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD */ +/* Description: vc1 withhold */ +#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 +#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED */ +/* Description: Force Credit on VC1 from debit cntr */ +#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 +#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_XNNI0_2_INTRANI_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_2_INTRANI_FLOW 0x0000000150030380 +#define SH_XNNI0_2_INTRANI_FLOW_MASK 0x00000000000000bf +#define SH_XNNI0_2_INTRANI_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 +#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 +#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_XNNI0_3_INTRANI_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_3_INTRANI_FLOW 0x0000000150030390 +#define SH_XNNI0_3_INTRANI_FLOW_MASK 0x00000000000000bf +#define SH_XNNI0_3_INTRANI_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD */ +/* Description: vc3 withhold */ +#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 +#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED */ +/* Description: Force Credit on VC3 from debit cntr */ +#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 +#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_XNNI0_VCSWITCH_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_VCSWITCH_FLOW 0x00000001500303a0 +#define SH_XNNI0_VCSWITCH_FLOW_MASK 0x0000000701010101 +#define SH_XNNI0_VCSWITCH_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH */ +/* Description: Swap VC0/2 with VC1/3 */ +#define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0 +#define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001 + +/* SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH */ +/* Description: Swap VC0/2 with VC1/3 */ +#define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8 +#define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100 + +/* SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH */ +/* Description: Swap VC0/2 with VC1/3 */ +#define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16 +#define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000 + +/* SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH */ +/* Description: Swap VC0/2 with VC1/3 */ +#define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24 +#define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000 + +/* SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN */ +#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32 +#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000 + +/* SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT */ +#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33 +#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000 + +/* SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES */ +#define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34 +#define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_TIMER_REG" */ +/* ==================================================================== */ + +#define SH_XNNI0_TIMER_REG 0x00000001500303b0 +#define SH_XNNI0_TIMER_REG_MASK 0x0000000100ffffff +#define SH_XNNI0_TIMER_REG_INIT 0x0000000000ffffff + +/* SH_XNNI0_TIMER_REG_TIMEOUT_REG */ +/* Description: Master Timeout Counter */ +#define SH_XNNI0_TIMER_REG_TIMEOUT_REG_SHFT 0 +#define SH_XNNI0_TIMER_REG_TIMEOUT_REG_MASK 0x0000000000ffffff + +/* SH_XNNI0_TIMER_REG_LINKCLEANUP_REG */ +/* Description: Link Clean Up */ +#define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_SHFT 32 +#define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_MASK 0x0000000100000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_FIFO02_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_FIFO02_FLOW 0x00000001500303c0 +#define SH_XNNI0_FIFO02_FLOW_MASK 0x00000f0f0f0f0f0f +#define SH_XNNI0_FIFO02_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT */ +/* Description: limit reg zero disables functionality */ +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0 +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f + +/* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN */ +/* Description: dynamic counter value */ +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_SHFT 8 +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_MASK 0x0000000000000f00 + +/* SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP */ +/* Description: captured counter value */ +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_SHFT 16 +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_MASK 0x00000000000f0000 + +/* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT */ +/* Description: limit reg zero disables functionality */ +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24 +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000 + +/* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN */ +/* Description: counter dynamic value */ +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_SHFT 32 +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_MASK 0x0000000f00000000 + +/* SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP */ +/* Description: captured counter value */ +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_SHFT 40 +#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_MASK 0x00000f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_FIFO13_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_FIFO13_FLOW 0x00000001500303d0 +#define SH_XNNI0_FIFO13_FLOW_MASK 0x00000f0f0f0f0f0f +#define SH_XNNI0_FIFO13_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT */ +/* Description: limit reg zero disables functionality */ +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0 +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f + +/* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN */ +/* Description: dynamic counter value */ +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_SHFT 8 +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_MASK 0x0000000000000f00 + +/* SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP */ +/* Description: captured counter value */ +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_SHFT 16 +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_MASK 0x00000000000f0000 + +/* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT */ +/* Description: limit reg zero disables functionality */ +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24 +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000 + +/* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN */ +/* Description: counter dynamic value */ +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_SHFT 32 +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_MASK 0x0000000f00000000 + +/* SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP */ +/* Description: captured counter value */ +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_SHFT 40 +#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_MASK 0x00000f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_NI_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_NI_FLOW 0x00000001500303e0 +#define SH_XNNI0_NI_FLOW_MASK 0xff0fff0fff0fff0f +#define SH_XNNI0_NI_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_NI_FLOW_VC0_LIMIT */ +/* Description: vc0 limit reg, zero disables functionality */ +#define SH_XNNI0_NI_FLOW_VC0_LIMIT_SHFT 0 +#define SH_XNNI0_NI_FLOW_VC0_LIMIT_MASK 0x000000000000000f + +/* SH_XNNI0_NI_FLOW_VC0_DYN */ +/* Description: vc0 counter dynamic value */ +#define SH_XNNI0_NI_FLOW_VC0_DYN_SHFT 8 +#define SH_XNNI0_NI_FLOW_VC0_DYN_MASK 0x0000000000000f00 + +/* SH_XNNI0_NI_FLOW_VC0_CAP */ +/* Description: vc0 counter captured value */ +#define SH_XNNI0_NI_FLOW_VC0_CAP_SHFT 12 +#define SH_XNNI0_NI_FLOW_VC0_CAP_MASK 0x000000000000f000 + +/* SH_XNNI0_NI_FLOW_VC1_LIMIT */ +/* Description: vc1 limit reg, zero disables functionality */ +#define SH_XNNI0_NI_FLOW_VC1_LIMIT_SHFT 16 +#define SH_XNNI0_NI_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 + +/* SH_XNNI0_NI_FLOW_VC1_DYN */ +/* Description: vc1 counter dynamic value */ +#define SH_XNNI0_NI_FLOW_VC1_DYN_SHFT 24 +#define SH_XNNI0_NI_FLOW_VC1_DYN_MASK 0x000000000f000000 + +/* SH_XNNI0_NI_FLOW_VC1_CAP */ +/* Description: vc1 counter captured value */ +#define SH_XNNI0_NI_FLOW_VC1_CAP_SHFT 28 +#define SH_XNNI0_NI_FLOW_VC1_CAP_MASK 0x00000000f0000000 + +/* SH_XNNI0_NI_FLOW_VC2_LIMIT */ +/* Description: vc2 limit reg, zero disables functionality */ +#define SH_XNNI0_NI_FLOW_VC2_LIMIT_SHFT 32 +#define SH_XNNI0_NI_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 + +/* SH_XNNI0_NI_FLOW_VC2_DYN */ +/* Description: vc2 counter dynamic value */ +#define SH_XNNI0_NI_FLOW_VC2_DYN_SHFT 40 +#define SH_XNNI0_NI_FLOW_VC2_DYN_MASK 0x00000f0000000000 + +/* SH_XNNI0_NI_FLOW_VC2_CAP */ +/* Description: vc2 counter captured value */ +#define SH_XNNI0_NI_FLOW_VC2_CAP_SHFT 44 +#define SH_XNNI0_NI_FLOW_VC2_CAP_MASK 0x0000f00000000000 + +/* SH_XNNI0_NI_FLOW_VC3_LIMIT */ +/* Description: vc3 limit reg, zero disables functionality */ +#define SH_XNNI0_NI_FLOW_VC3_LIMIT_SHFT 48 +#define SH_XNNI0_NI_FLOW_VC3_LIMIT_MASK 0x000f000000000000 + +/* SH_XNNI0_NI_FLOW_VC3_DYN */ +/* Description: vc3 counter dynamic value */ +#define SH_XNNI0_NI_FLOW_VC3_DYN_SHFT 56 +#define SH_XNNI0_NI_FLOW_VC3_DYN_MASK 0x0f00000000000000 + +/* SH_XNNI0_NI_FLOW_VC3_CAP */ +/* Description: vc3 counter captured value */ +#define SH_XNNI0_NI_FLOW_VC3_CAP_SHFT 60 +#define SH_XNNI0_NI_FLOW_VC3_CAP_MASK 0xf000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_DEAD_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI0_DEAD_FLOW 0x00000001500303f0 +#define SH_XNNI0_DEAD_FLOW_MASK 0xff0fff0fff0fff0f +#define SH_XNNI0_DEAD_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI0_DEAD_FLOW_VC0_LIMIT */ +/* Description: vc0 limit reg, zero disables functionality */ +#define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_SHFT 0 +#define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_MASK 0x000000000000000f + +/* SH_XNNI0_DEAD_FLOW_VC0_DYN */ +/* Description: vc0 counter dynamic value */ +#define SH_XNNI0_DEAD_FLOW_VC0_DYN_SHFT 8 +#define SH_XNNI0_DEAD_FLOW_VC0_DYN_MASK 0x0000000000000f00 + +/* SH_XNNI0_DEAD_FLOW_VC0_CAP */ +/* Description: vc0 counter captured value */ +#define SH_XNNI0_DEAD_FLOW_VC0_CAP_SHFT 12 +#define SH_XNNI0_DEAD_FLOW_VC0_CAP_MASK 0x000000000000f000 + +/* SH_XNNI0_DEAD_FLOW_VC1_LIMIT */ +/* Description: vc1 limit reg, zero disables functionality */ +#define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_SHFT 16 +#define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 + +/* SH_XNNI0_DEAD_FLOW_VC1_DYN */ +/* Description: vc1 counter dynamic value */ +#define SH_XNNI0_DEAD_FLOW_VC1_DYN_SHFT 24 +#define SH_XNNI0_DEAD_FLOW_VC1_DYN_MASK 0x000000000f000000 + +/* SH_XNNI0_DEAD_FLOW_VC1_CAP */ +/* Description: vc1 counter captured value */ +#define SH_XNNI0_DEAD_FLOW_VC1_CAP_SHFT 28 +#define SH_XNNI0_DEAD_FLOW_VC1_CAP_MASK 0x00000000f0000000 + +/* SH_XNNI0_DEAD_FLOW_VC2_LIMIT */ +/* Description: vc2 limit reg, zero disables functionality */ +#define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_SHFT 32 +#define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 + +/* SH_XNNI0_DEAD_FLOW_VC2_DYN */ +/* Description: vc2 counter dynamic value */ +#define SH_XNNI0_DEAD_FLOW_VC2_DYN_SHFT 40 +#define SH_XNNI0_DEAD_FLOW_VC2_DYN_MASK 0x00000f0000000000 + +/* SH_XNNI0_DEAD_FLOW_VC2_CAP */ +/* Description: vc2 counter captured value */ +#define SH_XNNI0_DEAD_FLOW_VC2_CAP_SHFT 44 +#define SH_XNNI0_DEAD_FLOW_VC2_CAP_MASK 0x0000f00000000000 + +/* SH_XNNI0_DEAD_FLOW_VC3_LIMIT */ +/* Description: vc3 limit reg, zero disables functionality */ +#define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_SHFT 48 +#define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_MASK 0x000f000000000000 + +/* SH_XNNI0_DEAD_FLOW_VC3_DYN */ +/* Description: vc3 counter dynamic value */ +#define SH_XNNI0_DEAD_FLOW_VC3_DYN_SHFT 56 +#define SH_XNNI0_DEAD_FLOW_VC3_DYN_MASK 0x0f00000000000000 + +/* SH_XNNI0_DEAD_FLOW_VC3_CAP */ +/* Description: vc3 counter captured value */ +#define SH_XNNI0_DEAD_FLOW_VC3_CAP_SHFT 60 +#define SH_XNNI0_DEAD_FLOW_VC3_CAP_MASK 0xf000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI0_INJECT_AGE" */ +/* ==================================================================== */ + +#define SH_XNNI0_INJECT_AGE 0x0000000150030400 +#define SH_XNNI0_INJECT_AGE_MASK 0x000000000000ffff +#define SH_XNNI0_INJECT_AGE_INIT 0x0000000000000000 + +/* SH_XNNI0_INJECT_AGE_REQUEST_INJECT */ +/* Description: Value of AGE field for outgoing requests */ +#define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_SHFT 0 +#define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_MASK 0x00000000000000ff + +/* SH_XNNI0_INJECT_AGE_REPLY_INJECT */ +/* Description: Value of AGE field for outgoing replies */ +#define SH_XNNI0_INJECT_AGE_REPLY_INJECT_SHFT 8 +#define SH_XNNI0_INJECT_AGE_REPLY_INJECT_MASK 0x000000000000ff00 + +/* ==================================================================== */ +/* Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT 0x0000000150030500 +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 + +/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 +#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT 0x0000000150030510 +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 + +/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 +#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT 0x0000000150030520 +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_MASK 0x7f7f007f7f00bfbf +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_INIT 0x0000000000000000 + +/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8 +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00 + +/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15 +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000 + +/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN */ +/* Description: vc0 debit dynamic value */ +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24 +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000 + +/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP */ +/* Description: vc0 debit captured value */ +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32 +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000 + +/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN */ +/* Description: vc2 debit dynamic value */ +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48 +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000 + +/* SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP */ +/* Description: vc2 debit captured value */ +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56 +#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT 0x0000000150030530 +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c + +/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f + +/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 + +/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 + +/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 + +/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 + +/* SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 +#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT 0x0000000150030540 +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c + +/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f + +/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 + +/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 + +/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 + +/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 + +/* SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 +#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT 0x0000000150030550 +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c + +/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST */ +/* Description: vc0 credit_test */ +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0 +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f + +/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN */ +/* Description: vc0 credit dynamic value */ +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8 +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00 + +/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP */ +/* Description: vc0 credit captured value */ +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16 +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000 + +/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST */ +/* Description: vc2 credit_test */ +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24 +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000 + +/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN */ +/* Description: vc2 credit dynamic value */ +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32 +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000 + +/* SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP */ +/* Description: vc2 credit captured value */ +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40 +#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_0_INTRANI_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_0_INTRANI_FLOW 0x0000000150030560 +#define SH_XNNI1_0_INTRANI_FLOW_MASK 0x00000000000000bf +#define SH_XNNI1_0_INTRANI_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD */ +/* Description: vc0 withhold */ +#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0 +#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED */ +/* Description: Force Credit on VC0 from debit cntr */ +#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7 +#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_XNNI1_1_INTRANI_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_1_INTRANI_FLOW 0x0000000150030570 +#define SH_XNNI1_1_INTRANI_FLOW_MASK 0x00000000000000bf +#define SH_XNNI1_1_INTRANI_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD */ +/* Description: vc1 withhold */ +#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0 +#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED */ +/* Description: Force Credit on VC1 from debit cntr */ +#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7 +#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_XNNI1_2_INTRANI_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_2_INTRANI_FLOW 0x0000000150030580 +#define SH_XNNI1_2_INTRANI_FLOW_MASK 0x00000000000000bf +#define SH_XNNI1_2_INTRANI_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD */ +/* Description: vc2 withhold */ +#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0 +#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED */ +/* Description: Force Credit on VC2 from debit cntr */ +#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7 +#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_XNNI1_3_INTRANI_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_3_INTRANI_FLOW 0x0000000150030590 +#define SH_XNNI1_3_INTRANI_FLOW_MASK 0x00000000000000bf +#define SH_XNNI1_3_INTRANI_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD */ +/* Description: vc3 withhold */ +#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0 +#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f + +/* SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED */ +/* Description: Force Credit on VC3 from debit cntr */ +#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7 +#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_XNNI1_VCSWITCH_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_VCSWITCH_FLOW 0x00000001500305a0 +#define SH_XNNI1_VCSWITCH_FLOW_MASK 0x0000000701010101 +#define SH_XNNI1_VCSWITCH_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH */ +/* Description: Swap VC0/2 with VC1/3 */ +#define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0 +#define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001 + +/* SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH */ +/* Description: Swap VC0/2 with VC1/3 */ +#define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8 +#define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100 + +/* SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH */ +/* Description: Swap VC0/2 with VC1/3 */ +#define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16 +#define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000 + +/* SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH */ +/* Description: Swap VC0/2 with VC1/3 */ +#define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24 +#define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000 + +/* SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN */ +#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32 +#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000 + +/* SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT */ +#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33 +#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000 + +/* SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES */ +#define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34 +#define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_TIMER_REG" */ +/* ==================================================================== */ + +#define SH_XNNI1_TIMER_REG 0x00000001500305b0 +#define SH_XNNI1_TIMER_REG_MASK 0x0000000100ffffff +#define SH_XNNI1_TIMER_REG_INIT 0x0000000000ffffff + +/* SH_XNNI1_TIMER_REG_TIMEOUT_REG */ +/* Description: Master Timeout Counter */ +#define SH_XNNI1_TIMER_REG_TIMEOUT_REG_SHFT 0 +#define SH_XNNI1_TIMER_REG_TIMEOUT_REG_MASK 0x0000000000ffffff + +/* SH_XNNI1_TIMER_REG_LINKCLEANUP_REG */ +/* Description: Link Clean Up */ +#define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_SHFT 32 +#define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_MASK 0x0000000100000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_FIFO02_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_FIFO02_FLOW 0x00000001500305c0 +#define SH_XNNI1_FIFO02_FLOW_MASK 0x00000f0f0f0f0f0f +#define SH_XNNI1_FIFO02_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT */ +/* Description: limit reg zero disables functionality */ +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0 +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f + +/* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN */ +/* Description: dynamic counter value */ +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_SHFT 8 +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_MASK 0x0000000000000f00 + +/* SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP */ +/* Description: captured counter value */ +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_SHFT 16 +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_MASK 0x00000000000f0000 + +/* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT */ +/* Description: limit reg zero disables functionality */ +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24 +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000 + +/* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN */ +/* Description: counter dynamic value */ +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_SHFT 32 +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_MASK 0x0000000f00000000 + +/* SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP */ +/* Description: captured counter value */ +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_SHFT 40 +#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_MASK 0x00000f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_FIFO13_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_FIFO13_FLOW 0x00000001500305d0 +#define SH_XNNI1_FIFO13_FLOW_MASK 0x00000f0f0f0f0f0f +#define SH_XNNI1_FIFO13_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT */ +/* Description: limit reg zero disables functionality */ +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0 +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f + +/* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN */ +/* Description: dynamic counter value */ +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_SHFT 8 +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_MASK 0x0000000000000f00 + +/* SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP */ +/* Description: captured counter value */ +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_SHFT 16 +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_MASK 0x00000000000f0000 + +/* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT */ +/* Description: limit reg zero disables functionality */ +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24 +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000 + +/* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN */ +/* Description: counter dynamic value */ +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_SHFT 32 +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_MASK 0x0000000f00000000 + +/* SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP */ +/* Description: captured counter value */ +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_SHFT 40 +#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_MASK 0x00000f0000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_NI_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_NI_FLOW 0x00000001500305e0 +#define SH_XNNI1_NI_FLOW_MASK 0xff0fff0fff0fff0f +#define SH_XNNI1_NI_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_NI_FLOW_VC0_LIMIT */ +/* Description: vc0 limit reg, zero disables functionality */ +#define SH_XNNI1_NI_FLOW_VC0_LIMIT_SHFT 0 +#define SH_XNNI1_NI_FLOW_VC0_LIMIT_MASK 0x000000000000000f + +/* SH_XNNI1_NI_FLOW_VC0_DYN */ +/* Description: vc0 counter dynamic value */ +#define SH_XNNI1_NI_FLOW_VC0_DYN_SHFT 8 +#define SH_XNNI1_NI_FLOW_VC0_DYN_MASK 0x0000000000000f00 + +/* SH_XNNI1_NI_FLOW_VC0_CAP */ +/* Description: vc0 counter captured value */ +#define SH_XNNI1_NI_FLOW_VC0_CAP_SHFT 12 +#define SH_XNNI1_NI_FLOW_VC0_CAP_MASK 0x000000000000f000 + +/* SH_XNNI1_NI_FLOW_VC1_LIMIT */ +/* Description: vc1 limit reg, zero disables functionality */ +#define SH_XNNI1_NI_FLOW_VC1_LIMIT_SHFT 16 +#define SH_XNNI1_NI_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 + +/* SH_XNNI1_NI_FLOW_VC1_DYN */ +/* Description: vc1 counter dynamic value */ +#define SH_XNNI1_NI_FLOW_VC1_DYN_SHFT 24 +#define SH_XNNI1_NI_FLOW_VC1_DYN_MASK 0x000000000f000000 + +/* SH_XNNI1_NI_FLOW_VC1_CAP */ +/* Description: vc1 counter captured value */ +#define SH_XNNI1_NI_FLOW_VC1_CAP_SHFT 28 +#define SH_XNNI1_NI_FLOW_VC1_CAP_MASK 0x00000000f0000000 + +/* SH_XNNI1_NI_FLOW_VC2_LIMIT */ +/* Description: vc2 limit reg, zero disables functionality */ +#define SH_XNNI1_NI_FLOW_VC2_LIMIT_SHFT 32 +#define SH_XNNI1_NI_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 + +/* SH_XNNI1_NI_FLOW_VC2_DYN */ +/* Description: vc2 counter dynamic value */ +#define SH_XNNI1_NI_FLOW_VC2_DYN_SHFT 40 +#define SH_XNNI1_NI_FLOW_VC2_DYN_MASK 0x00000f0000000000 + +/* SH_XNNI1_NI_FLOW_VC2_CAP */ +/* Description: vc2 counter captured value */ +#define SH_XNNI1_NI_FLOW_VC2_CAP_SHFT 44 +#define SH_XNNI1_NI_FLOW_VC2_CAP_MASK 0x0000f00000000000 + +/* SH_XNNI1_NI_FLOW_VC3_LIMIT */ +/* Description: vc3 limit reg, zero disables functionality */ +#define SH_XNNI1_NI_FLOW_VC3_LIMIT_SHFT 48 +#define SH_XNNI1_NI_FLOW_VC3_LIMIT_MASK 0x000f000000000000 + +/* SH_XNNI1_NI_FLOW_VC3_DYN */ +/* Description: vc3 counter dynamic value */ +#define SH_XNNI1_NI_FLOW_VC3_DYN_SHFT 56 +#define SH_XNNI1_NI_FLOW_VC3_DYN_MASK 0x0f00000000000000 + +/* SH_XNNI1_NI_FLOW_VC3_CAP */ +/* Description: vc3 counter captured value */ +#define SH_XNNI1_NI_FLOW_VC3_CAP_SHFT 60 +#define SH_XNNI1_NI_FLOW_VC3_CAP_MASK 0xf000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_DEAD_FLOW" */ +/* ==================================================================== */ + +#define SH_XNNI1_DEAD_FLOW 0x00000001500305f0 +#define SH_XNNI1_DEAD_FLOW_MASK 0xff0fff0fff0fff0f +#define SH_XNNI1_DEAD_FLOW_INIT 0x0000000000000000 + +/* SH_XNNI1_DEAD_FLOW_VC0_LIMIT */ +/* Description: vc0 limit reg, zero disables functionality */ +#define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_SHFT 0 +#define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_MASK 0x000000000000000f + +/* SH_XNNI1_DEAD_FLOW_VC0_DYN */ +/* Description: vc0 counter dynamic value */ +#define SH_XNNI1_DEAD_FLOW_VC0_DYN_SHFT 8 +#define SH_XNNI1_DEAD_FLOW_VC0_DYN_MASK 0x0000000000000f00 + +/* SH_XNNI1_DEAD_FLOW_VC0_CAP */ +/* Description: vc0 counter captured value */ +#define SH_XNNI1_DEAD_FLOW_VC0_CAP_SHFT 12 +#define SH_XNNI1_DEAD_FLOW_VC0_CAP_MASK 0x000000000000f000 + +/* SH_XNNI1_DEAD_FLOW_VC1_LIMIT */ +/* Description: vc1 limit reg, zero disables functionality */ +#define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_SHFT 16 +#define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_MASK 0x00000000000f0000 + +/* SH_XNNI1_DEAD_FLOW_VC1_DYN */ +/* Description: vc1 counter dynamic value */ +#define SH_XNNI1_DEAD_FLOW_VC1_DYN_SHFT 24 +#define SH_XNNI1_DEAD_FLOW_VC1_DYN_MASK 0x000000000f000000 + +/* SH_XNNI1_DEAD_FLOW_VC1_CAP */ +/* Description: vc1 counter captured value */ +#define SH_XNNI1_DEAD_FLOW_VC1_CAP_SHFT 28 +#define SH_XNNI1_DEAD_FLOW_VC1_CAP_MASK 0x00000000f0000000 + +/* SH_XNNI1_DEAD_FLOW_VC2_LIMIT */ +/* Description: vc2 limit reg, zero disables functionality */ +#define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_SHFT 32 +#define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_MASK 0x0000000f00000000 + +/* SH_XNNI1_DEAD_FLOW_VC2_DYN */ +/* Description: vc2 counter dynamic value */ +#define SH_XNNI1_DEAD_FLOW_VC2_DYN_SHFT 40 +#define SH_XNNI1_DEAD_FLOW_VC2_DYN_MASK 0x00000f0000000000 + +/* SH_XNNI1_DEAD_FLOW_VC2_CAP */ +/* Description: vc2 counter captured value */ +#define SH_XNNI1_DEAD_FLOW_VC2_CAP_SHFT 44 +#define SH_XNNI1_DEAD_FLOW_VC2_CAP_MASK 0x0000f00000000000 + +/* SH_XNNI1_DEAD_FLOW_VC3_LIMIT */ +/* Description: vc3 limit reg, zero disables functionality */ +#define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_SHFT 48 +#define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_MASK 0x000f000000000000 + +/* SH_XNNI1_DEAD_FLOW_VC3_DYN */ +/* Description: vc3 counter dynamic value */ +#define SH_XNNI1_DEAD_FLOW_VC3_DYN_SHFT 56 +#define SH_XNNI1_DEAD_FLOW_VC3_DYN_MASK 0x0f00000000000000 + +/* SH_XNNI1_DEAD_FLOW_VC3_CAP */ +/* Description: vc3 counter captured value */ +#define SH_XNNI1_DEAD_FLOW_VC3_CAP_SHFT 60 +#define SH_XNNI1_DEAD_FLOW_VC3_CAP_MASK 0xf000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNNI1_INJECT_AGE" */ +/* ==================================================================== */ + +#define SH_XNNI1_INJECT_AGE 0x0000000150030600 +#define SH_XNNI1_INJECT_AGE_MASK 0x000000000000ffff +#define SH_XNNI1_INJECT_AGE_INIT 0x0000000000000000 + +/* SH_XNNI1_INJECT_AGE_REQUEST_INJECT */ +/* Description: Value of AGE field for outgoing requests */ +#define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_SHFT 0 +#define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_MASK 0x00000000000000ff + +/* SH_XNNI1_INJECT_AGE_REPLY_INJECT */ +/* Description: Value of AGE field for outgoing replies */ +#define SH_XNNI1_INJECT_AGE_REPLY_INJECT_SHFT 8 +#define SH_XNNI1_INJECT_AGE_REPLY_INJECT_MASK 0x000000000000ff00 + +/* ==================================================================== */ +/* Register "SH_XN_DEBUG_SEL" */ +/* XN Debug Port Select */ +/* ==================================================================== */ + +#define SH_XN_DEBUG_SEL 0x0000000150031000 +#define SH_XN_DEBUG_SEL_MASK 0xf777777777777777 +#define SH_XN_DEBUG_SEL_INIT 0x0000000000000000 + +/* SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL */ +/* Description: Nibble 0 RLM select */ +#define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_SHFT 0 +#define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_MASK 0x0000000000000007 + +/* SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL */ +/* Description: Nibble 1 RLM select */ +#define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_SHFT 8 +#define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_MASK 0x0000000000000700 + +/* SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL */ +/* Description: Nibble 2 RLM select */ +#define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_SHFT 16 +#define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_MASK 0x0000000000070000 + +/* SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL */ +/* Description: Nibble 3 RLM select */ +#define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_SHFT 24 +#define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_MASK 0x0000000007000000 + +/* SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL */ +/* Description: Nibble 4 RLM select */ +#define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_SHFT 32 +#define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_MASK 0x0000000700000000 + +/* SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL */ +/* Description: Nibble 5 RLM select */ +#define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_SHFT 40 +#define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_MASK 0x0000070000000000 + +/* SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL */ +/* Description: Nibble 6 RLM select */ +#define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_SHFT 48 +#define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_MASK 0x0007000000000000 + +/* SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL */ +/* Description: Nibble 7 RLM select */ +#define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_SHFT 56 +#define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_MASK 0x0700000000000000 + +/* SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* SH_XN_DEBUG_SEL_TRIGGER_ENABLE */ +/* Description: Enable trigger on bit 32 of Analyzer data */ +#define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_SHFT 63 +#define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_DEBUG_TRIG_SEL" */ +/* XN Debug trigger Select */ +/* ==================================================================== */ + +#define SH_XN_DEBUG_TRIG_SEL 0x0000000150031020 +#define SH_XN_DEBUG_TRIG_SEL_MASK 0x7777777777777777 +#define SH_XN_DEBUG_TRIG_SEL_INIT 0x0000000000000000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL */ +/* Description: Nibble 0 RLM select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_SHFT 0 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_MASK 0x0000000000000007 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL */ +/* Description: Nibble 1 RLM select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_SHFT 8 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_MASK 0x0000000000000700 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL */ +/* Description: Nibble 2 RLM select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_SHFT 16 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_MASK 0x0000000000070000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL */ +/* Description: Nibble 3 RLM select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_SHFT 24 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_MASK 0x0000000007000000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL */ +/* Description: Nibble 4 RLM select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_SHFT 32 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_MASK 0x0000000700000000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL */ +/* Description: Nibble 5 RLM select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_SHFT 40 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_MASK 0x0000070000000000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL */ +/* Description: Nibble 6 RLM select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_SHFT 48 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_MASK 0x0007000000000000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL */ +/* Description: Nibble 7 RLM select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_SHFT 56 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_MASK 0x0700000000000000 + +/* SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60 +#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_TRIGGER_COMPARE" */ +/* XN Debug Compare */ +/* ==================================================================== */ + +#define SH_XN_TRIGGER_COMPARE 0x0000000150031040 +#define SH_XN_TRIGGER_COMPARE_MASK 0x00000000ffffffff +#define SH_XN_TRIGGER_COMPARE_INIT 0x0000000000000000 + +/* SH_XN_TRIGGER_COMPARE_MASK */ +/* Description: Mask to select Debug bits for trigger generation */ +#define SH_XN_TRIGGER_COMPARE_MASK_SHFT 0 +#define SH_XN_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_XN_TRIGGER_DATA" */ +/* XN Debug Compare Data */ +/* ==================================================================== */ + +#define SH_XN_TRIGGER_DATA 0x0000000150031050 +#define SH_XN_TRIGGER_DATA_MASK 0x00000000ffffffff +#define SH_XN_TRIGGER_DATA_INIT 0x00000000ffffffff + +/* SH_XN_TRIGGER_DATA_COMPARE_PATTERN */ +/* Description: debug bit pattern for trigger generation */ +#define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_SHFT 0 +#define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_DEBUG_SEL" */ +/* XN IILB Debug Port Select */ +/* ==================================================================== */ + +#define SH_XN_IILB_DEBUG_SEL 0x0000000150031060 +#define SH_XN_IILB_DEBUG_SEL_MASK 0x7777777777777777 +#define SH_XN_IILB_DEBUG_SEL_INIT 0x0000000000000000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL */ +/* Description: Nibble 0 input select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL */ +/* Description: Nibble 1 input select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL */ +/* Description: Nibble 2 input select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL */ +/* Description: Nibble 3 input select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL */ +/* Description: Nibble 4 input select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL */ +/* Description: Nibble 5 input select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL */ +/* Description: Nibble 6 input select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL */ +/* Description: Nibble 7 input select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 + +/* SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_PI_DEBUG_SEL" */ +/* XN PI Debug Port Select */ +/* ==================================================================== */ + +#define SH_XN_PI_DEBUG_SEL 0x00000001500310a0 +#define SH_XN_PI_DEBUG_SEL_MASK 0x7777777777777777 +#define SH_XN_PI_DEBUG_SEL_INIT 0x0000000000000000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL */ +/* Description: Nibble 0 input select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 +#define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL */ +/* Description: Nibble 1 input select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 +#define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL */ +/* Description: Nibble 2 input select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 +#define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL */ +/* Description: Nibble 3 input select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 +#define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL */ +/* Description: Nibble 4 input select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 +#define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL */ +/* Description: Nibble 5 input select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 +#define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL */ +/* Description: Nibble 6 input select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 +#define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL */ +/* Description: Nibble 7 input select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 +#define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 + +/* SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_MD_DEBUG_SEL" */ +/* XN MD Debug Port Select */ +/* ==================================================================== */ + +#define SH_XN_MD_DEBUG_SEL 0x0000000150031080 +#define SH_XN_MD_DEBUG_SEL_MASK 0x7777777777777777 +#define SH_XN_MD_DEBUG_SEL_INIT 0x0000000000000000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL */ +/* Description: Nibble 0 input select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 +#define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL */ +/* Description: Nibble 1 input select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 +#define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL */ +/* Description: Nibble 2 input select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 +#define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL */ +/* Description: Nibble 3 input select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 +#define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL */ +/* Description: Nibble 4 input select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 +#define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL */ +/* Description: Nibble 5 input select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 +#define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL */ +/* Description: Nibble 6 input select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 +#define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL */ +/* Description: Nibble 7 input select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 +#define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 + +/* SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_NI0_DEBUG_SEL" */ +/* XN NI0 Debug Port Select */ +/* ==================================================================== */ + +#define SH_XN_NI0_DEBUG_SEL 0x00000001500310c0 +#define SH_XN_NI0_DEBUG_SEL_MASK 0x7777777777777777 +#define SH_XN_NI0_DEBUG_SEL_INIT 0x0000000000000000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL */ +/* Description: Nibble 0 input select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL */ +/* Description: Nibble 1 input select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL */ +/* Description: Nibble 2 input select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL */ +/* Description: Nibble 3 input select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL */ +/* Description: Nibble 4 input select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL */ +/* Description: Nibble 5 input select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL */ +/* Description: Nibble 6 input select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL */ +/* Description: Nibble 7 input select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 + +/* SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_NI1_DEBUG_SEL" */ +/* XN NI1 Debug Port Select */ +/* ==================================================================== */ + +#define SH_XN_NI1_DEBUG_SEL 0x00000001500310e0 +#define SH_XN_NI1_DEBUG_SEL_MASK 0x7777777777777777 +#define SH_XN_NI1_DEBUG_SEL_INIT 0x0000000000000000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL */ +/* Description: Nibble 0 input select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL */ +/* Description: Nibble 1 input select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL */ +/* Description: Nibble 2 input select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL */ +/* Description: Nibble 3 input select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL */ +/* Description: Nibble 4 input select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL */ +/* Description: Nibble 5 input select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL */ +/* Description: Nibble 6 input select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL */ +/* Description: Nibble 7 input select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 + +/* SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_IILB_LB_CMP_EXP_DATA0" */ +/* IILB compare LB input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_LB_CMP_EXP_DATA0 0x0000000150031100 +#define SH_XN_IILB_LB_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_IILB_LB_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_IILB_LB_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_LB_CMP_EXP_DATA1" */ +/* IILB compare LB input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_LB_CMP_EXP_DATA1 0x0000000150031110 +#define SH_XN_IILB_LB_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_IILB_LB_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_IILB_LB_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_LB_CMP_ENABLE0" */ +/* IILB compare LB input enable0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_LB_CMP_ENABLE0 0x0000000150031120 +#define SH_XN_IILB_LB_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_IILB_LB_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_IILB_LB_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_LB_CMP_ENABLE1" */ +/* IILB compare LB input enable1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_LB_CMP_ENABLE1 0x0000000150031130 +#define SH_XN_IILB_LB_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_IILB_LB_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_IILB_LB_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_II_CMP_EXP_DATA0" */ +/* IILB compare II input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_II_CMP_EXP_DATA0 0x0000000150031140 +#define SH_XN_IILB_II_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_IILB_II_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_IILB_II_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_II_CMP_EXP_DATA1" */ +/* IILB compare II input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_II_CMP_EXP_DATA1 0x0000000150031150 +#define SH_XN_IILB_II_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_IILB_II_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_IILB_II_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_II_CMP_ENABLE0" */ +/* IILB compare II input enable0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_II_CMP_ENABLE0 0x0000000150031160 +#define SH_XN_IILB_II_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_IILB_II_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_IILB_II_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_II_CMP_ENABLE1" */ +/* IILB compare II input enable1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_II_CMP_ENABLE1 0x0000000150031170 +#define SH_XN_IILB_II_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_IILB_II_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_IILB_II_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_MD_CMP_EXP_DATA0" */ +/* IILB compare MD input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_MD_CMP_EXP_DATA0 0x0000000150031180 +#define SH_XN_IILB_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_IILB_MD_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_IILB_MD_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_MD_CMP_EXP_DATA1" */ +/* IILB compare MD input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_MD_CMP_EXP_DATA1 0x0000000150031190 +#define SH_XN_IILB_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_IILB_MD_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_IILB_MD_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_MD_CMP_ENABLE0" */ +/* IILB compare MD input enable0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_MD_CMP_ENABLE0 0x00000001500311a0 +#define SH_XN_IILB_MD_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_IILB_MD_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_IILB_MD_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_MD_CMP_ENABLE1" */ +/* IILB compare MD input enable1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_MD_CMP_ENABLE1 0x00000001500311b0 +#define SH_XN_IILB_MD_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_IILB_MD_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_IILB_MD_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_PI_CMP_EXP_DATA0" */ +/* IILB compare PI input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_PI_CMP_EXP_DATA0 0x00000001500311c0 +#define SH_XN_IILB_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_IILB_PI_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_IILB_PI_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_PI_CMP_EXP_DATA1" */ +/* IILB compare PI input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_PI_CMP_EXP_DATA1 0x00000001500311d0 +#define SH_XN_IILB_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_IILB_PI_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_IILB_PI_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_PI_CMP_ENABLE0" */ +/* IILB compare PI input enable0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_PI_CMP_ENABLE0 0x00000001500311e0 +#define SH_XN_IILB_PI_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_IILB_PI_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_IILB_PI_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_PI_CMP_ENABLE1" */ +/* IILB compare PI input enable1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_PI_CMP_ENABLE1 0x00000001500311f0 +#define SH_XN_IILB_PI_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_IILB_PI_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_IILB_PI_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI0_CMP_EXP_DATA0" */ +/* IILB compare NI0 input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_NI0_CMP_EXP_DATA0 0x0000000150031200 +#define SH_XN_IILB_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_IILB_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI0_CMP_EXP_DATA1" */ +/* IILB compare NI0 input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_NI0_CMP_EXP_DATA1 0x0000000150031210 +#define SH_XN_IILB_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_IILB_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI0_CMP_ENABLE0" */ +/* IILB compare NI0 input enable0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_NI0_CMP_ENABLE0 0x0000000150031220 +#define SH_XN_IILB_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_IILB_NI0_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI0_CMP_ENABLE1" */ +/* IILB compare NI0 input enable1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_NI0_CMP_ENABLE1 0x0000000150031230 +#define SH_XN_IILB_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_IILB_NI0_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI1_CMP_EXP_DATA0" */ +/* IILB compare NI1 input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_NI1_CMP_EXP_DATA0 0x0000000150031240 +#define SH_XN_IILB_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_IILB_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI1_CMP_EXP_DATA1" */ +/* IILB compare NI1 input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_NI1_CMP_EXP_DATA1 0x0000000150031250 +#define SH_XN_IILB_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_IILB_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI1_CMP_ENABLE0" */ +/* IILB compare NI1 input enable0 */ +/* ==================================================================== */ + +#define SH_XN_IILB_NI1_CMP_ENABLE0 0x0000000150031260 +#define SH_XN_IILB_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_IILB_NI1_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI1_CMP_ENABLE1" */ +/* IILB compare NI1 input enable1 */ +/* ==================================================================== */ + +#define SH_XN_IILB_NI1_CMP_ENABLE1 0x0000000150031270 +#define SH_XN_IILB_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_IILB_NI1_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_IILB_CMP_EXP_DATA0" */ +/* MD compare IILB input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_MD_IILB_CMP_EXP_DATA0 0x0000000150031500 +#define SH_XN_MD_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_MD_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_MD_IILB_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_IILB_CMP_EXP_DATA1" */ +/* MD compare IILB input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_MD_IILB_CMP_EXP_DATA1 0x0000000150031510 +#define SH_XN_MD_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_MD_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_MD_IILB_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_IILB_CMP_ENABLE0" */ +/* MD compare IILB input enable0 */ +/* ==================================================================== */ + +#define SH_XN_MD_IILB_CMP_ENABLE0 0x0000000150031520 +#define SH_XN_MD_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_MD_IILB_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_MD_IILB_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_IILB_CMP_ENABLE1" */ +/* MD compare IILB input enable1 */ +/* ==================================================================== */ + +#define SH_XN_MD_IILB_CMP_ENABLE1 0x0000000150031530 +#define SH_XN_MD_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_MD_IILB_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_MD_IILB_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI0_CMP_EXP_DATA0" */ +/* MD compare NI0 input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_MD_NI0_CMP_EXP_DATA0 0x0000000150031540 +#define SH_XN_MD_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_MD_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_MD_NI0_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI0_CMP_EXP_DATA1" */ +/* MD compare NI0 input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_MD_NI0_CMP_EXP_DATA1 0x0000000150031550 +#define SH_XN_MD_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_MD_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_MD_NI0_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI0_CMP_ENABLE0" */ +/* MD compare NI0 input enable0 */ +/* ==================================================================== */ + +#define SH_XN_MD_NI0_CMP_ENABLE0 0x0000000150031560 +#define SH_XN_MD_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_MD_NI0_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_MD_NI0_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI0_CMP_ENABLE1" */ +/* MD compare NI0 input enable1 */ +/* ==================================================================== */ + +#define SH_XN_MD_NI0_CMP_ENABLE1 0x0000000150031570 +#define SH_XN_MD_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_MD_NI0_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_MD_NI0_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI1_CMP_EXP_DATA0" */ +/* MD compare NI1 input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_MD_NI1_CMP_EXP_DATA0 0x0000000150031580 +#define SH_XN_MD_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_MD_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_MD_NI1_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI1_CMP_EXP_DATA1" */ +/* MD compare NI1 input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_MD_NI1_CMP_EXP_DATA1 0x0000000150031590 +#define SH_XN_MD_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_MD_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_MD_NI1_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI1_CMP_ENABLE0" */ +/* MD compare NI1 input enable0 */ +/* ==================================================================== */ + +#define SH_XN_MD_NI1_CMP_ENABLE0 0x00000001500315a0 +#define SH_XN_MD_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_MD_NI1_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_MD_NI1_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI1_CMP_ENABLE1" */ +/* MD compare NI1 input enable1 */ +/* ==================================================================== */ + +#define SH_XN_MD_NI1_CMP_ENABLE1 0x00000001500315b0 +#define SH_XN_MD_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_MD_NI1_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_MD_NI1_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_EXP_HDR0" */ +/* MD compare SIC input expected header0 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_EXP_HDR0 0x00000001500315c0 +#define SH_XN_MD_SIC_CMP_EXP_HDR0_MASK 0xffffffffffffffff +#define SH_XN_MD_SIC_CMP_EXP_HDR0_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_EXP_HDR0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_SHFT 0 +#define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_EXP_HDR1" */ +/* MD compare SIC input expected header1 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_EXP_HDR1 0x00000001500315d0 +#define SH_XN_MD_SIC_CMP_EXP_HDR1_MASK 0x000003ffffffffff +#define SH_XN_MD_SIC_CMP_EXP_HDR1_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_EXP_HDR1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_SHFT 0 +#define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_MASK 0x000003ffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0" */ +/* MD compare SIC header enable0 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_HDR_ENABLE0 0x00000001500315e0 +#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1" */ +/* MD compare SIC header enable1 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_HDR_ENABLE1 0x00000001500315f0 +#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_MASK 0x000003ffffffffff +#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA0" */ +/* MD compare SIC data0 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_DATA0 0x0000000150031600 +#define SH_XN_MD_SIC_CMP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_MD_SIC_CMP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_DATA0_DATA0 */ +/* Description: Data0 */ +#define SH_XN_MD_SIC_CMP_DATA0_DATA0_SHFT 0 +#define SH_XN_MD_SIC_CMP_DATA0_DATA0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA1" */ +/* MD compare SIC data1 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_DATA1 0x0000000150031610 +#define SH_XN_MD_SIC_CMP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_MD_SIC_CMP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_DATA1_DATA1 */ +/* Description: Data1 */ +#define SH_XN_MD_SIC_CMP_DATA1_DATA1_SHFT 0 +#define SH_XN_MD_SIC_CMP_DATA1_DATA1_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA2" */ +/* MD compare SIC data2 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_DATA2 0x0000000150031620 +#define SH_XN_MD_SIC_CMP_DATA2_MASK 0xffffffffffffffff +#define SH_XN_MD_SIC_CMP_DATA2_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_DATA2_DATA2 */ +/* Description: Data2 */ +#define SH_XN_MD_SIC_CMP_DATA2_DATA2_SHFT 0 +#define SH_XN_MD_SIC_CMP_DATA2_DATA2_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA3" */ +/* MD compare SIC data3 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_DATA3 0x0000000150031630 +#define SH_XN_MD_SIC_CMP_DATA3_MASK 0xffffffffffffffff +#define SH_XN_MD_SIC_CMP_DATA3_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_DATA3_DATA3 */ +/* Description: Data3 */ +#define SH_XN_MD_SIC_CMP_DATA3_DATA3_SHFT 0 +#define SH_XN_MD_SIC_CMP_DATA3_DATA3_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0" */ +/* MD enable compare SIC data0 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_DATA_ENABLE0 0x0000000150031640 +#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0 */ +/* Description: Data0 */ +#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0 +#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1" */ +/* MD enable compare SIC data1 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_DATA_ENABLE1 0x0000000150031650 +#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1 */ +/* Description: Data1 */ +#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0 +#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2" */ +/* MD enable compare SIC data2 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_DATA_ENABLE2 0x0000000150031660 +#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_MASK 0xffffffffffffffff +#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2 */ +/* Description: Data2 */ +#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0 +#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3" */ +/* MD enable compare SIC data3 */ +/* ==================================================================== */ + +#define SH_XN_MD_SIC_CMP_DATA_ENABLE3 0x0000000150031670 +#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_MASK 0xffffffffffffffff +#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_INIT 0x0000000000000000 + +/* SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3 */ +/* Description: Data3 */ +#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0 +#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_IILB_CMP_EXP_DATA0" */ +/* PI compare IILB input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_PI_IILB_CMP_EXP_DATA0 0x0000000150031300 +#define SH_XN_PI_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_PI_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_PI_IILB_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_IILB_CMP_EXP_DATA1" */ +/* PI compare IILB input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_PI_IILB_CMP_EXP_DATA1 0x0000000150031310 +#define SH_XN_PI_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_PI_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_PI_IILB_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_IILB_CMP_ENABLE0" */ +/* PI compare IILB input enable0 */ +/* ==================================================================== */ + +#define SH_XN_PI_IILB_CMP_ENABLE0 0x0000000150031320 +#define SH_XN_PI_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_PI_IILB_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_PI_IILB_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_IILB_CMP_ENABLE1" */ +/* PI compare IILB input enable1 */ +/* ==================================================================== */ + +#define SH_XN_PI_IILB_CMP_ENABLE1 0x0000000150031330 +#define SH_XN_PI_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_PI_IILB_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_PI_IILB_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI0_CMP_EXP_DATA0" */ +/* PI compare NI0 input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_PI_NI0_CMP_EXP_DATA0 0x0000000150031340 +#define SH_XN_PI_NI0_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_PI_NI0_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_PI_NI0_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI0_CMP_EXP_DATA1" */ +/* PI compare NI0 input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_PI_NI0_CMP_EXP_DATA1 0x0000000150031350 +#define SH_XN_PI_NI0_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_PI_NI0_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_PI_NI0_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI0_CMP_ENABLE0" */ +/* PI compare NI0 input enable0 */ +/* ==================================================================== */ + +#define SH_XN_PI_NI0_CMP_ENABLE0 0x0000000150031360 +#define SH_XN_PI_NI0_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_PI_NI0_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_PI_NI0_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI0_CMP_ENABLE1" */ +/* PI compare NI0 input enable1 */ +/* ==================================================================== */ + +#define SH_XN_PI_NI0_CMP_ENABLE1 0x0000000150031370 +#define SH_XN_PI_NI0_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_PI_NI0_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_PI_NI0_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI1_CMP_EXP_DATA0" */ +/* PI compare NI1 input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_PI_NI1_CMP_EXP_DATA0 0x0000000150031380 +#define SH_XN_PI_NI1_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_PI_NI1_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_PI_NI1_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI1_CMP_EXP_DATA1" */ +/* PI compare NI1 input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_PI_NI1_CMP_EXP_DATA1 0x0000000150031390 +#define SH_XN_PI_NI1_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_PI_NI1_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_PI_NI1_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI1_CMP_ENABLE0" */ +/* PI compare NI1 input enable0 */ +/* ==================================================================== */ + +#define SH_XN_PI_NI1_CMP_ENABLE0 0x00000001500313a0 +#define SH_XN_PI_NI1_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_PI_NI1_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_PI_NI1_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI1_CMP_ENABLE1" */ +/* PI compare NI1 input enable1 */ +/* ==================================================================== */ + +#define SH_XN_PI_NI1_CMP_ENABLE1 0x00000001500313b0 +#define SH_XN_PI_NI1_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_PI_NI1_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_PI_NI1_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_EXP_HDR0" */ +/* PI compare SIC input expected header0 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_EXP_HDR0 0x00000001500313c0 +#define SH_XN_PI_SIC_CMP_EXP_HDR0_MASK 0xffffffffffffffff +#define SH_XN_PI_SIC_CMP_EXP_HDR0_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_EXP_HDR0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_SHFT 0 +#define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_EXP_HDR1" */ +/* PI compare SIC input expected header1 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_EXP_HDR1 0x00000001500313d0 +#define SH_XN_PI_SIC_CMP_EXP_HDR1_MASK 0x000003ffffffffff +#define SH_XN_PI_SIC_CMP_EXP_HDR1_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_EXP_HDR1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_SHFT 0 +#define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_MASK 0x000003ffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0" */ +/* PI compare SIC header enable0 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_HDR_ENABLE0 0x00000001500313e0 +#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1" */ +/* PI compare SIC header enable1 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_HDR_ENABLE1 0x00000001500313f0 +#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_MASK 0x000003ffffffffff +#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA0" */ +/* PI compare SIC data0 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_DATA0 0x0000000150031400 +#define SH_XN_PI_SIC_CMP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_PI_SIC_CMP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_DATA0_DATA0 */ +/* Description: Data0 */ +#define SH_XN_PI_SIC_CMP_DATA0_DATA0_SHFT 0 +#define SH_XN_PI_SIC_CMP_DATA0_DATA0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA1" */ +/* PI compare SIC data1 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_DATA1 0x0000000150031410 +#define SH_XN_PI_SIC_CMP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_PI_SIC_CMP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_DATA1_DATA1 */ +/* Description: Data1 */ +#define SH_XN_PI_SIC_CMP_DATA1_DATA1_SHFT 0 +#define SH_XN_PI_SIC_CMP_DATA1_DATA1_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA2" */ +/* PI compare SIC data2 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_DATA2 0x0000000150031420 +#define SH_XN_PI_SIC_CMP_DATA2_MASK 0xffffffffffffffff +#define SH_XN_PI_SIC_CMP_DATA2_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_DATA2_DATA2 */ +/* Description: Data2 */ +#define SH_XN_PI_SIC_CMP_DATA2_DATA2_SHFT 0 +#define SH_XN_PI_SIC_CMP_DATA2_DATA2_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA3" */ +/* PI compare SIC data3 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_DATA3 0x0000000150031430 +#define SH_XN_PI_SIC_CMP_DATA3_MASK 0xffffffffffffffff +#define SH_XN_PI_SIC_CMP_DATA3_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_DATA3_DATA3 */ +/* Description: Data3 */ +#define SH_XN_PI_SIC_CMP_DATA3_DATA3_SHFT 0 +#define SH_XN_PI_SIC_CMP_DATA3_DATA3_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0" */ +/* PI enable compare SIC data0 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_DATA_ENABLE0 0x0000000150031440 +#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0 */ +/* Description: Data0 */ +#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0 +#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1" */ +/* PI enable compare SIC data1 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_DATA_ENABLE1 0x0000000150031450 +#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1 */ +/* Description: Data1 */ +#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0 +#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2" */ +/* PI enable compare SIC data2 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_DATA_ENABLE2 0x0000000150031460 +#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_MASK 0xffffffffffffffff +#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2 */ +/* Description: Data2 */ +#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0 +#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3" */ +/* PI enable compare SIC data3 */ +/* ==================================================================== */ + +#define SH_XN_PI_SIC_CMP_DATA_ENABLE3 0x0000000150031470 +#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_MASK 0xffffffffffffffff +#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_INIT 0x0000000000000000 + +/* SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3 */ +/* Description: Data3 */ +#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0 +#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_IILB_CMP_EXP_DATA0" */ +/* NI0 compare IILB input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_NI0_IILB_CMP_EXP_DATA0 0x0000000150031700 +#define SH_XN_NI0_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_NI0_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_IILB_CMP_EXP_DATA1" */ +/* NI0 compare IILB input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_NI0_IILB_CMP_EXP_DATA1 0x0000000150031710 +#define SH_XN_NI0_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_NI0_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_IILB_CMP_ENABLE0" */ +/* NI0 compare IILB input enable0 */ +/* ==================================================================== */ + +#define SH_XN_NI0_IILB_CMP_ENABLE0 0x0000000150031720 +#define SH_XN_NI0_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_NI0_IILB_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_IILB_CMP_ENABLE1" */ +/* NI0 compare IILB input enable1 */ +/* ==================================================================== */ + +#define SH_XN_NI0_IILB_CMP_ENABLE1 0x0000000150031730 +#define SH_XN_NI0_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_NI0_IILB_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_PI_CMP_EXP_DATA0" */ +/* NI0 compare PI input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_NI0_PI_CMP_EXP_DATA0 0x0000000150031740 +#define SH_XN_NI0_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_NI0_PI_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_NI0_PI_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_PI_CMP_EXP_DATA1" */ +/* NI0 compare PI input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_NI0_PI_CMP_EXP_DATA1 0x0000000150031750 +#define SH_XN_NI0_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_NI0_PI_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_NI0_PI_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_PI_CMP_ENABLE0" */ +/* NI0 compare PI input enable0 */ +/* ==================================================================== */ + +#define SH_XN_NI0_PI_CMP_ENABLE0 0x0000000150031760 +#define SH_XN_NI0_PI_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_NI0_PI_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_NI0_PI_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_PI_CMP_ENABLE1" */ +/* NI0 compare PI input enable1 */ +/* ==================================================================== */ + +#define SH_XN_NI0_PI_CMP_ENABLE1 0x0000000150031770 +#define SH_XN_NI0_PI_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_NI0_PI_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_NI0_PI_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_MD_CMP_EXP_DATA0" */ +/* NI0 compare MD input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_NI0_MD_CMP_EXP_DATA0 0x0000000150031780 +#define SH_XN_NI0_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_NI0_MD_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_NI0_MD_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_MD_CMP_EXP_DATA1" */ +/* NI0 compare MD input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_NI0_MD_CMP_EXP_DATA1 0x0000000150031790 +#define SH_XN_NI0_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_NI0_MD_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_NI0_MD_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_MD_CMP_ENABLE0" */ +/* NI0 compare MD input enable0 */ +/* ==================================================================== */ + +#define SH_XN_NI0_MD_CMP_ENABLE0 0x00000001500317a0 +#define SH_XN_NI0_MD_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_NI0_MD_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_NI0_MD_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_MD_CMP_ENABLE1" */ +/* NI0 compare MD input enable1 */ +/* ==================================================================== */ + +#define SH_XN_NI0_MD_CMP_ENABLE1 0x00000001500317b0 +#define SH_XN_NI0_MD_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_NI0_MD_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_NI0_MD_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_NI_CMP_EXP_DATA0" */ +/* NI0 compare NI input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_NI0_NI_CMP_EXP_DATA0 0x00000001500317c0 +#define SH_XN_NI0_NI_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_NI0_NI_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_NI0_NI_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_NI_CMP_EXP_DATA1" */ +/* NI0 compare NI input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_NI0_NI_CMP_EXP_DATA1 0x00000001500317d0 +#define SH_XN_NI0_NI_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_NI0_NI_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_NI0_NI_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_NI_CMP_ENABLE0" */ +/* NI0 compare NI input enable0 */ +/* ==================================================================== */ + +#define SH_XN_NI0_NI_CMP_ENABLE0 0x00000001500317e0 +#define SH_XN_NI0_NI_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_NI0_NI_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_NI0_NI_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_NI_CMP_ENABLE1" */ +/* NI0 compare NI input enable1 */ +/* ==================================================================== */ + +#define SH_XN_NI0_NI_CMP_ENABLE1 0x00000001500317f0 +#define SH_XN_NI0_NI_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_NI0_NI_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_NI0_NI_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_LLP_CMP_EXP_DATA0" */ +/* NI0 compare LLP input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_NI0_LLP_CMP_EXP_DATA0 0x0000000150031800 +#define SH_XN_NI0_LLP_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_NI0_LLP_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_LLP_CMP_EXP_DATA1" */ +/* NI0 compare LLP input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_NI0_LLP_CMP_EXP_DATA1 0x0000000150031810 +#define SH_XN_NI0_LLP_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_NI0_LLP_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_LLP_CMP_ENABLE0" */ +/* NI0 compare LLP input enable0 */ +/* ==================================================================== */ + +#define SH_XN_NI0_LLP_CMP_ENABLE0 0x0000000150031820 +#define SH_XN_NI0_LLP_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_NI0_LLP_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI0_LLP_CMP_ENABLE1" */ +/* NI0 compare LLP input enable1 */ +/* ==================================================================== */ + +#define SH_XN_NI0_LLP_CMP_ENABLE1 0x0000000150031830 +#define SH_XN_NI0_LLP_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_NI0_LLP_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_IILB_CMP_EXP_DATA0" */ +/* NI1 compare IILB input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_NI1_IILB_CMP_EXP_DATA0 0x0000000150031900 +#define SH_XN_NI1_IILB_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_NI1_IILB_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_IILB_CMP_EXP_DATA1" */ +/* NI1 compare IILB input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_NI1_IILB_CMP_EXP_DATA1 0x0000000150031910 +#define SH_XN_NI1_IILB_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_NI1_IILB_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_IILB_CMP_ENABLE0" */ +/* NI1 compare IILB input enable0 */ +/* ==================================================================== */ + +#define SH_XN_NI1_IILB_CMP_ENABLE0 0x0000000150031920 +#define SH_XN_NI1_IILB_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_NI1_IILB_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_IILB_CMP_ENABLE1" */ +/* NI1 compare IILB input enable1 */ +/* ==================================================================== */ + +#define SH_XN_NI1_IILB_CMP_ENABLE1 0x0000000150031930 +#define SH_XN_NI1_IILB_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_NI1_IILB_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_PI_CMP_EXP_DATA0" */ +/* NI1 compare PI input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_NI1_PI_CMP_EXP_DATA0 0x0000000150031940 +#define SH_XN_NI1_PI_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_NI1_PI_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_NI1_PI_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_PI_CMP_EXP_DATA1" */ +/* NI1 compare PI input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_NI1_PI_CMP_EXP_DATA1 0x0000000150031950 +#define SH_XN_NI1_PI_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_NI1_PI_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_NI1_PI_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_PI_CMP_ENABLE0" */ +/* NI1 compare PI input enable0 */ +/* ==================================================================== */ + +#define SH_XN_NI1_PI_CMP_ENABLE0 0x0000000150031960 +#define SH_XN_NI1_PI_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_NI1_PI_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_NI1_PI_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_PI_CMP_ENABLE1" */ +/* NI1 compare PI input enable1 */ +/* ==================================================================== */ + +#define SH_XN_NI1_PI_CMP_ENABLE1 0x0000000150031970 +#define SH_XN_NI1_PI_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_NI1_PI_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_NI1_PI_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_MD_CMP_EXP_DATA0" */ +/* NI1 compare MD input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_NI1_MD_CMP_EXP_DATA0 0x0000000150031980 +#define SH_XN_NI1_MD_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_NI1_MD_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_NI1_MD_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_MD_CMP_EXP_DATA1" */ +/* NI1 compare MD input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_NI1_MD_CMP_EXP_DATA1 0x0000000150031990 +#define SH_XN_NI1_MD_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_NI1_MD_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_NI1_MD_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_MD_CMP_ENABLE0" */ +/* NI1 compare MD input enable0 */ +/* ==================================================================== */ + +#define SH_XN_NI1_MD_CMP_ENABLE0 0x00000001500319a0 +#define SH_XN_NI1_MD_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_NI1_MD_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_NI1_MD_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_MD_CMP_ENABLE1" */ +/* NI1 compare MD input enable1 */ +/* ==================================================================== */ + +#define SH_XN_NI1_MD_CMP_ENABLE1 0x00000001500319b0 +#define SH_XN_NI1_MD_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_NI1_MD_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_NI1_MD_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_NI_CMP_EXP_DATA0" */ +/* NI1 compare NI input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_NI1_NI_CMP_EXP_DATA0 0x00000001500319c0 +#define SH_XN_NI1_NI_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_NI1_NI_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_NI1_NI_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_NI_CMP_EXP_DATA1" */ +/* NI1 compare NI input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_NI1_NI_CMP_EXP_DATA1 0x00000001500319d0 +#define SH_XN_NI1_NI_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_NI1_NI_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_NI1_NI_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_NI_CMP_ENABLE0" */ +/* NI1 compare NI input enable0 */ +/* ==================================================================== */ + +#define SH_XN_NI1_NI_CMP_ENABLE0 0x00000001500319e0 +#define SH_XN_NI1_NI_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_NI1_NI_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_NI1_NI_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_NI_CMP_ENABLE1" */ +/* NI1 compare NI input enable1 */ +/* ==================================================================== */ + +#define SH_XN_NI1_NI_CMP_ENABLE1 0x00000001500319f0 +#define SH_XN_NI1_NI_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_NI1_NI_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_NI1_NI_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_LLP_CMP_EXP_DATA0" */ +/* NI1 compare LLP input expected data0 */ +/* ==================================================================== */ + +#define SH_XN_NI1_LLP_CMP_EXP_DATA0 0x0000000150031a00 +#define SH_XN_NI1_LLP_CMP_EXP_DATA0_MASK 0xffffffffffffffff +#define SH_XN_NI1_LLP_CMP_EXP_DATA0_INIT 0x0000000000000000 + +/* SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA */ +/* Description: Expected data 0 */ +#define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_SHFT 0 +#define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_LLP_CMP_EXP_DATA1" */ +/* NI1 compare LLP input expected data1 */ +/* ==================================================================== */ + +#define SH_XN_NI1_LLP_CMP_EXP_DATA1 0x0000000150031a10 +#define SH_XN_NI1_LLP_CMP_EXP_DATA1_MASK 0xffffffffffffffff +#define SH_XN_NI1_LLP_CMP_EXP_DATA1_INIT 0x0000000000000000 + +/* SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA */ +/* Description: Expected data 1 */ +#define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_SHFT 0 +#define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_LLP_CMP_ENABLE0" */ +/* NI1 compare LLP input enable0 */ +/* ==================================================================== */ + +#define SH_XN_NI1_LLP_CMP_ENABLE0 0x0000000150031a20 +#define SH_XN_NI1_LLP_CMP_ENABLE0_MASK 0xffffffffffffffff +#define SH_XN_NI1_LLP_CMP_ENABLE0_INIT 0x0000000000000000 + +/* SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE */ +/* Description: Enable0 */ +#define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_SHFT 0 +#define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_NI1_LLP_CMP_ENABLE1" */ +/* NI1 compare LLP input enable1 */ +/* ==================================================================== */ + +#define SH_XN_NI1_LLP_CMP_ENABLE1 0x0000000150031a30 +#define SH_XN_NI1_LLP_CMP_ENABLE1_MASK 0xffffffffffffffff +#define SH_XN_NI1_LLP_CMP_ENABLE1_INIT 0x0000000000000000 + +/* SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE */ +/* Description: Enable1 */ +#define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_SHFT 0 +#define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XNPI_ECC_INJ_REG" */ +/* ==================================================================== */ + +#define SH_XNPI_ECC_INJ_REG 0x0000000150032000 +#define SH_XNPI_ECC_INJ_REG_MASK 0xf0fff0fff0fff0ff +#define SH_XNPI_ECC_INJ_REG_INIT 0x0000000000000000 + +/* SH_XNPI_ECC_INJ_REG_BYTE0 */ +/* Description: Replacement Checkbyte */ +#define SH_XNPI_ECC_INJ_REG_BYTE0_SHFT 0 +#define SH_XNPI_ECC_INJ_REG_BYTE0_MASK 0x00000000000000ff + +/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT0 */ +/* Description: 1 shot mask data */ +#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_SHFT 12 +#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_MASK 0x0000000000001000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CONT0 */ +/* Description: toggle mask data */ +#define SH_XNPI_ECC_INJ_REG_DATA_CONT0_SHFT 13 +#define SH_XNPI_ECC_INJ_REG_DATA_CONT0_MASK 0x0000000000002000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0 */ +/* Description: Replace Checkbyte One Shot */ +#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT 14 +#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_MASK 0x0000000000004000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0 */ +/* Description: Replace Checkbyte Continuous */ +#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_SHFT 15 +#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_MASK 0x0000000000008000 + +/* SH_XNPI_ECC_INJ_REG_BYTE1 */ +/* Description: Replacement Checkbyte */ +#define SH_XNPI_ECC_INJ_REG_BYTE1_SHFT 16 +#define SH_XNPI_ECC_INJ_REG_BYTE1_MASK 0x0000000000ff0000 + +/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT1 */ +/* Description: 1 shot mask data */ +#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_SHFT 28 +#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_MASK 0x0000000010000000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CONT1 */ +/* Description: toggle mask data */ +#define SH_XNPI_ECC_INJ_REG_DATA_CONT1_SHFT 29 +#define SH_XNPI_ECC_INJ_REG_DATA_CONT1_MASK 0x0000000020000000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1 */ +/* Description: Replace Checkbyte One Shot */ +#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT 30 +#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_MASK 0x0000000040000000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1 */ +/* Description: Replace Checkbyte Continous */ +#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_SHFT 31 +#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_MASK 0x0000000080000000 + +/* SH_XNPI_ECC_INJ_REG_BYTE2 */ +/* Description: Replacement Checkbyte */ +#define SH_XNPI_ECC_INJ_REG_BYTE2_SHFT 32 +#define SH_XNPI_ECC_INJ_REG_BYTE2_MASK 0x000000ff00000000 + +/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT2 */ +/* Description: 1 shot mask data */ +#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_SHFT 44 +#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_MASK 0x0000100000000000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CONT2 */ +/* Description: toggle mask data */ +#define SH_XNPI_ECC_INJ_REG_DATA_CONT2_SHFT 45 +#define SH_XNPI_ECC_INJ_REG_DATA_CONT2_MASK 0x0000200000000000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2 */ +/* Description: Replace Checkbyte OneShot */ +#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT 46 +#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_MASK 0x0000400000000000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2 */ +/* Description: Replace Checkbyte Continous */ +#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_SHFT 47 +#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_MASK 0x0000800000000000 + +/* SH_XNPI_ECC_INJ_REG_BYTE3 */ +/* Description: Replacement Checkbyte */ +#define SH_XNPI_ECC_INJ_REG_BYTE3_SHFT 48 +#define SH_XNPI_ECC_INJ_REG_BYTE3_MASK 0x00ff000000000000 + +/* SH_XNPI_ECC_INJ_REG_DATA_1SHOT3 */ +/* Description: 1 shot mask data */ +#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_SHFT 60 +#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_MASK 0x1000000000000000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CONT3 */ +/* Description: toggle mask data */ +#define SH_XNPI_ECC_INJ_REG_DATA_CONT3_SHFT 61 +#define SH_XNPI_ECC_INJ_REG_DATA_CONT3_MASK 0x2000000000000000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3 */ +/* Description: Replace Checkbyte One-Shot */ +#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT 62 +#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_MASK 0x4000000000000000 + +/* SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3 */ +/* Description: Replace Checkbyte Continous */ +#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_SHFT 63 +#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNPI_ECC0_INJ_MASK_REG" */ +/* ==================================================================== */ + +#define SH_XNPI_ECC0_INJ_MASK_REG 0x0000000150032008 +#define SH_XNPI_ECC0_INJ_MASK_REG_MASK 0xffffffffffffffff +#define SH_XNPI_ECC0_INJ_MASK_REG_INIT 0x0000000000000000 + +/* SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0 */ +/* Description: Replacement Data */ +#define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0 +#define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XNPI_ECC1_INJ_MASK_REG" */ +/* ==================================================================== */ + +#define SH_XNPI_ECC1_INJ_MASK_REG 0x0000000150032010 +#define SH_XNPI_ECC1_INJ_MASK_REG_MASK 0xffffffffffffffff +#define SH_XNPI_ECC1_INJ_MASK_REG_INIT 0x0000000000000000 + +/* SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1 */ +/* Description: Replacement Data */ +#define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0 +#define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XNPI_ECC2_INJ_MASK_REG" */ +/* ==================================================================== */ + +#define SH_XNPI_ECC2_INJ_MASK_REG 0x0000000150032018 +#define SH_XNPI_ECC2_INJ_MASK_REG_MASK 0xffffffffffffffff +#define SH_XNPI_ECC2_INJ_MASK_REG_INIT 0x0000000000000000 + +/* SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2 */ +/* Description: Replacement Data */ +#define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0 +#define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XNPI_ECC3_INJ_MASK_REG" */ +/* ==================================================================== */ + +#define SH_XNPI_ECC3_INJ_MASK_REG 0x0000000150032020 +#define SH_XNPI_ECC3_INJ_MASK_REG_MASK 0xffffffffffffffff +#define SH_XNPI_ECC3_INJ_MASK_REG_INIT 0x0000000000000000 + +/* SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3 */ +/* Description: Replacement Data */ +#define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0 +#define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC_INJ_REG" */ +/* ==================================================================== */ + +#define SH_XNMD_ECC_INJ_REG 0x0000000150032030 +#define SH_XNMD_ECC_INJ_REG_MASK 0xf0fff0fff0fff0ff +#define SH_XNMD_ECC_INJ_REG_INIT 0x0000000000000000 + +/* SH_XNMD_ECC_INJ_REG_BYTE0 */ +/* Description: Replacement Checkbyte */ +#define SH_XNMD_ECC_INJ_REG_BYTE0_SHFT 0 +#define SH_XNMD_ECC_INJ_REG_BYTE0_MASK 0x00000000000000ff + +/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT0 */ +/* Description: 1 shot mask data */ +#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_SHFT 12 +#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_MASK 0x0000000000001000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CONT0 */ +/* Description: toggle mask data */ +#define SH_XNMD_ECC_INJ_REG_DATA_CONT0_SHFT 13 +#define SH_XNMD_ECC_INJ_REG_DATA_CONT0_MASK 0x0000000000002000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0 */ +/* Description: Replace Checkbyte One Shot */ +#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT 14 +#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_MASK 0x0000000000004000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0 */ +/* Description: Replace Checkbyte Continuous */ +#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_SHFT 15 +#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_MASK 0x0000000000008000 + +/* SH_XNMD_ECC_INJ_REG_BYTE1 */ +/* Description: Replacement Checkbyte */ +#define SH_XNMD_ECC_INJ_REG_BYTE1_SHFT 16 +#define SH_XNMD_ECC_INJ_REG_BYTE1_MASK 0x0000000000ff0000 + +/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT1 */ +/* Description: 1 shot mask data */ +#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_SHFT 28 +#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_MASK 0x0000000010000000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CONT1 */ +/* Description: toggle mask data */ +#define SH_XNMD_ECC_INJ_REG_DATA_CONT1_SHFT 29 +#define SH_XNMD_ECC_INJ_REG_DATA_CONT1_MASK 0x0000000020000000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1 */ +/* Description: Replace Checkbyte One Shot */ +#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT 30 +#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_MASK 0x0000000040000000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1 */ +/* Description: Replace Checkbyte Continous */ +#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_SHFT 31 +#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_MASK 0x0000000080000000 + +/* SH_XNMD_ECC_INJ_REG_BYTE2 */ +/* Description: Replacement Checkbyte */ +#define SH_XNMD_ECC_INJ_REG_BYTE2_SHFT 32 +#define SH_XNMD_ECC_INJ_REG_BYTE2_MASK 0x000000ff00000000 + +/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT2 */ +/* Description: 1 shot mask data */ +#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_SHFT 44 +#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_MASK 0x0000100000000000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CONT2 */ +/* Description: toggle mask data */ +#define SH_XNMD_ECC_INJ_REG_DATA_CONT2_SHFT 45 +#define SH_XNMD_ECC_INJ_REG_DATA_CONT2_MASK 0x0000200000000000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2 */ +/* Description: Replace Checkbyte OneShot */ +#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT 46 +#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_MASK 0x0000400000000000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2 */ +/* Description: Replace Checkbyte Continous */ +#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_SHFT 47 +#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_MASK 0x0000800000000000 + +/* SH_XNMD_ECC_INJ_REG_BYTE3 */ +/* Description: Replacement Checkbyte */ +#define SH_XNMD_ECC_INJ_REG_BYTE3_SHFT 48 +#define SH_XNMD_ECC_INJ_REG_BYTE3_MASK 0x00ff000000000000 + +/* SH_XNMD_ECC_INJ_REG_DATA_1SHOT3 */ +/* Description: 1 shot mask data */ +#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_SHFT 60 +#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_MASK 0x1000000000000000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CONT3 */ +/* Description: toggle mask data */ +#define SH_XNMD_ECC_INJ_REG_DATA_CONT3_SHFT 61 +#define SH_XNMD_ECC_INJ_REG_DATA_CONT3_MASK 0x2000000000000000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3 */ +/* Description: Replace Checkbyte One-Shot */ +#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT 62 +#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_MASK 0x4000000000000000 + +/* SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3 */ +/* Description: Replace Checkbyte Continous */ +#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_SHFT 63 +#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC0_INJ_MASK_REG" */ +/* ==================================================================== */ + +#define SH_XNMD_ECC0_INJ_MASK_REG 0x0000000150032038 +#define SH_XNMD_ECC0_INJ_MASK_REG_MASK 0xffffffffffffffff +#define SH_XNMD_ECC0_INJ_MASK_REG_INIT 0x0000000000000000 + +/* SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0 */ +/* Description: Replacement Data */ +#define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0 +#define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC1_INJ_MASK_REG" */ +/* ==================================================================== */ + +#define SH_XNMD_ECC1_INJ_MASK_REG 0x0000000150032040 +#define SH_XNMD_ECC1_INJ_MASK_REG_MASK 0xffffffffffffffff +#define SH_XNMD_ECC1_INJ_MASK_REG_INIT 0x0000000000000000 + +/* SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1 */ +/* Description: Replacement Data */ +#define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0 +#define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC2_INJ_MASK_REG" */ +/* ==================================================================== */ + +#define SH_XNMD_ECC2_INJ_MASK_REG 0x0000000150032048 +#define SH_XNMD_ECC2_INJ_MASK_REG_MASK 0xffffffffffffffff +#define SH_XNMD_ECC2_INJ_MASK_REG_INIT 0x0000000000000000 + +/* SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2 */ +/* Description: Replacement Data */ +#define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0 +#define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC3_INJ_MASK_REG" */ +/* ==================================================================== */ + +#define SH_XNMD_ECC3_INJ_MASK_REG 0x0000000150032050 +#define SH_XNMD_ECC3_INJ_MASK_REG_MASK 0xffffffffffffffff +#define SH_XNMD_ECC3_INJ_MASK_REG_INIT 0x0000000000000000 + +/* SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3 */ +/* Description: Replacement Data */ +#define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0 +#define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC_ERR_REPORT" */ +/* ==================================================================== */ + +#define SH_XNMD_ECC_ERR_REPORT 0x0000000150032058 +#define SH_XNMD_ECC_ERR_REPORT_MASK 0x0001000100010001 +#define SH_XNMD_ECC_ERR_REPORT_INIT 0x0000000000000000 + +/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0 */ +/* Description: Disable Error Correction */ +#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_SHFT 0 +#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_MASK 0x0000000000000001 + +/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1 */ +/* Description: Disable Error Correction */ +#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_SHFT 16 +#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_MASK 0x0000000000010000 + +/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2 */ +/* Description: Disable Error Correction */ +#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_SHFT 32 +#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_MASK 0x0000000100000000 + +/* SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3 */ +/* Description: Disable Error Correction */ +#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_SHFT 48 +#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_MASK 0x0001000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_SUMMARY_1" */ +/* ni0 Error Summary Bits */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_SUMMARY_1 0x0000000150040500 +#define SH_NI0_ERROR_SUMMARY_1_MASK 0xffffffffffffffff +#define SH_NI0_ERROR_SUMMARY_1_INIT 0xffffffffffffffff + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0 */ +/* Description: Fifo 02 debit0 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2 */ +/* Description: Fifo 02 debit2 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0 */ +/* Description: Fifo 13 debit0 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2 */ +/* Description: Fifo 13 debit2 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit overflow 0 */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit overflow 1 */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit overflow 2 */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit overflow 0 */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit overflow 1 */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit overflow 2 */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0 */ +/* Description: PI Fifo debit0 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2 */ +/* Description: PI Fifo debit2 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0 */ +/* Description: IILB Fifo debit0 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2 */ +/* Description: IILB Fifo debit2 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0 */ +/* Description: MD Fifo debit0 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2 */ +/* Description: MD Fifo debit2 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0 */ +/* Description: NI Fifo debit0 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1 */ +/* Description: NI Fifo debit1 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2 */ +/* Description: NI Fifo debit2 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3 */ +/* Description: NI Fifo debit3 overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit overflow */ +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0 */ +/* Description: Fifo02 vc0 tail timeout */ +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2 */ +/* Description: Fifo02 vc2 tail timeout */ +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1 */ +/* Description: Fifo13 vc1 tail timeout */ +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3 */ +/* Description: Fifo13 vc3 tail timeout */ +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0 */ +/* Description: NI vc0 tail timeout */ +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1 */ +/* Description: NI vc1 tail timeout */ +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2 */ +/* Description: NI vc2 tail timeout */ +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 + +/* SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3 */ +/* Description: NI vc3 tail timeout */ +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 +#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_SUMMARY_1_ALIAS" */ +/* ni0 Error Summary Bits Alias */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_SUMMARY_1_ALIAS 0x0000000150040508 + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_SUMMARY_2" */ +/* ni0 Error Summary Bits */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_SUMMARY_2 0x0000000150040510 +#define SH_NI0_ERROR_SUMMARY_2_MASK 0x7fffffff003fffff +#define SH_NI0_ERROR_SUMMARY_2_INIT 0x7fffffff003fffff + +/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI */ +/* Description: Illegal VC NI */ +#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0 +#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001 + +/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI */ +/* Description: Illegal VC PI */ +#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1 +#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002 + +/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD */ +/* Description: Illegal VC MD */ +#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2 +#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004 + +/* SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB */ +/* Description: Illegal VC IILB */ +#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3 +#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit underflow 0 */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit underflow 1 */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit underflow 2 */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit underflow 0 */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit underflow 1 */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit underflow 2 */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit underflow */ +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0 */ +/* Description: llp deadlock vc0 */ +#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56 +#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1 */ +/* Description: llp deadlock vc1 */ +#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57 +#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2 */ +/* Description: llp deadlock vc2 */ +#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58 +#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3 */ +/* Description: llp deadlock vc3 */ +#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59 +#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60 +#define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61 +#define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000 + +/* SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR */ +/* Description: Retry Timeout Error */ +#define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62 +#define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_SUMMARY_2_ALIAS" */ +/* ni0 Error Summary Bits Alias */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_SUMMARY_2_ALIAS 0x0000000150040518 + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_OVERFLOW_1" */ +/* ni0 Error Overflow Bits */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_OVERFLOW_1 0x0000000150040520 +#define SH_NI0_ERROR_OVERFLOW_1_MASK 0xffffffffffffffff +#define SH_NI0_ERROR_OVERFLOW_1_INIT 0xffffffffffffffff + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0 */ +/* Description: Fifo 02 debit0 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2 */ +/* Description: Fifo 02 debit2 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0 */ +/* Description: Fifo 13 debit0 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2 */ +/* Description: Fifo 13 debit2 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit overflow 0 */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit overflow 1 */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit overflow 2 */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit overflow 0 */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit overflow 1 */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit overflow 2 */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0 */ +/* Description: PI Fifo debit0 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2 */ +/* Description: PI Fifo debit2 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0 */ +/* Description: IILB Fifo debit0 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2 */ +/* Description: IILB Fifo debit2 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0 */ +/* Description: MD Fifo debit0 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2 */ +/* Description: MD Fifo debit2 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0 */ +/* Description: NI Fifo debit0 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1 */ +/* Description: NI Fifo debit1 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2 */ +/* Description: NI Fifo debit2 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3 */ +/* Description: NI Fifo debit3 overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit overflow */ +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0 */ +/* Description: Fifo02 vc0 tail timeout */ +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2 */ +/* Description: Fifo02 vc2 tail timeout */ +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1 */ +/* Description: Fifo13 vc1 tail timeout */ +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3 */ +/* Description: Fifo13 vc3 tail timeout */ +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0 */ +/* Description: NI vc0 tail timeout */ +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1 */ +/* Description: NI vc1 tail timeout */ +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2 */ +/* Description: NI vc2 tail timeout */ +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 + +/* SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3 */ +/* Description: NI vc3 tail timeout */ +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 +#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_OVERFLOW_1_ALIAS" */ +/* ni0 Error Overflow Bits Alias */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_OVERFLOW_1_ALIAS 0x0000000150040528 + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_OVERFLOW_2" */ +/* ni0 Error Overflow Bits */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_OVERFLOW_2 0x0000000150040530 +#define SH_NI0_ERROR_OVERFLOW_2_MASK 0x7fffffff003fffff +#define SH_NI0_ERROR_OVERFLOW_2_INIT 0x7fffffff003fffff + +/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI */ +/* Description: Illegal VC NI */ +#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0 +#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001 + +/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI */ +/* Description: Illegal VC PI */ +#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1 +#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002 + +/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD */ +/* Description: Illegal VC MD */ +#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2 +#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004 + +/* SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB */ +/* Description: Illegal VC IILB */ +#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3 +#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit underflow 0 */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit underflow 1 */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit underflow 2 */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit underflow 0 */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit underflow 1 */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit underflow 2 */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit underflow */ +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0 */ +/* Description: llp deadlock vc0 */ +#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56 +#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1 */ +/* Description: llp deadlock vc1 */ +#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57 +#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2 */ +/* Description: llp deadlock vc2 */ +#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58 +#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3 */ +/* Description: llp deadlock vc3 */ +#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59 +#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60 +#define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61 +#define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000 + +/* SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR */ +/* Description: Retry Timeout Error */ +#define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62 +#define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_OVERFLOW_2_ALIAS" */ +/* ni0 Error Overflow Bits Alias */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_OVERFLOW_2_ALIAS 0x0000000150040538 + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_MASK_1" */ +/* ni0 Error Mask Bits */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_MASK_1 0x0000000150040540 +#define SH_NI0_ERROR_MASK_1_MASK 0xffffffffffffffff +#define SH_NI0_ERROR_MASK_1_INIT 0xffffffffffffffff + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0 */ +/* Description: Fifo 02 debit0 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2 */ +/* Description: Fifo 02 debit2 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0 */ +/* Description: Fifo 13 debit0 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2 */ +/* Description: Fifo 13 debit2 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit overflow 0 */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit overflow 1 */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit overflow 2 */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit overflow 0 */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit overflow 1 */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit overflow 2 */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0 */ +/* Description: PI Fifo debit0 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2 */ +/* Description: PI Fifo debit2 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0 */ +/* Description: IILB Fifo debit0 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2 */ +/* Description: IILB Fifo debit2 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0 */ +/* Description: MD Fifo debit0 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2 */ +/* Description: MD Fifo debit2 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0 */ +/* Description: NI Fifo debit0 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1 */ +/* Description: NI Fifo debit1 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2 */ +/* Description: NI Fifo debit2 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3 */ +/* Description: NI Fifo debit3 overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit overflow */ +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0 */ +/* Description: Fifo02 vc0 tail timeout */ +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 + +/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2 */ +/* Description: Fifo02 vc2 tail timeout */ +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 + +/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1 */ +/* Description: Fifo13 vc1 tail timeout */ +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 + +/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3 */ +/* Description: Fifo13 vc3 tail timeout */ +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 + +/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0 */ +/* Description: NI vc0 tail timeout */ +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 + +/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1 */ +/* Description: NI vc1 tail timeout */ +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 + +/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2 */ +/* Description: NI vc2 tail timeout */ +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 + +/* SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3 */ +/* Description: NI vc3 tail timeout */ +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 +#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_MASK_2" */ +/* ni0 Error Mask Bits */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_MASK_2 0x0000000150040550 +#define SH_NI0_ERROR_MASK_2_MASK 0x7fffffff003fffff +#define SH_NI0_ERROR_MASK_2_INIT 0x7fffffff003fffff + +/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI */ +/* Description: Illegal VC NI */ +#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_SHFT 0 +#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_MASK 0x0000000000000001 + +/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI */ +/* Description: Illegal VC PI */ +#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_SHFT 1 +#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_MASK 0x0000000000000002 + +/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD */ +/* Description: Illegal VC MD */ +#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_SHFT 2 +#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_MASK 0x0000000000000004 + +/* SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB */ +/* Description: Illegal VC IILB */ +#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT 3 +#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit underflow 0 */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit underflow 1 */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit underflow 2 */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit underflow 0 */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit underflow 1 */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit underflow 2 */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit underflow */ +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0 */ +/* Description: llp deadlock vc0 */ +#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56 +#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 + +/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1 */ +/* Description: llp deadlock vc1 */ +#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57 +#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 + +/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2 */ +/* Description: llp deadlock vc2 */ +#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58 +#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 + +/* SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3 */ +/* Description: llp deadlock vc3 */ +#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59 +#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 + +/* SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60 +#define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 + +/* SH_NI0_ERROR_MASK_2_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_SHFT 61 +#define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_MASK 0x2000000000000000 + +/* SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR */ +/* Description: Retry Timeout Error */ +#define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62 +#define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_FIRST_ERROR_1" */ +/* ni0 First Error Bits */ +/* ==================================================================== */ + +#define SH_NI0_FIRST_ERROR_1 0x0000000150040560 +#define SH_NI0_FIRST_ERROR_1_MASK 0xffffffffffffffff +#define SH_NI0_FIRST_ERROR_1_INIT 0xffffffffffffffff + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0 */ +/* Description: Fifo 02 debit0 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2 */ +/* Description: Fifo 02 debit2 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0 */ +/* Description: Fifo 13 debit0 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2 */ +/* Description: Fifo 13 debit2 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit overflow 0 */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit overflow 1 */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit overflow 2 */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit overflow 0 */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit overflow 1 */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit overflow 2 */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0 */ +/* Description: PI Fifo debit0 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2 */ +/* Description: PI Fifo debit2 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0 */ +/* Description: IILB Fifo debit0 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2 */ +/* Description: IILB Fifo debit2 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0 */ +/* Description: MD Fifo debit0 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2 */ +/* Description: MD Fifo debit2 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0 */ +/* Description: NI Fifo debit0 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1 */ +/* Description: NI Fifo debit1 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2 */ +/* Description: NI Fifo debit2 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3 */ +/* Description: NI Fifo debit3 overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit overflow */ +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0 */ +/* Description: Fifo02 vc0 tail timeout */ +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 + +/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2 */ +/* Description: Fifo02 vc2 tail timeout */ +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 + +/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1 */ +/* Description: Fifo13 vc1 tail timeout */ +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 + +/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3 */ +/* Description: Fifo13 vc3 tail timeout */ +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 + +/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0 */ +/* Description: NI vc0 tail timeout */ +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 + +/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1 */ +/* Description: NI vc1 tail timeout */ +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 + +/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2 */ +/* Description: NI vc2 tail timeout */ +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 + +/* SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3 */ +/* Description: NI vc3 tail timeout */ +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 +#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_FIRST_ERROR_2" */ +/* ni0 First Error Bits */ +/* ==================================================================== */ + +#define SH_NI0_FIRST_ERROR_2 0x0000000150040570 +#define SH_NI0_FIRST_ERROR_2_MASK 0x7fffffff003fffff +#define SH_NI0_FIRST_ERROR_2_INIT 0x7fffffff003fffff + +/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI */ +/* Description: Illegal VC NI */ +#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT 0 +#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_MASK 0x0000000000000001 + +/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI */ +/* Description: Illegal VC PI */ +#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT 1 +#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_MASK 0x0000000000000002 + +/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD */ +/* Description: Illegal VC MD */ +#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT 2 +#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_MASK 0x0000000000000004 + +/* SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB */ +/* Description: Illegal VC IILB */ +#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3 +#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit underflow 0 */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit underflow 1 */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit underflow 2 */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit underflow 0 */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit underflow 1 */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit underflow 2 */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit underflow */ +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0 */ +/* Description: llp deadlock vc0 */ +#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56 +#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 + +/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1 */ +/* Description: llp deadlock vc1 */ +#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57 +#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 + +/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2 */ +/* Description: llp deadlock vc2 */ +#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58 +#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 + +/* SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3 */ +/* Description: llp deadlock vc3 */ +#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59 +#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 + +/* SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60 +#define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 + +/* SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61 +#define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000 + +/* SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR */ +/* Description: Retry Timeout Error */ +#define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62 +#define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_DETAIL_1" */ +/* ni0 Chiplet no match header bits 63:0 */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_DETAIL_1 0x0000000150040580 +#define SH_NI0_ERROR_DETAIL_1_MASK 0xffffffffffffffff +#define SH_NI0_ERROR_DETAIL_1_INIT 0x0000000000000000 + +/* SH_NI0_ERROR_DETAIL_1_HEADER */ +/* Description: Header bits 63:0 */ +#define SH_NI0_ERROR_DETAIL_1_HEADER_SHFT 0 +#define SH_NI0_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_DETAIL_2" */ +/* ni0 Chiplet no match header bits 127:64 */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_DETAIL_2 0x0000000150040590 +#define SH_NI0_ERROR_DETAIL_2_MASK 0xffffffffffffffff +#define SH_NI0_ERROR_DETAIL_2_INIT 0x0000000000000000 + +/* SH_NI0_ERROR_DETAIL_2_HEADER */ +/* Description: Header bits 127:64 */ +#define SH_NI0_ERROR_DETAIL_2_HEADER_SHFT 0 +#define SH_NI0_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_SUMMARY_1" */ +/* ni1 Error Summary Bits */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_SUMMARY_1 0x0000000150040600 +#define SH_NI1_ERROR_SUMMARY_1_MASK 0xffffffffffffffff +#define SH_NI1_ERROR_SUMMARY_1_INIT 0xffffffffffffffff + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0 */ +/* Description: Fifo 02 debit0 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2 */ +/* Description: Fifo 02 debit2 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0 */ +/* Description: Fifo 13 debit0 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2 */ +/* Description: Fifo 13 debit2 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit overflow 0 */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit overflow 1 */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit overflow 2 */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit overflow 0 */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit overflow 1 */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit overflow 2 */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0 */ +/* Description: PI Fifo debit0 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2 */ +/* Description: PI Fifo debit2 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0 */ +/* Description: IILB Fifo debit0 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2 */ +/* Description: IILB Fifo debit2 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0 */ +/* Description: MD Fifo debit0 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2 */ +/* Description: MD Fifo debit2 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0 */ +/* Description: NI Fifo debit0 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1 */ +/* Description: NI Fifo debit1 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2 */ +/* Description: NI Fifo debit2 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3 */ +/* Description: NI Fifo debit3 overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit overflow */ +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0 */ +/* Description: Fifo02 vc0 tail timeout */ +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2 */ +/* Description: Fifo02 vc2 tail timeout */ +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1 */ +/* Description: Fifo13 vc1 tail timeout */ +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3 */ +/* Description: Fifo13 vc3 tail timeout */ +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0 */ +/* Description: NI vc0 tail timeout */ +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1 */ +/* Description: NI vc1 tail timeout */ +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2 */ +/* Description: NI vc2 tail timeout */ +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 + +/* SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3 */ +/* Description: NI vc3 tail timeout */ +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 +#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_SUMMARY_1_ALIAS" */ +/* ni1 Error Summary Bits Alias */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_SUMMARY_1_ALIAS 0x0000000150040608 + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_SUMMARY_2" */ +/* ni1 Error Summary Bits */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_SUMMARY_2 0x0000000150040610 +#define SH_NI1_ERROR_SUMMARY_2_MASK 0x7fffffff003fffff +#define SH_NI1_ERROR_SUMMARY_2_INIT 0x7fffffff003fffff + +/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI */ +/* Description: Illegal VC NI */ +#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0 +#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001 + +/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI */ +/* Description: Illegal VC PI */ +#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1 +#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002 + +/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD */ +/* Description: Illegal VC MD */ +#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2 +#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004 + +/* SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB */ +/* Description: Illegal VC IILB */ +#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3 +#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit underflow 0 */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit underflow 1 */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit underflow 2 */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit underflow 0 */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit underflow 1 */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit underflow 2 */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit underflow */ +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0 */ +/* Description: llp deadlock vc0 */ +#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56 +#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1 */ +/* Description: llp deadlock vc1 */ +#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57 +#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2 */ +/* Description: llp deadlock vc2 */ +#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58 +#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3 */ +/* Description: llp deadlock vc3 */ +#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59 +#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60 +#define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61 +#define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000 + +/* SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR */ +/* Description: Retry Timeout Error */ +#define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62 +#define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_SUMMARY_2_ALIAS" */ +/* ni1 Error Summary Bits Alias */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_SUMMARY_2_ALIAS 0x0000000150040618 + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_OVERFLOW_1" */ +/* ni1 Error Overflow Bits */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_OVERFLOW_1 0x0000000150040620 +#define SH_NI1_ERROR_OVERFLOW_1_MASK 0xffffffffffffffff +#define SH_NI1_ERROR_OVERFLOW_1_INIT 0xffffffffffffffff + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0 */ +/* Description: Fifo 02 debit0 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2 */ +/* Description: Fifo 02 debit2 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0 */ +/* Description: Fifo 13 debit0 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2 */ +/* Description: Fifo 13 debit2 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit overflow 0 */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit overflow 1 */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit overflow 2 */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit overflow 0 */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit overflow 1 */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit overflow 2 */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0 */ +/* Description: PI Fifo debit0 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2 */ +/* Description: PI Fifo debit2 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0 */ +/* Description: IILB Fifo debit0 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2 */ +/* Description: IILB Fifo debit2 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0 */ +/* Description: MD Fifo debit0 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2 */ +/* Description: MD Fifo debit2 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0 */ +/* Description: NI Fifo debit0 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1 */ +/* Description: NI Fifo debit1 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2 */ +/* Description: NI Fifo debit2 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3 */ +/* Description: NI Fifo debit3 overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit overflow */ +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0 */ +/* Description: Fifo02 vc0 tail timeout */ +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2 */ +/* Description: Fifo02 vc2 tail timeout */ +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1 */ +/* Description: Fifo13 vc1 tail timeout */ +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3 */ +/* Description: Fifo13 vc3 tail timeout */ +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0 */ +/* Description: NI vc0 tail timeout */ +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1 */ +/* Description: NI vc1 tail timeout */ +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2 */ +/* Description: NI vc2 tail timeout */ +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 + +/* SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3 */ +/* Description: NI vc3 tail timeout */ +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 +#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_OVERFLOW_1_ALIAS" */ +/* ni1 Error Overflow Bits Alias */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_OVERFLOW_1_ALIAS 0x0000000150040628 + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_OVERFLOW_2" */ +/* ni1 Error Overflow Bits */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_OVERFLOW_2 0x0000000150040630 +#define SH_NI1_ERROR_OVERFLOW_2_MASK 0x7fffffff003fffff +#define SH_NI1_ERROR_OVERFLOW_2_INIT 0x7fffffff003fffff + +/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI */ +/* Description: Illegal VC NI */ +#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0 +#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001 + +/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI */ +/* Description: Illegal VC PI */ +#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1 +#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002 + +/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD */ +/* Description: Illegal VC MD */ +#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2 +#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004 + +/* SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB */ +/* Description: Illegal VC IILB */ +#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3 +#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit underflow 0 */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit underflow 1 */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit underflow 2 */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit underflow 0 */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit underflow 1 */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit underflow 2 */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit underflow */ +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0 */ +/* Description: llp deadlock vc0 */ +#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56 +#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1 */ +/* Description: llp deadlock vc1 */ +#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57 +#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2 */ +/* Description: llp deadlock vc2 */ +#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58 +#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3 */ +/* Description: llp deadlock vc3 */ +#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59 +#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60 +#define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61 +#define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000 + +/* SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR */ +/* Description: Retry Timeout Error */ +#define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62 +#define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_OVERFLOW_2_ALIAS" */ +/* ni1 Error Overflow Bits Alias */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_OVERFLOW_2_ALIAS 0x0000000150040638 + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_MASK_1" */ +/* ni1 Error Mask Bits */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_MASK_1 0x0000000150040640 +#define SH_NI1_ERROR_MASK_1_MASK 0xffffffffffffffff +#define SH_NI1_ERROR_MASK_1_INIT 0xffffffffffffffff + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0 */ +/* Description: Fifo 02 debit0 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2 */ +/* Description: Fifo 02 debit2 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0 */ +/* Description: Fifo 13 debit0 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2 */ +/* Description: Fifo 13 debit2 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit overflow 0 */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit overflow 1 */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit overflow 2 */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit overflow 0 */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit overflow 1 */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit overflow 2 */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0 */ +/* Description: PI Fifo debit0 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2 */ +/* Description: PI Fifo debit2 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0 */ +/* Description: IILB Fifo debit0 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2 */ +/* Description: IILB Fifo debit2 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0 */ +/* Description: MD Fifo debit0 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2 */ +/* Description: MD Fifo debit2 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0 */ +/* Description: NI Fifo debit0 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1 */ +/* Description: NI Fifo debit1 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2 */ +/* Description: NI Fifo debit2 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3 */ +/* Description: NI Fifo debit3 overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit overflow */ +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0 */ +/* Description: Fifo02 vc0 tail timeout */ +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 + +/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2 */ +/* Description: Fifo02 vc2 tail timeout */ +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 + +/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1 */ +/* Description: Fifo13 vc1 tail timeout */ +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 + +/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3 */ +/* Description: Fifo13 vc3 tail timeout */ +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 + +/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0 */ +/* Description: NI vc0 tail timeout */ +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 + +/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1 */ +/* Description: NI vc1 tail timeout */ +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 + +/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2 */ +/* Description: NI vc2 tail timeout */ +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 + +/* SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3 */ +/* Description: NI vc3 tail timeout */ +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 +#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_MASK_2" */ +/* ni1 Error Mask Bits */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_MASK_2 0x0000000150040650 +#define SH_NI1_ERROR_MASK_2_MASK 0x7fffffff003fffff +#define SH_NI1_ERROR_MASK_2_INIT 0x7fffffff003fffff + +/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI */ +/* Description: Illegal VC NI */ +#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_SHFT 0 +#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_MASK 0x0000000000000001 + +/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI */ +/* Description: Illegal VC PI */ +#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_SHFT 1 +#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_MASK 0x0000000000000002 + +/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD */ +/* Description: Illegal VC MD */ +#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_SHFT 2 +#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_MASK 0x0000000000000004 + +/* SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB */ +/* Description: Illegal VC IILB */ +#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT 3 +#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit underflow 0 */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit underflow 1 */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit underflow 2 */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit underflow 0 */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit underflow 1 */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit underflow 2 */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit underflow */ +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0 */ +/* Description: llp deadlock vc0 */ +#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56 +#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 + +/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1 */ +/* Description: llp deadlock vc1 */ +#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57 +#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 + +/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2 */ +/* Description: llp deadlock vc2 */ +#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58 +#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 + +/* SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3 */ +/* Description: llp deadlock vc3 */ +#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59 +#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 + +/* SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60 +#define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 + +/* SH_NI1_ERROR_MASK_2_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_SHFT 61 +#define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_MASK 0x2000000000000000 + +/* SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR */ +/* Description: Retry Timeout Error */ +#define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62 +#define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_FIRST_ERROR_1" */ +/* ni1 First Error Bits */ +/* ==================================================================== */ + +#define SH_NI1_FIRST_ERROR_1 0x0000000150040660 +#define SH_NI1_FIRST_ERROR_1_MASK 0xffffffffffffffff +#define SH_NI1_FIRST_ERROR_1_INIT 0xffffffffffffffff + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0 */ +/* Description: Fifo 02 debit0 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2 */ +/* Description: Fifo 02 debit2 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0 */ +/* Description: Fifo 13 debit0 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2 */ +/* Description: Fifo 13 debit2 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit overflow 0 */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit overflow 1 */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit overflow 2 */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit overflow 0 */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit overflow 1 */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit overflow 2 */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0 */ +/* Description: PI Fifo debit0 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2 */ +/* Description: PI Fifo debit2 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0 */ +/* Description: IILB Fifo debit0 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2 */ +/* Description: IILB Fifo debit2 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0 */ +/* Description: MD Fifo debit0 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2 */ +/* Description: MD Fifo debit2 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0 */ +/* Description: NI Fifo debit0 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1 */ +/* Description: NI Fifo debit1 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2 */ +/* Description: NI Fifo debit2 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3 */ +/* Description: NI Fifo debit3 overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit overflow */ +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0 */ +/* Description: Fifo02 vc0 tail timeout */ +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56 +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000 + +/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2 */ +/* Description: Fifo02 vc2 tail timeout */ +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57 +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000 + +/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1 */ +/* Description: Fifo13 vc1 tail timeout */ +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58 +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000 + +/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3 */ +/* Description: Fifo13 vc3 tail timeout */ +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59 +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000 + +/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0 */ +/* Description: NI vc0 tail timeout */ +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60 +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000 + +/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1 */ +/* Description: NI vc1 tail timeout */ +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61 +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000 + +/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2 */ +/* Description: NI vc2 tail timeout */ +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62 +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000 + +/* SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3 */ +/* Description: NI vc3 tail timeout */ +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63 +#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_FIRST_ERROR_2" */ +/* ni1 First Error Bits */ +/* ==================================================================== */ + +#define SH_NI1_FIRST_ERROR_2 0x0000000150040670 +#define SH_NI1_FIRST_ERROR_2_MASK 0x7fffffff003fffff +#define SH_NI1_FIRST_ERROR_2_INIT 0x7fffffff003fffff + +/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI */ +/* Description: Illegal VC NI */ +#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT 0 +#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_MASK 0x0000000000000001 + +/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI */ +/* Description: Illegal VC PI */ +#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT 1 +#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_MASK 0x0000000000000002 + +/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD */ +/* Description: Illegal VC MD */ +#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT 2 +#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_MASK 0x0000000000000004 + +/* SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB */ +/* Description: Illegal VC IILB */ +#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3 +#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP */ +/* Description: Fifo 02 vc0 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP */ +/* Description: Fifo 02 vc2 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP */ +/* Description: Fifo 13 vc1 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP */ +/* Description: Fifo 13 vc3 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH */ +/* Description: Fifo 02 vc0 push underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH */ +/* Description: Fifo 02 vc2 push underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH */ +/* Description: Fifo 13 vc1 push underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH */ +/* Description: Fifo 13 vc3 push underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT */ +/* Description: Fifo 02 vc0 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT */ +/* Description: Fifo 02 vc2 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT */ +/* Description: Fifo 13 vc0 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT */ +/* Description: Fifo 13 vc2 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT */ +/* Description: VC0 credit underflow 0 */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT */ +/* Description: VC0 credit underflow 1 */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT */ +/* Description: VC0 credit underflow 2 */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT */ +/* Description: VC2 credit underflow 0 */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT */ +/* Description: VC2 credit underflow 1 */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT */ +/* Description: VC2 credit underflow 2 */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP */ +/* Description: PI Fifo vc0 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP */ +/* Description: PI Fifo vc2 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP */ +/* Description: IILB Fifo vc0 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP */ +/* Description: IILB Fifo vc2 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP */ +/* Description: MD Fifo vc0 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP */ +/* Description: MD Fifo vc2 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP */ +/* Description: NI Fifo vc0 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP */ +/* Description: NI Fifo vc2 pop underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH */ +/* Description: PI Fifo vc0 push underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH */ +/* Description: PI Fifo vc2 push underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH */ +/* Description: IILB Fifo vc0 push underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH */ +/* Description: IILB Fifo vc2 push underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH */ +/* Description: MD Fifo vc0 push underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH */ +/* Description: MD Fifo vc2 push underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT */ +/* Description: PI Fifo vc0 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT */ +/* Description: PI Fifo vc2 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT */ +/* Description: IILB Fifo vc0 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT */ +/* Description: IILB Fifo vc2 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT */ +/* Description: MD Fifo vc0 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT */ +/* Description: MD Fifo vc2 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT */ +/* Description: NI Fifo vc0 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT */ +/* Description: NI Fifo vc1 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT */ +/* Description: NI Fifo vc2 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000 + +/* SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT */ +/* Description: NI Fifo vc3 credit underflow */ +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55 +#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000 + +/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0 */ +/* Description: llp deadlock vc0 */ +#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56 +#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000 + +/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1 */ +/* Description: llp deadlock vc1 */ +#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57 +#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000 + +/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2 */ +/* Description: llp deadlock vc2 */ +#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58 +#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000 + +/* SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3 */ +/* Description: llp deadlock vc3 */ +#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59 +#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000 + +/* SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60 +#define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000 + +/* SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61 +#define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000 + +/* SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR */ +/* Description: Retry Timeout Error */ +#define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62 +#define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_DETAIL_1" */ +/* ni1 Chiplet no match header bits 63:0 */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_DETAIL_1 0x0000000150040680 +#define SH_NI1_ERROR_DETAIL_1_MASK 0xffffffffffffffff +#define SH_NI1_ERROR_DETAIL_1_INIT 0x0000000000000000 + +/* SH_NI1_ERROR_DETAIL_1_HEADER */ +/* Description: Header bits 63:0 */ +#define SH_NI1_ERROR_DETAIL_1_HEADER_SHFT 0 +#define SH_NI1_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_DETAIL_2" */ +/* ni1 Chiplet no match header bits 127:64 */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_DETAIL_2 0x0000000150040690 +#define SH_NI1_ERROR_DETAIL_2_MASK 0xffffffffffffffff +#define SH_NI1_ERROR_DETAIL_2_INIT 0x0000000000000000 + +/* SH_NI1_ERROR_DETAIL_2_HEADER */ +/* Description: Header bits 127:64 */ +#define SH_NI1_ERROR_DETAIL_2_HEADER_SHFT 0 +#define SH_NI1_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_CORRECTED_DETAIL_1" */ +/* Corrected error details */ +/* ==================================================================== */ + +#define SH_XN_CORRECTED_DETAIL_1 0x0000000150040070 +#define SH_XN_CORRECTED_DETAIL_1_MASK 0x0fff0fff0fff0fff +#define SH_XN_CORRECTED_DETAIL_1_INIT 0x0000000000000000 + +/* SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME */ +/* Description: ECC0 Syndrome */ +#define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0 +#define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff + +/* SH_XN_CORRECTED_DETAIL_1_ECC0_WC */ +/* Description: ECC0 Word Count */ +#define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_SHFT 8 +#define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_MASK 0x0000000000000300 + +/* SH_XN_CORRECTED_DETAIL_1_ECC0_VC */ +/* Description: ECC0 Virtual Channel */ +#define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_SHFT 10 +#define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_MASK 0x0000000000000c00 + +/* SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME */ +/* Description: ECC1 Syndrome */ +#define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16 +#define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000 + +/* SH_XN_CORRECTED_DETAIL_1_ECC1_WC */ +/* Description: ECC1 Word Count */ +#define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_SHFT 24 +#define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_MASK 0x0000000003000000 + +/* SH_XN_CORRECTED_DETAIL_1_ECC1_VC */ +/* Description: ECC1 Virtual Channel */ +#define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_SHFT 26 +#define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_MASK 0x000000000c000000 + +/* SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME */ +/* Description: ECC2 Syndrome */ +#define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32 +#define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000 + +/* SH_XN_CORRECTED_DETAIL_1_ECC2_WC */ +/* Description: ECC2 Word Count */ +#define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_SHFT 40 +#define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_MASK 0x0000030000000000 + +/* SH_XN_CORRECTED_DETAIL_1_ECC2_VC */ +/* Description: ECC2 Virtual Channel */ +#define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_SHFT 42 +#define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_MASK 0x00000c0000000000 + +/* SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME */ +/* Description: ECC3 Syndrome */ +#define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48 +#define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000 + +/* SH_XN_CORRECTED_DETAIL_1_ECC3_WC */ +/* Description: ECC3 Word Count */ +#define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_SHFT 56 +#define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_MASK 0x0300000000000000 + +/* SH_XN_CORRECTED_DETAIL_1_ECC3_VC */ +/* Description: ECC3 Virtual Channel */ +#define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_SHFT 58 +#define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_MASK 0x0c00000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_CORRECTED_DETAIL_2" */ +/* Corrected error data */ +/* ==================================================================== */ + +#define SH_XN_CORRECTED_DETAIL_2 0x0000000150040080 +#define SH_XN_CORRECTED_DETAIL_2_MASK 0xffffffffffffffff +#define SH_XN_CORRECTED_DETAIL_2_INIT 0x0000000000000000 + +/* SH_XN_CORRECTED_DETAIL_2_DATA */ +/* Description: ECC data */ +#define SH_XN_CORRECTED_DETAIL_2_DATA_SHFT 0 +#define SH_XN_CORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_CORRECTED_DETAIL_3" */ +/* Corrected error header0 */ +/* ==================================================================== */ + +#define SH_XN_CORRECTED_DETAIL_3 0x0000000150040090 +#define SH_XN_CORRECTED_DETAIL_3_MASK 0xffffffffffffffff +#define SH_XN_CORRECTED_DETAIL_3_INIT 0x0000000000000000 + +/* SH_XN_CORRECTED_DETAIL_3_HEADER0 */ +/* Description: ECC header0 (bits 63 - 0) */ +#define SH_XN_CORRECTED_DETAIL_3_HEADER0_SHFT 0 +#define SH_XN_CORRECTED_DETAIL_3_HEADER0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_CORRECTED_DETAIL_4" */ +/* Corrected error header1 */ +/* ==================================================================== */ + +#define SH_XN_CORRECTED_DETAIL_4 0x00000001500400a0 +#define SH_XN_CORRECTED_DETAIL_4_MASK 0xc00003ffffffffff +#define SH_XN_CORRECTED_DETAIL_4_INIT 0x0000000000000000 + +/* SH_XN_CORRECTED_DETAIL_4_HEADER1 */ +/* Description: ECC header1 (bits 104 - 64) */ +#define SH_XN_CORRECTED_DETAIL_4_HEADER1_SHFT 0 +#define SH_XN_CORRECTED_DETAIL_4_HEADER1_MASK 0x000003ffffffffff + +/* SH_XN_CORRECTED_DETAIL_4_ERR_GROUP */ +/* Description: Error group */ +#define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_SHFT 62 +#define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_MASK 0xc000000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_UNCORRECTED_DETAIL_1" */ +/* Uncorrected error details */ +/* ==================================================================== */ + +#define SH_XN_UNCORRECTED_DETAIL_1 0x00000001500400b0 +#define SH_XN_UNCORRECTED_DETAIL_1_MASK 0x0fff0fff0fff0fff +#define SH_XN_UNCORRECTED_DETAIL_1_INIT 0x0000000000000000 + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME */ +/* Description: ECC0 Syndrome */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC */ +/* Description: ECC0 Word Count */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_SHFT 8 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_MASK 0x0000000000000300 + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC */ +/* Description: ECC0 Virtual Channel */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_SHFT 10 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_MASK 0x0000000000000c00 + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME */ +/* Description: ECC1 Syndrome */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000 + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC */ +/* Description: ECC1 Word Count */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_SHFT 24 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_MASK 0x0000000003000000 + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC */ +/* Description: ECC1 Virtual Channel */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_SHFT 26 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_MASK 0x000000000c000000 + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME */ +/* Description: ECC2 Syndrome */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000 + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC */ +/* Description: ECC2 Word Count */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_SHFT 40 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_MASK 0x0000030000000000 + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC */ +/* Description: ECC2 Virtual Channel */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_SHFT 42 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_MASK 0x00000c0000000000 + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME */ +/* Description: ECC3 Syndrome */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000 + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC */ +/* Description: ECC3 Word Count */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_SHFT 56 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_MASK 0x0300000000000000 + +/* SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC */ +/* Description: ECC3 Virtual Channel */ +#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_SHFT 58 +#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_MASK 0x0c00000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_UNCORRECTED_DETAIL_2" */ +/* Uncorrected error data */ +/* ==================================================================== */ + +#define SH_XN_UNCORRECTED_DETAIL_2 0x00000001500400c0 +#define SH_XN_UNCORRECTED_DETAIL_2_MASK 0xffffffffffffffff +#define SH_XN_UNCORRECTED_DETAIL_2_INIT 0x0000000000000000 + +/* SH_XN_UNCORRECTED_DETAIL_2_DATA */ +/* Description: ECC data */ +#define SH_XN_UNCORRECTED_DETAIL_2_DATA_SHFT 0 +#define SH_XN_UNCORRECTED_DETAIL_2_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_UNCORRECTED_DETAIL_3" */ +/* Uncorrected error header0 */ +/* ==================================================================== */ + +#define SH_XN_UNCORRECTED_DETAIL_3 0x00000001500400d0 +#define SH_XN_UNCORRECTED_DETAIL_3_MASK 0xffffffffffffffff +#define SH_XN_UNCORRECTED_DETAIL_3_INIT 0x0000000000000000 + +/* SH_XN_UNCORRECTED_DETAIL_3_HEADER0 */ +/* Description: ECC header0 (bits 63 - 0) */ +#define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_SHFT 0 +#define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XN_UNCORRECTED_DETAIL_4" */ +/* Uncorrected error header1 */ +/* ==================================================================== */ + +#define SH_XN_UNCORRECTED_DETAIL_4 0x00000001500400e0 +#define SH_XN_UNCORRECTED_DETAIL_4_MASK 0xc00003ffffffffff +#define SH_XN_UNCORRECTED_DETAIL_4_INIT 0x0000000000000000 + +/* SH_XN_UNCORRECTED_DETAIL_4_HEADER1 */ +/* Description: ECC header1 (bits 104 - 64) */ +#define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_SHFT 0 +#define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_MASK 0x000003ffffffffff + +/* SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP */ +/* Description: Error group */ +#define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_SHFT 62 +#define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_MASK 0xc000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_ERROR_DETAIL_1" */ +/* Look Up Table Address (md) */ +/* ==================================================================== */ + +#define SH_XNMD_ERROR_DETAIL_1 0x00000001500400f0 +#define SH_XNMD_ERROR_DETAIL_1_MASK 0x00000000000007ff +#define SH_XNMD_ERROR_DETAIL_1_INIT 0x0000000000000000 + +/* SH_XNMD_ERROR_DETAIL_1_LUT_ADDR */ +/* Description: Look Up Table Read Address */ +#define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_SHFT 0 +#define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_MASK 0x00000000000007ff + +/* ==================================================================== */ +/* Register "SH_XNPI_ERROR_DETAIL_1" */ +/* Look Up Table Address (pi) */ +/* ==================================================================== */ + +#define SH_XNPI_ERROR_DETAIL_1 0x0000000150040100 +#define SH_XNPI_ERROR_DETAIL_1_MASK 0x00000000000007ff +#define SH_XNPI_ERROR_DETAIL_1_INIT 0x0000000000000000 + +/* SH_XNPI_ERROR_DETAIL_1_LUT_ADDR */ +/* Description: Look Up Table Read Address */ +#define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_SHFT 0 +#define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_MASK 0x00000000000007ff + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_DETAIL_1" */ +/* Chiplet NoMatch header [63:0] */ +/* ==================================================================== */ + +#define SH_XNIILB_ERROR_DETAIL_1 0x0000000150040110 +#define SH_XNIILB_ERROR_DETAIL_1_MASK 0xffffffffffffffff +#define SH_XNIILB_ERROR_DETAIL_1_INIT 0x0000000000000000 + +/* SH_XNIILB_ERROR_DETAIL_1_HEADER */ +/* Description: header bits [63:0] */ +#define SH_XNIILB_ERROR_DETAIL_1_HEADER_SHFT 0 +#define SH_XNIILB_ERROR_DETAIL_1_HEADER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_DETAIL_2" */ +/* Chiplet NoMatch header [127:64] */ +/* ==================================================================== */ + +#define SH_XNIILB_ERROR_DETAIL_2 0x0000000150040120 +#define SH_XNIILB_ERROR_DETAIL_2_MASK 0xffffffffffffffff +#define SH_XNIILB_ERROR_DETAIL_2_INIT 0x0000000000000000 + +/* SH_XNIILB_ERROR_DETAIL_2_HEADER */ +/* Description: header bits [127:64] */ +#define SH_XNIILB_ERROR_DETAIL_2_HEADER_SHFT 0 +#define SH_XNIILB_ERROR_DETAIL_2_HEADER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_DETAIL_3" */ +/* Look Up Table Address (iilb) */ +/* ==================================================================== */ + +#define SH_XNIILB_ERROR_DETAIL_3 0x0000000150040130 +#define SH_XNIILB_ERROR_DETAIL_3_MASK 0x00000000000007ff +#define SH_XNIILB_ERROR_DETAIL_3_INIT 0x0000000000000000 + +/* SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR */ +/* Description: Look Up Table Read Address */ +#define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_SHFT 0 +#define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_DETAIL_3" */ +/* Look Up Table Address (ni0) */ +/* ==================================================================== */ + +#define SH_NI0_ERROR_DETAIL_3 0x0000000150040140 +#define SH_NI0_ERROR_DETAIL_3_MASK 0x00000000000007ff +#define SH_NI0_ERROR_DETAIL_3_INIT 0x0000000000000000 + +/* SH_NI0_ERROR_DETAIL_3_LUT_ADDR */ +/* Description: Look Up Table Read Address */ +#define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_SHFT 0 +#define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_DETAIL_3" */ +/* Look Up Table Address (ni1) */ +/* ==================================================================== */ + +#define SH_NI1_ERROR_DETAIL_3 0x0000000150040150 +#define SH_NI1_ERROR_DETAIL_3_MASK 0x00000000000007ff +#define SH_NI1_ERROR_DETAIL_3_INIT 0x0000000000000000 + +/* SH_NI1_ERROR_DETAIL_3_LUT_ADDR */ +/* Description: Look Up Table Read Address */ +#define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_SHFT 0 +#define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_MASK 0x00000000000007ff + +/* ==================================================================== */ +/* Register "SH_XN_ERROR_SUMMARY" */ +/* ==================================================================== */ + +#define SH_XN_ERROR_SUMMARY 0x0000000150040000 +#define SH_XN_ERROR_SUMMARY_MASK 0x0000003fffffffff +#define SH_XN_ERROR_SUMMARY_INIT 0x0000003fffffffff + +/* SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW */ +/* Description: NI0 pop overflow */ +#define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_SHFT 0 +#define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_MASK 0x0000000000000001 + +/* SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW */ +/* Description: NI0 push overflow */ +#define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_SHFT 1 +#define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 + +/* SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW */ +/* Description: NI0 credit overflow */ +#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_SHFT 2 +#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 + +/* SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW */ +/* Description: NI0 debit overflow */ +#define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_SHFT 3 +#define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 + +/* SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW */ +/* Description: NI0 pop underflow */ +#define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_SHFT 4 +#define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 + +/* SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW */ +/* Description: NI0 push underflow */ +#define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_SHFT 5 +#define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 + +/* SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW */ +/* Description: NI0 credit underflow */ +#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_SHFT 6 +#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 + +/* SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR */ +/* Description: NI0 llp error */ +#define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_SHFT 7 +#define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_MASK 0x0000000000000080 + +/* SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR */ +/* Description: NI0 Pipe in/out errors */ +#define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_SHFT 8 +#define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_MASK 0x0000000000000100 + +/* SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW */ +/* Description: NI1 pop overflow */ +#define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_SHFT 9 +#define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_MASK 0x0000000000000200 + +/* SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW */ +/* Description: NI1 push overflow */ +#define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_SHFT 10 +#define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 + +/* SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW */ +/* Description: NI1 credit overflow */ +#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_SHFT 11 +#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 + +/* SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW */ +/* Description: NI1 debit overflow */ +#define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_SHFT 12 +#define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 + +/* SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW */ +/* Description: NI1 pop underflow */ +#define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_SHFT 13 +#define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 + +/* SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW */ +/* Description: NI1 push underflow */ +#define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_SHFT 14 +#define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 + +/* SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW */ +/* Description: NI1 credit underflow */ +#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_SHFT 15 +#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 + +/* SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR */ +/* Description: NI1 llp error */ +#define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_SHFT 16 +#define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_MASK 0x0000000000010000 + +/* SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR */ +/* Description: NI1 pipe in/out error */ +#define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_SHFT 17 +#define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_MASK 0x0000000000020000 + +/* SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW */ +/* Description: XNMD credit overflow */ +#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_SHFT 18 +#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 + +/* SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW */ +/* Description: XNMD debit overflow */ +#define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_SHFT 19 +#define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 + +/* SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW */ +/* Description: XNMD data buffer overflow */ +#define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 +#define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 + +/* SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW */ +/* Description: XNMD credit underflow */ +#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_SHFT 21 +#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 + +/* SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR */ +/* Description: XNMD single bit error */ +#define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_SHFT 22 +#define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_MASK 0x0000000000400000 + +/* SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR */ +/* Description: XNMD uncorrectable error */ +#define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_SHFT 23 +#define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_MASK 0x0000000000800000 + +/* SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR */ +/* Description: XNMD look up table error */ +#define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_SHFT 24 +#define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_MASK 0x0000000001000000 + +/* SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW */ +/* Description: XNMD credit overflow */ +#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_SHFT 25 +#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 + +/* SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW */ +/* Description: XNPI debit overflow */ +#define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_SHFT 26 +#define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 + +/* SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW */ +/* Description: XNPI data buffer overflow */ +#define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 +#define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 + +/* SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW */ +/* Description: XNPI credit underflow */ +#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_SHFT 28 +#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 + +/* SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR */ +/* Description: XNPI single bit error */ +#define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_SHFT 29 +#define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_MASK 0x0000000020000000 + +/* SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR */ +/* Description: XNPI uncorrectable error */ +#define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_SHFT 30 +#define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_MASK 0x0000000040000000 + +/* SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR */ +/* Description: XNPI look up table error */ +#define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_SHFT 31 +#define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_MASK 0x0000000080000000 + +/* SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW */ +/* Description: IILB debit overflow */ +#define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_SHFT 32 +#define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 + +/* SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW */ +/* Description: IILB credit overflow */ +#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_SHFT 33 +#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 + +/* SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW */ +/* Description: IILB fifo overflow */ +#define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_SHFT 34 +#define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 + +/* SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW */ +/* Description: IILB credit underflow */ +#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_SHFT 35 +#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 + +/* SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW */ +/* Description: IILB fifo underflow */ +#define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_SHFT 36 +#define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 + +/* SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT */ +/* Description: IILB chiplet nomatch or lut read error */ +#define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_SHFT 37 +#define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_XN_ERRORS_ALIAS" */ +/* ==================================================================== */ + +#define SH_XN_ERRORS_ALIAS 0x0000000150040008 + +/* ==================================================================== */ +/* Register "SH_XN_ERROR_OVERFLOW" */ +/* ==================================================================== */ + +#define SH_XN_ERROR_OVERFLOW 0x0000000150040020 +#define SH_XN_ERROR_OVERFLOW_MASK 0x0000003fffffffff +#define SH_XN_ERROR_OVERFLOW_INIT 0x0000003fffffffff + +/* SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW */ +/* Description: NI0 pop overflow */ +#define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_SHFT 0 +#define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_MASK 0x0000000000000001 + +/* SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW */ +/* Description: NI0 push overflow */ +#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_SHFT 1 +#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 + +/* SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW */ +/* Description: NI0 credit overflow */ +#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_SHFT 2 +#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 + +/* SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW */ +/* Description: NI0 debit overflow */ +#define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_SHFT 3 +#define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 + +/* SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW */ +/* Description: NI0 pop underflow */ +#define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_SHFT 4 +#define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 + +/* SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW */ +/* Description: NI0 push underflow */ +#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_SHFT 5 +#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 + +/* SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW */ +/* Description: NI0 credit underflow */ +#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_SHFT 6 +#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 + +/* SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR */ +/* Description: NI0 llp error */ +#define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_SHFT 7 +#define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_MASK 0x0000000000000080 + +/* SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR */ +/* Description: NI0 Pipe in/out errors */ +#define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_SHFT 8 +#define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_MASK 0x0000000000000100 + +/* SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW */ +/* Description: NI1 pop overflow */ +#define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_SHFT 9 +#define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_MASK 0x0000000000000200 + +/* SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW */ +/* Description: NI1 push overflow */ +#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_SHFT 10 +#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 + +/* SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW */ +/* Description: NI1 credit overflow */ +#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_SHFT 11 +#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 + +/* SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW */ +/* Description: NI1 debit overflow */ +#define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_SHFT 12 +#define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 + +/* SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW */ +/* Description: NI1 pop underflow */ +#define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_SHFT 13 +#define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 + +/* SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW */ +/* Description: NI1 push underflow */ +#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_SHFT 14 +#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 + +/* SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW */ +/* Description: NI1 credit underflow */ +#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_SHFT 15 +#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 + +/* SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR */ +/* Description: NI1 llp error */ +#define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_SHFT 16 +#define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_MASK 0x0000000000010000 + +/* SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR */ +/* Description: NI1 pipe in/out error */ +#define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_SHFT 17 +#define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_MASK 0x0000000000020000 + +/* SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW */ +/* Description: XNMD credit overflow */ +#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_SHFT 18 +#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 + +/* SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW */ +/* Description: XNMD debit overflow */ +#define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_SHFT 19 +#define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 + +/* SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW */ +/* Description: XNMD data buffer overflow */ +#define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 +#define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 + +/* SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW */ +/* Description: XNMD credit underflow */ +#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_SHFT 21 +#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 + +/* SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR */ +/* Description: XNMD single bit error */ +#define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_SHFT 22 +#define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_MASK 0x0000000000400000 + +/* SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR */ +/* Description: XNMD uncorrectable error */ +#define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_SHFT 23 +#define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_MASK 0x0000000000800000 + +/* SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR */ +/* Description: XNMD look up table error */ +#define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_SHFT 24 +#define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_MASK 0x0000000001000000 + +/* SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW */ +/* Description: XNMD credit overflow */ +#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_SHFT 25 +#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 + +/* SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW */ +/* Description: XNPI debit overflow */ +#define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_SHFT 26 +#define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 + +/* SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW */ +/* Description: XNPI data buffer overflow */ +#define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 +#define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 + +/* SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW */ +/* Description: XNPI credit underflow */ +#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_SHFT 28 +#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 + +/* SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR */ +/* Description: XNPI single bit error */ +#define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_SHFT 29 +#define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_MASK 0x0000000020000000 + +/* SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR */ +/* Description: XNPI uncorrectable error */ +#define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_SHFT 30 +#define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_MASK 0x0000000040000000 + +/* SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR */ +/* Description: XNPI look up table error */ +#define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_SHFT 31 +#define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_MASK 0x0000000080000000 + +/* SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW */ +/* Description: IILB debit overflow */ +#define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_SHFT 32 +#define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 + +/* SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW */ +/* Description: IILB credit overflow */ +#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_SHFT 33 +#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 + +/* SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW */ +/* Description: IILB fifo overflow */ +#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_SHFT 34 +#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 + +/* SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW */ +/* Description: IILB credit underflow */ +#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_SHFT 35 +#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 + +/* SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW */ +/* Description: IILB fifo underflow */ +#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_SHFT 36 +#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 + +/* SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT */ +/* Description: IILB chiplet nomatch or lut read error */ +#define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_SHFT 37 +#define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_XN_ERROR_OVERFLOW_ALIAS" */ +/* ==================================================================== */ + +#define SH_XN_ERROR_OVERFLOW_ALIAS 0x0000000150040028 + +/* ==================================================================== */ +/* Register "SH_XN_ERROR_MASK" */ +/* ==================================================================== */ + +#define SH_XN_ERROR_MASK 0x0000000150040040 +#define SH_XN_ERROR_MASK_MASK 0x0000003fffffffff +#define SH_XN_ERROR_MASK_INIT 0x0000003fffffffff + +/* SH_XN_ERROR_MASK_NI0_POP_OVERFLOW */ +/* Description: NI0 pop overflow */ +#define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_SHFT 0 +#define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_MASK 0x0000000000000001 + +/* SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW */ +/* Description: NI0 push overflow */ +#define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_SHFT 1 +#define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 + +/* SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW */ +/* Description: NI0 credit overflow */ +#define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_SHFT 2 +#define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 + +/* SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW */ +/* Description: NI0 debit overflow */ +#define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_SHFT 3 +#define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 + +/* SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW */ +/* Description: NI0 pop underflow */ +#define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_SHFT 4 +#define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 + +/* SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW */ +/* Description: NI0 push underflow */ +#define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_SHFT 5 +#define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 + +/* SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW */ +/* Description: NI0 credit underflow */ +#define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_SHFT 6 +#define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 + +/* SH_XN_ERROR_MASK_NI0_LLP_ERROR */ +/* Description: NI0 llp error */ +#define SH_XN_ERROR_MASK_NI0_LLP_ERROR_SHFT 7 +#define SH_XN_ERROR_MASK_NI0_LLP_ERROR_MASK 0x0000000000000080 + +/* SH_XN_ERROR_MASK_NI0_PIPE_ERROR */ +/* Description: NI0 Pipe in/out errors */ +#define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_SHFT 8 +#define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_MASK 0x0000000000000100 + +/* SH_XN_ERROR_MASK_NI1_POP_OVERFLOW */ +/* Description: NI1 pop overflow */ +#define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_SHFT 9 +#define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_MASK 0x0000000000000200 + +/* SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW */ +/* Description: NI1 push overflow */ +#define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_SHFT 10 +#define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 + +/* SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW */ +/* Description: NI1 credit overflow */ +#define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_SHFT 11 +#define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 + +/* SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW */ +/* Description: NI1 debit overflow */ +#define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_SHFT 12 +#define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 + +/* SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW */ +/* Description: NI1 pop underflow */ +#define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_SHFT 13 +#define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 + +/* SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW */ +/* Description: NI1 push underflow */ +#define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_SHFT 14 +#define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 + +/* SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW */ +/* Description: NI1 credit underflow */ +#define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_SHFT 15 +#define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 + +/* SH_XN_ERROR_MASK_NI1_LLP_ERROR */ +/* Description: NI1 llp error */ +#define SH_XN_ERROR_MASK_NI1_LLP_ERROR_SHFT 16 +#define SH_XN_ERROR_MASK_NI1_LLP_ERROR_MASK 0x0000000000010000 + +/* SH_XN_ERROR_MASK_NI1_PIPE_ERROR */ +/* Description: NI1 pipe in/out error */ +#define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_SHFT 17 +#define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_MASK 0x0000000000020000 + +/* SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW */ +/* Description: XNMD credit overflow */ +#define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_SHFT 18 +#define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 + +/* SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW */ +/* Description: XNMD debit overflow */ +#define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_SHFT 19 +#define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 + +/* SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW */ +/* Description: XNMD data buffer overflow */ +#define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 +#define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 + +/* SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW */ +/* Description: XNMD credit underflow */ +#define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_SHFT 21 +#define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 + +/* SH_XN_ERROR_MASK_XNMD_SBE_ERROR */ +/* Description: XNMD single bit error */ +#define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_SHFT 22 +#define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_MASK 0x0000000000400000 + +/* SH_XN_ERROR_MASK_XNMD_UCE_ERROR */ +/* Description: XNMD uncorrectable error */ +#define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_SHFT 23 +#define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_MASK 0x0000000000800000 + +/* SH_XN_ERROR_MASK_XNMD_LUT_ERROR */ +/* Description: XNMD look up table error */ +#define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_SHFT 24 +#define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_MASK 0x0000000001000000 + +/* SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW */ +/* Description: XNMD credit overflow */ +#define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_SHFT 25 +#define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 + +/* SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW */ +/* Description: XNPI debit overflow */ +#define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_SHFT 26 +#define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 + +/* SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW */ +/* Description: XNPI data buffer overflow */ +#define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 +#define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 + +/* SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW */ +/* Description: XNPI credit underflow */ +#define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_SHFT 28 +#define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 + +/* SH_XN_ERROR_MASK_XNPI_SBE_ERROR */ +/* Description: XNPI single bit error */ +#define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_SHFT 29 +#define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_MASK 0x0000000020000000 + +/* SH_XN_ERROR_MASK_XNPI_UCE_ERROR */ +/* Description: XNPI uncorrectable error */ +#define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_SHFT 30 +#define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_MASK 0x0000000040000000 + +/* SH_XN_ERROR_MASK_XNPI_LUT_ERROR */ +/* Description: XNPI look up table error */ +#define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_SHFT 31 +#define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_MASK 0x0000000080000000 + +/* SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW */ +/* Description: IILB debit overflow */ +#define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_SHFT 32 +#define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 + +/* SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW */ +/* Description: IILB credit overflow */ +#define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_SHFT 33 +#define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 + +/* SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW */ +/* Description: IILB fifo overflow */ +#define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_SHFT 34 +#define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 + +/* SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW */ +/* Description: IILB credit underflow */ +#define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_SHFT 35 +#define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 + +/* SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW */ +/* Description: IILB fifo underflow */ +#define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_SHFT 36 +#define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 + +/* SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT */ +/* Description: IILB chiplet nomatch or lut read error */ +#define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_SHFT 37 +#define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_XN_FIRST_ERROR" */ +/* ==================================================================== */ + +#define SH_XN_FIRST_ERROR 0x0000000150040060 +#define SH_XN_FIRST_ERROR_MASK 0x0000003fffffffff +#define SH_XN_FIRST_ERROR_INIT 0x0000003fffffffff + +/* SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW */ +/* Description: NI0 pop overflow */ +#define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_SHFT 0 +#define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_MASK 0x0000000000000001 + +/* SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW */ +/* Description: NI0 push overflow */ +#define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_SHFT 1 +#define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002 + +/* SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW */ +/* Description: NI0 credit overflow */ +#define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_SHFT 2 +#define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004 + +/* SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW */ +/* Description: NI0 debit overflow */ +#define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_SHFT 3 +#define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008 + +/* SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW */ +/* Description: NI0 pop underflow */ +#define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_SHFT 4 +#define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_MASK 0x0000000000000010 + +/* SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW */ +/* Description: NI0 push underflow */ +#define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_SHFT 5 +#define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020 + +/* SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW */ +/* Description: NI0 credit underflow */ +#define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_SHFT 6 +#define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040 + +/* SH_XN_FIRST_ERROR_NI0_LLP_ERROR */ +/* Description: NI0 llp error */ +#define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_SHFT 7 +#define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_MASK 0x0000000000000080 + +/* SH_XN_FIRST_ERROR_NI0_PIPE_ERROR */ +/* Description: NI0 Pipe in/out errors */ +#define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_SHFT 8 +#define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_MASK 0x0000000000000100 + +/* SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW */ +/* Description: NI1 pop overflow */ +#define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_SHFT 9 +#define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_MASK 0x0000000000000200 + +/* SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW */ +/* Description: NI1 push overflow */ +#define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_SHFT 10 +#define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400 + +/* SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW */ +/* Description: NI1 credit overflow */ +#define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_SHFT 11 +#define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800 + +/* SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW */ +/* Description: NI1 debit overflow */ +#define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_SHFT 12 +#define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000 + +/* SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW */ +/* Description: NI1 pop underflow */ +#define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_SHFT 13 +#define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_MASK 0x0000000000002000 + +/* SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW */ +/* Description: NI1 push underflow */ +#define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_SHFT 14 +#define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000 + +/* SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW */ +/* Description: NI1 credit underflow */ +#define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_SHFT 15 +#define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000 + +/* SH_XN_FIRST_ERROR_NI1_LLP_ERROR */ +/* Description: NI1 llp error */ +#define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_SHFT 16 +#define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_MASK 0x0000000000010000 + +/* SH_XN_FIRST_ERROR_NI1_PIPE_ERROR */ +/* Description: NI1 pipe in/out error */ +#define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_SHFT 17 +#define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_MASK 0x0000000000020000 + +/* SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW */ +/* Description: XNMD credit overflow */ +#define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_SHFT 18 +#define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000 + +/* SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW */ +/* Description: XNMD debit overflow */ +#define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_SHFT 19 +#define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000 + +/* SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW */ +/* Description: XNMD data buffer overflow */ +#define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_SHFT 20 +#define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000 + +/* SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW */ +/* Description: XNMD credit underflow */ +#define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_SHFT 21 +#define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000 + +/* SH_XN_FIRST_ERROR_XNMD_SBE_ERROR */ +/* Description: XNMD single bit error */ +#define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_SHFT 22 +#define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_MASK 0x0000000000400000 + +/* SH_XN_FIRST_ERROR_XNMD_UCE_ERROR */ +/* Description: XNMD uncorrectable error */ +#define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_SHFT 23 +#define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_MASK 0x0000000000800000 + +/* SH_XN_FIRST_ERROR_XNMD_LUT_ERROR */ +/* Description: XNMD look up table error */ +#define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_SHFT 24 +#define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_MASK 0x0000000001000000 + +/* SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW */ +/* Description: XNMD credit overflow */ +#define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_SHFT 25 +#define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000 + +/* SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW */ +/* Description: XNPI debit overflow */ +#define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_SHFT 26 +#define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000 + +/* SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW */ +/* Description: XNPI data buffer overflow */ +#define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_SHFT 27 +#define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000 + +/* SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW */ +/* Description: XNPI credit underflow */ +#define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_SHFT 28 +#define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000 + +/* SH_XN_FIRST_ERROR_XNPI_SBE_ERROR */ +/* Description: XNPI single bit error */ +#define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_SHFT 29 +#define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_MASK 0x0000000020000000 + +/* SH_XN_FIRST_ERROR_XNPI_UCE_ERROR */ +/* Description: XNPI uncorrectable error */ +#define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_SHFT 30 +#define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_MASK 0x0000000040000000 + +/* SH_XN_FIRST_ERROR_XNPI_LUT_ERROR */ +/* Description: XNPI look up table error */ +#define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_SHFT 31 +#define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_MASK 0x0000000080000000 + +/* SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW */ +/* Description: IILB debit overflow */ +#define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_SHFT 32 +#define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000 + +/* SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW */ +/* Description: IILB credit overflow */ +#define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_SHFT 33 +#define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000 + +/* SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW */ +/* Description: IILB fifo overflow */ +#define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_SHFT 34 +#define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000 + +/* SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW */ +/* Description: IILB credit underflow */ +#define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_SHFT 35 +#define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000 + +/* SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW */ +/* Description: IILB fifo underflow */ +#define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_SHFT 36 +#define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000 + +/* SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT */ +/* Description: IILB chiplet nomatch or lut read error */ +#define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_SHFT 37 +#define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_SUMMARY" */ +/* ==================================================================== */ + +#define SH_XNIILB_ERROR_SUMMARY 0x0000000150040200 +#define SH_XNIILB_ERROR_SUMMARY_MASK 0xffffffffffffffff +#define SH_XNIILB_ERROR_SUMMARY_INIT 0xffffffffffffffff + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0 */ +/* Description: II debit0 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_SHFT 0 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2 */ +/* Description: II debit2 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_SHFT 1 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0 */ +/* Description: LB debit0 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_SHFT 2 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2 */ +/* Description: LB debit2 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_SHFT 3 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0 */ +/* Description: II VC0 fifo overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_SHFT 4 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_MASK 0x0000000000000010 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2 */ +/* Description: II VC2 fifo overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_SHFT 5 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_MASK 0x0000000000000020 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0 */ +/* Description: II VC0 fifo underflow */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_SHFT 6 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_MASK 0x0000000000000040 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2 */ +/* Description: II VC2 fifo underflow */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_SHFT 7 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_MASK 0x0000000000000080 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0 */ +/* Description: LB VC0 fifo overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_SHFT 8 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_MASK 0x0000000000000100 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2 */ +/* Description: LB VC2 fifo overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_SHFT 9 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_MASK 0x0000000000000200 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0 */ +/* Description: LB VC0 fifo underflow */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_SHFT 10 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2 */ +/* Description: LB VC2 fifo underflow */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_SHFT 11 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN */ +/* Description: PI VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN */ +/* Description: IILB VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN */ +/* Description: MD VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN */ +/* Description: NI0 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN */ +/* Description: NI1 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN */ +/* Description: PI VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN */ +/* Description: IILB VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN */ +/* Description: MD VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN */ +/* Description: NI0 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN */ +/* Description: NI1 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN */ +/* Description: PI VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN */ +/* Description: IILB VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN */ +/* Description: MD VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN */ +/* Description: NI0 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN */ +/* Description: NI1 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN */ +/* Description: PI VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN */ +/* Description: IILB VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN */ +/* Description: MD VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN */ +/* Description: NI0 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN */ +/* Description: NI1 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0 */ +/* Description: PI Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_SHFT 32 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2 */ +/* Description: PI Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_SHFT 33 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 34 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 35 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0 */ +/* Description: MD Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_SHFT 36 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2 */ +/* Description: MD Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_SHFT 37 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 38 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 39 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 40 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 41 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 +#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 +#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_SHFT 62 +#define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_MASK 0x4000000000000000 + +/* SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 63 +#define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERRORS_ALIAS" */ +/* ==================================================================== */ + +#define SH_XNIILB_ERRORS_ALIAS 0x0000000150040208 + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_OVERFLOW" */ +/* ==================================================================== */ + +#define SH_XNIILB_ERROR_OVERFLOW 0x0000000150040220 +#define SH_XNIILB_ERROR_OVERFLOW_MASK 0xffffffffffffffff +#define SH_XNIILB_ERROR_OVERFLOW_INIT 0xffffffffffffffff + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0 */ +/* Description: II debit0 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_SHFT 0 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2 */ +/* Description: II debit2 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_SHFT 1 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0 */ +/* Description: LB debit0 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_SHFT 2 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2 */ +/* Description: LB debit2 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_SHFT 3 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0 */ +/* Description: II VC0 fifo overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_SHFT 4 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_MASK 0x0000000000000010 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2 */ +/* Description: II VC2 fifo overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_SHFT 5 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_MASK 0x0000000000000020 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0 */ +/* Description: II VC0 fifo underflow */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_SHFT 6 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_MASK 0x0000000000000040 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2 */ +/* Description: II VC2 fifo underflow */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_SHFT 7 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_MASK 0x0000000000000080 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0 */ +/* Description: LB VC0 fifo overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_SHFT 8 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_MASK 0x0000000000000100 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2 */ +/* Description: LB VC2 fifo overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_SHFT 9 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_MASK 0x0000000000000200 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0 */ +/* Description: LB VC0 fifo underflow */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_SHFT 10 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2 */ +/* Description: LB VC2 fifo underflow */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_SHFT 11 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN */ +/* Description: PI VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN */ +/* Description: IILB VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN */ +/* Description: MD VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN */ +/* Description: NI0 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN */ +/* Description: NI1 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN */ +/* Description: PI VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN */ +/* Description: IILB VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN */ +/* Description: MD VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN */ +/* Description: NI0 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN */ +/* Description: NI1 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN */ +/* Description: PI VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN */ +/* Description: IILB VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN */ +/* Description: MD VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN */ +/* Description: NI0 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN */ +/* Description: NI1 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN */ +/* Description: PI VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN */ +/* Description: IILB VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN */ +/* Description: MD VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN */ +/* Description: NI0 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN */ +/* Description: NI1 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0 */ +/* Description: PI Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_SHFT 32 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2 */ +/* Description: PI Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_SHFT 33 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 34 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 35 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0 */ +/* Description: MD Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_SHFT 36 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2 */ +/* Description: MD Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_SHFT 37 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 38 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 39 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 40 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 41 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 +#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 +#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_SHFT 62 +#define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_MASK 0x4000000000000000 + +/* SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 63 +#define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_OVERFLOW_ALIAS" */ +/* ==================================================================== */ + +#define SH_XNIILB_ERROR_OVERFLOW_ALIAS 0x0000000150040228 + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_MASK" */ +/* ==================================================================== */ + +#define SH_XNIILB_ERROR_MASK 0x0000000150040240 +#define SH_XNIILB_ERROR_MASK_MASK 0xffffffffffffffff +#define SH_XNIILB_ERROR_MASK_INIT 0xffffffffffffffff + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0 */ +/* Description: II debit0 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_SHFT 0 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2 */ +/* Description: II debit2 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_SHFT 1 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0 */ +/* Description: LB debit0 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_SHFT 2 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2 */ +/* Description: LB debit2 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_SHFT 3 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0 */ +/* Description: II VC0 fifo overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_SHFT 4 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_MASK 0x0000000000000010 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2 */ +/* Description: II VC2 fifo overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_SHFT 5 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_MASK 0x0000000000000020 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0 */ +/* Description: II VC0 fifo underflow */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_SHFT 6 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_MASK 0x0000000000000040 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2 */ +/* Description: II VC2 fifo underflow */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_SHFT 7 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_MASK 0x0000000000000080 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0 */ +/* Description: LB VC0 fifo overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_SHFT 8 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_MASK 0x0000000000000100 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2 */ +/* Description: LB VC2 fifo overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_SHFT 9 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_MASK 0x0000000000000200 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0 */ +/* Description: LB VC0 fifo underflow */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_SHFT 10 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2 */ +/* Description: LB VC2 fifo underflow */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_SHFT 11 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN */ +/* Description: PI VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN */ +/* Description: IILB VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN */ +/* Description: MD VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN */ +/* Description: NI0 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN */ +/* Description: NI1 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN */ +/* Description: PI VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN */ +/* Description: IILB VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN */ +/* Description: MD VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN */ +/* Description: NI0 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN */ +/* Description: NI1 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN */ +/* Description: PI VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN */ +/* Description: IILB VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN */ +/* Description: MD VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN */ +/* Description: NI0 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN */ +/* Description: NI1 VC0 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN */ +/* Description: PI VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN */ +/* Description: IILB VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN */ +/* Description: MD VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN */ +/* Description: NI0 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN */ +/* Description: NI1 VC2 credit overflow Pipe In */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0 */ +/* Description: PI Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_SHFT 32 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2 */ +/* Description: PI Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_SHFT 33 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 34 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 35 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0 */ +/* Description: MD Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_SHFT 36 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2 */ +/* Description: MD Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_SHFT 37 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 38 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 39 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Fifo Debit0 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 40 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Fifo Debit2 overflow */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 41 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 + +/* SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 +#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 + +/* SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 +#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 + +/* SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_SHFT 62 +#define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_MASK 0x4000000000000000 + +/* SH_XNIILB_ERROR_MASK_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_SHFT 63 +#define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNIILB_FIRST_ERROR" */ +/* ==================================================================== */ + +#define SH_XNIILB_FIRST_ERROR 0x0000000150040260 +#define SH_XNIILB_FIRST_ERROR_MASK 0xffffffffffffffff +#define SH_XNIILB_FIRST_ERROR_INIT 0xffffffffffffffff + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0 */ +/* Description: II debit0 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_SHFT 0 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2 */ +/* Description: II debit2 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_SHFT 1 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0 */ +/* Description: LB debit0 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_SHFT 2 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2 */ +/* Description: LB debit2 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_SHFT 3 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0 */ +/* Description: II VC0 fifo overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_SHFT 4 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_MASK 0x0000000000000010 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2 */ +/* Description: II VC2 fifo overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_SHFT 5 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_MASK 0x0000000000000020 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0 */ +/* Description: II VC0 fifo underflow */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_SHFT 6 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_MASK 0x0000000000000040 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2 */ +/* Description: II VC2 fifo underflow */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_SHFT 7 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_MASK 0x0000000000000080 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0 */ +/* Description: LB VC0 fifo overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_SHFT 8 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_MASK 0x0000000000000100 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2 */ +/* Description: LB VC2 fifo overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_SHFT 9 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_MASK 0x0000000000000200 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0 */ +/* Description: LB VC0 fifo underflow */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_SHFT 10 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_MASK 0x0000000000000400 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2 */ +/* Description: LB VC2 fifo underflow */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_SHFT 11 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_MASK 0x0000000000000800 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN */ +/* Description: PI VC0 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN */ +/* Description: IILB VC0 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN */ +/* Description: MD VC0 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN */ +/* Description: NI0 VC0 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN */ +/* Description: NI1 VC0 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN */ +/* Description: PI VC2 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN */ +/* Description: IILB VC2 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN */ +/* Description: MD VC2 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN */ +/* Description: NI0 VC2 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN */ +/* Description: NI1 VC2 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN */ +/* Description: PI VC0 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN */ +/* Description: IILB VC0 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN */ +/* Description: MD VC0 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN */ +/* Description: NI0 VC0 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN */ +/* Description: NI1 VC0 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN */ +/* Description: PI VC2 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN */ +/* Description: IILB VC2 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN */ +/* Description: MD VC2 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN */ +/* Description: NI0 VC2 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN */ +/* Description: NI1 VC2 credit overflow Pipe In */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0 */ +/* Description: PI Fifo Debit0 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_SHFT 32 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2 */ +/* Description: PI Fifo Debit2 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_SHFT 33 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Fifo Debit0 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 34 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Fifo Debit2 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 35 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0 */ +/* Description: MD Fifo Debit0 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_SHFT 36 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2 */ +/* Description: MD Fifo Debit2 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_SHFT 37 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Fifo Debit0 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 38 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Fifo Debit2 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 39 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Fifo Debit0 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 40 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Fifo Debit2 overflow */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 41 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000 + +/* SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51 +#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT */ +/* Description: PI VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT */ +/* Description: MD VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT */ +/* Description: IILB VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT */ +/* Description: NI0 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000 + +/* SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT */ +/* Description: NI1 VC0 Credit overflow Pipe Out */ +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61 +#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000 + +/* SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH */ +/* Description: chiplet nomatch */ +#define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_SHFT 62 +#define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_MASK 0x4000000000000000 + +/* SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_SHFT 63 +#define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XNPI_ERROR_SUMMARY" */ +/* ==================================================================== */ + +#define SH_XNPI_ERROR_SUMMARY 0x0000000150040300 +#define SH_XNPI_ERROR_SUMMARY_MASK 0x0003ffffffffffff +#define SH_XNPI_ERROR_SUMMARY_INIT 0x0003ffffffffffff + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0 */ +/* Description: VC0 Data Buffer overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2 */ +/* Description: VC2 Data Buffer overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 + +/* SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18 +#define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000 + +/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0 */ +/* Description: Single Bit Error in Bits 63:0 */ +#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19 +#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 + +/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1 */ +/* Description: Single Bit Error in Bits 127:64 */ +#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20 +#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 + +/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2 */ +/* Description: Single Bit Error in Bits 191:128 */ +#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21 +#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 + +/* SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3 */ +/* Description: Single Bit Error in Bits 255:192 */ +#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22 +#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 + +/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0 */ +/* Description: Uncorrectable Error in Bits 63:0 */ +#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_SHFT 23 +#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_MASK 0x0000000000800000 + +/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1 */ +/* Description: Uncorrectable Error in Bits 127:64 */ +#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_SHFT 24 +#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_MASK 0x0000000001000000 + +/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2 */ +/* Description: Uncorrectable Error in Bits 191:128 */ +#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_SHFT 25 +#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_MASK 0x0000000002000000 + +/* SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3 */ +/* Description: Uncorrectable Error in Bits 255:192 */ +#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_SHFT 26 +#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_MASK 0x0000000004000000 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Debit 0 Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Debit 2 Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Debit 0 Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Debit 2 Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Debit 0 Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Debit 2 Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Underflow */ +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 +#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 + +/* SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO */ +/* Description: Header Cancel Fifo Overflow */ +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 +#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 + +/* ==================================================================== */ +/* Register "SH_XNPI_ERRORS_ALIAS" */ +/* ==================================================================== */ + +#define SH_XNPI_ERRORS_ALIAS 0x0000000150040308 + +/* ==================================================================== */ +/* Register "SH_XNPI_ERROR_OVERFLOW" */ +/* ==================================================================== */ + +#define SH_XNPI_ERROR_OVERFLOW 0x0000000150040320 +#define SH_XNPI_ERROR_OVERFLOW_MASK 0x0003ffffffffffff +#define SH_XNPI_ERROR_OVERFLOW_INIT 0x0003ffffffffffff + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0 */ +/* Description: VC0 Data Buffer overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2 */ +/* Description: VC2 Data Buffer overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 + +/* SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18 +#define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000 + +/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0 */ +/* Description: Single Bit Error in Bits 63:0 */ +#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19 +#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 + +/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1 */ +/* Description: Single Bit Error in Bits 127:64 */ +#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20 +#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 + +/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2 */ +/* Description: Single Bit Error in Bits 191:128 */ +#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21 +#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 + +/* SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3 */ +/* Description: Single Bit Error in Bits 255:192 */ +#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22 +#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 + +/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0 */ +/* Description: Uncorrectable Error in Bits 63:0 */ +#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23 +#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000 + +/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1 */ +/* Description: Uncorrectable Error in Bits 127:64 */ +#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24 +#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000 + +/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2 */ +/* Description: Uncorrectable Error in Bits 191:128 */ +#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25 +#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000 + +/* SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3 */ +/* Description: Uncorrectable Error in Bits 255:192 */ +#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26 +#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Debit 0 Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Debit 2 Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Debit 0 Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Debit 2 Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Debit 0 Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Debit 2 Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Underflow */ +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 +#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 + +/* SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO */ +/* Description: Header Cancel Fifo Overflow */ +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 +#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 + +/* ==================================================================== */ +/* Register "SH_XNPI_ERROR_OVERFLOW_ALIAS" */ +/* ==================================================================== */ + +#define SH_XNPI_ERROR_OVERFLOW_ALIAS 0x0000000150040328 + +/* ==================================================================== */ +/* Register "SH_XNPI_ERROR_MASK" */ +/* ==================================================================== */ + +#define SH_XNPI_ERROR_MASK 0x0000000150040340 +#define SH_XNPI_ERROR_MASK_MASK 0x0003ffffffffffff +#define SH_XNPI_ERROR_MASK_INIT 0x0003ffffffffffff + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9 +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11 +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13 +#define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15 +#define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0 */ +/* Description: VC0 Data Buffer overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16 +#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2 */ +/* Description: VC2 Data Buffer overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17 +#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 + +/* SH_XNPI_ERROR_MASK_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_SHFT 18 +#define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_MASK 0x0000000000040000 + +/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0 */ +/* Description: Single Bit Error in Bits 63:0 */ +#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19 +#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 + +/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1 */ +/* Description: Single Bit Error in Bits 127:64 */ +#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20 +#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 + +/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2 */ +/* Description: Single Bit Error in Bits 191:128 */ +#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21 +#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 + +/* SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3 */ +/* Description: Single Bit Error in Bits 255:192 */ +#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22 +#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 + +/* SH_XNPI_ERROR_MASK_UNCOR_ERROR0 */ +/* Description: Uncorrectable Error in Bits 63:0 */ +#define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_SHFT 23 +#define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_MASK 0x0000000000800000 + +/* SH_XNPI_ERROR_MASK_UNCOR_ERROR1 */ +/* Description: Uncorrectable Error in Bits 127:64 */ +#define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_SHFT 24 +#define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_MASK 0x0000000001000000 + +/* SH_XNPI_ERROR_MASK_UNCOR_ERROR2 */ +/* Description: Uncorrectable Error in Bits 191:128 */ +#define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_SHFT 25 +#define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_MASK 0x0000000002000000 + +/* SH_XNPI_ERROR_MASK_UNCOR_ERROR3 */ +/* Description: Uncorrectable Error in Bits 255:192 */ +#define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_SHFT 26 +#define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_MASK 0x0000000004000000 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28 +#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30 +#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Debit 0 Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Debit 2 Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Debit 0 Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Debit 2 Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Debit 0 Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35 +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Debit 2 Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36 +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 +#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Underflow */ +#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 +#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 +#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 + +/* SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO */ +/* Description: Header Cancel Fifo Overflow */ +#define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 +#define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 + +/* ==================================================================== */ +/* Register "SH_XNPI_FIRST_ERROR" */ +/* ==================================================================== */ + +#define SH_XNPI_FIRST_ERROR 0x0000000150040360 +#define SH_XNPI_FIRST_ERROR_MASK 0x0003ffffffffffff +#define SH_XNPI_FIRST_ERROR_INIT 0x0003ffffffffffff + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0 */ +/* Description: VC0 Data Buffer overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2 */ +/* Description: VC2 Data Buffer overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 + +/* SH_XNPI_FIRST_ERROR_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_SHFT 18 +#define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_MASK 0x0000000000040000 + +/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0 */ +/* Description: Single Bit Error in Bits 63:0 */ +#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19 +#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 + +/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1 */ +/* Description: Single Bit Error in Bits 127:64 */ +#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20 +#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 + +/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2 */ +/* Description: Single Bit Error in Bits 191:128 */ +#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21 +#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 + +/* SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3 */ +/* Description: Single Bit Error in Bits 255:192 */ +#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22 +#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 + +/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR0 */ +/* Description: Uncorrectable Error in Bits 63:0 */ +#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_SHFT 23 +#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_MASK 0x0000000000800000 + +/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR1 */ +/* Description: Uncorrectable Error in Bits 127:64 */ +#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_SHFT 24 +#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_MASK 0x0000000001000000 + +/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR2 */ +/* Description: Uncorrectable Error in Bits 191:128 */ +#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_SHFT 25 +#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_MASK 0x0000000002000000 + +/* SH_XNPI_FIRST_ERROR_UNCOR_ERROR3 */ +/* Description: Uncorrectable Error in Bits 255:192 */ +#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_SHFT 26 +#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_MASK 0x0000000004000000 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Debit 0 Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Debit 2 Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Debit 0 Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Debit 2 Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Debit 0 Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Debit 2 Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Underflow */ +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 +#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 + +/* SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO */ +/* Description: Header Cancel Fifo Overflow */ +#define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 +#define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_ERROR_SUMMARY" */ +/* ==================================================================== */ + +#define SH_XNMD_ERROR_SUMMARY 0x0000000150040400 +#define SH_XNMD_ERROR_SUMMARY_MASK 0x0003ffffffffffff +#define SH_XNMD_ERROR_SUMMARY_INIT 0x0003ffffffffffff + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0 */ +/* Description: VC0 Data Buffer overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2 */ +/* Description: VC2 Data Buffer overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 + +/* SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18 +#define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000 + +/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0 */ +/* Description: Single Bit Error in Bits 63:0 */ +#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19 +#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 + +/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1 */ +/* Description: Single Bit Error in Bits 127:64 */ +#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20 +#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 + +/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2 */ +/* Description: Single Bit Error in Bits 191:128 */ +#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21 +#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 + +/* SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3 */ +/* Description: Single Bit Error in Bits 255:192 */ +#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22 +#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 + +/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0 */ +/* Description: Uncorrectable Error in Bits 63:0 */ +#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_SHFT 23 +#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_MASK 0x0000000000800000 + +/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1 */ +/* Description: Uncorrectable Error in Bits 127:64 */ +#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_SHFT 24 +#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_MASK 0x0000000001000000 + +/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2 */ +/* Description: Uncorrectable Error in Bits 191:128 */ +#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_SHFT 25 +#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_MASK 0x0000000002000000 + +/* SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3 */ +/* Description: Uncorrectable Error in Bits 255:192 */ +#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_SHFT 26 +#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_MASK 0x0000000004000000 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Debit 0 Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Debit 2 Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Debit 0 Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Debit 2 Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Debit 0 Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Debit 2 Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Underflow */ +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 +#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 + +/* SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO */ +/* Description: Header Cancel Fifo Overflow */ +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 +#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_ERRORS_ALIAS" */ +/* ==================================================================== */ + +#define SH_XNMD_ERRORS_ALIAS 0x0000000150040408 + +/* ==================================================================== */ +/* Register "SH_XNMD_ERROR_OVERFLOW" */ +/* ==================================================================== */ + +#define SH_XNMD_ERROR_OVERFLOW 0x0000000150040420 +#define SH_XNMD_ERROR_OVERFLOW_MASK 0x0003ffffffffffff +#define SH_XNMD_ERROR_OVERFLOW_INIT 0x0003ffffffffffff + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0 */ +/* Description: VC0 Data Buffer overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2 */ +/* Description: VC2 Data Buffer overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 + +/* SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18 +#define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000 + +/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0 */ +/* Description: Single Bit Error in Bits 63:0 */ +#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19 +#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 + +/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1 */ +/* Description: Single Bit Error in Bits 127:64 */ +#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20 +#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 + +/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2 */ +/* Description: Single Bit Error in Bits 191:128 */ +#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21 +#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 + +/* SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3 */ +/* Description: Single Bit Error in Bits 255:192 */ +#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22 +#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 + +/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0 */ +/* Description: Uncorrectable Error in Bits 63:0 */ +#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23 +#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000 + +/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1 */ +/* Description: Uncorrectable Error in Bits 127:64 */ +#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24 +#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000 + +/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2 */ +/* Description: Uncorrectable Error in Bits 191:128 */ +#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25 +#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000 + +/* SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3 */ +/* Description: Uncorrectable Error in Bits 255:192 */ +#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26 +#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Debit 0 Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Debit 2 Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Debit 0 Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Debit 2 Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Debit 0 Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Debit 2 Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Underflow */ +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 +#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 + +/* SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO */ +/* Description: Header Cancel Fifo Overflow */ +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 +#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_ERROR_OVERFLOW_ALIAS" */ +/* ==================================================================== */ + +#define SH_XNMD_ERROR_OVERFLOW_ALIAS 0x0000000150040428 + +/* ==================================================================== */ +/* Register "SH_XNMD_ERROR_MASK" */ +/* ==================================================================== */ + +#define SH_XNMD_ERROR_MASK 0x0000000150040440 +#define SH_XNMD_ERROR_MASK_MASK 0x0003ffffffffffff +#define SH_XNMD_ERROR_MASK_INIT 0x0003ffffffffffff + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9 +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11 +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13 +#define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15 +#define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0 */ +/* Description: VC0 Data Buffer overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16 +#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2 */ +/* Description: VC2 Data Buffer overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17 +#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 + +/* SH_XNMD_ERROR_MASK_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_SHFT 18 +#define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_MASK 0x0000000000040000 + +/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0 */ +/* Description: Single Bit Error in Bits 63:0 */ +#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19 +#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 + +/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1 */ +/* Description: Single Bit Error in Bits 127:64 */ +#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20 +#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 + +/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2 */ +/* Description: Single Bit Error in Bits 191:128 */ +#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21 +#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 + +/* SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3 */ +/* Description: Single Bit Error in Bits 255:192 */ +#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22 +#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 + +/* SH_XNMD_ERROR_MASK_UNCOR_ERROR0 */ +/* Description: Uncorrectable Error in Bits 63:0 */ +#define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_SHFT 23 +#define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_MASK 0x0000000000800000 + +/* SH_XNMD_ERROR_MASK_UNCOR_ERROR1 */ +/* Description: Uncorrectable Error in Bits 127:64 */ +#define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_SHFT 24 +#define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_MASK 0x0000000001000000 + +/* SH_XNMD_ERROR_MASK_UNCOR_ERROR2 */ +/* Description: Uncorrectable Error in Bits 191:128 */ +#define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_SHFT 25 +#define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_MASK 0x0000000002000000 + +/* SH_XNMD_ERROR_MASK_UNCOR_ERROR3 */ +/* Description: Uncorrectable Error in Bits 255:192 */ +#define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_SHFT 26 +#define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_MASK 0x0000000004000000 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28 +#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30 +#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Debit 0 Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Debit 2 Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Debit 0 Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Debit 2 Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Debit 0 Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35 +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Debit 2 Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36 +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 +#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Underflow */ +#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 +#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 +#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 + +/* SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO */ +/* Description: Header Cancel Fifo Overflow */ +#define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 +#define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 + +/* ==================================================================== */ +/* Register "SH_XNMD_FIRST_ERROR" */ +/* ==================================================================== */ + +#define SH_XNMD_FIRST_ERROR 0x0000000150040460 +#define SH_XNMD_FIRST_ERROR_MASK 0x0003ffffffffffff +#define SH_XNMD_FIRST_ERROR_INIT 0x0003ffffffffffff + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0 */ +/* Description: NI0 VC0 fifo overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2 */ +/* Description: NI0 VC2 fifo overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0 */ +/* Description: NI1 VC0 fifo overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2 */ +/* Description: NI1 VC2 fifo overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0 */ +/* Description: IILB VC0 fifo overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2 */ +/* Description: IILB VC2 fifo overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT */ +/* Description: VC0 Credit overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT */ +/* Description: VC2 Credit overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0 */ +/* Description: VC0 Data Buffer overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2 */ +/* Description: VC2 Data Buffer overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000 + +/* SH_XNMD_FIRST_ERROR_LUT_READ_ERROR */ +/* Description: LUT Read Error */ +#define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_SHFT 18 +#define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_MASK 0x0000000000040000 + +/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0 */ +/* Description: Single Bit Error in Bits 63:0 */ +#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19 +#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000 + +/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1 */ +/* Description: Single Bit Error in Bits 127:64 */ +#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20 +#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000 + +/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2 */ +/* Description: Single Bit Error in Bits 191:128 */ +#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21 +#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000 + +/* SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3 */ +/* Description: Single Bit Error in Bits 255:192 */ +#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22 +#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000 + +/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR0 */ +/* Description: Uncorrectable Error in Bits 63:0 */ +#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_SHFT 23 +#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_MASK 0x0000000000800000 + +/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR1 */ +/* Description: Uncorrectable Error in Bits 127:64 */ +#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_SHFT 24 +#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_MASK 0x0000000001000000 + +/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR2 */ +/* Description: Uncorrectable Error in Bits 191:128 */ +#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_SHFT 25 +#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_MASK 0x0000000002000000 + +/* SH_XNMD_FIRST_ERROR_UNCOR_ERROR3 */ +/* Description: Uncorrectable Error in Bits 255:192 */ +#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_SHFT 26 +#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_MASK 0x0000000004000000 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0 */ +/* Description: SIC Counter 0 Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2 */ +/* Description: SIC Counter 2 Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0 */ +/* Description: NI0 Debit 0 Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2 */ +/* Description: NI0 Debit 2 Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0 */ +/* Description: NI1 Debit 0 Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2 */ +/* Description: NI1 Debit 2 Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0 */ +/* Description: IILB Debit 0 Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2 */ +/* Description: IILB Debit 2 Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT */ +/* Description: NI0 VC0 Credit Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT */ +/* Description: NI0 VC2 Credit Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT */ +/* Description: NI1 VC0 Credit Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT */ +/* Description: NI1 VC2 Credit Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT */ +/* Description: IILB VC0 Credit Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000 + +/* SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Underflow */ +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47 +#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT */ +/* Description: IILB VC2 Credit Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000 + +/* SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO */ +/* Description: Header Cancel Fifo Overflow */ +#define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49 +#define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000 + +/* ==================================================================== */ +/* Register "SH_AUTO_REPLY_ENABLE0" */ +/* Automatic Maintenance Reply Enable 0 */ +/* ==================================================================== */ + +#define SH_AUTO_REPLY_ENABLE0 0x0000000110061000 +#define SH_AUTO_REPLY_ENABLE0_MASK 0xffffffffffffffff +#define SH_AUTO_REPLY_ENABLE0_INIT 0x0000000000000000 + +/* SH_AUTO_REPLY_ENABLE0_ENABLE0 */ +/* Description: Enable 0 */ +#define SH_AUTO_REPLY_ENABLE0_ENABLE0_SHFT 0 +#define SH_AUTO_REPLY_ENABLE0_ENABLE0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_AUTO_REPLY_ENABLE1" */ +/* Automatic Maintenance Reply Enable 1 */ +/* ==================================================================== */ + +#define SH_AUTO_REPLY_ENABLE1 0x0000000110061080 +#define SH_AUTO_REPLY_ENABLE1_MASK 0xffffffffffffffff +#define SH_AUTO_REPLY_ENABLE1_INIT 0x0000000000000000 + +/* SH_AUTO_REPLY_ENABLE1_ENABLE1 */ +/* Description: Enable 1 */ +#define SH_AUTO_REPLY_ENABLE1_ENABLE1_SHFT 0 +#define SH_AUTO_REPLY_ENABLE1_ENABLE1_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_AUTO_REPLY_HEADER0" */ +/* Automatic Maintenance Reply Header 0 */ +/* ==================================================================== */ + +#define SH_AUTO_REPLY_HEADER0 0x0000000110061100 +#define SH_AUTO_REPLY_HEADER0_MASK 0xffffffffffffffff +#define SH_AUTO_REPLY_HEADER0_INIT 0x0000000000000000 + +/* SH_AUTO_REPLY_HEADER0_HEADER0 */ +/* Description: Header 0 */ +#define SH_AUTO_REPLY_HEADER0_HEADER0_SHFT 0 +#define SH_AUTO_REPLY_HEADER0_HEADER0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_AUTO_REPLY_HEADER1" */ +/* Automatic Maintenance Reply Header 1 */ +/* ==================================================================== */ + +#define SH_AUTO_REPLY_HEADER1 0x0000000110061180 +#define SH_AUTO_REPLY_HEADER1_MASK 0xffffffffffffffff +#define SH_AUTO_REPLY_HEADER1_INIT 0x0000000000000000 + +/* SH_AUTO_REPLY_HEADER1_HEADER1 */ +/* Description: Header 1 */ +#define SH_AUTO_REPLY_HEADER1_HEADER1_SHFT 0 +#define SH_AUTO_REPLY_HEADER1_HEADER1_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_ENABLE_RP_AUTO_REPLY" */ +/* Enable Automatic Maintenance Reply From Reply Queue */ +/* ==================================================================== */ + +#define SH_ENABLE_RP_AUTO_REPLY 0x0000000110061200 +#define SH_ENABLE_RP_AUTO_REPLY_MASK 0x0000000000000001 +#define SH_ENABLE_RP_AUTO_REPLY_INIT 0x0000000000000000 + +/* SH_ENABLE_RP_AUTO_REPLY_ENABLE */ +/* Description: Enable Reply Auto Reply */ +#define SH_ENABLE_RP_AUTO_REPLY_ENABLE_SHFT 0 +#define SH_ENABLE_RP_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_ENABLE_RQ_AUTO_REPLY" */ +/* Enable Automatic Maintenance Reply From Request Queue */ +/* ==================================================================== */ + +#define SH_ENABLE_RQ_AUTO_REPLY 0x0000000110061280 +#define SH_ENABLE_RQ_AUTO_REPLY_MASK 0x0000000000000001 +#define SH_ENABLE_RQ_AUTO_REPLY_INIT 0x0000000000000000 + +/* SH_ENABLE_RQ_AUTO_REPLY_ENABLE */ +/* Description: Enable Request Auto Reply */ +#define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_SHFT 0 +#define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_REDIRECT_INVAL" */ +/* Redirect invalidate to LB instead of PI */ +/* ==================================================================== */ + +#define SH_REDIRECT_INVAL 0x0000000110061300 +#define SH_REDIRECT_INVAL_MASK 0x0000000000000001 +#define SH_REDIRECT_INVAL_INIT 0x0000000000000000 + +/* SH_REDIRECT_INVAL_REDIRECT */ +/* Description: Redirect invalidates to LB instead of PI */ +#define SH_REDIRECT_INVAL_REDIRECT_SHFT 0 +#define SH_REDIRECT_INVAL_REDIRECT_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_CNTRL" */ +/* Diagnostic Message Control Register */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_CNTRL 0x0000000110062000 +#define SH_DIAG_MSG_CNTRL_MASK 0xc000000000003fff +#define SH_DIAG_MSG_CNTRL_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_CNTRL_MSG_LENGTH */ +/* Description: Message data payload length, 0 - 63 */ +#define SH_DIAG_MSG_CNTRL_MSG_LENGTH_SHFT 0 +#define SH_DIAG_MSG_CNTRL_MSG_LENGTH_MASK 0x000000000000003f + +/* SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT */ +/* Description: Point message that the error bit would be activated */ +#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_SHFT 6 +#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_MASK 0x0000000000000fc0 + +/* SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE */ +/* Description: Enable ERROR_INJECT_POINT field */ +#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_SHFT 12 +#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_MASK 0x0000000000001000 + +/* SH_DIAG_MSG_CNTRL_PORT */ +/* Description: 0 = request port, 1 = reply port */ +#define SH_DIAG_MSG_CNTRL_PORT_SHFT 13 +#define SH_DIAG_MSG_CNTRL_PORT_MASK 0x0000000000002000 + +/* SH_DIAG_MSG_CNTRL_START */ +/* Description: Start */ +#define SH_DIAG_MSG_CNTRL_START_SHFT 62 +#define SH_DIAG_MSG_CNTRL_START_MASK 0x4000000000000000 + +/* SH_DIAG_MSG_CNTRL_BUSY */ +/* Description: Busy */ +#define SH_DIAG_MSG_CNTRL_BUSY_SHFT 63 +#define SH_DIAG_MSG_CNTRL_BUSY_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA0L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA0L 0x0000000110062080 +#define SH_DIAG_MSG_DATA0L_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA0L_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA0L_DATA_LOWER */ +/* Description: Lower 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA0L_DATA_LOWER_SHFT 0 +#define SH_DIAG_MSG_DATA0L_DATA_LOWER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA0U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA0U 0x0000000110062100 +#define SH_DIAG_MSG_DATA0U_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA0U_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA0U_DATA_UPPER */ +/* Description: Upper 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA0U_DATA_UPPER_SHFT 0 +#define SH_DIAG_MSG_DATA0U_DATA_UPPER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA1L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA1L 0x0000000110062180 +#define SH_DIAG_MSG_DATA1L_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA1L_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA1L_DATA_LOWER */ +/* Description: Lower 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA1L_DATA_LOWER_SHFT 0 +#define SH_DIAG_MSG_DATA1L_DATA_LOWER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA1U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA1U 0x0000000110062200 +#define SH_DIAG_MSG_DATA1U_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA1U_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA1U_DATA_UPPER */ +/* Description: Upper 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA1U_DATA_UPPER_SHFT 0 +#define SH_DIAG_MSG_DATA1U_DATA_UPPER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA2L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA2L 0x0000000110062280 +#define SH_DIAG_MSG_DATA2L_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA2L_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA2L_DATA_LOWER */ +/* Description: Lower 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA2L_DATA_LOWER_SHFT 0 +#define SH_DIAG_MSG_DATA2L_DATA_LOWER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA2U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA2U 0x0000000110062300 +#define SH_DIAG_MSG_DATA2U_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA2U_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA2U_DATA_UPPER */ +/* Description: Upper 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA2U_DATA_UPPER_SHFT 0 +#define SH_DIAG_MSG_DATA2U_DATA_UPPER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA3L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA3L 0x0000000110062380 +#define SH_DIAG_MSG_DATA3L_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA3L_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA3L_DATA_LOWER */ +/* Description: Lower 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA3L_DATA_LOWER_SHFT 0 +#define SH_DIAG_MSG_DATA3L_DATA_LOWER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA3U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA3U 0x0000000110062400 +#define SH_DIAG_MSG_DATA3U_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA3U_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA3U_DATA_UPPER */ +/* Description: Upper 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA3U_DATA_UPPER_SHFT 0 +#define SH_DIAG_MSG_DATA3U_DATA_UPPER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA4L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA4L 0x0000000110062480 +#define SH_DIAG_MSG_DATA4L_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA4L_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA4L_DATA_LOWER */ +/* Description: Lower 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA4L_DATA_LOWER_SHFT 0 +#define SH_DIAG_MSG_DATA4L_DATA_LOWER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA4U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA4U 0x0000000110062500 +#define SH_DIAG_MSG_DATA4U_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA4U_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA4U_DATA_UPPER */ +/* Description: Upper 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA4U_DATA_UPPER_SHFT 0 +#define SH_DIAG_MSG_DATA4U_DATA_UPPER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA5L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA5L 0x0000000110062580 +#define SH_DIAG_MSG_DATA5L_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA5L_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA5L_DATA_LOWER */ +/* Description: Lower 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA5L_DATA_LOWER_SHFT 0 +#define SH_DIAG_MSG_DATA5L_DATA_LOWER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA5U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA5U 0x0000000110062600 +#define SH_DIAG_MSG_DATA5U_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA5U_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA5U_DATA_UPPER */ +/* Description: Upper 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA5U_DATA_UPPER_SHFT 0 +#define SH_DIAG_MSG_DATA5U_DATA_UPPER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA6L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA6L 0x0000000110062680 +#define SH_DIAG_MSG_DATA6L_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA6L_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA6L_DATA_LOWER */ +/* Description: Lower 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA6L_DATA_LOWER_SHFT 0 +#define SH_DIAG_MSG_DATA6L_DATA_LOWER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA6U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA6U 0x0000000110062700 +#define SH_DIAG_MSG_DATA6U_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA6U_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA6U_DATA_UPPER */ +/* Description: Upper 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA6U_DATA_UPPER_SHFT 0 +#define SH_DIAG_MSG_DATA6U_DATA_UPPER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA7L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA7L 0x0000000110062780 +#define SH_DIAG_MSG_DATA7L_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA7L_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA7L_DATA_LOWER */ +/* Description: Lower 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA7L_DATA_LOWER_SHFT 0 +#define SH_DIAG_MSG_DATA7L_DATA_LOWER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA7U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA7U 0x0000000110062800 +#define SH_DIAG_MSG_DATA7U_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA7U_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA7U_DATA_UPPER */ +/* Description: Upper 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA7U_DATA_UPPER_SHFT 0 +#define SH_DIAG_MSG_DATA7U_DATA_UPPER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA8L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA8L 0x0000000110062880 +#define SH_DIAG_MSG_DATA8L_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA8L_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA8L_DATA_LOWER */ +/* Description: Lower 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA8L_DATA_LOWER_SHFT 0 +#define SH_DIAG_MSG_DATA8L_DATA_LOWER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA8U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_DATA8U 0x0000000110062900 +#define SH_DIAG_MSG_DATA8U_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_DATA8U_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_DATA8U_DATA_UPPER */ +/* Description: Upper 64 bits of Diagnositic Message Data */ +#define SH_DIAG_MSG_DATA8U_DATA_UPPER_SHFT 0 +#define SH_DIAG_MSG_DATA8U_DATA_UPPER_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_HDR0" */ +/* Diagnostice Data, lower 64 bits of header */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_HDR0 0x0000000110062980 +#define SH_DIAG_MSG_HDR0_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_HDR0_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_HDR0_HEADER0 */ +/* Description: Lower 64 bits of Diagnositic Message Header */ +#define SH_DIAG_MSG_HDR0_HEADER0_SHFT 0 +#define SH_DIAG_MSG_HDR0_HEADER0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_HDR1" */ +/* Diagnostice Data, upper 64 bits of header */ +/* ==================================================================== */ + +#define SH_DIAG_MSG_HDR1 0x0000000110062a00 +#define SH_DIAG_MSG_HDR1_MASK 0xffffffffffffffff +#define SH_DIAG_MSG_HDR1_INIT 0x0000000000000000 + +/* SH_DIAG_MSG_HDR1_HEADER1 */ +/* Description: Upper 64 bits of Diagnositic Message Header */ +#define SH_DIAG_MSG_HDR1_HEADER1_SHFT 0 +#define SH_DIAG_MSG_HDR1_HEADER1_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_DEBUG_SELECT" */ +/* SHub Debug Port Select */ +/* ==================================================================== */ + +#define SH_DEBUG_SELECT 0x0000000110063000 +#define SH_DEBUG_SELECT_MASK 0x8fffffffffffffff +#define SH_DEBUG_SELECT_INIT 0x0000e38e38e38e38 + +/* SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble0_nibble_select */ +#define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 0 +#define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000007 + +/* SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL */ +/* Description: Nibble0_chiplet_select */ +#define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 3 +#define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000038 + +/* SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble1_nibble_select */ +#define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 6 +#define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x00000000000001c0 + +/* SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL */ +/* Description: Nibble1_chiplet_select */ +#define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 9 +#define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000e00 + +/* SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble2_nibble_select */ +#define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 12 +#define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL */ +/* Description: Nibble2_chiplet_select */ +#define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 15 +#define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000038000 + +/* SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble3_nibble_select */ +#define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 18 +#define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x00000000001c0000 + +/* SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL */ +/* Description: Nibble3_chiplet_select */ +#define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 21 +#define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000000e00000 + +/* SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble4_nibble_select */ +#define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 24 +#define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000000007000000 + +/* SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL */ +/* Description: Nibble4_chiplet_select */ +#define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 27 +#define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000038000000 + +/* SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble5_nibble_select */ +#define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 30 +#define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x00000001c0000000 + +/* SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL */ +/* Description: Nibble5_chiplet_select */ +#define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 33 +#define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000000e00000000 + +/* SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble6_nibble_select */ +#define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 36 +#define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL */ +/* Description: Nibble6_chiplet_select */ +#define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 39 +#define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0000038000000000 + +/* SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble7_nibble_select */ +#define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 42 +#define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x00001c0000000000 + +/* SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL */ +/* Description: Nibble7_chiplet_select */ +#define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 45 +#define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0000e00000000000 + +/* SH_DEBUG_SELECT_DEBUG_II_SEL */ +/* Description: Select bits to II port */ +#define SH_DEBUG_SELECT_DEBUG_II_SEL_SHFT 48 +#define SH_DEBUG_SELECT_DEBUG_II_SEL_MASK 0x0007000000000000 + +/* SH_DEBUG_SELECT_SEL_II */ +/* Description: Select II to debug port */ +#define SH_DEBUG_SELECT_SEL_II_SHFT 51 +#define SH_DEBUG_SELECT_SEL_II_MASK 0x0ff8000000000000 + +/* SH_DEBUG_SELECT_TRIGGER_ENABLE */ +/* Description: Enable trigger on bit 32 of Analyzer data */ +#define SH_DEBUG_SELECT_TRIGGER_ENABLE_SHFT 63 +#define SH_DEBUG_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_TRIGGER_COMPARE_MASK" */ +/* SHub Trigger Compare Mask */ +/* ==================================================================== */ + +#define SH_TRIGGER_COMPARE_MASK 0x0000000110063080 +#define SH_TRIGGER_COMPARE_MASK_MASK 0x00000000ffffffff +#define SH_TRIGGER_COMPARE_MASK_INIT 0x0000000000000000 + +/* SH_TRIGGER_COMPARE_MASK_MASK */ +/* Description: SHub Trigger Compare Mask */ +#define SH_TRIGGER_COMPARE_MASK_MASK_SHFT 0 +#define SH_TRIGGER_COMPARE_MASK_MASK_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_TRIGGER_COMPARE_PATTERN" */ +/* SHub Trigger Compare Pattern */ +/* ==================================================================== */ + +#define SH_TRIGGER_COMPARE_PATTERN 0x0000000110063100 +#define SH_TRIGGER_COMPARE_PATTERN_MASK 0x00000000ffffffff +#define SH_TRIGGER_COMPARE_PATTERN_INIT 0x0000000000000000 + +/* SH_TRIGGER_COMPARE_PATTERN_DATA */ +/* Description: SHub Trigger Compare Pattern */ +#define SH_TRIGGER_COMPARE_PATTERN_DATA_SHFT 0 +#define SH_TRIGGER_COMPARE_PATTERN_DATA_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_TRIGGER_SEL" */ +/* Trigger select for SHUB debug port */ +/* ==================================================================== */ + +#define SH_TRIGGER_SEL 0x0000000110063180 +#define SH_TRIGGER_SEL_MASK 0x7777777777777777 +#define SH_TRIGGER_SEL_INIT 0x0000000000000000 + +/* SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL */ +/* Description: Nibble 0 input select */ +#define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_SHFT 0 +#define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007 + +/* SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL */ +/* Description: Nibble 0 Nibble select */ +#define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4 +#define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070 + +/* SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL */ +/* Description: Nibble 1 input select */ +#define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_SHFT 8 +#define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700 + +/* SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL */ +/* Description: Nibble 1 Nibble select */ +#define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12 +#define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000 + +/* SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL */ +/* Description: Nibble 2 input select */ +#define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_SHFT 16 +#define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000 + +/* SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL */ +/* Description: Nibble 2 Nibble select */ +#define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20 +#define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000 + +/* SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL */ +/* Description: Nibble 3 input select */ +#define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_SHFT 24 +#define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000 + +/* SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL */ +/* Description: Nibble 3 Nibble select */ +#define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28 +#define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000 + +/* SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL */ +/* Description: Nibble 4 input select */ +#define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_SHFT 32 +#define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000 + +/* SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL */ +/* Description: Nibble 4 Nibble select */ +#define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36 +#define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000 + +/* SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL */ +/* Description: Nibble 5 input select */ +#define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_SHFT 40 +#define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000 + +/* SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL */ +/* Description: Nibble 5 Nibble select */ +#define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44 +#define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000 + +/* SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL */ +/* Description: Nibble 6 input select */ +#define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_SHFT 48 +#define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000 + +/* SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL */ +/* Description: Nibble 6 Nibble select */ +#define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52 +#define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000 + +/* SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL */ +/* Description: Nibble 7 input select */ +#define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_SHFT 56 +#define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000 + +/* SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL */ +/* Description: Nibble 7 Nibble select */ +#define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60 +#define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_STOP_CLK_CONTROL" */ +/* Stop Clock Control */ +/* ==================================================================== */ + +#define SH_STOP_CLK_CONTROL 0x0000000110064000 +#define SH_STOP_CLK_CONTROL_MASK 0x00000000000000ff +#define SH_STOP_CLK_CONTROL_INIT 0x00000000000000e0 + +/* SH_STOP_CLK_CONTROL_STIMULUS */ +/* Description: Counter stimulus */ +#define SH_STOP_CLK_CONTROL_STIMULUS_SHFT 0 +#define SH_STOP_CLK_CONTROL_STIMULUS_MASK 0x000000000000001f + +/* SH_STOP_CLK_CONTROL_EVENT */ +/* Description: Counter event select (0-greater than, 1-equal) */ +#define SH_STOP_CLK_CONTROL_EVENT_SHFT 5 +#define SH_STOP_CLK_CONTROL_EVENT_MASK 0x0000000000000020 + +/* SH_STOP_CLK_CONTROL_POLARITY */ +/* Description: Counter polarity select (0-negative edge, 1-positiv */ +/* e edge) */ +#define SH_STOP_CLK_CONTROL_POLARITY_SHFT 6 +#define SH_STOP_CLK_CONTROL_POLARITY_MASK 0x0000000000000040 + +/* SH_STOP_CLK_CONTROL_MODE */ +/* Description: Counter mode select (0-internal, 1-external) */ +#define SH_STOP_CLK_CONTROL_MODE_SHFT 7 +#define SH_STOP_CLK_CONTROL_MODE_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_STOP_CLK_DELAY_PHASE" */ +/* Stop Clock Delay Phase */ +/* ==================================================================== */ + +#define SH_STOP_CLK_DELAY_PHASE 0x0000000110064080 +#define SH_STOP_CLK_DELAY_PHASE_MASK 0x00000000000000ff +#define SH_STOP_CLK_DELAY_PHASE_INIT 0x0000000000000000 + +/* SH_STOP_CLK_DELAY_PHASE_DELAY */ +/* Description: Delay phase */ +#define SH_STOP_CLK_DELAY_PHASE_DELAY_SHFT 0 +#define SH_STOP_CLK_DELAY_PHASE_DELAY_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_TSF_ARM_MASK" */ +/* Trigger sequencing facility arm mask */ +/* ==================================================================== */ + +#define SH_TSF_ARM_MASK 0x0000000110065000 +#define SH_TSF_ARM_MASK_MASK 0xffffffffffffffff +#define SH_TSF_ARM_MASK_INIT 0x0000000000000000 + +/* SH_TSF_ARM_MASK_MASK */ +/* Description: Trigger sequencing facility arm mask */ +#define SH_TSF_ARM_MASK_MASK_SHFT 0 +#define SH_TSF_ARM_MASK_MASK_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_TSF_COUNTER_PRESETS" */ +/* Trigger sequencing facility counter presets */ +/* ==================================================================== */ + +#define SH_TSF_COUNTER_PRESETS 0x0000000110065080 +#define SH_TSF_COUNTER_PRESETS_MASK 0xffffffffffffffff +#define SH_TSF_COUNTER_PRESETS_INIT 0x0000000000000000 + +/* SH_TSF_COUNTER_PRESETS_COUNT_32 */ +/* Description: Trigger sequencing facility counter 32 */ +#define SH_TSF_COUNTER_PRESETS_COUNT_32_SHFT 0 +#define SH_TSF_COUNTER_PRESETS_COUNT_32_MASK 0x00000000ffffffff + +/* SH_TSF_COUNTER_PRESETS_COUNT_16 */ +/* Description: Trigger sequencing facility counter 16 */ +#define SH_TSF_COUNTER_PRESETS_COUNT_16_SHFT 32 +#define SH_TSF_COUNTER_PRESETS_COUNT_16_MASK 0x0000ffff00000000 + +/* SH_TSF_COUNTER_PRESETS_COUNT_8B */ +/* Description: Trigger sequencing facility counter 8b */ +#define SH_TSF_COUNTER_PRESETS_COUNT_8B_SHFT 48 +#define SH_TSF_COUNTER_PRESETS_COUNT_8B_MASK 0x00ff000000000000 + +/* SH_TSF_COUNTER_PRESETS_COUNT_8A */ +/* Description: Trigger sequencing facility counter 8a */ +#define SH_TSF_COUNTER_PRESETS_COUNT_8A_SHFT 56 +#define SH_TSF_COUNTER_PRESETS_COUNT_8A_MASK 0xff00000000000000 + +/* ==================================================================== */ +/* Register "SH_TSF_DECREMENT_CTL" */ +/* Trigger sequencing facility counter decrement control */ +/* ==================================================================== */ + +#define SH_TSF_DECREMENT_CTL 0x0000000110065100 +#define SH_TSF_DECREMENT_CTL_MASK 0x000000000000ffff +#define SH_TSF_DECREMENT_CTL_INIT 0x0000000000000000 + +/* SH_TSF_DECREMENT_CTL_CTL */ +/* Description: Trigger sequencing facility counter decrement contr */ +#define SH_TSF_DECREMENT_CTL_CTL_SHFT 0 +#define SH_TSF_DECREMENT_CTL_CTL_MASK 0x000000000000ffff + +/* ==================================================================== */ +/* Register "SH_TSF_DIAG_MSG_CTL" */ +/* Trigger sequencing facility diagnostic message control */ +/* ==================================================================== */ + +#define SH_TSF_DIAG_MSG_CTL 0x0000000110065180 +#define SH_TSF_DIAG_MSG_CTL_MASK 0x00000000000000ff +#define SH_TSF_DIAG_MSG_CTL_INIT 0x0000000000000000 + +/* SH_TSF_DIAG_MSG_CTL_ENABLE */ +/* Description: Trigger sequencing facility diagnostic message cont */ +#define SH_TSF_DIAG_MSG_CTL_ENABLE_SHFT 0 +#define SH_TSF_DIAG_MSG_CTL_ENABLE_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_TSF_DISARM_MASK" */ +/* Trigger sequencing facility disarm mask */ +/* ==================================================================== */ + +#define SH_TSF_DISARM_MASK 0x0000000110065200 +#define SH_TSF_DISARM_MASK_MASK 0xffffffffffffffff +#define SH_TSF_DISARM_MASK_INIT 0x0000000000000000 + +/* SH_TSF_DISARM_MASK_MASK */ +/* Description: Trigger sequencing facility disarm mask */ +#define SH_TSF_DISARM_MASK_MASK_SHFT 0 +#define SH_TSF_DISARM_MASK_MASK_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_TSF_ENABLE_CTL" */ +/* Trigger sequencing facility counter enable control */ +/* ==================================================================== */ + +#define SH_TSF_ENABLE_CTL 0x0000000110065280 +#define SH_TSF_ENABLE_CTL_MASK 0x000000000000ffff +#define SH_TSF_ENABLE_CTL_INIT 0x0000000000000000 + +/* SH_TSF_ENABLE_CTL_CTL */ +/* Description: Trigger sequencing facility counter enable control */ +#define SH_TSF_ENABLE_CTL_CTL_SHFT 0 +#define SH_TSF_ENABLE_CTL_CTL_MASK 0x000000000000ffff + +/* ==================================================================== */ +/* Register "SH_TSF_SOFTWARE_ARM" */ +/* Trigger sequencing facility software arm */ +/* ==================================================================== */ + +#define SH_TSF_SOFTWARE_ARM 0x0000000110065300 +#define SH_TSF_SOFTWARE_ARM_MASK 0x00000000000000ff +#define SH_TSF_SOFTWARE_ARM_INIT 0x0000000000000000 + +/* SH_TSF_SOFTWARE_ARM_BIT0 */ +/* Description: Trigger sequencing facility software arm bit 0 */ +#define SH_TSF_SOFTWARE_ARM_BIT0_SHFT 0 +#define SH_TSF_SOFTWARE_ARM_BIT0_MASK 0x0000000000000001 + +/* SH_TSF_SOFTWARE_ARM_BIT1 */ +/* Description: Trigger sequencing facility software arm bit 1 */ +#define SH_TSF_SOFTWARE_ARM_BIT1_SHFT 1 +#define SH_TSF_SOFTWARE_ARM_BIT1_MASK 0x0000000000000002 + +/* SH_TSF_SOFTWARE_ARM_BIT2 */ +/* Description: Trigger sequencing facility software arm bit 2 */ +#define SH_TSF_SOFTWARE_ARM_BIT2_SHFT 2 +#define SH_TSF_SOFTWARE_ARM_BIT2_MASK 0x0000000000000004 + +/* SH_TSF_SOFTWARE_ARM_BIT3 */ +/* Description: Trigger sequencing facility software arm bit 3 */ +#define SH_TSF_SOFTWARE_ARM_BIT3_SHFT 3 +#define SH_TSF_SOFTWARE_ARM_BIT3_MASK 0x0000000000000008 + +/* SH_TSF_SOFTWARE_ARM_BIT4 */ +/* Description: Trigger sequencing facility software arm bit 4 */ +#define SH_TSF_SOFTWARE_ARM_BIT4_SHFT 4 +#define SH_TSF_SOFTWARE_ARM_BIT4_MASK 0x0000000000000010 + +/* SH_TSF_SOFTWARE_ARM_BIT5 */ +/* Description: Trigger sequencing facility software arm bit 5 */ +#define SH_TSF_SOFTWARE_ARM_BIT5_SHFT 5 +#define SH_TSF_SOFTWARE_ARM_BIT5_MASK 0x0000000000000020 + +/* SH_TSF_SOFTWARE_ARM_BIT6 */ +/* Description: Trigger sequencing facility software arm bit 6 */ +#define SH_TSF_SOFTWARE_ARM_BIT6_SHFT 6 +#define SH_TSF_SOFTWARE_ARM_BIT6_MASK 0x0000000000000040 + +/* SH_TSF_SOFTWARE_ARM_BIT7 */ +/* Description: Trigger sequencing facility software arm bit 7 */ +#define SH_TSF_SOFTWARE_ARM_BIT7_SHFT 7 +#define SH_TSF_SOFTWARE_ARM_BIT7_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_TSF_SOFTWARE_DISARM" */ +/* Trigger sequencing facility software disarm */ +/* ==================================================================== */ + +#define SH_TSF_SOFTWARE_DISARM 0x0000000110065380 +#define SH_TSF_SOFTWARE_DISARM_MASK 0x00000000000000ff +#define SH_TSF_SOFTWARE_DISARM_INIT 0x0000000000000000 + +/* SH_TSF_SOFTWARE_DISARM_BIT0 */ +/* Description: Trigger sequencing facility software disarm bit 0 */ +#define SH_TSF_SOFTWARE_DISARM_BIT0_SHFT 0 +#define SH_TSF_SOFTWARE_DISARM_BIT0_MASK 0x0000000000000001 + +/* SH_TSF_SOFTWARE_DISARM_BIT1 */ +/* Description: Trigger sequencing facility software disarm bit 1 */ +#define SH_TSF_SOFTWARE_DISARM_BIT1_SHFT 1 +#define SH_TSF_SOFTWARE_DISARM_BIT1_MASK 0x0000000000000002 + +/* SH_TSF_SOFTWARE_DISARM_BIT2 */ +/* Description: Trigger sequencing facility software disarm bit 2 */ +#define SH_TSF_SOFTWARE_DISARM_BIT2_SHFT 2 +#define SH_TSF_SOFTWARE_DISARM_BIT2_MASK 0x0000000000000004 + +/* SH_TSF_SOFTWARE_DISARM_BIT3 */ +/* Description: Trigger sequencing facility software disarm bit 3 */ +#define SH_TSF_SOFTWARE_DISARM_BIT3_SHFT 3 +#define SH_TSF_SOFTWARE_DISARM_BIT3_MASK 0x0000000000000008 + +/* SH_TSF_SOFTWARE_DISARM_BIT4 */ +/* Description: Trigger sequencing facility software disarm bit 4 */ +#define SH_TSF_SOFTWARE_DISARM_BIT4_SHFT 4 +#define SH_TSF_SOFTWARE_DISARM_BIT4_MASK 0x0000000000000010 + +/* SH_TSF_SOFTWARE_DISARM_BIT5 */ +/* Description: Trigger sequencing facility software disarm bit 5 */ +#define SH_TSF_SOFTWARE_DISARM_BIT5_SHFT 5 +#define SH_TSF_SOFTWARE_DISARM_BIT5_MASK 0x0000000000000020 + +/* SH_TSF_SOFTWARE_DISARM_BIT6 */ +/* Description: Trigger sequencing facility software disarm bit 6 */ +#define SH_TSF_SOFTWARE_DISARM_BIT6_SHFT 6 +#define SH_TSF_SOFTWARE_DISARM_BIT6_MASK 0x0000000000000040 + +/* SH_TSF_SOFTWARE_DISARM_BIT7 */ +/* Description: Trigger sequencing facility software disarm bit 7 */ +#define SH_TSF_SOFTWARE_DISARM_BIT7_SHFT 7 +#define SH_TSF_SOFTWARE_DISARM_BIT7_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_TSF_SOFTWARE_TRIGGERED" */ +/* Trigger sequencing facility software triggered */ +/* ==================================================================== */ + +#define SH_TSF_SOFTWARE_TRIGGERED 0x0000000110065400 +#define SH_TSF_SOFTWARE_TRIGGERED_MASK 0x00000000000000ff +#define SH_TSF_SOFTWARE_TRIGGERED_INIT 0x0000000000000000 + +/* SH_TSF_SOFTWARE_TRIGGERED_BIT0 */ +/* Description: Trigger sequencing facility software triggered bit */ +#define SH_TSF_SOFTWARE_TRIGGERED_BIT0_SHFT 0 +#define SH_TSF_SOFTWARE_TRIGGERED_BIT0_MASK 0x0000000000000001 + +/* SH_TSF_SOFTWARE_TRIGGERED_BIT1 */ +/* Description: Trigger sequencing facility software triggered bit */ +#define SH_TSF_SOFTWARE_TRIGGERED_BIT1_SHFT 1 +#define SH_TSF_SOFTWARE_TRIGGERED_BIT1_MASK 0x0000000000000002 + +/* SH_TSF_SOFTWARE_TRIGGERED_BIT2 */ +/* Description: Trigger sequencing facility software triggered bit */ +#define SH_TSF_SOFTWARE_TRIGGERED_BIT2_SHFT 2 +#define SH_TSF_SOFTWARE_TRIGGERED_BIT2_MASK 0x0000000000000004 + +/* SH_TSF_SOFTWARE_TRIGGERED_BIT3 */ +/* Description: Trigger sequencing facility software triggered bit */ +#define SH_TSF_SOFTWARE_TRIGGERED_BIT3_SHFT 3 +#define SH_TSF_SOFTWARE_TRIGGERED_BIT3_MASK 0x0000000000000008 + +/* SH_TSF_SOFTWARE_TRIGGERED_BIT4 */ +/* Description: Trigger sequencing facility software triggered bit */ +#define SH_TSF_SOFTWARE_TRIGGERED_BIT4_SHFT 4 +#define SH_TSF_SOFTWARE_TRIGGERED_BIT4_MASK 0x0000000000000010 + +/* SH_TSF_SOFTWARE_TRIGGERED_BIT5 */ +/* Description: Trigger sequencing facility software triggered bit */ +#define SH_TSF_SOFTWARE_TRIGGERED_BIT5_SHFT 5 +#define SH_TSF_SOFTWARE_TRIGGERED_BIT5_MASK 0x0000000000000020 + +/* SH_TSF_SOFTWARE_TRIGGERED_BIT6 */ +/* Description: Trigger sequencing facility software triggered bit */ +#define SH_TSF_SOFTWARE_TRIGGERED_BIT6_SHFT 6 +#define SH_TSF_SOFTWARE_TRIGGERED_BIT6_MASK 0x0000000000000040 + +/* SH_TSF_SOFTWARE_TRIGGERED_BIT7 */ +/* Description: Trigger sequencing facility software triggered bit */ +#define SH_TSF_SOFTWARE_TRIGGERED_BIT7_SHFT 7 +#define SH_TSF_SOFTWARE_TRIGGERED_BIT7_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_TSF_TRIGGER_MASK" */ +/* Trigger sequencing facility trigger mask */ +/* ==================================================================== */ + +#define SH_TSF_TRIGGER_MASK 0x0000000110065480 +#define SH_TSF_TRIGGER_MASK_MASK 0xffffffffffffffff +#define SH_TSF_TRIGGER_MASK_INIT 0x0000000000000000 + +/* SH_TSF_TRIGGER_MASK_MASK */ +/* Description: Trigger sequencing facility trigger mask */ +#define SH_TSF_TRIGGER_MASK_MASK_SHFT 0 +#define SH_TSF_TRIGGER_MASK_MASK_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_VEC_DATA" */ +/* Vector Write Request Message Data */ +/* ==================================================================== */ + +#define SH_VEC_DATA 0x0000000110066000 +#define SH_VEC_DATA_MASK 0xffffffffffffffff +#define SH_VEC_DATA_INIT 0x0000000000000000 + +/* SH_VEC_DATA_DATA */ +/* Description: Data */ +#define SH_VEC_DATA_DATA_SHFT 0 +#define SH_VEC_DATA_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_VEC_PARMS" */ +/* Vector Message Parameters Register */ +/* ==================================================================== */ + +#define SH_VEC_PARMS 0x0000000110066080 +#define SH_VEC_PARMS_MASK 0xc0003ffffffffffb +#define SH_VEC_PARMS_INIT 0x0000000000000000 + +/* SH_VEC_PARMS_TYPE */ +/* Description: Vector Request Message Type */ +#define SH_VEC_PARMS_TYPE_SHFT 0 +#define SH_VEC_PARMS_TYPE_MASK 0x0000000000000001 + +/* SH_VEC_PARMS_NI_PORT */ +/* Description: Network Interface Port Select */ +#define SH_VEC_PARMS_NI_PORT_SHFT 1 +#define SH_VEC_PARMS_NI_PORT_MASK 0x0000000000000002 + +/* SH_VEC_PARMS_ADDRESS */ +/* Description: Address[37:6] */ +#define SH_VEC_PARMS_ADDRESS_SHFT 3 +#define SH_VEC_PARMS_ADDRESS_MASK 0x00000007fffffff8 + +/* SH_VEC_PARMS_PIO_ID */ +/* Description: PIO ID */ +#define SH_VEC_PARMS_PIO_ID_SHFT 35 +#define SH_VEC_PARMS_PIO_ID_MASK 0x00003ff800000000 + +/* SH_VEC_PARMS_START */ +/* Description: Start */ +#define SH_VEC_PARMS_START_SHFT 62 +#define SH_VEC_PARMS_START_MASK 0x4000000000000000 + +/* SH_VEC_PARMS_BUSY */ +/* Description: Busy */ +#define SH_VEC_PARMS_BUSY_SHFT 63 +#define SH_VEC_PARMS_BUSY_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_VEC_ROUTE" */ +/* Vector Request Message Route */ +/* ==================================================================== */ + +#define SH_VEC_ROUTE 0x0000000110066100 +#define SH_VEC_ROUTE_MASK 0xffffffffffffffff +#define SH_VEC_ROUTE_INIT 0x0000000000000000 + +/* SH_VEC_ROUTE_ROUTE */ +/* Description: Route */ +#define SH_VEC_ROUTE_ROUTE_SHFT 0 +#define SH_VEC_ROUTE_ROUTE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_CPU_PERM" */ +/* CPU MMR Access Permission Bits */ +/* ==================================================================== */ + +#define SH_CPU_PERM 0x0000000110060000 +#define SH_CPU_PERM_MASK 0xffffffffffffffff +#define SH_CPU_PERM_INIT 0xffffffffffffffff + +/* SH_CPU_PERM_ACCESS_BITS */ +/* Description: Access Bits */ +#define SH_CPU_PERM_ACCESS_BITS_SHFT 0 +#define SH_CPU_PERM_ACCESS_BITS_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_CPU_PERM_OVR" */ +/* CPU MMR Access Permission Override */ +/* ==================================================================== */ + +#define SH_CPU_PERM_OVR 0x0000000110060080 +#define SH_CPU_PERM_OVR_MASK 0xffffffffffffffff +#define SH_CPU_PERM_OVR_INIT 0x0000000000000000 + +/* SH_CPU_PERM_OVR_OVERRIDE */ +/* Description: Override */ +#define SH_CPU_PERM_OVR_OVERRIDE_SHFT 0 +#define SH_CPU_PERM_OVR_OVERRIDE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_EXT_IO_PERM" */ +/* External IO MMR Access Permission Bits */ +/* ==================================================================== */ + +#define SH_EXT_IO_PERM 0x0000000110060100 +#define SH_EXT_IO_PERM_MASK 0xffffffffffffffff +#define SH_EXT_IO_PERM_INIT 0x0000000000000000 + +/* SH_EXT_IO_PERM_ACCESS_BITS */ +/* Description: Access Bits */ +#define SH_EXT_IO_PERM_ACCESS_BITS_SHFT 0 +#define SH_EXT_IO_PERM_ACCESS_BITS_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_EXT_IOI_ACCESS" */ +/* External IO Interrupt Access Permission Bits */ +/* ==================================================================== */ + +#define SH_EXT_IOI_ACCESS 0x0000000110060180 +#define SH_EXT_IOI_ACCESS_MASK 0xffffffffffffffff +#define SH_EXT_IOI_ACCESS_INIT 0xffffffffffffffff + +/* SH_EXT_IOI_ACCESS_ACCESS_BITS */ +/* Description: Access Bits */ +#define SH_EXT_IOI_ACCESS_ACCESS_BITS_SHFT 0 +#define SH_EXT_IOI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_GC_FIL_CTRL" */ +/* SHub Global Clock Filter Control */ +/* ==================================================================== */ + +#define SH_GC_FIL_CTRL 0x0000000110060200 +#define SH_GC_FIL_CTRL_MASK 0x03ff3ff3ff1fff1f +#define SH_GC_FIL_CTRL_INIT 0x0000000000000000 + +/* SH_GC_FIL_CTRL_OFFSET */ +/* Description: Offset */ +#define SH_GC_FIL_CTRL_OFFSET_SHFT 0 +#define SH_GC_FIL_CTRL_OFFSET_MASK 0x000000000000001f + +/* SH_GC_FIL_CTRL_MASK_COUNTER */ +/* Description: Mask Counter */ +#define SH_GC_FIL_CTRL_MASK_COUNTER_SHFT 8 +#define SH_GC_FIL_CTRL_MASK_COUNTER_MASK 0x00000000000fff00 + +/* SH_GC_FIL_CTRL_MASK_ENABLE */ +/* Description: Mask Enable */ +#define SH_GC_FIL_CTRL_MASK_ENABLE_SHFT 20 +#define SH_GC_FIL_CTRL_MASK_ENABLE_MASK 0x0000000000100000 + +/* SH_GC_FIL_CTRL_DROPOUT_COUNTER */ +/* Description: Dropout Counter */ +#define SH_GC_FIL_CTRL_DROPOUT_COUNTER_SHFT 24 +#define SH_GC_FIL_CTRL_DROPOUT_COUNTER_MASK 0x00000003ff000000 + +/* SH_GC_FIL_CTRL_DROPOUT_THRESH */ +/* Description: Dropout threshold */ +#define SH_GC_FIL_CTRL_DROPOUT_THRESH_SHFT 36 +#define SH_GC_FIL_CTRL_DROPOUT_THRESH_MASK 0x00003ff000000000 + +/* SH_GC_FIL_CTRL_ERROR_COUNTER */ +/* Description: Error counter */ +#define SH_GC_FIL_CTRL_ERROR_COUNTER_SHFT 48 +#define SH_GC_FIL_CTRL_ERROR_COUNTER_MASK 0x03ff000000000000 + +/* ==================================================================== */ +/* Register "SH_GC_SRC_CTRL" */ +/* SHub Global Clock Control */ +/* ==================================================================== */ + +#define SH_GC_SRC_CTRL 0x0000000110060280 +#define SH_GC_SRC_CTRL_MASK 0x0000000313ff3ff1 +#define SH_GC_SRC_CTRL_INIT 0x0000000100000000 + +/* SH_GC_SRC_CTRL_ENABLE_COUNTER */ +/* Description: Enable Counter */ +#define SH_GC_SRC_CTRL_ENABLE_COUNTER_SHFT 0 +#define SH_GC_SRC_CTRL_ENABLE_COUNTER_MASK 0x0000000000000001 + +/* SH_GC_SRC_CTRL_MAX_COUNT */ +/* Description: Max Count */ +#define SH_GC_SRC_CTRL_MAX_COUNT_SHFT 4 +#define SH_GC_SRC_CTRL_MAX_COUNT_MASK 0x0000000000003ff0 + +/* SH_GC_SRC_CTRL_COUNTER */ +/* Description: Counter */ +#define SH_GC_SRC_CTRL_COUNTER_SHFT 16 +#define SH_GC_SRC_CTRL_COUNTER_MASK 0x0000000003ff0000 + +/* SH_GC_SRC_CTRL_TOGGLE_BIT */ +/* Description: Toggle bit */ +#define SH_GC_SRC_CTRL_TOGGLE_BIT_SHFT 28 +#define SH_GC_SRC_CTRL_TOGGLE_BIT_MASK 0x0000000010000000 + +/* SH_GC_SRC_CTRL_SOURCE_SEL */ +/* Description: Source select (0=ext., 1=Int., 2=SHUB) */ +#define SH_GC_SRC_CTRL_SOURCE_SEL_SHFT 32 +#define SH_GC_SRC_CTRL_SOURCE_SEL_MASK 0x0000000300000000 + +/* ==================================================================== */ +/* Register "SH_HARD_RESET" */ +/* SHub Hard Reset */ +/* ==================================================================== */ + +#define SH_HARD_RESET 0x0000000110060300 +#define SH_HARD_RESET_MASK 0x0000000000000001 +#define SH_HARD_RESET_INIT 0x0000000000000000 + +/* SH_HARD_RESET_HARD_RESET */ +/* Description: Hard Reset */ +#define SH_HARD_RESET_HARD_RESET_SHFT 0 +#define SH_HARD_RESET_HARD_RESET_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_IO_PERM" */ +/* II MMR Access Permission Bits */ +/* ==================================================================== */ + +#define SH_IO_PERM 0x0000000110060380 +#define SH_IO_PERM_MASK 0xffffffffffffffff +#define SH_IO_PERM_INIT 0x0000000000000000 + +/* SH_IO_PERM_ACCESS_BITS */ +/* Description: Access Bits */ +#define SH_IO_PERM_ACCESS_BITS_SHFT 0 +#define SH_IO_PERM_ACCESS_BITS_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_IOI_ACCESS" */ +/* II Interrupt Access Permission Bits */ +/* ==================================================================== */ + +#define SH_IOI_ACCESS 0x0000000110060400 +#define SH_IOI_ACCESS_MASK 0xffffffffffffffff +#define SH_IOI_ACCESS_INIT 0xffffffffffffffff + +/* SH_IOI_ACCESS_ACCESS_BITS */ +/* Description: Access Bits */ +#define SH_IOI_ACCESS_ACCESS_BITS_SHFT 0 +#define SH_IOI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_IPI_ACCESS" */ +/* CPU interrupt Access Permission Bits */ +/* ==================================================================== */ + +#define SH_IPI_ACCESS 0x0000000110060480 +#define SH_IPI_ACCESS_MASK 0xffffffffffffffff +#define SH_IPI_ACCESS_INIT 0xffffffffffffffff + +/* SH_IPI_ACCESS_ACCESS_BITS */ +/* Description: Access Bits */ +#define SH_IPI_ACCESS_ACCESS_BITS_SHFT 0 +#define SH_IPI_ACCESS_ACCESS_BITS_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_JTAG_CONFIG" */ +/* SHub JTAG configuration */ +/* ==================================================================== */ + +#define SH_JTAG_CONFIG 0x0000000110060500 +#define SH_JTAG_CONFIG_MASK 0x00ffffffffffffff +#define SH_JTAG_CONFIG_INIT 0x0000000000000000 + +/* SH_JTAG_CONFIG_MD_CLK_SEL */ +/* Description: Select divide freq of DRAMCLK */ +#define SH_JTAG_CONFIG_MD_CLK_SEL_SHFT 0 +#define SH_JTAG_CONFIG_MD_CLK_SEL_MASK 0x0000000000000003 + +/* SH_JTAG_CONFIG_NI_CLK_SEL */ +/* Description: Selects clock source for NICLK domain */ +#define SH_JTAG_CONFIG_NI_CLK_SEL_SHFT 2 +#define SH_JTAG_CONFIG_NI_CLK_SEL_MASK 0x0000000000000004 + +/* SH_JTAG_CONFIG_II_CLK_SEL */ +/* Description: Selects clock source for IOCLK domain */ +#define SH_JTAG_CONFIG_II_CLK_SEL_SHFT 3 +#define SH_JTAG_CONFIG_II_CLK_SEL_MASK 0x0000000000000018 + +/* SH_JTAG_CONFIG_WRT90_TARGET */ +/* Description: wrt90_target */ +#define SH_JTAG_CONFIG_WRT90_TARGET_SHFT 5 +#define SH_JTAG_CONFIG_WRT90_TARGET_MASK 0x000000000007ffe0 + +/* SH_JTAG_CONFIG_WRT90_OVERRIDER */ +/* Description: wrt90_overrideR */ +#define SH_JTAG_CONFIG_WRT90_OVERRIDER_SHFT 19 +#define SH_JTAG_CONFIG_WRT90_OVERRIDER_MASK 0x0000000000080000 + +/* SH_JTAG_CONFIG_WRT90_OVERRIDE */ +/* Description: wrt90_override */ +#define SH_JTAG_CONFIG_WRT90_OVERRIDE_SHFT 20 +#define SH_JTAG_CONFIG_WRT90_OVERRIDE_MASK 0x0000000000100000 + +/* SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY */ +/* Description: jtag_mci_reset_delay */ +#define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_SHFT 21 +#define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_MASK 0x0000000001e00000 + +/* SH_JTAG_CONFIG_JTAG_MCI_TARGET */ +/* Description: jtag_mci_target */ +#define SH_JTAG_CONFIG_JTAG_MCI_TARGET_SHFT 25 +#define SH_JTAG_CONFIG_JTAG_MCI_TARGET_MASK 0x0000007ffe000000 + +/* SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE */ +/* Description: jtag_mci_override */ +#define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_SHFT 39 +#define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_MASK 0x0000008000000000 + +/* SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH */ +/* Description: 0=depth 8, 1=depth1 */ +#define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_SHFT 40 +#define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_MASK 0x0000010000000000 + +/* SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT */ +/* Description: Enable sampling of BINIT */ +#define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_SHFT 41 +#define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_MASK 0x0000020000000000 + +/* SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING */ +#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_SHFT 42 +#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_MASK 0x0000040000000000 + +/* SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO */ +#define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_SHFT 43 +#define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_MASK 0x0000f80000000000 + +/* SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE */ +/* Description: Output tristate control */ +#define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_SHFT 48 +#define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_MASK 0x000f000000000000 + +/* SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST */ +/* Description: Enables BIST */ +#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_SHFT 52 +#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_MASK 0x0010000000000000 + +/* SH_JTAG_CONFIG_FSB_CONFIG_AUX */ +/* Description: Enables BIST */ +#define SH_JTAG_CONFIG_FSB_CONFIG_AUX_SHFT 53 +#define SH_JTAG_CONFIG_FSB_CONFIG_AUX_MASK 0x0060000000000000 + +/* SH_JTAG_CONFIG_GTL_CONFIG_RE */ +/* Description: Reference Enable selection for GTL io */ +#define SH_JTAG_CONFIG_GTL_CONFIG_RE_SHFT 55 +#define SH_JTAG_CONFIG_GTL_CONFIG_RE_MASK 0x0080000000000000 + +/* ==================================================================== */ +/* Register "SH_SHUB_ID" */ +/* SHub ID Number */ +/* ==================================================================== */ + +#define SH_SHUB_ID 0x0000000110060580 +#define SH_SHUB_ID_MASK 0x011f37ffffffffff +#define SH_SHUB_ID_INIT 0x0010300000000000 + +/* SH_SHUB_ID_FORCE1 */ +/* Description: Must be 1 */ +#define SH_SHUB_ID_FORCE1_SHFT 0 +#define SH_SHUB_ID_FORCE1_MASK 0x0000000000000001 + +/* SH_SHUB_ID_MANUFACTURER */ +/* Description: Manufacturer */ +#define SH_SHUB_ID_MANUFACTURER_SHFT 1 +#define SH_SHUB_ID_MANUFACTURER_MASK 0x0000000000000ffe + +/* SH_SHUB_ID_PART_NUMBER */ +/* Description: Part Number */ +#define SH_SHUB_ID_PART_NUMBER_SHFT 12 +#define SH_SHUB_ID_PART_NUMBER_MASK 0x000000000ffff000 + +/* SH_SHUB_ID_REVISION */ +/* Description: Revision */ +#define SH_SHUB_ID_REVISION_SHFT 28 +#define SH_SHUB_ID_REVISION_MASK 0x00000000f0000000 + +/* SH_SHUB_ID_NODE_ID */ +/* Description: Node Identification */ +#define SH_SHUB_ID_NODE_ID_SHFT 32 +#define SH_SHUB_ID_NODE_ID_MASK 0x000007ff00000000 + +/* SH_SHUB_ID_SHARING_MODE */ +/* Description: Sharing mode (Coherency Domain Size) */ +#define SH_SHUB_ID_SHARING_MODE_SHFT 44 +#define SH_SHUB_ID_SHARING_MODE_MASK 0x0000300000000000 + +/* SH_SHUB_ID_NODES_PER_BIT */ +/* Description: Nodes per bit definition for MMR access */ +#define SH_SHUB_ID_NODES_PER_BIT_SHFT 48 +#define SH_SHUB_ID_NODES_PER_BIT_MASK 0x001f000000000000 + +/* SH_SHUB_ID_NI_PORT */ +/* Description: NI port of vector reference, 0 = NI0, 1 = NI1 */ +#define SH_SHUB_ID_NI_PORT_SHFT 56 +#define SH_SHUB_ID_NI_PORT_MASK 0x0100000000000000 + +/* ==================================================================== */ +/* Register "SH_SHUBS_PRESENT0" */ +/* Shubs 0 - 63 Present. Used for invalidate generation */ +/* ==================================================================== */ + +#define SH_SHUBS_PRESENT0 0x0000000110060600 +#define SH_SHUBS_PRESENT0_MASK 0xffffffffffffffff +#define SH_SHUBS_PRESENT0_INIT 0xffffffffffffffff + +/* SH_SHUBS_PRESENT0_SHUBS_PRESENT0 */ +/* Description: Shubs 0 - 63 Present configuration */ +#define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_SHFT 0 +#define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_SHUBS_PRESENT1" */ +/* Shubs 64 - 127 Present. Used for invalidate generation */ +/* ==================================================================== */ + +#define SH_SHUBS_PRESENT1 0x0000000110060680 +#define SH_SHUBS_PRESENT1_MASK 0xffffffffffffffff +#define SH_SHUBS_PRESENT1_INIT 0xffffffffffffffff + +/* SH_SHUBS_PRESENT1_SHUBS_PRESENT1 */ +/* Description: Shubs 64 - 127 Present configuration */ +#define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_SHFT 0 +#define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_SHUBS_PRESENT2" */ +/* Shubs 128 - 191 Present. Used for invalidate generation */ +/* ==================================================================== */ + +#define SH_SHUBS_PRESENT2 0x0000000110060700 +#define SH_SHUBS_PRESENT2_MASK 0xffffffffffffffff +#define SH_SHUBS_PRESENT2_INIT 0xffffffffffffffff + +/* SH_SHUBS_PRESENT2_SHUBS_PRESENT2 */ +/* Description: Shubs 128 - 191 Present configuration */ +#define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_SHFT 0 +#define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_SHUBS_PRESENT3" */ +/* Shubs 192 - 255 Present. Used for invalidate generation */ +/* ==================================================================== */ + +#define SH_SHUBS_PRESENT3 0x0000000110060780 +#define SH_SHUBS_PRESENT3_MASK 0xffffffffffffffff +#define SH_SHUBS_PRESENT3_INIT 0xffffffffffffffff + +/* SH_SHUBS_PRESENT3_SHUBS_PRESENT3 */ +/* Description: Shubs 192 - 255 Present configuration */ +#define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_SHFT 0 +#define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_SOFT_RESET" */ +/* SHub Soft Reset */ +/* ==================================================================== */ + +#define SH_SOFT_RESET 0x0000000110060800 +#define SH_SOFT_RESET_MASK 0x0000000000000001 +#define SH_SOFT_RESET_INIT 0x0000000000000000 + +/* SH_SOFT_RESET_SOFT_RESET */ +/* Description: Soft Reset */ +#define SH_SOFT_RESET_SOFT_RESET_SHFT 0 +#define SH_SOFT_RESET_SOFT_RESET_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_FIRST_ERROR" */ +/* Shub Global First Error Flags */ +/* ==================================================================== */ + +#define SH_FIRST_ERROR 0x0000000110071000 +#define SH_FIRST_ERROR_MASK 0x000000000007ffff +#define SH_FIRST_ERROR_INIT 0x0000000000000000 + +/* SH_FIRST_ERROR_FIRST_ERROR */ +/* Description: Chiplet with first error */ +#define SH_FIRST_ERROR_FIRST_ERROR_SHFT 0 +#define SH_FIRST_ERROR_FIRST_ERROR_MASK 0x000000000007ffff + +/* ==================================================================== */ +/* Register "SH_II_HW_TIME_STAMP" */ +/* II hardware error time stamp */ +/* ==================================================================== */ + +#define SH_II_HW_TIME_STAMP 0x0000000110071080 +#define SH_II_HW_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_II_HW_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_II_HW_TIME_STAMP_TIME */ +/* Description: II hardware error time stamp */ +#define SH_II_HW_TIME_STAMP_TIME_SHFT 0 +#define SH_II_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_II_HW_TIME_STAMP_VALID */ +/* Description: II hardware error time stamp valid */ +#define SH_II_HW_TIME_STAMP_VALID_SHFT 63 +#define SH_II_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_LB_HW_TIME_STAMP" */ +/* LB hardware error time stamp */ +/* ==================================================================== */ + +#define SH_LB_HW_TIME_STAMP 0x0000000110071100 +#define SH_LB_HW_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_LB_HW_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_LB_HW_TIME_STAMP_TIME */ +/* Description: LB hardware error time stamp */ +#define SH_LB_HW_TIME_STAMP_TIME_SHFT 0 +#define SH_LB_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_LB_HW_TIME_STAMP_VALID */ +/* Description: LB hardware error time stamp valid */ +#define SH_LB_HW_TIME_STAMP_VALID_SHFT 63 +#define SH_LB_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_COR_TIME_STAMP" */ +/* MD correctable error time stamp */ +/* ==================================================================== */ + +#define SH_MD_COR_TIME_STAMP 0x0000000110071180 +#define SH_MD_COR_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_MD_COR_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_MD_COR_TIME_STAMP_TIME */ +/* Description: MD correctable error time stamp */ +#define SH_MD_COR_TIME_STAMP_TIME_SHFT 0 +#define SH_MD_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_MD_COR_TIME_STAMP_VALID */ +/* Description: MD correctable error time stamp valid */ +#define SH_MD_COR_TIME_STAMP_VALID_SHFT 63 +#define SH_MD_COR_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_HW_TIME_STAMP" */ +/* MD hardware error time stamp */ +/* ==================================================================== */ + +#define SH_MD_HW_TIME_STAMP 0x0000000110071200 +#define SH_MD_HW_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_MD_HW_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_MD_HW_TIME_STAMP_TIME */ +/* Description: MD hardware error time stamp */ +#define SH_MD_HW_TIME_STAMP_TIME_SHFT 0 +#define SH_MD_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_MD_HW_TIME_STAMP_VALID */ +/* Description: MD hardware error time stamp valid */ +#define SH_MD_HW_TIME_STAMP_VALID_SHFT 63 +#define SH_MD_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_UNCOR_TIME_STAMP" */ +/* MD uncorrectable error time stamp */ +/* ==================================================================== */ + +#define SH_MD_UNCOR_TIME_STAMP 0x0000000110071280 +#define SH_MD_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_MD_UNCOR_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_MD_UNCOR_TIME_STAMP_TIME */ +/* Description: MD uncorrectable error time stamp */ +#define SH_MD_UNCOR_TIME_STAMP_TIME_SHFT 0 +#define SH_MD_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_MD_UNCOR_TIME_STAMP_VALID */ +/* Description: MD uncorrectable error time stamp valid */ +#define SH_MD_UNCOR_TIME_STAMP_VALID_SHFT 63 +#define SH_MD_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_COR_TIME_STAMP" */ +/* PI correctable error time stamp */ +/* ==================================================================== */ + +#define SH_PI_COR_TIME_STAMP 0x0000000110071300 +#define SH_PI_COR_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_PI_COR_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_PI_COR_TIME_STAMP_TIME */ +/* Description: PI correctable error time stamp */ +#define SH_PI_COR_TIME_STAMP_TIME_SHFT 0 +#define SH_PI_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_PI_COR_TIME_STAMP_VALID */ +/* Description: PI correctable error time stamp valid */ +#define SH_PI_COR_TIME_STAMP_VALID_SHFT 63 +#define SH_PI_COR_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_HW_TIME_STAMP" */ +/* PI hardware error time stamp */ +/* ==================================================================== */ + +#define SH_PI_HW_TIME_STAMP 0x0000000110071380 +#define SH_PI_HW_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_PI_HW_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_PI_HW_TIME_STAMP_TIME */ +/* Description: PI hardware error time stamp */ +#define SH_PI_HW_TIME_STAMP_TIME_SHFT 0 +#define SH_PI_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_PI_HW_TIME_STAMP_VALID */ +/* Description: PI hardware error time stamp valid */ +#define SH_PI_HW_TIME_STAMP_VALID_SHFT 63 +#define SH_PI_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PI_UNCOR_TIME_STAMP" */ +/* PI uncorrectable error time stamp */ +/* ==================================================================== */ + +#define SH_PI_UNCOR_TIME_STAMP 0x0000000110071400 +#define SH_PI_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_PI_UNCOR_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_PI_UNCOR_TIME_STAMP_TIME */ +/* Description: PI uncorrectable error time stamp */ +#define SH_PI_UNCOR_TIME_STAMP_TIME_SHFT 0 +#define SH_PI_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_PI_UNCOR_TIME_STAMP_VALID */ +/* Description: PI uncorrectable error time stamp valid */ +#define SH_PI_UNCOR_TIME_STAMP_VALID_SHFT 63 +#define SH_PI_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC0_ADV_TIME_STAMP" */ +/* Proc 0 advisory time stamp */ +/* ==================================================================== */ + +#define SH_PROC0_ADV_TIME_STAMP 0x0000000110071480 +#define SH_PROC0_ADV_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_PROC0_ADV_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_PROC0_ADV_TIME_STAMP_TIME */ +/* Description: Processor 0 advisory time stamp */ +#define SH_PROC0_ADV_TIME_STAMP_TIME_SHFT 0 +#define SH_PROC0_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_PROC0_ADV_TIME_STAMP_VALID */ +/* Description: Processor 0 advisory time stamp valid */ +#define SH_PROC0_ADV_TIME_STAMP_VALID_SHFT 63 +#define SH_PROC0_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC0_ERR_TIME_STAMP" */ +/* Proc 0 error time stamp */ +/* ==================================================================== */ + +#define SH_PROC0_ERR_TIME_STAMP 0x0000000110071500 +#define SH_PROC0_ERR_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_PROC0_ERR_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_PROC0_ERR_TIME_STAMP_TIME */ +/* Description: Processor 0 error time stamp */ +#define SH_PROC0_ERR_TIME_STAMP_TIME_SHFT 0 +#define SH_PROC0_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_PROC0_ERR_TIME_STAMP_VALID */ +/* Description: Processor 0 error time stamp valid */ +#define SH_PROC0_ERR_TIME_STAMP_VALID_SHFT 63 +#define SH_PROC0_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC1_ADV_TIME_STAMP" */ +/* Proc 1 advisory time stamp */ +/* ==================================================================== */ + +#define SH_PROC1_ADV_TIME_STAMP 0x0000000110071580 +#define SH_PROC1_ADV_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_PROC1_ADV_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_PROC1_ADV_TIME_STAMP_TIME */ +/* Description: Processor 1 advisory time stamp */ +#define SH_PROC1_ADV_TIME_STAMP_TIME_SHFT 0 +#define SH_PROC1_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_PROC1_ADV_TIME_STAMP_VALID */ +/* Description: Processor 1 advisory time stamp valid */ +#define SH_PROC1_ADV_TIME_STAMP_VALID_SHFT 63 +#define SH_PROC1_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC1_ERR_TIME_STAMP" */ +/* Proc 1 error time stamp */ +/* ==================================================================== */ + +#define SH_PROC1_ERR_TIME_STAMP 0x0000000110071600 +#define SH_PROC1_ERR_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_PROC1_ERR_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_PROC1_ERR_TIME_STAMP_TIME */ +/* Description: Processor 1 error time stamp */ +#define SH_PROC1_ERR_TIME_STAMP_TIME_SHFT 0 +#define SH_PROC1_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_PROC1_ERR_TIME_STAMP_VALID */ +/* Description: Processor 1 error time stamp valid */ +#define SH_PROC1_ERR_TIME_STAMP_VALID_SHFT 63 +#define SH_PROC1_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC2_ADV_TIME_STAMP" */ +/* Proc 2 advisory time stamp */ +/* ==================================================================== */ + +#define SH_PROC2_ADV_TIME_STAMP 0x0000000110071680 +#define SH_PROC2_ADV_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_PROC2_ADV_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_PROC2_ADV_TIME_STAMP_TIME */ +/* Description: Processor 2 advisory time stamp */ +#define SH_PROC2_ADV_TIME_STAMP_TIME_SHFT 0 +#define SH_PROC2_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_PROC2_ADV_TIME_STAMP_VALID */ +/* Description: Processor 2 advisory time stamp valid */ +#define SH_PROC2_ADV_TIME_STAMP_VALID_SHFT 63 +#define SH_PROC2_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC2_ERR_TIME_STAMP" */ +/* Proc 2 error time stamp */ +/* ==================================================================== */ + +#define SH_PROC2_ERR_TIME_STAMP 0x0000000110071700 +#define SH_PROC2_ERR_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_PROC2_ERR_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_PROC2_ERR_TIME_STAMP_TIME */ +/* Description: Processor 2 error time stamp */ +#define SH_PROC2_ERR_TIME_STAMP_TIME_SHFT 0 +#define SH_PROC2_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_PROC2_ERR_TIME_STAMP_VALID */ +/* Description: Processor 2 error time stamp valid */ +#define SH_PROC2_ERR_TIME_STAMP_VALID_SHFT 63 +#define SH_PROC2_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC3_ADV_TIME_STAMP" */ +/* Proc 3 advisory time stamp */ +/* ==================================================================== */ + +#define SH_PROC3_ADV_TIME_STAMP 0x0000000110071780 +#define SH_PROC3_ADV_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_PROC3_ADV_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_PROC3_ADV_TIME_STAMP_TIME */ +/* Description: Processor 3 advisory time stamp */ +#define SH_PROC3_ADV_TIME_STAMP_TIME_SHFT 0 +#define SH_PROC3_ADV_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_PROC3_ADV_TIME_STAMP_VALID */ +/* Description: Processor 3 advisory time stamp valid */ +#define SH_PROC3_ADV_TIME_STAMP_VALID_SHFT 63 +#define SH_PROC3_ADV_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PROC3_ERR_TIME_STAMP" */ +/* Proc 3 error time stamp */ +/* ==================================================================== */ + +#define SH_PROC3_ERR_TIME_STAMP 0x0000000110071800 +#define SH_PROC3_ERR_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_PROC3_ERR_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_PROC3_ERR_TIME_STAMP_TIME */ +/* Description: Processor 3 error time stamp */ +#define SH_PROC3_ERR_TIME_STAMP_TIME_SHFT 0 +#define SH_PROC3_ERR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_PROC3_ERR_TIME_STAMP_VALID */ +/* Description: Processor 3 error time stamp valid */ +#define SH_PROC3_ERR_TIME_STAMP_VALID_SHFT 63 +#define SH_PROC3_ERR_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_COR_TIME_STAMP" */ +/* XN correctable error time stamp */ +/* ==================================================================== */ + +#define SH_XN_COR_TIME_STAMP 0x0000000110071880 +#define SH_XN_COR_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_XN_COR_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_XN_COR_TIME_STAMP_TIME */ +/* Description: XN correctable error time stamp */ +#define SH_XN_COR_TIME_STAMP_TIME_SHFT 0 +#define SH_XN_COR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_XN_COR_TIME_STAMP_VALID */ +/* Description: XN correctable error time stamp valid */ +#define SH_XN_COR_TIME_STAMP_VALID_SHFT 63 +#define SH_XN_COR_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_HW_TIME_STAMP" */ +/* XN hardware error time stamp */ +/* ==================================================================== */ + +#define SH_XN_HW_TIME_STAMP 0x0000000110071900 +#define SH_XN_HW_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_XN_HW_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_XN_HW_TIME_STAMP_TIME */ +/* Description: XN hardware error time stamp */ +#define SH_XN_HW_TIME_STAMP_TIME_SHFT 0 +#define SH_XN_HW_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_XN_HW_TIME_STAMP_VALID */ +/* Description: XN hardware error time stamp valid */ +#define SH_XN_HW_TIME_STAMP_VALID_SHFT 63 +#define SH_XN_HW_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_XN_UNCOR_TIME_STAMP" */ +/* XN uncorrectable error time stamp */ +/* ==================================================================== */ + +#define SH_XN_UNCOR_TIME_STAMP 0x0000000110071980 +#define SH_XN_UNCOR_TIME_STAMP_MASK 0xffffffffffffffff +#define SH_XN_UNCOR_TIME_STAMP_INIT 0x0000000000000000 + +/* SH_XN_UNCOR_TIME_STAMP_TIME */ +/* Description: XN uncorrectable error time stamp */ +#define SH_XN_UNCOR_TIME_STAMP_TIME_SHFT 0 +#define SH_XN_UNCOR_TIME_STAMP_TIME_MASK 0x7fffffffffffffff + +/* SH_XN_UNCOR_TIME_STAMP_VALID */ +/* Description: XN uncorrectable error time stamp valid */ +#define SH_XN_UNCOR_TIME_STAMP_VALID_SHFT 63 +#define SH_XN_UNCOR_TIME_STAMP_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_DEBUG_PORT" */ +/* SHub Debug Port */ +/* ==================================================================== */ + +#define SH_DEBUG_PORT 0x0000000110072000 +#define SH_DEBUG_PORT_MASK 0x00000000ffffffff +#define SH_DEBUG_PORT_INIT 0x0000000000000000 + +/* SH_DEBUG_PORT_DEBUG_NIBBLE0 */ +/* Description: Debug port nibble 0 */ +#define SH_DEBUG_PORT_DEBUG_NIBBLE0_SHFT 0 +#define SH_DEBUG_PORT_DEBUG_NIBBLE0_MASK 0x000000000000000f + +/* SH_DEBUG_PORT_DEBUG_NIBBLE1 */ +/* Description: Debug port nibble 1 */ +#define SH_DEBUG_PORT_DEBUG_NIBBLE1_SHFT 4 +#define SH_DEBUG_PORT_DEBUG_NIBBLE1_MASK 0x00000000000000f0 + +/* SH_DEBUG_PORT_DEBUG_NIBBLE2 */ +/* Description: Debug port nibble 2 */ +#define SH_DEBUG_PORT_DEBUG_NIBBLE2_SHFT 8 +#define SH_DEBUG_PORT_DEBUG_NIBBLE2_MASK 0x0000000000000f00 + +/* SH_DEBUG_PORT_DEBUG_NIBBLE3 */ +/* Description: Debug port nibble 3 */ +#define SH_DEBUG_PORT_DEBUG_NIBBLE3_SHFT 12 +#define SH_DEBUG_PORT_DEBUG_NIBBLE3_MASK 0x000000000000f000 + +/* SH_DEBUG_PORT_DEBUG_NIBBLE4 */ +/* Description: Debug port nibble 4 */ +#define SH_DEBUG_PORT_DEBUG_NIBBLE4_SHFT 16 +#define SH_DEBUG_PORT_DEBUG_NIBBLE4_MASK 0x00000000000f0000 + +/* SH_DEBUG_PORT_DEBUG_NIBBLE5 */ +/* Description: Debug port nibble 5 */ +#define SH_DEBUG_PORT_DEBUG_NIBBLE5_SHFT 20 +#define SH_DEBUG_PORT_DEBUG_NIBBLE5_MASK 0x0000000000f00000 + +/* SH_DEBUG_PORT_DEBUG_NIBBLE6 */ +/* Description: Debug port nibble 6 */ +#define SH_DEBUG_PORT_DEBUG_NIBBLE6_SHFT 24 +#define SH_DEBUG_PORT_DEBUG_NIBBLE6_MASK 0x000000000f000000 + +/* SH_DEBUG_PORT_DEBUG_NIBBLE7 */ +/* Description: Debug port nibble 7 */ +#define SH_DEBUG_PORT_DEBUG_NIBBLE7_SHFT 28 +#define SH_DEBUG_PORT_DEBUG_NIBBLE7_MASK 0x00000000f0000000 + +/* ==================================================================== */ +/* Register "SH_II_DEBUG_DATA" */ +/* II Debug Data */ +/* ==================================================================== */ + +#define SH_II_DEBUG_DATA 0x0000000110072080 +#define SH_II_DEBUG_DATA_MASK 0x00000000ffffffff +#define SH_II_DEBUG_DATA_INIT 0x0000000000000000 + +/* SH_II_DEBUG_DATA_II_DATA */ +/* Description: II debug data */ +#define SH_II_DEBUG_DATA_II_DATA_SHFT 0 +#define SH_II_DEBUG_DATA_II_DATA_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_II_WRAP_DEBUG_DATA" */ +/* SHub II Wrapper Debug Data */ +/* ==================================================================== */ + +#define SH_II_WRAP_DEBUG_DATA 0x0000000110072100 +#define SH_II_WRAP_DEBUG_DATA_MASK 0x00000000ffffffff +#define SH_II_WRAP_DEBUG_DATA_INIT 0x0000000000000000 + +/* SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA */ +/* Description: II wrapper debug data */ +#define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_SHFT 0 +#define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_LB_DEBUG_DATA" */ +/* SHub LB Debug Data */ +/* ==================================================================== */ + +#define SH_LB_DEBUG_DATA 0x0000000110072180 +#define SH_LB_DEBUG_DATA_MASK 0x00000000ffffffff +#define SH_LB_DEBUG_DATA_INIT 0x0000000000000000 + +/* SH_LB_DEBUG_DATA_LB_DATA */ +/* Description: LB debug data */ +#define SH_LB_DEBUG_DATA_LB_DATA_SHFT 0 +#define SH_LB_DEBUG_DATA_LB_DATA_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DEBUG_DATA" */ +/* SHub MD Debug Data */ +/* ==================================================================== */ + +#define SH_MD_DEBUG_DATA 0x0000000110072200 +#define SH_MD_DEBUG_DATA_MASK 0x00000000ffffffff +#define SH_MD_DEBUG_DATA_INIT 0x0000000000000000 + +/* SH_MD_DEBUG_DATA_MD_DATA */ +/* Description: MD debug data */ +#define SH_MD_DEBUG_DATA_MD_DATA_SHFT 0 +#define SH_MD_DEBUG_DATA_MD_DATA_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_PI_DEBUG_DATA" */ +/* SHub PI Debug Data */ +/* ==================================================================== */ + +#define SH_PI_DEBUG_DATA 0x0000000110072280 +#define SH_PI_DEBUG_DATA_MASK 0x00000000ffffffff +#define SH_PI_DEBUG_DATA_INIT 0x0000000000000000 + +/* SH_PI_DEBUG_DATA_PI_DATA */ +/* Description: PI Debug Data */ +#define SH_PI_DEBUG_DATA_PI_DATA_SHFT 0 +#define SH_PI_DEBUG_DATA_PI_DATA_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_XN_DEBUG_DATA" */ +/* SHub XN Debug Data */ +/* ==================================================================== */ + +#define SH_XN_DEBUG_DATA 0x0000000110072300 +#define SH_XN_DEBUG_DATA_MASK 0x00000000ffffffff +#define SH_XN_DEBUG_DATA_INIT 0x0000000000000000 + +/* SH_XN_DEBUG_DATA_XN_DATA */ +/* Description: XN debug data */ +#define SH_XN_DEBUG_DATA_XN_DATA_SHFT 0 +#define SH_XN_DEBUG_DATA_XN_DATA_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_TSF_ARMED_STATE" */ +/* Trigger sequencing facility arm state */ +/* ==================================================================== */ + +#define SH_TSF_ARMED_STATE 0x0000000110073000 +#define SH_TSF_ARMED_STATE_MASK 0x00000000000000ff +#define SH_TSF_ARMED_STATE_INIT 0x0000000000000000 + +/* SH_TSF_ARMED_STATE_STATE */ +/* Description: Trigger sequencing facility armed state */ +#define SH_TSF_ARMED_STATE_STATE_SHFT 0 +#define SH_TSF_ARMED_STATE_STATE_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_TSF_COUNTER_VALUE" */ +/* Trigger sequencing facility counter value */ +/* ==================================================================== */ + +#define SH_TSF_COUNTER_VALUE 0x0000000110073080 +#define SH_TSF_COUNTER_VALUE_MASK 0xffffffffffffffff +#define SH_TSF_COUNTER_VALUE_INIT 0x0000000000000000 + +/* SH_TSF_COUNTER_VALUE_COUNT_32 */ +/* Description: Trigger sequencing facility counter 32 */ +#define SH_TSF_COUNTER_VALUE_COUNT_32_SHFT 0 +#define SH_TSF_COUNTER_VALUE_COUNT_32_MASK 0x00000000ffffffff + +/* SH_TSF_COUNTER_VALUE_COUNT_16 */ +/* Description: Trigger sequencing facility counter 16 */ +#define SH_TSF_COUNTER_VALUE_COUNT_16_SHFT 32 +#define SH_TSF_COUNTER_VALUE_COUNT_16_MASK 0x0000ffff00000000 + +/* SH_TSF_COUNTER_VALUE_COUNT_8B */ +/* Description: Trigger sequencing facility counter 8b */ +#define SH_TSF_COUNTER_VALUE_COUNT_8B_SHFT 48 +#define SH_TSF_COUNTER_VALUE_COUNT_8B_MASK 0x00ff000000000000 + +/* SH_TSF_COUNTER_VALUE_COUNT_8A */ +/* Description: Trigger sequencing facility counter 8a */ +#define SH_TSF_COUNTER_VALUE_COUNT_8A_SHFT 56 +#define SH_TSF_COUNTER_VALUE_COUNT_8A_MASK 0xff00000000000000 + +/* ==================================================================== */ +/* Register "SH_TSF_TRIGGERED_STATE" */ +/* Trigger sequencing facility triggered state */ +/* ==================================================================== */ + +#define SH_TSF_TRIGGERED_STATE 0x0000000110073100 +#define SH_TSF_TRIGGERED_STATE_MASK 0x00000000000000ff +#define SH_TSF_TRIGGERED_STATE_INIT 0x0000000000000000 + +/* SH_TSF_TRIGGERED_STATE_STATE */ +/* Description: Trigger sequencing facility triggered state */ +#define SH_TSF_TRIGGERED_STATE_STATE_SHFT 0 +#define SH_TSF_TRIGGERED_STATE_STATE_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_VEC_RDDATA" */ +/* Vector Reply Message Data */ +/* ==================================================================== */ + +#define SH_VEC_RDDATA 0x0000000110074000 +#define SH_VEC_RDDATA_MASK 0xffffffffffffffff +#define SH_VEC_RDDATA_INIT 0x0000000000000000 + +/* SH_VEC_RDDATA_DATA */ +/* Description: Data */ +#define SH_VEC_RDDATA_DATA_SHFT 0 +#define SH_VEC_RDDATA_DATA_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_VEC_RETURN" */ +/* Vector Reply Message Return Route */ +/* ==================================================================== */ + +#define SH_VEC_RETURN 0x0000000110074080 +#define SH_VEC_RETURN_MASK 0xffffffffffffffff +#define SH_VEC_RETURN_INIT 0x0000000000000000 + +/* SH_VEC_RETURN_ROUTE */ +/* Description: Route */ +#define SH_VEC_RETURN_ROUTE_SHFT 0 +#define SH_VEC_RETURN_ROUTE_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_VEC_STATUS" */ +/* Vector Reply Message Status */ +/* ==================================================================== */ + +#define SH_VEC_STATUS 0x0000000110074100 +#define SH_VEC_STATUS_MASK 0xcfffffffffffffff +#define SH_VEC_STATUS_INIT 0x0000000000000000 + +/* SH_VEC_STATUS_TYPE */ +/* Description: Type */ +#define SH_VEC_STATUS_TYPE_SHFT 0 +#define SH_VEC_STATUS_TYPE_MASK 0x0000000000000007 + +/* SH_VEC_STATUS_ADDRESS */ +/* Description: Address */ +#define SH_VEC_STATUS_ADDRESS_SHFT 3 +#define SH_VEC_STATUS_ADDRESS_MASK 0x00000007fffffff8 + +/* SH_VEC_STATUS_PIO_ID */ +/* Description: PIO ID */ +#define SH_VEC_STATUS_PIO_ID_SHFT 35 +#define SH_VEC_STATUS_PIO_ID_MASK 0x00003ff800000000 + +/* SH_VEC_STATUS_SOURCE */ +/* Description: Source */ +#define SH_VEC_STATUS_SOURCE_SHFT 46 +#define SH_VEC_STATUS_SOURCE_MASK 0x0fffc00000000000 + +/* SH_VEC_STATUS_OVERRUN */ +/* Description: Overrun */ +#define SH_VEC_STATUS_OVERRUN_SHFT 62 +#define SH_VEC_STATUS_OVERRUN_MASK 0x4000000000000000 + +/* SH_VEC_STATUS_STATUS_VALID */ +/* Description: Status_Valid */ +#define SH_VEC_STATUS_STATUS_VALID_SHFT 63 +#define SH_VEC_STATUS_STATUS_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_VEC_STATUS_ALIAS" */ +/* Vector Reply Message Status Alias */ +/* ==================================================================== */ + +#define SH_VEC_STATUS_ALIAS 0x0000000110074108 + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT0_CONTROL" */ +/* Performance Counter 0 Control */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNT0_CONTROL 0x0000000110080000 +#define SH_PERFORMANCE_COUNT0_CONTROL_MASK 0x000000000007ffff +#define SH_PERFORMANCE_COUNT0_CONTROL_INIT 0x000000000000b8b8 + +/* SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS */ +/* Description: Counter 0 up stimulus */ +#define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_SHFT 0 +#define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_MASK 0x000000000000001f + +/* SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT */ +/* Description: Counter 0 up event select (1-greater than, 0-equal) */ +#define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_SHFT 5 +#define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_MASK 0x0000000000000020 + +/* SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY */ +/* Description: Counter 0 up polarity select (1-negative edge, 0-po */ +/* sitive edge) */ +#define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_SHFT 6 +#define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_MASK 0x0000000000000040 + +/* SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE */ +/* Description: Counter 0 up mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_SHFT 7 +#define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_MASK 0x0000000000000080 + +/* SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS */ +/* Description: Counter 0 down stimulus */ +#define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_SHFT 8 +#define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 + +/* SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT */ +/* Description: Counter 0 down event select (1-greater than, 0-equa */ +#define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_SHFT 13 +#define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_MASK 0x0000000000002000 + +/* SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY */ +/* Description: Counter 0 down polarity select (1-negative edge, 0- */ +/* positive edge) */ +#define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_SHFT 14 +#define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_MASK 0x0000000000004000 + +/* SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE */ +/* Description: Counter 0 down mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_SHFT 15 +#define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_MASK 0x0000000000008000 + +/* SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE */ +/* Description: Counter 0 enable increment */ +#define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_SHFT 16 +#define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_MASK 0x0000000000010000 + +/* SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE */ +/* Description: Counter 0 enable decrement */ +#define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_SHFT 17 +#define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 + +/* SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE */ +/* Description: Counter 0 enable peak detection */ +#define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_SHFT 18 +#define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT1_CONTROL" */ +/* Performance Counter 1 Control */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNT1_CONTROL 0x0000000110090000 +#define SH_PERFORMANCE_COUNT1_CONTROL_MASK 0x000000000007ffff +#define SH_PERFORMANCE_COUNT1_CONTROL_INIT 0x000000000000b8b8 + +/* SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS */ +/* Description: Counter 1 up stimulus */ +#define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_SHFT 0 +#define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_MASK 0x000000000000001f + +/* SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT */ +/* Description: Counter 1 up event select (1-greater than, 0-equal) */ +#define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_SHFT 5 +#define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_MASK 0x0000000000000020 + +/* SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY */ +/* Description: Counter 1 up polarity select (1-negative edge, 0-po */ +/* sitive edge) */ +#define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_SHFT 6 +#define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_MASK 0x0000000000000040 + +/* SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE */ +/* Description: Counter 1 up mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_SHFT 7 +#define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_MASK 0x0000000000000080 + +/* SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS */ +/* Description: Counter 1 down stimulus */ +#define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_SHFT 8 +#define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 + +/* SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT */ +/* Description: Counter 1 down event select (1-greater than, 0-equa */ +#define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_SHFT 13 +#define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_MASK 0x0000000000002000 + +/* SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY */ +/* Description: Counter 1 down polarity select (1-negative edge, 0- */ +/* positive edge) */ +#define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_SHFT 14 +#define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_MASK 0x0000000000004000 + +/* SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE */ +/* Description: Counter 1 down mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_SHFT 15 +#define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_MASK 0x0000000000008000 + +/* SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE */ +/* Description: Counter 1 enable increment */ +#define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_SHFT 16 +#define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_MASK 0x0000000000010000 + +/* SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE */ +/* Description: Counter 1 enable decrement */ +#define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_SHFT 17 +#define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 + +/* SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE */ +/* Description: Counter 1 enable peak detection */ +#define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_SHFT 18 +#define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT2_CONTROL" */ +/* Performance Counter 2 Control */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNT2_CONTROL 0x00000001100a0000 +#define SH_PERFORMANCE_COUNT2_CONTROL_MASK 0x000000000007ffff +#define SH_PERFORMANCE_COUNT2_CONTROL_INIT 0x000000000000b8b8 + +/* SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS */ +/* Description: Counter 2 up stimulus */ +#define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_SHFT 0 +#define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_MASK 0x000000000000001f + +/* SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT */ +/* Description: Counter 2 up event select (1-greater than, 0-equal) */ +#define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_SHFT 5 +#define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_MASK 0x0000000000000020 + +/* SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY */ +/* Description: Counter 2 up polarity select (1-negative edge, 0-po */ +/* sitive edge) */ +#define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_SHFT 6 +#define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_MASK 0x0000000000000040 + +/* SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE */ +/* Description: Counter 2 up mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_SHFT 7 +#define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_MASK 0x0000000000000080 + +/* SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS */ +/* Description: Counter 2 down stimulus */ +#define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_SHFT 8 +#define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 + +/* SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT */ +/* Description: Counter 2 down event select (1-greater than, 0-equa */ +#define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_SHFT 13 +#define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_MASK 0x0000000000002000 + +/* SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY */ +/* Description: Counter 2 down polarity select (1-negative edge, 0- */ +/* positive edge) */ +#define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_SHFT 14 +#define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_MASK 0x0000000000004000 + +/* SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE */ +/* Description: Counter 2 down mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_SHFT 15 +#define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_MASK 0x0000000000008000 + +/* SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE */ +/* Description: Counter 2 enable increment */ +#define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_SHFT 16 +#define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_MASK 0x0000000000010000 + +/* SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE */ +/* Description: Counter 2 enable decrement */ +#define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_SHFT 17 +#define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 + +/* SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE */ +/* Description: Counter 2 enable peak detection */ +#define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_SHFT 18 +#define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT3_CONTROL" */ +/* Performance Counter 3 Control */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNT3_CONTROL 0x00000001100b0000 +#define SH_PERFORMANCE_COUNT3_CONTROL_MASK 0x000000000007ffff +#define SH_PERFORMANCE_COUNT3_CONTROL_INIT 0x000000000000b8b8 + +/* SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS */ +/* Description: Counter 3 up stimulus */ +#define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_SHFT 0 +#define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_MASK 0x000000000000001f + +/* SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT */ +/* Description: Counter 3 up event select (1-greater than, 0-equal) */ +#define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_SHFT 5 +#define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_MASK 0x0000000000000020 + +/* SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY */ +/* Description: Counter 3 up polarity select (1-negative edge, 0-po */ +/* sitive edge) */ +#define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_SHFT 6 +#define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_MASK 0x0000000000000040 + +/* SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE */ +/* Description: Counter 3 up mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_SHFT 7 +#define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_MASK 0x0000000000000080 + +/* SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS */ +/* Description: Counter 3 down stimulus */ +#define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_SHFT 8 +#define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 + +/* SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT */ +/* Description: Counter 3 down event select (1-greater than, 0-equa */ +#define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_SHFT 13 +#define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_MASK 0x0000000000002000 + +/* SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY */ +/* Description: Counter 3 down polarity select (1-negative edge, 0- */ +/* positive edge) */ +#define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_SHFT 14 +#define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_MASK 0x0000000000004000 + +/* SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE */ +/* Description: Counter 3 down mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_SHFT 15 +#define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_MASK 0x0000000000008000 + +/* SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE */ +/* Description: Counter 3 enable increment */ +#define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_SHFT 16 +#define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_MASK 0x0000000000010000 + +/* SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE */ +/* Description: Counter 3 enable decrement */ +#define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_SHFT 17 +#define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 + +/* SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE */ +/* Description: Counter 3 enable peak detection */ +#define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_SHFT 18 +#define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT4_CONTROL" */ +/* Performance Counter 4 Control */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNT4_CONTROL 0x00000001100c0000 +#define SH_PERFORMANCE_COUNT4_CONTROL_MASK 0x000000000007ffff +#define SH_PERFORMANCE_COUNT4_CONTROL_INIT 0x000000000000b8b8 + +/* SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS */ +/* Description: Counter 4 up stimulus */ +#define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_SHFT 0 +#define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_MASK 0x000000000000001f + +/* SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT */ +/* Description: Counter 4 up event select (1-greater than, 0-equal) */ +#define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_SHFT 5 +#define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_MASK 0x0000000000000020 + +/* SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY */ +/* Description: Counter 4 up polarity select (1-negative edge, 0-po */ +/* sitive edge) */ +#define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_SHFT 6 +#define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_MASK 0x0000000000000040 + +/* SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE */ +/* Description: Counter 4 up mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_SHFT 7 +#define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_MASK 0x0000000000000080 + +/* SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS */ +/* Description: Counter 4 down stimulus */ +#define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_SHFT 8 +#define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 + +/* SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT */ +/* Description: Counter 4 down event select (1-greater than, 0-equa */ +#define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_SHFT 13 +#define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_MASK 0x0000000000002000 + +/* SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY */ +/* Description: Counter 4 down polarity select (1-negative edge, 0- */ +/* positive edge) */ +#define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_SHFT 14 +#define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_MASK 0x0000000000004000 + +/* SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE */ +/* Description: Counter 4 down mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_SHFT 15 +#define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_MASK 0x0000000000008000 + +/* SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE */ +/* Description: Counter 4 enable increment */ +#define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_SHFT 16 +#define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_MASK 0x0000000000010000 + +/* SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE */ +/* Description: Counter 4 enable decrement */ +#define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_SHFT 17 +#define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 + +/* SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE */ +/* Description: Counter 4 enable peak detection */ +#define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_SHFT 18 +#define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT5_CONTROL" */ +/* Performance Counter 5 Control */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNT5_CONTROL 0x00000001100d0000 +#define SH_PERFORMANCE_COUNT5_CONTROL_MASK 0x000000000007ffff +#define SH_PERFORMANCE_COUNT5_CONTROL_INIT 0x000000000000b8b8 + +/* SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS */ +/* Description: Counter 5 up stimulus */ +#define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_SHFT 0 +#define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_MASK 0x000000000000001f + +/* SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT */ +/* Description: Counter 5 up event select (1-greater than, 0-equal) */ +#define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_SHFT 5 +#define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_MASK 0x0000000000000020 + +/* SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY */ +/* Description: Counter 5 up polarity select (1-negative edge, 0-po */ +/* sitive edge) */ +#define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_SHFT 6 +#define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_MASK 0x0000000000000040 + +/* SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE */ +/* Description: Counter 5 up mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_SHFT 7 +#define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_MASK 0x0000000000000080 + +/* SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS */ +/* Description: Counter 5 down stimulus */ +#define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_SHFT 8 +#define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 + +/* SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT */ +/* Description: Counter 5 down event select (1-greater than, 0-equa */ +#define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_SHFT 13 +#define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_MASK 0x0000000000002000 + +/* SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY */ +/* Description: Counter 5 down polarity select (1-negative edge, 0- */ +/* positive edge) */ +#define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_SHFT 14 +#define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_MASK 0x0000000000004000 + +/* SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE */ +/* Description: Counter 5 down mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_SHFT 15 +#define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_MASK 0x0000000000008000 + +/* SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE */ +/* Description: Counter 5 enable increment */ +#define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_SHFT 16 +#define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_MASK 0x0000000000010000 + +/* SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE */ +/* Description: Counter 5 enable decrement */ +#define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_SHFT 17 +#define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 + +/* SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE */ +/* Description: Counter 5 enable peak detection */ +#define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_SHFT 18 +#define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT6_CONTROL" */ +/* Performance Counter 6 Control */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNT6_CONTROL 0x00000001100e0000 +#define SH_PERFORMANCE_COUNT6_CONTROL_MASK 0x000000000007ffff +#define SH_PERFORMANCE_COUNT6_CONTROL_INIT 0x000000000000b8b8 + +/* SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS */ +/* Description: Counter 6 up stimulus */ +#define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_SHFT 0 +#define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_MASK 0x000000000000001f + +/* SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT */ +/* Description: Counter 6 up event select (1-greater than, 0-equal) */ +#define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_SHFT 5 +#define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_MASK 0x0000000000000020 + +/* SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY */ +/* Description: Counter 6 up polarity select (1-negative edge, 0-po */ +/* sitive edge) */ +#define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_SHFT 6 +#define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_MASK 0x0000000000000040 + +/* SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE */ +/* Description: Counter 6 up mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_SHFT 7 +#define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_MASK 0x0000000000000080 + +/* SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS */ +/* Description: Counter 6 down stimulus */ +#define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_SHFT 8 +#define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 + +/* SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT */ +/* Description: Counter 6 down event select (1-greater than, 0-equa */ +#define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_SHFT 13 +#define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_MASK 0x0000000000002000 + +/* SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY */ +/* Description: Counter 6 down polarity select (1-negative edge, 0- */ +/* positive edge) */ +#define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_SHFT 14 +#define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_MASK 0x0000000000004000 + +/* SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE */ +/* Description: Counter 6 down mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_SHFT 15 +#define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_MASK 0x0000000000008000 + +/* SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE */ +/* Description: Counter 6 enable increment */ +#define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_SHFT 16 +#define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_MASK 0x0000000000010000 + +/* SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE */ +/* Description: Counter 6 enable decrement */ +#define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_SHFT 17 +#define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 + +/* SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE */ +/* Description: Counter 6 enable peak detection */ +#define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_SHFT 18 +#define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT7_CONTROL" */ +/* Performance Counter 7 Control */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNT7_CONTROL 0x00000001100f0000 +#define SH_PERFORMANCE_COUNT7_CONTROL_MASK 0x000000000007ffff +#define SH_PERFORMANCE_COUNT7_CONTROL_INIT 0x000000000000b8b8 + +/* SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS */ +/* Description: Counter 7 up stimulus */ +#define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_SHFT 0 +#define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_MASK 0x000000000000001f + +/* SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT */ +/* Description: Counter 7 up event select (1-greater than, 0-equal) */ +#define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_SHFT 5 +#define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_MASK 0x0000000000000020 + +/* SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY */ +/* Description: Counter 7 up polarity select (1-negative edge, 0-po */ +/* sitive edge) */ +#define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_SHFT 6 +#define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_MASK 0x0000000000000040 + +/* SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE */ +/* Description: Counter 7 up mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_SHFT 7 +#define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_MASK 0x0000000000000080 + +/* SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS */ +/* Description: Counter 7 down stimulus */ +#define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_SHFT 8 +#define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00 + +/* SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT */ +/* Description: Counter 7 down event select (1-greater than, 0-equa */ +#define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_SHFT 13 +#define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_MASK 0x0000000000002000 + +/* SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY */ +/* Description: Counter 7 down polarity select (1-negative edge, 0- */ +/* positive edge) */ +#define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_SHFT 14 +#define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_MASK 0x0000000000004000 + +/* SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE */ +/* Description: Counter 7 down mode select (1-internal, 0-external) */ +#define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_SHFT 15 +#define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_MASK 0x0000000000008000 + +/* SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE */ +/* Description: Counter 7 enable increment */ +#define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_SHFT 16 +#define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_MASK 0x0000000000010000 + +/* SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE */ +/* Description: Counter 7 enable decrement */ +#define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_SHFT 17 +#define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_MASK 0x0000000000020000 + +/* SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE */ +/* Description: Counter 7 enable peak detection */ +#define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_SHFT 18 +#define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000 + +/* ==================================================================== */ +/* Register "SH_PROFILE_DN_CONTROL" */ +/* Profile Counter Down Control */ +/* ==================================================================== */ + +#define SH_PROFILE_DN_CONTROL 0x0000000110100000 +#define SH_PROFILE_DN_CONTROL_MASK 0x00000000000000ff +#define SH_PROFILE_DN_CONTROL_INIT 0x00000000000000b8 + +/* SH_PROFILE_DN_CONTROL_STIMULUS */ +/* Description: Counter stimulus */ +#define SH_PROFILE_DN_CONTROL_STIMULUS_SHFT 0 +#define SH_PROFILE_DN_CONTROL_STIMULUS_MASK 0x000000000000001f + +/* SH_PROFILE_DN_CONTROL_EVENT */ +/* Description: Counter event select (1-greater than, 0-equal) */ +#define SH_PROFILE_DN_CONTROL_EVENT_SHFT 5 +#define SH_PROFILE_DN_CONTROL_EVENT_MASK 0x0000000000000020 + +/* SH_PROFILE_DN_CONTROL_POLARITY */ +/* Description: Counter polarity select (1-negative edge, 0-positiv */ +/* e edge) */ +#define SH_PROFILE_DN_CONTROL_POLARITY_SHFT 6 +#define SH_PROFILE_DN_CONTROL_POLARITY_MASK 0x0000000000000040 + +/* SH_PROFILE_DN_CONTROL_MODE */ +/* Description: Counter mode select (1-internal, 0-external) */ +#define SH_PROFILE_DN_CONTROL_MODE_SHFT 7 +#define SH_PROFILE_DN_CONTROL_MODE_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_PROFILE_PEAK_CONTROL" */ +/* Profile Counter Peak Control */ +/* ==================================================================== */ + +#define SH_PROFILE_PEAK_CONTROL 0x0000000110100080 +#define SH_PROFILE_PEAK_CONTROL_MASK 0x0000000000000068 +#define SH_PROFILE_PEAK_CONTROL_INIT 0x0000000000000060 + +/* SH_PROFILE_PEAK_CONTROL_STIMULUS */ +/* Description: Counter stimulus */ +#define SH_PROFILE_PEAK_CONTROL_STIMULUS_SHFT 3 +#define SH_PROFILE_PEAK_CONTROL_STIMULUS_MASK 0x0000000000000008 + +/* SH_PROFILE_PEAK_CONTROL_EVENT */ +/* Description: Counter event select (0-greater than, 1-equal) */ +#define SH_PROFILE_PEAK_CONTROL_EVENT_SHFT 5 +#define SH_PROFILE_PEAK_CONTROL_EVENT_MASK 0x0000000000000020 + +/* SH_PROFILE_PEAK_CONTROL_POLARITY */ +/* Description: Counter polarity select (0-negative edge, 1-positiv */ +/* e edge) */ +#define SH_PROFILE_PEAK_CONTROL_POLARITY_SHFT 6 +#define SH_PROFILE_PEAK_CONTROL_POLARITY_MASK 0x0000000000000040 + +/* ==================================================================== */ +/* Register "SH_PROFILE_RANGE" */ +/* Profile Counter Range */ +/* ==================================================================== */ + +#define SH_PROFILE_RANGE 0x0000000110100100 +#define SH_PROFILE_RANGE_MASK 0xffffffffffffffff +#define SH_PROFILE_RANGE_INIT 0x0000000000000000 + +/* SH_PROFILE_RANGE_RANGE0 */ +/* Description: Profiling range 0 */ +#define SH_PROFILE_RANGE_RANGE0_SHFT 0 +#define SH_PROFILE_RANGE_RANGE0_MASK 0x00000000000000ff + +/* SH_PROFILE_RANGE_RANGE1 */ +/* Description: Profiling range 1 */ +#define SH_PROFILE_RANGE_RANGE1_SHFT 8 +#define SH_PROFILE_RANGE_RANGE1_MASK 0x000000000000ff00 + +/* SH_PROFILE_RANGE_RANGE2 */ +/* Description: Profiling range 2 */ +#define SH_PROFILE_RANGE_RANGE2_SHFT 16 +#define SH_PROFILE_RANGE_RANGE2_MASK 0x0000000000ff0000 + +/* SH_PROFILE_RANGE_RANGE3 */ +/* Description: Profiling range 3 */ +#define SH_PROFILE_RANGE_RANGE3_SHFT 24 +#define SH_PROFILE_RANGE_RANGE3_MASK 0x00000000ff000000 + +/* SH_PROFILE_RANGE_RANGE4 */ +/* Description: Profiling range 4 */ +#define SH_PROFILE_RANGE_RANGE4_SHFT 32 +#define SH_PROFILE_RANGE_RANGE4_MASK 0x000000ff00000000 + +/* SH_PROFILE_RANGE_RANGE5 */ +/* Description: Profiling range 5 */ +#define SH_PROFILE_RANGE_RANGE5_SHFT 40 +#define SH_PROFILE_RANGE_RANGE5_MASK 0x0000ff0000000000 + +/* SH_PROFILE_RANGE_RANGE6 */ +/* Description: Profiling range 6 */ +#define SH_PROFILE_RANGE_RANGE6_SHFT 48 +#define SH_PROFILE_RANGE_RANGE6_MASK 0x00ff000000000000 + +/* SH_PROFILE_RANGE_RANGE7 */ +/* Description: Profiling range 7 */ +#define SH_PROFILE_RANGE_RANGE7_SHFT 56 +#define SH_PROFILE_RANGE_RANGE7_MASK 0xff00000000000000 + +/* ==================================================================== */ +/* Register "SH_PROFILE_UP_CONTROL" */ +/* Profile Counter Up Control */ +/* ==================================================================== */ + +#define SH_PROFILE_UP_CONTROL 0x0000000110100180 +#define SH_PROFILE_UP_CONTROL_MASK 0x00000000000000ff +#define SH_PROFILE_UP_CONTROL_INIT 0x00000000000000b8 + +/* SH_PROFILE_UP_CONTROL_STIMULUS */ +/* Description: Counter stimulus */ +#define SH_PROFILE_UP_CONTROL_STIMULUS_SHFT 0 +#define SH_PROFILE_UP_CONTROL_STIMULUS_MASK 0x000000000000001f + +/* SH_PROFILE_UP_CONTROL_EVENT */ +/* Description: Counter event select (1-greater than, 0-equal) */ +#define SH_PROFILE_UP_CONTROL_EVENT_SHFT 5 +#define SH_PROFILE_UP_CONTROL_EVENT_MASK 0x0000000000000020 + +/* SH_PROFILE_UP_CONTROL_POLARITY */ +/* Description: Counter polarity select (1-negative edge, 0-positiv */ +/* e edge) */ +#define SH_PROFILE_UP_CONTROL_POLARITY_SHFT 6 +#define SH_PROFILE_UP_CONTROL_POLARITY_MASK 0x0000000000000040 + +/* SH_PROFILE_UP_CONTROL_MODE */ +/* Description: Counter mode select (1-internal, 0-external) */ +#define SH_PROFILE_UP_CONTROL_MODE_SHFT 7 +#define SH_PROFILE_UP_CONTROL_MODE_MASK 0x0000000000000080 + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER0" */ +/* Performance Counter 0 */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNTER0 0x0000000110110000 +#define SH_PERFORMANCE_COUNTER0_MASK 0x00000000ffffffff +#define SH_PERFORMANCE_COUNTER0_INIT 0x0000000000000000 + +/* SH_PERFORMANCE_COUNTER0_COUNT */ +/* Description: Counter 0 */ +#define SH_PERFORMANCE_COUNTER0_COUNT_SHFT 0 +#define SH_PERFORMANCE_COUNTER0_COUNT_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER1" */ +/* Performance Counter 1 */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNTER1 0x0000000110120000 +#define SH_PERFORMANCE_COUNTER1_MASK 0x00000000ffffffff +#define SH_PERFORMANCE_COUNTER1_INIT 0x0000000000000000 + +/* SH_PERFORMANCE_COUNTER1_COUNT */ +/* Description: Counter 1 */ +#define SH_PERFORMANCE_COUNTER1_COUNT_SHFT 0 +#define SH_PERFORMANCE_COUNTER1_COUNT_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER2" */ +/* Performance Counter 2 */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNTER2 0x0000000110130000 +#define SH_PERFORMANCE_COUNTER2_MASK 0x00000000ffffffff +#define SH_PERFORMANCE_COUNTER2_INIT 0x0000000000000000 + +/* SH_PERFORMANCE_COUNTER2_COUNT */ +/* Description: Counter 2 */ +#define SH_PERFORMANCE_COUNTER2_COUNT_SHFT 0 +#define SH_PERFORMANCE_COUNTER2_COUNT_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER3" */ +/* Performance Counter 3 */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNTER3 0x0000000110140000 +#define SH_PERFORMANCE_COUNTER3_MASK 0x00000000ffffffff +#define SH_PERFORMANCE_COUNTER3_INIT 0x0000000000000000 + +/* SH_PERFORMANCE_COUNTER3_COUNT */ +/* Description: Counter 3 */ +#define SH_PERFORMANCE_COUNTER3_COUNT_SHFT 0 +#define SH_PERFORMANCE_COUNTER3_COUNT_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER4" */ +/* Performance Counter 4 */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNTER4 0x0000000110150000 +#define SH_PERFORMANCE_COUNTER4_MASK 0x00000000ffffffff +#define SH_PERFORMANCE_COUNTER4_INIT 0x0000000000000000 + +/* SH_PERFORMANCE_COUNTER4_COUNT */ +/* Description: Counter 4 */ +#define SH_PERFORMANCE_COUNTER4_COUNT_SHFT 0 +#define SH_PERFORMANCE_COUNTER4_COUNT_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER5" */ +/* Performance Counter 5 */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNTER5 0x0000000110160000 +#define SH_PERFORMANCE_COUNTER5_MASK 0x00000000ffffffff +#define SH_PERFORMANCE_COUNTER5_INIT 0x0000000000000000 + +/* SH_PERFORMANCE_COUNTER5_COUNT */ +/* Description: Counter 5 */ +#define SH_PERFORMANCE_COUNTER5_COUNT_SHFT 0 +#define SH_PERFORMANCE_COUNTER5_COUNT_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER6" */ +/* Performance Counter 6 */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNTER6 0x0000000110170000 +#define SH_PERFORMANCE_COUNTER6_MASK 0x00000000ffffffff +#define SH_PERFORMANCE_COUNTER6_INIT 0x0000000000000000 + +/* SH_PERFORMANCE_COUNTER6_COUNT */ +/* Description: Counter 6 */ +#define SH_PERFORMANCE_COUNTER6_COUNT_SHFT 0 +#define SH_PERFORMANCE_COUNTER6_COUNT_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER7" */ +/* Performance Counter 7 */ +/* ==================================================================== */ + +#define SH_PERFORMANCE_COUNTER7 0x0000000110180000 +#define SH_PERFORMANCE_COUNTER7_MASK 0x00000000ffffffff +#define SH_PERFORMANCE_COUNTER7_INIT 0x0000000000000000 + +/* SH_PERFORMANCE_COUNTER7_COUNT */ +/* Description: Counter 7 */ +#define SH_PERFORMANCE_COUNTER7_COUNT_SHFT 0 +#define SH_PERFORMANCE_COUNTER7_COUNT_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_PROFILE_COUNTER" */ +/* Profile Counter */ +/* ==================================================================== */ + +#define SH_PROFILE_COUNTER 0x0000000110190000 +#define SH_PROFILE_COUNTER_MASK 0x00000000000000ff +#define SH_PROFILE_COUNTER_INIT 0x0000000000000000 + +/* SH_PROFILE_COUNTER_COUNTER */ +/* Description: Counter Value */ +#define SH_PROFILE_COUNTER_COUNTER_SHFT 0 +#define SH_PROFILE_COUNTER_COUNTER_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_PROFILE_PEAK" */ +/* Profile Peak Counter */ +/* ==================================================================== */ + +#define SH_PROFILE_PEAK 0x0000000110190080 +#define SH_PROFILE_PEAK_MASK 0x00000000000000ff +#define SH_PROFILE_PEAK_INIT 0x0000000000000000 + +/* SH_PROFILE_PEAK_COUNTER */ +/* Description: Counter Value */ +#define SH_PROFILE_PEAK_COUNTER_SHFT 0 +#define SH_PROFILE_PEAK_COUNTER_MASK 0x00000000000000ff + +/* ==================================================================== */ +/* Register "SH_PTC_0" */ +/* Puge Translation Cache Message Configuration Information */ +/* ==================================================================== */ + +#define SH_PTC_0 0x00000001101a0000 +#define SH_PTC_0_MASK 0x80000000fffffffd +#define SH_PTC_0_INIT 0x0000000000000000 + +/* SH_PTC_0_A */ +/* Description: Type */ +#define SH_PTC_0_A_SHFT 0 +#define SH_PTC_0_A_MASK 0x0000000000000001 + +/* SH_PTC_0_PS */ +/* Description: Page Size */ +#define SH_PTC_0_PS_SHFT 2 +#define SH_PTC_0_PS_MASK 0x00000000000000fc + +/* SH_PTC_0_RID */ +/* Description: Region ID */ +#define SH_PTC_0_RID_SHFT 8 +#define SH_PTC_0_RID_MASK 0x00000000ffffff00 + +/* SH_PTC_0_START */ +/* Description: Start */ +#define SH_PTC_0_START_SHFT 63 +#define SH_PTC_0_START_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PTC_1" */ +/* Puge Translation Cache Message Configuration Information */ +/* ==================================================================== */ + +#define SH_PTC_1 0x00000001101a0080 +#define SH_PTC_1_MASK 0x9ffffffffffff000 +#define SH_PTC_1_INIT 0x0000000000000000 + +/* SH_PTC_1_VPN */ +/* Description: Virtual page number */ +#define SH_PTC_1_VPN_SHFT 12 +#define SH_PTC_1_VPN_MASK 0x1ffffffffffff000 + +/* SH_PTC_1_START */ +/* Description: PTC_1 Start */ +#define SH_PTC_1_START_SHFT 63 +#define SH_PTC_1_START_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PTC_PARMS" */ +/* PTC Time-out parmaeters */ +/* ==================================================================== */ + +#define SH_PTC_PARMS 0x00000001101a0100 +#define SH_PTC_PARMS_MASK 0x0000000fffffffff +#define SH_PTC_PARMS_INIT 0x00000007ffffffff + +/* SH_PTC_PARMS_PTC_TO_WRAP */ +/* Description: PTC time-out period */ +#define SH_PTC_PARMS_PTC_TO_WRAP_SHFT 0 +#define SH_PTC_PARMS_PTC_TO_WRAP_MASK 0x0000000000ffffff + +/* SH_PTC_PARMS_PTC_TO_VAL */ +/* Description: PTC time-out valid */ +#define SH_PTC_PARMS_PTC_TO_VAL_SHFT 24 +#define SH_PTC_PARMS_PTC_TO_VAL_MASK 0x0000000fff000000 + +/* ==================================================================== */ +/* Register "SH_INT_CMPA" */ +/* RTC Compare Value for Processor A */ +/* ==================================================================== */ + +#define SH_INT_CMPA 0x00000001101b0000 +#define SH_INT_CMPA_MASK 0x007fffffffffffff +#define SH_INT_CMPA_INIT 0x0000000000000000 + +/* SH_INT_CMPA_REAL_TIME_CMPA */ +/* Description: Real Time Clock Compare */ +#define SH_INT_CMPA_REAL_TIME_CMPA_SHFT 0 +#define SH_INT_CMPA_REAL_TIME_CMPA_MASK 0x007fffffffffffff + +/* ==================================================================== */ +/* Register "SH_INT_CMPB" */ +/* RTC Compare Value for Processor B */ +/* ==================================================================== */ + +#define SH_INT_CMPB 0x00000001101b0080 +#define SH_INT_CMPB_MASK 0x007fffffffffffff +#define SH_INT_CMPB_INIT 0x0000000000000000 + +/* SH_INT_CMPB_REAL_TIME_CMPB */ +/* Description: Real Time Clock Compare */ +#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 +#define SH_INT_CMPB_REAL_TIME_CMPB_MASK 0x007fffffffffffff + +/* ==================================================================== */ +/* Register "SH_INT_CMPC" */ +/* RTC Compare Value for Processor C */ +/* ==================================================================== */ + +#define SH_INT_CMPC 0x00000001101b0100 +#define SH_INT_CMPC_MASK 0x007fffffffffffff +#define SH_INT_CMPC_INIT 0x0000000000000000 + +/* SH_INT_CMPC_REAL_TIME_CMPC */ +/* Description: Real Time Clock Compare */ +#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT 0 +#define SH_INT_CMPC_REAL_TIME_CMPC_MASK 0x007fffffffffffff + +/* ==================================================================== */ +/* Register "SH_INT_CMPD" */ +/* RTC Compare Value for Processor D */ +/* ==================================================================== */ + +#define SH_INT_CMPD 0x00000001101b0180 +#define SH_INT_CMPD_MASK 0x007fffffffffffff +#define SH_INT_CMPD_INIT 0x0000000000000000 + +/* SH_INT_CMPD_REAL_TIME_CMPD */ +/* Description: Real Time Clock Compare */ +#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 +#define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff + +/* ==================================================================== */ +/* Register "SH_INT_PROF" */ +/* Profile Compare Registers */ +/* ==================================================================== */ + +#define SH_INT_PROF 0x00000001101b0200 +#define SH_INT_PROF_MASK 0x00000000ffffffff +#define SH_INT_PROF_INIT 0x0000000000000000 + +/* SH_INT_PROF_PROFILE_COMPARE */ +/* Description: Profile Compare */ +#define SH_INT_PROF_PROFILE_COMPARE_SHFT 0 +#define SH_INT_PROF_PROFILE_COMPARE_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_RTC" */ +/* Real-time Clock */ +/* ==================================================================== */ + +#define SH_RTC 0x00000001101c0000 +#define SH_RTC_MASK 0x007fffffffffffff +#define SH_RTC_INIT 0x0000000000000000 + +/* SH_RTC_REAL_TIME_CLOCK */ +/* Description: Real-time Clock */ +#define SH_RTC_REAL_TIME_CLOCK_SHFT 0 +#define SH_RTC_REAL_TIME_CLOCK_MASK 0x007fffffffffffff + +/* ==================================================================== */ +/* Register "SH_SCRATCH0" */ +/* Scratch Register 0 */ +/* ==================================================================== */ + +#define SH_SCRATCH0 0x00000001101d0000 +#define SH_SCRATCH0_MASK 0xffffffffffffffff +#define SH_SCRATCH0_INIT 0x0000000000000000 + +/* SH_SCRATCH0_SCRATCH0 */ +/* Description: Scratch register 0 */ +#define SH_SCRATCH0_SCRATCH0_SHFT 0 +#define SH_SCRATCH0_SCRATCH0_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_SCRATCH0_ALIAS" */ +/* Scratch Register 0 Alias Address */ +/* ==================================================================== */ + +#define SH_SCRATCH0_ALIAS 0x00000001101d0008 + +/* ==================================================================== */ +/* Register "SH_SCRATCH1" */ +/* Scratch Register 1 */ +/* ==================================================================== */ + +#define SH_SCRATCH1 0x00000001101d0080 +#define SH_SCRATCH1_MASK 0xffffffffffffffff +#define SH_SCRATCH1_INIT 0x0000000000000000 + +/* SH_SCRATCH1_SCRATCH1 */ +/* Description: Scratch register 1 */ +#define SH_SCRATCH1_SCRATCH1_SHFT 0 +#define SH_SCRATCH1_SCRATCH1_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_SCRATCH1_ALIAS" */ +/* Scratch Register 1 Alias Address */ +/* ==================================================================== */ + +#define SH_SCRATCH1_ALIAS 0x00000001101d0088 + +/* ==================================================================== */ +/* Register "SH_SCRATCH2" */ +/* Scratch Register 2 */ +/* ==================================================================== */ + +#define SH_SCRATCH2 0x00000001101d0100 +#define SH_SCRATCH2_MASK 0xffffffffffffffff +#define SH_SCRATCH2_INIT 0x0000000000000000 + +/* SH_SCRATCH2_SCRATCH2 */ +/* Description: Scratch register 2 */ +#define SH_SCRATCH2_SCRATCH2_SHFT 0 +#define SH_SCRATCH2_SCRATCH2_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_SCRATCH2_ALIAS" */ +/* Scratch Register 2 Alias Address */ +/* ==================================================================== */ + +#define SH_SCRATCH2_ALIAS 0x00000001101d0108 + +/* ==================================================================== */ +/* Register "SH_SCRATCH3" */ +/* Scratch Register 3 */ +/* ==================================================================== */ + +#define SH_SCRATCH3 0x00000001101d0180 +#define SH_SCRATCH3_MASK 0x0000000000000001 +#define SH_SCRATCH3_INIT 0x0000000000000000 + +/* SH_SCRATCH3_SCRATCH3 */ +/* Description: Scratch register 3 */ +#define SH_SCRATCH3_SCRATCH3_SHFT 0 +#define SH_SCRATCH3_SCRATCH3_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_SCRATCH3_ALIAS" */ +/* Scratch Register 3 Alias Address */ +/* ==================================================================== */ + +#define SH_SCRATCH3_ALIAS 0x00000001101d0188 + +/* ==================================================================== */ +/* Register "SH_SCRATCH4" */ +/* Scratch Register 4 */ +/* ==================================================================== */ + +#define SH_SCRATCH4 0x00000001101d0200 +#define SH_SCRATCH4_MASK 0x0000000000000001 +#define SH_SCRATCH4_INIT 0x0000000000000000 + +/* SH_SCRATCH4_SCRATCH4 */ +/* Description: Scratch register 4 */ +#define SH_SCRATCH4_SCRATCH4_SHFT 0 +#define SH_SCRATCH4_SCRATCH4_MASK 0x0000000000000001 + +/* ==================================================================== */ +/* Register "SH_SCRATCH4_ALIAS" */ +/* Scratch Register 4 Alias Address */ +/* ==================================================================== */ + +#define SH_SCRATCH4_ALIAS 0x00000001101d0208 + +/* ==================================================================== */ +/* Register "SH_CRB_MESSAGE_CONTROL" */ +/* Coherent Request Buffer Message Control */ +/* ==================================================================== */ + +#define SH_CRB_MESSAGE_CONTROL 0x0000000120000000 +#define SH_CRB_MESSAGE_CONTROL_MASK 0xffffffff00000fff +#define SH_CRB_MESSAGE_CONTROL_INIT 0x0000000000000006 + +/* SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE */ +/* Description: System Coherence Enabled */ +#define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_SHFT 0 +#define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_MASK 0x0000000000000001 + +/* SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE */ +/* Description: Speculative Read Requests to Local Memory Enabled */ +#define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_SHFT 1 +#define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000002 + +/* SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE */ +/* Description: Speculative Read Requests to Remote Memory Enabled */ +#define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_SHFT 2 +#define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000004 + +/* SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR */ +/* Description: Define color of message */ +#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_SHFT 3 +#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_MASK 0x0000000000000008 + +/* SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE */ +/* Description: Enable color message processing */ +#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_SHFT 4 +#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_MASK 0x0000000000000010 + +/* SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */ +/* Description: Enable FSB RRB Mismatch check */ +#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 5 +#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000020 + +/* SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */ +/* Description: Enable FSB WRB Mismatch check */ +#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 6 +#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000040 + +/* SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE */ +/* Description: Enable FSB IRB Mismatch check */ +#define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 7 +#define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000080 + +/* SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE */ +/* Description: Enable XB RRB Mismatch check */ +#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 8 +#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000100 + +/* SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE */ +/* Description: Enable XB WRB Mismatch check */ +#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 9 +#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000200 + +/* SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES */ +/* Description: ignor residual write data */ +#define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_SHFT 10 +#define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_MASK 0x0000000000000400 + +/* SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION */ +/* Description: enable IVACK reply consolidation */ +#define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_SHFT 11 +#define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_MASK 0x0000000000000800 + +/* SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT */ +/* Description: IVACK stall counter */ +#define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_SHFT 32 +#define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_MASK 0x0000ffff00000000 + +/* SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL */ +/* Description: IVACK throttling limit/timer control */ +#define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_SHFT 48 +#define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_MASK 0xffff000000000000 + +/* ==================================================================== */ +/* Register "SH_CRB_NACK_LIMIT" */ +/* CRB Nack Limit */ +/* ==================================================================== */ + +#define SH_CRB_NACK_LIMIT 0x0000000120000080 +#define SH_CRB_NACK_LIMIT_MASK 0x800000000000ffff +#define SH_CRB_NACK_LIMIT_INIT 0x0000000000000000 + +/* SH_CRB_NACK_LIMIT_LIMIT */ +/* Description: Nack Count Limit */ +#define SH_CRB_NACK_LIMIT_LIMIT_SHFT 0 +#define SH_CRB_NACK_LIMIT_LIMIT_MASK 0x0000000000000fff + +/* SH_CRB_NACK_LIMIT_PRI_FREQ */ +/* Description: Frequency at which priority count is incremented */ +#define SH_CRB_NACK_LIMIT_PRI_FREQ_SHFT 12 +#define SH_CRB_NACK_LIMIT_PRI_FREQ_MASK 0x000000000000f000 + +/* SH_CRB_NACK_LIMIT_ENABLE */ +/* Description: Enable NACK limit detection */ +#define SH_CRB_NACK_LIMIT_ENABLE_SHFT 63 +#define SH_CRB_NACK_LIMIT_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_CRB_TIMEOUT_PRESCALE" */ +/* Coherent Request Buffer Timeout Prescale */ +/* ==================================================================== */ + +#define SH_CRB_TIMEOUT_PRESCALE 0x0000000120000100 +#define SH_CRB_TIMEOUT_PRESCALE_MASK 0x00000000ffffffff +#define SH_CRB_TIMEOUT_PRESCALE_INIT 0x0000000000000000 + +/* SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR */ +/* Description: CRB Time-out Prescale Factor */ +#define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_SHFT 0 +#define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_MASK 0x00000000ffffffff + +/* ==================================================================== */ +/* Register "SH_CRB_TIMEOUT_SKID" */ +/* Coherent Request Buffer Timeout Skid Limit */ +/* ==================================================================== */ + +#define SH_CRB_TIMEOUT_SKID 0x0000000120000180 +#define SH_CRB_TIMEOUT_SKID_MASK 0x800000000000003f +#define SH_CRB_TIMEOUT_SKID_INIT 0x0000000000000007 + +/* SH_CRB_TIMEOUT_SKID_SKID */ +/* Description: CRB Time-out Skid */ +#define SH_CRB_TIMEOUT_SKID_SKID_SHFT 0 +#define SH_CRB_TIMEOUT_SKID_SKID_MASK 0x000000000000003f + +/* SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT */ +/* Description: Reset Skid counter */ +#define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_SHFT 63 +#define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_MEMORY_WRITE_STATUS_0" */ +/* Memory Write Status for CPU 0 */ +/* ==================================================================== */ + +#define SH_MEMORY_WRITE_STATUS_0 0x0000000120070000 +#define SH_MEMORY_WRITE_STATUS_0_MASK 0x000000000000003f +#define SH_MEMORY_WRITE_STATUS_0_INIT 0x0000000000000000 + +/* SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT */ +/* Description: Pending Write Count */ +#define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 0 +#define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f + +/* ==================================================================== */ +/* Register "SH_MEMORY_WRITE_STATUS_1" */ +/* Memory Write Status for CPU 1 */ +/* ==================================================================== */ + +#define SH_MEMORY_WRITE_STATUS_1 0x0000000120070080 +#define SH_MEMORY_WRITE_STATUS_1_MASK 0x000000000000003f +#define SH_MEMORY_WRITE_STATUS_1_INIT 0x0000000000000000 + +/* SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT */ +/* Description: Pending Write Count */ +#define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 0 +#define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f + +/* ==================================================================== */ +/* Register "SH_PIO_WRITE_STATUS_0" */ +/* PIO Write Status for CPU 0 */ +/* ==================================================================== */ + +#define SH_PIO_WRITE_STATUS_0 0x0000000120070200 +#define SH_PIO_WRITE_STATUS_0_MASK 0xbf03ffffffffffff +#define SH_PIO_WRITE_STATUS_0_INIT 0x8000000000000000 + +/* SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR */ +/* Description: More than one PIO write error occured */ +#define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_SHFT 0 +#define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_MASK 0x0000000000000001 + +/* SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK */ +/* Description: Deaklock response detected */ +#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1 +#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK 0x0000000000000002 + +/* SH_PIO_WRITE_STATUS_0_WRITE_ERROR */ +/* Description: Error response detected */ +#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_SHFT 2 +#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_MASK 0x0000000000000004 + +/* SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS */ +/* Description: Address associated with error response */ +#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_SHFT 3 +#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8 + +/* SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT */ +/* Description: Count of currently pending PIO writes */ +#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56 +#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 + +/* SH_PIO_WRITE_STATUS_0_WRITES_OK */ +/* Description: No pending writes or errors */ +#define SH_PIO_WRITE_STATUS_0_WRITES_OK_SHFT 63 +#define SH_PIO_WRITE_STATUS_0_WRITES_OK_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PIO_WRITE_STATUS_1" */ +/* PIO Write Status for CPU 1 */ +/* ==================================================================== */ + +#define SH_PIO_WRITE_STATUS_1 0x0000000120070280 +#define SH_PIO_WRITE_STATUS_1_MASK 0xbf03ffffffffffff +#define SH_PIO_WRITE_STATUS_1_INIT 0x8000000000000000 + +/* SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR */ +/* Description: More than one PIO write error occured */ +#define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_SHFT 0 +#define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_MASK 0x0000000000000001 + +/* SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK */ +/* Description: Deaklock response detected */ +#define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_SHFT 1 +#define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_MASK 0x0000000000000002 + +/* SH_PIO_WRITE_STATUS_1_WRITE_ERROR */ +/* Description: Error response detected */ +#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_SHFT 2 +#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_MASK 0x0000000000000004 + +/* SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS */ +/* Description: Address associated with error response */ +#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_SHFT 3 +#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8 + +/* SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT */ +/* Description: Count of currently pending PIO writes */ +#define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 56 +#define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x3f00000000000000 + +/* SH_PIO_WRITE_STATUS_1_WRITES_OK */ +/* Description: No pending writes or errors */ +#define SH_PIO_WRITE_STATUS_1_WRITES_OK_SHFT 63 +#define SH_PIO_WRITE_STATUS_1_WRITES_OK_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_PIO_WRITE_STATUS_0_ALIAS" */ +/* ==================================================================== */ + +#define SH_PIO_WRITE_STATUS_0_ALIAS 0x0000000120070208 + +/* ==================================================================== */ +/* Register "SH_PIO_WRITE_STATUS_1_ALIAS" */ +/* ==================================================================== */ + +#define SH_PIO_WRITE_STATUS_1_ALIAS 0x0000000120070288 + +/* ==================================================================== */ +/* Register "SH_MEMORY_WRITE_STATUS_NON_USER_0" */ +/* Memory Write Status for CPU 0. OS access only */ +/* ==================================================================== */ + +#define SH_MEMORY_WRITE_STATUS_NON_USER_0 0x0000000120070400 +#define SH_MEMORY_WRITE_STATUS_NON_USER_0_MASK 0x800000000000003f +#define SH_MEMORY_WRITE_STATUS_NON_USER_0_INIT 0x0000000000000000 + +/* SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT */ +/* Description: Pending Write Count */ +#define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_SHFT 0 +#define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f + +/* SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR */ +/* Description: Clear pending write count */ +#define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_SHFT 63 +#define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_MEMORY_WRITE_STATUS_NON_USER_1" */ +/* Memory Write Status for CPU 1. OS access only */ +/* ==================================================================== */ + +#define SH_MEMORY_WRITE_STATUS_NON_USER_1 0x0000000120070480 +#define SH_MEMORY_WRITE_STATUS_NON_USER_1_MASK 0x800000000000003f +#define SH_MEMORY_WRITE_STATUS_NON_USER_1_INIT 0x0000000000000000 + +/* SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT */ +/* Description: Pending Write Count */ +#define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_SHFT 0 +#define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f + +/* SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR */ +/* Description: Clear pending write count */ +#define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_SHFT 63 +#define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_MMRBIST_ERR" */ +/* Error capture for bist read errors */ +/* ==================================================================== */ + +#define SH_MMRBIST_ERR 0x0000000100000080 +#define SH_MMRBIST_ERR_MASK 0x00000071ffffffff +#define SH_MMRBIST_ERR_INIT 0x0000000000000000 + +/* SH_MMRBIST_ERR_ADDR */ +/* Description: dword address of bist error */ +#define SH_MMRBIST_ERR_ADDR_SHFT 0 +#define SH_MMRBIST_ERR_ADDR_MASK 0x00000001ffffffff + +/* SH_MMRBIST_ERR_DETECTED */ +/* Description: error detected flag */ +#define SH_MMRBIST_ERR_DETECTED_SHFT 36 +#define SH_MMRBIST_ERR_DETECTED_MASK 0x0000001000000000 + +/* SH_MMRBIST_ERR_MULTIPLE_DETECTED */ +/* Description: multiple errors detected flag */ +#define SH_MMRBIST_ERR_MULTIPLE_DETECTED_SHFT 37 +#define SH_MMRBIST_ERR_MULTIPLE_DETECTED_MASK 0x0000002000000000 + +/* SH_MMRBIST_ERR_CANCELLED */ +/* Description: mmr/bist was cancelled */ +#define SH_MMRBIST_ERR_CANCELLED_SHFT 38 +#define SH_MMRBIST_ERR_CANCELLED_MASK 0x0000004000000000 + +/* ==================================================================== */ +/* Register "SH_MISC_ERR_HDR_LOWER" */ +/* Header capture register */ +/* ==================================================================== */ + +#define SH_MISC_ERR_HDR_LOWER 0x0000000100000088 +#define SH_MISC_ERR_HDR_LOWER_MASK 0x93fffffffffffff8 +#define SH_MISC_ERR_HDR_LOWER_INIT 0x0000000000000000 + +/* SH_MISC_ERR_HDR_LOWER_ADDR */ +/* Description: upper bits of reference address */ +#define SH_MISC_ERR_HDR_LOWER_ADDR_SHFT 3 +#define SH_MISC_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8 + +/* SH_MISC_ERR_HDR_LOWER_CMD */ +/* Description: command of reference */ +#define SH_MISC_ERR_HDR_LOWER_CMD_SHFT 36 +#define SH_MISC_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000 + +/* SH_MISC_ERR_HDR_LOWER_SRC */ +/* Description: source node of reference */ +#define SH_MISC_ERR_HDR_LOWER_SRC_SHFT 44 +#define SH_MISC_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000 + +/* SH_MISC_ERR_HDR_LOWER_WRITE */ +/* Description: reference is a write */ +#define SH_MISC_ERR_HDR_LOWER_WRITE_SHFT 60 +#define SH_MISC_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000 + +/* SH_MISC_ERR_HDR_LOWER_VALID */ +/* Description: set when capture occurs */ +#define SH_MISC_ERR_HDR_LOWER_VALID_SHFT 63 +#define SH_MISC_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_MISC_ERR_HDR_UPPER" */ +/* Error header capture packet and protocol errors */ +/* ==================================================================== */ + +#define SH_MISC_ERR_HDR_UPPER 0x0000000100000090 +#define SH_MISC_ERR_HDR_UPPER_MASK 0x000000001ff000ff +#define SH_MISC_ERR_HDR_UPPER_INIT 0x0000000000000000 + +/* SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL */ +/* Description: indicates a directory protocol error captured */ +#define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_SHFT 0 +#define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_MASK 0x0000000000000001 + +/* SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD */ +/* Description: indicates an illegal command error captured */ +#define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_SHFT 1 +#define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_MASK 0x0000000000000002 + +/* SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR */ +/* Description: indicates a non-existent memory error captured */ +#define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_SHFT 2 +#define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_MASK 0x0000000000000004 + +/* SH_MISC_ERR_HDR_UPPER_RMW_UC */ +/* Description: indicates an uncorrectable store rmw */ +#define SH_MISC_ERR_HDR_UPPER_RMW_UC_SHFT 3 +#define SH_MISC_ERR_HDR_UPPER_RMW_UC_MASK 0x0000000000000008 + +/* SH_MISC_ERR_HDR_UPPER_RMW_COR */ +/* Description: indicates a correctable store rmw */ +#define SH_MISC_ERR_HDR_UPPER_RMW_COR_SHFT 4 +#define SH_MISC_ERR_HDR_UPPER_RMW_COR_MASK 0x0000000000000010 + +/* SH_MISC_ERR_HDR_UPPER_DIR_ACC */ +/* Description: indicates a data request to directory memory error */ +/* captured */ +#define SH_MISC_ERR_HDR_UPPER_DIR_ACC_SHFT 5 +#define SH_MISC_ERR_HDR_UPPER_DIR_ACC_MASK 0x0000000000000020 + +/* SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE */ +/* Description: indicates a pkt size error from pi */ +#define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_SHFT 6 +#define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_MASK 0x0000000000000040 + +/* SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE */ +/* Description: indicates a pkt size error from xn */ +#define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_SHFT 7 +#define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_MASK 0x0000000000000080 + +/* SH_MISC_ERR_HDR_UPPER_ECHO */ +#define SH_MISC_ERR_HDR_UPPER_ECHO_SHFT 20 +#define SH_MISC_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000 + +/* ==================================================================== */ +/* Register "SH_DIR_UC_ERR_HDR_LOWER" */ +/* Header capture register */ +/* ==================================================================== */ + +#define SH_DIR_UC_ERR_HDR_LOWER 0x0000000100000098 +#define SH_DIR_UC_ERR_HDR_LOWER_MASK 0x93fffffffffffff8 +#define SH_DIR_UC_ERR_HDR_LOWER_INIT 0x0000000000000000 + +/* SH_DIR_UC_ERR_HDR_LOWER_ADDR */ +/* Description: upper bits of reference address */ +#define SH_DIR_UC_ERR_HDR_LOWER_ADDR_SHFT 3 +#define SH_DIR_UC_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8 + +/* SH_DIR_UC_ERR_HDR_LOWER_CMD */ +/* Description: command of reference */ +#define SH_DIR_UC_ERR_HDR_LOWER_CMD_SHFT 36 +#define SH_DIR_UC_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000 + +/* SH_DIR_UC_ERR_HDR_LOWER_SRC */ +/* Description: source node of reference */ +#define SH_DIR_UC_ERR_HDR_LOWER_SRC_SHFT 44 +#define SH_DIR_UC_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000 + +/* SH_DIR_UC_ERR_HDR_LOWER_WRITE */ +/* Description: reference is a write */ +#define SH_DIR_UC_ERR_HDR_LOWER_WRITE_SHFT 60 +#define SH_DIR_UC_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000 + +/* SH_DIR_UC_ERR_HDR_LOWER_VALID */ +/* Description: set when capture occurs */ +#define SH_DIR_UC_ERR_HDR_LOWER_VALID_SHFT 63 +#define SH_DIR_UC_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_DIR_UC_ERR_HDR_UPPER" */ +/* Error header capture packet and protocol errors */ +/* ==================================================================== */ + +#define SH_DIR_UC_ERR_HDR_UPPER 0x00000001000000a0 +#define SH_DIR_UC_ERR_HDR_UPPER_MASK 0x000000001ff00008 +#define SH_DIR_UC_ERR_HDR_UPPER_INIT 0x0000000000000000 + +/* SH_DIR_UC_ERR_HDR_UPPER_DIR_UC */ +/* Description: indicates uncorrectable directory error captured */ +#define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_SHFT 3 +#define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_MASK 0x0000000000000008 + +/* SH_DIR_UC_ERR_HDR_UPPER_ECHO */ +#define SH_DIR_UC_ERR_HDR_UPPER_ECHO_SHFT 20 +#define SH_DIR_UC_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000 + +/* ==================================================================== */ +/* Register "SH_DIR_COR_ERR_HDR_LOWER" */ +/* Header capture register */ +/* ==================================================================== */ + +#define SH_DIR_COR_ERR_HDR_LOWER 0x00000001000000a8 +#define SH_DIR_COR_ERR_HDR_LOWER_MASK 0x93fffffffffffff8 +#define SH_DIR_COR_ERR_HDR_LOWER_INIT 0x0000000000000000 + +/* SH_DIR_COR_ERR_HDR_LOWER_ADDR */ +/* Description: upper bits of reference address */ +#define SH_DIR_COR_ERR_HDR_LOWER_ADDR_SHFT 3 +#define SH_DIR_COR_ERR_HDR_LOWER_ADDR_MASK 0x0000000ffffffff8 + +/* SH_DIR_COR_ERR_HDR_LOWER_CMD */ +/* Description: command of reference */ +#define SH_DIR_COR_ERR_HDR_LOWER_CMD_SHFT 36 +#define SH_DIR_COR_ERR_HDR_LOWER_CMD_MASK 0x00000ff000000000 + +/* SH_DIR_COR_ERR_HDR_LOWER_SRC */ +/* Description: source node of reference */ +#define SH_DIR_COR_ERR_HDR_LOWER_SRC_SHFT 44 +#define SH_DIR_COR_ERR_HDR_LOWER_SRC_MASK 0x03fff00000000000 + +/* SH_DIR_COR_ERR_HDR_LOWER_WRITE */ +/* Description: reference is a write */ +#define SH_DIR_COR_ERR_HDR_LOWER_WRITE_SHFT 60 +#define SH_DIR_COR_ERR_HDR_LOWER_WRITE_MASK 0x1000000000000000 + +/* SH_DIR_COR_ERR_HDR_LOWER_VALID */ +/* Description: set when capture occurs */ +#define SH_DIR_COR_ERR_HDR_LOWER_VALID_SHFT 63 +#define SH_DIR_COR_ERR_HDR_LOWER_VALID_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_DIR_COR_ERR_HDR_UPPER" */ +/* Error header capture packet and protocol errors */ +/* ==================================================================== */ + +#define SH_DIR_COR_ERR_HDR_UPPER 0x00000001000000b0 +#define SH_DIR_COR_ERR_HDR_UPPER_MASK 0x000000001ff00100 +#define SH_DIR_COR_ERR_HDR_UPPER_INIT 0x0000000000000000 + +/* SH_DIR_COR_ERR_HDR_UPPER_DIR_COR */ +/* Description: indicates correctable directory error captured */ +#define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_SHFT 8 +#define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_MASK 0x0000000000000100 + +/* SH_DIR_COR_ERR_HDR_UPPER_ECHO */ +#define SH_DIR_COR_ERR_HDR_UPPER_ECHO_SHFT 20 +#define SH_DIR_COR_ERR_HDR_UPPER_ECHO_MASK 0x000000001ff00000 + +/* ==================================================================== */ +/* Register "SH_MEM_ERROR_SUMMARY" */ +/* Memory error flags */ +/* ==================================================================== */ + +#define SH_MEM_ERROR_SUMMARY 0x00000001000000b8 +#define SH_MEM_ERROR_SUMMARY_MASK 0x00000007f77777ff +#define SH_MEM_ERROR_SUMMARY_INIT 0x0000000000000000 + +/* SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD */ +/* Description: illegal command error */ +#define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_SHFT 0 +#define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_MASK 0x0000000000000001 + +/* SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR */ +/* Description: non-existent memory error */ +#define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_SHFT 1 +#define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_MASK 0x0000000000000002 + +/* SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR */ +/* Description: directory protocol error in dqlp */ +#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_SHFT 2 +#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_MASK 0x0000000000000004 + +/* SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR */ +/* Description: directory protocol error in dqrp */ +#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_SHFT 3 +#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_MASK 0x0000000000000008 + +/* SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC */ +/* Description: uncorrectable directory error in dqlp */ +#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_SHFT 4 +#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_MASK 0x0000000000000010 + +/* SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR */ +/* Description: correctable directory error in dqlp */ +#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_SHFT 5 +#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_MASK 0x0000000000000020 + +/* SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC */ +/* Description: uncorrectable directory error in dqrp */ +#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_SHFT 6 +#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_MASK 0x0000000000000040 + +/* SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR */ +/* Description: correctable directory error in dqrp */ +#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_SHFT 7 +#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_MASK 0x0000000000000080 + +/* SH_MEM_ERROR_SUMMARY_ACX_INT_HW */ +/* Description: hardware interrupt from acx */ +#define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_SHFT 8 +#define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_MASK 0x0000000000000100 + +/* SH_MEM_ERROR_SUMMARY_ACY_INT_HW */ +/* Description: hardware interrupt from acy */ +#define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_SHFT 9 +#define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_MASK 0x0000000000000200 + +/* SH_MEM_ERROR_SUMMARY_DIR_ACC */ +/* Description: directory memory access error */ +#define SH_MEM_ERROR_SUMMARY_DIR_ACC_SHFT 10 +#define SH_MEM_ERROR_SUMMARY_DIR_ACC_MASK 0x0000000000000400 + +/* SH_MEM_ERROR_SUMMARY_DQLP_INT_UC */ +/* Description: uncorrectable interrupt from dqlp */ +#define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_SHFT 12 +#define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_MASK 0x0000000000001000 + +/* SH_MEM_ERROR_SUMMARY_DQLP_INT_COR */ +/* Description: correctable interrupt from dqlp */ +#define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_SHFT 13 +#define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_MASK 0x0000000000002000 + +/* SH_MEM_ERROR_SUMMARY_DQLP_INT_HW */ +/* Description: hardware interrupt from dqlp */ +#define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_SHFT 14 +#define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_MASK 0x0000000000004000 + +/* SH_MEM_ERROR_SUMMARY_DQLS_INT_UC */ +/* Description: uncorrectable interrupt from dqls */ +#define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_SHFT 16 +#define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_MASK 0x0000000000010000 + +/* SH_MEM_ERROR_SUMMARY_DQLS_INT_COR */ +/* Description: correctable interrupt from dqls */ +#define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_SHFT 17 +#define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_MASK 0x0000000000020000 + +/* SH_MEM_ERROR_SUMMARY_DQLS_INT_HW */ +/* Description: hardware interrupt from dqls */ +#define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_SHFT 18 +#define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_MASK 0x0000000000040000 + +/* SH_MEM_ERROR_SUMMARY_DQRP_INT_UC */ +/* Description: uncorrectable interrupt from dqrp */ +#define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_SHFT 20 +#define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_MASK 0x0000000000100000 + +/* SH_MEM_ERROR_SUMMARY_DQRP_INT_COR */ +/* Description: correctable interrupt from dqrp */ +#define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_SHFT 21 +#define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_MASK 0x0000000000200000 + +/* SH_MEM_ERROR_SUMMARY_DQRP_INT_HW */ +/* Description: hardware interrupt from dqrp */ +#define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_SHFT 22 +#define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_MASK 0x0000000000400000 + +/* SH_MEM_ERROR_SUMMARY_DQRS_INT_UC */ +/* Description: uncorrectable interrupt from dqrs */ +#define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_SHFT 24 +#define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_MASK 0x0000000001000000 + +/* SH_MEM_ERROR_SUMMARY_DQRS_INT_COR */ +/* Description: correctable interrupt from dqrs */ +#define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_SHFT 25 +#define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_MASK 0x0000000002000000 + +/* SH_MEM_ERROR_SUMMARY_DQRS_INT_HW */ +/* Description: hardware interrupt from dqrs */ +#define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_SHFT 26 +#define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_MASK 0x0000000004000000 + +/* SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW */ +/* Description: too many reply packets came from pi */ +#define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_SHFT 28 +#define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_MASK 0x0000000010000000 + +/* SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW */ +/* Description: too many reply packets came from xn */ +#define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_SHFT 29 +#define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_MASK 0x0000000020000000 + +/* SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW */ +/* Description: too many request packets came from pi */ +#define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_SHFT 30 +#define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000 + +/* SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW */ +/* Description: too many request packets came from xn */ +#define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_SHFT 31 +#define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000 + +/* SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT */ +/* Description: red black scheme did not clean up soon enough */ +#define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_SHFT 32 +#define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000 + +/* SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE */ +/* Description: received data bearing packet from pi with wrong siz */ +#define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_SHFT 33 +#define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_MASK 0x0000000200000000 + +/* SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE */ +/* Description: received data bearing packet from xn with wrong siz */ +#define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_SHFT 34 +#define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_MEM_ERROR_SUMMARY_ALIAS" */ +/* Memory error flags clear alias */ +/* ==================================================================== */ + +#define SH_MEM_ERROR_SUMMARY_ALIAS 0x00000001000000c0 + +/* ==================================================================== */ +/* Register "SH_MEM_ERROR_OVERFLOW" */ +/* Memory error flags */ +/* ==================================================================== */ + +#define SH_MEM_ERROR_OVERFLOW 0x00000001000000c8 +#define SH_MEM_ERROR_OVERFLOW_MASK 0x00000007f77777ff +#define SH_MEM_ERROR_OVERFLOW_INIT 0x0000000000000000 + +/* SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD */ +/* Description: illegal command error */ +#define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_SHFT 0 +#define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_MASK 0x0000000000000001 + +/* SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR */ +/* Description: non-existent memory error */ +#define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_SHFT 1 +#define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_MASK 0x0000000000000002 + +/* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR */ +/* Description: directory protocol error in dqlp */ +#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_SHFT 2 +#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_MASK 0x0000000000000004 + +/* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR */ +/* Description: directory protocol error in dqrp */ +#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_SHFT 3 +#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_MASK 0x0000000000000008 + +/* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC */ +/* Description: uncorrectable directory error in dqlp */ +#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_SHFT 4 +#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_MASK 0x0000000000000010 + +/* SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR */ +/* Description: correctable directory error in dqlp */ +#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_SHFT 5 +#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_MASK 0x0000000000000020 + +/* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC */ +/* Description: uncorrectable directory error in dqrp */ +#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_SHFT 6 +#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_MASK 0x0000000000000040 + +/* SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR */ +/* Description: correctable directory error in dqrp */ +#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_SHFT 7 +#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_MASK 0x0000000000000080 + +/* SH_MEM_ERROR_OVERFLOW_ACX_INT_HW */ +/* Description: hardware interrupt from acx */ +#define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_SHFT 8 +#define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_MASK 0x0000000000000100 + +/* SH_MEM_ERROR_OVERFLOW_ACY_INT_HW */ +/* Description: hardware interrupt from acy */ +#define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_SHFT 9 +#define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_MASK 0x0000000000000200 + +/* SH_MEM_ERROR_OVERFLOW_DIR_ACC */ +/* Description: directory memory access error */ +#define SH_MEM_ERROR_OVERFLOW_DIR_ACC_SHFT 10 +#define SH_MEM_ERROR_OVERFLOW_DIR_ACC_MASK 0x0000000000000400 + +/* SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC */ +/* Description: uncorrectable interrupt from dqlp */ +#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_SHFT 12 +#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_MASK 0x0000000000001000 + +/* SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR */ +/* Description: correctable interrupt from dqlp */ +#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_SHFT 13 +#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_MASK 0x0000000000002000 + +/* SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW */ +/* Description: hardware interrupt from dqlp */ +#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_SHFT 14 +#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_MASK 0x0000000000004000 + +/* SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC */ +/* Description: uncorrectable interrupt from dqls */ +#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_SHFT 16 +#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_MASK 0x0000000000010000 + +/* SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR */ +/* Description: correctable interrupt from dqls */ +#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_SHFT 17 +#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_MASK 0x0000000000020000 + +/* SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW */ +/* Description: hardware interrupt from dqls */ +#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_SHFT 18 +#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_MASK 0x0000000000040000 + +/* SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC */ +/* Description: uncorrectable interrupt from dqrp */ +#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_SHFT 20 +#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_MASK 0x0000000000100000 + +/* SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR */ +/* Description: correctable interrupt from dqrp */ +#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_SHFT 21 +#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_MASK 0x0000000000200000 + +/* SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW */ +/* Description: hardware interrupt from dqrp */ +#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_SHFT 22 +#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_MASK 0x0000000000400000 + +/* SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC */ +/* Description: uncorrectable interrupt from dqrs */ +#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_SHFT 24 +#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_MASK 0x0000000001000000 + +/* SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR */ +/* Description: correctable interrupt from dqrs */ +#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_SHFT 25 +#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_MASK 0x0000000002000000 + +/* SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW */ +/* Description: hardware interrupt from dqrs */ +#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_SHFT 26 +#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_MASK 0x0000000004000000 + +/* SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW */ +/* Description: too many reply packets came from pi */ +#define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_SHFT 28 +#define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_MASK 0x0000000010000000 + +/* SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW */ +/* Description: too many reply packets came from xn */ +#define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_SHFT 29 +#define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_MASK 0x0000000020000000 + +/* SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW */ +/* Description: too many request packets came from pi */ +#define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_SHFT 30 +#define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000 + +/* SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW */ +/* Description: too many request packets came from xn */ +#define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_SHFT 31 +#define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000 + +/* SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT */ +/* Description: red black scheme did not clean up soon enough */ +#define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_SHFT 32 +#define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000 + +/* SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE */ +/* Description: received data bearing packet from pi with wrong siz */ +#define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_SHFT 33 +#define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_MASK 0x0000000200000000 + +/* SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE */ +/* Description: received data bearing packet from xn with wrong siz */ +#define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_SHFT 34 +#define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_MEM_ERROR_OVERFLOW_ALIAS" */ +/* Memory error flags clear alias */ +/* ==================================================================== */ + +#define SH_MEM_ERROR_OVERFLOW_ALIAS 0x00000001000000d0 + +/* ==================================================================== */ +/* Register "SH_MEM_ERROR_MASK" */ +/* Memory error flags */ +/* ==================================================================== */ + +#define SH_MEM_ERROR_MASK 0x00000001000000d8 +#define SH_MEM_ERROR_MASK_MASK 0x00000007f77777ff +#define SH_MEM_ERROR_MASK_INIT 0x00000007f77773ff + +/* SH_MEM_ERROR_MASK_ILLEGAL_CMD */ +/* Description: illegal command error */ +#define SH_MEM_ERROR_MASK_ILLEGAL_CMD_SHFT 0 +#define SH_MEM_ERROR_MASK_ILLEGAL_CMD_MASK 0x0000000000000001 + +/* SH_MEM_ERROR_MASK_NONEXIST_ADDR */ +/* Description: non-existent memory error */ +#define SH_MEM_ERROR_MASK_NONEXIST_ADDR_SHFT 1 +#define SH_MEM_ERROR_MASK_NONEXIST_ADDR_MASK 0x0000000000000002 + +/* SH_MEM_ERROR_MASK_DQLP_DIR_PERR */ +/* Description: directory protocol error in dqlp */ +#define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_SHFT 2 +#define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_MASK 0x0000000000000004 + +/* SH_MEM_ERROR_MASK_DQRP_DIR_PERR */ +/* Description: directory protocol error in dqrp */ +#define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_SHFT 3 +#define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_MASK 0x0000000000000008 + +/* SH_MEM_ERROR_MASK_DQLP_DIR_UC */ +/* Description: uncorrectable directory error in dqlp */ +#define SH_MEM_ERROR_MASK_DQLP_DIR_UC_SHFT 4 +#define SH_MEM_ERROR_MASK_DQLP_DIR_UC_MASK 0x0000000000000010 + +/* SH_MEM_ERROR_MASK_DQLP_DIR_COR */ +/* Description: correctable directory error in dqlp */ +#define SH_MEM_ERROR_MASK_DQLP_DIR_COR_SHFT 5 +#define SH_MEM_ERROR_MASK_DQLP_DIR_COR_MASK 0x0000000000000020 + +/* SH_MEM_ERROR_MASK_DQRP_DIR_UC */ +/* Description: uncorrectable directory error in dqrp */ +#define SH_MEM_ERROR_MASK_DQRP_DIR_UC_SHFT 6 +#define SH_MEM_ERROR_MASK_DQRP_DIR_UC_MASK 0x0000000000000040 + +/* SH_MEM_ERROR_MASK_DQRP_DIR_COR */ +/* Description: correctable directory error in dqrp */ +#define SH_MEM_ERROR_MASK_DQRP_DIR_COR_SHFT 7 +#define SH_MEM_ERROR_MASK_DQRP_DIR_COR_MASK 0x0000000000000080 + +/* SH_MEM_ERROR_MASK_ACX_INT_HW */ +/* Description: hardware interrupt from acx */ +#define SH_MEM_ERROR_MASK_ACX_INT_HW_SHFT 8 +#define SH_MEM_ERROR_MASK_ACX_INT_HW_MASK 0x0000000000000100 + +/* SH_MEM_ERROR_MASK_ACY_INT_HW */ +/* Description: hardware interrupt from acy */ +#define SH_MEM_ERROR_MASK_ACY_INT_HW_SHFT 9 +#define SH_MEM_ERROR_MASK_ACY_INT_HW_MASK 0x0000000000000200 + +/* SH_MEM_ERROR_MASK_DIR_ACC */ +/* Description: directory memory access error */ +#define SH_MEM_ERROR_MASK_DIR_ACC_SHFT 10 +#define SH_MEM_ERROR_MASK_DIR_ACC_MASK 0x0000000000000400 + +/* SH_MEM_ERROR_MASK_DQLP_INT_UC */ +/* Description: uncorrectable interrupt from dqlp */ +#define SH_MEM_ERROR_MASK_DQLP_INT_UC_SHFT 12 +#define SH_MEM_ERROR_MASK_DQLP_INT_UC_MASK 0x0000000000001000 + +/* SH_MEM_ERROR_MASK_DQLP_INT_COR */ +/* Description: correctable interrupt from dqlp */ +#define SH_MEM_ERROR_MASK_DQLP_INT_COR_SHFT 13 +#define SH_MEM_ERROR_MASK_DQLP_INT_COR_MASK 0x0000000000002000 + +/* SH_MEM_ERROR_MASK_DQLP_INT_HW */ +/* Description: hardware interrupt from dqlp */ +#define SH_MEM_ERROR_MASK_DQLP_INT_HW_SHFT 14 +#define SH_MEM_ERROR_MASK_DQLP_INT_HW_MASK 0x0000000000004000 + +/* SH_MEM_ERROR_MASK_DQLS_INT_UC */ +/* Description: uncorrectable interrupt from dqls */ +#define SH_MEM_ERROR_MASK_DQLS_INT_UC_SHFT 16 +#define SH_MEM_ERROR_MASK_DQLS_INT_UC_MASK 0x0000000000010000 + +/* SH_MEM_ERROR_MASK_DQLS_INT_COR */ +/* Description: correctable interrupt from dqls */ +#define SH_MEM_ERROR_MASK_DQLS_INT_COR_SHFT 17 +#define SH_MEM_ERROR_MASK_DQLS_INT_COR_MASK 0x0000000000020000 + +/* SH_MEM_ERROR_MASK_DQLS_INT_HW */ +/* Description: hardware interrupt from dqls */ +#define SH_MEM_ERROR_MASK_DQLS_INT_HW_SHFT 18 +#define SH_MEM_ERROR_MASK_DQLS_INT_HW_MASK 0x0000000000040000 + +/* SH_MEM_ERROR_MASK_DQRP_INT_UC */ +/* Description: uncorrectable interrupt from dqrp */ +#define SH_MEM_ERROR_MASK_DQRP_INT_UC_SHFT 20 +#define SH_MEM_ERROR_MASK_DQRP_INT_UC_MASK 0x0000000000100000 + +/* SH_MEM_ERROR_MASK_DQRP_INT_COR */ +/* Description: correctable interrupt from dqrp */ +#define SH_MEM_ERROR_MASK_DQRP_INT_COR_SHFT 21 +#define SH_MEM_ERROR_MASK_DQRP_INT_COR_MASK 0x0000000000200000 + +/* SH_MEM_ERROR_MASK_DQRP_INT_HW */ +/* Description: hardware interrupt from dqrp */ +#define SH_MEM_ERROR_MASK_DQRP_INT_HW_SHFT 22 +#define SH_MEM_ERROR_MASK_DQRP_INT_HW_MASK 0x0000000000400000 + +/* SH_MEM_ERROR_MASK_DQRS_INT_UC */ +/* Description: uncorrectable interrupt from dqrs */ +#define SH_MEM_ERROR_MASK_DQRS_INT_UC_SHFT 24 +#define SH_MEM_ERROR_MASK_DQRS_INT_UC_MASK 0x0000000001000000 + +/* SH_MEM_ERROR_MASK_DQRS_INT_COR */ +/* Description: correctable interrupt from dqrs */ +#define SH_MEM_ERROR_MASK_DQRS_INT_COR_SHFT 25 +#define SH_MEM_ERROR_MASK_DQRS_INT_COR_MASK 0x0000000002000000 + +/* SH_MEM_ERROR_MASK_DQRS_INT_HW */ +/* Description: hardware interrupt from dqrs */ +#define SH_MEM_ERROR_MASK_DQRS_INT_HW_SHFT 26 +#define SH_MEM_ERROR_MASK_DQRS_INT_HW_MASK 0x0000000004000000 + +/* SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW */ +/* Description: too many reply packets came from pi */ +#define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_SHFT 28 +#define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_MASK 0x0000000010000000 + +/* SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW */ +/* Description: too many reply packets came from xn */ +#define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_SHFT 29 +#define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_MASK 0x0000000020000000 + +/* SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW */ +/* Description: too many request packets came from pi */ +#define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_SHFT 30 +#define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000 + +/* SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW */ +/* Description: too many request packets came from xn */ +#define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_SHFT 31 +#define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000 + +/* SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT */ +/* Description: red black scheme did not clean up soon enough */ +#define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_SHFT 32 +#define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000 + +/* SH_MEM_ERROR_MASK_PI_PKT_SIZE */ +/* Description: received data bearing packet from pi with wrong siz */ +#define SH_MEM_ERROR_MASK_PI_PKT_SIZE_SHFT 33 +#define SH_MEM_ERROR_MASK_PI_PKT_SIZE_MASK 0x0000000200000000 + +/* SH_MEM_ERROR_MASK_XN_PKT_SIZE */ +/* Description: received data bearing packet from xn with wrong siz */ +#define SH_MEM_ERROR_MASK_XN_PKT_SIZE_SHFT 34 +#define SH_MEM_ERROR_MASK_XN_PKT_SIZE_MASK 0x0000000400000000 + +/* ==================================================================== */ +/* Register "SH_X_DIMM_CFG" */ +/* AC Mem Config Registers */ +/* ==================================================================== */ + +#define SH_X_DIMM_CFG 0x0000000100010000 +#define SH_X_DIMM_CFG_MASK 0x0000000f7f7f7f7f +#define SH_X_DIMM_CFG_INIT 0x000000026f4f2f0f + +/* SH_X_DIMM_CFG_DIMM0_SIZE */ +/* Description: DIMM 0 DRAM size */ +#define SH_X_DIMM_CFG_DIMM0_SIZE_SHFT 0 +#define SH_X_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007 + +/* SH_X_DIMM_CFG_DIMM0_2BK */ +/* Description: DIMM 0 has two physical banks */ +#define SH_X_DIMM_CFG_DIMM0_2BK_SHFT 3 +#define SH_X_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008 + +/* SH_X_DIMM_CFG_DIMM0_REV */ +/* Description: DIMM 0 physical banks reversed */ +#define SH_X_DIMM_CFG_DIMM0_REV_SHFT 4 +#define SH_X_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010 + +/* SH_X_DIMM_CFG_DIMM0_CS */ +/* Description: DIMM 0 chip select, addr[35:34] match */ +#define SH_X_DIMM_CFG_DIMM0_CS_SHFT 5 +#define SH_X_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060 + +/* SH_X_DIMM_CFG_DIMM1_SIZE */ +/* Description: DIMM 1 DRAM size */ +#define SH_X_DIMM_CFG_DIMM1_SIZE_SHFT 8 +#define SH_X_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700 + +/* SH_X_DIMM_CFG_DIMM1_2BK */ +/* Description: DIMM 1 has two physical banks */ +#define SH_X_DIMM_CFG_DIMM1_2BK_SHFT 11 +#define SH_X_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800 + +/* SH_X_DIMM_CFG_DIMM1_REV */ +/* Description: DIMM 1 physical banks reversed */ +#define SH_X_DIMM_CFG_DIMM1_REV_SHFT 12 +#define SH_X_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000 + +/* SH_X_DIMM_CFG_DIMM1_CS */ +/* Description: DIMM 1 chip select, addr[35:34] match */ +#define SH_X_DIMM_CFG_DIMM1_CS_SHFT 13 +#define SH_X_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000 + +/* SH_X_DIMM_CFG_DIMM2_SIZE */ +/* Description: DIMM 2 DRAM size */ +#define SH_X_DIMM_CFG_DIMM2_SIZE_SHFT 16 +#define SH_X_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000 + +/* SH_X_DIMM_CFG_DIMM2_2BK */ +/* Description: DIMM 2 has two physical banks */ +#define SH_X_DIMM_CFG_DIMM2_2BK_SHFT 19 +#define SH_X_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000 + +/* SH_X_DIMM_CFG_DIMM2_REV */ +/* Description: DIMM 2 physical banks reversed */ +#define SH_X_DIMM_CFG_DIMM2_REV_SHFT 20 +#define SH_X_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000 + +/* SH_X_DIMM_CFG_DIMM2_CS */ +/* Description: DIMM 2 chip select, addr[35:34] match */ +#define SH_X_DIMM_CFG_DIMM2_CS_SHFT 21 +#define SH_X_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000 + +/* SH_X_DIMM_CFG_DIMM3_SIZE */ +/* Description: DIMM 3 DRAM size */ +#define SH_X_DIMM_CFG_DIMM3_SIZE_SHFT 24 +#define SH_X_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000 + +/* SH_X_DIMM_CFG_DIMM3_2BK */ +/* Description: DIMM 3 has two physical banks */ +#define SH_X_DIMM_CFG_DIMM3_2BK_SHFT 27 +#define SH_X_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000 + +/* SH_X_DIMM_CFG_DIMM3_REV */ +/* Description: DIMM 3 physical banks reversed */ +#define SH_X_DIMM_CFG_DIMM3_REV_SHFT 28 +#define SH_X_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000 + +/* SH_X_DIMM_CFG_DIMM3_CS */ +/* Description: DIMM 3 chip select, addr[35:34] match */ +#define SH_X_DIMM_CFG_DIMM3_CS_SHFT 29 +#define SH_X_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000 + +/* SH_X_DIMM_CFG_FREQ */ +/* Description: DIMM frequency select */ +#define SH_X_DIMM_CFG_FREQ_SHFT 32 +#define SH_X_DIMM_CFG_FREQ_MASK 0x0000000f00000000 + +/* ==================================================================== */ +/* Register "SH_Y_DIMM_CFG" */ +/* AC Mem Config Registers */ +/* ==================================================================== */ + +#define SH_Y_DIMM_CFG 0x0000000100010008 +#define SH_Y_DIMM_CFG_MASK 0x0000000f7f7f7f7f +#define SH_Y_DIMM_CFG_INIT 0x000000026f4f2f0f + +/* SH_Y_DIMM_CFG_DIMM0_SIZE */ +/* Description: DIMM 0 DRAM size */ +#define SH_Y_DIMM_CFG_DIMM0_SIZE_SHFT 0 +#define SH_Y_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007 + +/* SH_Y_DIMM_CFG_DIMM0_2BK */ +/* Description: DIMM 0 has two physical banks */ +#define SH_Y_DIMM_CFG_DIMM0_2BK_SHFT 3 +#define SH_Y_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008 + +/* SH_Y_DIMM_CFG_DIMM0_REV */ +/* Description: DIMM 0 physical banks reversed */ +#define SH_Y_DIMM_CFG_DIMM0_REV_SHFT 4 +#define SH_Y_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010 + +/* SH_Y_DIMM_CFG_DIMM0_CS */ +/* Description: DIMM 0 chip select, addr[35:34] match */ +#define SH_Y_DIMM_CFG_DIMM0_CS_SHFT 5 +#define SH_Y_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060 + +/* SH_Y_DIMM_CFG_DIMM1_SIZE */ +/* Description: DIMM 1 DRAM size */ +#define SH_Y_DIMM_CFG_DIMM1_SIZE_SHFT 8 +#define SH_Y_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700 + +/* SH_Y_DIMM_CFG_DIMM1_2BK */ +/* Description: DIMM 1 has two physical banks */ +#define SH_Y_DIMM_CFG_DIMM1_2BK_SHFT 11 +#define SH_Y_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800 + +/* SH_Y_DIMM_CFG_DIMM1_REV */ +/* Description: DIMM 1 physical banks reversed */ +#define SH_Y_DIMM_CFG_DIMM1_REV_SHFT 12 +#define SH_Y_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000 + +/* SH_Y_DIMM_CFG_DIMM1_CS */ +/* Description: DIMM 1 chip select, addr[35:34] match */ +#define SH_Y_DIMM_CFG_DIMM1_CS_SHFT 13 +#define SH_Y_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000 + +/* SH_Y_DIMM_CFG_DIMM2_SIZE */ +/* Description: DIMM 2 DRAM size */ +#define SH_Y_DIMM_CFG_DIMM2_SIZE_SHFT 16 +#define SH_Y_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000 + +/* SH_Y_DIMM_CFG_DIMM2_2BK */ +/* Description: DIMM 2 has two physical banks */ +#define SH_Y_DIMM_CFG_DIMM2_2BK_SHFT 19 +#define SH_Y_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000 + +/* SH_Y_DIMM_CFG_DIMM2_REV */ +/* Description: DIMM 2 physical banks reversed */ +#define SH_Y_DIMM_CFG_DIMM2_REV_SHFT 20 +#define SH_Y_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000 + +/* SH_Y_DIMM_CFG_DIMM2_CS */ +/* Description: DIMM 2 chip select, addr[35:34] match */ +#define SH_Y_DIMM_CFG_DIMM2_CS_SHFT 21 +#define SH_Y_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000 + +/* SH_Y_DIMM_CFG_DIMM3_SIZE */ +/* Description: DIMM 3 DRAM size */ +#define SH_Y_DIMM_CFG_DIMM3_SIZE_SHFT 24 +#define SH_Y_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000 + +/* SH_Y_DIMM_CFG_DIMM3_2BK */ +/* Description: DIMM 3 has two physical banks */ +#define SH_Y_DIMM_CFG_DIMM3_2BK_SHFT 27 +#define SH_Y_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000 + +/* SH_Y_DIMM_CFG_DIMM3_REV */ +/* Description: DIMM 3 physical banks reversed */ +#define SH_Y_DIMM_CFG_DIMM3_REV_SHFT 28 +#define SH_Y_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000 + +/* SH_Y_DIMM_CFG_DIMM3_CS */ +/* Description: DIMM 3 chip select, addr[35:34] match */ +#define SH_Y_DIMM_CFG_DIMM3_CS_SHFT 29 +#define SH_Y_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000 + +/* SH_Y_DIMM_CFG_FREQ */ +/* Description: DIMM frequency select */ +#define SH_Y_DIMM_CFG_FREQ_SHFT 32 +#define SH_Y_DIMM_CFG_FREQ_MASK 0x0000000f00000000 + +/* ==================================================================== */ +/* Register "SH_JNR_DIMM_CFG" */ +/* AC Mem Config Registers */ +/* ==================================================================== */ + +#define SH_JNR_DIMM_CFG 0x0000000100010010 +#define SH_JNR_DIMM_CFG_MASK 0x0000000f7f7f7f7f +#define SH_JNR_DIMM_CFG_INIT 0x000000026f4f2f0f + +/* SH_JNR_DIMM_CFG_DIMM0_SIZE */ +/* Description: DIMM 0 DRAM size */ +#define SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT 0 +#define SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK 0x0000000000000007 + +/* SH_JNR_DIMM_CFG_DIMM0_2BK */ +/* Description: DIMM 0 has two physical banks */ +#define SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT 3 +#define SH_JNR_DIMM_CFG_DIMM0_2BK_MASK 0x0000000000000008 + +/* SH_JNR_DIMM_CFG_DIMM0_REV */ +/* Description: DIMM 0 physical banks reversed */ +#define SH_JNR_DIMM_CFG_DIMM0_REV_SHFT 4 +#define SH_JNR_DIMM_CFG_DIMM0_REV_MASK 0x0000000000000010 + +/* SH_JNR_DIMM_CFG_DIMM0_CS */ +/* Description: DIMM 0 chip select, addr[35:34] match */ +#define SH_JNR_DIMM_CFG_DIMM0_CS_SHFT 5 +#define SH_JNR_DIMM_CFG_DIMM0_CS_MASK 0x0000000000000060 + +/* SH_JNR_DIMM_CFG_DIMM1_SIZE */ +/* Description: DIMM 1 DRAM size */ +#define SH_JNR_DIMM_CFG_DIMM1_SIZE_SHFT 8 +#define SH_JNR_DIMM_CFG_DIMM1_SIZE_MASK 0x0000000000000700 + +/* SH_JNR_DIMM_CFG_DIMM1_2BK */ +/* Description: DIMM 1 has two physical banks */ +#define SH_JNR_DIMM_CFG_DIMM1_2BK_SHFT 11 +#define SH_JNR_DIMM_CFG_DIMM1_2BK_MASK 0x0000000000000800 + +/* SH_JNR_DIMM_CFG_DIMM1_REV */ +/* Description: DIMM 1 physical banks reversed */ +#define SH_JNR_DIMM_CFG_DIMM1_REV_SHFT 12 +#define SH_JNR_DIMM_CFG_DIMM1_REV_MASK 0x0000000000001000 + +/* SH_JNR_DIMM_CFG_DIMM1_CS */ +/* Description: DIMM 1 chip select, addr[35:34] match */ +#define SH_JNR_DIMM_CFG_DIMM1_CS_SHFT 13 +#define SH_JNR_DIMM_CFG_DIMM1_CS_MASK 0x0000000000006000 + +/* SH_JNR_DIMM_CFG_DIMM2_SIZE */ +/* Description: DIMM 2 DRAM size */ +#define SH_JNR_DIMM_CFG_DIMM2_SIZE_SHFT 16 +#define SH_JNR_DIMM_CFG_DIMM2_SIZE_MASK 0x0000000000070000 + +/* SH_JNR_DIMM_CFG_DIMM2_2BK */ +/* Description: DIMM 2 has two physical banks */ +#define SH_JNR_DIMM_CFG_DIMM2_2BK_SHFT 19 +#define SH_JNR_DIMM_CFG_DIMM2_2BK_MASK 0x0000000000080000 + +/* SH_JNR_DIMM_CFG_DIMM2_REV */ +/* Description: DIMM 2 physical banks reversed */ +#define SH_JNR_DIMM_CFG_DIMM2_REV_SHFT 20 +#define SH_JNR_DIMM_CFG_DIMM2_REV_MASK 0x0000000000100000 + +/* SH_JNR_DIMM_CFG_DIMM2_CS */ +/* Description: DIMM 2 chip select, addr[35:34] match */ +#define SH_JNR_DIMM_CFG_DIMM2_CS_SHFT 21 +#define SH_JNR_DIMM_CFG_DIMM2_CS_MASK 0x0000000000600000 + +/* SH_JNR_DIMM_CFG_DIMM3_SIZE */ +/* Description: DIMM 3 DRAM size */ +#define SH_JNR_DIMM_CFG_DIMM3_SIZE_SHFT 24 +#define SH_JNR_DIMM_CFG_DIMM3_SIZE_MASK 0x0000000007000000 + +/* SH_JNR_DIMM_CFG_DIMM3_2BK */ +/* Description: DIMM 3 has two physical banks */ +#define SH_JNR_DIMM_CFG_DIMM3_2BK_SHFT 27 +#define SH_JNR_DIMM_CFG_DIMM3_2BK_MASK 0x0000000008000000 + +/* SH_JNR_DIMM_CFG_DIMM3_REV */ +/* Description: DIMM 3 physical banks reversed */ +#define SH_JNR_DIMM_CFG_DIMM3_REV_SHFT 28 +#define SH_JNR_DIMM_CFG_DIMM3_REV_MASK 0x0000000010000000 + +/* SH_JNR_DIMM_CFG_DIMM3_CS */ +/* Description: DIMM 3 chip select, addr[35:34] match */ +#define SH_JNR_DIMM_CFG_DIMM3_CS_SHFT 29 +#define SH_JNR_DIMM_CFG_DIMM3_CS_MASK 0x0000000060000000 + +/* SH_JNR_DIMM_CFG_FREQ */ +/* Description: DIMM frequency select */ +#define SH_JNR_DIMM_CFG_FREQ_SHFT 32 +#define SH_JNR_DIMM_CFG_FREQ_MASK 0x0000000f00000000 + +/* ==================================================================== */ +/* Register "SH_X_PHASE_CFG" */ +/* AC Phase Config Registers */ +/* ==================================================================== */ + +#define SH_X_PHASE_CFG 0x0000000100010018 +#define SH_X_PHASE_CFG_MASK 0x7fffffffffffffff +#define SH_X_PHASE_CFG_INIT 0x0000000000000000 + +/* SH_X_PHASE_CFG_LD_A */ +/* Description: Address, control load core clock A latch */ +#define SH_X_PHASE_CFG_LD_A_SHFT 0 +#define SH_X_PHASE_CFG_LD_A_MASK 0x000000000000001f + +/* SH_X_PHASE_CFG_LD_B */ +/* Description: Address, control load core clock B latch */ +#define SH_X_PHASE_CFG_LD_B_SHFT 5 +#define SH_X_PHASE_CFG_LD_B_MASK 0x00000000000003e0 + +/* SH_X_PHASE_CFG_DQ_LD_A */ +/* Description: DATA MCI load core clock A latch */ +#define SH_X_PHASE_CFG_DQ_LD_A_SHFT 10 +#define SH_X_PHASE_CFG_DQ_LD_A_MASK 0x0000000000007c00 + +/* SH_X_PHASE_CFG_DQ_LD_B */ +/* Description: DATA MCI load core clock B latch */ +#define SH_X_PHASE_CFG_DQ_LD_B_SHFT 15 +#define SH_X_PHASE_CFG_DQ_LD_B_MASK 0x00000000000f8000 + +/* SH_X_PHASE_CFG_HOLD */ +/* Description: Hold request on core clock phase */ +#define SH_X_PHASE_CFG_HOLD_SHFT 20 +#define SH_X_PHASE_CFG_HOLD_MASK 0x0000000001f00000 + +/* SH_X_PHASE_CFG_HOLD_REQ */ +/* Description: Hold next request on core clock phase */ +#define SH_X_PHASE_CFG_HOLD_REQ_SHFT 25 +#define SH_X_PHASE_CFG_HOLD_REQ_MASK 0x000000003e000000 + +/* SH_X_PHASE_CFG_ADD_CP */ +/* Description: add delay clock period to dqct delay chain on phase */ +#define SH_X_PHASE_CFG_ADD_CP_SHFT 30 +#define SH_X_PHASE_CFG_ADD_CP_MASK 0x00000007c0000000 + +/* SH_X_PHASE_CFG_BUBBLE_EN */ +/* Description: bubble, idle core clock to wait for memory clock */ +#define SH_X_PHASE_CFG_BUBBLE_EN_SHFT 35 +#define SH_X_PHASE_CFG_BUBBLE_EN_MASK 0x000000f800000000 + +/* SH_X_PHASE_CFG_PHA_BUBBLE */ +/* Description: MMR phaseA bubble value */ +#define SH_X_PHASE_CFG_PHA_BUBBLE_SHFT 40 +#define SH_X_PHASE_CFG_PHA_BUBBLE_MASK 0x0000070000000000 + +/* SH_X_PHASE_CFG_PHB_BUBBLE */ +/* Description: MMR phaseB bubble value */ +#define SH_X_PHASE_CFG_PHB_BUBBLE_SHFT 43 +#define SH_X_PHASE_CFG_PHB_BUBBLE_MASK 0x0000380000000000 + +/* SH_X_PHASE_CFG_PHC_BUBBLE */ +/* Description: MMR phaseC bubble value */ +#define SH_X_PHASE_CFG_PHC_BUBBLE_SHFT 46 +#define SH_X_PHASE_CFG_PHC_BUBBLE_MASK 0x0001c00000000000 + +/* SH_X_PHASE_CFG_PHD_BUBBLE */ +/* Description: MMR phaseD bubble value */ +#define SH_X_PHASE_CFG_PHD_BUBBLE_SHFT 49 +#define SH_X_PHASE_CFG_PHD_BUBBLE_MASK 0x000e000000000000 + +/* SH_X_PHASE_CFG_PHE_BUBBLE */ +/* Description: MMR phaseE bubble value */ +#define SH_X_PHASE_CFG_PHE_BUBBLE_SHFT 52 +#define SH_X_PHASE_CFG_PHE_BUBBLE_MASK 0x0070000000000000 + +/* SH_X_PHASE_CFG_SEL_A */ +/* Description: address,control select A memory clock latch */ +#define SH_X_PHASE_CFG_SEL_A_SHFT 55 +#define SH_X_PHASE_CFG_SEL_A_MASK 0x0780000000000000 + +/* SH_X_PHASE_CFG_DQ_SEL_A */ +/* Description: DATA MCI select A memory clock latch */ +#define SH_X_PHASE_CFG_DQ_SEL_A_SHFT 59 +#define SH_X_PHASE_CFG_DQ_SEL_A_MASK 0x7800000000000000 + +/* ==================================================================== */ +/* Register "SH_X_CFG" */ +/* AC Config Registers */ +/* ==================================================================== */ + +#define SH_X_CFG 0x0000000100010020 +#define SH_X_CFG_MASK 0xffffffffffffffff +#define SH_X_CFG_INIT 0x108443103322100c + +/* SH_X_CFG_MODE_SERIAL */ +/* Description: Arbque arbitration in serial mode */ +#define SH_X_CFG_MODE_SERIAL_SHFT 0 +#define SH_X_CFG_MODE_SERIAL_MASK 0x0000000000000001 + +/* SH_X_CFG_DIRC_RANDOM_REPLACEMENT */ +/* Description: Directory cache random replacement */ +#define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_SHFT 1 +#define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_MASK 0x0000000000000002 + +/* SH_X_CFG_DIR_COUNTER_INIT */ +/* Description: Dir counter initial value */ +#define SH_X_CFG_DIR_COUNTER_INIT_SHFT 2 +#define SH_X_CFG_DIR_COUNTER_INIT_MASK 0x00000000000000fc + +/* SH_X_CFG_TA_DLYS */ +/* Description: Turn around delays */ +#define SH_X_CFG_TA_DLYS_SHFT 8 +#define SH_X_CFG_TA_DLYS_MASK 0x000000ffffffff00 + +/* SH_X_CFG_DA_BB_CLR */ +/* Description: Bank busy CPs for a data read request */ +#define SH_X_CFG_DA_BB_CLR_SHFT 40 +#define SH_X_CFG_DA_BB_CLR_MASK 0x00000f0000000000 + +/* SH_X_CFG_DC_BB_CLR */ +/* Description: Bank busy CPs for a directory cache read request */ +#define SH_X_CFG_DC_BB_CLR_SHFT 44 +#define SH_X_CFG_DC_BB_CLR_MASK 0x0000f00000000000 + +/* SH_X_CFG_WT_BB_CLR */ +/* Description: Bank busy CPs for all write request */ +#define SH_X_CFG_WT_BB_CLR_SHFT 48 +#define SH_X_CFG_WT_BB_CLR_MASK 0x000f000000000000 + +/* SH_X_CFG_SSO_WT_EN */ +/* Description: Simultaneous switching enabled on output data pins */ +#define SH_X_CFG_SSO_WT_EN_SHFT 52 +#define SH_X_CFG_SSO_WT_EN_MASK 0x0010000000000000 + +/* SH_X_CFG_TRCD2_EN */ +/* Description: Trcd, ras to cas delay of 2 CPs enabled */ +#define SH_X_CFG_TRCD2_EN_SHFT 53 +#define SH_X_CFG_TRCD2_EN_MASK 0x0020000000000000 + +/* SH_X_CFG_TRCD4_EN */ +/* Description: Trcd, ras to case delay of 4 CPs enabled */ +#define SH_X_CFG_TRCD4_EN_SHFT 54 +#define SH_X_CFG_TRCD4_EN_MASK 0x0040000000000000 + +/* SH_X_CFG_REQ_CNTR_DIS */ +/* Description: Request delay counter disabled */ +#define SH_X_CFG_REQ_CNTR_DIS_SHFT 55 +#define SH_X_CFG_REQ_CNTR_DIS_MASK 0x0080000000000000 + +/* SH_X_CFG_REQ_CNTR_VAL */ +/* Description: Request counter delay value in CPs */ +#define SH_X_CFG_REQ_CNTR_VAL_SHFT 56 +#define SH_X_CFG_REQ_CNTR_VAL_MASK 0x3f00000000000000 + +/* SH_X_CFG_INV_CAS_ADDR */ +/* Description: Invert cas address bits 3 to 7 */ +#define SH_X_CFG_INV_CAS_ADDR_SHFT 62 +#define SH_X_CFG_INV_CAS_ADDR_MASK 0x4000000000000000 + +/* SH_X_CFG_CLR_DIR_CACHE */ +/* Description: Clear directory cache tags */ +#define SH_X_CFG_CLR_DIR_CACHE_SHFT 63 +#define SH_X_CFG_CLR_DIR_CACHE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_X_DQCT_CFG" */ +/* AC Config Registers */ +/* ==================================================================== */ + +#define SH_X_DQCT_CFG 0x0000000100010028 +#define SH_X_DQCT_CFG_MASK 0x0000000000ffffff +#define SH_X_DQCT_CFG_INIT 0x0000000000585418 + +/* SH_X_DQCT_CFG_RD_SEL */ +/* Description: Read data select */ +#define SH_X_DQCT_CFG_RD_SEL_SHFT 0 +#define SH_X_DQCT_CFG_RD_SEL_MASK 0x000000000000000f + +/* SH_X_DQCT_CFG_WT_SEL */ +/* Description: Write data select */ +#define SH_X_DQCT_CFG_WT_SEL_SHFT 4 +#define SH_X_DQCT_CFG_WT_SEL_MASK 0x00000000000000f0 + +/* SH_X_DQCT_CFG_DTA_RD_SEL */ +/* Description: Data ready read select */ +#define SH_X_DQCT_CFG_DTA_RD_SEL_SHFT 8 +#define SH_X_DQCT_CFG_DTA_RD_SEL_MASK 0x0000000000000f00 + +/* SH_X_DQCT_CFG_DTA_WT_SEL */ +/* Description: Data ready write select */ +#define SH_X_DQCT_CFG_DTA_WT_SEL_SHFT 12 +#define SH_X_DQCT_CFG_DTA_WT_SEL_MASK 0x000000000000f000 + +/* SH_X_DQCT_CFG_DIR_RD_SEL */ +/* Description: Dir ready read select */ +#define SH_X_DQCT_CFG_DIR_RD_SEL_SHFT 16 +#define SH_X_DQCT_CFG_DIR_RD_SEL_MASK 0x00000000000f0000 + +/* SH_X_DQCT_CFG_MDIR_RD_SEL */ +/* Description: Dir ready read select */ +#define SH_X_DQCT_CFG_MDIR_RD_SEL_SHFT 20 +#define SH_X_DQCT_CFG_MDIR_RD_SEL_MASK 0x0000000000f00000 + +/* ==================================================================== */ +/* Register "SH_X_REFRESH_CONTROL" */ +/* Refresh Control Register */ +/* ==================================================================== */ + +#define SH_X_REFRESH_CONTROL 0x0000000100010030 +#define SH_X_REFRESH_CONTROL_MASK 0x000000000fffffff +#define SH_X_REFRESH_CONTROL_INIT 0x00000000009cc300 + +/* SH_X_REFRESH_CONTROL_ENABLE */ +/* Description: Refresh enable */ +#define SH_X_REFRESH_CONTROL_ENABLE_SHFT 0 +#define SH_X_REFRESH_CONTROL_ENABLE_MASK 0x00000000000000ff + +/* SH_X_REFRESH_CONTROL_INTERVAL */ +/* Description: Refresh interval in core CPs */ +#define SH_X_REFRESH_CONTROL_INTERVAL_SHFT 8 +#define SH_X_REFRESH_CONTROL_INTERVAL_MASK 0x000000000001ff00 + +/* SH_X_REFRESH_CONTROL_HOLD */ +/* Description: Refresh hold */ +#define SH_X_REFRESH_CONTROL_HOLD_SHFT 17 +#define SH_X_REFRESH_CONTROL_HOLD_MASK 0x00000000007e0000 + +/* SH_X_REFRESH_CONTROL_INTERLEAVE */ +/* Description: Refresh interleave */ +#define SH_X_REFRESH_CONTROL_INTERLEAVE_SHFT 23 +#define SH_X_REFRESH_CONTROL_INTERLEAVE_MASK 0x0000000000800000 + +/* SH_X_REFRESH_CONTROL_HALF_RATE */ +/* Description: Refresh half rate */ +#define SH_X_REFRESH_CONTROL_HALF_RATE_SHFT 24 +#define SH_X_REFRESH_CONTROL_HALF_RATE_MASK 0x000000000f000000 + +/* ==================================================================== */ +/* Register "SH_Y_PHASE_CFG" */ +/* AC Phase Config Registers */ +/* ==================================================================== */ + +#define SH_Y_PHASE_CFG 0x0000000100010038 +#define SH_Y_PHASE_CFG_MASK 0x7fffffffffffffff +#define SH_Y_PHASE_CFG_INIT 0x0000000000000000 + +/* SH_Y_PHASE_CFG_LD_A */ +/* Description: Address, control load core clock A latch */ +#define SH_Y_PHASE_CFG_LD_A_SHFT 0 +#define SH_Y_PHASE_CFG_LD_A_MASK 0x000000000000001f + +/* SH_Y_PHASE_CFG_LD_B */ +/* Description: Address, control load core clock B latch */ +#define SH_Y_PHASE_CFG_LD_B_SHFT 5 +#define SH_Y_PHASE_CFG_LD_B_MASK 0x00000000000003e0 + +/* SH_Y_PHASE_CFG_DQ_LD_A */ +/* Description: DATA MCI load core clock A latch */ +#define SH_Y_PHASE_CFG_DQ_LD_A_SHFT 10 +#define SH_Y_PHASE_CFG_DQ_LD_A_MASK 0x0000000000007c00 + +/* SH_Y_PHASE_CFG_DQ_LD_B */ +/* Description: DATA MCI load core clock B latch */ +#define SH_Y_PHASE_CFG_DQ_LD_B_SHFT 15 +#define SH_Y_PHASE_CFG_DQ_LD_B_MASK 0x00000000000f8000 + +/* SH_Y_PHASE_CFG_HOLD */ +/* Description: Hold request on core clock phase */ +#define SH_Y_PHASE_CFG_HOLD_SHFT 20 +#define SH_Y_PHASE_CFG_HOLD_MASK 0x0000000001f00000 + +/* SH_Y_PHASE_CFG_HOLD_REQ */ +/* Description: Hold next request on core clock phase */ +#define SH_Y_PHASE_CFG_HOLD_REQ_SHFT 25 +#define SH_Y_PHASE_CFG_HOLD_REQ_MASK 0x000000003e000000 + +/* SH_Y_PHASE_CFG_ADD_CP */ +/* Description: add delay clock period to dqct delay chain on phase */ +#define SH_Y_PHASE_CFG_ADD_CP_SHFT 30 +#define SH_Y_PHASE_CFG_ADD_CP_MASK 0x00000007c0000000 + +/* SH_Y_PHASE_CFG_BUBBLE_EN */ +/* Description: bubble, idle core clock to wait for memory clock */ +#define SH_Y_PHASE_CFG_BUBBLE_EN_SHFT 35 +#define SH_Y_PHASE_CFG_BUBBLE_EN_MASK 0x000000f800000000 + +/* SH_Y_PHASE_CFG_PHA_BUBBLE */ +/* Description: MMR phaseA bubble value */ +#define SH_Y_PHASE_CFG_PHA_BUBBLE_SHFT 40 +#define SH_Y_PHASE_CFG_PHA_BUBBLE_MASK 0x0000070000000000 + +/* SH_Y_PHASE_CFG_PHB_BUBBLE */ +/* Description: MMR phaseB bubble value */ +#define SH_Y_PHASE_CFG_PHB_BUBBLE_SHFT 43 +#define SH_Y_PHASE_CFG_PHB_BUBBLE_MASK 0x0000380000000000 + +/* SH_Y_PHASE_CFG_PHC_BUBBLE */ +/* Description: MMR phaseC bubble value */ +#define SH_Y_PHASE_CFG_PHC_BUBBLE_SHFT 46 +#define SH_Y_PHASE_CFG_PHC_BUBBLE_MASK 0x0001c00000000000 + +/* SH_Y_PHASE_CFG_PHD_BUBBLE */ +/* Description: MMR phaseD bubble value */ +#define SH_Y_PHASE_CFG_PHD_BUBBLE_SHFT 49 +#define SH_Y_PHASE_CFG_PHD_BUBBLE_MASK 0x000e000000000000 + +/* SH_Y_PHASE_CFG_PHE_BUBBLE */ +/* Description: MMR phaseE bubble value */ +#define SH_Y_PHASE_CFG_PHE_BUBBLE_SHFT 52 +#define SH_Y_PHASE_CFG_PHE_BUBBLE_MASK 0x0070000000000000 + +/* SH_Y_PHASE_CFG_SEL_A */ +/* Description: address,control select A memory clock latch */ +#define SH_Y_PHASE_CFG_SEL_A_SHFT 55 +#define SH_Y_PHASE_CFG_SEL_A_MASK 0x0780000000000000 + +/* SH_Y_PHASE_CFG_DQ_SEL_A */ +/* Description: DATA MCI select A memory clock latch */ +#define SH_Y_PHASE_CFG_DQ_SEL_A_SHFT 59 +#define SH_Y_PHASE_CFG_DQ_SEL_A_MASK 0x7800000000000000 + +/* ==================================================================== */ +/* Register "SH_Y_CFG" */ +/* AC Config Registers */ +/* ==================================================================== */ + +#define SH_Y_CFG 0x0000000100010040 +#define SH_Y_CFG_MASK 0xffffffffffffffff +#define SH_Y_CFG_INIT 0x108443103322100c + +/* SH_Y_CFG_MODE_SERIAL */ +/* Description: Arbque arbitration in serial mode */ +#define SH_Y_CFG_MODE_SERIAL_SHFT 0 +#define SH_Y_CFG_MODE_SERIAL_MASK 0x0000000000000001 + +/* SH_Y_CFG_DIRC_RANDOM_REPLACEMENT */ +/* Description: Directory cache random replacement */ +#define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_SHFT 1 +#define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_MASK 0x0000000000000002 + +/* SH_Y_CFG_DIR_COUNTER_INIT */ +/* Description: Dir counter initial value */ +#define SH_Y_CFG_DIR_COUNTER_INIT_SHFT 2 +#define SH_Y_CFG_DIR_COUNTER_INIT_MASK 0x00000000000000fc + +/* SH_Y_CFG_TA_DLYS */ +/* Description: Turn around delays */ +#define SH_Y_CFG_TA_DLYS_SHFT 8 +#define SH_Y_CFG_TA_DLYS_MASK 0x000000ffffffff00 + +/* SH_Y_CFG_DA_BB_CLR */ +/* Description: Bank busy CPs for a data read request */ +#define SH_Y_CFG_DA_BB_CLR_SHFT 40 +#define SH_Y_CFG_DA_BB_CLR_MASK 0x00000f0000000000 + +/* SH_Y_CFG_DC_BB_CLR */ +/* Description: Bank busy CPs for a directory cache read request */ +#define SH_Y_CFG_DC_BB_CLR_SHFT 44 +#define SH_Y_CFG_DC_BB_CLR_MASK 0x0000f00000000000 + +/* SH_Y_CFG_WT_BB_CLR */ +/* Description: Bank busy CPs for all write request */ +#define SH_Y_CFG_WT_BB_CLR_SHFT 48 +#define SH_Y_CFG_WT_BB_CLR_MASK 0x000f000000000000 + +/* SH_Y_CFG_SSO_WT_EN */ +/* Description: Simultaneous switching enabled on output data pins */ +#define SH_Y_CFG_SSO_WT_EN_SHFT 52 +#define SH_Y_CFG_SSO_WT_EN_MASK 0x0010000000000000 + +/* SH_Y_CFG_TRCD2_EN */ +/* Description: Trcd, ras to cas delay of 2 CPs enabled */ +#define SH_Y_CFG_TRCD2_EN_SHFT 53 +#define SH_Y_CFG_TRCD2_EN_MASK 0x0020000000000000 + +/* SH_Y_CFG_TRCD4_EN */ +/* Description: Trcd, ras to case delay of 4 CPs enabled */ +#define SH_Y_CFG_TRCD4_EN_SHFT 54 +#define SH_Y_CFG_TRCD4_EN_MASK 0x0040000000000000 + +/* SH_Y_CFG_REQ_CNTR_DIS */ +/* Description: Request delay counter disabled */ +#define SH_Y_CFG_REQ_CNTR_DIS_SHFT 55 +#define SH_Y_CFG_REQ_CNTR_DIS_MASK 0x0080000000000000 + +/* SH_Y_CFG_REQ_CNTR_VAL */ +/* Description: Request counter delay value in CPs */ +#define SH_Y_CFG_REQ_CNTR_VAL_SHFT 56 +#define SH_Y_CFG_REQ_CNTR_VAL_MASK 0x3f00000000000000 + +/* SH_Y_CFG_INV_CAS_ADDR */ +/* Description: Invert cas address bits 3 to 7 */ +#define SH_Y_CFG_INV_CAS_ADDR_SHFT 62 +#define SH_Y_CFG_INV_CAS_ADDR_MASK 0x4000000000000000 + +/* SH_Y_CFG_CLR_DIR_CACHE */ +/* Description: Clear directory cache tags */ +#define SH_Y_CFG_CLR_DIR_CACHE_SHFT 63 +#define SH_Y_CFG_CLR_DIR_CACHE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_Y_DQCT_CFG" */ +/* AC Config Registers */ +/* ==================================================================== */ + +#define SH_Y_DQCT_CFG 0x0000000100010048 +#define SH_Y_DQCT_CFG_MASK 0x0000000000ffffff +#define SH_Y_DQCT_CFG_INIT 0x0000000000585418 + +/* SH_Y_DQCT_CFG_RD_SEL */ +/* Description: Read data select */ +#define SH_Y_DQCT_CFG_RD_SEL_SHFT 0 +#define SH_Y_DQCT_CFG_RD_SEL_MASK 0x000000000000000f + +/* SH_Y_DQCT_CFG_WT_SEL */ +/* Description: Write data select */ +#define SH_Y_DQCT_CFG_WT_SEL_SHFT 4 +#define SH_Y_DQCT_CFG_WT_SEL_MASK 0x00000000000000f0 + +/* SH_Y_DQCT_CFG_DTA_RD_SEL */ +/* Description: Data ready read select */ +#define SH_Y_DQCT_CFG_DTA_RD_SEL_SHFT 8 +#define SH_Y_DQCT_CFG_DTA_RD_SEL_MASK 0x0000000000000f00 + +/* SH_Y_DQCT_CFG_DTA_WT_SEL */ +/* Description: Data ready write select */ +#define SH_Y_DQCT_CFG_DTA_WT_SEL_SHFT 12 +#define SH_Y_DQCT_CFG_DTA_WT_SEL_MASK 0x000000000000f000 + +/* SH_Y_DQCT_CFG_DIR_RD_SEL */ +/* Description: Dir ready read select */ +#define SH_Y_DQCT_CFG_DIR_RD_SEL_SHFT 16 +#define SH_Y_DQCT_CFG_DIR_RD_SEL_MASK 0x00000000000f0000 + +/* SH_Y_DQCT_CFG_MDIR_RD_SEL */ +/* Description: Dir ready read select */ +#define SH_Y_DQCT_CFG_MDIR_RD_SEL_SHFT 20 +#define SH_Y_DQCT_CFG_MDIR_RD_SEL_MASK 0x0000000000f00000 + +/* ==================================================================== */ +/* Register "SH_Y_REFRESH_CONTROL" */ +/* Refresh Control Register */ +/* ==================================================================== */ + +#define SH_Y_REFRESH_CONTROL 0x0000000100010050 +#define SH_Y_REFRESH_CONTROL_MASK 0x000000000fffffff +#define SH_Y_REFRESH_CONTROL_INIT 0x00000000009cc300 + +/* SH_Y_REFRESH_CONTROL_ENABLE */ +/* Description: Refresh enable */ +#define SH_Y_REFRESH_CONTROL_ENABLE_SHFT 0 +#define SH_Y_REFRESH_CONTROL_ENABLE_MASK 0x00000000000000ff + +/* SH_Y_REFRESH_CONTROL_INTERVAL */ +/* Description: Refresh interval in core CPs */ +#define SH_Y_REFRESH_CONTROL_INTERVAL_SHFT 8 +#define SH_Y_REFRESH_CONTROL_INTERVAL_MASK 0x000000000001ff00 + +/* SH_Y_REFRESH_CONTROL_HOLD */ +/* Description: Refresh hold */ +#define SH_Y_REFRESH_CONTROL_HOLD_SHFT 17 +#define SH_Y_REFRESH_CONTROL_HOLD_MASK 0x00000000007e0000 + +/* SH_Y_REFRESH_CONTROL_INTERLEAVE */ +/* Description: Refresh interleave */ +#define SH_Y_REFRESH_CONTROL_INTERLEAVE_SHFT 23 +#define SH_Y_REFRESH_CONTROL_INTERLEAVE_MASK 0x0000000000800000 + +/* SH_Y_REFRESH_CONTROL_HALF_RATE */ +/* Description: Refresh half rate */ +#define SH_Y_REFRESH_CONTROL_HALF_RATE_SHFT 24 +#define SH_Y_REFRESH_CONTROL_HALF_RATE_MASK 0x000000000f000000 + +/* ==================================================================== */ +/* Register "SH_MEM_RED_BLACK" */ +/* MD fairness watchdog timers */ +/* ==================================================================== */ + +#define SH_MEM_RED_BLACK 0x0000000100010058 +#define SH_MEM_RED_BLACK_MASK 0x000fffffffffffff +#define SH_MEM_RED_BLACK_INIT 0x0000000040000400 + +/* SH_MEM_RED_BLACK_TIME */ +/* Description: Clocks to tag references with a given color */ +#define SH_MEM_RED_BLACK_TIME_SHFT 0 +#define SH_MEM_RED_BLACK_TIME_MASK 0x000000000000ffff + +/* SH_MEM_RED_BLACK_ERR_TIME */ +/* Description: Max clocks to wait after red/black change for old c */ +/* olor to clear. */ +#define SH_MEM_RED_BLACK_ERR_TIME_SHFT 16 +#define SH_MEM_RED_BLACK_ERR_TIME_MASK 0x000fffffffff0000 + +/* ==================================================================== */ +/* Register "SH_MISC_MEM_CFG" */ +/* ==================================================================== */ + +#define SH_MISC_MEM_CFG 0x0000000100010060 +#define SH_MISC_MEM_CFG_MASK 0x0013f1f1fff3f3ff +#define SH_MISC_MEM_CFG_INIT 0x0000000000010107 + +/* SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE */ +/* Description: enables the use of express headers from md to pi */ +#define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_SHFT 0 +#define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_MASK 0x0000000000000001 + +/* SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE */ +/* Description: enables the use of speculative headers from md to p */ +#define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_SHFT 1 +#define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_MASK 0x0000000000000002 + +/* SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE */ +/* Description: enables bypass path for requests going through ac */ +#define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_SHFT 2 +#define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_MASK 0x0000000000000004 + +/* SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI */ +/* Description: disables a one clock delay of XN read data */ +#define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_SHFT 3 +#define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_MASK 0x0000000000000008 + +/* SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD */ +/* Description: point at which data writes get higher priority */ +#define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_SHFT 4 +#define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_MASK 0x00000000000003f0 + +/* SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD */ +/* Description: point at which dir cache writes get higher priority */ +#define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_SHFT 12 +#define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_MASK 0x000000000003f000 + +/* SH_MISC_MEM_CFG_THROTTLE_CNT */ +/* Description: number of clocks between accepting references */ +#define SH_MISC_MEM_CFG_THROTTLE_CNT_SHFT 20 +#define SH_MISC_MEM_CFG_THROTTLE_CNT_MASK 0x000000000ff00000 + +/* SH_MISC_MEM_CFG_DISABLED_READ_TNUMS */ +/* Description: number of read tnums to take out of circulation */ +#define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_SHFT 28 +#define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_MASK 0x00000001f0000000 + +/* SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS */ +/* Description: number of write tnums to take out of circulation */ +#define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_SHFT 36 +#define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_MASK 0x000001f000000000 + +/* SH_MISC_MEM_CFG_DISABLED_VICTIMS */ +/* Description: number of dir cache victim buffers to take out of c */ +/* irculation in each quadrant of the MD */ +#define SH_MISC_MEM_CFG_DISABLED_VICTIMS_SHFT 44 +#define SH_MISC_MEM_CFG_DISABLED_VICTIMS_MASK 0x0003f00000000000 + +/* SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE */ +/* Description: enables plane alternating for replies to XN */ +#define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_SHFT 52 +#define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_MASK 0x0010000000000000 + +/* ==================================================================== */ +/* Register "SH_PIO_RQ_CRD_CTL" */ +/* pio_rq Credit Circulation Control */ +/* ==================================================================== */ + +#define SH_PIO_RQ_CRD_CTL 0x0000000100010068 +#define SH_PIO_RQ_CRD_CTL_MASK 0x000000000000003f +#define SH_PIO_RQ_CRD_CTL_INIT 0x0000000000000002 + +/* SH_PIO_RQ_CRD_CTL_DEPTH */ +/* Description: Total depth of buffering (in sic packets) */ +#define SH_PIO_RQ_CRD_CTL_DEPTH_SHFT 0 +#define SH_PIO_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f + +/* ==================================================================== */ +/* Register "SH_PI_MD_RQ_CRD_CTL" */ +/* pi_md_rq Credit Circulation Control */ +/* ==================================================================== */ + +#define SH_PI_MD_RQ_CRD_CTL 0x0000000100010070 +#define SH_PI_MD_RQ_CRD_CTL_MASK 0x000000000000003f +#define SH_PI_MD_RQ_CRD_CTL_INIT 0x0000000000000008 + +/* SH_PI_MD_RQ_CRD_CTL_DEPTH */ +/* Description: Total depth of buffering (in sic packets) */ +#define SH_PI_MD_RQ_CRD_CTL_DEPTH_SHFT 0 +#define SH_PI_MD_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f + +/* ==================================================================== */ +/* Register "SH_PI_MD_RP_CRD_CTL" */ +/* pi_md_rp Credit Circulation Control */ +/* ==================================================================== */ + +#define SH_PI_MD_RP_CRD_CTL 0x0000000100010078 +#define SH_PI_MD_RP_CRD_CTL_MASK 0x000000000000003f +#define SH_PI_MD_RP_CRD_CTL_INIT 0x0000000000000004 + +/* SH_PI_MD_RP_CRD_CTL_DEPTH */ +/* Description: Total depth of buffering (in sic packets) */ +#define SH_PI_MD_RP_CRD_CTL_DEPTH_SHFT 0 +#define SH_PI_MD_RP_CRD_CTL_DEPTH_MASK 0x000000000000003f + +/* ==================================================================== */ +/* Register "SH_XN_MD_RQ_CRD_CTL" */ +/* xn_md_rq Credit Circulation Control */ +/* ==================================================================== */ + +#define SH_XN_MD_RQ_CRD_CTL 0x0000000100010080 +#define SH_XN_MD_RQ_CRD_CTL_MASK 0x000000000000003f +#define SH_XN_MD_RQ_CRD_CTL_INIT 0x0000000000000008 + +/* SH_XN_MD_RQ_CRD_CTL_DEPTH */ +/* Description: Total depth of buffering (in sic packets) */ +#define SH_XN_MD_RQ_CRD_CTL_DEPTH_SHFT 0 +#define SH_XN_MD_RQ_CRD_CTL_DEPTH_MASK 0x000000000000003f + +/* ==================================================================== */ +/* Register "SH_XN_MD_RP_CRD_CTL" */ +/* xn_md_rp Credit Circulation Control */ +/* ==================================================================== */ + +#define SH_XN_MD_RP_CRD_CTL 0x0000000100010088 +#define SH_XN_MD_RP_CRD_CTL_MASK 0x000000000000003f +#define SH_XN_MD_RP_CRD_CTL_INIT 0x0000000000000004 + +/* SH_XN_MD_RP_CRD_CTL_DEPTH */ +/* Description: Total depth of buffering (in sic packets) */ +#define SH_XN_MD_RP_CRD_CTL_DEPTH_SHFT 0 +#define SH_XN_MD_RP_CRD_CTL_DEPTH_MASK 0x000000000000003f + +/* ==================================================================== */ +/* Register "SH_X_TAG0" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_X_TAG0 0x0000000100020000 +#define SH_X_TAG0_MASK 0x00000000000fffff +#define SH_X_TAG0_INIT 0x0000000000000000 + +/* SH_X_TAG0_TAG */ +/* Description: Valid + Tag Address */ +#define SH_X_TAG0_TAG_SHFT 0 +#define SH_X_TAG0_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_X_TAG1" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_X_TAG1 0x0000000100020008 +#define SH_X_TAG1_MASK 0x00000000000fffff +#define SH_X_TAG1_INIT 0x0000000000000000 + +/* SH_X_TAG1_TAG */ +/* Description: Valid + Tag Address */ +#define SH_X_TAG1_TAG_SHFT 0 +#define SH_X_TAG1_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_X_TAG2" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_X_TAG2 0x0000000100020010 +#define SH_X_TAG2_MASK 0x00000000000fffff +#define SH_X_TAG2_INIT 0x0000000000000000 + +/* SH_X_TAG2_TAG */ +/* Description: Valid + Tag Address */ +#define SH_X_TAG2_TAG_SHFT 0 +#define SH_X_TAG2_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_X_TAG3" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_X_TAG3 0x0000000100020018 +#define SH_X_TAG3_MASK 0x00000000000fffff +#define SH_X_TAG3_INIT 0x0000000000000000 + +/* SH_X_TAG3_TAG */ +/* Description: Valid + Tag Address */ +#define SH_X_TAG3_TAG_SHFT 0 +#define SH_X_TAG3_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_X_TAG4" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_X_TAG4 0x0000000100020020 +#define SH_X_TAG4_MASK 0x00000000000fffff +#define SH_X_TAG4_INIT 0x0000000000000000 + +/* SH_X_TAG4_TAG */ +/* Description: Valid + Tag Address */ +#define SH_X_TAG4_TAG_SHFT 0 +#define SH_X_TAG4_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_X_TAG5" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_X_TAG5 0x0000000100020028 +#define SH_X_TAG5_MASK 0x00000000000fffff +#define SH_X_TAG5_INIT 0x0000000000000000 + +/* SH_X_TAG5_TAG */ +/* Description: Valid + Tag Address */ +#define SH_X_TAG5_TAG_SHFT 0 +#define SH_X_TAG5_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_X_TAG6" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_X_TAG6 0x0000000100020030 +#define SH_X_TAG6_MASK 0x00000000000fffff +#define SH_X_TAG6_INIT 0x0000000000000000 + +/* SH_X_TAG6_TAG */ +/* Description: Valid + Tag Address */ +#define SH_X_TAG6_TAG_SHFT 0 +#define SH_X_TAG6_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_X_TAG7" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_X_TAG7 0x0000000100020038 +#define SH_X_TAG7_MASK 0x00000000000fffff +#define SH_X_TAG7_INIT 0x0000000000000000 + +/* SH_X_TAG7_TAG */ +/* Description: Valid + Tag Address */ +#define SH_X_TAG7_TAG_SHFT 0 +#define SH_X_TAG7_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_Y_TAG0" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_Y_TAG0 0x0000000100020040 +#define SH_Y_TAG0_MASK 0x00000000000fffff +#define SH_Y_TAG0_INIT 0x0000000000000000 + +/* SH_Y_TAG0_TAG */ +/* Description: Valid + Tag Address */ +#define SH_Y_TAG0_TAG_SHFT 0 +#define SH_Y_TAG0_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_Y_TAG1" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_Y_TAG1 0x0000000100020048 +#define SH_Y_TAG1_MASK 0x00000000000fffff +#define SH_Y_TAG1_INIT 0x0000000000000000 + +/* SH_Y_TAG1_TAG */ +/* Description: Valid + Tag Address */ +#define SH_Y_TAG1_TAG_SHFT 0 +#define SH_Y_TAG1_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_Y_TAG2" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_Y_TAG2 0x0000000100020050 +#define SH_Y_TAG2_MASK 0x00000000000fffff +#define SH_Y_TAG2_INIT 0x0000000000000000 + +/* SH_Y_TAG2_TAG */ +/* Description: Valid + Tag Address */ +#define SH_Y_TAG2_TAG_SHFT 0 +#define SH_Y_TAG2_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_Y_TAG3" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_Y_TAG3 0x0000000100020058 +#define SH_Y_TAG3_MASK 0x00000000000fffff +#define SH_Y_TAG3_INIT 0x0000000000000000 + +/* SH_Y_TAG3_TAG */ +/* Description: Valid + Tag Address */ +#define SH_Y_TAG3_TAG_SHFT 0 +#define SH_Y_TAG3_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_Y_TAG4" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_Y_TAG4 0x0000000100020060 +#define SH_Y_TAG4_MASK 0x00000000000fffff +#define SH_Y_TAG4_INIT 0x0000000000000000 + +/* SH_Y_TAG4_TAG */ +/* Description: Valid + Tag Address */ +#define SH_Y_TAG4_TAG_SHFT 0 +#define SH_Y_TAG4_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_Y_TAG5" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_Y_TAG5 0x0000000100020068 +#define SH_Y_TAG5_MASK 0x00000000000fffff +#define SH_Y_TAG5_INIT 0x0000000000000000 + +/* SH_Y_TAG5_TAG */ +/* Description: Valid + Tag Address */ +#define SH_Y_TAG5_TAG_SHFT 0 +#define SH_Y_TAG5_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_Y_TAG6" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_Y_TAG6 0x0000000100020070 +#define SH_Y_TAG6_MASK 0x00000000000fffff +#define SH_Y_TAG6_INIT 0x0000000000000000 + +/* SH_Y_TAG6_TAG */ +/* Description: Valid + Tag Address */ +#define SH_Y_TAG6_TAG_SHFT 0 +#define SH_Y_TAG6_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_Y_TAG7" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#define SH_Y_TAG7 0x0000000100020078 +#define SH_Y_TAG7_MASK 0x00000000000fffff +#define SH_Y_TAG7_INIT 0x0000000000000000 + +/* SH_Y_TAG7_TAG */ +/* Description: Valid + Tag Address */ +#define SH_Y_TAG7_TAG_SHFT 0 +#define SH_Y_TAG7_TAG_MASK 0x00000000000fffff + +/* ==================================================================== */ +/* Register "SH_MMRBIST_BASE" */ +/* mmr/bist base address */ +/* ==================================================================== */ + +#define SH_MMRBIST_BASE 0x0000000100020080 +#define SH_MMRBIST_BASE_MASK 0x0003fffffffffff8 +#define SH_MMRBIST_BASE_INIT 0x0000000000000000 + +/* SH_MMRBIST_BASE_DWORD_ADDR */ +/* Description: bits 49:3 of the memory address */ +#define SH_MMRBIST_BASE_DWORD_ADDR_SHFT 3 +#define SH_MMRBIST_BASE_DWORD_ADDR_MASK 0x0003fffffffffff8 + +/* ==================================================================== */ +/* Register "SH_MMRBIST_CTL" */ +/* Bist base address */ +/* ==================================================================== */ + +#define SH_MMRBIST_CTL 0x0000000100020088 +#define SH_MMRBIST_CTL_MASK 0x0000177f7fffffff +#define SH_MMRBIST_CTL_INIT 0x0000000000000000 + +/* SH_MMRBIST_CTL_BLOCK_LENGTH */ +/* Description: number of dwords in operation */ +#define SH_MMRBIST_CTL_BLOCK_LENGTH_SHFT 0 +#define SH_MMRBIST_CTL_BLOCK_LENGTH_MASK 0x000000007fffffff + +/* SH_MMRBIST_CTL_CMD */ +/* Description: mmr/bist function */ +#define SH_MMRBIST_CTL_CMD_SHFT 32 +#define SH_MMRBIST_CTL_CMD_MASK 0x0000007f00000000 + +/* SH_MMRBIST_CTL_IN_PROGRESS */ +/* Description: writing a 1 starts operation, hardware clears on co */ +/* mpletion */ +#define SH_MMRBIST_CTL_IN_PROGRESS_SHFT 40 +#define SH_MMRBIST_CTL_IN_PROGRESS_MASK 0x0000010000000000 + +/* SH_MMRBIST_CTL_FAIL */ +/* Description: mmr/bist had a data or address error */ +#define SH_MMRBIST_CTL_FAIL_SHFT 41 +#define SH_MMRBIST_CTL_FAIL_MASK 0x0000020000000000 + +/* SH_MMRBIST_CTL_MEM_IDLE */ +/* Description: all memory activity is complete */ +#define SH_MMRBIST_CTL_MEM_IDLE_SHFT 42 +#define SH_MMRBIST_CTL_MEM_IDLE_MASK 0x0000040000000000 + +/* SH_MMRBIST_CTL_RESET_STATE */ +/* Description: writing a 1 resets mmrbist hardware, hardware clear */ +/* s on completion */ +#define SH_MMRBIST_CTL_RESET_STATE_SHFT 44 +#define SH_MMRBIST_CTL_RESET_STATE_MASK 0x0000100000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DBUG_DATA_CFG" */ +/* configuration for md debug data muxes */ +/* ==================================================================== */ + +#define SH_MD_DBUG_DATA_CFG 0x0000000100020100 +#define SH_MD_DBUG_DATA_CFG_MASK 0x7777777777777777 +#define SH_MD_DBUG_DATA_CFG_INIT 0x0000000000000000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET */ +/* Description: selects which md chiplet drives nibble0 */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_SHFT 0 +#define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_SHFT 4 +#define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_MASK 0x0000000000000070 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET */ +/* Description: selects which md chiplet drives nibble1 */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_SHFT 8 +#define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_SHFT 12 +#define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_MASK 0x0000000000007000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET */ +/* Description: selects which md chiplet drives nibble2 */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_SHFT 16 +#define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_SHFT 20 +#define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_MASK 0x0000000000700000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET */ +/* Description: selects which md chiplet drives nibble3 */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_SHFT 24 +#define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_SHFT 28 +#define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_MASK 0x0000000070000000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET */ +/* Description: selects which md chiplet drives nibble4 */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_SHFT 32 +#define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_SHFT 36 +#define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_MASK 0x0000007000000000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET */ +/* Description: selects which md chiplet drives nibble5 */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_SHFT 40 +#define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_SHFT 44 +#define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_MASK 0x0000700000000000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET */ +/* Description: selects which md chiplet drives nibble6 */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_SHFT 48 +#define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_SHFT 52 +#define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_MASK 0x0070000000000000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET */ +/* Description: selects which md chiplet drives nibble7 */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_SHFT 56 +#define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000 + +/* SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_SHFT 60 +#define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_MASK 0x7000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DBUG_TRIGGER_CFG" */ +/* configuration for md debug triggers */ +/* ==================================================================== */ + +#define SH_MD_DBUG_TRIGGER_CFG 0x0000000100020108 +#define SH_MD_DBUG_TRIGGER_CFG_MASK 0xf777777777777777 +#define SH_MD_DBUG_TRIGGER_CFG_INIT 0x0000000000000000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET */ +/* Description: selects which md chiplet drives nibble0 */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_SHFT 0 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_SHFT 4 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_MASK 0x0000000000000070 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET */ +/* Description: selects which md chiplet drives nibble1 */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_SHFT 8 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_SHFT 12 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_MASK 0x0000000000007000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET */ +/* Description: selects which md chiplet drives nibble2 */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_SHFT 16 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_SHFT 20 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_MASK 0x0000000000700000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET */ +/* Description: selects which md chiplet drives nibble3 */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_SHFT 24 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_SHFT 28 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_MASK 0x0000000070000000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET */ +/* Description: selects which md chiplet drives nibble4 */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_SHFT 32 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_SHFT 36 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_MASK 0x0000007000000000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET */ +/* Description: selects which md chiplet drives nibble5 */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_SHFT 40 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_SHFT 44 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_MASK 0x0000700000000000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET */ +/* Description: selects which md chiplet drives nibble6 */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_SHFT 48 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_SHFT 52 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_MASK 0x0070000000000000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET */ +/* Description: selects which md chiplet drives nibble7 */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_SHFT 56 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000 + +/* SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE */ +/* Description: selects which nibble from selected chiplet drives n */ +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_SHFT 60 +#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_MASK 0x7000000000000000 + +/* SH_MD_DBUG_TRIGGER_CFG_ENABLE */ +/* Description: enables triggering on pattern match */ +#define SH_MD_DBUG_TRIGGER_CFG_ENABLE_SHFT 63 +#define SH_MD_DBUG_TRIGGER_CFG_ENABLE_MASK 0x8000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DBUG_COMPARE" */ +/* md debug compare pattern and mask */ +/* ==================================================================== */ + +#define SH_MD_DBUG_COMPARE 0x0000000100020110 +#define SH_MD_DBUG_COMPARE_MASK 0xffffffffffffffff +#define SH_MD_DBUG_COMPARE_INIT 0x0000000000000000 + +/* SH_MD_DBUG_COMPARE_PATTERN */ +/* Description: pattern against which to compare dbug data for trig */ +#define SH_MD_DBUG_COMPARE_PATTERN_SHFT 0 +#define SH_MD_DBUG_COMPARE_PATTERN_MASK 0x00000000ffffffff + +/* SH_MD_DBUG_COMPARE_MASK */ +/* Description: bits to include in compare of dbug data for trigger */ +#define SH_MD_DBUG_COMPARE_MASK_SHFT 32 +#define SH_MD_DBUG_COMPARE_MASK_MASK 0xffffffff00000000 + +/* ==================================================================== */ +/* Register "SH_X_MOD_DBUG_SEL" */ +/* MD acx debug select */ +/* ==================================================================== */ + +#define SH_X_MOD_DBUG_SEL 0x0000000100020118 +#define SH_X_MOD_DBUG_SEL_MASK 0x03ffffffffffffff +#define SH_X_MOD_DBUG_SEL_INIT 0x0000000000000000 + +/* SH_X_MOD_DBUG_SEL_TAG_SEL */ +/* Description: tagmgr select */ +#define SH_X_MOD_DBUG_SEL_TAG_SEL_SHFT 0 +#define SH_X_MOD_DBUG_SEL_TAG_SEL_MASK 0x00000000000000ff + +/* SH_X_MOD_DBUG_SEL_WBQ_SEL */ +/* Description: wbqtg select */ +#define SH_X_MOD_DBUG_SEL_WBQ_SEL_SHFT 8 +#define SH_X_MOD_DBUG_SEL_WBQ_SEL_MASK 0x000000000000ff00 + +/* SH_X_MOD_DBUG_SEL_ARB_SEL */ +/* Description: arbque select */ +#define SH_X_MOD_DBUG_SEL_ARB_SEL_SHFT 16 +#define SH_X_MOD_DBUG_SEL_ARB_SEL_MASK 0x0000000000ff0000 + +/* SH_X_MOD_DBUG_SEL_ATL_SEL */ +/* Description: aintl select */ +#define SH_X_MOD_DBUG_SEL_ATL_SEL_SHFT 24 +#define SH_X_MOD_DBUG_SEL_ATL_SEL_MASK 0x00000007ff000000 + +/* SH_X_MOD_DBUG_SEL_ATR_SEL */ +/* Description: aintr select */ +#define SH_X_MOD_DBUG_SEL_ATR_SEL_SHFT 35 +#define SH_X_MOD_DBUG_SEL_ATR_SEL_MASK 0x00003ff800000000 + +/* SH_X_MOD_DBUG_SEL_DQL_SEL */ +/* Description: dqctr select */ +#define SH_X_MOD_DBUG_SEL_DQL_SEL_SHFT 46 +#define SH_X_MOD_DBUG_SEL_DQL_SEL_MASK 0x000fc00000000000 + +/* SH_X_MOD_DBUG_SEL_DQR_SEL */ +/* Description: dqctl select */ +#define SH_X_MOD_DBUG_SEL_DQR_SEL_SHFT 52 +#define SH_X_MOD_DBUG_SEL_DQR_SEL_MASK 0x03f0000000000000 + +/* ==================================================================== */ +/* Register "SH_X_DBUG_SEL" */ +/* MD acx debug select */ +/* ==================================================================== */ + +#define SH_X_DBUG_SEL 0x0000000100020120 +#define SH_X_DBUG_SEL_MASK 0x0000000000ffffff +#define SH_X_DBUG_SEL_INIT 0x0000000000000000 + +/* SH_X_DBUG_SEL_DBG_SEL */ +/* Description: debug select */ +#define SH_X_DBUG_SEL_DBG_SEL_SHFT 0 +#define SH_X_DBUG_SEL_DBG_SEL_MASK 0x0000000000ffffff + +/* ==================================================================== */ +/* Register "SH_X_LADDR_CMP" */ +/* MD acx address compare */ +/* ==================================================================== */ + +#define SH_X_LADDR_CMP 0x0000000100020128 +#define SH_X_LADDR_CMP_MASK 0x0fffffff0fffffff +#define SH_X_LADDR_CMP_INIT 0x0000000000000000 + +/* SH_X_LADDR_CMP_CMP_VAL */ +/* Description: Compare value */ +#define SH_X_LADDR_CMP_CMP_VAL_SHFT 0 +#define SH_X_LADDR_CMP_CMP_VAL_MASK 0x000000000fffffff + +/* SH_X_LADDR_CMP_MASK_VAL */ +/* Description: Mask value */ +#define SH_X_LADDR_CMP_MASK_VAL_SHFT 32 +#define SH_X_LADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 + +/* ==================================================================== */ +/* Register "SH_X_RADDR_CMP" */ +/* MD acx address compare */ +/* ==================================================================== */ + +#define SH_X_RADDR_CMP 0x0000000100020130 +#define SH_X_RADDR_CMP_MASK 0x0fffffff0fffffff +#define SH_X_RADDR_CMP_INIT 0x0000000000000000 + +/* SH_X_RADDR_CMP_CMP_VAL */ +/* Description: Compare value */ +#define SH_X_RADDR_CMP_CMP_VAL_SHFT 0 +#define SH_X_RADDR_CMP_CMP_VAL_MASK 0x000000000fffffff + +/* SH_X_RADDR_CMP_MASK_VAL */ +/* Description: Mask value */ +#define SH_X_RADDR_CMP_MASK_VAL_SHFT 32 +#define SH_X_RADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 + +/* ==================================================================== */ +/* Register "SH_X_TAG_CMP" */ +/* MD acx tagmgr compare */ +/* ==================================================================== */ + +#define SH_X_TAG_CMP 0x0000000100020138 +#define SH_X_TAG_CMP_MASK 0x007fffffffffffff +#define SH_X_TAG_CMP_INIT 0x0000000000000000 + +/* SH_X_TAG_CMP_CMD */ +/* Description: Command compare value */ +#define SH_X_TAG_CMP_CMD_SHFT 0 +#define SH_X_TAG_CMP_CMD_MASK 0x00000000000000ff + +/* SH_X_TAG_CMP_ADDR */ +/* Description: Address compare value */ +#define SH_X_TAG_CMP_ADDR_SHFT 8 +#define SH_X_TAG_CMP_ADDR_MASK 0x000001ffffffff00 + +/* SH_X_TAG_CMP_SRC */ +/* Description: Source compare value */ +#define SH_X_TAG_CMP_SRC_SHFT 41 +#define SH_X_TAG_CMP_SRC_MASK 0x007ffe0000000000 + +/* ==================================================================== */ +/* Register "SH_X_TAG_MASK" */ +/* MD acx tagmgr mask */ +/* ==================================================================== */ + +#define SH_X_TAG_MASK 0x0000000100020140 +#define SH_X_TAG_MASK_MASK 0x007fffffffffffff +#define SH_X_TAG_MASK_INIT 0x0000000000000000 + +/* SH_X_TAG_MASK_CMD */ +/* Description: Command compare value */ +#define SH_X_TAG_MASK_CMD_SHFT 0 +#define SH_X_TAG_MASK_CMD_MASK 0x00000000000000ff + +/* SH_X_TAG_MASK_ADDR */ +/* Description: Address compare value */ +#define SH_X_TAG_MASK_ADDR_SHFT 8 +#define SH_X_TAG_MASK_ADDR_MASK 0x000001ffffffff00 + +/* SH_X_TAG_MASK_SRC */ +/* Description: Source compare value */ +#define SH_X_TAG_MASK_SRC_SHFT 41 +#define SH_X_TAG_MASK_SRC_MASK 0x007ffe0000000000 + +/* ==================================================================== */ +/* Register "SH_Y_MOD_DBUG_SEL" */ +/* MD acy debug select */ +/* ==================================================================== */ + +#define SH_Y_MOD_DBUG_SEL 0x0000000100020148 +#define SH_Y_MOD_DBUG_SEL_MASK 0x03ffffffffffffff +#define SH_Y_MOD_DBUG_SEL_INIT 0x0000000000000000 + +/* SH_Y_MOD_DBUG_SEL_TAG_SEL */ +/* Description: tagmgr select */ +#define SH_Y_MOD_DBUG_SEL_TAG_SEL_SHFT 0 +#define SH_Y_MOD_DBUG_SEL_TAG_SEL_MASK 0x00000000000000ff + +/* SH_Y_MOD_DBUG_SEL_WBQ_SEL */ +/* Description: wbqtg select */ +#define SH_Y_MOD_DBUG_SEL_WBQ_SEL_SHFT 8 +#define SH_Y_MOD_DBUG_SEL_WBQ_SEL_MASK 0x000000000000ff00 + +/* SH_Y_MOD_DBUG_SEL_ARB_SEL */ +/* Description: arbque select */ +#define SH_Y_MOD_DBUG_SEL_ARB_SEL_SHFT 16 +#define SH_Y_MOD_DBUG_SEL_ARB_SEL_MASK 0x0000000000ff0000 + +/* SH_Y_MOD_DBUG_SEL_ATL_SEL */ +/* Description: aintl select */ +#define SH_Y_MOD_DBUG_SEL_ATL_SEL_SHFT 24 +#define SH_Y_MOD_DBUG_SEL_ATL_SEL_MASK 0x00000007ff000000 + +/* SH_Y_MOD_DBUG_SEL_ATR_SEL */ +/* Description: aintr select */ +#define SH_Y_MOD_DBUG_SEL_ATR_SEL_SHFT 35 +#define SH_Y_MOD_DBUG_SEL_ATR_SEL_MASK 0x00003ff800000000 + +/* SH_Y_MOD_DBUG_SEL_DQL_SEL */ +/* Description: dqctr select */ +#define SH_Y_MOD_DBUG_SEL_DQL_SEL_SHFT 46 +#define SH_Y_MOD_DBUG_SEL_DQL_SEL_MASK 0x000fc00000000000 + +/* SH_Y_MOD_DBUG_SEL_DQR_SEL */ +/* Description: dqctl select */ +#define SH_Y_MOD_DBUG_SEL_DQR_SEL_SHFT 52 +#define SH_Y_MOD_DBUG_SEL_DQR_SEL_MASK 0x03f0000000000000 + +/* ==================================================================== */ +/* Register "SH_Y_DBUG_SEL" */ +/* MD acy debug select */ +/* ==================================================================== */ + +#define SH_Y_DBUG_SEL 0x0000000100020150 +#define SH_Y_DBUG_SEL_MASK 0x0000000000ffffff +#define SH_Y_DBUG_SEL_INIT 0x0000000000000000 + +/* SH_Y_DBUG_SEL_DBG_SEL */ +/* Description: debug select */ +#define SH_Y_DBUG_SEL_DBG_SEL_SHFT 0 +#define SH_Y_DBUG_SEL_DBG_SEL_MASK 0x0000000000ffffff + +/* ==================================================================== */ +/* Register "SH_Y_LADDR_CMP" */ +/* MD acy address compare */ +/* ==================================================================== */ + +#define SH_Y_LADDR_CMP 0x0000000100020158 +#define SH_Y_LADDR_CMP_MASK 0x0fffffff0fffffff +#define SH_Y_LADDR_CMP_INIT 0x0000000000000000 + +/* SH_Y_LADDR_CMP_CMP_VAL */ +/* Description: Compare value */ +#define SH_Y_LADDR_CMP_CMP_VAL_SHFT 0 +#define SH_Y_LADDR_CMP_CMP_VAL_MASK 0x000000000fffffff + +/* SH_Y_LADDR_CMP_MASK_VAL */ +/* Description: Mask value */ +#define SH_Y_LADDR_CMP_MASK_VAL_SHFT 32 +#define SH_Y_LADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 + +/* ==================================================================== */ +/* Register "SH_Y_RADDR_CMP" */ +/* MD acy address compare */ +/* ==================================================================== */ + +#define SH_Y_RADDR_CMP 0x0000000100020160 +#define SH_Y_RADDR_CMP_MASK 0x0fffffff0fffffff +#define SH_Y_RADDR_CMP_INIT 0x0000000000000000 + +/* SH_Y_RADDR_CMP_CMP_VAL */ +/* Description: Compare value */ +#define SH_Y_RADDR_CMP_CMP_VAL_SHFT 0 +#define SH_Y_RADDR_CMP_CMP_VAL_MASK 0x000000000fffffff + +/* SH_Y_RADDR_CMP_MASK_VAL */ +/* Description: Mask value */ +#define SH_Y_RADDR_CMP_MASK_VAL_SHFT 32 +#define SH_Y_RADDR_CMP_MASK_VAL_MASK 0x0fffffff00000000 + +/* ==================================================================== */ +/* Register "SH_Y_TAG_CMP" */ +/* MD acy tagmgr compare */ +/* ==================================================================== */ + +#define SH_Y_TAG_CMP 0x0000000100020168 +#define SH_Y_TAG_CMP_MASK 0x007fffffffffffff +#define SH_Y_TAG_CMP_INIT 0x0000000000000000 + +/* SH_Y_TAG_CMP_CMD */ +/* Description: Command compare value */ +#define SH_Y_TAG_CMP_CMD_SHFT 0 +#define SH_Y_TAG_CMP_CMD_MASK 0x00000000000000ff + +/* SH_Y_TAG_CMP_ADDR */ +/* Description: Address compare value */ +#define SH_Y_TAG_CMP_ADDR_SHFT 8 +#define SH_Y_TAG_CMP_ADDR_MASK 0x000001ffffffff00 + +/* SH_Y_TAG_CMP_SRC */ +/* Description: Source compare value */ +#define SH_Y_TAG_CMP_SRC_SHFT 41 +#define SH_Y_TAG_CMP_SRC_MASK 0x007ffe0000000000 + +/* ==================================================================== */ +/* Register "SH_Y_TAG_MASK" */ +/* MD acy tagmgr mask */ +/* ==================================================================== */ + +#define SH_Y_TAG_MASK 0x0000000100020170 +#define SH_Y_TAG_MASK_MASK 0x007fffffffffffff +#define SH_Y_TAG_MASK_INIT 0x0000000000000000 + +/* SH_Y_TAG_MASK_CMD */ +/* Description: Command compare value */ +#define SH_Y_TAG_MASK_CMD_SHFT 0 +#define SH_Y_TAG_MASK_CMD_MASK 0x00000000000000ff + +/* SH_Y_TAG_MASK_ADDR */ +/* Description: Address compare value */ +#define SH_Y_TAG_MASK_ADDR_SHFT 8 +#define SH_Y_TAG_MASK_ADDR_MASK 0x000001ffffffff00 + +/* SH_Y_TAG_MASK_SRC */ +/* Description: Source compare value */ +#define SH_Y_TAG_MASK_SRC_SHFT 41 +#define SH_Y_TAG_MASK_SRC_MASK 0x007ffe0000000000 + +/* ==================================================================== */ +/* Register "SH_MD_JNR_DBUG_DATA_CFG" */ +/* configuration for md jnr debug data muxes */ +/* ==================================================================== */ + +#define SH_MD_JNR_DBUG_DATA_CFG 0x0000000100020178 +#define SH_MD_JNR_DBUG_DATA_CFG_MASK 0x0000000077777777 +#define SH_MD_JNR_DBUG_DATA_CFG_INIT 0x0000000000000000 + +/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL */ +/* Description: selects which nibble drives nibble0 */ +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_SHFT 0 +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_MASK 0x0000000000000007 + +/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL */ +/* Description: selects which nibble drives nibble1 */ +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_SHFT 4 +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_MASK 0x0000000000000070 + +/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL */ +/* Description: selects which nibble drives nibble2 */ +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_SHFT 8 +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_MASK 0x0000000000000700 + +/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL */ +/* Description: selects which nibble drives nibble3 */ +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_SHFT 12 +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_MASK 0x0000000000007000 + +/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL */ +/* Description: selects which nibble drives nibble4 */ +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_SHFT 16 +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_MASK 0x0000000000070000 + +/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL */ +/* Description: selects which nibble drives nibble5 */ +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_SHFT 20 +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_MASK 0x0000000000700000 + +/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL */ +/* Description: selects which nibble drives nibble6 */ +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_SHFT 24 +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_MASK 0x0000000007000000 + +/* SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL */ +/* Description: selects which nibble drives nibble7 */ +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_SHFT 28 +#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_MASK 0x0000000070000000 + +/* ==================================================================== */ +/* Register "SH_MD_LAST_CREDIT" */ +/* captures last credit values on reset */ +/* ==================================================================== */ + +#define SH_MD_LAST_CREDIT 0x0000000100020180 +#define SH_MD_LAST_CREDIT_MASK 0x0000003f3f3f3f3f +#define SH_MD_LAST_CREDIT_INIT 0x0000000000000000 + +/* SH_MD_LAST_CREDIT_RQ_TO_PI */ +/* Description: capture of request credits to pi */ +#define SH_MD_LAST_CREDIT_RQ_TO_PI_SHFT 0 +#define SH_MD_LAST_CREDIT_RQ_TO_PI_MASK 0x000000000000003f + +/* SH_MD_LAST_CREDIT_RP_TO_PI */ +/* Description: capture of reply credits to pi */ +#define SH_MD_LAST_CREDIT_RP_TO_PI_SHFT 8 +#define SH_MD_LAST_CREDIT_RP_TO_PI_MASK 0x0000000000003f00 + +/* SH_MD_LAST_CREDIT_RQ_TO_XN */ +/* Description: capture of request credits to xn */ +#define SH_MD_LAST_CREDIT_RQ_TO_XN_SHFT 16 +#define SH_MD_LAST_CREDIT_RQ_TO_XN_MASK 0x00000000003f0000 + +/* SH_MD_LAST_CREDIT_RP_TO_XN */ +/* Description: capture of reply credits to xn */ +#define SH_MD_LAST_CREDIT_RP_TO_XN_SHFT 24 +#define SH_MD_LAST_CREDIT_RP_TO_XN_MASK 0x000000003f000000 + +/* SH_MD_LAST_CREDIT_TO_LB */ +/* Description: capture of credits to pi */ +#define SH_MD_LAST_CREDIT_TO_LB_SHFT 32 +#define SH_MD_LAST_CREDIT_TO_LB_MASK 0x0000003f00000000 + +/* ==================================================================== */ +/* Register "SH_MEM_CAPTURE_ADDR" */ +/* Address capture address register */ +/* ==================================================================== */ + +#define SH_MEM_CAPTURE_ADDR 0x0000000100020300 +#define SH_MEM_CAPTURE_ADDR_MASK 0x00000ffffffffff8 +#define SH_MEM_CAPTURE_ADDR_INIT 0x0000000000000000 + +/* SH_MEM_CAPTURE_ADDR_ADDR */ +/* Description: upper bits of address */ +#define SH_MEM_CAPTURE_ADDR_ADDR_SHFT 3 +#define SH_MEM_CAPTURE_ADDR_ADDR_MASK 0x0000000ffffffff8 + +/* SH_MEM_CAPTURE_ADDR_CMD */ +/* Description: command of reference */ +#define SH_MEM_CAPTURE_ADDR_CMD_SHFT 36 +#define SH_MEM_CAPTURE_ADDR_CMD_MASK 0x00000ff000000000 + +/* ==================================================================== */ +/* Register "SH_MEM_CAPTURE_MASK" */ +/* Address capture mask register */ +/* ==================================================================== */ + +#define SH_MEM_CAPTURE_MASK 0x0000000100020308 +#define SH_MEM_CAPTURE_MASK_MASK 0x00003ffffffffff8 +#define SH_MEM_CAPTURE_MASK_INIT 0x0000000000000000 + +/* SH_MEM_CAPTURE_MASK_ADDR */ +/* Description: upper bits of address */ +#define SH_MEM_CAPTURE_MASK_ADDR_SHFT 3 +#define SH_MEM_CAPTURE_MASK_ADDR_MASK 0x0000000ffffffff8 + +/* SH_MEM_CAPTURE_MASK_CMD */ +/* Description: command of reference */ +#define SH_MEM_CAPTURE_MASK_CMD_SHFT 36 +#define SH_MEM_CAPTURE_MASK_CMD_MASK 0x00000ff000000000 + +/* SH_MEM_CAPTURE_MASK_ENABLE_LOCAL */ +/* Description: capture references originating locally */ +#define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_SHFT 44 +#define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_MASK 0x0000100000000000 + +/* SH_MEM_CAPTURE_MASK_ENABLE_REMOTE */ +/* Description: capture references originating remotely */ +#define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_SHFT 45 +#define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_MASK 0x0000200000000000 + +/* ==================================================================== */ +/* Register "SH_MEM_CAPTURE_HDR" */ +/* Address capture header register */ +/* ==================================================================== */ + +#define SH_MEM_CAPTURE_HDR 0x0000000100020310 +#define SH_MEM_CAPTURE_HDR_MASK 0xfffffffffffffff8 +#define SH_MEM_CAPTURE_HDR_INIT 0x0000000000000000 + +/* SH_MEM_CAPTURE_HDR_ADDR */ +/* Description: upper bits of reference address */ +#define SH_MEM_CAPTURE_HDR_ADDR_SHFT 3 +#define SH_MEM_CAPTURE_HDR_ADDR_MASK 0x0000000ffffffff8 + +/* SH_MEM_CAPTURE_HDR_CMD */ +/* Description: command of reference */ +#define SH_MEM_CAPTURE_HDR_CMD_SHFT 36 +#define SH_MEM_CAPTURE_HDR_CMD_MASK 0x00000ff000000000 + +/* SH_MEM_CAPTURE_HDR_SRC */ +/* Description: source node of reference */ +#define SH_MEM_CAPTURE_HDR_SRC_SHFT 44 +#define SH_MEM_CAPTURE_HDR_SRC_MASK 0x03fff00000000000 + +/* SH_MEM_CAPTURE_HDR_CNTR */ +/* Description: increments on every capture */ +#define SH_MEM_CAPTURE_HDR_CNTR_SHFT 58 +#define SH_MEM_CAPTURE_HDR_CNTR_MASK 0xfc00000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_CONFIG" */ +/* DQ directory config register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_CONFIG 0x0000000100030000 +#define SH_MD_DQLP_MMR_DIR_CONFIG_MASK 0x000000000000001f +#define SH_MD_DQLP_MMR_DIR_CONFIG_INIT 0x0000000000000010 + +/* SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE */ +/* Description: system size code */ +#define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_MASK 0x0000000000000007 + +/* SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC */ +/* Description: enable directory ecc correction */ +#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3 +#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008 + +/* SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS */ +/* Description: enable local poisoning for dir table fall-through */ +#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4 +#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC0" */ +/* node [63:0] presence bits */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRESVEC0 0x0000000100030100 +#define SH_MD_DQLP_MMR_DIR_PRESVEC0_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_PRESVEC0_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC */ +/* Description: node presence bits, 1=present */ +#define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC1" */ +/* node [127:64] presence bits */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRESVEC1 0x0000000100030110 +#define SH_MD_DQLP_MMR_DIR_PRESVEC1_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_PRESVEC1_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC */ +/* Description: node presence bits, 1=present */ +#define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC2" */ +/* node [191:128] presence bits */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRESVEC2 0x0000000100030120 +#define SH_MD_DQLP_MMR_DIR_PRESVEC2_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_PRESVEC2_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC */ +/* Description: node presence bits, 1=present */ +#define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC3" */ +/* node [255:192] presence bits */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRESVEC3 0x0000000100030130 +#define SH_MD_DQLP_MMR_DIR_PRESVEC3_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_PRESVEC3_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC */ +/* Description: node presence bits, 1=present */ +#define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC0" */ +/* local vector for acc=0 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_LOCVEC0 0x0000000100030200 +#define SH_MD_DQLP_MMR_DIR_LOCVEC0_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_LOCVEC0_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC1" */ +/* local vector for acc=1 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_LOCVEC1 0x0000000100030210 +#define SH_MD_DQLP_MMR_DIR_LOCVEC1_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_LOCVEC1_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC2" */ +/* local vector for acc=2 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_LOCVEC2 0x0000000100030220 +#define SH_MD_DQLP_MMR_DIR_LOCVEC2_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_LOCVEC2_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC3" */ +/* local vector for acc=3 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_LOCVEC3 0x0000000100030230 +#define SH_MD_DQLP_MMR_DIR_LOCVEC3_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_LOCVEC3_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC4" */ +/* local vector for acc=4 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_LOCVEC4 0x0000000100030240 +#define SH_MD_DQLP_MMR_DIR_LOCVEC4_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_LOCVEC4_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC5" */ +/* local vector for acc=5 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_LOCVEC5 0x0000000100030250 +#define SH_MD_DQLP_MMR_DIR_LOCVEC5_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_LOCVEC5_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC6" */ +/* local vector for acc=6 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_LOCVEC6 0x0000000100030260 +#define SH_MD_DQLP_MMR_DIR_LOCVEC6_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_LOCVEC6_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC7" */ +/* local vector for acc=7 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_LOCVEC7 0x0000000100030270 +#define SH_MD_DQLP_MMR_DIR_LOCVEC7_MASK 0xffffffffffffffff +#define SH_MD_DQLP_MMR_DIR_LOCVEC7_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ +/* privilege vector for acc=0 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300 +#define SH_MD_DQLP_MMR_DIR_PRIVEC0_MASK 0x000000000fffffff +#define SH_MD_DQLP_MMR_DIR_PRIVEC0_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRIVEC0_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_MASK 0x0000000000003fff + +/* SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_SHFT 14 +#define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC1" */ +/* privilege vector for acc=1 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRIVEC1 0x0000000100030310 +#define SH_MD_DQLP_MMR_DIR_PRIVEC1_MASK 0x000000000fffffff +#define SH_MD_DQLP_MMR_DIR_PRIVEC1_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRIVEC1_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_MASK 0x0000000000003fff + +/* SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_SHFT 14 +#define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC2" */ +/* privilege vector for acc=2 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRIVEC2 0x0000000100030320 +#define SH_MD_DQLP_MMR_DIR_PRIVEC2_MASK 0x000000000fffffff +#define SH_MD_DQLP_MMR_DIR_PRIVEC2_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRIVEC2_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_MASK 0x0000000000003fff + +/* SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_SHFT 14 +#define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC3" */ +/* privilege vector for acc=3 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRIVEC3 0x0000000100030330 +#define SH_MD_DQLP_MMR_DIR_PRIVEC3_MASK 0x000000000fffffff +#define SH_MD_DQLP_MMR_DIR_PRIVEC3_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRIVEC3_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_MASK 0x0000000000003fff + +/* SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_SHFT 14 +#define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC4" */ +/* privilege vector for acc=4 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRIVEC4 0x0000000100030340 +#define SH_MD_DQLP_MMR_DIR_PRIVEC4_MASK 0x000000000fffffff +#define SH_MD_DQLP_MMR_DIR_PRIVEC4_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRIVEC4_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_MASK 0x0000000000003fff + +/* SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_SHFT 14 +#define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC5" */ +/* privilege vector for acc=5 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRIVEC5 0x0000000100030350 +#define SH_MD_DQLP_MMR_DIR_PRIVEC5_MASK 0x000000000fffffff +#define SH_MD_DQLP_MMR_DIR_PRIVEC5_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRIVEC5_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_MASK 0x0000000000003fff + +/* SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_SHFT 14 +#define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC6" */ +/* privilege vector for acc=6 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRIVEC6 0x0000000100030360 +#define SH_MD_DQLP_MMR_DIR_PRIVEC6_MASK 0x000000000fffffff +#define SH_MD_DQLP_MMR_DIR_PRIVEC6_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRIVEC6_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_MASK 0x0000000000003fff + +/* SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_SHFT 14 +#define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC7" */ +/* privilege vector for acc=7 */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_PRIVEC7 0x0000000100030370 +#define SH_MD_DQLP_MMR_DIR_PRIVEC7_MASK 0x000000000fffffff +#define SH_MD_DQLP_MMR_DIR_PRIVEC7_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_PRIVEC7_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_MASK 0x0000000000003fff + +/* SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_SHFT 14 +#define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_TIMER" */ +/* MD SXRO timer */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_TIMER 0x0000000100030400 +#define SH_MD_DQLP_MMR_DIR_TIMER_MASK 0x00000000003fffff +#define SH_MD_DQLP_MMR_DIR_TIMER_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV */ +/* Description: timer divide register */ +#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_MASK 0x0000000000000fff + +/* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN */ +/* Description: timer enable */ +#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_SHFT 12 +#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_MASK 0x0000000000001000 + +/* SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR */ +/* Description: value of current timer */ +#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_SHFT 13 +#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_MASK 0x00000000003fe000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY" */ +/* directory pio write data */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY 0x0000000100031000 +#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_MASK 0x03ffffffffffffff +#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA */ +/* Description: directory entry A */ +#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0 +#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff + +/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB */ +/* Description: directory entry B */ +#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26 +#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000 + +/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI */ +/* Description: directory priority */ +#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT 52 +#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_MASK 0x0070000000000000 + +/* SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC */ +/* Description: directory access bits */ +#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT 55 +#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_MASK 0x0380000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC" */ +/* directory ecc register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC 0x0000000100031010 +#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_MASK 0x0000000000003fff +#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA */ +/* Description: XOR bits for directory ECC group 1 */ +#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_SHFT 0 +#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_MASK 0x000000000000007f + +/* SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB */ +/* Description: XOR bits for directory ECC group 2 */ +#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_SHFT 7 +#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_MASK 0x0000000000003f80 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY" */ +/* x directory pio read data */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY 0x0000000100032000 +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_MASK 0x0fffffffffffffff +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA */ +/* Description: directory entry A */ +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0 +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff + +/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB */ +/* Description: directory entry B */ +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26 +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 + +/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI */ +/* Description: directory priority */ +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52 +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000 + +/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC */ +/* Description: directory access bits */ +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55 +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000 + +/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR */ +/* Description: correctable ecc error */ +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58 +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000 + +/* SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC */ +/* Description: uncorrectable ecc error */ +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59 +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC" */ +/* x directory ecc */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC 0x0000000100032010 +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_MASK 0x0000000000003fff +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA */ +/* Description: group 1 ecc */ +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0 +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f + +/* SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB */ +/* Description: group 2 ecc */ +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7 +#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY" */ +/* y directory pio read data */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY 0x0000000100032800 +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_MASK 0x0fffffffffffffff +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA */ +/* Description: directory entry A */ +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0 +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff + +/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB */ +/* Description: directory entry B */ +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26 +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 + +/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI */ +/* Description: directory priority */ +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52 +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000 + +/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC */ +/* Description: directory access bits */ +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55 +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000 + +/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR */ +/* Description: correctable ecc error */ +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58 +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000 + +/* SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC */ +/* Description: uncorrectable ecc error */ +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59 +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC" */ +/* y directory ecc */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC 0x0000000100032810 +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_MASK 0x0000000000003fff +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA */ +/* Description: group 1 ecc */ +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0 +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f + +/* SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB */ +/* Description: group 2 ecc */ +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7 +#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XCERR1" */ +/* correctable dir ecc group 1 error register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_XCERR1 0x0000000100033000 +#define SH_MD_DQLP_MMR_XCERR1_MASK 0x0000007fffffffff +#define SH_MD_DQLP_MMR_XCERR1_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_XCERR1_GRP1 */ +/* Description: ecc group 1 bits */ +#define SH_MD_DQLP_MMR_XCERR1_GRP1_SHFT 0 +#define SH_MD_DQLP_MMR_XCERR1_GRP1_MASK 0x0000000fffffffff + +/* SH_MD_DQLP_MMR_XCERR1_VAL */ +/* Description: correctable ecc error in group 1 bits */ +#define SH_MD_DQLP_MMR_XCERR1_VAL_SHFT 36 +#define SH_MD_DQLP_MMR_XCERR1_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQLP_MMR_XCERR1_MORE */ +/* Description: more than one correctable ecc error in group 1 */ +#define SH_MD_DQLP_MMR_XCERR1_MORE_SHFT 37 +#define SH_MD_DQLP_MMR_XCERR1_MORE_MASK 0x0000002000000000 + +/* SH_MD_DQLP_MMR_XCERR1_ARM */ +/* Description: writing 1 arms uncorrectable ecc error capture */ +#define SH_MD_DQLP_MMR_XCERR1_ARM_SHFT 38 +#define SH_MD_DQLP_MMR_XCERR1_ARM_MASK 0x0000004000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XCERR2" */ +/* correctable dir ecc group 2 error register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_XCERR2 0x0000000100033010 +#define SH_MD_DQLP_MMR_XCERR2_MASK 0x0000003fffffffff +#define SH_MD_DQLP_MMR_XCERR2_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_XCERR2_GRP2 */ +/* Description: ecc group 2 bits */ +#define SH_MD_DQLP_MMR_XCERR2_GRP2_SHFT 0 +#define SH_MD_DQLP_MMR_XCERR2_GRP2_MASK 0x0000000fffffffff + +/* SH_MD_DQLP_MMR_XCERR2_VAL */ +/* Description: correctable ecc error in group 2 bits */ +#define SH_MD_DQLP_MMR_XCERR2_VAL_SHFT 36 +#define SH_MD_DQLP_MMR_XCERR2_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQLP_MMR_XCERR2_MORE */ +/* Description: more than one correctable ecc error in group 2 */ +#define SH_MD_DQLP_MMR_XCERR2_MORE_SHFT 37 +#define SH_MD_DQLP_MMR_XCERR2_MORE_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XUERR1" */ +/* uncorrectable dir ecc group 1 error register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_XUERR1 0x0000000100033020 +#define SH_MD_DQLP_MMR_XUERR1_MASK 0x0000007fffffffff +#define SH_MD_DQLP_MMR_XUERR1_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_XUERR1_GRP1 */ +/* Description: ecc group 1 bits */ +#define SH_MD_DQLP_MMR_XUERR1_GRP1_SHFT 0 +#define SH_MD_DQLP_MMR_XUERR1_GRP1_MASK 0x0000000fffffffff + +/* SH_MD_DQLP_MMR_XUERR1_VAL */ +/* Description: uncorrectable ecc error in group 1 bits */ +#define SH_MD_DQLP_MMR_XUERR1_VAL_SHFT 36 +#define SH_MD_DQLP_MMR_XUERR1_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQLP_MMR_XUERR1_MORE */ +/* Description: more than one uncorrectable ecc error in group 1 */ +#define SH_MD_DQLP_MMR_XUERR1_MORE_SHFT 37 +#define SH_MD_DQLP_MMR_XUERR1_MORE_MASK 0x0000002000000000 + +/* SH_MD_DQLP_MMR_XUERR1_ARM */ +/* Description: writing 1 arms uncorrectable ecc error capture */ +#define SH_MD_DQLP_MMR_XUERR1_ARM_SHFT 38 +#define SH_MD_DQLP_MMR_XUERR1_ARM_MASK 0x0000004000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XUERR2" */ +/* uncorrectable dir ecc group 2 error register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_XUERR2 0x0000000100033030 +#define SH_MD_DQLP_MMR_XUERR2_MASK 0x0000003fffffffff +#define SH_MD_DQLP_MMR_XUERR2_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_XUERR2_GRP2 */ +/* Description: ecc group 2 bits */ +#define SH_MD_DQLP_MMR_XUERR2_GRP2_SHFT 0 +#define SH_MD_DQLP_MMR_XUERR2_GRP2_MASK 0x0000000fffffffff + +/* SH_MD_DQLP_MMR_XUERR2_VAL */ +/* Description: uncorrectable ecc error in group 2 bits */ +#define SH_MD_DQLP_MMR_XUERR2_VAL_SHFT 36 +#define SH_MD_DQLP_MMR_XUERR2_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQLP_MMR_XUERR2_MORE */ +/* Description: more than one uncorrectable ecc error in group 2 */ +#define SH_MD_DQLP_MMR_XUERR2_MORE_SHFT 37 +#define SH_MD_DQLP_MMR_XUERR2_MORE_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XPERR" */ +/* protocol error register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_XPERR 0x0000000100033040 +#define SH_MD_DQLP_MMR_XPERR_MASK 0x7fffffffffffffff +#define SH_MD_DQLP_MMR_XPERR_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_XPERR_DIR */ +/* Description: directory entry */ +#define SH_MD_DQLP_MMR_XPERR_DIR_SHFT 0 +#define SH_MD_DQLP_MMR_XPERR_DIR_MASK 0x0000000003ffffff + +/* SH_MD_DQLP_MMR_XPERR_CMD */ +/* Description: incoming command */ +#define SH_MD_DQLP_MMR_XPERR_CMD_SHFT 26 +#define SH_MD_DQLP_MMR_XPERR_CMD_MASK 0x00000003fc000000 + +/* SH_MD_DQLP_MMR_XPERR_SRC */ +/* Description: source node of dir operation */ +#define SH_MD_DQLP_MMR_XPERR_SRC_SHFT 34 +#define SH_MD_DQLP_MMR_XPERR_SRC_MASK 0x0000fffc00000000 + +/* SH_MD_DQLP_MMR_XPERR_PRIGE */ +/* Description: priority was greater-equal */ +#define SH_MD_DQLP_MMR_XPERR_PRIGE_SHFT 48 +#define SH_MD_DQLP_MMR_XPERR_PRIGE_MASK 0x0001000000000000 + +/* SH_MD_DQLP_MMR_XPERR_PRIV */ +/* Description: access privilege bit */ +#define SH_MD_DQLP_MMR_XPERR_PRIV_SHFT 49 +#define SH_MD_DQLP_MMR_XPERR_PRIV_MASK 0x0002000000000000 + +/* SH_MD_DQLP_MMR_XPERR_COR */ +/* Description: correctable ecc error */ +#define SH_MD_DQLP_MMR_XPERR_COR_SHFT 50 +#define SH_MD_DQLP_MMR_XPERR_COR_MASK 0x0004000000000000 + +/* SH_MD_DQLP_MMR_XPERR_UNC */ +/* Description: uncorrectable ecc error */ +#define SH_MD_DQLP_MMR_XPERR_UNC_SHFT 51 +#define SH_MD_DQLP_MMR_XPERR_UNC_MASK 0x0008000000000000 + +/* SH_MD_DQLP_MMR_XPERR_MYBIT */ +/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ +#define SH_MD_DQLP_MMR_XPERR_MYBIT_SHFT 52 +#define SH_MD_DQLP_MMR_XPERR_MYBIT_MASK 0x0ff0000000000000 + +/* SH_MD_DQLP_MMR_XPERR_VAL */ +/* Description: protocol error info valid */ +#define SH_MD_DQLP_MMR_XPERR_VAL_SHFT 60 +#define SH_MD_DQLP_MMR_XPERR_VAL_MASK 0x1000000000000000 + +/* SH_MD_DQLP_MMR_XPERR_MORE */ +/* Description: more than one protocol error */ +#define SH_MD_DQLP_MMR_XPERR_MORE_SHFT 61 +#define SH_MD_DQLP_MMR_XPERR_MORE_MASK 0x2000000000000000 + +/* SH_MD_DQLP_MMR_XPERR_ARM */ +/* Description: writing 1 arms error capture */ +#define SH_MD_DQLP_MMR_XPERR_ARM_SHFT 62 +#define SH_MD_DQLP_MMR_XPERR_ARM_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YCERR1" */ +/* correctable dir ecc group 1 error register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_YCERR1 0x0000000100033800 +#define SH_MD_DQLP_MMR_YCERR1_MASK 0x0000007fffffffff +#define SH_MD_DQLP_MMR_YCERR1_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_YCERR1_GRP1 */ +/* Description: ecc group 1 bits */ +#define SH_MD_DQLP_MMR_YCERR1_GRP1_SHFT 0 +#define SH_MD_DQLP_MMR_YCERR1_GRP1_MASK 0x0000000fffffffff + +/* SH_MD_DQLP_MMR_YCERR1_VAL */ +/* Description: correctable ecc error in group 1 bits */ +#define SH_MD_DQLP_MMR_YCERR1_VAL_SHFT 36 +#define SH_MD_DQLP_MMR_YCERR1_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQLP_MMR_YCERR1_MORE */ +/* Description: more than one correctable ecc error in group 1 */ +#define SH_MD_DQLP_MMR_YCERR1_MORE_SHFT 37 +#define SH_MD_DQLP_MMR_YCERR1_MORE_MASK 0x0000002000000000 + +/* SH_MD_DQLP_MMR_YCERR1_ARM */ +/* Description: writing 1 arms uncorrectable ecc error capture */ +#define SH_MD_DQLP_MMR_YCERR1_ARM_SHFT 38 +#define SH_MD_DQLP_MMR_YCERR1_ARM_MASK 0x0000004000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YCERR2" */ +/* correctable dir ecc group 2 error register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_YCERR2 0x0000000100033810 +#define SH_MD_DQLP_MMR_YCERR2_MASK 0x0000003fffffffff +#define SH_MD_DQLP_MMR_YCERR2_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_YCERR2_GRP2 */ +/* Description: ecc group 2 bits */ +#define SH_MD_DQLP_MMR_YCERR2_GRP2_SHFT 0 +#define SH_MD_DQLP_MMR_YCERR2_GRP2_MASK 0x0000000fffffffff + +/* SH_MD_DQLP_MMR_YCERR2_VAL */ +/* Description: correctable ecc error in group 2 bits */ +#define SH_MD_DQLP_MMR_YCERR2_VAL_SHFT 36 +#define SH_MD_DQLP_MMR_YCERR2_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQLP_MMR_YCERR2_MORE */ +/* Description: more than one correctable ecc error in group 2 */ +#define SH_MD_DQLP_MMR_YCERR2_MORE_SHFT 37 +#define SH_MD_DQLP_MMR_YCERR2_MORE_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YUERR1" */ +/* uncorrectable dir ecc group 1 error register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_YUERR1 0x0000000100033820 +#define SH_MD_DQLP_MMR_YUERR1_MASK 0x0000007fffffffff +#define SH_MD_DQLP_MMR_YUERR1_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_YUERR1_GRP1 */ +/* Description: ecc group 1 bits */ +#define SH_MD_DQLP_MMR_YUERR1_GRP1_SHFT 0 +#define SH_MD_DQLP_MMR_YUERR1_GRP1_MASK 0x0000000fffffffff + +/* SH_MD_DQLP_MMR_YUERR1_VAL */ +/* Description: uncorrectable ecc error in group 1 bits */ +#define SH_MD_DQLP_MMR_YUERR1_VAL_SHFT 36 +#define SH_MD_DQLP_MMR_YUERR1_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQLP_MMR_YUERR1_MORE */ +/* Description: more than one uncorrectable ecc error in group 1 */ +#define SH_MD_DQLP_MMR_YUERR1_MORE_SHFT 37 +#define SH_MD_DQLP_MMR_YUERR1_MORE_MASK 0x0000002000000000 + +/* SH_MD_DQLP_MMR_YUERR1_ARM */ +/* Description: writing 1 arms uncorrectable ecc error capture */ +#define SH_MD_DQLP_MMR_YUERR1_ARM_SHFT 38 +#define SH_MD_DQLP_MMR_YUERR1_ARM_MASK 0x0000004000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YUERR2" */ +/* uncorrectable dir ecc group 2 error register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_YUERR2 0x0000000100033830 +#define SH_MD_DQLP_MMR_YUERR2_MASK 0x0000003fffffffff +#define SH_MD_DQLP_MMR_YUERR2_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_YUERR2_GRP2 */ +/* Description: ecc group 2 bits */ +#define SH_MD_DQLP_MMR_YUERR2_GRP2_SHFT 0 +#define SH_MD_DQLP_MMR_YUERR2_GRP2_MASK 0x0000000fffffffff + +/* SH_MD_DQLP_MMR_YUERR2_VAL */ +/* Description: uncorrectable ecc error in group 2 bits */ +#define SH_MD_DQLP_MMR_YUERR2_VAL_SHFT 36 +#define SH_MD_DQLP_MMR_YUERR2_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQLP_MMR_YUERR2_MORE */ +/* Description: more than one uncorrectable ecc error in group 2 */ +#define SH_MD_DQLP_MMR_YUERR2_MORE_SHFT 37 +#define SH_MD_DQLP_MMR_YUERR2_MORE_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YPERR" */ +/* protocol error register */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_YPERR 0x0000000100033840 +#define SH_MD_DQLP_MMR_YPERR_MASK 0x7fffffffffffffff +#define SH_MD_DQLP_MMR_YPERR_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_YPERR_DIR */ +/* Description: directory entry */ +#define SH_MD_DQLP_MMR_YPERR_DIR_SHFT 0 +#define SH_MD_DQLP_MMR_YPERR_DIR_MASK 0x0000000003ffffff + +/* SH_MD_DQLP_MMR_YPERR_CMD */ +/* Description: incoming command */ +#define SH_MD_DQLP_MMR_YPERR_CMD_SHFT 26 +#define SH_MD_DQLP_MMR_YPERR_CMD_MASK 0x00000003fc000000 + +/* SH_MD_DQLP_MMR_YPERR_SRC */ +/* Description: source node of dir operation */ +#define SH_MD_DQLP_MMR_YPERR_SRC_SHFT 34 +#define SH_MD_DQLP_MMR_YPERR_SRC_MASK 0x0000fffc00000000 + +/* SH_MD_DQLP_MMR_YPERR_PRIGE */ +/* Description: priority was greater-equal */ +#define SH_MD_DQLP_MMR_YPERR_PRIGE_SHFT 48 +#define SH_MD_DQLP_MMR_YPERR_PRIGE_MASK 0x0001000000000000 + +/* SH_MD_DQLP_MMR_YPERR_PRIV */ +/* Description: access privilege bit */ +#define SH_MD_DQLP_MMR_YPERR_PRIV_SHFT 49 +#define SH_MD_DQLP_MMR_YPERR_PRIV_MASK 0x0002000000000000 + +/* SH_MD_DQLP_MMR_YPERR_COR */ +/* Description: correctable ecc error */ +#define SH_MD_DQLP_MMR_YPERR_COR_SHFT 50 +#define SH_MD_DQLP_MMR_YPERR_COR_MASK 0x0004000000000000 + +/* SH_MD_DQLP_MMR_YPERR_UNC */ +/* Description: uncorrectable ecc error */ +#define SH_MD_DQLP_MMR_YPERR_UNC_SHFT 51 +#define SH_MD_DQLP_MMR_YPERR_UNC_MASK 0x0008000000000000 + +/* SH_MD_DQLP_MMR_YPERR_MYBIT */ +/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ +#define SH_MD_DQLP_MMR_YPERR_MYBIT_SHFT 52 +#define SH_MD_DQLP_MMR_YPERR_MYBIT_MASK 0x0ff0000000000000 + +/* SH_MD_DQLP_MMR_YPERR_VAL */ +/* Description: protocol error info valid */ +#define SH_MD_DQLP_MMR_YPERR_VAL_SHFT 60 +#define SH_MD_DQLP_MMR_YPERR_VAL_MASK 0x1000000000000000 + +/* SH_MD_DQLP_MMR_YPERR_MORE */ +/* Description: more than one protocol error */ +#define SH_MD_DQLP_MMR_YPERR_MORE_SHFT 61 +#define SH_MD_DQLP_MMR_YPERR_MORE_MASK 0x2000000000000000 + +/* SH_MD_DQLP_MMR_YPERR_ARM */ +/* Description: writing 1 arms error capture */ +#define SH_MD_DQLP_MMR_YPERR_ARM_SHFT 62 +#define SH_MD_DQLP_MMR_YPERR_ARM_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_CMDTRIG" */ +/* cmd triggers */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_CMDTRIG 0x0000000100034000 +#define SH_MD_DQLP_MMR_DIR_CMDTRIG_MASK 0x00000000ffffffff +#define SH_MD_DQLP_MMR_DIR_CMDTRIG_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0 */ +/* Description: command trigger 0 */ +#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_MASK 0x00000000000000ff + +/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1 */ +/* Description: command trigger 1 */ +#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_SHFT 8 +#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_MASK 0x000000000000ff00 + +/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2 */ +/* Description: command trigger 2 */ +#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_SHFT 16 +#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_MASK 0x0000000000ff0000 + +/* SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3 */ +/* Description: command trigger 3 */ +#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_SHFT 24 +#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_MASK 0x00000000ff000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_TBLTRIG" */ +/* dir table trigger */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_TBLTRIG 0x0000000100034010 +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MASK 0x000003ffffffffff +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC */ +/* Description: source of request */ +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_MASK 0x0000000000003fff + +/* SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD */ +/* Description: incoming request */ +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_SHFT 14 +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_MASK 0x00000000003fc000 + +/* SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC */ +/* Description: uncorrectable error, privilege bit */ +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_SHFT 22 +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_MASK 0x0000000000c00000 + +/* SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE */ +/* Description: priority greater-equal */ +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_SHFT 24 +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_MASK 0x0000000001000000 + +/* SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST */ +/* Description: shrd,sxro,sub-state */ +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_SHFT 25 +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_MASK 0x00000003fe000000 + +/* SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT */ +/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_SHFT 34 +#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_MASK 0x000003fc00000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_TBLMASK" */ +/* dir table trigger mask */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_DIR_TBLMASK 0x0000000100034020 +#define SH_MD_DQLP_MMR_DIR_TBLMASK_MASK 0x000003ffffffffff +#define SH_MD_DQLP_MMR_DIR_TBLMASK_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_DIR_TBLMASK_SRC */ +/* Description: source of request */ +#define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_SHFT 0 +#define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_MASK 0x0000000000003fff + +/* SH_MD_DQLP_MMR_DIR_TBLMASK_CMD */ +/* Description: incoming request */ +#define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_SHFT 14 +#define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_MASK 0x00000000003fc000 + +/* SH_MD_DQLP_MMR_DIR_TBLMASK_ACC */ +/* Description: uncorrectable error, privilege bit */ +#define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_SHFT 22 +#define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_MASK 0x0000000000c00000 + +/* SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE */ +/* Description: priority greater-equal */ +#define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_SHFT 24 +#define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_MASK 0x0000000001000000 + +/* SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST */ +/* Description: shrd,sxro,sub-state */ +#define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_SHFT 25 +#define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_MASK 0x00000003fe000000 + +/* SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT */ +/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ +#define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_SHFT 34 +#define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_MASK 0x000003fc00000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_XBIST_H 0x0000000100038000 +#define SH_MD_DQLP_MMR_XBIST_H_MASK 0x00000700ffffffff +#define SH_MD_DQLP_MMR_XBIST_H_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_XBIST_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLP_MMR_XBIST_H_PAT_SHFT 0 +#define SH_MD_DQLP_MMR_XBIST_H_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQLP_MMR_XBIST_H_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQLP_MMR_XBIST_H_INV_SHFT 40 +#define SH_MD_DQLP_MMR_XBIST_H_INV_MASK 0x0000010000000000 + +/* SH_MD_DQLP_MMR_XBIST_H_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQLP_MMR_XBIST_H_ROT_SHFT 41 +#define SH_MD_DQLP_MMR_XBIST_H_ROT_MASK 0x0000020000000000 + +/* SH_MD_DQLP_MMR_XBIST_H_ARM */ +/* Description: writing 1 arms data miscompare capture */ +#define SH_MD_DQLP_MMR_XBIST_H_ARM_SHFT 42 +#define SH_MD_DQLP_MMR_XBIST_H_ARM_MASK 0x0000040000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_XBIST_L 0x0000000100038010 +#define SH_MD_DQLP_MMR_XBIST_L_MASK 0x00000300ffffffff +#define SH_MD_DQLP_MMR_XBIST_L_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_XBIST_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLP_MMR_XBIST_L_PAT_SHFT 0 +#define SH_MD_DQLP_MMR_XBIST_L_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQLP_MMR_XBIST_L_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQLP_MMR_XBIST_L_INV_SHFT 40 +#define SH_MD_DQLP_MMR_XBIST_L_INV_MASK 0x0000010000000000 + +/* SH_MD_DQLP_MMR_XBIST_L_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQLP_MMR_XBIST_L_ROT_SHFT 41 +#define SH_MD_DQLP_MMR_XBIST_L_ROT_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_XBIST_ERR_H 0x0000000100038020 +#define SH_MD_DQLP_MMR_XBIST_ERR_H_MASK 0x00000300ffffffff +#define SH_MD_DQLP_MMR_XBIST_ERR_H_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_XBIST_ERR_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_SHFT 0 +#define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQLP_MMR_XBIST_ERR_H_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_SHFT 40 +#define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQLP_MMR_XBIST_ERR_H_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_SHFT 41 +#define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_XBIST_ERR_L 0x0000000100038030 +#define SH_MD_DQLP_MMR_XBIST_ERR_L_MASK 0x00000300ffffffff +#define SH_MD_DQLP_MMR_XBIST_ERR_L_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_XBIST_ERR_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_SHFT 0 +#define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQLP_MMR_XBIST_ERR_L_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_SHFT 40 +#define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQLP_MMR_XBIST_ERR_L_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_SHFT 41 +#define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_YBIST_H 0x0000000100038800 +#define SH_MD_DQLP_MMR_YBIST_H_MASK 0x00000700ffffffff +#define SH_MD_DQLP_MMR_YBIST_H_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_YBIST_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLP_MMR_YBIST_H_PAT_SHFT 0 +#define SH_MD_DQLP_MMR_YBIST_H_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQLP_MMR_YBIST_H_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQLP_MMR_YBIST_H_INV_SHFT 40 +#define SH_MD_DQLP_MMR_YBIST_H_INV_MASK 0x0000010000000000 + +/* SH_MD_DQLP_MMR_YBIST_H_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQLP_MMR_YBIST_H_ROT_SHFT 41 +#define SH_MD_DQLP_MMR_YBIST_H_ROT_MASK 0x0000020000000000 + +/* SH_MD_DQLP_MMR_YBIST_H_ARM */ +/* Description: writing 1 arms data miscompare capture */ +#define SH_MD_DQLP_MMR_YBIST_H_ARM_SHFT 42 +#define SH_MD_DQLP_MMR_YBIST_H_ARM_MASK 0x0000040000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_YBIST_L 0x0000000100038810 +#define SH_MD_DQLP_MMR_YBIST_L_MASK 0x00000300ffffffff +#define SH_MD_DQLP_MMR_YBIST_L_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_YBIST_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLP_MMR_YBIST_L_PAT_SHFT 0 +#define SH_MD_DQLP_MMR_YBIST_L_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQLP_MMR_YBIST_L_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQLP_MMR_YBIST_L_INV_SHFT 40 +#define SH_MD_DQLP_MMR_YBIST_L_INV_MASK 0x0000010000000000 + +/* SH_MD_DQLP_MMR_YBIST_L_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQLP_MMR_YBIST_L_ROT_SHFT 41 +#define SH_MD_DQLP_MMR_YBIST_L_ROT_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_YBIST_ERR_H 0x0000000100038820 +#define SH_MD_DQLP_MMR_YBIST_ERR_H_MASK 0x00000300ffffffff +#define SH_MD_DQLP_MMR_YBIST_ERR_H_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_YBIST_ERR_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_SHFT 0 +#define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQLP_MMR_YBIST_ERR_H_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_SHFT 40 +#define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQLP_MMR_YBIST_ERR_H_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_SHFT 41 +#define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLP_MMR_YBIST_ERR_L 0x0000000100038830 +#define SH_MD_DQLP_MMR_YBIST_ERR_L_MASK 0x00000300ffffffff +#define SH_MD_DQLP_MMR_YBIST_ERR_L_INIT 0x0000000000000000 + +/* SH_MD_DQLP_MMR_YBIST_ERR_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_SHFT 0 +#define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQLP_MMR_YBIST_ERR_L_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_SHFT 40 +#define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQLP_MMR_YBIST_ERR_L_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_SHFT 41 +#define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_XBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLS_MMR_XBIST_H 0x0000000100048000 +#define SH_MD_DQLS_MMR_XBIST_H_MASK 0x000007ffffffffff +#define SH_MD_DQLS_MMR_XBIST_H_INIT 0x0000000000000000 + +/* SH_MD_DQLS_MMR_XBIST_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLS_MMR_XBIST_H_PAT_SHFT 0 +#define SH_MD_DQLS_MMR_XBIST_H_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQLS_MMR_XBIST_H_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQLS_MMR_XBIST_H_INV_SHFT 40 +#define SH_MD_DQLS_MMR_XBIST_H_INV_MASK 0x0000010000000000 + +/* SH_MD_DQLS_MMR_XBIST_H_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQLS_MMR_XBIST_H_ROT_SHFT 41 +#define SH_MD_DQLS_MMR_XBIST_H_ROT_MASK 0x0000020000000000 + +/* SH_MD_DQLS_MMR_XBIST_H_ARM */ +/* Description: writing 1 arms data miscompare capture */ +#define SH_MD_DQLS_MMR_XBIST_H_ARM_SHFT 42 +#define SH_MD_DQLS_MMR_XBIST_H_ARM_MASK 0x0000040000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_XBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLS_MMR_XBIST_L 0x0000000100048010 +#define SH_MD_DQLS_MMR_XBIST_L_MASK 0x000003ffffffffff +#define SH_MD_DQLS_MMR_XBIST_L_INIT 0x0000000000000000 + +/* SH_MD_DQLS_MMR_XBIST_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLS_MMR_XBIST_L_PAT_SHFT 0 +#define SH_MD_DQLS_MMR_XBIST_L_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQLS_MMR_XBIST_L_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQLS_MMR_XBIST_L_INV_SHFT 40 +#define SH_MD_DQLS_MMR_XBIST_L_INV_MASK 0x0000010000000000 + +/* SH_MD_DQLS_MMR_XBIST_L_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQLS_MMR_XBIST_L_ROT_SHFT 41 +#define SH_MD_DQLS_MMR_XBIST_L_ROT_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_XBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLS_MMR_XBIST_ERR_H 0x0000000100048020 +#define SH_MD_DQLS_MMR_XBIST_ERR_H_MASK 0x000003ffffffffff +#define SH_MD_DQLS_MMR_XBIST_ERR_H_INIT 0x0000000000000000 + +/* SH_MD_DQLS_MMR_XBIST_ERR_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_SHFT 0 +#define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQLS_MMR_XBIST_ERR_H_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_SHFT 40 +#define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQLS_MMR_XBIST_ERR_H_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_SHFT 41 +#define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_XBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLS_MMR_XBIST_ERR_L 0x0000000100048030 +#define SH_MD_DQLS_MMR_XBIST_ERR_L_MASK 0x000003ffffffffff +#define SH_MD_DQLS_MMR_XBIST_ERR_L_INIT 0x0000000000000000 + +/* SH_MD_DQLS_MMR_XBIST_ERR_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_SHFT 0 +#define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQLS_MMR_XBIST_ERR_L_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_SHFT 40 +#define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQLS_MMR_XBIST_ERR_L_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_SHFT 41 +#define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_YBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLS_MMR_YBIST_H 0x0000000100048800 +#define SH_MD_DQLS_MMR_YBIST_H_MASK 0x000007ffffffffff +#define SH_MD_DQLS_MMR_YBIST_H_INIT 0x0000000000000000 + +/* SH_MD_DQLS_MMR_YBIST_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLS_MMR_YBIST_H_PAT_SHFT 0 +#define SH_MD_DQLS_MMR_YBIST_H_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQLS_MMR_YBIST_H_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQLS_MMR_YBIST_H_INV_SHFT 40 +#define SH_MD_DQLS_MMR_YBIST_H_INV_MASK 0x0000010000000000 + +/* SH_MD_DQLS_MMR_YBIST_H_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQLS_MMR_YBIST_H_ROT_SHFT 41 +#define SH_MD_DQLS_MMR_YBIST_H_ROT_MASK 0x0000020000000000 + +/* SH_MD_DQLS_MMR_YBIST_H_ARM */ +/* Description: writing 1 arms data miscompare capture */ +#define SH_MD_DQLS_MMR_YBIST_H_ARM_SHFT 42 +#define SH_MD_DQLS_MMR_YBIST_H_ARM_MASK 0x0000040000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_YBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLS_MMR_YBIST_L 0x0000000100048810 +#define SH_MD_DQLS_MMR_YBIST_L_MASK 0x000003ffffffffff +#define SH_MD_DQLS_MMR_YBIST_L_INIT 0x0000000000000000 + +/* SH_MD_DQLS_MMR_YBIST_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLS_MMR_YBIST_L_PAT_SHFT 0 +#define SH_MD_DQLS_MMR_YBIST_L_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQLS_MMR_YBIST_L_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQLS_MMR_YBIST_L_INV_SHFT 40 +#define SH_MD_DQLS_MMR_YBIST_L_INV_MASK 0x0000010000000000 + +/* SH_MD_DQLS_MMR_YBIST_L_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQLS_MMR_YBIST_L_ROT_SHFT 41 +#define SH_MD_DQLS_MMR_YBIST_L_ROT_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_YBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLS_MMR_YBIST_ERR_H 0x0000000100048820 +#define SH_MD_DQLS_MMR_YBIST_ERR_H_MASK 0x000003ffffffffff +#define SH_MD_DQLS_MMR_YBIST_ERR_H_INIT 0x0000000000000000 + +/* SH_MD_DQLS_MMR_YBIST_ERR_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_SHFT 0 +#define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQLS_MMR_YBIST_ERR_H_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_SHFT 40 +#define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQLS_MMR_YBIST_ERR_H_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_SHFT 41 +#define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_YBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQLS_MMR_YBIST_ERR_L 0x0000000100048830 +#define SH_MD_DQLS_MMR_YBIST_ERR_L_MASK 0x000003ffffffffff +#define SH_MD_DQLS_MMR_YBIST_ERR_L_INIT 0x0000000000000000 + +/* SH_MD_DQLS_MMR_YBIST_ERR_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_SHFT 0 +#define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQLS_MMR_YBIST_ERR_L_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_SHFT 40 +#define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQLS_MMR_YBIST_ERR_L_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_SHFT 41 +#define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_JNR_DEBUG" */ +/* joiner/fct debug configuration */ +/* ==================================================================== */ + +#define SH_MD_DQLS_MMR_JNR_DEBUG 0x0000000100049000 +#define SH_MD_DQLS_MMR_JNR_DEBUG_MASK 0x0000000000000003 +#define SH_MD_DQLS_MMR_JNR_DEBUG_INIT 0x0000000000000000 + +/* SH_MD_DQLS_MMR_JNR_DEBUG_PX */ +/* Description: select 0=pi 1=xn side */ +#define SH_MD_DQLS_MMR_JNR_DEBUG_PX_SHFT 0 +#define SH_MD_DQLS_MMR_JNR_DEBUG_PX_MASK 0x0000000000000001 + +/* SH_MD_DQLS_MMR_JNR_DEBUG_RW */ +/* Description: select 0=read 1=write side */ +#define SH_MD_DQLS_MMR_JNR_DEBUG_RW_SHFT 1 +#define SH_MD_DQLS_MMR_JNR_DEBUG_RW_MASK 0x0000000000000002 + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_XAMOPW_ERR" */ +/* amo/partial rmw ecc error register */ +/* ==================================================================== */ + +#define SH_MD_DQLS_MMR_XAMOPW_ERR 0x000000010004a000 +#define SH_MD_DQLS_MMR_XAMOPW_ERR_MASK 0x0000000103ff03ff +#define SH_MD_DQLS_MMR_XAMOPW_ERR_INIT 0x0000000000000000 + +/* SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN */ +/* Description: store data syndrome */ +#define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_SHFT 0 +#define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_MASK 0x00000000000000ff + +/* SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR */ +/* Description: correctable ecc errror on store data */ +#define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_SHFT 8 +#define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_MASK 0x0000000000000100 + +/* SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC */ +/* Description: uncorrectable ecc errror on store data */ +#define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_SHFT 9 +#define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_MASK 0x0000000000000200 + +/* SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN */ +/* Description: memory read data syndrome */ +#define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_SHFT 16 +#define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_MASK 0x0000000000ff0000 + +/* SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR */ +/* Description: correctable ecc errror on read data */ +#define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_SHFT 24 +#define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_MASK 0x0000000001000000 + +/* SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC */ +/* Description: uncorrectable ecc errror on read data */ +#define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_SHFT 25 +#define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_MASK 0x0000000002000000 + +/* SH_MD_DQLS_MMR_XAMOPW_ERR_ARM */ +/* Description: writing 1 arms ecc error capture */ +#define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_SHFT 32 +#define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_MASK 0x0000000100000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_CONFIG" */ +/* DQ directory config register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_CONFIG 0x0000000100050000 +#define SH_MD_DQRP_MMR_DIR_CONFIG_MASK 0x000000000000001f +#define SH_MD_DQRP_MMR_DIR_CONFIG_INIT 0x0000000000000010 + +/* SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE */ +/* Description: system size code */ +#define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_MASK 0x0000000000000007 + +/* SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC */ +/* Description: enable directory ecc correction */ +#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3 +#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008 + +/* SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS */ +/* Description: enable local poisoning for dir table fall-through */ +#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4 +#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC0" */ +/* node [63:0] presence bits */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRESVEC0 0x0000000100050100 +#define SH_MD_DQRP_MMR_DIR_PRESVEC0_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_PRESVEC0_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC */ +/* Description: node presence bits, 1=present */ +#define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC1" */ +/* node [127:64] presence bits */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRESVEC1 0x0000000100050110 +#define SH_MD_DQRP_MMR_DIR_PRESVEC1_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_PRESVEC1_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC */ +/* Description: node presence bits, 1=present */ +#define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC2" */ +/* node [191:128] presence bits */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRESVEC2 0x0000000100050120 +#define SH_MD_DQRP_MMR_DIR_PRESVEC2_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_PRESVEC2_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC */ +/* Description: node presence bits, 1=present */ +#define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC3" */ +/* node [255:192] presence bits */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRESVEC3 0x0000000100050130 +#define SH_MD_DQRP_MMR_DIR_PRESVEC3_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_PRESVEC3_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC */ +/* Description: node presence bits, 1=present */ +#define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC0" */ +/* local vector for acc=0 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_LOCVEC0 0x0000000100050200 +#define SH_MD_DQRP_MMR_DIR_LOCVEC0_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_LOCVEC0_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC1" */ +/* local vector for acc=1 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_LOCVEC1 0x0000000100050210 +#define SH_MD_DQRP_MMR_DIR_LOCVEC1_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_LOCVEC1_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC2" */ +/* local vector for acc=2 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_LOCVEC2 0x0000000100050220 +#define SH_MD_DQRP_MMR_DIR_LOCVEC2_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_LOCVEC2_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC3" */ +/* local vector for acc=3 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_LOCVEC3 0x0000000100050230 +#define SH_MD_DQRP_MMR_DIR_LOCVEC3_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_LOCVEC3_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC4" */ +/* local vector for acc=4 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_LOCVEC4 0x0000000100050240 +#define SH_MD_DQRP_MMR_DIR_LOCVEC4_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_LOCVEC4_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC5" */ +/* local vector for acc=5 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_LOCVEC5 0x0000000100050250 +#define SH_MD_DQRP_MMR_DIR_LOCVEC5_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_LOCVEC5_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC6" */ +/* local vector for acc=6 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_LOCVEC6 0x0000000100050260 +#define SH_MD_DQRP_MMR_DIR_LOCVEC6_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_LOCVEC6_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC7" */ +/* local vector for acc=7 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_LOCVEC7 0x0000000100050270 +#define SH_MD_DQRP_MMR_DIR_LOCVEC7_MASK 0xffffffffffffffff +#define SH_MD_DQRP_MMR_DIR_LOCVEC7_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC */ +/* Description: 1 node is local */ +#define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_MASK 0xffffffffffffffff + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ +/* privilege vector for acc=0 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300 +#define SH_MD_DQRP_MMR_DIR_PRIVEC0_MASK 0x000000000fffffff +#define SH_MD_DQRP_MMR_DIR_PRIVEC0_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRIVEC0_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_MASK 0x0000000000003fff + +/* SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_SHFT 14 +#define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC1" */ +/* privilege vector for acc=1 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRIVEC1 0x0000000100050310 +#define SH_MD_DQRP_MMR_DIR_PRIVEC1_MASK 0x000000000fffffff +#define SH_MD_DQRP_MMR_DIR_PRIVEC1_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRIVEC1_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_MASK 0x0000000000003fff + +/* SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_SHFT 14 +#define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC2" */ +/* privilege vector for acc=2 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRIVEC2 0x0000000100050320 +#define SH_MD_DQRP_MMR_DIR_PRIVEC2_MASK 0x000000000fffffff +#define SH_MD_DQRP_MMR_DIR_PRIVEC2_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRIVEC2_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_MASK 0x0000000000003fff + +/* SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_SHFT 14 +#define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC3" */ +/* privilege vector for acc=3 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRIVEC3 0x0000000100050330 +#define SH_MD_DQRP_MMR_DIR_PRIVEC3_MASK 0x000000000fffffff +#define SH_MD_DQRP_MMR_DIR_PRIVEC3_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRIVEC3_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_MASK 0x0000000000003fff + +/* SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_SHFT 14 +#define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC4" */ +/* privilege vector for acc=4 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRIVEC4 0x0000000100050340 +#define SH_MD_DQRP_MMR_DIR_PRIVEC4_MASK 0x000000000fffffff +#define SH_MD_DQRP_MMR_DIR_PRIVEC4_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRIVEC4_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_MASK 0x0000000000003fff + +/* SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_SHFT 14 +#define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC5" */ +/* privilege vector for acc=5 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRIVEC5 0x0000000100050350 +#define SH_MD_DQRP_MMR_DIR_PRIVEC5_MASK 0x000000000fffffff +#define SH_MD_DQRP_MMR_DIR_PRIVEC5_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRIVEC5_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_MASK 0x0000000000003fff + +/* SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_SHFT 14 +#define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC6" */ +/* privilege vector for acc=6 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRIVEC6 0x0000000100050360 +#define SH_MD_DQRP_MMR_DIR_PRIVEC6_MASK 0x000000000fffffff +#define SH_MD_DQRP_MMR_DIR_PRIVEC6_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRIVEC6_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_MASK 0x0000000000003fff + +/* SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_SHFT 14 +#define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC7" */ +/* privilege vector for acc=7 */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_PRIVEC7 0x0000000100050370 +#define SH_MD_DQRP_MMR_DIR_PRIVEC7_MASK 0x000000000fffffff +#define SH_MD_DQRP_MMR_DIR_PRIVEC7_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_PRIVEC7_IN */ +/* Description: in partition privileges, locvec bit=1 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_MASK 0x0000000000003fff + +/* SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT */ +/* Description: out of partition privileges, locvec bit=0 */ +#define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_SHFT 14 +#define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_MASK 0x000000000fffc000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_TIMER" */ +/* MD SXRO timer */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_TIMER 0x0000000100050400 +#define SH_MD_DQRP_MMR_DIR_TIMER_MASK 0x00000000003fffff +#define SH_MD_DQRP_MMR_DIR_TIMER_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV */ +/* Description: timer divide register */ +#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_MASK 0x0000000000000fff + +/* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN */ +/* Description: timer enable */ +#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_SHFT 12 +#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_MASK 0x0000000000001000 + +/* SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR */ +/* Description: value of current timer */ +#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_SHFT 13 +#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_MASK 0x00000000003fe000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY" */ +/* directory pio write data */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY 0x0000000100051000 +#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_MASK 0x03ffffffffffffff +#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA */ +/* Description: directory entry A */ +#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0 +#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff + +/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB */ +/* Description: directory entry B */ +#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26 +#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000 + +/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI */ +/* Description: directory priority */ +#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT 52 +#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_MASK 0x0070000000000000 + +/* SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC */ +/* Description: directory access bits */ +#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT 55 +#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_MASK 0x0380000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC" */ +/* directory ecc register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC 0x0000000100051010 +#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_MASK 0x0000000000003fff +#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA */ +/* Description: XOR bits for directory ECC group 1 */ +#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_SHFT 0 +#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_MASK 0x000000000000007f + +/* SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB */ +/* Description: XOR bits for directory ECC group 2 */ +#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_SHFT 7 +#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_MASK 0x0000000000003f80 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY" */ +/* x directory pio read data */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY 0x0000000100052000 +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_MASK 0x0fffffffffffffff +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA */ +/* Description: directory entry A */ +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0 +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff + +/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB */ +/* Description: directory entry B */ +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26 +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 + +/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI */ +/* Description: directory priority */ +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52 +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000 + +/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC */ +/* Description: directory access bits */ +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55 +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000 + +/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR */ +/* Description: correctable ecc error */ +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58 +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000 + +/* SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC */ +/* Description: uncorrectable ecc error */ +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59 +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC" */ +/* x directory ecc */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC 0x0000000100052010 +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_MASK 0x0000000000003fff +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA */ +/* Description: group 1 ecc */ +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0 +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f + +/* SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB */ +/* Description: group 2 ecc */ +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7 +#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY" */ +/* y directory pio read data */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY 0x0000000100052800 +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_MASK 0x0fffffffffffffff +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA */ +/* Description: directory entry A */ +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0 +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff + +/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB */ +/* Description: directory entry B */ +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26 +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000 + +/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI */ +/* Description: directory priority */ +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52 +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000 + +/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC */ +/* Description: directory access bits */ +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55 +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000 + +/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR */ +/* Description: correctable ecc error */ +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58 +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000 + +/* SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC */ +/* Description: uncorrectable ecc error */ +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59 +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC" */ +/* y directory ecc */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC 0x0000000100052810 +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_MASK 0x0000000000003fff +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA */ +/* Description: group 1 ecc */ +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0 +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f + +/* SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB */ +/* Description: group 2 ecc */ +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7 +#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XCERR1" */ +/* correctable dir ecc group 1 error register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_XCERR1 0x0000000100053000 +#define SH_MD_DQRP_MMR_XCERR1_MASK 0x0000007fffffffff +#define SH_MD_DQRP_MMR_XCERR1_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_XCERR1_GRP1 */ +/* Description: ecc group 1 bits */ +#define SH_MD_DQRP_MMR_XCERR1_GRP1_SHFT 0 +#define SH_MD_DQRP_MMR_XCERR1_GRP1_MASK 0x0000000fffffffff + +/* SH_MD_DQRP_MMR_XCERR1_VAL */ +/* Description: correctable ecc error in group 1 bits */ +#define SH_MD_DQRP_MMR_XCERR1_VAL_SHFT 36 +#define SH_MD_DQRP_MMR_XCERR1_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQRP_MMR_XCERR1_MORE */ +/* Description: more than one correctable ecc error in group 1 */ +#define SH_MD_DQRP_MMR_XCERR1_MORE_SHFT 37 +#define SH_MD_DQRP_MMR_XCERR1_MORE_MASK 0x0000002000000000 + +/* SH_MD_DQRP_MMR_XCERR1_ARM */ +/* Description: writing 1 arms uncorrectable ecc error capture */ +#define SH_MD_DQRP_MMR_XCERR1_ARM_SHFT 38 +#define SH_MD_DQRP_MMR_XCERR1_ARM_MASK 0x0000004000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XCERR2" */ +/* correctable dir ecc group 2 error register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_XCERR2 0x0000000100053010 +#define SH_MD_DQRP_MMR_XCERR2_MASK 0x0000003fffffffff +#define SH_MD_DQRP_MMR_XCERR2_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_XCERR2_GRP2 */ +/* Description: ecc group 2 bits */ +#define SH_MD_DQRP_MMR_XCERR2_GRP2_SHFT 0 +#define SH_MD_DQRP_MMR_XCERR2_GRP2_MASK 0x0000000fffffffff + +/* SH_MD_DQRP_MMR_XCERR2_VAL */ +/* Description: correctable ecc error in group 2 bits */ +#define SH_MD_DQRP_MMR_XCERR2_VAL_SHFT 36 +#define SH_MD_DQRP_MMR_XCERR2_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQRP_MMR_XCERR2_MORE */ +/* Description: more than one correctable ecc error in group 2 */ +#define SH_MD_DQRP_MMR_XCERR2_MORE_SHFT 37 +#define SH_MD_DQRP_MMR_XCERR2_MORE_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XUERR1" */ +/* uncorrectable dir ecc group 1 error register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_XUERR1 0x0000000100053020 +#define SH_MD_DQRP_MMR_XUERR1_MASK 0x0000007fffffffff +#define SH_MD_DQRP_MMR_XUERR1_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_XUERR1_GRP1 */ +/* Description: ecc group 1 bits */ +#define SH_MD_DQRP_MMR_XUERR1_GRP1_SHFT 0 +#define SH_MD_DQRP_MMR_XUERR1_GRP1_MASK 0x0000000fffffffff + +/* SH_MD_DQRP_MMR_XUERR1_VAL */ +/* Description: uncorrectable ecc error in group 1 bits */ +#define SH_MD_DQRP_MMR_XUERR1_VAL_SHFT 36 +#define SH_MD_DQRP_MMR_XUERR1_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQRP_MMR_XUERR1_MORE */ +/* Description: more than one uncorrectable ecc error in group 1 */ +#define SH_MD_DQRP_MMR_XUERR1_MORE_SHFT 37 +#define SH_MD_DQRP_MMR_XUERR1_MORE_MASK 0x0000002000000000 + +/* SH_MD_DQRP_MMR_XUERR1_ARM */ +/* Description: writing 1 arms uncorrectable ecc error capture */ +#define SH_MD_DQRP_MMR_XUERR1_ARM_SHFT 38 +#define SH_MD_DQRP_MMR_XUERR1_ARM_MASK 0x0000004000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XUERR2" */ +/* uncorrectable dir ecc group 2 error register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_XUERR2 0x0000000100053030 +#define SH_MD_DQRP_MMR_XUERR2_MASK 0x0000003fffffffff +#define SH_MD_DQRP_MMR_XUERR2_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_XUERR2_GRP2 */ +/* Description: ecc group 2 bits */ +#define SH_MD_DQRP_MMR_XUERR2_GRP2_SHFT 0 +#define SH_MD_DQRP_MMR_XUERR2_GRP2_MASK 0x0000000fffffffff + +/* SH_MD_DQRP_MMR_XUERR2_VAL */ +/* Description: uncorrectable ecc error in group 2 bits */ +#define SH_MD_DQRP_MMR_XUERR2_VAL_SHFT 36 +#define SH_MD_DQRP_MMR_XUERR2_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQRP_MMR_XUERR2_MORE */ +/* Description: more than one uncorrectable ecc error in group 2 */ +#define SH_MD_DQRP_MMR_XUERR2_MORE_SHFT 37 +#define SH_MD_DQRP_MMR_XUERR2_MORE_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XPERR" */ +/* protocol error register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_XPERR 0x0000000100053040 +#define SH_MD_DQRP_MMR_XPERR_MASK 0x7fffffffffffffff +#define SH_MD_DQRP_MMR_XPERR_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_XPERR_DIR */ +/* Description: directory entry */ +#define SH_MD_DQRP_MMR_XPERR_DIR_SHFT 0 +#define SH_MD_DQRP_MMR_XPERR_DIR_MASK 0x0000000003ffffff + +/* SH_MD_DQRP_MMR_XPERR_CMD */ +/* Description: incoming command */ +#define SH_MD_DQRP_MMR_XPERR_CMD_SHFT 26 +#define SH_MD_DQRP_MMR_XPERR_CMD_MASK 0x00000003fc000000 + +/* SH_MD_DQRP_MMR_XPERR_SRC */ +/* Description: source node of dir operation */ +#define SH_MD_DQRP_MMR_XPERR_SRC_SHFT 34 +#define SH_MD_DQRP_MMR_XPERR_SRC_MASK 0x0000fffc00000000 + +/* SH_MD_DQRP_MMR_XPERR_PRIGE */ +/* Description: priority was greater-equal */ +#define SH_MD_DQRP_MMR_XPERR_PRIGE_SHFT 48 +#define SH_MD_DQRP_MMR_XPERR_PRIGE_MASK 0x0001000000000000 + +/* SH_MD_DQRP_MMR_XPERR_PRIV */ +/* Description: access privilege bit */ +#define SH_MD_DQRP_MMR_XPERR_PRIV_SHFT 49 +#define SH_MD_DQRP_MMR_XPERR_PRIV_MASK 0x0002000000000000 + +/* SH_MD_DQRP_MMR_XPERR_COR */ +/* Description: correctable ecc error */ +#define SH_MD_DQRP_MMR_XPERR_COR_SHFT 50 +#define SH_MD_DQRP_MMR_XPERR_COR_MASK 0x0004000000000000 + +/* SH_MD_DQRP_MMR_XPERR_UNC */ +/* Description: uncorrectable ecc error */ +#define SH_MD_DQRP_MMR_XPERR_UNC_SHFT 51 +#define SH_MD_DQRP_MMR_XPERR_UNC_MASK 0x0008000000000000 + +/* SH_MD_DQRP_MMR_XPERR_MYBIT */ +/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ +#define SH_MD_DQRP_MMR_XPERR_MYBIT_SHFT 52 +#define SH_MD_DQRP_MMR_XPERR_MYBIT_MASK 0x0ff0000000000000 + +/* SH_MD_DQRP_MMR_XPERR_VAL */ +/* Description: protocol error info valid */ +#define SH_MD_DQRP_MMR_XPERR_VAL_SHFT 60 +#define SH_MD_DQRP_MMR_XPERR_VAL_MASK 0x1000000000000000 + +/* SH_MD_DQRP_MMR_XPERR_MORE */ +/* Description: more than one protocol error */ +#define SH_MD_DQRP_MMR_XPERR_MORE_SHFT 61 +#define SH_MD_DQRP_MMR_XPERR_MORE_MASK 0x2000000000000000 + +/* SH_MD_DQRP_MMR_XPERR_ARM */ +/* Description: writing 1 arms error capture */ +#define SH_MD_DQRP_MMR_XPERR_ARM_SHFT 62 +#define SH_MD_DQRP_MMR_XPERR_ARM_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YCERR1" */ +/* correctable dir ecc group 1 error register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_YCERR1 0x0000000100053800 +#define SH_MD_DQRP_MMR_YCERR1_MASK 0x0000007fffffffff +#define SH_MD_DQRP_MMR_YCERR1_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_YCERR1_GRP1 */ +/* Description: ecc group 1 bits */ +#define SH_MD_DQRP_MMR_YCERR1_GRP1_SHFT 0 +#define SH_MD_DQRP_MMR_YCERR1_GRP1_MASK 0x0000000fffffffff + +/* SH_MD_DQRP_MMR_YCERR1_VAL */ +/* Description: correctable ecc error in group 1 bits */ +#define SH_MD_DQRP_MMR_YCERR1_VAL_SHFT 36 +#define SH_MD_DQRP_MMR_YCERR1_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQRP_MMR_YCERR1_MORE */ +/* Description: more than one correctable ecc error in group 1 */ +#define SH_MD_DQRP_MMR_YCERR1_MORE_SHFT 37 +#define SH_MD_DQRP_MMR_YCERR1_MORE_MASK 0x0000002000000000 + +/* SH_MD_DQRP_MMR_YCERR1_ARM */ +/* Description: writing 1 arms uncorrectable ecc error capture */ +#define SH_MD_DQRP_MMR_YCERR1_ARM_SHFT 38 +#define SH_MD_DQRP_MMR_YCERR1_ARM_MASK 0x0000004000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YCERR2" */ +/* correctable dir ecc group 2 error register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_YCERR2 0x0000000100053810 +#define SH_MD_DQRP_MMR_YCERR2_MASK 0x0000003fffffffff +#define SH_MD_DQRP_MMR_YCERR2_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_YCERR2_GRP2 */ +/* Description: ecc group 2 bits */ +#define SH_MD_DQRP_MMR_YCERR2_GRP2_SHFT 0 +#define SH_MD_DQRP_MMR_YCERR2_GRP2_MASK 0x0000000fffffffff + +/* SH_MD_DQRP_MMR_YCERR2_VAL */ +/* Description: correctable ecc error in group 2 bits */ +#define SH_MD_DQRP_MMR_YCERR2_VAL_SHFT 36 +#define SH_MD_DQRP_MMR_YCERR2_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQRP_MMR_YCERR2_MORE */ +/* Description: more than one correctable ecc error in group 2 */ +#define SH_MD_DQRP_MMR_YCERR2_MORE_SHFT 37 +#define SH_MD_DQRP_MMR_YCERR2_MORE_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YUERR1" */ +/* uncorrectable dir ecc group 1 error register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_YUERR1 0x0000000100053820 +#define SH_MD_DQRP_MMR_YUERR1_MASK 0x0000007fffffffff +#define SH_MD_DQRP_MMR_YUERR1_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_YUERR1_GRP1 */ +/* Description: ecc group 1 bits */ +#define SH_MD_DQRP_MMR_YUERR1_GRP1_SHFT 0 +#define SH_MD_DQRP_MMR_YUERR1_GRP1_MASK 0x0000000fffffffff + +/* SH_MD_DQRP_MMR_YUERR1_VAL */ +/* Description: uncorrectable ecc error in group 1 bits */ +#define SH_MD_DQRP_MMR_YUERR1_VAL_SHFT 36 +#define SH_MD_DQRP_MMR_YUERR1_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQRP_MMR_YUERR1_MORE */ +/* Description: more than one uncorrectable ecc error in group 1 */ +#define SH_MD_DQRP_MMR_YUERR1_MORE_SHFT 37 +#define SH_MD_DQRP_MMR_YUERR1_MORE_MASK 0x0000002000000000 + +/* SH_MD_DQRP_MMR_YUERR1_ARM */ +/* Description: writing 1 arms uncorrectable ecc error capture */ +#define SH_MD_DQRP_MMR_YUERR1_ARM_SHFT 38 +#define SH_MD_DQRP_MMR_YUERR1_ARM_MASK 0x0000004000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YUERR2" */ +/* uncorrectable dir ecc group 2 error register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_YUERR2 0x0000000100053830 +#define SH_MD_DQRP_MMR_YUERR2_MASK 0x0000003fffffffff +#define SH_MD_DQRP_MMR_YUERR2_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_YUERR2_GRP2 */ +/* Description: ecc group 2 bits */ +#define SH_MD_DQRP_MMR_YUERR2_GRP2_SHFT 0 +#define SH_MD_DQRP_MMR_YUERR2_GRP2_MASK 0x0000000fffffffff + +/* SH_MD_DQRP_MMR_YUERR2_VAL */ +/* Description: uncorrectable ecc error in group 2 bits */ +#define SH_MD_DQRP_MMR_YUERR2_VAL_SHFT 36 +#define SH_MD_DQRP_MMR_YUERR2_VAL_MASK 0x0000001000000000 + +/* SH_MD_DQRP_MMR_YUERR2_MORE */ +/* Description: more than one uncorrectable ecc error in group 2 */ +#define SH_MD_DQRP_MMR_YUERR2_MORE_SHFT 37 +#define SH_MD_DQRP_MMR_YUERR2_MORE_MASK 0x0000002000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YPERR" */ +/* protocol error register */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_YPERR 0x0000000100053840 +#define SH_MD_DQRP_MMR_YPERR_MASK 0x7fffffffffffffff +#define SH_MD_DQRP_MMR_YPERR_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_YPERR_DIR */ +/* Description: directory entry */ +#define SH_MD_DQRP_MMR_YPERR_DIR_SHFT 0 +#define SH_MD_DQRP_MMR_YPERR_DIR_MASK 0x0000000003ffffff + +/* SH_MD_DQRP_MMR_YPERR_CMD */ +/* Description: incoming command */ +#define SH_MD_DQRP_MMR_YPERR_CMD_SHFT 26 +#define SH_MD_DQRP_MMR_YPERR_CMD_MASK 0x00000003fc000000 + +/* SH_MD_DQRP_MMR_YPERR_SRC */ +/* Description: source node of dir operation */ +#define SH_MD_DQRP_MMR_YPERR_SRC_SHFT 34 +#define SH_MD_DQRP_MMR_YPERR_SRC_MASK 0x0000fffc00000000 + +/* SH_MD_DQRP_MMR_YPERR_PRIGE */ +/* Description: priority was greater-equal */ +#define SH_MD_DQRP_MMR_YPERR_PRIGE_SHFT 48 +#define SH_MD_DQRP_MMR_YPERR_PRIGE_MASK 0x0001000000000000 + +/* SH_MD_DQRP_MMR_YPERR_PRIV */ +/* Description: access privilege bit */ +#define SH_MD_DQRP_MMR_YPERR_PRIV_SHFT 49 +#define SH_MD_DQRP_MMR_YPERR_PRIV_MASK 0x0002000000000000 + +/* SH_MD_DQRP_MMR_YPERR_COR */ +/* Description: correctable ecc error */ +#define SH_MD_DQRP_MMR_YPERR_COR_SHFT 50 +#define SH_MD_DQRP_MMR_YPERR_COR_MASK 0x0004000000000000 + +/* SH_MD_DQRP_MMR_YPERR_UNC */ +/* Description: uncorrectable ecc error */ +#define SH_MD_DQRP_MMR_YPERR_UNC_SHFT 51 +#define SH_MD_DQRP_MMR_YPERR_UNC_MASK 0x0008000000000000 + +/* SH_MD_DQRP_MMR_YPERR_MYBIT */ +/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ +#define SH_MD_DQRP_MMR_YPERR_MYBIT_SHFT 52 +#define SH_MD_DQRP_MMR_YPERR_MYBIT_MASK 0x0ff0000000000000 + +/* SH_MD_DQRP_MMR_YPERR_VAL */ +/* Description: protocol error info valid */ +#define SH_MD_DQRP_MMR_YPERR_VAL_SHFT 60 +#define SH_MD_DQRP_MMR_YPERR_VAL_MASK 0x1000000000000000 + +/* SH_MD_DQRP_MMR_YPERR_MORE */ +/* Description: more than one protocol error */ +#define SH_MD_DQRP_MMR_YPERR_MORE_SHFT 61 +#define SH_MD_DQRP_MMR_YPERR_MORE_MASK 0x2000000000000000 + +/* SH_MD_DQRP_MMR_YPERR_ARM */ +/* Description: writing 1 arms error capture */ +#define SH_MD_DQRP_MMR_YPERR_ARM_SHFT 62 +#define SH_MD_DQRP_MMR_YPERR_ARM_MASK 0x4000000000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_CMDTRIG" */ +/* cmd triggers */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_CMDTRIG 0x0000000100054000 +#define SH_MD_DQRP_MMR_DIR_CMDTRIG_MASK 0x00000000ffffffff +#define SH_MD_DQRP_MMR_DIR_CMDTRIG_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0 */ +/* Description: command trigger 0 */ +#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_MASK 0x00000000000000ff + +/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1 */ +/* Description: command trigger 1 */ +#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_SHFT 8 +#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_MASK 0x000000000000ff00 + +/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2 */ +/* Description: command trigger 2 */ +#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_SHFT 16 +#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_MASK 0x0000000000ff0000 + +/* SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3 */ +/* Description: command trigger 3 */ +#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_SHFT 24 +#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_MASK 0x00000000ff000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_TBLTRIG" */ +/* dir table trigger */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_TBLTRIG 0x0000000100054010 +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MASK 0x000003ffffffffff +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC */ +/* Description: source of request */ +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_MASK 0x0000000000003fff + +/* SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD */ +/* Description: incoming request */ +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_SHFT 14 +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_MASK 0x00000000003fc000 + +/* SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC */ +/* Description: uncorrectable error, privilege bit */ +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_SHFT 22 +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_MASK 0x0000000000c00000 + +/* SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE */ +/* Description: priority greater-equal */ +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_SHFT 24 +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_MASK 0x0000000001000000 + +/* SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST */ +/* Description: shrd,sxro,sub-state */ +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_SHFT 25 +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_MASK 0x00000003fe000000 + +/* SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT */ +/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_SHFT 34 +#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_MASK 0x000003fc00000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_TBLMASK" */ +/* dir table trigger mask */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_DIR_TBLMASK 0x0000000100054020 +#define SH_MD_DQRP_MMR_DIR_TBLMASK_MASK 0x000003ffffffffff +#define SH_MD_DQRP_MMR_DIR_TBLMASK_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_DIR_TBLMASK_SRC */ +/* Description: source of request */ +#define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_SHFT 0 +#define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_MASK 0x0000000000003fff + +/* SH_MD_DQRP_MMR_DIR_TBLMASK_CMD */ +/* Description: incoming request */ +#define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_SHFT 14 +#define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_MASK 0x00000000003fc000 + +/* SH_MD_DQRP_MMR_DIR_TBLMASK_ACC */ +/* Description: uncorrectable error, privilege bit */ +#define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_SHFT 22 +#define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_MASK 0x0000000000c00000 + +/* SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE */ +/* Description: priority greater-equal */ +#define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_SHFT 24 +#define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_MASK 0x0000000001000000 + +/* SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST */ +/* Description: shrd,sxro,sub-state */ +#define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_SHFT 25 +#define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_MASK 0x00000003fe000000 + +/* SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT */ +/* Description: ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src */ +#define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_SHFT 34 +#define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_MASK 0x000003fc00000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_XBIST_H 0x0000000100058000 +#define SH_MD_DQRP_MMR_XBIST_H_MASK 0x00000700ffffffff +#define SH_MD_DQRP_MMR_XBIST_H_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_XBIST_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRP_MMR_XBIST_H_PAT_SHFT 0 +#define SH_MD_DQRP_MMR_XBIST_H_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQRP_MMR_XBIST_H_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQRP_MMR_XBIST_H_INV_SHFT 40 +#define SH_MD_DQRP_MMR_XBIST_H_INV_MASK 0x0000010000000000 + +/* SH_MD_DQRP_MMR_XBIST_H_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQRP_MMR_XBIST_H_ROT_SHFT 41 +#define SH_MD_DQRP_MMR_XBIST_H_ROT_MASK 0x0000020000000000 + +/* SH_MD_DQRP_MMR_XBIST_H_ARM */ +/* Description: writing 1 arms data miscompare capture */ +#define SH_MD_DQRP_MMR_XBIST_H_ARM_SHFT 42 +#define SH_MD_DQRP_MMR_XBIST_H_ARM_MASK 0x0000040000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_XBIST_L 0x0000000100058010 +#define SH_MD_DQRP_MMR_XBIST_L_MASK 0x00000300ffffffff +#define SH_MD_DQRP_MMR_XBIST_L_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_XBIST_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRP_MMR_XBIST_L_PAT_SHFT 0 +#define SH_MD_DQRP_MMR_XBIST_L_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQRP_MMR_XBIST_L_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQRP_MMR_XBIST_L_INV_SHFT 40 +#define SH_MD_DQRP_MMR_XBIST_L_INV_MASK 0x0000010000000000 + +/* SH_MD_DQRP_MMR_XBIST_L_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQRP_MMR_XBIST_L_ROT_SHFT 41 +#define SH_MD_DQRP_MMR_XBIST_L_ROT_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_XBIST_ERR_H 0x0000000100058020 +#define SH_MD_DQRP_MMR_XBIST_ERR_H_MASK 0x00000300ffffffff +#define SH_MD_DQRP_MMR_XBIST_ERR_H_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_XBIST_ERR_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_SHFT 0 +#define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQRP_MMR_XBIST_ERR_H_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_SHFT 40 +#define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQRP_MMR_XBIST_ERR_H_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_SHFT 41 +#define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_XBIST_ERR_L 0x0000000100058030 +#define SH_MD_DQRP_MMR_XBIST_ERR_L_MASK 0x00000300ffffffff +#define SH_MD_DQRP_MMR_XBIST_ERR_L_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_XBIST_ERR_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_SHFT 0 +#define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQRP_MMR_XBIST_ERR_L_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_SHFT 40 +#define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQRP_MMR_XBIST_ERR_L_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_SHFT 41 +#define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_YBIST_H 0x0000000100058800 +#define SH_MD_DQRP_MMR_YBIST_H_MASK 0x00000700ffffffff +#define SH_MD_DQRP_MMR_YBIST_H_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_YBIST_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRP_MMR_YBIST_H_PAT_SHFT 0 +#define SH_MD_DQRP_MMR_YBIST_H_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQRP_MMR_YBIST_H_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQRP_MMR_YBIST_H_INV_SHFT 40 +#define SH_MD_DQRP_MMR_YBIST_H_INV_MASK 0x0000010000000000 + +/* SH_MD_DQRP_MMR_YBIST_H_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQRP_MMR_YBIST_H_ROT_SHFT 41 +#define SH_MD_DQRP_MMR_YBIST_H_ROT_MASK 0x0000020000000000 + +/* SH_MD_DQRP_MMR_YBIST_H_ARM */ +/* Description: writing 1 arms data miscompare capture */ +#define SH_MD_DQRP_MMR_YBIST_H_ARM_SHFT 42 +#define SH_MD_DQRP_MMR_YBIST_H_ARM_MASK 0x0000040000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_YBIST_L 0x0000000100058810 +#define SH_MD_DQRP_MMR_YBIST_L_MASK 0x00000300ffffffff +#define SH_MD_DQRP_MMR_YBIST_L_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_YBIST_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRP_MMR_YBIST_L_PAT_SHFT 0 +#define SH_MD_DQRP_MMR_YBIST_L_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQRP_MMR_YBIST_L_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQRP_MMR_YBIST_L_INV_SHFT 40 +#define SH_MD_DQRP_MMR_YBIST_L_INV_MASK 0x0000010000000000 + +/* SH_MD_DQRP_MMR_YBIST_L_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQRP_MMR_YBIST_L_ROT_SHFT 41 +#define SH_MD_DQRP_MMR_YBIST_L_ROT_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_YBIST_ERR_H 0x0000000100058820 +#define SH_MD_DQRP_MMR_YBIST_ERR_H_MASK 0x00000300ffffffff +#define SH_MD_DQRP_MMR_YBIST_ERR_H_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_YBIST_ERR_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_SHFT 0 +#define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQRP_MMR_YBIST_ERR_H_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_SHFT 40 +#define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQRP_MMR_YBIST_ERR_H_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_SHFT 41 +#define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRP_MMR_YBIST_ERR_L 0x0000000100058830 +#define SH_MD_DQRP_MMR_YBIST_ERR_L_MASK 0x00000300ffffffff +#define SH_MD_DQRP_MMR_YBIST_ERR_L_INIT 0x0000000000000000 + +/* SH_MD_DQRP_MMR_YBIST_ERR_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_SHFT 0 +#define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_MASK 0x00000000ffffffff + +/* SH_MD_DQRP_MMR_YBIST_ERR_L_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_SHFT 40 +#define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQRP_MMR_YBIST_ERR_L_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_SHFT 41 +#define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_XBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRS_MMR_XBIST_H 0x0000000100068000 +#define SH_MD_DQRS_MMR_XBIST_H_MASK 0x000007ffffffffff +#define SH_MD_DQRS_MMR_XBIST_H_INIT 0x0000000000000000 + +/* SH_MD_DQRS_MMR_XBIST_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRS_MMR_XBIST_H_PAT_SHFT 0 +#define SH_MD_DQRS_MMR_XBIST_H_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQRS_MMR_XBIST_H_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQRS_MMR_XBIST_H_INV_SHFT 40 +#define SH_MD_DQRS_MMR_XBIST_H_INV_MASK 0x0000010000000000 + +/* SH_MD_DQRS_MMR_XBIST_H_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQRS_MMR_XBIST_H_ROT_SHFT 41 +#define SH_MD_DQRS_MMR_XBIST_H_ROT_MASK 0x0000020000000000 + +/* SH_MD_DQRS_MMR_XBIST_H_ARM */ +/* Description: writing 1 arms data miscompare capture */ +#define SH_MD_DQRS_MMR_XBIST_H_ARM_SHFT 42 +#define SH_MD_DQRS_MMR_XBIST_H_ARM_MASK 0x0000040000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_XBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRS_MMR_XBIST_L 0x0000000100068010 +#define SH_MD_DQRS_MMR_XBIST_L_MASK 0x000003ffffffffff +#define SH_MD_DQRS_MMR_XBIST_L_INIT 0x0000000000000000 + +/* SH_MD_DQRS_MMR_XBIST_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRS_MMR_XBIST_L_PAT_SHFT 0 +#define SH_MD_DQRS_MMR_XBIST_L_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQRS_MMR_XBIST_L_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQRS_MMR_XBIST_L_INV_SHFT 40 +#define SH_MD_DQRS_MMR_XBIST_L_INV_MASK 0x0000010000000000 + +/* SH_MD_DQRS_MMR_XBIST_L_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQRS_MMR_XBIST_L_ROT_SHFT 41 +#define SH_MD_DQRS_MMR_XBIST_L_ROT_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_XBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRS_MMR_XBIST_ERR_H 0x0000000100068020 +#define SH_MD_DQRS_MMR_XBIST_ERR_H_MASK 0x000003ffffffffff +#define SH_MD_DQRS_MMR_XBIST_ERR_H_INIT 0x0000000000000000 + +/* SH_MD_DQRS_MMR_XBIST_ERR_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_SHFT 0 +#define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQRS_MMR_XBIST_ERR_H_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_SHFT 40 +#define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQRS_MMR_XBIST_ERR_H_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_SHFT 41 +#define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_XBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRS_MMR_XBIST_ERR_L 0x0000000100068030 +#define SH_MD_DQRS_MMR_XBIST_ERR_L_MASK 0x000003ffffffffff +#define SH_MD_DQRS_MMR_XBIST_ERR_L_INIT 0x0000000000000000 + +/* SH_MD_DQRS_MMR_XBIST_ERR_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_SHFT 0 +#define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQRS_MMR_XBIST_ERR_L_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_SHFT 40 +#define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQRS_MMR_XBIST_ERR_L_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_SHFT 41 +#define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_YBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRS_MMR_YBIST_H 0x0000000100068800 +#define SH_MD_DQRS_MMR_YBIST_H_MASK 0x000007ffffffffff +#define SH_MD_DQRS_MMR_YBIST_H_INIT 0x0000000000000000 + +/* SH_MD_DQRS_MMR_YBIST_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRS_MMR_YBIST_H_PAT_SHFT 0 +#define SH_MD_DQRS_MMR_YBIST_H_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQRS_MMR_YBIST_H_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQRS_MMR_YBIST_H_INV_SHFT 40 +#define SH_MD_DQRS_MMR_YBIST_H_INV_MASK 0x0000010000000000 + +/* SH_MD_DQRS_MMR_YBIST_H_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQRS_MMR_YBIST_H_ROT_SHFT 41 +#define SH_MD_DQRS_MMR_YBIST_H_ROT_MASK 0x0000020000000000 + +/* SH_MD_DQRS_MMR_YBIST_H_ARM */ +/* Description: writing 1 arms data miscompare capture */ +#define SH_MD_DQRS_MMR_YBIST_H_ARM_SHFT 42 +#define SH_MD_DQRS_MMR_YBIST_H_ARM_MASK 0x0000040000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_YBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRS_MMR_YBIST_L 0x0000000100068810 +#define SH_MD_DQRS_MMR_YBIST_L_MASK 0x000003ffffffffff +#define SH_MD_DQRS_MMR_YBIST_L_INIT 0x0000000000000000 + +/* SH_MD_DQRS_MMR_YBIST_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRS_MMR_YBIST_L_PAT_SHFT 0 +#define SH_MD_DQRS_MMR_YBIST_L_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQRS_MMR_YBIST_L_INV */ +/* Description: invert data pattern in next cycle */ +#define SH_MD_DQRS_MMR_YBIST_L_INV_SHFT 40 +#define SH_MD_DQRS_MMR_YBIST_L_INV_MASK 0x0000010000000000 + +/* SH_MD_DQRS_MMR_YBIST_L_ROT */ +/* Description: rotate left data pattern in next cycle */ +#define SH_MD_DQRS_MMR_YBIST_L_ROT_SHFT 41 +#define SH_MD_DQRS_MMR_YBIST_L_ROT_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_YBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRS_MMR_YBIST_ERR_H 0x0000000100068820 +#define SH_MD_DQRS_MMR_YBIST_ERR_H_MASK 0x000003ffffffffff +#define SH_MD_DQRS_MMR_YBIST_ERR_H_INIT 0x0000000000000000 + +/* SH_MD_DQRS_MMR_YBIST_ERR_H_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_SHFT 0 +#define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQRS_MMR_YBIST_ERR_H_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_SHFT 40 +#define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQRS_MMR_YBIST_ERR_H_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_SHFT 41 +#define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_YBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#define SH_MD_DQRS_MMR_YBIST_ERR_L 0x0000000100068830 +#define SH_MD_DQRS_MMR_YBIST_ERR_L_MASK 0x000003ffffffffff +#define SH_MD_DQRS_MMR_YBIST_ERR_L_INIT 0x0000000000000000 + +/* SH_MD_DQRS_MMR_YBIST_ERR_L_PAT */ +/* Description: data pattern */ +#define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_SHFT 0 +#define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_MASK 0x000000ffffffffff + +/* SH_MD_DQRS_MMR_YBIST_ERR_L_VAL */ +/* Description: bist data miscompare */ +#define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_SHFT 40 +#define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_MASK 0x0000010000000000 + +/* SH_MD_DQRS_MMR_YBIST_ERR_L_MORE */ +/* Description: more than one bist data miscompare */ +#define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_SHFT 41 +#define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_MASK 0x0000020000000000 + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_JNR_DEBUG" */ +/* joiner/fct debug configuration */ +/* ==================================================================== */ + +#define SH_MD_DQRS_MMR_JNR_DEBUG 0x0000000100069000 +#define SH_MD_DQRS_MMR_JNR_DEBUG_MASK 0x0000000000000003 +#define SH_MD_DQRS_MMR_JNR_DEBUG_INIT 0x0000000000000000 + +/* SH_MD_DQRS_MMR_JNR_DEBUG_PX */ +/* Description: select 0=pi 1=xn side */ +#define SH_MD_DQRS_MMR_JNR_DEBUG_PX_SHFT 0 +#define SH_MD_DQRS_MMR_JNR_DEBUG_PX_MASK 0x0000000000000001 + +/* SH_MD_DQRS_MMR_JNR_DEBUG_RW */ +/* Description: select 0=read 1=write side */ +#define SH_MD_DQRS_MMR_JNR_DEBUG_RW_SHFT 1 +#define SH_MD_DQRS_MMR_JNR_DEBUG_RW_MASK 0x0000000000000002 + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_YAMOPW_ERR" */ +/* amo/partial rmw ecc error register */ +/* ==================================================================== */ + +#define SH_MD_DQRS_MMR_YAMOPW_ERR 0x000000010006a000 +#define SH_MD_DQRS_MMR_YAMOPW_ERR_MASK 0x0000000103ff03ff +#define SH_MD_DQRS_MMR_YAMOPW_ERR_INIT 0x0000000000000000 + +/* SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN */ +/* Description: store data syndrome */ +#define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_SHFT 0 +#define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_MASK 0x00000000000000ff + +/* SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR */ +/* Description: correctable ecc errror on store data */ +#define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_SHFT 8 +#define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_MASK 0x0000000000000100 + +/* SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC */ +/* Description: uncorrectable ecc errror on store data */ +#define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_SHFT 9 +#define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_MASK 0x0000000000000200 + +/* SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN */ +/* Description: memory read data syndrome */ +#define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_SHFT 16 +#define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_MASK 0x0000000000ff0000 + +/* SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR */ +/* Description: correctable ecc errror on read data */ +#define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_SHFT 24 +#define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_MASK 0x0000000001000000 + +/* SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC */ +/* Description: uncorrectable ecc errror on read data */ +#define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_SHFT 25 +#define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_MASK 0x0000000002000000 + +/* SH_MD_DQRS_MMR_YAMOPW_ERR_ARM */ +/* Description: writing 1 arms ecc error capture */ +#define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_SHFT 32 +#define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_MASK 0x0000000100000000 + + +#endif /* _ASM_IA64_SN_SN2_SHUB_MMR_H */ diff --git a/include/asm-ia64/sn/sn2/shub_mmr_t.h b/include/asm-ia64/sn/sn2/shub_mmr_t.h new file mode 100644 index 000000000000..d2cef5e24a81 --- /dev/null +++ b/include/asm-ia64/sn/sn2/shub_mmr_t.h @@ -0,0 +1,27385 @@ +/* + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + */ + + + +#ifndef _ASM_IA64_SN_SN2_SHUB_MMR_T_H +#define _ASM_IA64_SN_SN2_SHUB_MMR_T_H + +#include <asm/sn/arch.h> + +/* ==================================================================== */ +/* Register "SH_FSB_BINIT_CONTROL" */ +/* FSB BINIT# Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_fsb_binit_control_u { + mmr_t sh_fsb_binit_control_regval; + struct { + mmr_t binit : 1; + mmr_t reserved_0 : 63; + } sh_fsb_binit_control_s; +} sh_fsb_binit_control_u_t; +#else +typedef union sh_fsb_binit_control_u { + mmr_t sh_fsb_binit_control_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t binit : 1; + } sh_fsb_binit_control_s; +} sh_fsb_binit_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_FSB_RESET_CONTROL" */ +/* FSB Reset Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_fsb_reset_control_u { + mmr_t sh_fsb_reset_control_regval; + struct { + mmr_t reset : 1; + mmr_t reserved_0 : 63; + } sh_fsb_reset_control_s; +} sh_fsb_reset_control_u_t; +#else +typedef union sh_fsb_reset_control_u { + mmr_t sh_fsb_reset_control_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t reset : 1; + } sh_fsb_reset_control_s; +} sh_fsb_reset_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_FSB_SYSTEM_AGENT_CONFIG" */ +/* FSB System Agent Configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_fsb_system_agent_config_u { + mmr_t sh_fsb_system_agent_config_regval; + struct { + mmr_t rcnt_scnt_en : 1; + mmr_t reserved_0 : 2; + mmr_t berr_assert_en : 1; + mmr_t berr_sampling_en : 1; + mmr_t binit_assert_en : 1; + mmr_t bnr_throttling_en : 1; + mmr_t short_hang_en : 1; + mmr_t inta_rsp_data : 8; + mmr_t io_trans_rsp : 1; + mmr_t xtpr_trans_rsp : 1; + mmr_t inta_trans_rsp : 1; + mmr_t reserved_1 : 4; + mmr_t tdot : 1; + mmr_t serialize_fsb_en : 1; + mmr_t reserved_2 : 7; + mmr_t binit_event_enables : 14; + mmr_t reserved_3 : 18; + } sh_fsb_system_agent_config_s; +} sh_fsb_system_agent_config_u_t; +#else +typedef union sh_fsb_system_agent_config_u { + mmr_t sh_fsb_system_agent_config_regval; + struct { + mmr_t reserved_3 : 18; + mmr_t binit_event_enables : 14; + mmr_t reserved_2 : 7; + mmr_t serialize_fsb_en : 1; + mmr_t tdot : 1; + mmr_t reserved_1 : 4; + mmr_t inta_trans_rsp : 1; + mmr_t xtpr_trans_rsp : 1; + mmr_t io_trans_rsp : 1; + mmr_t inta_rsp_data : 8; + mmr_t short_hang_en : 1; + mmr_t bnr_throttling_en : 1; + mmr_t binit_assert_en : 1; + mmr_t berr_sampling_en : 1; + mmr_t berr_assert_en : 1; + mmr_t reserved_0 : 2; + mmr_t rcnt_scnt_en : 1; + } sh_fsb_system_agent_config_s; +} sh_fsb_system_agent_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_FSB_VGA_REMAP" */ +/* FSB VGA Address Space Remap */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_fsb_vga_remap_u { + mmr_t sh_fsb_vga_remap_regval; + struct { + mmr_t reserved_0 : 17; + mmr_t offset : 19; + mmr_t asid : 2; + mmr_t nid : 11; + mmr_t reserved_1 : 13; + mmr_t vga_remapping_enabled : 1; + mmr_t reserved_2 : 1; + } sh_fsb_vga_remap_s; +} sh_fsb_vga_remap_u_t; +#else +typedef union sh_fsb_vga_remap_u { + mmr_t sh_fsb_vga_remap_regval; + struct { + mmr_t reserved_2 : 1; + mmr_t vga_remapping_enabled : 1; + mmr_t reserved_1 : 13; + mmr_t nid : 11; + mmr_t asid : 2; + mmr_t offset : 19; + mmr_t reserved_0 : 17; + } sh_fsb_vga_remap_s; +} sh_fsb_vga_remap_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_FSB_RESET_STATUS" */ +/* FSB Reset Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_fsb_reset_status_u { + mmr_t sh_fsb_reset_status_regval; + struct { + mmr_t reset_in_progress : 1; + mmr_t reserved_0 : 63; + } sh_fsb_reset_status_s; +} sh_fsb_reset_status_u_t; +#else +typedef union sh_fsb_reset_status_u { + mmr_t sh_fsb_reset_status_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t reset_in_progress : 1; + } sh_fsb_reset_status_s; +} sh_fsb_reset_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_FSB_SYMMETRIC_AGENT_STATUS" */ +/* FSB Symmetric Agent Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_fsb_symmetric_agent_status_u { + mmr_t sh_fsb_symmetric_agent_status_regval; + struct { + mmr_t cpu_0_active : 1; + mmr_t cpu_1_active : 1; + mmr_t cpus_ready : 1; + mmr_t reserved_0 : 61; + } sh_fsb_symmetric_agent_status_s; +} sh_fsb_symmetric_agent_status_u_t; +#else +typedef union sh_fsb_symmetric_agent_status_u { + mmr_t sh_fsb_symmetric_agent_status_regval; + struct { + mmr_t reserved_0 : 61; + mmr_t cpus_ready : 1; + mmr_t cpu_1_active : 1; + mmr_t cpu_0_active : 1; + } sh_fsb_symmetric_agent_status_s; +} sh_fsb_symmetric_agent_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_CREDIT_COUNT_0" */ +/* Graphics-write Credit Count for CPU 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_credit_count_0_u { + mmr_t sh_gfx_credit_count_0_regval; + struct { + mmr_t count : 20; + mmr_t reserved_0 : 43; + mmr_t reset_gfx_state : 1; + } sh_gfx_credit_count_0_s; +} sh_gfx_credit_count_0_u_t; +#else +typedef union sh_gfx_credit_count_0_u { + mmr_t sh_gfx_credit_count_0_regval; + struct { + mmr_t reset_gfx_state : 1; + mmr_t reserved_0 : 43; + mmr_t count : 20; + } sh_gfx_credit_count_0_s; +} sh_gfx_credit_count_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_CREDIT_COUNT_1" */ +/* Graphics-write Credit Count for CPU 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_credit_count_1_u { + mmr_t sh_gfx_credit_count_1_regval; + struct { + mmr_t count : 20; + mmr_t reserved_0 : 43; + mmr_t reset_gfx_state : 1; + } sh_gfx_credit_count_1_s; +} sh_gfx_credit_count_1_u_t; +#else +typedef union sh_gfx_credit_count_1_u { + mmr_t sh_gfx_credit_count_1_regval; + struct { + mmr_t reset_gfx_state : 1; + mmr_t reserved_0 : 43; + mmr_t count : 20; + } sh_gfx_credit_count_1_s; +} sh_gfx_credit_count_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_MODE_CNTRL_0" */ +/* Graphics credit mode amd message ordering for CPU 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_mode_cntrl_0_u { + mmr_t sh_gfx_mode_cntrl_0_regval; + struct { + mmr_t dword_credits : 1; + mmr_t mixed_mode_credits : 1; + mmr_t relaxed_ordering : 1; + mmr_t reserved_0 : 61; + } sh_gfx_mode_cntrl_0_s; +} sh_gfx_mode_cntrl_0_u_t; +#else +typedef union sh_gfx_mode_cntrl_0_u { + mmr_t sh_gfx_mode_cntrl_0_regval; + struct { + mmr_t reserved_0 : 61; + mmr_t relaxed_ordering : 1; + mmr_t mixed_mode_credits : 1; + mmr_t dword_credits : 1; + } sh_gfx_mode_cntrl_0_s; +} sh_gfx_mode_cntrl_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_MODE_CNTRL_1" */ +/* Graphics credit mode amd message ordering for CPU 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_mode_cntrl_1_u { + mmr_t sh_gfx_mode_cntrl_1_regval; + struct { + mmr_t dword_credits : 1; + mmr_t mixed_mode_credits : 1; + mmr_t relaxed_ordering : 1; + mmr_t reserved_0 : 61; + } sh_gfx_mode_cntrl_1_s; +} sh_gfx_mode_cntrl_1_u_t; +#else +typedef union sh_gfx_mode_cntrl_1_u { + mmr_t sh_gfx_mode_cntrl_1_regval; + struct { + mmr_t reserved_0 : 61; + mmr_t relaxed_ordering : 1; + mmr_t mixed_mode_credits : 1; + mmr_t dword_credits : 1; + } sh_gfx_mode_cntrl_1_s; +} sh_gfx_mode_cntrl_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_SKID_CREDIT_COUNT_0" */ +/* Graphics-write Skid Credit Count for CPU 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_skid_credit_count_0_u { + mmr_t sh_gfx_skid_credit_count_0_regval; + struct { + mmr_t skid : 20; + mmr_t reserved_0 : 44; + } sh_gfx_skid_credit_count_0_s; +} sh_gfx_skid_credit_count_0_u_t; +#else +typedef union sh_gfx_skid_credit_count_0_u { + mmr_t sh_gfx_skid_credit_count_0_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t skid : 20; + } sh_gfx_skid_credit_count_0_s; +} sh_gfx_skid_credit_count_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_SKID_CREDIT_COUNT_1" */ +/* Graphics-write Skid Credit Count for CPU 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_skid_credit_count_1_u { + mmr_t sh_gfx_skid_credit_count_1_regval; + struct { + mmr_t skid : 20; + mmr_t reserved_0 : 44; + } sh_gfx_skid_credit_count_1_s; +} sh_gfx_skid_credit_count_1_u_t; +#else +typedef union sh_gfx_skid_credit_count_1_u { + mmr_t sh_gfx_skid_credit_count_1_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t skid : 20; + } sh_gfx_skid_credit_count_1_s; +} sh_gfx_skid_credit_count_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_STALL_LIMIT_0" */ +/* Graphics-write Stall Limit for CPU 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_stall_limit_0_u { + mmr_t sh_gfx_stall_limit_0_regval; + struct { + mmr_t limit : 26; + mmr_t reserved_0 : 38; + } sh_gfx_stall_limit_0_s; +} sh_gfx_stall_limit_0_u_t; +#else +typedef union sh_gfx_stall_limit_0_u { + mmr_t sh_gfx_stall_limit_0_regval; + struct { + mmr_t reserved_0 : 38; + mmr_t limit : 26; + } sh_gfx_stall_limit_0_s; +} sh_gfx_stall_limit_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_STALL_LIMIT_1" */ +/* Graphics-write Stall Limit for CPU 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_stall_limit_1_u { + mmr_t sh_gfx_stall_limit_1_regval; + struct { + mmr_t limit : 26; + mmr_t reserved_0 : 38; + } sh_gfx_stall_limit_1_s; +} sh_gfx_stall_limit_1_u_t; +#else +typedef union sh_gfx_stall_limit_1_u { + mmr_t sh_gfx_stall_limit_1_regval; + struct { + mmr_t reserved_0 : 38; + mmr_t limit : 26; + } sh_gfx_stall_limit_1_s; +} sh_gfx_stall_limit_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_STALL_TIMER_0" */ +/* Graphics-write Stall Timer for CPU 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_stall_timer_0_u { + mmr_t sh_gfx_stall_timer_0_regval; + struct { + mmr_t timer_value : 26; + mmr_t reserved_0 : 38; + } sh_gfx_stall_timer_0_s; +} sh_gfx_stall_timer_0_u_t; +#else +typedef union sh_gfx_stall_timer_0_u { + mmr_t sh_gfx_stall_timer_0_regval; + struct { + mmr_t reserved_0 : 38; + mmr_t timer_value : 26; + } sh_gfx_stall_timer_0_s; +} sh_gfx_stall_timer_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_STALL_TIMER_1" */ +/* Graphics-write Stall Timer for CPU 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_stall_timer_1_u { + mmr_t sh_gfx_stall_timer_1_regval; + struct { + mmr_t timer_value : 26; + mmr_t reserved_0 : 38; + } sh_gfx_stall_timer_1_s; +} sh_gfx_stall_timer_1_u_t; +#else +typedef union sh_gfx_stall_timer_1_u { + mmr_t sh_gfx_stall_timer_1_regval; + struct { + mmr_t reserved_0 : 38; + mmr_t timer_value : 26; + } sh_gfx_stall_timer_1_s; +} sh_gfx_stall_timer_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_WINDOW_0" */ +/* Graphics-write Window for CPU 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_window_0_u { + mmr_t sh_gfx_window_0_regval; + struct { + mmr_t reserved_0 : 24; + mmr_t base_addr : 12; + mmr_t reserved_1 : 27; + mmr_t gfx_window_en : 1; + } sh_gfx_window_0_s; +} sh_gfx_window_0_u_t; +#else +typedef union sh_gfx_window_0_u { + mmr_t sh_gfx_window_0_regval; + struct { + mmr_t gfx_window_en : 1; + mmr_t reserved_1 : 27; + mmr_t base_addr : 12; + mmr_t reserved_0 : 24; + } sh_gfx_window_0_s; +} sh_gfx_window_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_WINDOW_1" */ +/* Graphics-write Window for CPU 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_window_1_u { + mmr_t sh_gfx_window_1_regval; + struct { + mmr_t reserved_0 : 24; + mmr_t base_addr : 12; + mmr_t reserved_1 : 27; + mmr_t gfx_window_en : 1; + } sh_gfx_window_1_s; +} sh_gfx_window_1_u_t; +#else +typedef union sh_gfx_window_1_u { + mmr_t sh_gfx_window_1_regval; + struct { + mmr_t gfx_window_en : 1; + mmr_t reserved_1 : 27; + mmr_t base_addr : 12; + mmr_t reserved_0 : 24; + } sh_gfx_window_1_s; +} sh_gfx_window_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0" */ +/* Graphics-write Interrupt Limit for CPU 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_interrupt_timer_limit_0_u { + mmr_t sh_gfx_interrupt_timer_limit_0_regval; + struct { + mmr_t interrupt_timer_limit : 8; + mmr_t reserved_0 : 56; + } sh_gfx_interrupt_timer_limit_0_s; +} sh_gfx_interrupt_timer_limit_0_u_t; +#else +typedef union sh_gfx_interrupt_timer_limit_0_u { + mmr_t sh_gfx_interrupt_timer_limit_0_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t interrupt_timer_limit : 8; + } sh_gfx_interrupt_timer_limit_0_s; +} sh_gfx_interrupt_timer_limit_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1" */ +/* Graphics-write Interrupt Limit for CPU 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_interrupt_timer_limit_1_u { + mmr_t sh_gfx_interrupt_timer_limit_1_regval; + struct { + mmr_t interrupt_timer_limit : 8; + mmr_t reserved_0 : 56; + } sh_gfx_interrupt_timer_limit_1_s; +} sh_gfx_interrupt_timer_limit_1_u_t; +#else +typedef union sh_gfx_interrupt_timer_limit_1_u { + mmr_t sh_gfx_interrupt_timer_limit_1_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t interrupt_timer_limit : 8; + } sh_gfx_interrupt_timer_limit_1_s; +} sh_gfx_interrupt_timer_limit_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_WRITE_STATUS_0" */ +/* Graphics Write Status for CPU 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_write_status_0_u { + mmr_t sh_gfx_write_status_0_regval; + struct { + mmr_t busy : 1; + mmr_t reserved_0 : 62; + mmr_t re_enable_gfx_stall : 1; + } sh_gfx_write_status_0_s; +} sh_gfx_write_status_0_u_t; +#else +typedef union sh_gfx_write_status_0_u { + mmr_t sh_gfx_write_status_0_regval; + struct { + mmr_t re_enable_gfx_stall : 1; + mmr_t reserved_0 : 62; + mmr_t busy : 1; + } sh_gfx_write_status_0_s; +} sh_gfx_write_status_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GFX_WRITE_STATUS_1" */ +/* Graphics Write Status for CPU 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gfx_write_status_1_u { + mmr_t sh_gfx_write_status_1_regval; + struct { + mmr_t busy : 1; + mmr_t reserved_0 : 62; + mmr_t re_enable_gfx_stall : 1; + } sh_gfx_write_status_1_s; +} sh_gfx_write_status_1_u_t; +#else +typedef union sh_gfx_write_status_1_u { + mmr_t sh_gfx_write_status_1_regval; + struct { + mmr_t re_enable_gfx_stall : 1; + mmr_t reserved_0 : 62; + mmr_t busy : 1; + } sh_gfx_write_status_1_s; +} sh_gfx_write_status_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_II_INT0" */ +/* SHub II Interrupt 0 Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ii_int0_u { + mmr_t sh_ii_int0_regval; + struct { + mmr_t idx : 8; + mmr_t send : 1; + mmr_t reserved_0 : 55; + } sh_ii_int0_s; +} sh_ii_int0_u_t; +#else +typedef union sh_ii_int0_u { + mmr_t sh_ii_int0_regval; + struct { + mmr_t reserved_0 : 55; + mmr_t send : 1; + mmr_t idx : 8; + } sh_ii_int0_s; +} sh_ii_int0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_II_INT0_CONFIG" */ +/* SHub II Interrupt 0 Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ii_int0_config_u { + mmr_t sh_ii_int0_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 14; + } sh_ii_int0_config_s; +} sh_ii_int0_config_u_t; +#else +typedef union sh_ii_int0_config_u { + mmr_t sh_ii_int0_config_regval; + struct { + mmr_t reserved_1 : 14; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_ii_int0_config_s; +} sh_ii_int0_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_II_INT0_ENABLE" */ +/* SHub II Interrupt 0 Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ii_int0_enable_u { + mmr_t sh_ii_int0_enable_regval; + struct { + mmr_t ii_enable : 1; + mmr_t reserved_0 : 63; + } sh_ii_int0_enable_s; +} sh_ii_int0_enable_u_t; +#else +typedef union sh_ii_int0_enable_u { + mmr_t sh_ii_int0_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t ii_enable : 1; + } sh_ii_int0_enable_s; +} sh_ii_int0_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_II_INT1" */ +/* SHub II Interrupt 1 Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ii_int1_u { + mmr_t sh_ii_int1_regval; + struct { + mmr_t idx : 8; + mmr_t send : 1; + mmr_t reserved_0 : 55; + } sh_ii_int1_s; +} sh_ii_int1_u_t; +#else +typedef union sh_ii_int1_u { + mmr_t sh_ii_int1_regval; + struct { + mmr_t reserved_0 : 55; + mmr_t send : 1; + mmr_t idx : 8; + } sh_ii_int1_s; +} sh_ii_int1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_II_INT1_CONFIG" */ +/* SHub II Interrupt 1 Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ii_int1_config_u { + mmr_t sh_ii_int1_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 14; + } sh_ii_int1_config_s; +} sh_ii_int1_config_u_t; +#else +typedef union sh_ii_int1_config_u { + mmr_t sh_ii_int1_config_regval; + struct { + mmr_t reserved_1 : 14; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_ii_int1_config_s; +} sh_ii_int1_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_II_INT1_ENABLE" */ +/* SHub II Interrupt 1 Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ii_int1_enable_u { + mmr_t sh_ii_int1_enable_regval; + struct { + mmr_t ii_enable : 1; + mmr_t reserved_0 : 63; + } sh_ii_int1_enable_s; +} sh_ii_int1_enable_u_t; +#else +typedef union sh_ii_int1_enable_u { + mmr_t sh_ii_int1_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t ii_enable : 1; + } sh_ii_int1_enable_s; +} sh_ii_int1_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_INT_NODE_ID_CONFIG" */ +/* SHub Interrupt Node ID Configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_int_node_id_config_u { + mmr_t sh_int_node_id_config_regval; + struct { + mmr_t node_id : 11; + mmr_t id_sel : 1; + mmr_t reserved_0 : 52; + } sh_int_node_id_config_s; +} sh_int_node_id_config_u_t; +#else +typedef union sh_int_node_id_config_u { + mmr_t sh_int_node_id_config_regval; + struct { + mmr_t reserved_0 : 52; + mmr_t id_sel : 1; + mmr_t node_id : 11; + } sh_int_node_id_config_s; +} sh_int_node_id_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_IPI_INT" */ +/* SHub Inter-Processor Interrupt Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ipi_int_u { + mmr_t sh_ipi_int_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 3; + mmr_t send : 1; + } sh_ipi_int_s; +} sh_ipi_int_u_t; +#else +typedef union sh_ipi_int_u { + mmr_t sh_ipi_int_regval; + struct { + mmr_t send : 1; + mmr_t reserved_2 : 3; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_ipi_int_s; +} sh_ipi_int_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_IPI_INT_ENABLE" */ +/* SHub Inter-Processor Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ipi_int_enable_u { + mmr_t sh_ipi_int_enable_regval; + struct { + mmr_t pio_enable : 1; + mmr_t reserved_0 : 63; + } sh_ipi_int_enable_s; +} sh_ipi_int_enable_u_t; +#else +typedef union sh_ipi_int_enable_u { + mmr_t sh_ipi_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t pio_enable : 1; + } sh_ipi_int_enable_s; +} sh_ipi_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT0_CONFIG" */ +/* SHub Local Interrupt 0 Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int0_config_u { + mmr_t sh_local_int0_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_local_int0_config_s; +} sh_local_int0_config_u_t; +#else +typedef union sh_local_int0_config_u { + mmr_t sh_local_int0_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_local_int0_config_s; +} sh_local_int0_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT0_ENABLE" */ +/* SHub Local Interrupt 0 Enable */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int0_enable_u { + mmr_t sh_local_int0_enable_regval; + struct { + mmr_t pi_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t ii_hw_int : 1; + mmr_t pi_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t xn_uce_int : 1; + mmr_t reserved_0 : 1; + mmr_t system_shutdown_int : 1; + mmr_t uart_int : 1; + mmr_t l1_nmi_int : 1; + mmr_t stop_clock : 1; + mmr_t reserved_1 : 48; + } sh_local_int0_enable_s; +} sh_local_int0_enable_u_t; +#else +typedef union sh_local_int0_enable_u { + mmr_t sh_local_int0_enable_regval; + struct { + mmr_t reserved_1 : 48; + mmr_t stop_clock : 1; + mmr_t l1_nmi_int : 1; + mmr_t uart_int : 1; + mmr_t system_shutdown_int : 1; + mmr_t reserved_0 : 1; + mmr_t xn_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t pi_ce_int : 1; + mmr_t ii_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t pi_hw_int : 1; + } sh_local_int0_enable_s; +} sh_local_int0_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT1_CONFIG" */ +/* SHub Local Interrupt 1 Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int1_config_u { + mmr_t sh_local_int1_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_local_int1_config_s; +} sh_local_int1_config_u_t; +#else +typedef union sh_local_int1_config_u { + mmr_t sh_local_int1_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_local_int1_config_s; +} sh_local_int1_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT1_ENABLE" */ +/* SHub Local Interrupt 1 Enable */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int1_enable_u { + mmr_t sh_local_int1_enable_regval; + struct { + mmr_t pi_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t ii_hw_int : 1; + mmr_t pi_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t xn_uce_int : 1; + mmr_t reserved_0 : 1; + mmr_t system_shutdown_int : 1; + mmr_t uart_int : 1; + mmr_t l1_nmi_int : 1; + mmr_t stop_clock : 1; + mmr_t reserved_1 : 48; + } sh_local_int1_enable_s; +} sh_local_int1_enable_u_t; +#else +typedef union sh_local_int1_enable_u { + mmr_t sh_local_int1_enable_regval; + struct { + mmr_t reserved_1 : 48; + mmr_t stop_clock : 1; + mmr_t l1_nmi_int : 1; + mmr_t uart_int : 1; + mmr_t system_shutdown_int : 1; + mmr_t reserved_0 : 1; + mmr_t xn_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t pi_ce_int : 1; + mmr_t ii_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t pi_hw_int : 1; + } sh_local_int1_enable_s; +} sh_local_int1_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT2_CONFIG" */ +/* SHub Local Interrupt 2 Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int2_config_u { + mmr_t sh_local_int2_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_local_int2_config_s; +} sh_local_int2_config_u_t; +#else +typedef union sh_local_int2_config_u { + mmr_t sh_local_int2_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_local_int2_config_s; +} sh_local_int2_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT2_ENABLE" */ +/* SHub Local Interrupt 2 Enable */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int2_enable_u { + mmr_t sh_local_int2_enable_regval; + struct { + mmr_t pi_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t ii_hw_int : 1; + mmr_t pi_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t xn_uce_int : 1; + mmr_t reserved_0 : 1; + mmr_t system_shutdown_int : 1; + mmr_t uart_int : 1; + mmr_t l1_nmi_int : 1; + mmr_t stop_clock : 1; + mmr_t reserved_1 : 48; + } sh_local_int2_enable_s; +} sh_local_int2_enable_u_t; +#else +typedef union sh_local_int2_enable_u { + mmr_t sh_local_int2_enable_regval; + struct { + mmr_t reserved_1 : 48; + mmr_t stop_clock : 1; + mmr_t l1_nmi_int : 1; + mmr_t uart_int : 1; + mmr_t system_shutdown_int : 1; + mmr_t reserved_0 : 1; + mmr_t xn_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t pi_ce_int : 1; + mmr_t ii_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t pi_hw_int : 1; + } sh_local_int2_enable_s; +} sh_local_int2_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT3_CONFIG" */ +/* SHub Local Interrupt 3 Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int3_config_u { + mmr_t sh_local_int3_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_local_int3_config_s; +} sh_local_int3_config_u_t; +#else +typedef union sh_local_int3_config_u { + mmr_t sh_local_int3_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_local_int3_config_s; +} sh_local_int3_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT3_ENABLE" */ +/* SHub Local Interrupt 3 Enable */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int3_enable_u { + mmr_t sh_local_int3_enable_regval; + struct { + mmr_t pi_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t ii_hw_int : 1; + mmr_t pi_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t xn_uce_int : 1; + mmr_t reserved_0 : 1; + mmr_t system_shutdown_int : 1; + mmr_t uart_int : 1; + mmr_t l1_nmi_int : 1; + mmr_t stop_clock : 1; + mmr_t reserved_1 : 48; + } sh_local_int3_enable_s; +} sh_local_int3_enable_u_t; +#else +typedef union sh_local_int3_enable_u { + mmr_t sh_local_int3_enable_regval; + struct { + mmr_t reserved_1 : 48; + mmr_t stop_clock : 1; + mmr_t l1_nmi_int : 1; + mmr_t uart_int : 1; + mmr_t system_shutdown_int : 1; + mmr_t reserved_0 : 1; + mmr_t xn_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t pi_ce_int : 1; + mmr_t ii_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t pi_hw_int : 1; + } sh_local_int3_enable_s; +} sh_local_int3_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT4_CONFIG" */ +/* SHub Local Interrupt 4 Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int4_config_u { + mmr_t sh_local_int4_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_local_int4_config_s; +} sh_local_int4_config_u_t; +#else +typedef union sh_local_int4_config_u { + mmr_t sh_local_int4_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_local_int4_config_s; +} sh_local_int4_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT4_ENABLE" */ +/* SHub Local Interrupt 4 Enable */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int4_enable_u { + mmr_t sh_local_int4_enable_regval; + struct { + mmr_t pi_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t ii_hw_int : 1; + mmr_t pi_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t xn_uce_int : 1; + mmr_t reserved_0 : 1; + mmr_t system_shutdown_int : 1; + mmr_t uart_int : 1; + mmr_t l1_nmi_int : 1; + mmr_t stop_clock : 1; + mmr_t reserved_1 : 48; + } sh_local_int4_enable_s; +} sh_local_int4_enable_u_t; +#else +typedef union sh_local_int4_enable_u { + mmr_t sh_local_int4_enable_regval; + struct { + mmr_t reserved_1 : 48; + mmr_t stop_clock : 1; + mmr_t l1_nmi_int : 1; + mmr_t uart_int : 1; + mmr_t system_shutdown_int : 1; + mmr_t reserved_0 : 1; + mmr_t xn_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t pi_ce_int : 1; + mmr_t ii_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t pi_hw_int : 1; + } sh_local_int4_enable_s; +} sh_local_int4_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT5_CONFIG" */ +/* SHub Local Interrupt 5 Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int5_config_u { + mmr_t sh_local_int5_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_local_int5_config_s; +} sh_local_int5_config_u_t; +#else +typedef union sh_local_int5_config_u { + mmr_t sh_local_int5_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_local_int5_config_s; +} sh_local_int5_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LOCAL_INT5_ENABLE" */ +/* SHub Local Interrupt 5 Enable */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_local_int5_enable_u { + mmr_t sh_local_int5_enable_regval; + struct { + mmr_t pi_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t ii_hw_int : 1; + mmr_t pi_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t xn_uce_int : 1; + mmr_t reserved_0 : 1; + mmr_t system_shutdown_int : 1; + mmr_t uart_int : 1; + mmr_t l1_nmi_int : 1; + mmr_t stop_clock : 1; + mmr_t reserved_1 : 48; + } sh_local_int5_enable_s; +} sh_local_int5_enable_u_t; +#else +typedef union sh_local_int5_enable_u { + mmr_t sh_local_int5_enable_regval; + struct { + mmr_t reserved_1 : 48; + mmr_t stop_clock : 1; + mmr_t l1_nmi_int : 1; + mmr_t uart_int : 1; + mmr_t system_shutdown_int : 1; + mmr_t reserved_0 : 1; + mmr_t xn_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t pi_ce_int : 1; + mmr_t ii_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t pi_hw_int : 1; + } sh_local_int5_enable_s; +} sh_local_int5_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC0_ERR_INT_CONFIG" */ +/* SHub Processor 0 Error Interrupt Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc0_err_int_config_u { + mmr_t sh_proc0_err_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_proc0_err_int_config_s; +} sh_proc0_err_int_config_u_t; +#else +typedef union sh_proc0_err_int_config_u { + mmr_t sh_proc0_err_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_proc0_err_int_config_s; +} sh_proc0_err_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC1_ERR_INT_CONFIG" */ +/* SHub Processor 1 Error Interrupt Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc1_err_int_config_u { + mmr_t sh_proc1_err_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_proc1_err_int_config_s; +} sh_proc1_err_int_config_u_t; +#else +typedef union sh_proc1_err_int_config_u { + mmr_t sh_proc1_err_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_proc1_err_int_config_s; +} sh_proc1_err_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC2_ERR_INT_CONFIG" */ +/* SHub Processor 2 Error Interrupt Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc2_err_int_config_u { + mmr_t sh_proc2_err_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_proc2_err_int_config_s; +} sh_proc2_err_int_config_u_t; +#else +typedef union sh_proc2_err_int_config_u { + mmr_t sh_proc2_err_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_proc2_err_int_config_s; +} sh_proc2_err_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC3_ERR_INT_CONFIG" */ +/* SHub Processor 3 Error Interrupt Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc3_err_int_config_u { + mmr_t sh_proc3_err_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_proc3_err_int_config_s; +} sh_proc3_err_int_config_u_t; +#else +typedef union sh_proc3_err_int_config_u { + mmr_t sh_proc3_err_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_proc3_err_int_config_s; +} sh_proc3_err_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC0_ADV_INT_CONFIG" */ +/* SHub Processor 0 Advisory Interrupt Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc0_adv_int_config_u { + mmr_t sh_proc0_adv_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_proc0_adv_int_config_s; +} sh_proc0_adv_int_config_u_t; +#else +typedef union sh_proc0_adv_int_config_u { + mmr_t sh_proc0_adv_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_proc0_adv_int_config_s; +} sh_proc0_adv_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC1_ADV_INT_CONFIG" */ +/* SHub Processor 1 Advisory Interrupt Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc1_adv_int_config_u { + mmr_t sh_proc1_adv_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_proc1_adv_int_config_s; +} sh_proc1_adv_int_config_u_t; +#else +typedef union sh_proc1_adv_int_config_u { + mmr_t sh_proc1_adv_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_proc1_adv_int_config_s; +} sh_proc1_adv_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC2_ADV_INT_CONFIG" */ +/* SHub Processor 2 Advisory Interrupt Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc2_adv_int_config_u { + mmr_t sh_proc2_adv_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_proc2_adv_int_config_s; +} sh_proc2_adv_int_config_u_t; +#else +typedef union sh_proc2_adv_int_config_u { + mmr_t sh_proc2_adv_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_proc2_adv_int_config_s; +} sh_proc2_adv_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC3_ADV_INT_CONFIG" */ +/* SHub Processor 3 Advisory Interrupt Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc3_adv_int_config_u { + mmr_t sh_proc3_adv_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_proc3_adv_int_config_s; +} sh_proc3_adv_int_config_u_t; +#else +typedef union sh_proc3_adv_int_config_u { + mmr_t sh_proc3_adv_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_proc3_adv_int_config_s; +} sh_proc3_adv_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC0_ERR_INT_ENABLE" */ +/* SHub Processor 0 Error Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc0_err_int_enable_u { + mmr_t sh_proc0_err_int_enable_regval; + struct { + mmr_t proc0_err_enable : 1; + mmr_t reserved_0 : 63; + } sh_proc0_err_int_enable_s; +} sh_proc0_err_int_enable_u_t; +#else +typedef union sh_proc0_err_int_enable_u { + mmr_t sh_proc0_err_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t proc0_err_enable : 1; + } sh_proc0_err_int_enable_s; +} sh_proc0_err_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC1_ERR_INT_ENABLE" */ +/* SHub Processor 1 Error Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc1_err_int_enable_u { + mmr_t sh_proc1_err_int_enable_regval; + struct { + mmr_t proc1_err_enable : 1; + mmr_t reserved_0 : 63; + } sh_proc1_err_int_enable_s; +} sh_proc1_err_int_enable_u_t; +#else +typedef union sh_proc1_err_int_enable_u { + mmr_t sh_proc1_err_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t proc1_err_enable : 1; + } sh_proc1_err_int_enable_s; +} sh_proc1_err_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC2_ERR_INT_ENABLE" */ +/* SHub Processor 2 Error Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc2_err_int_enable_u { + mmr_t sh_proc2_err_int_enable_regval; + struct { + mmr_t proc2_err_enable : 1; + mmr_t reserved_0 : 63; + } sh_proc2_err_int_enable_s; +} sh_proc2_err_int_enable_u_t; +#else +typedef union sh_proc2_err_int_enable_u { + mmr_t sh_proc2_err_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t proc2_err_enable : 1; + } sh_proc2_err_int_enable_s; +} sh_proc2_err_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC3_ERR_INT_ENABLE" */ +/* SHub Processor 3 Error Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc3_err_int_enable_u { + mmr_t sh_proc3_err_int_enable_regval; + struct { + mmr_t proc3_err_enable : 1; + mmr_t reserved_0 : 63; + } sh_proc3_err_int_enable_s; +} sh_proc3_err_int_enable_u_t; +#else +typedef union sh_proc3_err_int_enable_u { + mmr_t sh_proc3_err_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t proc3_err_enable : 1; + } sh_proc3_err_int_enable_s; +} sh_proc3_err_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC0_ADV_INT_ENABLE" */ +/* SHub Processor 0 Advisory Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc0_adv_int_enable_u { + mmr_t sh_proc0_adv_int_enable_regval; + struct { + mmr_t proc0_adv_enable : 1; + mmr_t reserved_0 : 63; + } sh_proc0_adv_int_enable_s; +} sh_proc0_adv_int_enable_u_t; +#else +typedef union sh_proc0_adv_int_enable_u { + mmr_t sh_proc0_adv_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t proc0_adv_enable : 1; + } sh_proc0_adv_int_enable_s; +} sh_proc0_adv_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC1_ADV_INT_ENABLE" */ +/* SHub Processor 1 Advisory Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc1_adv_int_enable_u { + mmr_t sh_proc1_adv_int_enable_regval; + struct { + mmr_t proc1_adv_enable : 1; + mmr_t reserved_0 : 63; + } sh_proc1_adv_int_enable_s; +} sh_proc1_adv_int_enable_u_t; +#else +typedef union sh_proc1_adv_int_enable_u { + mmr_t sh_proc1_adv_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t proc1_adv_enable : 1; + } sh_proc1_adv_int_enable_s; +} sh_proc1_adv_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC2_ADV_INT_ENABLE" */ +/* SHub Processor 2 Advisory Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc2_adv_int_enable_u { + mmr_t sh_proc2_adv_int_enable_regval; + struct { + mmr_t proc2_adv_enable : 1; + mmr_t reserved_0 : 63; + } sh_proc2_adv_int_enable_s; +} sh_proc2_adv_int_enable_u_t; +#else +typedef union sh_proc2_adv_int_enable_u { + mmr_t sh_proc2_adv_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t proc2_adv_enable : 1; + } sh_proc2_adv_int_enable_s; +} sh_proc2_adv_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC3_ADV_INT_ENABLE" */ +/* SHub Processor 3 Advisory Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc3_adv_int_enable_u { + mmr_t sh_proc3_adv_int_enable_regval; + struct { + mmr_t proc3_adv_enable : 1; + mmr_t reserved_0 : 63; + } sh_proc3_adv_int_enable_s; +} sh_proc3_adv_int_enable_u_t; +#else +typedef union sh_proc3_adv_int_enable_u { + mmr_t sh_proc3_adv_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t proc3_adv_enable : 1; + } sh_proc3_adv_int_enable_s; +} sh_proc3_adv_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROFILE_INT_CONFIG" */ +/* SHub Profile Interrupt Configuration Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_profile_int_config_u { + mmr_t sh_profile_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_profile_int_config_s; +} sh_profile_int_config_u_t; +#else +typedef union sh_profile_int_config_u { + mmr_t sh_profile_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_profile_int_config_s; +} sh_profile_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROFILE_INT_ENABLE" */ +/* SHub Profile Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_profile_int_enable_u { + mmr_t sh_profile_int_enable_regval; + struct { + mmr_t profile_enable : 1; + mmr_t reserved_0 : 63; + } sh_profile_int_enable_s; +} sh_profile_int_enable_u_t; +#else +typedef union sh_profile_int_enable_u { + mmr_t sh_profile_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t profile_enable : 1; + } sh_profile_int_enable_s; +} sh_profile_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_RTC0_INT_CONFIG" */ +/* SHub RTC 0 Interrupt Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_rtc0_int_config_u { + mmr_t sh_rtc0_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_rtc0_int_config_s; +} sh_rtc0_int_config_u_t; +#else +typedef union sh_rtc0_int_config_u { + mmr_t sh_rtc0_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_rtc0_int_config_s; +} sh_rtc0_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_RTC0_INT_ENABLE" */ +/* SHub RTC 0 Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_rtc0_int_enable_u { + mmr_t sh_rtc0_int_enable_regval; + struct { + mmr_t rtc0_enable : 1; + mmr_t reserved_0 : 63; + } sh_rtc0_int_enable_s; +} sh_rtc0_int_enable_u_t; +#else +typedef union sh_rtc0_int_enable_u { + mmr_t sh_rtc0_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t rtc0_enable : 1; + } sh_rtc0_int_enable_s; +} sh_rtc0_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_RTC1_INT_CONFIG" */ +/* SHub RTC 1 Interrupt Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_rtc1_int_config_u { + mmr_t sh_rtc1_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_rtc1_int_config_s; +} sh_rtc1_int_config_u_t; +#else +typedef union sh_rtc1_int_config_u { + mmr_t sh_rtc1_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_rtc1_int_config_s; +} sh_rtc1_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_RTC1_INT_ENABLE" */ +/* SHub RTC 1 Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_rtc1_int_enable_u { + mmr_t sh_rtc1_int_enable_regval; + struct { + mmr_t rtc1_enable : 1; + mmr_t reserved_0 : 63; + } sh_rtc1_int_enable_s; +} sh_rtc1_int_enable_u_t; +#else +typedef union sh_rtc1_int_enable_u { + mmr_t sh_rtc1_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t rtc1_enable : 1; + } sh_rtc1_int_enable_s; +} sh_rtc1_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_RTC2_INT_CONFIG" */ +/* SHub RTC 2 Interrupt Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_rtc2_int_config_u { + mmr_t sh_rtc2_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_rtc2_int_config_s; +} sh_rtc2_int_config_u_t; +#else +typedef union sh_rtc2_int_config_u { + mmr_t sh_rtc2_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_rtc2_int_config_s; +} sh_rtc2_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_RTC2_INT_ENABLE" */ +/* SHub RTC 2 Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_rtc2_int_enable_u { + mmr_t sh_rtc2_int_enable_regval; + struct { + mmr_t rtc2_enable : 1; + mmr_t reserved_0 : 63; + } sh_rtc2_int_enable_s; +} sh_rtc2_int_enable_u_t; +#else +typedef union sh_rtc2_int_enable_u { + mmr_t sh_rtc2_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t rtc2_enable : 1; + } sh_rtc2_int_enable_s; +} sh_rtc2_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_RTC3_INT_CONFIG" */ +/* SHub RTC 3 Interrupt Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_rtc3_int_config_u { + mmr_t sh_rtc3_int_config_regval; + struct { + mmr_t type : 3; + mmr_t agt : 1; + mmr_t pid : 16; + mmr_t reserved_0 : 1; + mmr_t base : 29; + mmr_t reserved_1 : 2; + mmr_t idx : 8; + mmr_t reserved_2 : 4; + } sh_rtc3_int_config_s; +} sh_rtc3_int_config_u_t; +#else +typedef union sh_rtc3_int_config_u { + mmr_t sh_rtc3_int_config_regval; + struct { + mmr_t reserved_2 : 4; + mmr_t idx : 8; + mmr_t reserved_1 : 2; + mmr_t base : 29; + mmr_t reserved_0 : 1; + mmr_t pid : 16; + mmr_t agt : 1; + mmr_t type : 3; + } sh_rtc3_int_config_s; +} sh_rtc3_int_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_RTC3_INT_ENABLE" */ +/* SHub RTC 3 Interrupt Enable Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_rtc3_int_enable_u { + mmr_t sh_rtc3_int_enable_regval; + struct { + mmr_t rtc3_enable : 1; + mmr_t reserved_0 : 63; + } sh_rtc3_int_enable_s; +} sh_rtc3_int_enable_u_t; +#else +typedef union sh_rtc3_int_enable_u { + mmr_t sh_rtc3_int_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t rtc3_enable : 1; + } sh_rtc3_int_enable_s; +} sh_rtc3_int_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_EVENT_OCCURRED" */ +/* SHub Interrupt Event Occurred */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_event_occurred_u { + mmr_t sh_event_occurred_regval; + struct { + mmr_t pi_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t ii_hw_int : 1; + mmr_t pi_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t xn_uce_int : 1; + mmr_t proc0_adv_int : 1; + mmr_t proc1_adv_int : 1; + mmr_t proc2_adv_int : 1; + mmr_t proc3_adv_int : 1; + mmr_t proc0_err_int : 1; + mmr_t proc1_err_int : 1; + mmr_t proc2_err_int : 1; + mmr_t proc3_err_int : 1; + mmr_t system_shutdown_int : 1; + mmr_t uart_int : 1; + mmr_t l1_nmi_int : 1; + mmr_t stop_clock : 1; + mmr_t rtc0_int : 1; + mmr_t rtc1_int : 1; + mmr_t rtc2_int : 1; + mmr_t rtc3_int : 1; + mmr_t profile_int : 1; + mmr_t ipi_int : 1; + mmr_t ii_int0 : 1; + mmr_t ii_int1 : 1; + mmr_t reserved_0 : 33; + } sh_event_occurred_s; +} sh_event_occurred_u_t; +#else +typedef union sh_event_occurred_u { + mmr_t sh_event_occurred_regval; + struct { + mmr_t reserved_0 : 33; + mmr_t ii_int1 : 1; + mmr_t ii_int0 : 1; + mmr_t ipi_int : 1; + mmr_t profile_int : 1; + mmr_t rtc3_int : 1; + mmr_t rtc2_int : 1; + mmr_t rtc1_int : 1; + mmr_t rtc0_int : 1; + mmr_t stop_clock : 1; + mmr_t l1_nmi_int : 1; + mmr_t uart_int : 1; + mmr_t system_shutdown_int : 1; + mmr_t proc3_err_int : 1; + mmr_t proc2_err_int : 1; + mmr_t proc1_err_int : 1; + mmr_t proc0_err_int : 1; + mmr_t proc3_adv_int : 1; + mmr_t proc2_adv_int : 1; + mmr_t proc1_adv_int : 1; + mmr_t proc0_adv_int : 1; + mmr_t xn_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t pi_ce_int : 1; + mmr_t ii_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t pi_hw_int : 1; + } sh_event_occurred_s; +} sh_event_occurred_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_EVENT_OVERFLOW" */ +/* SHub Interrupt Event Occurred Overflow */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_event_overflow_u { + mmr_t sh_event_overflow_regval; + struct { + mmr_t pi_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t ii_hw_int : 1; + mmr_t pi_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t xn_uce_int : 1; + mmr_t proc0_adv_int : 1; + mmr_t proc1_adv_int : 1; + mmr_t proc2_adv_int : 1; + mmr_t proc3_adv_int : 1; + mmr_t proc0_err_int : 1; + mmr_t proc1_err_int : 1; + mmr_t proc2_err_int : 1; + mmr_t proc3_err_int : 1; + mmr_t system_shutdown_int : 1; + mmr_t uart_int : 1; + mmr_t l1_nmi_int : 1; + mmr_t stop_clock : 1; + mmr_t rtc0_int : 1; + mmr_t rtc1_int : 1; + mmr_t rtc2_int : 1; + mmr_t rtc3_int : 1; + mmr_t profile_int : 1; + mmr_t reserved_0 : 36; + } sh_event_overflow_s; +} sh_event_overflow_u_t; +#else +typedef union sh_event_overflow_u { + mmr_t sh_event_overflow_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t profile_int : 1; + mmr_t rtc3_int : 1; + mmr_t rtc2_int : 1; + mmr_t rtc1_int : 1; + mmr_t rtc0_int : 1; + mmr_t stop_clock : 1; + mmr_t l1_nmi_int : 1; + mmr_t uart_int : 1; + mmr_t system_shutdown_int : 1; + mmr_t proc3_err_int : 1; + mmr_t proc2_err_int : 1; + mmr_t proc1_err_int : 1; + mmr_t proc0_err_int : 1; + mmr_t proc3_adv_int : 1; + mmr_t proc2_adv_int : 1; + mmr_t proc1_adv_int : 1; + mmr_t proc0_adv_int : 1; + mmr_t xn_uce_int : 1; + mmr_t md_uce_int : 1; + mmr_t pi_uce_int : 1; + mmr_t xn_ce_int : 1; + mmr_t md_ce_int : 1; + mmr_t pi_ce_int : 1; + mmr_t ii_hw_int : 1; + mmr_t lb_hw_int : 1; + mmr_t xn_hw_int : 1; + mmr_t md_hw_int : 1; + mmr_t pi_hw_int : 1; + } sh_event_overflow_s; +} sh_event_overflow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_JUNK_BUS_TIME" */ +/* Junk Bus Timing */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_junk_bus_time_u { + mmr_t sh_junk_bus_time_regval; + struct { + mmr_t fprom_setup_hold : 8; + mmr_t fprom_enable : 8; + mmr_t uart_setup_hold : 8; + mmr_t uart_enable : 8; + mmr_t reserved_0 : 32; + } sh_junk_bus_time_s; +} sh_junk_bus_time_u_t; +#else +typedef union sh_junk_bus_time_u { + mmr_t sh_junk_bus_time_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t uart_enable : 8; + mmr_t uart_setup_hold : 8; + mmr_t fprom_enable : 8; + mmr_t fprom_setup_hold : 8; + } sh_junk_bus_time_s; +} sh_junk_bus_time_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_JUNK_LATCH_TIME" */ +/* Junk Bus Latch Timing */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_junk_latch_time_u { + mmr_t sh_junk_latch_time_regval; + struct { + mmr_t setup_hold : 3; + mmr_t reserved_0 : 61; + } sh_junk_latch_time_s; +} sh_junk_latch_time_u_t; +#else +typedef union sh_junk_latch_time_u { + mmr_t sh_junk_latch_time_regval; + struct { + mmr_t reserved_0 : 61; + mmr_t setup_hold : 3; + } sh_junk_latch_time_s; +} sh_junk_latch_time_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_JUNK_NACK_RESET" */ +/* Junk Bus Nack Counter Reset */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_junk_nack_reset_u { + mmr_t sh_junk_nack_reset_regval; + struct { + mmr_t pulse : 1; + mmr_t reserved_0 : 63; + } sh_junk_nack_reset_s; +} sh_junk_nack_reset_u_t; +#else +typedef union sh_junk_nack_reset_u { + mmr_t sh_junk_nack_reset_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t pulse : 1; + } sh_junk_nack_reset_s; +} sh_junk_nack_reset_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_JUNK_BUS_LED0" */ +/* Junk Bus LED0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_junk_bus_led0_u { + mmr_t sh_junk_bus_led0_regval; + struct { + mmr_t led0_data : 8; + mmr_t reserved_0 : 56; + } sh_junk_bus_led0_s; +} sh_junk_bus_led0_u_t; +#else +typedef union sh_junk_bus_led0_u { + mmr_t sh_junk_bus_led0_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t led0_data : 8; + } sh_junk_bus_led0_s; +} sh_junk_bus_led0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_JUNK_BUS_LED1" */ +/* Junk Bus LED1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_junk_bus_led1_u { + mmr_t sh_junk_bus_led1_regval; + struct { + mmr_t led1_data : 8; + mmr_t reserved_0 : 56; + } sh_junk_bus_led1_s; +} sh_junk_bus_led1_u_t; +#else +typedef union sh_junk_bus_led1_u { + mmr_t sh_junk_bus_led1_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t led1_data : 8; + } sh_junk_bus_led1_s; +} sh_junk_bus_led1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_JUNK_BUS_LED2" */ +/* Junk Bus LED2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_junk_bus_led2_u { + mmr_t sh_junk_bus_led2_regval; + struct { + mmr_t led2_data : 8; + mmr_t reserved_0 : 56; + } sh_junk_bus_led2_s; +} sh_junk_bus_led2_u_t; +#else +typedef union sh_junk_bus_led2_u { + mmr_t sh_junk_bus_led2_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t led2_data : 8; + } sh_junk_bus_led2_s; +} sh_junk_bus_led2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_JUNK_BUS_LED3" */ +/* Junk Bus LED3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_junk_bus_led3_u { + mmr_t sh_junk_bus_led3_regval; + struct { + mmr_t led3_data : 8; + mmr_t reserved_0 : 56; + } sh_junk_bus_led3_s; +} sh_junk_bus_led3_u_t; +#else +typedef union sh_junk_bus_led3_u { + mmr_t sh_junk_bus_led3_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t led3_data : 8; + } sh_junk_bus_led3_s; +} sh_junk_bus_led3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_JUNK_ERROR_STATUS" */ +/* Junk Bus Error Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_junk_error_status_u { + mmr_t sh_junk_error_status_regval; + struct { + mmr_t address : 47; + mmr_t reserved_0 : 1; + mmr_t cmd : 8; + mmr_t mode : 1; + mmr_t status : 4; + mmr_t reserved_1 : 3; + } sh_junk_error_status_s; +} sh_junk_error_status_u_t; +#else +typedef union sh_junk_error_status_u { + mmr_t sh_junk_error_status_regval; + struct { + mmr_t reserved_1 : 3; + mmr_t status : 4; + mmr_t mode : 1; + mmr_t cmd : 8; + mmr_t reserved_0 : 1; + mmr_t address : 47; + } sh_junk_error_status_s; +} sh_junk_error_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_STAT" */ +/* This register describes the LLP status. */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_llp_stat_u { + mmr_t sh_ni0_llp_stat_regval; + struct { + mmr_t link_reset_state : 4; + mmr_t reserved_0 : 60; + } sh_ni0_llp_stat_s; +} sh_ni0_llp_stat_u_t; +#else +typedef union sh_ni0_llp_stat_u { + mmr_t sh_ni0_llp_stat_regval; + struct { + mmr_t reserved_0 : 60; + mmr_t link_reset_state : 4; + } sh_ni0_llp_stat_s; +} sh_ni0_llp_stat_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_RESET" */ +/* Writing issues a reset to the network interface */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_llp_reset_u { + mmr_t sh_ni0_llp_reset_regval; + struct { + mmr_t link : 1; + mmr_t warm : 1; + mmr_t reserved_0 : 62; + } sh_ni0_llp_reset_s; +} sh_ni0_llp_reset_u_t; +#else +typedef union sh_ni0_llp_reset_u { + mmr_t sh_ni0_llp_reset_regval; + struct { + mmr_t reserved_0 : 62; + mmr_t warm : 1; + mmr_t link : 1; + } sh_ni0_llp_reset_s; +} sh_ni0_llp_reset_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_RESET_EN" */ +/* Controls LLP warm reset propagation */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_llp_reset_en_u { + mmr_t sh_ni0_llp_reset_en_regval; + struct { + mmr_t ok : 1; + mmr_t reserved_0 : 63; + } sh_ni0_llp_reset_en_s; +} sh_ni0_llp_reset_en_u_t; +#else +typedef union sh_ni0_llp_reset_en_u { + mmr_t sh_ni0_llp_reset_en_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t ok : 1; + } sh_ni0_llp_reset_en_s; +} sh_ni0_llp_reset_en_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_CHAN_MODE" */ +/* Sets the signaling mode of LLP and channel */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_llp_chan_mode_u { + mmr_t sh_ni0_llp_chan_mode_regval; + struct { + mmr_t bitmode32 : 1; + mmr_t ac_encode : 1; + mmr_t enable_tuning : 1; + mmr_t enable_rmt_ft_upd : 1; + mmr_t enable_clkquad : 1; + mmr_t reserved_0 : 59; + } sh_ni0_llp_chan_mode_s; +} sh_ni0_llp_chan_mode_u_t; +#else +typedef union sh_ni0_llp_chan_mode_u { + mmr_t sh_ni0_llp_chan_mode_regval; + struct { + mmr_t reserved_0 : 59; + mmr_t enable_clkquad : 1; + mmr_t enable_rmt_ft_upd : 1; + mmr_t enable_tuning : 1; + mmr_t ac_encode : 1; + mmr_t bitmode32 : 1; + } sh_ni0_llp_chan_mode_s; +} sh_ni0_llp_chan_mode_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_CONFIG" */ +/* Sets the configuration of LLP and channel */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_llp_config_u { + mmr_t sh_ni0_llp_config_regval; + struct { + mmr_t maxburst : 10; + mmr_t maxretry : 10; + mmr_t nulltimeout : 6; + mmr_t ftu_time : 12; + mmr_t reserved_0 : 26; + } sh_ni0_llp_config_s; +} sh_ni0_llp_config_u_t; +#else +typedef union sh_ni0_llp_config_u { + mmr_t sh_ni0_llp_config_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t ftu_time : 12; + mmr_t nulltimeout : 6; + mmr_t maxretry : 10; + mmr_t maxburst : 10; + } sh_ni0_llp_config_s; +} sh_ni0_llp_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_TEST_CTL" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_llp_test_ctl_u { + mmr_t sh_ni0_llp_test_ctl_regval; + struct { + mmr_t pattern : 40; + mmr_t send_test_mode : 2; + mmr_t reserved_0 : 2; + mmr_t wire_sel : 6; + mmr_t reserved_1 : 2; + mmr_t lfsr_mode : 2; + mmr_t noise_mode : 2; + mmr_t armcapture : 1; + mmr_t capturecbonly : 1; + mmr_t sendcberror : 1; + mmr_t sendsnerror : 1; + mmr_t fakesnerror : 1; + mmr_t captured : 1; + mmr_t cberror : 1; + mmr_t reserved_2 : 1; + } sh_ni0_llp_test_ctl_s; +} sh_ni0_llp_test_ctl_u_t; +#else +typedef union sh_ni0_llp_test_ctl_u { + mmr_t sh_ni0_llp_test_ctl_regval; + struct { + mmr_t reserved_2 : 1; + mmr_t cberror : 1; + mmr_t captured : 1; + mmr_t fakesnerror : 1; + mmr_t sendsnerror : 1; + mmr_t sendcberror : 1; + mmr_t capturecbonly : 1; + mmr_t armcapture : 1; + mmr_t noise_mode : 2; + mmr_t lfsr_mode : 2; + mmr_t reserved_1 : 2; + mmr_t wire_sel : 6; + mmr_t reserved_0 : 2; + mmr_t send_test_mode : 2; + mmr_t pattern : 40; + } sh_ni0_llp_test_ctl_s; +} sh_ni0_llp_test_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_CAPT_WD1" */ +/* low order 64-bit captured word */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_llp_capt_wd1_u { + mmr_t sh_ni0_llp_capt_wd1_regval; + struct { + mmr_t data : 64; + } sh_ni0_llp_capt_wd1_s; +} sh_ni0_llp_capt_wd1_u_t; +#else +typedef union sh_ni0_llp_capt_wd1_u { + mmr_t sh_ni0_llp_capt_wd1_regval; + struct { + mmr_t data : 64; + } sh_ni0_llp_capt_wd1_s; +} sh_ni0_llp_capt_wd1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_CAPT_WD2" */ +/* high order 64-bit captured word */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_llp_capt_wd2_u { + mmr_t sh_ni0_llp_capt_wd2_regval; + struct { + mmr_t data : 64; + } sh_ni0_llp_capt_wd2_s; +} sh_ni0_llp_capt_wd2_u_t; +#else +typedef union sh_ni0_llp_capt_wd2_u { + mmr_t sh_ni0_llp_capt_wd2_regval; + struct { + mmr_t data : 64; + } sh_ni0_llp_capt_wd2_s; +} sh_ni0_llp_capt_wd2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_CAPT_SBCB" */ +/* captured sideband, sequence, and CRC */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_llp_capt_sbcb_u { + mmr_t sh_ni0_llp_capt_sbcb_regval; + struct { + mmr_t capturedrcvsbsn : 16; + mmr_t capturedrcvcrc : 16; + mmr_t sentallcberrors : 1; + mmr_t sentallsnerrors : 1; + mmr_t fakedallsnerrors : 1; + mmr_t chargeoverflow : 1; + mmr_t chargeunderflow : 1; + mmr_t reserved_0 : 27; + } sh_ni0_llp_capt_sbcb_s; +} sh_ni0_llp_capt_sbcb_u_t; +#else +typedef union sh_ni0_llp_capt_sbcb_u { + mmr_t sh_ni0_llp_capt_sbcb_regval; + struct { + mmr_t reserved_0 : 27; + mmr_t chargeunderflow : 1; + mmr_t chargeoverflow : 1; + mmr_t fakedallsnerrors : 1; + mmr_t sentallsnerrors : 1; + mmr_t sentallcberrors : 1; + mmr_t capturedrcvcrc : 16; + mmr_t capturedrcvsbsn : 16; + } sh_ni0_llp_capt_sbcb_s; +} sh_ni0_llp_capt_sbcb_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_LLP_ERR" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_llp_err_u { + mmr_t sh_ni0_llp_err_regval; + struct { + mmr_t rx_sn_err_count : 8; + mmr_t rx_cb_err_count : 8; + mmr_t retry_count : 8; + mmr_t retry_timeout : 1; + mmr_t rcv_link_reset : 1; + mmr_t squash : 1; + mmr_t power_not_ok : 1; + mmr_t wire_cnt : 24; + mmr_t wire_overflow : 1; + mmr_t reserved_0 : 11; + } sh_ni0_llp_err_s; +} sh_ni0_llp_err_u_t; +#else +typedef union sh_ni0_llp_err_u { + mmr_t sh_ni0_llp_err_regval; + struct { + mmr_t reserved_0 : 11; + mmr_t wire_overflow : 1; + mmr_t wire_cnt : 24; + mmr_t power_not_ok : 1; + mmr_t squash : 1; + mmr_t rcv_link_reset : 1; + mmr_t retry_timeout : 1; + mmr_t retry_count : 8; + mmr_t rx_cb_err_count : 8; + mmr_t rx_sn_err_count : 8; + } sh_ni0_llp_err_s; +} sh_ni0_llp_err_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_STAT" */ +/* This register describes the LLP status. */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_llp_stat_u { + mmr_t sh_ni1_llp_stat_regval; + struct { + mmr_t link_reset_state : 4; + mmr_t reserved_0 : 60; + } sh_ni1_llp_stat_s; +} sh_ni1_llp_stat_u_t; +#else +typedef union sh_ni1_llp_stat_u { + mmr_t sh_ni1_llp_stat_regval; + struct { + mmr_t reserved_0 : 60; + mmr_t link_reset_state : 4; + } sh_ni1_llp_stat_s; +} sh_ni1_llp_stat_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_RESET" */ +/* Writing issues a reset to the network interface */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_llp_reset_u { + mmr_t sh_ni1_llp_reset_regval; + struct { + mmr_t link : 1; + mmr_t warm : 1; + mmr_t reserved_0 : 62; + } sh_ni1_llp_reset_s; +} sh_ni1_llp_reset_u_t; +#else +typedef union sh_ni1_llp_reset_u { + mmr_t sh_ni1_llp_reset_regval; + struct { + mmr_t reserved_0 : 62; + mmr_t warm : 1; + mmr_t link : 1; + } sh_ni1_llp_reset_s; +} sh_ni1_llp_reset_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_RESET_EN" */ +/* Controls LLP warm reset propagation */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_llp_reset_en_u { + mmr_t sh_ni1_llp_reset_en_regval; + struct { + mmr_t ok : 1; + mmr_t reserved_0 : 63; + } sh_ni1_llp_reset_en_s; +} sh_ni1_llp_reset_en_u_t; +#else +typedef union sh_ni1_llp_reset_en_u { + mmr_t sh_ni1_llp_reset_en_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t ok : 1; + } sh_ni1_llp_reset_en_s; +} sh_ni1_llp_reset_en_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_CHAN_MODE" */ +/* Sets the signaling mode of LLP and channel */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_llp_chan_mode_u { + mmr_t sh_ni1_llp_chan_mode_regval; + struct { + mmr_t bitmode32 : 1; + mmr_t ac_encode : 1; + mmr_t enable_tuning : 1; + mmr_t enable_rmt_ft_upd : 1; + mmr_t enable_clkquad : 1; + mmr_t reserved_0 : 59; + } sh_ni1_llp_chan_mode_s; +} sh_ni1_llp_chan_mode_u_t; +#else +typedef union sh_ni1_llp_chan_mode_u { + mmr_t sh_ni1_llp_chan_mode_regval; + struct { + mmr_t reserved_0 : 59; + mmr_t enable_clkquad : 1; + mmr_t enable_rmt_ft_upd : 1; + mmr_t enable_tuning : 1; + mmr_t ac_encode : 1; + mmr_t bitmode32 : 1; + } sh_ni1_llp_chan_mode_s; +} sh_ni1_llp_chan_mode_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_CONFIG" */ +/* Sets the configuration of LLP and channel */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_llp_config_u { + mmr_t sh_ni1_llp_config_regval; + struct { + mmr_t maxburst : 10; + mmr_t maxretry : 10; + mmr_t nulltimeout : 6; + mmr_t ftu_time : 12; + mmr_t reserved_0 : 26; + } sh_ni1_llp_config_s; +} sh_ni1_llp_config_u_t; +#else +typedef union sh_ni1_llp_config_u { + mmr_t sh_ni1_llp_config_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t ftu_time : 12; + mmr_t nulltimeout : 6; + mmr_t maxretry : 10; + mmr_t maxburst : 10; + } sh_ni1_llp_config_s; +} sh_ni1_llp_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_TEST_CTL" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_llp_test_ctl_u { + mmr_t sh_ni1_llp_test_ctl_regval; + struct { + mmr_t pattern : 40; + mmr_t send_test_mode : 2; + mmr_t reserved_0 : 2; + mmr_t wire_sel : 6; + mmr_t reserved_1 : 2; + mmr_t lfsr_mode : 2; + mmr_t noise_mode : 2; + mmr_t armcapture : 1; + mmr_t capturecbonly : 1; + mmr_t sendcberror : 1; + mmr_t sendsnerror : 1; + mmr_t fakesnerror : 1; + mmr_t captured : 1; + mmr_t cberror : 1; + mmr_t reserved_2 : 1; + } sh_ni1_llp_test_ctl_s; +} sh_ni1_llp_test_ctl_u_t; +#else +typedef union sh_ni1_llp_test_ctl_u { + mmr_t sh_ni1_llp_test_ctl_regval; + struct { + mmr_t reserved_2 : 1; + mmr_t cberror : 1; + mmr_t captured : 1; + mmr_t fakesnerror : 1; + mmr_t sendsnerror : 1; + mmr_t sendcberror : 1; + mmr_t capturecbonly : 1; + mmr_t armcapture : 1; + mmr_t noise_mode : 2; + mmr_t lfsr_mode : 2; + mmr_t reserved_1 : 2; + mmr_t wire_sel : 6; + mmr_t reserved_0 : 2; + mmr_t send_test_mode : 2; + mmr_t pattern : 40; + } sh_ni1_llp_test_ctl_s; +} sh_ni1_llp_test_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_CAPT_WD1" */ +/* low order 64-bit captured word */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_llp_capt_wd1_u { + mmr_t sh_ni1_llp_capt_wd1_regval; + struct { + mmr_t data : 64; + } sh_ni1_llp_capt_wd1_s; +} sh_ni1_llp_capt_wd1_u_t; +#else +typedef union sh_ni1_llp_capt_wd1_u { + mmr_t sh_ni1_llp_capt_wd1_regval; + struct { + mmr_t data : 64; + } sh_ni1_llp_capt_wd1_s; +} sh_ni1_llp_capt_wd1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_CAPT_WD2" */ +/* high order 64-bit captured word */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_llp_capt_wd2_u { + mmr_t sh_ni1_llp_capt_wd2_regval; + struct { + mmr_t data : 64; + } sh_ni1_llp_capt_wd2_s; +} sh_ni1_llp_capt_wd2_u_t; +#else +typedef union sh_ni1_llp_capt_wd2_u { + mmr_t sh_ni1_llp_capt_wd2_regval; + struct { + mmr_t data : 64; + } sh_ni1_llp_capt_wd2_s; +} sh_ni1_llp_capt_wd2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_CAPT_SBCB" */ +/* captured sideband, sequence, and CRC */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_llp_capt_sbcb_u { + mmr_t sh_ni1_llp_capt_sbcb_regval; + struct { + mmr_t capturedrcvsbsn : 16; + mmr_t capturedrcvcrc : 16; + mmr_t sentallcberrors : 1; + mmr_t sentallsnerrors : 1; + mmr_t fakedallsnerrors : 1; + mmr_t chargeoverflow : 1; + mmr_t chargeunderflow : 1; + mmr_t reserved_0 : 27; + } sh_ni1_llp_capt_sbcb_s; +} sh_ni1_llp_capt_sbcb_u_t; +#else +typedef union sh_ni1_llp_capt_sbcb_u { + mmr_t sh_ni1_llp_capt_sbcb_regval; + struct { + mmr_t reserved_0 : 27; + mmr_t chargeunderflow : 1; + mmr_t chargeoverflow : 1; + mmr_t fakedallsnerrors : 1; + mmr_t sentallsnerrors : 1; + mmr_t sentallcberrors : 1; + mmr_t capturedrcvcrc : 16; + mmr_t capturedrcvsbsn : 16; + } sh_ni1_llp_capt_sbcb_s; +} sh_ni1_llp_capt_sbcb_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_LLP_ERR" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_llp_err_u { + mmr_t sh_ni1_llp_err_regval; + struct { + mmr_t rx_sn_err_count : 8; + mmr_t rx_cb_err_count : 8; + mmr_t retry_count : 8; + mmr_t retry_timeout : 1; + mmr_t rcv_link_reset : 1; + mmr_t squash : 1; + mmr_t power_not_ok : 1; + mmr_t wire_cnt : 24; + mmr_t wire_overflow : 1; + mmr_t reserved_0 : 11; + } sh_ni1_llp_err_s; +} sh_ni1_llp_err_u_t; +#else +typedef union sh_ni1_llp_err_u { + mmr_t sh_ni1_llp_err_regval; + struct { + mmr_t reserved_0 : 11; + mmr_t wire_overflow : 1; + mmr_t wire_cnt : 24; + mmr_t power_not_ok : 1; + mmr_t squash : 1; + mmr_t rcv_link_reset : 1; + mmr_t retry_timeout : 1; + mmr_t retry_count : 8; + mmr_t rx_cb_err_count : 8; + mmr_t rx_sn_err_count : 8; + } sh_ni1_llp_err_s; +} sh_ni1_llp_err_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_LLP_TO_FIFO02_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_llp_to_fifo02_flow_u { + mmr_t sh_xnni0_llp_to_fifo02_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_6 : 2; + } sh_xnni0_llp_to_fifo02_flow_s; +} sh_xnni0_llp_to_fifo02_flow_u_t; +#else +typedef union sh_xnni0_llp_to_fifo02_flow_u { + mmr_t sh_xnni0_llp_to_fifo02_flow_regval; + struct { + mmr_t reserved_6 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_2 : 8; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnni0_llp_to_fifo02_flow_s; +} sh_xnni0_llp_to_fifo02_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_LLP_TO_FIFO13_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_llp_to_fifo13_flow_u { + mmr_t sh_xnni0_llp_to_fifo13_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_6 : 2; + } sh_xnni0_llp_to_fifo13_flow_s; +} sh_xnni0_llp_to_fifo13_flow_u_t; +#else +typedef union sh_xnni0_llp_to_fifo13_flow_u { + mmr_t sh_xnni0_llp_to_fifo13_flow_regval; + struct { + mmr_t reserved_6 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_2 : 8; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnni0_llp_to_fifo13_flow_s; +} sh_xnni0_llp_to_fifo13_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_LLP_DEBIT_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_llp_debit_flow_u { + mmr_t sh_xnni0_llp_debit_flow_regval; + struct { + mmr_t debit_vc0_dyn : 5; + mmr_t reserved_0 : 3; + mmr_t debit_vc0_cap : 5; + mmr_t reserved_1 : 3; + mmr_t debit_vc1_dyn : 5; + mmr_t reserved_2 : 3; + mmr_t debit_vc1_cap : 5; + mmr_t reserved_3 : 3; + mmr_t debit_vc2_dyn : 5; + mmr_t reserved_4 : 3; + mmr_t debit_vc2_cap : 5; + mmr_t reserved_5 : 3; + mmr_t debit_vc3_dyn : 5; + mmr_t reserved_6 : 3; + mmr_t debit_vc3_cap : 5; + mmr_t reserved_7 : 3; + } sh_xnni0_llp_debit_flow_s; +} sh_xnni0_llp_debit_flow_u_t; +#else +typedef union sh_xnni0_llp_debit_flow_u { + mmr_t sh_xnni0_llp_debit_flow_regval; + struct { + mmr_t reserved_7 : 3; + mmr_t debit_vc3_cap : 5; + mmr_t reserved_6 : 3; + mmr_t debit_vc3_dyn : 5; + mmr_t reserved_5 : 3; + mmr_t debit_vc2_cap : 5; + mmr_t reserved_4 : 3; + mmr_t debit_vc2_dyn : 5; + mmr_t reserved_3 : 3; + mmr_t debit_vc1_cap : 5; + mmr_t reserved_2 : 3; + mmr_t debit_vc1_dyn : 5; + mmr_t reserved_1 : 3; + mmr_t debit_vc0_cap : 5; + mmr_t reserved_0 : 3; + mmr_t debit_vc0_dyn : 5; + } sh_xnni0_llp_debit_flow_s; +} sh_xnni0_llp_debit_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_LINK_0_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_link_0_flow_u { + mmr_t sh_xnni0_link_0_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t credit_vc0_test : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc0_dyn : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc0_cap : 7; + mmr_t reserved_3 : 33; + } sh_xnni0_link_0_flow_s; +} sh_xnni0_link_0_flow_u_t; +#else +typedef union sh_xnni0_link_0_flow_u { + mmr_t sh_xnni0_link_0_flow_regval; + struct { + mmr_t reserved_3 : 33; + mmr_t credit_vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc0_test : 7; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnni0_link_0_flow_s; +} sh_xnni0_link_0_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_LINK_1_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_link_1_flow_u { + mmr_t sh_xnni0_link_1_flow_regval; + struct { + mmr_t debit_vc1_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc1_force_cred : 1; + mmr_t credit_vc1_test : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc1_dyn : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc1_cap : 7; + mmr_t reserved_3 : 33; + } sh_xnni0_link_1_flow_s; +} sh_xnni0_link_1_flow_u_t; +#else +typedef union sh_xnni0_link_1_flow_u { + mmr_t sh_xnni0_link_1_flow_regval; + struct { + mmr_t reserved_3 : 33; + mmr_t credit_vc1_cap : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc1_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc1_test : 7; + mmr_t debit_vc1_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc1_withhold : 6; + } sh_xnni0_link_1_flow_s; +} sh_xnni0_link_1_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_LINK_2_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_link_2_flow_u { + mmr_t sh_xnni0_link_2_flow_regval; + struct { + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t credit_vc2_test : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc2_dyn : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc2_cap : 7; + mmr_t reserved_3 : 33; + } sh_xnni0_link_2_flow_s; +} sh_xnni0_link_2_flow_u_t; +#else +typedef union sh_xnni0_link_2_flow_u { + mmr_t sh_xnni0_link_2_flow_regval; + struct { + mmr_t reserved_3 : 33; + mmr_t credit_vc2_cap : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc2_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc2_test : 7; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc2_withhold : 6; + } sh_xnni0_link_2_flow_s; +} sh_xnni0_link_2_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_LINK_3_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_link_3_flow_u { + mmr_t sh_xnni0_link_3_flow_regval; + struct { + mmr_t debit_vc3_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc3_force_cred : 1; + mmr_t credit_vc3_test : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc3_dyn : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc3_cap : 7; + mmr_t reserved_3 : 33; + } sh_xnni0_link_3_flow_s; +} sh_xnni0_link_3_flow_u_t; +#else +typedef union sh_xnni0_link_3_flow_u { + mmr_t sh_xnni0_link_3_flow_regval; + struct { + mmr_t reserved_3 : 33; + mmr_t credit_vc3_cap : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc3_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc3_test : 7; + mmr_t debit_vc3_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc3_withhold : 6; + } sh_xnni0_link_3_flow_s; +} sh_xnni0_link_3_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_LLP_TO_FIFO02_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_llp_to_fifo02_flow_u { + mmr_t sh_xnni1_llp_to_fifo02_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_6 : 2; + } sh_xnni1_llp_to_fifo02_flow_s; +} sh_xnni1_llp_to_fifo02_flow_u_t; +#else +typedef union sh_xnni1_llp_to_fifo02_flow_u { + mmr_t sh_xnni1_llp_to_fifo02_flow_regval; + struct { + mmr_t reserved_6 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_2 : 8; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnni1_llp_to_fifo02_flow_s; +} sh_xnni1_llp_to_fifo02_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_LLP_TO_FIFO13_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_llp_to_fifo13_flow_u { + mmr_t sh_xnni1_llp_to_fifo13_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_6 : 2; + } sh_xnni1_llp_to_fifo13_flow_s; +} sh_xnni1_llp_to_fifo13_flow_u_t; +#else +typedef union sh_xnni1_llp_to_fifo13_flow_u { + mmr_t sh_xnni1_llp_to_fifo13_flow_regval; + struct { + mmr_t reserved_6 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_2 : 8; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnni1_llp_to_fifo13_flow_s; +} sh_xnni1_llp_to_fifo13_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_LLP_DEBIT_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_llp_debit_flow_u { + mmr_t sh_xnni1_llp_debit_flow_regval; + struct { + mmr_t debit_vc0_dyn : 5; + mmr_t reserved_0 : 3; + mmr_t debit_vc0_cap : 5; + mmr_t reserved_1 : 3; + mmr_t debit_vc1_dyn : 5; + mmr_t reserved_2 : 3; + mmr_t debit_vc1_cap : 5; + mmr_t reserved_3 : 3; + mmr_t debit_vc2_dyn : 5; + mmr_t reserved_4 : 3; + mmr_t debit_vc2_cap : 5; + mmr_t reserved_5 : 3; + mmr_t debit_vc3_dyn : 5; + mmr_t reserved_6 : 3; + mmr_t debit_vc3_cap : 5; + mmr_t reserved_7 : 3; + } sh_xnni1_llp_debit_flow_s; +} sh_xnni1_llp_debit_flow_u_t; +#else +typedef union sh_xnni1_llp_debit_flow_u { + mmr_t sh_xnni1_llp_debit_flow_regval; + struct { + mmr_t reserved_7 : 3; + mmr_t debit_vc3_cap : 5; + mmr_t reserved_6 : 3; + mmr_t debit_vc3_dyn : 5; + mmr_t reserved_5 : 3; + mmr_t debit_vc2_cap : 5; + mmr_t reserved_4 : 3; + mmr_t debit_vc2_dyn : 5; + mmr_t reserved_3 : 3; + mmr_t debit_vc1_cap : 5; + mmr_t reserved_2 : 3; + mmr_t debit_vc1_dyn : 5; + mmr_t reserved_1 : 3; + mmr_t debit_vc0_cap : 5; + mmr_t reserved_0 : 3; + mmr_t debit_vc0_dyn : 5; + } sh_xnni1_llp_debit_flow_s; +} sh_xnni1_llp_debit_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_LINK_0_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_link_0_flow_u { + mmr_t sh_xnni1_link_0_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t credit_vc0_test : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc0_dyn : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc0_cap : 7; + mmr_t reserved_3 : 33; + } sh_xnni1_link_0_flow_s; +} sh_xnni1_link_0_flow_u_t; +#else +typedef union sh_xnni1_link_0_flow_u { + mmr_t sh_xnni1_link_0_flow_regval; + struct { + mmr_t reserved_3 : 33; + mmr_t credit_vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc0_test : 7; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnni1_link_0_flow_s; +} sh_xnni1_link_0_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_LINK_1_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_link_1_flow_u { + mmr_t sh_xnni1_link_1_flow_regval; + struct { + mmr_t debit_vc1_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc1_force_cred : 1; + mmr_t credit_vc1_test : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc1_dyn : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc1_cap : 7; + mmr_t reserved_3 : 33; + } sh_xnni1_link_1_flow_s; +} sh_xnni1_link_1_flow_u_t; +#else +typedef union sh_xnni1_link_1_flow_u { + mmr_t sh_xnni1_link_1_flow_regval; + struct { + mmr_t reserved_3 : 33; + mmr_t credit_vc1_cap : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc1_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc1_test : 7; + mmr_t debit_vc1_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc1_withhold : 6; + } sh_xnni1_link_1_flow_s; +} sh_xnni1_link_1_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_LINK_2_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_link_2_flow_u { + mmr_t sh_xnni1_link_2_flow_regval; + struct { + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t credit_vc2_test : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc2_dyn : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc2_cap : 7; + mmr_t reserved_3 : 33; + } sh_xnni1_link_2_flow_s; +} sh_xnni1_link_2_flow_u_t; +#else +typedef union sh_xnni1_link_2_flow_u { + mmr_t sh_xnni1_link_2_flow_regval; + struct { + mmr_t reserved_3 : 33; + mmr_t credit_vc2_cap : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc2_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc2_test : 7; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc2_withhold : 6; + } sh_xnni1_link_2_flow_s; +} sh_xnni1_link_2_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_LINK_3_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_link_3_flow_u { + mmr_t sh_xnni1_link_3_flow_regval; + struct { + mmr_t debit_vc3_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc3_force_cred : 1; + mmr_t credit_vc3_test : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc3_dyn : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc3_cap : 7; + mmr_t reserved_3 : 33; + } sh_xnni1_link_3_flow_s; +} sh_xnni1_link_3_flow_u_t; +#else +typedef union sh_xnni1_link_3_flow_u { + mmr_t sh_xnni1_link_3_flow_regval; + struct { + mmr_t reserved_3 : 33; + mmr_t credit_vc3_cap : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc3_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t credit_vc3_test : 7; + mmr_t debit_vc3_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc3_withhold : 6; + } sh_xnni1_link_3_flow_s; +} sh_xnni1_link_3_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_IILB_LOCAL_TABLE" */ +/* local lookup table */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_iilb_local_table_u { + mmr_t sh_iilb_local_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t ni_sel0 : 1; + mmr_t reserved_0 : 57; + mmr_t valid : 1; + } sh_iilb_local_table_s; +} sh_iilb_local_table_u_t; +#else +typedef union sh_iilb_local_table_u { + mmr_t sh_iilb_local_table_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_0 : 57; + mmr_t ni_sel0 : 1; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_iilb_local_table_s; +} sh_iilb_local_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_IILB_GLOBAL_TABLE" */ +/* global lookup table */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_iilb_global_table_u { + mmr_t sh_iilb_global_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t ni_sel0 : 1; + mmr_t reserved_0 : 57; + mmr_t valid : 1; + } sh_iilb_global_table_s; +} sh_iilb_global_table_u_t; +#else +typedef union sh_iilb_global_table_u { + mmr_t sh_iilb_global_table_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_0 : 57; + mmr_t ni_sel0 : 1; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_iilb_global_table_s; +} sh_iilb_global_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_IILB_OVER_RIDE_TABLE" */ +/* If enabled, bypass the Global/Local tables */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_iilb_over_ride_table_u { + mmr_t sh_iilb_over_ride_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t ni_sel0 : 1; + mmr_t reserved_0 : 57; + mmr_t enable : 1; + } sh_iilb_over_ride_table_s; +} sh_iilb_over_ride_table_u_t; +#else +typedef union sh_iilb_over_ride_table_u { + mmr_t sh_iilb_over_ride_table_regval; + struct { + mmr_t enable : 1; + mmr_t reserved_0 : 57; + mmr_t ni_sel0 : 1; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_iilb_over_ride_table_s; +} sh_iilb_over_ride_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_IILB_RSP_PLANE_HINT" */ +/* If enabled, invert incoming response only plane hint bit before lo */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_iilb_rsp_plane_hint_u { + mmr_t sh_iilb_rsp_plane_hint_regval; + struct { + mmr_t reserved_0 : 64; + } sh_iilb_rsp_plane_hint_s; +} sh_iilb_rsp_plane_hint_u_t; +#else +typedef union sh_iilb_rsp_plane_hint_u { + mmr_t sh_iilb_rsp_plane_hint_regval; + struct { + mmr_t reserved_0 : 64; + } sh_iilb_rsp_plane_hint_s; +} sh_iilb_rsp_plane_hint_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_LOCAL_TABLE" */ +/* local lookup table */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_local_table_u { + mmr_t sh_pi_local_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t ni_sel0 : 1; + mmr_t reserved_0 : 2; + mmr_t dir1 : 4; + mmr_t v1 : 1; + mmr_t ni_sel1 : 1; + mmr_t reserved_1 : 49; + mmr_t valid : 1; + } sh_pi_local_table_s; +} sh_pi_local_table_u_t; +#else +typedef union sh_pi_local_table_u { + mmr_t sh_pi_local_table_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_1 : 49; + mmr_t ni_sel1 : 1; + mmr_t v1 : 1; + mmr_t dir1 : 4; + mmr_t reserved_0 : 2; + mmr_t ni_sel0 : 1; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_pi_local_table_s; +} sh_pi_local_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_GLOBAL_TABLE" */ +/* global lookup table */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_global_table_u { + mmr_t sh_pi_global_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t ni_sel0 : 1; + mmr_t reserved_0 : 2; + mmr_t dir1 : 4; + mmr_t v1 : 1; + mmr_t ni_sel1 : 1; + mmr_t reserved_1 : 49; + mmr_t valid : 1; + } sh_pi_global_table_s; +} sh_pi_global_table_u_t; +#else +typedef union sh_pi_global_table_u { + mmr_t sh_pi_global_table_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_1 : 49; + mmr_t ni_sel1 : 1; + mmr_t v1 : 1; + mmr_t dir1 : 4; + mmr_t reserved_0 : 2; + mmr_t ni_sel0 : 1; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_pi_global_table_s; +} sh_pi_global_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_OVER_RIDE_TABLE" */ +/* If enabled, bypass the Global/Local tables */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_over_ride_table_u { + mmr_t sh_pi_over_ride_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t ni_sel0 : 1; + mmr_t reserved_0 : 2; + mmr_t dir1 : 4; + mmr_t v1 : 1; + mmr_t ni_sel1 : 1; + mmr_t reserved_1 : 49; + mmr_t enable : 1; + } sh_pi_over_ride_table_s; +} sh_pi_over_ride_table_u_t; +#else +typedef union sh_pi_over_ride_table_u { + mmr_t sh_pi_over_ride_table_regval; + struct { + mmr_t enable : 1; + mmr_t reserved_1 : 49; + mmr_t ni_sel1 : 1; + mmr_t v1 : 1; + mmr_t dir1 : 4; + mmr_t reserved_0 : 2; + mmr_t ni_sel0 : 1; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_pi_over_ride_table_s; +} sh_pi_over_ride_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_RSP_PLANE_HINT" */ +/* If enabled, invert incoming response only plane hint bit before lo */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_rsp_plane_hint_u { + mmr_t sh_pi_rsp_plane_hint_regval; + struct { + mmr_t invert : 1; + mmr_t reserved_0 : 63; + } sh_pi_rsp_plane_hint_s; +} sh_pi_rsp_plane_hint_u_t; +#else +typedef union sh_pi_rsp_plane_hint_u { + mmr_t sh_pi_rsp_plane_hint_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t invert : 1; + } sh_pi_rsp_plane_hint_s; +} sh_pi_rsp_plane_hint_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_LOCAL_TABLE" */ +/* local lookup table */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_local_table_u { + mmr_t sh_ni0_local_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t reserved_0 : 58; + mmr_t valid : 1; + } sh_ni0_local_table_s; +} sh_ni0_local_table_u_t; +#else +typedef union sh_ni0_local_table_u { + mmr_t sh_ni0_local_table_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_0 : 58; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_ni0_local_table_s; +} sh_ni0_local_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_GLOBAL_TABLE" */ +/* global lookup table */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_global_table_u { + mmr_t sh_ni0_global_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t reserved_0 : 58; + mmr_t valid : 1; + } sh_ni0_global_table_s; +} sh_ni0_global_table_u_t; +#else +typedef union sh_ni0_global_table_u { + mmr_t sh_ni0_global_table_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_0 : 58; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_ni0_global_table_s; +} sh_ni0_global_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_OVER_RIDE_TABLE" */ +/* If enabled, bypass the Global/Local tables */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_over_ride_table_u { + mmr_t sh_ni0_over_ride_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t reserved_0 : 58; + mmr_t enable : 1; + } sh_ni0_over_ride_table_s; +} sh_ni0_over_ride_table_u_t; +#else +typedef union sh_ni0_over_ride_table_u { + mmr_t sh_ni0_over_ride_table_regval; + struct { + mmr_t enable : 1; + mmr_t reserved_0 : 58; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_ni0_over_ride_table_s; +} sh_ni0_over_ride_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_RSP_PLANE_HINT" */ +/* If enabled, invert incoming response only plane hint bit before lo */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_rsp_plane_hint_u { + mmr_t sh_ni0_rsp_plane_hint_regval; + struct { + mmr_t reserved_0 : 64; + } sh_ni0_rsp_plane_hint_s; +} sh_ni0_rsp_plane_hint_u_t; +#else +typedef union sh_ni0_rsp_plane_hint_u { + mmr_t sh_ni0_rsp_plane_hint_regval; + struct { + mmr_t reserved_0 : 64; + } sh_ni0_rsp_plane_hint_s; +} sh_ni0_rsp_plane_hint_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_LOCAL_TABLE" */ +/* local lookup table */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_local_table_u { + mmr_t sh_ni1_local_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t reserved_0 : 58; + mmr_t valid : 1; + } sh_ni1_local_table_s; +} sh_ni1_local_table_u_t; +#else +typedef union sh_ni1_local_table_u { + mmr_t sh_ni1_local_table_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_0 : 58; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_ni1_local_table_s; +} sh_ni1_local_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_GLOBAL_TABLE" */ +/* global lookup table */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_global_table_u { + mmr_t sh_ni1_global_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t reserved_0 : 58; + mmr_t valid : 1; + } sh_ni1_global_table_s; +} sh_ni1_global_table_u_t; +#else +typedef union sh_ni1_global_table_u { + mmr_t sh_ni1_global_table_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_0 : 58; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_ni1_global_table_s; +} sh_ni1_global_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_OVER_RIDE_TABLE" */ +/* If enabled, bypass the Global/Local tables */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_over_ride_table_u { + mmr_t sh_ni1_over_ride_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t reserved_0 : 58; + mmr_t enable : 1; + } sh_ni1_over_ride_table_s; +} sh_ni1_over_ride_table_u_t; +#else +typedef union sh_ni1_over_ride_table_u { + mmr_t sh_ni1_over_ride_table_regval; + struct { + mmr_t enable : 1; + mmr_t reserved_0 : 58; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_ni1_over_ride_table_s; +} sh_ni1_over_ride_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_RSP_PLANE_HINT" */ +/* If enabled, invert incoming response only plane hint bit before lo */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_rsp_plane_hint_u { + mmr_t sh_ni1_rsp_plane_hint_regval; + struct { + mmr_t reserved_0 : 64; + } sh_ni1_rsp_plane_hint_s; +} sh_ni1_rsp_plane_hint_u_t; +#else +typedef union sh_ni1_rsp_plane_hint_u { + mmr_t sh_ni1_rsp_plane_hint_regval; + struct { + mmr_t reserved_0 : 64; + } sh_ni1_rsp_plane_hint_s; +} sh_ni1_rsp_plane_hint_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_LOCAL_TABLE" */ +/* local lookup table */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_local_table_u { + mmr_t sh_md_local_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t ni_sel0 : 1; + mmr_t reserved_0 : 2; + mmr_t dir1 : 4; + mmr_t v1 : 1; + mmr_t ni_sel1 : 1; + mmr_t reserved_1 : 49; + mmr_t valid : 1; + } sh_md_local_table_s; +} sh_md_local_table_u_t; +#else +typedef union sh_md_local_table_u { + mmr_t sh_md_local_table_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_1 : 49; + mmr_t ni_sel1 : 1; + mmr_t v1 : 1; + mmr_t dir1 : 4; + mmr_t reserved_0 : 2; + mmr_t ni_sel0 : 1; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_md_local_table_s; +} sh_md_local_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_GLOBAL_TABLE" */ +/* global lookup table */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_global_table_u { + mmr_t sh_md_global_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t ni_sel0 : 1; + mmr_t reserved_0 : 2; + mmr_t dir1 : 4; + mmr_t v1 : 1; + mmr_t ni_sel1 : 1; + mmr_t reserved_1 : 49; + mmr_t valid : 1; + } sh_md_global_table_s; +} sh_md_global_table_u_t; +#else +typedef union sh_md_global_table_u { + mmr_t sh_md_global_table_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_1 : 49; + mmr_t ni_sel1 : 1; + mmr_t v1 : 1; + mmr_t dir1 : 4; + mmr_t reserved_0 : 2; + mmr_t ni_sel0 : 1; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_md_global_table_s; +} sh_md_global_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_OVER_RIDE_TABLE" */ +/* If enabled, bypass the Global/Local tables */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_over_ride_table_u { + mmr_t sh_md_over_ride_table_regval; + struct { + mmr_t dir0 : 4; + mmr_t v0 : 1; + mmr_t ni_sel0 : 1; + mmr_t reserved_0 : 2; + mmr_t dir1 : 4; + mmr_t v1 : 1; + mmr_t ni_sel1 : 1; + mmr_t reserved_1 : 49; + mmr_t enable : 1; + } sh_md_over_ride_table_s; +} sh_md_over_ride_table_u_t; +#else +typedef union sh_md_over_ride_table_u { + mmr_t sh_md_over_ride_table_regval; + struct { + mmr_t enable : 1; + mmr_t reserved_1 : 49; + mmr_t ni_sel1 : 1; + mmr_t v1 : 1; + mmr_t dir1 : 4; + mmr_t reserved_0 : 2; + mmr_t ni_sel0 : 1; + mmr_t v0 : 1; + mmr_t dir0 : 4; + } sh_md_over_ride_table_s; +} sh_md_over_ride_table_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_RSP_PLANE_HINT" */ +/* If enabled, invert incoming response only plane hint bit before lo */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_rsp_plane_hint_u { + mmr_t sh_md_rsp_plane_hint_regval; + struct { + mmr_t invert : 1; + mmr_t reserved_0 : 63; + } sh_md_rsp_plane_hint_s; +} sh_md_rsp_plane_hint_u_t; +#else +typedef union sh_md_rsp_plane_hint_u { + mmr_t sh_md_rsp_plane_hint_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t invert : 1; + } sh_md_rsp_plane_hint_s; +} sh_md_rsp_plane_hint_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_LIQ_CTL" */ +/* Local Block LIQ Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_liq_ctl_u { + mmr_t sh_lb_liq_ctl_regval; + struct { + mmr_t liq_req_ctl : 5; + mmr_t reserved_0 : 3; + mmr_t liq_rpl_ctl : 4; + mmr_t reserved_1 : 4; + mmr_t force_rq_credit : 1; + mmr_t force_rp_credit : 1; + mmr_t force_linvv_credit : 1; + mmr_t reserved_2 : 45; + } sh_lb_liq_ctl_s; +} sh_lb_liq_ctl_u_t; +#else +typedef union sh_lb_liq_ctl_u { + mmr_t sh_lb_liq_ctl_regval; + struct { + mmr_t reserved_2 : 45; + mmr_t force_linvv_credit : 1; + mmr_t force_rp_credit : 1; + mmr_t force_rq_credit : 1; + mmr_t reserved_1 : 4; + mmr_t liq_rpl_ctl : 4; + mmr_t reserved_0 : 3; + mmr_t liq_req_ctl : 5; + } sh_lb_liq_ctl_s; +} sh_lb_liq_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_LOQ_CTL" */ +/* Local Block LOQ Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_loq_ctl_u { + mmr_t sh_lb_loq_ctl_regval; + struct { + mmr_t loq_req_ctl : 1; + mmr_t loq_rpl_ctl : 1; + mmr_t reserved_0 : 62; + } sh_lb_loq_ctl_s; +} sh_lb_loq_ctl_u_t; +#else +typedef union sh_lb_loq_ctl_u { + mmr_t sh_lb_loq_ctl_regval; + struct { + mmr_t reserved_0 : 62; + mmr_t loq_rpl_ctl : 1; + mmr_t loq_req_ctl : 1; + } sh_lb_loq_ctl_s; +} sh_lb_loq_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_MAX_REP_CREDIT_CNT" */ +/* Maximum number of reply credits from XN */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_max_rep_credit_cnt_u { + mmr_t sh_lb_max_rep_credit_cnt_regval; + struct { + mmr_t max_cnt : 5; + mmr_t reserved_0 : 59; + } sh_lb_max_rep_credit_cnt_s; +} sh_lb_max_rep_credit_cnt_u_t; +#else +typedef union sh_lb_max_rep_credit_cnt_u { + mmr_t sh_lb_max_rep_credit_cnt_regval; + struct { + mmr_t reserved_0 : 59; + mmr_t max_cnt : 5; + } sh_lb_max_rep_credit_cnt_s; +} sh_lb_max_rep_credit_cnt_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_MAX_REQ_CREDIT_CNT" */ +/* Maximum number of request credits from XN */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_max_req_credit_cnt_u { + mmr_t sh_lb_max_req_credit_cnt_regval; + struct { + mmr_t max_cnt : 5; + mmr_t reserved_0 : 59; + } sh_lb_max_req_credit_cnt_s; +} sh_lb_max_req_credit_cnt_u_t; +#else +typedef union sh_lb_max_req_credit_cnt_u { + mmr_t sh_lb_max_req_credit_cnt_regval; + struct { + mmr_t reserved_0 : 59; + mmr_t max_cnt : 5; + } sh_lb_max_req_credit_cnt_s; +} sh_lb_max_req_credit_cnt_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PIO_TIME_OUT" */ +/* Local Block PIO time out value */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pio_time_out_u { + mmr_t sh_pio_time_out_regval; + struct { + mmr_t value : 16; + mmr_t reserved_0 : 48; + } sh_pio_time_out_s; +} sh_pio_time_out_u_t; +#else +typedef union sh_pio_time_out_u { + mmr_t sh_pio_time_out_regval; + struct { + mmr_t reserved_0 : 48; + mmr_t value : 16; + } sh_pio_time_out_s; +} sh_pio_time_out_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PIO_NACK_RESET" */ +/* Local Block PIO Reset for nack counters */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pio_nack_reset_u { + mmr_t sh_pio_nack_reset_regval; + struct { + mmr_t pulse : 1; + mmr_t reserved_0 : 63; + } sh_pio_nack_reset_s; +} sh_pio_nack_reset_u_t; +#else +typedef union sh_pio_nack_reset_u { + mmr_t sh_pio_nack_reset_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t pulse : 1; + } sh_pio_nack_reset_s; +} sh_pio_nack_reset_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_CONVEYOR_BELT_TIME_OUT" */ +/* Local Block conveyor belt time out value */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_conveyor_belt_time_out_u { + mmr_t sh_conveyor_belt_time_out_regval; + struct { + mmr_t value : 12; + mmr_t reserved_0 : 52; + } sh_conveyor_belt_time_out_s; +} sh_conveyor_belt_time_out_u_t; +#else +typedef union sh_conveyor_belt_time_out_u { + mmr_t sh_conveyor_belt_time_out_regval; + struct { + mmr_t reserved_0 : 52; + mmr_t value : 12; + } sh_conveyor_belt_time_out_s; +} sh_conveyor_belt_time_out_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_CREDIT_STATUS" */ +/* Credit Counter Status Register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_credit_status_u { + mmr_t sh_lb_credit_status_regval; + struct { + mmr_t liq_rq_credit : 5; + mmr_t reserved_0 : 1; + mmr_t liq_rp_credit : 4; + mmr_t reserved_1 : 2; + mmr_t linvv_credit : 6; + mmr_t loq_rq_credit : 5; + mmr_t loq_rp_credit : 5; + mmr_t reserved_2 : 36; + } sh_lb_credit_status_s; +} sh_lb_credit_status_u_t; +#else +typedef union sh_lb_credit_status_u { + mmr_t sh_lb_credit_status_regval; + struct { + mmr_t reserved_2 : 36; + mmr_t loq_rp_credit : 5; + mmr_t loq_rq_credit : 5; + mmr_t linvv_credit : 6; + mmr_t reserved_1 : 2; + mmr_t liq_rp_credit : 4; + mmr_t reserved_0 : 1; + mmr_t liq_rq_credit : 5; + } sh_lb_credit_status_s; +} sh_lb_credit_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_DEBUG_LOCAL_SEL" */ +/* LB Debug Port Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_debug_local_sel_u { + mmr_t sh_lb_debug_local_sel_regval; + struct { + mmr_t nibble0_chiplet_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_chiplet_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_chiplet_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_chiplet_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_chiplet_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_chiplet_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_chiplet_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_chiplet_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t trigger_enable : 1; + } sh_lb_debug_local_sel_s; +} sh_lb_debug_local_sel_u_t; +#else +typedef union sh_lb_debug_local_sel_u { + mmr_t sh_lb_debug_local_sel_regval; + struct { + mmr_t trigger_enable : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_chiplet_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_chiplet_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_chiplet_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_chiplet_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_chiplet_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_chiplet_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_chiplet_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_chiplet_sel : 3; + } sh_lb_debug_local_sel_s; +} sh_lb_debug_local_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_DEBUG_PERF_SEL" */ +/* LB Debug Port Performance Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_debug_perf_sel_u { + mmr_t sh_lb_debug_perf_sel_regval; + struct { + mmr_t nibble0_chiplet_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_chiplet_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_chiplet_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_chiplet_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_chiplet_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_chiplet_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_chiplet_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_chiplet_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_lb_debug_perf_sel_s; +} sh_lb_debug_perf_sel_u_t; +#else +typedef union sh_lb_debug_perf_sel_u { + mmr_t sh_lb_debug_perf_sel_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_chiplet_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_chiplet_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_chiplet_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_chiplet_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_chiplet_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_chiplet_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_chiplet_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_chiplet_sel : 3; + } sh_lb_debug_perf_sel_s; +} sh_lb_debug_perf_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_DEBUG_TRIG_SEL" */ +/* LB Debug Trigger Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_debug_trig_sel_u { + mmr_t sh_lb_debug_trig_sel_regval; + struct { + mmr_t trigger0_chiplet_sel : 3; + mmr_t reserved_0 : 1; + mmr_t trigger0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t trigger1_chiplet_sel : 3; + mmr_t reserved_2 : 1; + mmr_t trigger1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t trigger2_chiplet_sel : 3; + mmr_t reserved_4 : 1; + mmr_t trigger2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t trigger3_chiplet_sel : 3; + mmr_t reserved_6 : 1; + mmr_t trigger3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t trigger4_chiplet_sel : 3; + mmr_t reserved_8 : 1; + mmr_t trigger4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t trigger5_chiplet_sel : 3; + mmr_t reserved_10 : 1; + mmr_t trigger5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t trigger6_chiplet_sel : 3; + mmr_t reserved_12 : 1; + mmr_t trigger6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t trigger7_chiplet_sel : 3; + mmr_t reserved_14 : 1; + mmr_t trigger7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_lb_debug_trig_sel_s; +} sh_lb_debug_trig_sel_u_t; +#else +typedef union sh_lb_debug_trig_sel_u { + mmr_t sh_lb_debug_trig_sel_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t trigger7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t trigger7_chiplet_sel : 3; + mmr_t reserved_13 : 1; + mmr_t trigger6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t trigger6_chiplet_sel : 3; + mmr_t reserved_11 : 1; + mmr_t trigger5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t trigger5_chiplet_sel : 3; + mmr_t reserved_9 : 1; + mmr_t trigger4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t trigger4_chiplet_sel : 3; + mmr_t reserved_7 : 1; + mmr_t trigger3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t trigger3_chiplet_sel : 3; + mmr_t reserved_5 : 1; + mmr_t trigger2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t trigger2_chiplet_sel : 3; + mmr_t reserved_3 : 1; + mmr_t trigger1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t trigger1_chiplet_sel : 3; + mmr_t reserved_1 : 1; + mmr_t trigger0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t trigger0_chiplet_sel : 3; + } sh_lb_debug_trig_sel_s; +} sh_lb_debug_trig_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_DETAIL_1" */ +/* LB Error capture information: HDR1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_error_detail_1_u { + mmr_t sh_lb_error_detail_1_regval; + struct { + mmr_t command : 8; + mmr_t suppl : 14; + mmr_t reserved_0 : 2; + mmr_t source : 14; + mmr_t reserved_1 : 2; + mmr_t dest : 3; + mmr_t reserved_2 : 5; + mmr_t hdr_err : 1; + mmr_t data_err : 1; + mmr_t reserved_3 : 13; + mmr_t valid : 1; + } sh_lb_error_detail_1_s; +} sh_lb_error_detail_1_u_t; +#else +typedef union sh_lb_error_detail_1_u { + mmr_t sh_lb_error_detail_1_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_3 : 13; + mmr_t data_err : 1; + mmr_t hdr_err : 1; + mmr_t reserved_2 : 5; + mmr_t dest : 3; + mmr_t reserved_1 : 2; + mmr_t source : 14; + mmr_t reserved_0 : 2; + mmr_t suppl : 14; + mmr_t command : 8; + } sh_lb_error_detail_1_s; +} sh_lb_error_detail_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_DETAIL_2" */ +/* LB Error Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_error_detail_2_u { + mmr_t sh_lb_error_detail_2_regval; + struct { + mmr_t address : 47; + mmr_t reserved_0 : 17; + } sh_lb_error_detail_2_s; +} sh_lb_error_detail_2_u_t; +#else +typedef union sh_lb_error_detail_2_u { + mmr_t sh_lb_error_detail_2_regval; + struct { + mmr_t reserved_0 : 17; + mmr_t address : 47; + } sh_lb_error_detail_2_s; +} sh_lb_error_detail_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_DETAIL_3" */ +/* LB Error Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_error_detail_3_u { + mmr_t sh_lb_error_detail_3_regval; + struct { + mmr_t data : 64; + } sh_lb_error_detail_3_s; +} sh_lb_error_detail_3_u_t; +#else +typedef union sh_lb_error_detail_3_u { + mmr_t sh_lb_error_detail_3_regval; + struct { + mmr_t data : 64; + } sh_lb_error_detail_3_s; +} sh_lb_error_detail_3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_DETAIL_4" */ +/* LB Error Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_error_detail_4_u { + mmr_t sh_lb_error_detail_4_regval; + struct { + mmr_t route : 64; + } sh_lb_error_detail_4_s; +} sh_lb_error_detail_4_u_t; +#else +typedef union sh_lb_error_detail_4_u { + mmr_t sh_lb_error_detail_4_regval; + struct { + mmr_t route : 64; + } sh_lb_error_detail_4_s; +} sh_lb_error_detail_4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_DETAIL_5" */ +/* LB Error Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_error_detail_5_u { + mmr_t sh_lb_error_detail_5_regval; + struct { + mmr_t read_retry : 1; + mmr_t ptc1_write : 1; + mmr_t write_retry : 1; + mmr_t count_a_overflow : 1; + mmr_t count_b_overflow : 1; + mmr_t nack_a_timeout : 1; + mmr_t nack_b_timeout : 1; + mmr_t reserved_0 : 57; + } sh_lb_error_detail_5_s; +} sh_lb_error_detail_5_u_t; +#else +typedef union sh_lb_error_detail_5_u { + mmr_t sh_lb_error_detail_5_regval; + struct { + mmr_t reserved_0 : 57; + mmr_t nack_b_timeout : 1; + mmr_t nack_a_timeout : 1; + mmr_t count_b_overflow : 1; + mmr_t count_a_overflow : 1; + mmr_t write_retry : 1; + mmr_t ptc1_write : 1; + mmr_t read_retry : 1; + } sh_lb_error_detail_5_s; +} sh_lb_error_detail_5_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_MASK" */ +/* LB Error Mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_error_mask_u { + mmr_t sh_lb_error_mask_regval; + struct { + mmr_t rq_bad_cmd : 1; + mmr_t rp_bad_cmd : 1; + mmr_t rq_short : 1; + mmr_t rp_short : 1; + mmr_t rq_long : 1; + mmr_t rp_long : 1; + mmr_t rq_bad_data : 1; + mmr_t rp_bad_data : 1; + mmr_t rq_bad_addr : 1; + mmr_t rq_time_out : 1; + mmr_t linvv_overflow : 1; + mmr_t unexpected_linv : 1; + mmr_t ptc_1_timeout : 1; + mmr_t junk_bus_err : 1; + mmr_t pio_cb_err : 1; + mmr_t vector_rq_route_error : 1; + mmr_t vector_rp_route_error : 1; + mmr_t gclk_drop : 1; + mmr_t rq_fifo_error : 1; + mmr_t rp_fifo_error : 1; + mmr_t unexp_valid : 1; + mmr_t rq_credit_overflow : 1; + mmr_t rp_credit_overflow : 1; + mmr_t reserved_0 : 41; + } sh_lb_error_mask_s; +} sh_lb_error_mask_u_t; +#else +typedef union sh_lb_error_mask_u { + mmr_t sh_lb_error_mask_regval; + struct { + mmr_t reserved_0 : 41; + mmr_t rp_credit_overflow : 1; + mmr_t rq_credit_overflow : 1; + mmr_t unexp_valid : 1; + mmr_t rp_fifo_error : 1; + mmr_t rq_fifo_error : 1; + mmr_t gclk_drop : 1; + mmr_t vector_rp_route_error : 1; + mmr_t vector_rq_route_error : 1; + mmr_t pio_cb_err : 1; + mmr_t junk_bus_err : 1; + mmr_t ptc_1_timeout : 1; + mmr_t unexpected_linv : 1; + mmr_t linvv_overflow : 1; + mmr_t rq_time_out : 1; + mmr_t rq_bad_addr : 1; + mmr_t rp_bad_data : 1; + mmr_t rq_bad_data : 1; + mmr_t rp_long : 1; + mmr_t rq_long : 1; + mmr_t rp_short : 1; + mmr_t rq_short : 1; + mmr_t rp_bad_cmd : 1; + mmr_t rq_bad_cmd : 1; + } sh_lb_error_mask_s; +} sh_lb_error_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_OVERFLOW" */ +/* LB Error Overflow */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_error_overflow_u { + mmr_t sh_lb_error_overflow_regval; + struct { + mmr_t rq_bad_cmd_ovrfl : 1; + mmr_t rp_bad_cmd_ovrfl : 1; + mmr_t rq_short_ovrfl : 1; + mmr_t rp_short_ovrfl : 1; + mmr_t rq_long_ovrfl : 1; + mmr_t rp_long_ovrfl : 1; + mmr_t rq_bad_data_ovrfl : 1; + mmr_t rp_bad_data_ovrfl : 1; + mmr_t rq_bad_addr_ovrfl : 1; + mmr_t rq_time_out_ovrfl : 1; + mmr_t linvv_overflow_ovrfl : 1; + mmr_t unexpected_linv_ovrfl : 1; + mmr_t ptc_1_timeout_ovrfl : 1; + mmr_t junk_bus_err_ovrfl : 1; + mmr_t pio_cb_err_ovrfl : 1; + mmr_t vector_rq_route_error_ovrfl : 1; + mmr_t vector_rp_route_error_ovrfl : 1; + mmr_t gclk_drop_ovrfl : 1; + mmr_t rq_fifo_error_ovrfl : 1; + mmr_t rp_fifo_error_ovrfl : 1; + mmr_t unexp_valid_ovrfl : 1; + mmr_t rq_credit_overflow_ovrfl : 1; + mmr_t rp_credit_overflow_ovrfl : 1; + mmr_t reserved_0 : 41; + } sh_lb_error_overflow_s; +} sh_lb_error_overflow_u_t; +#else +typedef union sh_lb_error_overflow_u { + mmr_t sh_lb_error_overflow_regval; + struct { + mmr_t reserved_0 : 41; + mmr_t rp_credit_overflow_ovrfl : 1; + mmr_t rq_credit_overflow_ovrfl : 1; + mmr_t unexp_valid_ovrfl : 1; + mmr_t rp_fifo_error_ovrfl : 1; + mmr_t rq_fifo_error_ovrfl : 1; + mmr_t gclk_drop_ovrfl : 1; + mmr_t vector_rp_route_error_ovrfl : 1; + mmr_t vector_rq_route_error_ovrfl : 1; + mmr_t pio_cb_err_ovrfl : 1; + mmr_t junk_bus_err_ovrfl : 1; + mmr_t ptc_1_timeout_ovrfl : 1; + mmr_t unexpected_linv_ovrfl : 1; + mmr_t linvv_overflow_ovrfl : 1; + mmr_t rq_time_out_ovrfl : 1; + mmr_t rq_bad_addr_ovrfl : 1; + mmr_t rp_bad_data_ovrfl : 1; + mmr_t rq_bad_data_ovrfl : 1; + mmr_t rp_long_ovrfl : 1; + mmr_t rq_long_ovrfl : 1; + mmr_t rp_short_ovrfl : 1; + mmr_t rq_short_ovrfl : 1; + mmr_t rp_bad_cmd_ovrfl : 1; + mmr_t rq_bad_cmd_ovrfl : 1; + } sh_lb_error_overflow_s; +} sh_lb_error_overflow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_ERROR_SUMMARY" */ +/* LB Error Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_error_summary_u { + mmr_t sh_lb_error_summary_regval; + struct { + mmr_t rq_bad_cmd : 1; + mmr_t rp_bad_cmd : 1; + mmr_t rq_short : 1; + mmr_t rp_short : 1; + mmr_t rq_long : 1; + mmr_t rp_long : 1; + mmr_t rq_bad_data : 1; + mmr_t rp_bad_data : 1; + mmr_t rq_bad_addr : 1; + mmr_t rq_time_out : 1; + mmr_t linvv_overflow : 1; + mmr_t unexpected_linv : 1; + mmr_t ptc_1_timeout : 1; + mmr_t junk_bus_err : 1; + mmr_t pio_cb_err : 1; + mmr_t vector_rq_route_error : 1; + mmr_t vector_rp_route_error : 1; + mmr_t gclk_drop : 1; + mmr_t rq_fifo_error : 1; + mmr_t rp_fifo_error : 1; + mmr_t unexp_valid : 1; + mmr_t rq_credit_overflow : 1; + mmr_t rp_credit_overflow : 1; + mmr_t reserved_0 : 41; + } sh_lb_error_summary_s; +} sh_lb_error_summary_u_t; +#else +typedef union sh_lb_error_summary_u { + mmr_t sh_lb_error_summary_regval; + struct { + mmr_t reserved_0 : 41; + mmr_t rp_credit_overflow : 1; + mmr_t rq_credit_overflow : 1; + mmr_t unexp_valid : 1; + mmr_t rp_fifo_error : 1; + mmr_t rq_fifo_error : 1; + mmr_t gclk_drop : 1; + mmr_t vector_rp_route_error : 1; + mmr_t vector_rq_route_error : 1; + mmr_t pio_cb_err : 1; + mmr_t junk_bus_err : 1; + mmr_t ptc_1_timeout : 1; + mmr_t unexpected_linv : 1; + mmr_t linvv_overflow : 1; + mmr_t rq_time_out : 1; + mmr_t rq_bad_addr : 1; + mmr_t rp_bad_data : 1; + mmr_t rq_bad_data : 1; + mmr_t rp_long : 1; + mmr_t rq_long : 1; + mmr_t rp_short : 1; + mmr_t rq_short : 1; + mmr_t rp_bad_cmd : 1; + mmr_t rq_bad_cmd : 1; + } sh_lb_error_summary_s; +} sh_lb_error_summary_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_FIRST_ERROR" */ +/* LB First Error */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_first_error_u { + mmr_t sh_lb_first_error_regval; + struct { + mmr_t rq_bad_cmd : 1; + mmr_t rp_bad_cmd : 1; + mmr_t rq_short : 1; + mmr_t rp_short : 1; + mmr_t rq_long : 1; + mmr_t rp_long : 1; + mmr_t rq_bad_data : 1; + mmr_t rp_bad_data : 1; + mmr_t rq_bad_addr : 1; + mmr_t rq_time_out : 1; + mmr_t linvv_overflow : 1; + mmr_t unexpected_linv : 1; + mmr_t ptc_1_timeout : 1; + mmr_t junk_bus_err : 1; + mmr_t pio_cb_err : 1; + mmr_t vector_rq_route_error : 1; + mmr_t vector_rp_route_error : 1; + mmr_t gclk_drop : 1; + mmr_t rq_fifo_error : 1; + mmr_t rp_fifo_error : 1; + mmr_t unexp_valid : 1; + mmr_t rq_credit_overflow : 1; + mmr_t rp_credit_overflow : 1; + mmr_t reserved_0 : 41; + } sh_lb_first_error_s; +} sh_lb_first_error_u_t; +#else +typedef union sh_lb_first_error_u { + mmr_t sh_lb_first_error_regval; + struct { + mmr_t reserved_0 : 41; + mmr_t rp_credit_overflow : 1; + mmr_t rq_credit_overflow : 1; + mmr_t unexp_valid : 1; + mmr_t rp_fifo_error : 1; + mmr_t rq_fifo_error : 1; + mmr_t gclk_drop : 1; + mmr_t vector_rp_route_error : 1; + mmr_t vector_rq_route_error : 1; + mmr_t pio_cb_err : 1; + mmr_t junk_bus_err : 1; + mmr_t ptc_1_timeout : 1; + mmr_t unexpected_linv : 1; + mmr_t linvv_overflow : 1; + mmr_t rq_time_out : 1; + mmr_t rq_bad_addr : 1; + mmr_t rp_bad_data : 1; + mmr_t rq_bad_data : 1; + mmr_t rp_long : 1; + mmr_t rq_long : 1; + mmr_t rp_short : 1; + mmr_t rq_short : 1; + mmr_t rp_bad_cmd : 1; + mmr_t rq_bad_cmd : 1; + } sh_lb_first_error_s; +} sh_lb_first_error_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_LAST_CREDIT" */ +/* Credit counter status register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_last_credit_u { + mmr_t sh_lb_last_credit_regval; + struct { + mmr_t liq_rq_credit : 5; + mmr_t reserved_0 : 1; + mmr_t liq_rp_credit : 4; + mmr_t reserved_1 : 2; + mmr_t linvv_credit : 6; + mmr_t loq_rq_credit : 5; + mmr_t loq_rp_credit : 5; + mmr_t reserved_2 : 36; + } sh_lb_last_credit_s; +} sh_lb_last_credit_u_t; +#else +typedef union sh_lb_last_credit_u { + mmr_t sh_lb_last_credit_regval; + struct { + mmr_t reserved_2 : 36; + mmr_t loq_rp_credit : 5; + mmr_t loq_rq_credit : 5; + mmr_t linvv_credit : 6; + mmr_t reserved_1 : 2; + mmr_t liq_rp_credit : 4; + mmr_t reserved_0 : 1; + mmr_t liq_rq_credit : 5; + } sh_lb_last_credit_s; +} sh_lb_last_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_NACK_STATUS" */ +/* Nack Counter Status Register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_nack_status_u { + mmr_t sh_lb_nack_status_regval; + struct { + mmr_t pio_nack_a : 12; + mmr_t reserved_0 : 4; + mmr_t pio_nack_b : 12; + mmr_t reserved_1 : 4; + mmr_t junk_nack : 16; + mmr_t cb_timeout_count : 12; + mmr_t cb_state : 2; + mmr_t reserved_2 : 2; + } sh_lb_nack_status_s; +} sh_lb_nack_status_u_t; +#else +typedef union sh_lb_nack_status_u { + mmr_t sh_lb_nack_status_regval; + struct { + mmr_t reserved_2 : 2; + mmr_t cb_state : 2; + mmr_t cb_timeout_count : 12; + mmr_t junk_nack : 16; + mmr_t reserved_1 : 4; + mmr_t pio_nack_b : 12; + mmr_t reserved_0 : 4; + mmr_t pio_nack_a : 12; + } sh_lb_nack_status_s; +} sh_lb_nack_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_TRIGGER_COMPARE" */ +/* LB Test-point Trigger Compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_trigger_compare_u { + mmr_t sh_lb_trigger_compare_regval; + struct { + mmr_t mask : 32; + mmr_t reserved_0 : 32; + } sh_lb_trigger_compare_s; +} sh_lb_trigger_compare_u_t; +#else +typedef union sh_lb_trigger_compare_u { + mmr_t sh_lb_trigger_compare_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t mask : 32; + } sh_lb_trigger_compare_s; +} sh_lb_trigger_compare_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_TRIGGER_DATA" */ +/* LB Test-point Trigger Compare Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_trigger_data_u { + mmr_t sh_lb_trigger_data_regval; + struct { + mmr_t compare_pattern : 32; + mmr_t reserved_0 : 32; + } sh_lb_trigger_data_s; +} sh_lb_trigger_data_u_t; +#else +typedef union sh_lb_trigger_data_u { + mmr_t sh_lb_trigger_data_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t compare_pattern : 32; + } sh_lb_trigger_data_s; +} sh_lb_trigger_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_AEC_CONFIG" */ +/* PI Adaptive Error Correction Configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_aec_config_u { + mmr_t sh_pi_aec_config_regval; + struct { + mmr_t mode : 3; + mmr_t reserved_0 : 61; + } sh_pi_aec_config_s; +} sh_pi_aec_config_u_t; +#else +typedef union sh_pi_aec_config_u { + mmr_t sh_pi_aec_config_regval; + struct { + mmr_t reserved_0 : 61; + mmr_t mode : 3; + } sh_pi_aec_config_s; +} sh_pi_aec_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_AFI_ERROR_MASK" */ +/* PI AFI Error Mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_afi_error_mask_u { + mmr_t sh_pi_afi_error_mask_regval; + struct { + mmr_t reserved_0 : 21; + mmr_t hung_bus : 1; + mmr_t rsp_parity : 1; + mmr_t ioq_overrun : 1; + mmr_t req_format : 1; + mmr_t addr_access : 1; + mmr_t req_parity : 1; + mmr_t addr_parity : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_ce : 1; + mmr_t livelock : 1; + mmr_t bad_snoop : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t msg_len : 1; + mmr_t reserved_1 : 29; + } sh_pi_afi_error_mask_s; +} sh_pi_afi_error_mask_u_t; +#else +typedef union sh_pi_afi_error_mask_u { + mmr_t sh_pi_afi_error_mask_regval; + struct { + mmr_t reserved_1 : 29; + mmr_t msg_len : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t bad_snoop : 1; + mmr_t livelock : 1; + mmr_t shub_fsb_ce : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t addr_parity : 1; + mmr_t req_parity : 1; + mmr_t addr_access : 1; + mmr_t req_format : 1; + mmr_t ioq_overrun : 1; + mmr_t rsp_parity : 1; + mmr_t hung_bus : 1; + mmr_t reserved_0 : 21; + } sh_pi_afi_error_mask_s; +} sh_pi_afi_error_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_AFI_TEST_POINT_COMPARE" */ +/* PI AFI Test Point Compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_afi_test_point_compare_u { + mmr_t sh_pi_afi_test_point_compare_regval; + struct { + mmr_t compare_mask : 32; + mmr_t compare_pattern : 32; + } sh_pi_afi_test_point_compare_s; +} sh_pi_afi_test_point_compare_u_t; +#else +typedef union sh_pi_afi_test_point_compare_u { + mmr_t sh_pi_afi_test_point_compare_regval; + struct { + mmr_t compare_pattern : 32; + mmr_t compare_mask : 32; + } sh_pi_afi_test_point_compare_s; +} sh_pi_afi_test_point_compare_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_AFI_TEST_POINT_SELECT" */ +/* PI AFI Test Point Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_afi_test_point_select_u { + mmr_t sh_pi_afi_test_point_select_regval; + struct { + mmr_t nibble0_chiplet_sel : 4; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble1_chiplet_sel : 4; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble2_chiplet_sel : 4; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble3_chiplet_sel : 4; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble4_chiplet_sel : 4; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble5_chiplet_sel : 4; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble6_chiplet_sel : 4; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble7_chiplet_sel : 4; + mmr_t nibble7_nibble_sel : 3; + mmr_t trigger_enable : 1; + } sh_pi_afi_test_point_select_s; +} sh_pi_afi_test_point_select_u_t; +#else +typedef union sh_pi_afi_test_point_select_u { + mmr_t sh_pi_afi_test_point_select_regval; + struct { + mmr_t trigger_enable : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t nibble7_chiplet_sel : 4; + mmr_t reserved_6 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t nibble6_chiplet_sel : 4; + mmr_t reserved_5 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t nibble5_chiplet_sel : 4; + mmr_t reserved_4 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t nibble4_chiplet_sel : 4; + mmr_t reserved_3 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t nibble3_chiplet_sel : 4; + mmr_t reserved_2 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t nibble2_chiplet_sel : 4; + mmr_t reserved_1 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t nibble1_chiplet_sel : 4; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t nibble0_chiplet_sel : 4; + } sh_pi_afi_test_point_select_s; +} sh_pi_afi_test_point_select_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT" */ +/* PI CRBC Test Point Trigger Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_afi_test_point_trigger_select_u { + mmr_t sh_pi_afi_test_point_trigger_select_regval; + struct { + mmr_t trigger0_chiplet_sel : 4; + mmr_t trigger0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t trigger1_chiplet_sel : 4; + mmr_t trigger1_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t trigger2_chiplet_sel : 4; + mmr_t trigger2_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t trigger3_chiplet_sel : 4; + mmr_t trigger3_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t trigger4_chiplet_sel : 4; + mmr_t trigger4_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t trigger5_chiplet_sel : 4; + mmr_t trigger5_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t trigger6_chiplet_sel : 4; + mmr_t trigger6_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t trigger7_chiplet_sel : 4; + mmr_t trigger7_nibble_sel : 3; + mmr_t reserved_7 : 1; + } sh_pi_afi_test_point_trigger_select_s; +} sh_pi_afi_test_point_trigger_select_u_t; +#else +typedef union sh_pi_afi_test_point_trigger_select_u { + mmr_t sh_pi_afi_test_point_trigger_select_regval; + struct { + mmr_t reserved_7 : 1; + mmr_t trigger7_nibble_sel : 3; + mmr_t trigger7_chiplet_sel : 4; + mmr_t reserved_6 : 1; + mmr_t trigger6_nibble_sel : 3; + mmr_t trigger6_chiplet_sel : 4; + mmr_t reserved_5 : 1; + mmr_t trigger5_nibble_sel : 3; + mmr_t trigger5_chiplet_sel : 4; + mmr_t reserved_4 : 1; + mmr_t trigger4_nibble_sel : 3; + mmr_t trigger4_chiplet_sel : 4; + mmr_t reserved_3 : 1; + mmr_t trigger3_nibble_sel : 3; + mmr_t trigger3_chiplet_sel : 4; + mmr_t reserved_2 : 1; + mmr_t trigger2_nibble_sel : 3; + mmr_t trigger2_chiplet_sel : 4; + mmr_t reserved_1 : 1; + mmr_t trigger1_nibble_sel : 3; + mmr_t trigger1_chiplet_sel : 4; + mmr_t reserved_0 : 1; + mmr_t trigger0_nibble_sel : 3; + mmr_t trigger0_chiplet_sel : 4; + } sh_pi_afi_test_point_trigger_select_s; +} sh_pi_afi_test_point_trigger_select_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_AUTO_REPLY_ENABLE" */ +/* PI Auto Reply Enable */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_auto_reply_enable_u { + mmr_t sh_pi_auto_reply_enable_regval; + struct { + mmr_t auto_reply_enable : 1; + mmr_t reserved_0 : 63; + } sh_pi_auto_reply_enable_s; +} sh_pi_auto_reply_enable_u_t; +#else +typedef union sh_pi_auto_reply_enable_u { + mmr_t sh_pi_auto_reply_enable_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t auto_reply_enable : 1; + } sh_pi_auto_reply_enable_s; +} sh_pi_auto_reply_enable_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CAM_CONTROL" */ +/* CRB CAM MMR Access Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_cam_control_u { + mmr_t sh_pi_cam_control_regval; + struct { + mmr_t cam_indx : 7; + mmr_t reserved_0 : 1; + mmr_t cam_write : 1; + mmr_t rrb_rd_xfer_clear : 1; + mmr_t reserved_1 : 53; + mmr_t start : 1; + } sh_pi_cam_control_s; +} sh_pi_cam_control_u_t; +#else +typedef union sh_pi_cam_control_u { + mmr_t sh_pi_cam_control_regval; + struct { + mmr_t start : 1; + mmr_t reserved_1 : 53; + mmr_t rrb_rd_xfer_clear : 1; + mmr_t cam_write : 1; + mmr_t reserved_0 : 1; + mmr_t cam_indx : 7; + } sh_pi_cam_control_s; +} sh_pi_cam_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBC_TEST_POINT_COMPARE" */ +/* PI CRBC Test Point Compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbc_test_point_compare_u { + mmr_t sh_pi_crbc_test_point_compare_regval; + struct { + mmr_t compare_mask : 32; + mmr_t compare_pattern : 32; + } sh_pi_crbc_test_point_compare_s; +} sh_pi_crbc_test_point_compare_u_t; +#else +typedef union sh_pi_crbc_test_point_compare_u { + mmr_t sh_pi_crbc_test_point_compare_regval; + struct { + mmr_t compare_pattern : 32; + mmr_t compare_mask : 32; + } sh_pi_crbc_test_point_compare_s; +} sh_pi_crbc_test_point_compare_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBC_TEST_POINT_SELECT" */ +/* PI CRBC Test Point Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbc_test_point_select_u { + mmr_t sh_pi_crbc_test_point_select_regval; + struct { + mmr_t nibble0_chiplet_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_chiplet_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_chiplet_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_chiplet_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_chiplet_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_chiplet_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_chiplet_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_chiplet_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t trigger_enable : 1; + } sh_pi_crbc_test_point_select_s; +} sh_pi_crbc_test_point_select_u_t; +#else +typedef union sh_pi_crbc_test_point_select_u { + mmr_t sh_pi_crbc_test_point_select_regval; + struct { + mmr_t trigger_enable : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_chiplet_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_chiplet_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_chiplet_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_chiplet_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_chiplet_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_chiplet_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_chiplet_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_chiplet_sel : 3; + } sh_pi_crbc_test_point_select_s; +} sh_pi_crbc_test_point_select_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT" */ +/* PI CRBC Test Point Trigger Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbc_test_point_trigger_select_u { + mmr_t sh_pi_crbc_test_point_trigger_select_regval; + struct { + mmr_t trigger0_chiplet_sel : 3; + mmr_t reserved_0 : 1; + mmr_t trigger0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t trigger1_chiplet_sel : 3; + mmr_t reserved_2 : 1; + mmr_t trigger1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t trigger2_chiplet_sel : 3; + mmr_t reserved_4 : 1; + mmr_t trigger2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t trigger3_chiplet_sel : 3; + mmr_t reserved_6 : 1; + mmr_t trigger3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t trigger4_chiplet_sel : 3; + mmr_t reserved_8 : 1; + mmr_t trigger4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t trigger5_chiplet_sel : 3; + mmr_t reserved_10 : 1; + mmr_t trigger5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t trigger6_chiplet_sel : 3; + mmr_t reserved_12 : 1; + mmr_t trigger6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t trigger7_chiplet_sel : 3; + mmr_t reserved_14 : 1; + mmr_t trigger7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_pi_crbc_test_point_trigger_select_s; +} sh_pi_crbc_test_point_trigger_select_u_t; +#else +typedef union sh_pi_crbc_test_point_trigger_select_u { + mmr_t sh_pi_crbc_test_point_trigger_select_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t trigger7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t trigger7_chiplet_sel : 3; + mmr_t reserved_13 : 1; + mmr_t trigger6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t trigger6_chiplet_sel : 3; + mmr_t reserved_11 : 1; + mmr_t trigger5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t trigger5_chiplet_sel : 3; + mmr_t reserved_9 : 1; + mmr_t trigger4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t trigger4_chiplet_sel : 3; + mmr_t reserved_7 : 1; + mmr_t trigger3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t trigger3_chiplet_sel : 3; + mmr_t reserved_5 : 1; + mmr_t trigger2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t trigger2_chiplet_sel : 3; + mmr_t reserved_3 : 1; + mmr_t trigger1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t trigger1_chiplet_sel : 3; + mmr_t reserved_1 : 1; + mmr_t trigger0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t trigger0_chiplet_sel : 3; + } sh_pi_crbc_test_point_trigger_select_s; +} sh_pi_crbc_test_point_trigger_select_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_ERROR_MASK" */ +/* PI CRBP Error Mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbp_error_mask_u { + mmr_t sh_pi_crbp_error_mask_regval; + struct { + mmr_t fsb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t mem_rp_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_to_err : 1; + mmr_t fsb_shub_uce : 1; + mmr_t fsb_shub_ce : 1; + mmr_t msg_color_err : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t nack_oflow : 1; + mmr_t gfx_int_0 : 1; + mmr_t gfx_int_1 : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t xn_rp_crd_oflow : 1; + mmr_t reserved_0 : 43; + } sh_pi_crbp_error_mask_s; +} sh_pi_crbp_error_mask_u_t; +#else +typedef union sh_pi_crbp_error_mask_u { + mmr_t sh_pi_crbp_error_mask_regval; + struct { + mmr_t reserved_0 : 43; + mmr_t xn_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t gfx_int_1 : 1; + mmr_t gfx_int_0 : 1; + mmr_t nack_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t msg_color_err : 1; + mmr_t fsb_shub_ce : 1; + mmr_t fsb_shub_uce : 1; + mmr_t pio_to_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t fsb_proto_err : 1; + } sh_pi_crbp_error_mask_s; +} sh_pi_crbp_error_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_FSB_PIPE_COMPARE" */ +/* CRBP FSB Pipe Compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbp_fsb_pipe_compare_u { + mmr_t sh_pi_crbp_fsb_pipe_compare_regval; + struct { + mmr_t compare_address : 47; + mmr_t compare_req : 6; + mmr_t reserved_0 : 11; + } sh_pi_crbp_fsb_pipe_compare_s; +} sh_pi_crbp_fsb_pipe_compare_u_t; +#else +typedef union sh_pi_crbp_fsb_pipe_compare_u { + mmr_t sh_pi_crbp_fsb_pipe_compare_regval; + struct { + mmr_t reserved_0 : 11; + mmr_t compare_req : 6; + mmr_t compare_address : 47; + } sh_pi_crbp_fsb_pipe_compare_s; +} sh_pi_crbp_fsb_pipe_compare_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_FSB_PIPE_MASK" */ +/* CRBP Compare Mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbp_fsb_pipe_mask_u { + mmr_t sh_pi_crbp_fsb_pipe_mask_regval; + struct { + mmr_t compare_address_mask : 47; + mmr_t compare_req_mask : 6; + mmr_t reserved_0 : 11; + } sh_pi_crbp_fsb_pipe_mask_s; +} sh_pi_crbp_fsb_pipe_mask_u_t; +#else +typedef union sh_pi_crbp_fsb_pipe_mask_u { + mmr_t sh_pi_crbp_fsb_pipe_mask_regval; + struct { + mmr_t reserved_0 : 11; + mmr_t compare_req_mask : 6; + mmr_t compare_address_mask : 47; + } sh_pi_crbp_fsb_pipe_mask_s; +} sh_pi_crbp_fsb_pipe_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_TEST_POINT_COMPARE" */ +/* PI CRBP Test Point Compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbp_test_point_compare_u { + mmr_t sh_pi_crbp_test_point_compare_regval; + struct { + mmr_t compare_mask : 32; + mmr_t compare_pattern : 32; + } sh_pi_crbp_test_point_compare_s; +} sh_pi_crbp_test_point_compare_u_t; +#else +typedef union sh_pi_crbp_test_point_compare_u { + mmr_t sh_pi_crbp_test_point_compare_regval; + struct { + mmr_t compare_pattern : 32; + mmr_t compare_mask : 32; + } sh_pi_crbp_test_point_compare_s; +} sh_pi_crbp_test_point_compare_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_TEST_POINT_SELECT" */ +/* PI CRBP Test Point Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbp_test_point_select_u { + mmr_t sh_pi_crbp_test_point_select_regval; + struct { + mmr_t nibble0_chiplet_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_chiplet_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_chiplet_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_chiplet_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_chiplet_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_chiplet_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_chiplet_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_chiplet_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t trigger_enable : 1; + } sh_pi_crbp_test_point_select_s; +} sh_pi_crbp_test_point_select_u_t; +#else +typedef union sh_pi_crbp_test_point_select_u { + mmr_t sh_pi_crbp_test_point_select_regval; + struct { + mmr_t trigger_enable : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_chiplet_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_chiplet_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_chiplet_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_chiplet_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_chiplet_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_chiplet_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_chiplet_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_chiplet_sel : 3; + } sh_pi_crbp_test_point_select_s; +} sh_pi_crbp_test_point_select_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT" */ +/* PI CRBP Test Point Trigger Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbp_test_point_trigger_select_u { + mmr_t sh_pi_crbp_test_point_trigger_select_regval; + struct { + mmr_t trigger0_chiplet_sel : 3; + mmr_t reserved_0 : 1; + mmr_t trigger0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t trigger1_chiplet_sel : 3; + mmr_t reserved_2 : 1; + mmr_t trigger1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t trigger2_chiplet_sel : 3; + mmr_t reserved_4 : 1; + mmr_t trigger2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t trigger3_chiplet_sel : 3; + mmr_t reserved_6 : 1; + mmr_t trigger3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t trigger4_chiplet_sel : 3; + mmr_t reserved_8 : 1; + mmr_t trigger4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t trigger5_chiplet_sel : 3; + mmr_t reserved_10 : 1; + mmr_t trigger5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t trigger6_chiplet_sel : 3; + mmr_t reserved_12 : 1; + mmr_t trigger6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t trigger7_chiplet_sel : 3; + mmr_t reserved_14 : 1; + mmr_t trigger7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_pi_crbp_test_point_trigger_select_s; +} sh_pi_crbp_test_point_trigger_select_u_t; +#else +typedef union sh_pi_crbp_test_point_trigger_select_u { + mmr_t sh_pi_crbp_test_point_trigger_select_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t trigger7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t trigger7_chiplet_sel : 3; + mmr_t reserved_13 : 1; + mmr_t trigger6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t trigger6_chiplet_sel : 3; + mmr_t reserved_11 : 1; + mmr_t trigger5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t trigger5_chiplet_sel : 3; + mmr_t reserved_9 : 1; + mmr_t trigger4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t trigger4_chiplet_sel : 3; + mmr_t reserved_7 : 1; + mmr_t trigger3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t trigger3_chiplet_sel : 3; + mmr_t reserved_5 : 1; + mmr_t trigger2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t trigger2_chiplet_sel : 3; + mmr_t reserved_3 : 1; + mmr_t trigger1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t trigger1_chiplet_sel : 3; + mmr_t reserved_1 : 1; + mmr_t trigger0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t trigger0_chiplet_sel : 3; + } sh_pi_crbp_test_point_trigger_select_s; +} sh_pi_crbp_test_point_trigger_select_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_XB_PIPE_COMPARE_0" */ +/* CRBP XB Pipe Compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbp_xb_pipe_compare_0_u { + mmr_t sh_pi_crbp_xb_pipe_compare_0_regval; + struct { + mmr_t compare_address : 47; + mmr_t compare_command : 8; + mmr_t reserved_0 : 9; + } sh_pi_crbp_xb_pipe_compare_0_s; +} sh_pi_crbp_xb_pipe_compare_0_u_t; +#else +typedef union sh_pi_crbp_xb_pipe_compare_0_u { + mmr_t sh_pi_crbp_xb_pipe_compare_0_regval; + struct { + mmr_t reserved_0 : 9; + mmr_t compare_command : 8; + mmr_t compare_address : 47; + } sh_pi_crbp_xb_pipe_compare_0_s; +} sh_pi_crbp_xb_pipe_compare_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_XB_PIPE_COMPARE_1" */ +/* CRBP XB Pipe Compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbp_xb_pipe_compare_1_u { + mmr_t sh_pi_crbp_xb_pipe_compare_1_regval; + struct { + mmr_t compare_source : 14; + mmr_t reserved_0 : 2; + mmr_t compare_supplemental : 14; + mmr_t reserved_1 : 2; + mmr_t compare_echo : 9; + mmr_t reserved_2 : 23; + } sh_pi_crbp_xb_pipe_compare_1_s; +} sh_pi_crbp_xb_pipe_compare_1_u_t; +#else +typedef union sh_pi_crbp_xb_pipe_compare_1_u { + mmr_t sh_pi_crbp_xb_pipe_compare_1_regval; + struct { + mmr_t reserved_2 : 23; + mmr_t compare_echo : 9; + mmr_t reserved_1 : 2; + mmr_t compare_supplemental : 14; + mmr_t reserved_0 : 2; + mmr_t compare_source : 14; + } sh_pi_crbp_xb_pipe_compare_1_s; +} sh_pi_crbp_xb_pipe_compare_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_XB_PIPE_MASK_0" */ +/* CRBP Compare Mask Register 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbp_xb_pipe_mask_0_u { + mmr_t sh_pi_crbp_xb_pipe_mask_0_regval; + struct { + mmr_t compare_address_mask : 47; + mmr_t compare_command_mask : 8; + mmr_t reserved_0 : 9; + } sh_pi_crbp_xb_pipe_mask_0_s; +} sh_pi_crbp_xb_pipe_mask_0_u_t; +#else +typedef union sh_pi_crbp_xb_pipe_mask_0_u { + mmr_t sh_pi_crbp_xb_pipe_mask_0_regval; + struct { + mmr_t reserved_0 : 9; + mmr_t compare_command_mask : 8; + mmr_t compare_address_mask : 47; + } sh_pi_crbp_xb_pipe_mask_0_s; +} sh_pi_crbp_xb_pipe_mask_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_XB_PIPE_MASK_1" */ +/* CRBP XB Pipe Compare Mask Register 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbp_xb_pipe_mask_1_u { + mmr_t sh_pi_crbp_xb_pipe_mask_1_regval; + struct { + mmr_t compare_source_mask : 14; + mmr_t reserved_0 : 2; + mmr_t compare_supplemental_mask : 14; + mmr_t reserved_1 : 2; + mmr_t compare_echo_mask : 9; + mmr_t reserved_2 : 23; + } sh_pi_crbp_xb_pipe_mask_1_s; +} sh_pi_crbp_xb_pipe_mask_1_u_t; +#else +typedef union sh_pi_crbp_xb_pipe_mask_1_u { + mmr_t sh_pi_crbp_xb_pipe_mask_1_regval; + struct { + mmr_t reserved_2 : 23; + mmr_t compare_echo_mask : 9; + mmr_t reserved_1 : 2; + mmr_t compare_supplemental_mask : 14; + mmr_t reserved_0 : 2; + mmr_t compare_source_mask : 14; + } sh_pi_crbp_xb_pipe_mask_1_s; +} sh_pi_crbp_xb_pipe_mask_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_DPC_QUEUE_CONFIG" */ +/* DPC Queue Configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_dpc_queue_config_u { + mmr_t sh_pi_dpc_queue_config_regval; + struct { + mmr_t dwcq_ae_level : 5; + mmr_t reserved_0 : 3; + mmr_t dwcq_af_thresh : 5; + mmr_t reserved_1 : 3; + mmr_t fwcq_ae_level : 5; + mmr_t reserved_2 : 3; + mmr_t fwcq_af_thresh : 5; + mmr_t reserved_3 : 35; + } sh_pi_dpc_queue_config_s; +} sh_pi_dpc_queue_config_u_t; +#else +typedef union sh_pi_dpc_queue_config_u { + mmr_t sh_pi_dpc_queue_config_regval; + struct { + mmr_t reserved_3 : 35; + mmr_t fwcq_af_thresh : 5; + mmr_t reserved_2 : 3; + mmr_t fwcq_ae_level : 5; + mmr_t reserved_1 : 3; + mmr_t dwcq_af_thresh : 5; + mmr_t reserved_0 : 3; + mmr_t dwcq_ae_level : 5; + } sh_pi_dpc_queue_config_s; +} sh_pi_dpc_queue_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_MASK" */ +/* PI Error Mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_error_mask_u { + mmr_t sh_pi_error_mask_regval; + struct { + mmr_t fsb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t mem_rp_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_to_err : 1; + mmr_t fsb_shub_uce : 1; + mmr_t fsb_shub_ce : 1; + mmr_t msg_color_err : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t nack_oflow : 1; + mmr_t gfx_int_0 : 1; + mmr_t gfx_int_1 : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t xn_rp_crd_oflow : 1; + mmr_t hung_bus : 1; + mmr_t rsp_parity : 1; + mmr_t ioq_overrun : 1; + mmr_t req_format : 1; + mmr_t addr_access : 1; + mmr_t req_parity : 1; + mmr_t addr_parity : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_ce : 1; + mmr_t livelock : 1; + mmr_t bad_snoop : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t msg_length : 1; + mmr_t reserved_0 : 29; + } sh_pi_error_mask_s; +} sh_pi_error_mask_u_t; +#else +typedef union sh_pi_error_mask_u { + mmr_t sh_pi_error_mask_regval; + struct { + mmr_t reserved_0 : 29; + mmr_t msg_length : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t bad_snoop : 1; + mmr_t livelock : 1; + mmr_t shub_fsb_ce : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t addr_parity : 1; + mmr_t req_parity : 1; + mmr_t addr_access : 1; + mmr_t req_format : 1; + mmr_t ioq_overrun : 1; + mmr_t rsp_parity : 1; + mmr_t hung_bus : 1; + mmr_t xn_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t gfx_int_1 : 1; + mmr_t gfx_int_0 : 1; + mmr_t nack_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t msg_color_err : 1; + mmr_t fsb_shub_ce : 1; + mmr_t fsb_shub_uce : 1; + mmr_t pio_to_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t fsb_proto_err : 1; + } sh_pi_error_mask_s; +} sh_pi_error_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_EXPRESS_REPLY_CONFIG" */ +/* PI Express Reply Configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_express_reply_config_u { + mmr_t sh_pi_express_reply_config_regval; + struct { + mmr_t mode : 3; + mmr_t reserved_0 : 61; + } sh_pi_express_reply_config_s; +} sh_pi_express_reply_config_u_t; +#else +typedef union sh_pi_express_reply_config_u { + mmr_t sh_pi_express_reply_config_regval; + struct { + mmr_t reserved_0 : 61; + mmr_t mode : 3; + } sh_pi_express_reply_config_s; +} sh_pi_express_reply_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_FSB_COMPARE_VALUE" */ +/* FSB Compare Value */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_fsb_compare_value_u { + mmr_t sh_pi_fsb_compare_value_regval; + struct { + mmr_t compare_value : 64; + } sh_pi_fsb_compare_value_s; +} sh_pi_fsb_compare_value_u_t; +#else +typedef union sh_pi_fsb_compare_value_u { + mmr_t sh_pi_fsb_compare_value_regval; + struct { + mmr_t compare_value : 64; + } sh_pi_fsb_compare_value_s; +} sh_pi_fsb_compare_value_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_FSB_COMPARE_MASK" */ +/* FSB Compare Mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_fsb_compare_mask_u { + mmr_t sh_pi_fsb_compare_mask_regval; + struct { + mmr_t mask_value : 64; + } sh_pi_fsb_compare_mask_s; +} sh_pi_fsb_compare_mask_u_t; +#else +typedef union sh_pi_fsb_compare_mask_u { + mmr_t sh_pi_fsb_compare_mask_regval; + struct { + mmr_t mask_value : 64; + } sh_pi_fsb_compare_mask_s; +} sh_pi_fsb_compare_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_FSB_ERROR_INJECTION" */ +/* Inject an Error onto the FSB */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_fsb_error_injection_u { + mmr_t sh_pi_fsb_error_injection_regval; + struct { + mmr_t rp_pe_to_fsb : 1; + mmr_t ap0_pe_to_fsb : 1; + mmr_t ap1_pe_to_fsb : 1; + mmr_t rsp_pe_to_fsb : 1; + mmr_t dw0_ce_to_fsb : 1; + mmr_t dw0_uce_to_fsb : 1; + mmr_t dw1_ce_to_fsb : 1; + mmr_t dw1_uce_to_fsb : 1; + mmr_t ip0_pe_to_fsb : 1; + mmr_t ip1_pe_to_fsb : 1; + mmr_t reserved_0 : 6; + mmr_t rp_pe_from_fsb : 1; + mmr_t ap0_pe_from_fsb : 1; + mmr_t ap1_pe_from_fsb : 1; + mmr_t rsp_pe_from_fsb : 1; + mmr_t dw0_ce_from_fsb : 1; + mmr_t dw0_uce_from_fsb : 1; + mmr_t dw1_ce_from_fsb : 1; + mmr_t dw1_uce_from_fsb : 1; + mmr_t dw2_ce_from_fsb : 1; + mmr_t dw2_uce_from_fsb : 1; + mmr_t dw3_ce_from_fsb : 1; + mmr_t dw3_uce_from_fsb : 1; + mmr_t reserved_1 : 4; + mmr_t ioq_overrun : 1; + mmr_t livelock : 1; + mmr_t bus_hang : 1; + mmr_t reserved_2 : 29; + } sh_pi_fsb_error_injection_s; +} sh_pi_fsb_error_injection_u_t; +#else +typedef union sh_pi_fsb_error_injection_u { + mmr_t sh_pi_fsb_error_injection_regval; + struct { + mmr_t reserved_2 : 29; + mmr_t bus_hang : 1; + mmr_t livelock : 1; + mmr_t ioq_overrun : 1; + mmr_t reserved_1 : 4; + mmr_t dw3_uce_from_fsb : 1; + mmr_t dw3_ce_from_fsb : 1; + mmr_t dw2_uce_from_fsb : 1; + mmr_t dw2_ce_from_fsb : 1; + mmr_t dw1_uce_from_fsb : 1; + mmr_t dw1_ce_from_fsb : 1; + mmr_t dw0_uce_from_fsb : 1; + mmr_t dw0_ce_from_fsb : 1; + mmr_t rsp_pe_from_fsb : 1; + mmr_t ap1_pe_from_fsb : 1; + mmr_t ap0_pe_from_fsb : 1; + mmr_t rp_pe_from_fsb : 1; + mmr_t reserved_0 : 6; + mmr_t ip1_pe_to_fsb : 1; + mmr_t ip0_pe_to_fsb : 1; + mmr_t dw1_uce_to_fsb : 1; + mmr_t dw1_ce_to_fsb : 1; + mmr_t dw0_uce_to_fsb : 1; + mmr_t dw0_ce_to_fsb : 1; + mmr_t rsp_pe_to_fsb : 1; + mmr_t ap1_pe_to_fsb : 1; + mmr_t ap0_pe_to_fsb : 1; + mmr_t rp_pe_to_fsb : 1; + } sh_pi_fsb_error_injection_s; +} sh_pi_fsb_error_injection_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_MD2PI_REPLY_VC_CONFIG" */ +/* MD-to-PI Reply Virtual Channel Configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_md2pi_reply_vc_config_u { + mmr_t sh_pi_md2pi_reply_vc_config_regval; + struct { + mmr_t hdr_depth : 4; + mmr_t data_depth : 4; + mmr_t max_credits : 6; + mmr_t reserved_0 : 48; + mmr_t force_credit : 1; + mmr_t capture_credit_status : 1; + } sh_pi_md2pi_reply_vc_config_s; +} sh_pi_md2pi_reply_vc_config_u_t; +#else +typedef union sh_pi_md2pi_reply_vc_config_u { + mmr_t sh_pi_md2pi_reply_vc_config_regval; + struct { + mmr_t capture_credit_status : 1; + mmr_t force_credit : 1; + mmr_t reserved_0 : 48; + mmr_t max_credits : 6; + mmr_t data_depth : 4; + mmr_t hdr_depth : 4; + } sh_pi_md2pi_reply_vc_config_s; +} sh_pi_md2pi_reply_vc_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_MD2PI_REQUEST_VC_CONFIG" */ +/* MD-to-PI Request Virtual Channel Configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_md2pi_request_vc_config_u { + mmr_t sh_pi_md2pi_request_vc_config_regval; + struct { + mmr_t hdr_depth : 4; + mmr_t data_depth : 4; + mmr_t max_credits : 6; + mmr_t reserved_0 : 48; + mmr_t force_credit : 1; + mmr_t capture_credit_status : 1; + } sh_pi_md2pi_request_vc_config_s; +} sh_pi_md2pi_request_vc_config_u_t; +#else +typedef union sh_pi_md2pi_request_vc_config_u { + mmr_t sh_pi_md2pi_request_vc_config_regval; + struct { + mmr_t capture_credit_status : 1; + mmr_t force_credit : 1; + mmr_t reserved_0 : 48; + mmr_t max_credits : 6; + mmr_t data_depth : 4; + mmr_t hdr_depth : 4; + } sh_pi_md2pi_request_vc_config_s; +} sh_pi_md2pi_request_vc_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_QUEUE_ERROR_INJECTION" */ +/* PI Queue Error Injection */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_queue_error_injection_u { + mmr_t sh_pi_queue_error_injection_regval; + struct { + mmr_t dat_dfr_q : 1; + mmr_t dxb_wtl_cmnd_q : 1; + mmr_t fsb_wtl_cmnd_q : 1; + mmr_t mdpi_rpy_bfr : 1; + mmr_t ptc_intr : 1; + mmr_t rxl_kill_q : 1; + mmr_t rxl_rdy_q : 1; + mmr_t xnpi_rpy_bfr : 1; + mmr_t reserved_0 : 56; + } sh_pi_queue_error_injection_s; +} sh_pi_queue_error_injection_u_t; +#else +typedef union sh_pi_queue_error_injection_u { + mmr_t sh_pi_queue_error_injection_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t xnpi_rpy_bfr : 1; + mmr_t rxl_rdy_q : 1; + mmr_t rxl_kill_q : 1; + mmr_t ptc_intr : 1; + mmr_t mdpi_rpy_bfr : 1; + mmr_t fsb_wtl_cmnd_q : 1; + mmr_t dxb_wtl_cmnd_q : 1; + mmr_t dat_dfr_q : 1; + } sh_pi_queue_error_injection_s; +} sh_pi_queue_error_injection_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_TEST_POINT_COMPARE" */ +/* PI Test Point Compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_test_point_compare_u { + mmr_t sh_pi_test_point_compare_regval; + struct { + mmr_t compare_mask : 32; + mmr_t compare_pattern : 32; + } sh_pi_test_point_compare_s; +} sh_pi_test_point_compare_u_t; +#else +typedef union sh_pi_test_point_compare_u { + mmr_t sh_pi_test_point_compare_regval; + struct { + mmr_t compare_pattern : 32; + mmr_t compare_mask : 32; + } sh_pi_test_point_compare_s; +} sh_pi_test_point_compare_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_TEST_POINT_SELECT" */ +/* PI Test Point Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_test_point_select_u { + mmr_t sh_pi_test_point_select_regval; + struct { + mmr_t nibble0_chiplet_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_chiplet_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_chiplet_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_chiplet_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_chiplet_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_chiplet_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_chiplet_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_chiplet_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t trigger_enable : 1; + } sh_pi_test_point_select_s; +} sh_pi_test_point_select_u_t; +#else +typedef union sh_pi_test_point_select_u { + mmr_t sh_pi_test_point_select_regval; + struct { + mmr_t trigger_enable : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_chiplet_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_chiplet_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_chiplet_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_chiplet_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_chiplet_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_chiplet_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_chiplet_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_chiplet_sel : 3; + } sh_pi_test_point_select_s; +} sh_pi_test_point_select_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_TEST_POINT_TRIGGER_SELECT" */ +/* PI Test Point Trigger Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_test_point_trigger_select_u { + mmr_t sh_pi_test_point_trigger_select_regval; + struct { + mmr_t trigger0_chiplet_sel : 3; + mmr_t reserved_0 : 1; + mmr_t trigger0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t trigger1_chiplet_sel : 3; + mmr_t reserved_2 : 1; + mmr_t trigger1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t trigger2_chiplet_sel : 3; + mmr_t reserved_4 : 1; + mmr_t trigger2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t trigger3_chiplet_sel : 3; + mmr_t reserved_6 : 1; + mmr_t trigger3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t trigger4_chiplet_sel : 3; + mmr_t reserved_8 : 1; + mmr_t trigger4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t trigger5_chiplet_sel : 3; + mmr_t reserved_10 : 1; + mmr_t trigger5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t trigger6_chiplet_sel : 3; + mmr_t reserved_12 : 1; + mmr_t trigger6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t trigger7_chiplet_sel : 3; + mmr_t reserved_14 : 1; + mmr_t trigger7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_pi_test_point_trigger_select_s; +} sh_pi_test_point_trigger_select_u_t; +#else +typedef union sh_pi_test_point_trigger_select_u { + mmr_t sh_pi_test_point_trigger_select_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t trigger7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t trigger7_chiplet_sel : 3; + mmr_t reserved_13 : 1; + mmr_t trigger6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t trigger6_chiplet_sel : 3; + mmr_t reserved_11 : 1; + mmr_t trigger5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t trigger5_chiplet_sel : 3; + mmr_t reserved_9 : 1; + mmr_t trigger4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t trigger4_chiplet_sel : 3; + mmr_t reserved_7 : 1; + mmr_t trigger3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t trigger3_chiplet_sel : 3; + mmr_t reserved_5 : 1; + mmr_t trigger2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t trigger2_chiplet_sel : 3; + mmr_t reserved_3 : 1; + mmr_t trigger1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t trigger1_chiplet_sel : 3; + mmr_t reserved_1 : 1; + mmr_t trigger0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t trigger0_chiplet_sel : 3; + } sh_pi_test_point_trigger_select_s; +} sh_pi_test_point_trigger_select_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_XN2PI_REPLY_VC_CONFIG" */ +/* XN-to-PI Reply Virtual Channel Configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_xn2pi_reply_vc_config_u { + mmr_t sh_pi_xn2pi_reply_vc_config_regval; + struct { + mmr_t hdr_depth : 4; + mmr_t data_depth : 4; + mmr_t max_credits : 6; + mmr_t reserved_0 : 48; + mmr_t force_credit : 1; + mmr_t capture_credit_status : 1; + } sh_pi_xn2pi_reply_vc_config_s; +} sh_pi_xn2pi_reply_vc_config_u_t; +#else +typedef union sh_pi_xn2pi_reply_vc_config_u { + mmr_t sh_pi_xn2pi_reply_vc_config_regval; + struct { + mmr_t capture_credit_status : 1; + mmr_t force_credit : 1; + mmr_t reserved_0 : 48; + mmr_t max_credits : 6; + mmr_t data_depth : 4; + mmr_t hdr_depth : 4; + } sh_pi_xn2pi_reply_vc_config_s; +} sh_pi_xn2pi_reply_vc_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_XN2PI_REQUEST_VC_CONFIG" */ +/* XN-to-PI Request Virtual Channel Configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_xn2pi_request_vc_config_u { + mmr_t sh_pi_xn2pi_request_vc_config_regval; + struct { + mmr_t hdr_depth : 4; + mmr_t data_depth : 4; + mmr_t max_credits : 6; + mmr_t reserved_0 : 48; + mmr_t force_credit : 1; + mmr_t capture_credit_status : 1; + } sh_pi_xn2pi_request_vc_config_s; +} sh_pi_xn2pi_request_vc_config_u_t; +#else +typedef union sh_pi_xn2pi_request_vc_config_u { + mmr_t sh_pi_xn2pi_request_vc_config_regval; + struct { + mmr_t capture_credit_status : 1; + mmr_t force_credit : 1; + mmr_t reserved_0 : 48; + mmr_t max_credits : 6; + mmr_t data_depth : 4; + mmr_t hdr_depth : 4; + } sh_pi_xn2pi_request_vc_config_s; +} sh_pi_xn2pi_request_vc_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_AEC_STATUS" */ +/* PI Adaptive Error Correction Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_aec_status_u { + mmr_t sh_pi_aec_status_regval; + struct { + mmr_t state : 3; + mmr_t reserved_0 : 61; + } sh_pi_aec_status_s; +} sh_pi_aec_status_u_t; +#else +typedef union sh_pi_aec_status_u { + mmr_t sh_pi_aec_status_regval; + struct { + mmr_t reserved_0 : 61; + mmr_t state : 3; + } sh_pi_aec_status_s; +} sh_pi_aec_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_AFI_FIRST_ERROR" */ +/* PI AFI First Error */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_afi_first_error_u { + mmr_t sh_pi_afi_first_error_regval; + struct { + mmr_t reserved_0 : 7; + mmr_t fsb_shub_uce : 1; + mmr_t fsb_shub_ce : 1; + mmr_t reserved_1 : 12; + mmr_t hung_bus : 1; + mmr_t rsp_parity : 1; + mmr_t ioq_overrun : 1; + mmr_t req_format : 1; + mmr_t addr_access : 1; + mmr_t req_parity : 1; + mmr_t addr_parity : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_ce : 1; + mmr_t livelock : 1; + mmr_t bad_snoop : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t msg_len : 1; + mmr_t reserved_2 : 29; + } sh_pi_afi_first_error_s; +} sh_pi_afi_first_error_u_t; +#else +typedef union sh_pi_afi_first_error_u { + mmr_t sh_pi_afi_first_error_regval; + struct { + mmr_t reserved_2 : 29; + mmr_t msg_len : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t bad_snoop : 1; + mmr_t livelock : 1; + mmr_t shub_fsb_ce : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t addr_parity : 1; + mmr_t req_parity : 1; + mmr_t addr_access : 1; + mmr_t req_format : 1; + mmr_t ioq_overrun : 1; + mmr_t rsp_parity : 1; + mmr_t hung_bus : 1; + mmr_t reserved_1 : 12; + mmr_t fsb_shub_ce : 1; + mmr_t fsb_shub_uce : 1; + mmr_t reserved_0 : 7; + } sh_pi_afi_first_error_s; +} sh_pi_afi_first_error_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CAM_ADDRESS_READ_DATA" */ +/* CRB CAM MMR Address Read Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_cam_address_read_data_u { + mmr_t sh_pi_cam_address_read_data_regval; + struct { + mmr_t cam_addr : 48; + mmr_t reserved_0 : 15; + mmr_t cam_addr_val : 1; + } sh_pi_cam_address_read_data_s; +} sh_pi_cam_address_read_data_u_t; +#else +typedef union sh_pi_cam_address_read_data_u { + mmr_t sh_pi_cam_address_read_data_regval; + struct { + mmr_t cam_addr_val : 1; + mmr_t reserved_0 : 15; + mmr_t cam_addr : 48; + } sh_pi_cam_address_read_data_s; +} sh_pi_cam_address_read_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CAM_LPRA_READ_DATA" */ +/* CRB CAM MMR LPRA Read Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_cam_lpra_read_data_u { + mmr_t sh_pi_cam_lpra_read_data_regval; + struct { + mmr_t cam_lpra : 64; + } sh_pi_cam_lpra_read_data_s; +} sh_pi_cam_lpra_read_data_u_t; +#else +typedef union sh_pi_cam_lpra_read_data_u { + mmr_t sh_pi_cam_lpra_read_data_regval; + struct { + mmr_t cam_lpra : 64; + } sh_pi_cam_lpra_read_data_s; +} sh_pi_cam_lpra_read_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CAM_STATE_READ_DATA" */ +/* CRB CAM MMR State Read Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_cam_state_read_data_u { + mmr_t sh_pi_cam_state_read_data_regval; + struct { + mmr_t cam_state : 4; + mmr_t cam_to : 1; + mmr_t cam_state_rd_pend : 1; + mmr_t reserved_0 : 26; + mmr_t cam_lpra : 18; + mmr_t reserved_1 : 13; + mmr_t cam_rd_data_val : 1; + } sh_pi_cam_state_read_data_s; +} sh_pi_cam_state_read_data_u_t; +#else +typedef union sh_pi_cam_state_read_data_u { + mmr_t sh_pi_cam_state_read_data_regval; + struct { + mmr_t cam_rd_data_val : 1; + mmr_t reserved_1 : 13; + mmr_t cam_lpra : 18; + mmr_t reserved_0 : 26; + mmr_t cam_state_rd_pend : 1; + mmr_t cam_to : 1; + mmr_t cam_state : 4; + } sh_pi_cam_state_read_data_s; +} sh_pi_cam_state_read_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CORRECTED_DETAIL_1" */ +/* PI Corrected Error Detail */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_corrected_detail_1_u { + mmr_t sh_pi_corrected_detail_1_regval; + struct { + mmr_t address : 48; + mmr_t syndrome : 8; + mmr_t dep : 8; + } sh_pi_corrected_detail_1_s; +} sh_pi_corrected_detail_1_u_t; +#else +typedef union sh_pi_corrected_detail_1_u { + mmr_t sh_pi_corrected_detail_1_regval; + struct { + mmr_t dep : 8; + mmr_t syndrome : 8; + mmr_t address : 48; + } sh_pi_corrected_detail_1_s; +} sh_pi_corrected_detail_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CORRECTED_DETAIL_2" */ +/* PI Corrected Error Detail 2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_corrected_detail_2_u { + mmr_t sh_pi_corrected_detail_2_regval; + struct { + mmr_t data : 64; + } sh_pi_corrected_detail_2_s; +} sh_pi_corrected_detail_2_u_t; +#else +typedef union sh_pi_corrected_detail_2_u { + mmr_t sh_pi_corrected_detail_2_regval; + struct { + mmr_t data : 64; + } sh_pi_corrected_detail_2_s; +} sh_pi_corrected_detail_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CORRECTED_DETAIL_3" */ +/* PI Corrected Error Detail 3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_corrected_detail_3_u { + mmr_t sh_pi_corrected_detail_3_regval; + struct { + mmr_t address : 48; + mmr_t syndrome : 8; + mmr_t dep : 8; + } sh_pi_corrected_detail_3_s; +} sh_pi_corrected_detail_3_u_t; +#else +typedef union sh_pi_corrected_detail_3_u { + mmr_t sh_pi_corrected_detail_3_regval; + struct { + mmr_t dep : 8; + mmr_t syndrome : 8; + mmr_t address : 48; + } sh_pi_corrected_detail_3_s; +} sh_pi_corrected_detail_3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CORRECTED_DETAIL_4" */ +/* PI Corrected Error Detail 4 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_corrected_detail_4_u { + mmr_t sh_pi_corrected_detail_4_regval; + struct { + mmr_t data : 64; + } sh_pi_corrected_detail_4_s; +} sh_pi_corrected_detail_4_u_t; +#else +typedef union sh_pi_corrected_detail_4_u { + mmr_t sh_pi_corrected_detail_4_regval; + struct { + mmr_t data : 64; + } sh_pi_corrected_detail_4_s; +} sh_pi_corrected_detail_4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_CRBP_FIRST_ERROR" */ +/* PI CRBP First Error */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_crbp_first_error_u { + mmr_t sh_pi_crbp_first_error_regval; + struct { + mmr_t fsb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t mem_rp_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_to_err : 1; + mmr_t fsb_shub_uce : 1; + mmr_t fsb_shub_ce : 1; + mmr_t msg_color_err : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t nack_oflow : 1; + mmr_t gfx_int_0 : 1; + mmr_t gfx_int_1 : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t xn_rp_crd_oflow : 1; + mmr_t reserved_0 : 43; + } sh_pi_crbp_first_error_s; +} sh_pi_crbp_first_error_u_t; +#else +typedef union sh_pi_crbp_first_error_u { + mmr_t sh_pi_crbp_first_error_regval; + struct { + mmr_t reserved_0 : 43; + mmr_t xn_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t gfx_int_1 : 1; + mmr_t gfx_int_0 : 1; + mmr_t nack_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t msg_color_err : 1; + mmr_t fsb_shub_ce : 1; + mmr_t fsb_shub_uce : 1; + mmr_t pio_to_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t fsb_proto_err : 1; + } sh_pi_crbp_first_error_s; +} sh_pi_crbp_first_error_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_DETAIL_1" */ +/* PI Error Detail 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_error_detail_1_u { + mmr_t sh_pi_error_detail_1_regval; + struct { + mmr_t status : 64; + } sh_pi_error_detail_1_s; +} sh_pi_error_detail_1_u_t; +#else +typedef union sh_pi_error_detail_1_u { + mmr_t sh_pi_error_detail_1_regval; + struct { + mmr_t status : 64; + } sh_pi_error_detail_1_s; +} sh_pi_error_detail_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_DETAIL_2" */ +/* PI Error Detail 2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_error_detail_2_u { + mmr_t sh_pi_error_detail_2_regval; + struct { + mmr_t status : 64; + } sh_pi_error_detail_2_s; +} sh_pi_error_detail_2_u_t; +#else +typedef union sh_pi_error_detail_2_u { + mmr_t sh_pi_error_detail_2_regval; + struct { + mmr_t status : 64; + } sh_pi_error_detail_2_s; +} sh_pi_error_detail_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_OVERFLOW" */ +/* PI Error Overflow */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_error_overflow_u { + mmr_t sh_pi_error_overflow_regval; + struct { + mmr_t fsb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t mem_rp_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_to_err : 1; + mmr_t fsb_shub_uce : 1; + mmr_t fsb_shub_ce : 1; + mmr_t msg_color_err : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t nack_oflow : 1; + mmr_t gfx_int_0 : 1; + mmr_t gfx_int_1 : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t xn_rp_crd_oflow : 1; + mmr_t hung_bus : 1; + mmr_t rsp_parity : 1; + mmr_t ioq_overrun : 1; + mmr_t req_format : 1; + mmr_t addr_access : 1; + mmr_t req_parity : 1; + mmr_t addr_parity : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_ce : 1; + mmr_t livelock : 1; + mmr_t bad_snoop : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t msg_length : 1; + mmr_t reserved_0 : 29; + } sh_pi_error_overflow_s; +} sh_pi_error_overflow_u_t; +#else +typedef union sh_pi_error_overflow_u { + mmr_t sh_pi_error_overflow_regval; + struct { + mmr_t reserved_0 : 29; + mmr_t msg_length : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t bad_snoop : 1; + mmr_t livelock : 1; + mmr_t shub_fsb_ce : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t addr_parity : 1; + mmr_t req_parity : 1; + mmr_t addr_access : 1; + mmr_t req_format : 1; + mmr_t ioq_overrun : 1; + mmr_t rsp_parity : 1; + mmr_t hung_bus : 1; + mmr_t xn_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t gfx_int_1 : 1; + mmr_t gfx_int_0 : 1; + mmr_t nack_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t msg_color_err : 1; + mmr_t fsb_shub_ce : 1; + mmr_t fsb_shub_uce : 1; + mmr_t pio_to_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t fsb_proto_err : 1; + } sh_pi_error_overflow_s; +} sh_pi_error_overflow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_ERROR_SUMMARY" */ +/* PI Error Summary */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_error_summary_u { + mmr_t sh_pi_error_summary_regval; + struct { + mmr_t fsb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t mem_rp_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_to_err : 1; + mmr_t fsb_shub_uce : 1; + mmr_t fsb_shub_ce : 1; + mmr_t msg_color_err : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t nack_oflow : 1; + mmr_t gfx_int_0 : 1; + mmr_t gfx_int_1 : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t xn_rp_crd_oflow : 1; + mmr_t hung_bus : 1; + mmr_t rsp_parity : 1; + mmr_t ioq_overrun : 1; + mmr_t req_format : 1; + mmr_t addr_access : 1; + mmr_t req_parity : 1; + mmr_t addr_parity : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_ce : 1; + mmr_t livelock : 1; + mmr_t bad_snoop : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t msg_length : 1; + mmr_t reserved_0 : 29; + } sh_pi_error_summary_s; +} sh_pi_error_summary_u_t; +#else +typedef union sh_pi_error_summary_u { + mmr_t sh_pi_error_summary_regval; + struct { + mmr_t reserved_0 : 29; + mmr_t msg_length : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t bad_snoop : 1; + mmr_t livelock : 1; + mmr_t shub_fsb_ce : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t addr_parity : 1; + mmr_t req_parity : 1; + mmr_t addr_access : 1; + mmr_t req_format : 1; + mmr_t ioq_overrun : 1; + mmr_t rsp_parity : 1; + mmr_t hung_bus : 1; + mmr_t xn_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t gfx_int_1 : 1; + mmr_t gfx_int_0 : 1; + mmr_t nack_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t msg_color_err : 1; + mmr_t fsb_shub_ce : 1; + mmr_t fsb_shub_uce : 1; + mmr_t pio_to_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t fsb_proto_err : 1; + } sh_pi_error_summary_s; +} sh_pi_error_summary_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_EXPRESS_REPLY_STATUS" */ +/* PI Express Reply Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_express_reply_status_u { + mmr_t sh_pi_express_reply_status_regval; + struct { + mmr_t state : 3; + mmr_t reserved_0 : 61; + } sh_pi_express_reply_status_s; +} sh_pi_express_reply_status_u_t; +#else +typedef union sh_pi_express_reply_status_u { + mmr_t sh_pi_express_reply_status_regval; + struct { + mmr_t reserved_0 : 61; + mmr_t state : 3; + } sh_pi_express_reply_status_s; +} sh_pi_express_reply_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_FIRST_ERROR" */ +/* PI First Error */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_first_error_u { + mmr_t sh_pi_first_error_regval; + struct { + mmr_t fsb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t mem_rp_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_to_err : 1; + mmr_t fsb_shub_uce : 1; + mmr_t fsb_shub_ce : 1; + mmr_t msg_color_err : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t nack_oflow : 1; + mmr_t gfx_int_0 : 1; + mmr_t gfx_int_1 : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t xn_rp_crd_oflow : 1; + mmr_t hung_bus : 1; + mmr_t rsp_parity : 1; + mmr_t ioq_overrun : 1; + mmr_t req_format : 1; + mmr_t addr_access : 1; + mmr_t req_parity : 1; + mmr_t addr_parity : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_ce : 1; + mmr_t livelock : 1; + mmr_t bad_snoop : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t msg_length : 1; + mmr_t reserved_0 : 29; + } sh_pi_first_error_s; +} sh_pi_first_error_u_t; +#else +typedef union sh_pi_first_error_u { + mmr_t sh_pi_first_error_regval; + struct { + mmr_t reserved_0 : 29; + mmr_t msg_length : 1; + mmr_t fsb_tbl_miss : 1; + mmr_t bad_snoop : 1; + mmr_t livelock : 1; + mmr_t shub_fsb_ce : 1; + mmr_t shub_fsb_uce : 1; + mmr_t shub_fsb_dqe : 1; + mmr_t addr_parity : 1; + mmr_t req_parity : 1; + mmr_t addr_access : 1; + mmr_t req_format : 1; + mmr_t ioq_overrun : 1; + mmr_t rsp_parity : 1; + mmr_t hung_bus : 1; + mmr_t xn_rp_crd_oflow : 1; + mmr_t xn_rq_crd_oflow : 1; + mmr_t md_rp_crd_oflow : 1; + mmr_t md_rq_crd_oflow : 1; + mmr_t gfx_int_1 : 1; + mmr_t gfx_int_0 : 1; + mmr_t nack_oflow : 1; + mmr_t xn_rp_q_oflow : 1; + mmr_t xn_rq_q_oflow : 1; + mmr_t md_rp_q_oflow : 1; + mmr_t md_rq_q_oflow : 1; + mmr_t msg_color_err : 1; + mmr_t fsb_shub_ce : 1; + mmr_t fsb_shub_uce : 1; + mmr_t pio_to_err : 1; + mmr_t mem_to_err : 1; + mmr_t pio_rp_err : 1; + mmr_t mem_rp_err : 1; + mmr_t xb_proto_err : 1; + mmr_t gfx_rp_err : 1; + mmr_t fsb_proto_err : 1; + } sh_pi_first_error_s; +} sh_pi_first_error_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_PI2MD_REPLY_VC_STATUS" */ +/* PI-to-MD Reply Virtual Channel Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_pi2md_reply_vc_status_u { + mmr_t sh_pi_pi2md_reply_vc_status_regval; + struct { + mmr_t output_crd_stat : 6; + mmr_t reserved_0 : 58; + } sh_pi_pi2md_reply_vc_status_s; +} sh_pi_pi2md_reply_vc_status_u_t; +#else +typedef union sh_pi_pi2md_reply_vc_status_u { + mmr_t sh_pi_pi2md_reply_vc_status_regval; + struct { + mmr_t reserved_0 : 58; + mmr_t output_crd_stat : 6; + } sh_pi_pi2md_reply_vc_status_s; +} sh_pi_pi2md_reply_vc_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_PI2MD_REQUEST_VC_STATUS" */ +/* PI-to-MD Request Virtual Channel Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_pi2md_request_vc_status_u { + mmr_t sh_pi_pi2md_request_vc_status_regval; + struct { + mmr_t output_crd_stat : 6; + mmr_t reserved_0 : 58; + } sh_pi_pi2md_request_vc_status_s; +} sh_pi_pi2md_request_vc_status_u_t; +#else +typedef union sh_pi_pi2md_request_vc_status_u { + mmr_t sh_pi_pi2md_request_vc_status_regval; + struct { + mmr_t reserved_0 : 58; + mmr_t output_crd_stat : 6; + } sh_pi_pi2md_request_vc_status_s; +} sh_pi_pi2md_request_vc_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_PI2XN_REPLY_VC_STATUS" */ +/* PI-to-XN Reply Virtual Channel Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_pi2xn_reply_vc_status_u { + mmr_t sh_pi_pi2xn_reply_vc_status_regval; + struct { + mmr_t output_crd_stat : 6; + mmr_t reserved_0 : 58; + } sh_pi_pi2xn_reply_vc_status_s; +} sh_pi_pi2xn_reply_vc_status_u_t; +#else +typedef union sh_pi_pi2xn_reply_vc_status_u { + mmr_t sh_pi_pi2xn_reply_vc_status_regval; + struct { + mmr_t reserved_0 : 58; + mmr_t output_crd_stat : 6; + } sh_pi_pi2xn_reply_vc_status_s; +} sh_pi_pi2xn_reply_vc_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_PI2XN_REQUEST_VC_STATUS" */ +/* PI-to-XN Request Virtual Channel Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_pi2xn_request_vc_status_u { + mmr_t sh_pi_pi2xn_request_vc_status_regval; + struct { + mmr_t output_crd_stat : 6; + mmr_t reserved_0 : 58; + } sh_pi_pi2xn_request_vc_status_s; +} sh_pi_pi2xn_request_vc_status_u_t; +#else +typedef union sh_pi_pi2xn_request_vc_status_u { + mmr_t sh_pi_pi2xn_request_vc_status_regval; + struct { + mmr_t reserved_0 : 58; + mmr_t output_crd_stat : 6; + } sh_pi_pi2xn_request_vc_status_s; +} sh_pi_pi2xn_request_vc_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_UNCORRECTED_DETAIL_1" */ +/* PI Uncorrected Error Detail 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_uncorrected_detail_1_u { + mmr_t sh_pi_uncorrected_detail_1_regval; + struct { + mmr_t address : 48; + mmr_t syndrome : 8; + mmr_t dep : 8; + } sh_pi_uncorrected_detail_1_s; +} sh_pi_uncorrected_detail_1_u_t; +#else +typedef union sh_pi_uncorrected_detail_1_u { + mmr_t sh_pi_uncorrected_detail_1_regval; + struct { + mmr_t dep : 8; + mmr_t syndrome : 8; + mmr_t address : 48; + } sh_pi_uncorrected_detail_1_s; +} sh_pi_uncorrected_detail_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_UNCORRECTED_DETAIL_2" */ +/* PI Uncorrected Error Detail 2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_uncorrected_detail_2_u { + mmr_t sh_pi_uncorrected_detail_2_regval; + struct { + mmr_t data : 64; + } sh_pi_uncorrected_detail_2_s; +} sh_pi_uncorrected_detail_2_u_t; +#else +typedef union sh_pi_uncorrected_detail_2_u { + mmr_t sh_pi_uncorrected_detail_2_regval; + struct { + mmr_t data : 64; + } sh_pi_uncorrected_detail_2_s; +} sh_pi_uncorrected_detail_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_UNCORRECTED_DETAIL_3" */ +/* PI Uncorrected Error Detail 3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_uncorrected_detail_3_u { + mmr_t sh_pi_uncorrected_detail_3_regval; + struct { + mmr_t address : 48; + mmr_t syndrome : 8; + mmr_t dep : 8; + } sh_pi_uncorrected_detail_3_s; +} sh_pi_uncorrected_detail_3_u_t; +#else +typedef union sh_pi_uncorrected_detail_3_u { + mmr_t sh_pi_uncorrected_detail_3_regval; + struct { + mmr_t dep : 8; + mmr_t syndrome : 8; + mmr_t address : 48; + } sh_pi_uncorrected_detail_3_s; +} sh_pi_uncorrected_detail_3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_UNCORRECTED_DETAIL_4" */ +/* PI Uncorrected Error Detail 4 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_uncorrected_detail_4_u { + mmr_t sh_pi_uncorrected_detail_4_regval; + struct { + mmr_t data : 64; + } sh_pi_uncorrected_detail_4_s; +} sh_pi_uncorrected_detail_4_u_t; +#else +typedef union sh_pi_uncorrected_detail_4_u { + mmr_t sh_pi_uncorrected_detail_4_regval; + struct { + mmr_t data : 64; + } sh_pi_uncorrected_detail_4_s; +} sh_pi_uncorrected_detail_4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_MD2PI_REPLY_VC_STATUS" */ +/* MD-to-PI Reply Virtual Channel Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_md2pi_reply_vc_status_u { + mmr_t sh_pi_md2pi_reply_vc_status_regval; + struct { + mmr_t input_hdr_crd_stat : 4; + mmr_t input_dat_crd_stat : 4; + mmr_t input_queue_stat : 4; + mmr_t reserved_0 : 52; + } sh_pi_md2pi_reply_vc_status_s; +} sh_pi_md2pi_reply_vc_status_u_t; +#else +typedef union sh_pi_md2pi_reply_vc_status_u { + mmr_t sh_pi_md2pi_reply_vc_status_regval; + struct { + mmr_t reserved_0 : 52; + mmr_t input_queue_stat : 4; + mmr_t input_dat_crd_stat : 4; + mmr_t input_hdr_crd_stat : 4; + } sh_pi_md2pi_reply_vc_status_s; +} sh_pi_md2pi_reply_vc_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_MD2PI_REQUEST_VC_STATUS" */ +/* MD-to-PI Request Virtual Channel Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_md2pi_request_vc_status_u { + mmr_t sh_pi_md2pi_request_vc_status_regval; + struct { + mmr_t input_hdr_crd_stat : 4; + mmr_t input_dat_crd_stat : 4; + mmr_t input_queue_stat : 4; + mmr_t reserved_0 : 52; + } sh_pi_md2pi_request_vc_status_s; +} sh_pi_md2pi_request_vc_status_u_t; +#else +typedef union sh_pi_md2pi_request_vc_status_u { + mmr_t sh_pi_md2pi_request_vc_status_regval; + struct { + mmr_t reserved_0 : 52; + mmr_t input_queue_stat : 4; + mmr_t input_dat_crd_stat : 4; + mmr_t input_hdr_crd_stat : 4; + } sh_pi_md2pi_request_vc_status_s; +} sh_pi_md2pi_request_vc_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_XN2PI_REPLY_VC_STATUS" */ +/* XN-to-PI Reply Virtual Channel Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_xn2pi_reply_vc_status_u { + mmr_t sh_pi_xn2pi_reply_vc_status_regval; + struct { + mmr_t input_hdr_crd_stat : 4; + mmr_t input_dat_crd_stat : 4; + mmr_t input_queue_stat : 4; + mmr_t reserved_0 : 52; + } sh_pi_xn2pi_reply_vc_status_s; +} sh_pi_xn2pi_reply_vc_status_u_t; +#else +typedef union sh_pi_xn2pi_reply_vc_status_u { + mmr_t sh_pi_xn2pi_reply_vc_status_regval; + struct { + mmr_t reserved_0 : 52; + mmr_t input_queue_stat : 4; + mmr_t input_dat_crd_stat : 4; + mmr_t input_hdr_crd_stat : 4; + } sh_pi_xn2pi_reply_vc_status_s; +} sh_pi_xn2pi_reply_vc_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_XN2PI_REQUEST_VC_STATUS" */ +/* XN-to-PI Request Virtual Channel Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_xn2pi_request_vc_status_u { + mmr_t sh_pi_xn2pi_request_vc_status_regval; + struct { + mmr_t input_hdr_crd_stat : 4; + mmr_t input_dat_crd_stat : 4; + mmr_t input_queue_stat : 4; + mmr_t reserved_0 : 52; + } sh_pi_xn2pi_request_vc_status_s; +} sh_pi_xn2pi_request_vc_status_u_t; +#else +typedef union sh_pi_xn2pi_request_vc_status_u { + mmr_t sh_pi_xn2pi_request_vc_status_regval; + struct { + mmr_t reserved_0 : 52; + mmr_t input_queue_stat : 4; + mmr_t input_dat_crd_stat : 4; + mmr_t input_hdr_crd_stat : 4; + } sh_pi_xn2pi_request_vc_status_s; +} sh_pi_xn2pi_request_vc_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_SIC_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_sic_flow_u { + mmr_t sh_xnpi_sic_flow_regval; + struct { + mmr_t debit_vc0_withhold : 5; + mmr_t reserved_0 : 2; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 5; + mmr_t reserved_1 : 2; + mmr_t debit_vc2_force_cred : 1; + mmr_t credit_vc0_test : 5; + mmr_t reserved_2 : 3; + mmr_t credit_vc0_dyn : 5; + mmr_t reserved_3 : 3; + mmr_t credit_vc0_cap : 5; + mmr_t reserved_4 : 3; + mmr_t credit_vc2_test : 5; + mmr_t reserved_5 : 3; + mmr_t credit_vc2_dyn : 5; + mmr_t reserved_6 : 3; + mmr_t credit_vc2_cap : 5; + mmr_t reserved_7 : 2; + mmr_t disable_bypass_out : 1; + } sh_xnpi_sic_flow_s; +} sh_xnpi_sic_flow_u_t; +#else +typedef union sh_xnpi_sic_flow_u { + mmr_t sh_xnpi_sic_flow_regval; + struct { + mmr_t disable_bypass_out : 1; + mmr_t reserved_7 : 2; + mmr_t credit_vc2_cap : 5; + mmr_t reserved_6 : 3; + mmr_t credit_vc2_dyn : 5; + mmr_t reserved_5 : 3; + mmr_t credit_vc2_test : 5; + mmr_t reserved_4 : 3; + mmr_t credit_vc0_cap : 5; + mmr_t reserved_3 : 3; + mmr_t credit_vc0_dyn : 5; + mmr_t reserved_2 : 3; + mmr_t credit_vc0_test : 5; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 2; + mmr_t debit_vc2_withhold : 5; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 2; + mmr_t debit_vc0_withhold : 5; + } sh_xnpi_sic_flow_s; +} sh_xnpi_sic_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_TO_NI0_PORT_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_to_ni0_port_flow_u { + mmr_t sh_xnpi_to_ni0_port_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_6 : 2; + } sh_xnpi_to_ni0_port_flow_s; +} sh_xnpi_to_ni0_port_flow_u_t; +#else +typedef union sh_xnpi_to_ni0_port_flow_u { + mmr_t sh_xnpi_to_ni0_port_flow_regval; + struct { + mmr_t reserved_6 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_2 : 8; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnpi_to_ni0_port_flow_s; +} sh_xnpi_to_ni0_port_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_TO_NI1_PORT_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_to_ni1_port_flow_u { + mmr_t sh_xnpi_to_ni1_port_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_6 : 2; + } sh_xnpi_to_ni1_port_flow_s; +} sh_xnpi_to_ni1_port_flow_u_t; +#else +typedef union sh_xnpi_to_ni1_port_flow_u { + mmr_t sh_xnpi_to_ni1_port_flow_regval; + struct { + mmr_t reserved_6 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_2 : 8; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnpi_to_ni1_port_flow_s; +} sh_xnpi_to_ni1_port_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_TO_IILB_PORT_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_to_iilb_port_flow_u { + mmr_t sh_xnpi_to_iilb_port_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_6 : 2; + } sh_xnpi_to_iilb_port_flow_s; +} sh_xnpi_to_iilb_port_flow_u_t; +#else +typedef union sh_xnpi_to_iilb_port_flow_u { + mmr_t sh_xnpi_to_iilb_port_flow_regval; + struct { + mmr_t reserved_6 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_2 : 8; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnpi_to_iilb_port_flow_s; +} sh_xnpi_to_iilb_port_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_fr_ni0_port_flow_fifo_u { + mmr_t sh_xnpi_fr_ni0_port_flow_fifo_regval; + struct { + mmr_t entry_vc0_dyn : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_3 : 2; + mmr_t entry_vc0_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc2_test : 5; + mmr_t reserved_5 : 19; + } sh_xnpi_fr_ni0_port_flow_fifo_s; +} sh_xnpi_fr_ni0_port_flow_fifo_u_t; +#else +typedef union sh_xnpi_fr_ni0_port_flow_fifo_u { + mmr_t sh_xnpi_fr_ni0_port_flow_fifo_regval; + struct { + mmr_t reserved_5 : 19; + mmr_t entry_vc2_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc0_test : 5; + mmr_t reserved_3 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_dyn : 6; + } sh_xnpi_fr_ni0_port_flow_fifo_s; +} sh_xnpi_fr_ni0_port_flow_fifo_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_fr_ni1_port_flow_fifo_u { + mmr_t sh_xnpi_fr_ni1_port_flow_fifo_regval; + struct { + mmr_t entry_vc0_dyn : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_3 : 2; + mmr_t entry_vc0_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc2_test : 5; + mmr_t reserved_5 : 19; + } sh_xnpi_fr_ni1_port_flow_fifo_s; +} sh_xnpi_fr_ni1_port_flow_fifo_u_t; +#else +typedef union sh_xnpi_fr_ni1_port_flow_fifo_u { + mmr_t sh_xnpi_fr_ni1_port_flow_fifo_regval; + struct { + mmr_t reserved_5 : 19; + mmr_t entry_vc2_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc0_test : 5; + mmr_t reserved_3 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_dyn : 6; + } sh_xnpi_fr_ni1_port_flow_fifo_s; +} sh_xnpi_fr_ni1_port_flow_fifo_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_fr_iilb_port_flow_fifo_u { + mmr_t sh_xnpi_fr_iilb_port_flow_fifo_regval; + struct { + mmr_t entry_vc0_dyn : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_3 : 2; + mmr_t entry_vc0_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc2_test : 5; + mmr_t reserved_5 : 19; + } sh_xnpi_fr_iilb_port_flow_fifo_s; +} sh_xnpi_fr_iilb_port_flow_fifo_u_t; +#else +typedef union sh_xnpi_fr_iilb_port_flow_fifo_u { + mmr_t sh_xnpi_fr_iilb_port_flow_fifo_regval; + struct { + mmr_t reserved_5 : 19; + mmr_t entry_vc2_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc0_test : 5; + mmr_t reserved_3 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_dyn : 6; + } sh_xnpi_fr_iilb_port_flow_fifo_s; +} sh_xnpi_fr_iilb_port_flow_fifo_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_SIC_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_sic_flow_u { + mmr_t sh_xnmd_sic_flow_regval; + struct { + mmr_t debit_vc0_withhold : 5; + mmr_t reserved_0 : 2; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 5; + mmr_t reserved_1 : 2; + mmr_t debit_vc2_force_cred : 1; + mmr_t credit_vc0_test : 5; + mmr_t reserved_2 : 3; + mmr_t credit_vc0_dyn : 5; + mmr_t reserved_3 : 3; + mmr_t credit_vc0_cap : 5; + mmr_t reserved_4 : 3; + mmr_t credit_vc2_test : 5; + mmr_t reserved_5 : 3; + mmr_t credit_vc2_dyn : 5; + mmr_t reserved_6 : 3; + mmr_t credit_vc2_cap : 5; + mmr_t reserved_7 : 2; + mmr_t disable_bypass_out : 1; + } sh_xnmd_sic_flow_s; +} sh_xnmd_sic_flow_u_t; +#else +typedef union sh_xnmd_sic_flow_u { + mmr_t sh_xnmd_sic_flow_regval; + struct { + mmr_t disable_bypass_out : 1; + mmr_t reserved_7 : 2; + mmr_t credit_vc2_cap : 5; + mmr_t reserved_6 : 3; + mmr_t credit_vc2_dyn : 5; + mmr_t reserved_5 : 3; + mmr_t credit_vc2_test : 5; + mmr_t reserved_4 : 3; + mmr_t credit_vc0_cap : 5; + mmr_t reserved_3 : 3; + mmr_t credit_vc0_dyn : 5; + mmr_t reserved_2 : 3; + mmr_t credit_vc0_test : 5; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 2; + mmr_t debit_vc2_withhold : 5; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 2; + mmr_t debit_vc0_withhold : 5; + } sh_xnmd_sic_flow_s; +} sh_xnmd_sic_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_TO_NI0_PORT_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_to_ni0_port_flow_u { + mmr_t sh_xnmd_to_ni0_port_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_6 : 2; + } sh_xnmd_to_ni0_port_flow_s; +} sh_xnmd_to_ni0_port_flow_u_t; +#else +typedef union sh_xnmd_to_ni0_port_flow_u { + mmr_t sh_xnmd_to_ni0_port_flow_regval; + struct { + mmr_t reserved_6 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_2 : 8; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnmd_to_ni0_port_flow_s; +} sh_xnmd_to_ni0_port_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_TO_NI1_PORT_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_to_ni1_port_flow_u { + mmr_t sh_xnmd_to_ni1_port_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_6 : 2; + } sh_xnmd_to_ni1_port_flow_s; +} sh_xnmd_to_ni1_port_flow_u_t; +#else +typedef union sh_xnmd_to_ni1_port_flow_u { + mmr_t sh_xnmd_to_ni1_port_flow_regval; + struct { + mmr_t reserved_6 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_2 : 8; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnmd_to_ni1_port_flow_s; +} sh_xnmd_to_ni1_port_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_TO_IILB_PORT_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_to_iilb_port_flow_u { + mmr_t sh_xnmd_to_iilb_port_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_6 : 2; + } sh_xnmd_to_iilb_port_flow_s; +} sh_xnmd_to_iilb_port_flow_u_t; +#else +typedef union sh_xnmd_to_iilb_port_flow_u { + mmr_t sh_xnmd_to_iilb_port_flow_regval; + struct { + mmr_t reserved_6 : 2; + mmr_t credit_vc2_cap : 6; + mmr_t reserved_5 : 2; + mmr_t credit_vc2_dyn : 6; + mmr_t reserved_4 : 10; + mmr_t credit_vc0_cap : 6; + mmr_t reserved_3 : 2; + mmr_t credit_vc0_dyn : 6; + mmr_t reserved_2 : 8; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnmd_to_iilb_port_flow_s; +} sh_xnmd_to_iilb_port_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_fr_ni0_port_flow_fifo_u { + mmr_t sh_xnmd_fr_ni0_port_flow_fifo_regval; + struct { + mmr_t entry_vc0_dyn : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_3 : 2; + mmr_t entry_vc0_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc2_test : 5; + mmr_t reserved_5 : 19; + } sh_xnmd_fr_ni0_port_flow_fifo_s; +} sh_xnmd_fr_ni0_port_flow_fifo_u_t; +#else +typedef union sh_xnmd_fr_ni0_port_flow_fifo_u { + mmr_t sh_xnmd_fr_ni0_port_flow_fifo_regval; + struct { + mmr_t reserved_5 : 19; + mmr_t entry_vc2_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc0_test : 5; + mmr_t reserved_3 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_dyn : 6; + } sh_xnmd_fr_ni0_port_flow_fifo_s; +} sh_xnmd_fr_ni0_port_flow_fifo_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_fr_ni1_port_flow_fifo_u { + mmr_t sh_xnmd_fr_ni1_port_flow_fifo_regval; + struct { + mmr_t entry_vc0_dyn : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_3 : 2; + mmr_t entry_vc0_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc2_test : 5; + mmr_t reserved_5 : 19; + } sh_xnmd_fr_ni1_port_flow_fifo_s; +} sh_xnmd_fr_ni1_port_flow_fifo_u_t; +#else +typedef union sh_xnmd_fr_ni1_port_flow_fifo_u { + mmr_t sh_xnmd_fr_ni1_port_flow_fifo_regval; + struct { + mmr_t reserved_5 : 19; + mmr_t entry_vc2_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc0_test : 5; + mmr_t reserved_3 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_dyn : 6; + } sh_xnmd_fr_ni1_port_flow_fifo_s; +} sh_xnmd_fr_ni1_port_flow_fifo_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_fr_iilb_port_flow_fifo_u { + mmr_t sh_xnmd_fr_iilb_port_flow_fifo_regval; + struct { + mmr_t entry_vc0_dyn : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_3 : 2; + mmr_t entry_vc0_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc2_test : 5; + mmr_t reserved_5 : 19; + } sh_xnmd_fr_iilb_port_flow_fifo_s; +} sh_xnmd_fr_iilb_port_flow_fifo_u_t; +#else +typedef union sh_xnmd_fr_iilb_port_flow_fifo_u { + mmr_t sh_xnmd_fr_iilb_port_flow_fifo_regval; + struct { + mmr_t reserved_5 : 19; + mmr_t entry_vc2_test : 5; + mmr_t reserved_4 : 3; + mmr_t entry_vc0_test : 5; + mmr_t reserved_3 : 2; + mmr_t entry_vc2_cap : 6; + mmr_t reserved_2 : 2; + mmr_t entry_vc2_dyn : 6; + mmr_t reserved_1 : 2; + mmr_t entry_vc0_cap : 6; + mmr_t reserved_0 : 2; + mmr_t entry_vc0_dyn : 6; + } sh_xnmd_fr_iilb_port_flow_fifo_s; +} sh_xnmd_fr_iilb_port_flow_fifo_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNII_INTRA_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnii_intra_flow_u { + mmr_t sh_xnii_intra_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t credit_vc0_test : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t credit_vc0_cap : 7; + mmr_t reserved_4 : 1; + mmr_t credit_vc2_test : 7; + mmr_t reserved_5 : 1; + mmr_t credit_vc2_dyn : 7; + mmr_t reserved_6 : 1; + mmr_t credit_vc2_cap : 7; + mmr_t reserved_7 : 1; + } sh_xnii_intra_flow_s; +} sh_xnii_intra_flow_u_t; +#else +typedef union sh_xnii_intra_flow_u { + mmr_t sh_xnii_intra_flow_regval; + struct { + mmr_t reserved_7 : 1; + mmr_t credit_vc2_cap : 7; + mmr_t reserved_6 : 1; + mmr_t credit_vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t credit_vc2_test : 7; + mmr_t reserved_4 : 1; + mmr_t credit_vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t credit_vc0_dyn : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc0_test : 7; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnii_intra_flow_s; +} sh_xnii_intra_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNLB_INTRA_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnlb_intra_flow_u { + mmr_t sh_xnlb_intra_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t credit_vc0_test : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t credit_vc0_cap : 7; + mmr_t reserved_4 : 1; + mmr_t credit_vc2_test : 7; + mmr_t reserved_5 : 1; + mmr_t credit_vc2_dyn : 7; + mmr_t reserved_6 : 1; + mmr_t credit_vc2_cap : 7; + mmr_t disable_bypass_in : 1; + } sh_xnlb_intra_flow_s; +} sh_xnlb_intra_flow_u_t; +#else +typedef union sh_xnlb_intra_flow_u { + mmr_t sh_xnlb_intra_flow_regval; + struct { + mmr_t disable_bypass_in : 1; + mmr_t credit_vc2_cap : 7; + mmr_t reserved_6 : 1; + mmr_t credit_vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t credit_vc2_test : 7; + mmr_t reserved_4 : 1; + mmr_t credit_vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t credit_vc0_dyn : 7; + mmr_t reserved_2 : 1; + mmr_t credit_vc0_test : 7; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t debit_vc2_withhold : 6; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnlb_intra_flow_s; +} sh_xnlb_intra_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_to_ni0_intra_flow_debit_u { + mmr_t sh_xniilb_to_ni0_intra_flow_debit_regval; + struct { + mmr_t vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t vc0_force_cred : 1; + mmr_t vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_4 : 9; + mmr_t vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_6 : 1; + } sh_xniilb_to_ni0_intra_flow_debit_s; +} sh_xniilb_to_ni0_intra_flow_debit_u_t; +#else +typedef union sh_xniilb_to_ni0_intra_flow_debit_u { + mmr_t sh_xniilb_to_ni0_intra_flow_debit_regval; + struct { + mmr_t reserved_6 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 9; + mmr_t vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_2 : 8; + mmr_t vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t vc2_withhold : 6; + mmr_t vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t vc0_withhold : 6; + } sh_xniilb_to_ni0_intra_flow_debit_s; +} sh_xniilb_to_ni0_intra_flow_debit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_to_ni1_intra_flow_debit_u { + mmr_t sh_xniilb_to_ni1_intra_flow_debit_regval; + struct { + mmr_t vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t vc0_force_cred : 1; + mmr_t vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_4 : 9; + mmr_t vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_6 : 1; + } sh_xniilb_to_ni1_intra_flow_debit_s; +} sh_xniilb_to_ni1_intra_flow_debit_u_t; +#else +typedef union sh_xniilb_to_ni1_intra_flow_debit_u { + mmr_t sh_xniilb_to_ni1_intra_flow_debit_regval; + struct { + mmr_t reserved_6 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 9; + mmr_t vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_2 : 8; + mmr_t vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t vc2_withhold : 6; + mmr_t vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t vc0_withhold : 6; + } sh_xniilb_to_ni1_intra_flow_debit_s; +} sh_xniilb_to_ni1_intra_flow_debit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_to_md_intra_flow_debit_u { + mmr_t sh_xniilb_to_md_intra_flow_debit_regval; + struct { + mmr_t vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t vc0_force_cred : 1; + mmr_t vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_4 : 9; + mmr_t vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_6 : 1; + } sh_xniilb_to_md_intra_flow_debit_s; +} sh_xniilb_to_md_intra_flow_debit_u_t; +#else +typedef union sh_xniilb_to_md_intra_flow_debit_u { + mmr_t sh_xniilb_to_md_intra_flow_debit_regval; + struct { + mmr_t reserved_6 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 9; + mmr_t vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_2 : 8; + mmr_t vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t vc2_withhold : 6; + mmr_t vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t vc0_withhold : 6; + } sh_xniilb_to_md_intra_flow_debit_s; +} sh_xniilb_to_md_intra_flow_debit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_to_iilb_intra_flow_debit_u { + mmr_t sh_xniilb_to_iilb_intra_flow_debit_regval; + struct { + mmr_t vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t vc0_force_cred : 1; + mmr_t vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_4 : 9; + mmr_t vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_6 : 1; + } sh_xniilb_to_iilb_intra_flow_debit_s; +} sh_xniilb_to_iilb_intra_flow_debit_u_t; +#else +typedef union sh_xniilb_to_iilb_intra_flow_debit_u { + mmr_t sh_xniilb_to_iilb_intra_flow_debit_regval; + struct { + mmr_t reserved_6 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 9; + mmr_t vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_2 : 8; + mmr_t vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t vc2_withhold : 6; + mmr_t vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t vc0_withhold : 6; + } sh_xniilb_to_iilb_intra_flow_debit_s; +} sh_xniilb_to_iilb_intra_flow_debit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_to_pi_intra_flow_debit_u { + mmr_t sh_xniilb_to_pi_intra_flow_debit_regval; + struct { + mmr_t vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t vc0_force_cred : 1; + mmr_t vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_4 : 9; + mmr_t vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_6 : 1; + } sh_xniilb_to_pi_intra_flow_debit_s; +} sh_xniilb_to_pi_intra_flow_debit_u_t; +#else +typedef union sh_xniilb_to_pi_intra_flow_debit_u { + mmr_t sh_xniilb_to_pi_intra_flow_debit_regval; + struct { + mmr_t reserved_6 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 9; + mmr_t vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_2 : 8; + mmr_t vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t vc2_withhold : 6; + mmr_t vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t vc0_withhold : 6; + } sh_xniilb_to_pi_intra_flow_debit_s; +} sh_xniilb_to_pi_intra_flow_debit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_fr_ni0_intra_flow_credit_u { + mmr_t sh_xniilb_fr_ni0_intra_flow_credit_regval; + struct { + mmr_t vc0_test : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 17; + } sh_xniilb_fr_ni0_intra_flow_credit_s; +} sh_xniilb_fr_ni0_intra_flow_credit_u_t; +#else +typedef union sh_xniilb_fr_ni0_intra_flow_credit_u { + mmr_t sh_xniilb_fr_ni0_intra_flow_credit_regval; + struct { + mmr_t reserved_5 : 17; + mmr_t vc2_cap : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_2 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_test : 7; + } sh_xniilb_fr_ni0_intra_flow_credit_s; +} sh_xniilb_fr_ni0_intra_flow_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_fr_ni1_intra_flow_credit_u { + mmr_t sh_xniilb_fr_ni1_intra_flow_credit_regval; + struct { + mmr_t vc0_test : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 17; + } sh_xniilb_fr_ni1_intra_flow_credit_s; +} sh_xniilb_fr_ni1_intra_flow_credit_u_t; +#else +typedef union sh_xniilb_fr_ni1_intra_flow_credit_u { + mmr_t sh_xniilb_fr_ni1_intra_flow_credit_regval; + struct { + mmr_t reserved_5 : 17; + mmr_t vc2_cap : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_2 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_test : 7; + } sh_xniilb_fr_ni1_intra_flow_credit_s; +} sh_xniilb_fr_ni1_intra_flow_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_fr_md_intra_flow_credit_u { + mmr_t sh_xniilb_fr_md_intra_flow_credit_regval; + struct { + mmr_t vc0_test : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 17; + } sh_xniilb_fr_md_intra_flow_credit_s; +} sh_xniilb_fr_md_intra_flow_credit_u_t; +#else +typedef union sh_xniilb_fr_md_intra_flow_credit_u { + mmr_t sh_xniilb_fr_md_intra_flow_credit_regval; + struct { + mmr_t reserved_5 : 17; + mmr_t vc2_cap : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_2 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_test : 7; + } sh_xniilb_fr_md_intra_flow_credit_s; +} sh_xniilb_fr_md_intra_flow_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_fr_iilb_intra_flow_credit_u { + mmr_t sh_xniilb_fr_iilb_intra_flow_credit_regval; + struct { + mmr_t vc0_test : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 17; + } sh_xniilb_fr_iilb_intra_flow_credit_s; +} sh_xniilb_fr_iilb_intra_flow_credit_u_t; +#else +typedef union sh_xniilb_fr_iilb_intra_flow_credit_u { + mmr_t sh_xniilb_fr_iilb_intra_flow_credit_regval; + struct { + mmr_t reserved_5 : 17; + mmr_t vc2_cap : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_2 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_test : 7; + } sh_xniilb_fr_iilb_intra_flow_credit_s; +} sh_xniilb_fr_iilb_intra_flow_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_fr_pi_intra_flow_credit_u { + mmr_t sh_xniilb_fr_pi_intra_flow_credit_regval; + struct { + mmr_t vc0_test : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 17; + } sh_xniilb_fr_pi_intra_flow_credit_s; +} sh_xniilb_fr_pi_intra_flow_credit_u_t; +#else +typedef union sh_xniilb_fr_pi_intra_flow_credit_u { + mmr_t sh_xniilb_fr_pi_intra_flow_credit_regval; + struct { + mmr_t reserved_5 : 17; + mmr_t vc2_cap : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_2 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_test : 7; + } sh_xniilb_fr_pi_intra_flow_credit_s; +} sh_xniilb_fr_pi_intra_flow_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_to_pi_intra_flow_debit_u { + mmr_t sh_xnni0_to_pi_intra_flow_debit_regval; + struct { + mmr_t vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t vc0_force_cred : 1; + mmr_t vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_4 : 9; + mmr_t vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_6 : 1; + } sh_xnni0_to_pi_intra_flow_debit_s; +} sh_xnni0_to_pi_intra_flow_debit_u_t; +#else +typedef union sh_xnni0_to_pi_intra_flow_debit_u { + mmr_t sh_xnni0_to_pi_intra_flow_debit_regval; + struct { + mmr_t reserved_6 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 9; + mmr_t vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_2 : 8; + mmr_t vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t vc2_withhold : 6; + mmr_t vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t vc0_withhold : 6; + } sh_xnni0_to_pi_intra_flow_debit_s; +} sh_xnni0_to_pi_intra_flow_debit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_to_md_intra_flow_debit_u { + mmr_t sh_xnni0_to_md_intra_flow_debit_regval; + struct { + mmr_t vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t vc0_force_cred : 1; + mmr_t vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_4 : 9; + mmr_t vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_6 : 1; + } sh_xnni0_to_md_intra_flow_debit_s; +} sh_xnni0_to_md_intra_flow_debit_u_t; +#else +typedef union sh_xnni0_to_md_intra_flow_debit_u { + mmr_t sh_xnni0_to_md_intra_flow_debit_regval; + struct { + mmr_t reserved_6 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 9; + mmr_t vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_2 : 8; + mmr_t vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t vc2_withhold : 6; + mmr_t vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t vc0_withhold : 6; + } sh_xnni0_to_md_intra_flow_debit_s; +} sh_xnni0_to_md_intra_flow_debit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_to_iilb_intra_flow_debit_u { + mmr_t sh_xnni0_to_iilb_intra_flow_debit_regval; + struct { + mmr_t vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t vc0_force_cred : 1; + mmr_t vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_4 : 9; + mmr_t vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_6 : 1; + } sh_xnni0_to_iilb_intra_flow_debit_s; +} sh_xnni0_to_iilb_intra_flow_debit_u_t; +#else +typedef union sh_xnni0_to_iilb_intra_flow_debit_u { + mmr_t sh_xnni0_to_iilb_intra_flow_debit_regval; + struct { + mmr_t reserved_6 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 9; + mmr_t vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_2 : 8; + mmr_t vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t vc2_withhold : 6; + mmr_t vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t vc0_withhold : 6; + } sh_xnni0_to_iilb_intra_flow_debit_s; +} sh_xnni0_to_iilb_intra_flow_debit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_fr_pi_intra_flow_credit_u { + mmr_t sh_xnni0_fr_pi_intra_flow_credit_regval; + struct { + mmr_t vc0_test : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 17; + } sh_xnni0_fr_pi_intra_flow_credit_s; +} sh_xnni0_fr_pi_intra_flow_credit_u_t; +#else +typedef union sh_xnni0_fr_pi_intra_flow_credit_u { + mmr_t sh_xnni0_fr_pi_intra_flow_credit_regval; + struct { + mmr_t reserved_5 : 17; + mmr_t vc2_cap : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_2 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_test : 7; + } sh_xnni0_fr_pi_intra_flow_credit_s; +} sh_xnni0_fr_pi_intra_flow_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_fr_md_intra_flow_credit_u { + mmr_t sh_xnni0_fr_md_intra_flow_credit_regval; + struct { + mmr_t vc0_test : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 17; + } sh_xnni0_fr_md_intra_flow_credit_s; +} sh_xnni0_fr_md_intra_flow_credit_u_t; +#else +typedef union sh_xnni0_fr_md_intra_flow_credit_u { + mmr_t sh_xnni0_fr_md_intra_flow_credit_regval; + struct { + mmr_t reserved_5 : 17; + mmr_t vc2_cap : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_2 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_test : 7; + } sh_xnni0_fr_md_intra_flow_credit_s; +} sh_xnni0_fr_md_intra_flow_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_fr_iilb_intra_flow_credit_u { + mmr_t sh_xnni0_fr_iilb_intra_flow_credit_regval; + struct { + mmr_t vc0_test : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 17; + } sh_xnni0_fr_iilb_intra_flow_credit_s; +} sh_xnni0_fr_iilb_intra_flow_credit_u_t; +#else +typedef union sh_xnni0_fr_iilb_intra_flow_credit_u { + mmr_t sh_xnni0_fr_iilb_intra_flow_credit_regval; + struct { + mmr_t reserved_5 : 17; + mmr_t vc2_cap : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_2 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_test : 7; + } sh_xnni0_fr_iilb_intra_flow_credit_s; +} sh_xnni0_fr_iilb_intra_flow_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_0_INTRANI_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_0_intrani_flow_u { + mmr_t sh_xnni0_0_intrani_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_1 : 56; + } sh_xnni0_0_intrani_flow_s; +} sh_xnni0_0_intrani_flow_u_t; +#else +typedef union sh_xnni0_0_intrani_flow_u { + mmr_t sh_xnni0_0_intrani_flow_regval; + struct { + mmr_t reserved_1 : 56; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnni0_0_intrani_flow_s; +} sh_xnni0_0_intrani_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_1_INTRANI_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_1_intrani_flow_u { + mmr_t sh_xnni0_1_intrani_flow_regval; + struct { + mmr_t debit_vc1_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc1_force_cred : 1; + mmr_t reserved_1 : 56; + } sh_xnni0_1_intrani_flow_s; +} sh_xnni0_1_intrani_flow_u_t; +#else +typedef union sh_xnni0_1_intrani_flow_u { + mmr_t sh_xnni0_1_intrani_flow_regval; + struct { + mmr_t reserved_1 : 56; + mmr_t debit_vc1_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc1_withhold : 6; + } sh_xnni0_1_intrani_flow_s; +} sh_xnni0_1_intrani_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_2_INTRANI_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_2_intrani_flow_u { + mmr_t sh_xnni0_2_intrani_flow_regval; + struct { + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 56; + } sh_xnni0_2_intrani_flow_s; +} sh_xnni0_2_intrani_flow_u_t; +#else +typedef union sh_xnni0_2_intrani_flow_u { + mmr_t sh_xnni0_2_intrani_flow_regval; + struct { + mmr_t reserved_1 : 56; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc2_withhold : 6; + } sh_xnni0_2_intrani_flow_s; +} sh_xnni0_2_intrani_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_3_INTRANI_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_3_intrani_flow_u { + mmr_t sh_xnni0_3_intrani_flow_regval; + struct { + mmr_t debit_vc3_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc3_force_cred : 1; + mmr_t reserved_1 : 56; + } sh_xnni0_3_intrani_flow_s; +} sh_xnni0_3_intrani_flow_u_t; +#else +typedef union sh_xnni0_3_intrani_flow_u { + mmr_t sh_xnni0_3_intrani_flow_regval; + struct { + mmr_t reserved_1 : 56; + mmr_t debit_vc3_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc3_withhold : 6; + } sh_xnni0_3_intrani_flow_s; +} sh_xnni0_3_intrani_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_VCSWITCH_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_vcswitch_flow_u { + mmr_t sh_xnni0_vcswitch_flow_regval; + struct { + mmr_t ni_vcfifo_dateline_switch : 1; + mmr_t reserved_0 : 7; + mmr_t pi_vcfifo_switch : 1; + mmr_t reserved_1 : 7; + mmr_t md_vcfifo_switch : 1; + mmr_t reserved_2 : 7; + mmr_t iilb_vcfifo_switch : 1; + mmr_t reserved_3 : 7; + mmr_t disable_sync_bypass_in : 1; + mmr_t disable_sync_bypass_out : 1; + mmr_t async_fifoes : 1; + mmr_t reserved_4 : 29; + } sh_xnni0_vcswitch_flow_s; +} sh_xnni0_vcswitch_flow_u_t; +#else +typedef union sh_xnni0_vcswitch_flow_u { + mmr_t sh_xnni0_vcswitch_flow_regval; + struct { + mmr_t reserved_4 : 29; + mmr_t async_fifoes : 1; + mmr_t disable_sync_bypass_out : 1; + mmr_t disable_sync_bypass_in : 1; + mmr_t reserved_3 : 7; + mmr_t iilb_vcfifo_switch : 1; + mmr_t reserved_2 : 7; + mmr_t md_vcfifo_switch : 1; + mmr_t reserved_1 : 7; + mmr_t pi_vcfifo_switch : 1; + mmr_t reserved_0 : 7; + mmr_t ni_vcfifo_dateline_switch : 1; + } sh_xnni0_vcswitch_flow_s; +} sh_xnni0_vcswitch_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_TIMER_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_timer_reg_u { + mmr_t sh_xnni0_timer_reg_regval; + struct { + mmr_t timeout_reg : 24; + mmr_t reserved_0 : 8; + mmr_t linkcleanup_reg : 1; + mmr_t reserved_1 : 31; + } sh_xnni0_timer_reg_s; +} sh_xnni0_timer_reg_u_t; +#else +typedef union sh_xnni0_timer_reg_u { + mmr_t sh_xnni0_timer_reg_regval; + struct { + mmr_t reserved_1 : 31; + mmr_t linkcleanup_reg : 1; + mmr_t reserved_0 : 8; + mmr_t timeout_reg : 24; + } sh_xnni0_timer_reg_s; +} sh_xnni0_timer_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_FIFO02_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_fifo02_flow_u { + mmr_t sh_xnni0_fifo02_flow_regval; + struct { + mmr_t count_vc0_limit : 4; + mmr_t reserved_0 : 4; + mmr_t count_vc0_dyn : 4; + mmr_t reserved_1 : 4; + mmr_t count_vc0_cap : 4; + mmr_t reserved_2 : 4; + mmr_t count_vc2_limit : 4; + mmr_t reserved_3 : 4; + mmr_t count_vc2_dyn : 4; + mmr_t reserved_4 : 4; + mmr_t count_vc2_cap : 4; + mmr_t reserved_5 : 20; + } sh_xnni0_fifo02_flow_s; +} sh_xnni0_fifo02_flow_u_t; +#else +typedef union sh_xnni0_fifo02_flow_u { + mmr_t sh_xnni0_fifo02_flow_regval; + struct { + mmr_t reserved_5 : 20; + mmr_t count_vc2_cap : 4; + mmr_t reserved_4 : 4; + mmr_t count_vc2_dyn : 4; + mmr_t reserved_3 : 4; + mmr_t count_vc2_limit : 4; + mmr_t reserved_2 : 4; + mmr_t count_vc0_cap : 4; + mmr_t reserved_1 : 4; + mmr_t count_vc0_dyn : 4; + mmr_t reserved_0 : 4; + mmr_t count_vc0_limit : 4; + } sh_xnni0_fifo02_flow_s; +} sh_xnni0_fifo02_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_FIFO13_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_fifo13_flow_u { + mmr_t sh_xnni0_fifo13_flow_regval; + struct { + mmr_t count_vc1_limit : 4; + mmr_t reserved_0 : 4; + mmr_t count_vc1_dyn : 4; + mmr_t reserved_1 : 4; + mmr_t count_vc1_cap : 4; + mmr_t reserved_2 : 4; + mmr_t count_vc3_limit : 4; + mmr_t reserved_3 : 4; + mmr_t count_vc3_dyn : 4; + mmr_t reserved_4 : 4; + mmr_t count_vc3_cap : 4; + mmr_t reserved_5 : 20; + } sh_xnni0_fifo13_flow_s; +} sh_xnni0_fifo13_flow_u_t; +#else +typedef union sh_xnni0_fifo13_flow_u { + mmr_t sh_xnni0_fifo13_flow_regval; + struct { + mmr_t reserved_5 : 20; + mmr_t count_vc3_cap : 4; + mmr_t reserved_4 : 4; + mmr_t count_vc3_dyn : 4; + mmr_t reserved_3 : 4; + mmr_t count_vc3_limit : 4; + mmr_t reserved_2 : 4; + mmr_t count_vc1_cap : 4; + mmr_t reserved_1 : 4; + mmr_t count_vc1_dyn : 4; + mmr_t reserved_0 : 4; + mmr_t count_vc1_limit : 4; + } sh_xnni0_fifo13_flow_s; +} sh_xnni0_fifo13_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_NI_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_ni_flow_u { + mmr_t sh_xnni0_ni_flow_regval; + struct { + mmr_t vc0_limit : 4; + mmr_t reserved_0 : 4; + mmr_t vc0_dyn : 4; + mmr_t vc0_cap : 4; + mmr_t vc1_limit : 4; + mmr_t reserved_1 : 4; + mmr_t vc1_dyn : 4; + mmr_t vc1_cap : 4; + mmr_t vc2_limit : 4; + mmr_t reserved_2 : 4; + mmr_t vc2_dyn : 4; + mmr_t vc2_cap : 4; + mmr_t vc3_limit : 4; + mmr_t reserved_3 : 4; + mmr_t vc3_dyn : 4; + mmr_t vc3_cap : 4; + } sh_xnni0_ni_flow_s; +} sh_xnni0_ni_flow_u_t; +#else +typedef union sh_xnni0_ni_flow_u { + mmr_t sh_xnni0_ni_flow_regval; + struct { + mmr_t vc3_cap : 4; + mmr_t vc3_dyn : 4; + mmr_t reserved_3 : 4; + mmr_t vc3_limit : 4; + mmr_t vc2_cap : 4; + mmr_t vc2_dyn : 4; + mmr_t reserved_2 : 4; + mmr_t vc2_limit : 4; + mmr_t vc1_cap : 4; + mmr_t vc1_dyn : 4; + mmr_t reserved_1 : 4; + mmr_t vc1_limit : 4; + mmr_t vc0_cap : 4; + mmr_t vc0_dyn : 4; + mmr_t reserved_0 : 4; + mmr_t vc0_limit : 4; + } sh_xnni0_ni_flow_s; +} sh_xnni0_ni_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_DEAD_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_dead_flow_u { + mmr_t sh_xnni0_dead_flow_regval; + struct { + mmr_t vc0_limit : 4; + mmr_t reserved_0 : 4; + mmr_t vc0_dyn : 4; + mmr_t vc0_cap : 4; + mmr_t vc1_limit : 4; + mmr_t reserved_1 : 4; + mmr_t vc1_dyn : 4; + mmr_t vc1_cap : 4; + mmr_t vc2_limit : 4; + mmr_t reserved_2 : 4; + mmr_t vc2_dyn : 4; + mmr_t vc2_cap : 4; + mmr_t vc3_limit : 4; + mmr_t reserved_3 : 4; + mmr_t vc3_dyn : 4; + mmr_t vc3_cap : 4; + } sh_xnni0_dead_flow_s; +} sh_xnni0_dead_flow_u_t; +#else +typedef union sh_xnni0_dead_flow_u { + mmr_t sh_xnni0_dead_flow_regval; + struct { + mmr_t vc3_cap : 4; + mmr_t vc3_dyn : 4; + mmr_t reserved_3 : 4; + mmr_t vc3_limit : 4; + mmr_t vc2_cap : 4; + mmr_t vc2_dyn : 4; + mmr_t reserved_2 : 4; + mmr_t vc2_limit : 4; + mmr_t vc1_cap : 4; + mmr_t vc1_dyn : 4; + mmr_t reserved_1 : 4; + mmr_t vc1_limit : 4; + mmr_t vc0_cap : 4; + mmr_t vc0_dyn : 4; + mmr_t reserved_0 : 4; + mmr_t vc0_limit : 4; + } sh_xnni0_dead_flow_s; +} sh_xnni0_dead_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI0_INJECT_AGE" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni0_inject_age_u { + mmr_t sh_xnni0_inject_age_regval; + struct { + mmr_t request_inject : 8; + mmr_t reply_inject : 8; + mmr_t reserved_0 : 48; + } sh_xnni0_inject_age_s; +} sh_xnni0_inject_age_u_t; +#else +typedef union sh_xnni0_inject_age_u { + mmr_t sh_xnni0_inject_age_regval; + struct { + mmr_t reserved_0 : 48; + mmr_t reply_inject : 8; + mmr_t request_inject : 8; + } sh_xnni0_inject_age_s; +} sh_xnni0_inject_age_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_to_pi_intra_flow_debit_u { + mmr_t sh_xnni1_to_pi_intra_flow_debit_regval; + struct { + mmr_t vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t vc0_force_cred : 1; + mmr_t vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_4 : 9; + mmr_t vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_6 : 1; + } sh_xnni1_to_pi_intra_flow_debit_s; +} sh_xnni1_to_pi_intra_flow_debit_u_t; +#else +typedef union sh_xnni1_to_pi_intra_flow_debit_u { + mmr_t sh_xnni1_to_pi_intra_flow_debit_regval; + struct { + mmr_t reserved_6 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 9; + mmr_t vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_2 : 8; + mmr_t vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t vc2_withhold : 6; + mmr_t vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t vc0_withhold : 6; + } sh_xnni1_to_pi_intra_flow_debit_s; +} sh_xnni1_to_pi_intra_flow_debit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_to_md_intra_flow_debit_u { + mmr_t sh_xnni1_to_md_intra_flow_debit_regval; + struct { + mmr_t vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t vc0_force_cred : 1; + mmr_t vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_4 : 9; + mmr_t vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_6 : 1; + } sh_xnni1_to_md_intra_flow_debit_s; +} sh_xnni1_to_md_intra_flow_debit_u_t; +#else +typedef union sh_xnni1_to_md_intra_flow_debit_u { + mmr_t sh_xnni1_to_md_intra_flow_debit_regval; + struct { + mmr_t reserved_6 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 9; + mmr_t vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_2 : 8; + mmr_t vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t vc2_withhold : 6; + mmr_t vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t vc0_withhold : 6; + } sh_xnni1_to_md_intra_flow_debit_s; +} sh_xnni1_to_md_intra_flow_debit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_to_iilb_intra_flow_debit_u { + mmr_t sh_xnni1_to_iilb_intra_flow_debit_regval; + struct { + mmr_t vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t vc0_force_cred : 1; + mmr_t vc2_withhold : 6; + mmr_t reserved_1 : 1; + mmr_t vc2_force_cred : 1; + mmr_t reserved_2 : 8; + mmr_t vc0_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_4 : 9; + mmr_t vc2_dyn : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_6 : 1; + } sh_xnni1_to_iilb_intra_flow_debit_s; +} sh_xnni1_to_iilb_intra_flow_debit_u_t; +#else +typedef union sh_xnni1_to_iilb_intra_flow_debit_u { + mmr_t sh_xnni1_to_iilb_intra_flow_debit_regval; + struct { + mmr_t reserved_6 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 9; + mmr_t vc0_cap : 7; + mmr_t reserved_3 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_2 : 8; + mmr_t vc2_force_cred : 1; + mmr_t reserved_1 : 1; + mmr_t vc2_withhold : 6; + mmr_t vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t vc0_withhold : 6; + } sh_xnni1_to_iilb_intra_flow_debit_s; +} sh_xnni1_to_iilb_intra_flow_debit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_fr_pi_intra_flow_credit_u { + mmr_t sh_xnni1_fr_pi_intra_flow_credit_regval; + struct { + mmr_t vc0_test : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 17; + } sh_xnni1_fr_pi_intra_flow_credit_s; +} sh_xnni1_fr_pi_intra_flow_credit_u_t; +#else +typedef union sh_xnni1_fr_pi_intra_flow_credit_u { + mmr_t sh_xnni1_fr_pi_intra_flow_credit_regval; + struct { + mmr_t reserved_5 : 17; + mmr_t vc2_cap : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_2 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_test : 7; + } sh_xnni1_fr_pi_intra_flow_credit_s; +} sh_xnni1_fr_pi_intra_flow_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_fr_md_intra_flow_credit_u { + mmr_t sh_xnni1_fr_md_intra_flow_credit_regval; + struct { + mmr_t vc0_test : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 17; + } sh_xnni1_fr_md_intra_flow_credit_s; +} sh_xnni1_fr_md_intra_flow_credit_u_t; +#else +typedef union sh_xnni1_fr_md_intra_flow_credit_u { + mmr_t sh_xnni1_fr_md_intra_flow_credit_regval; + struct { + mmr_t reserved_5 : 17; + mmr_t vc2_cap : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_2 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_test : 7; + } sh_xnni1_fr_md_intra_flow_credit_s; +} sh_xnni1_fr_md_intra_flow_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_fr_iilb_intra_flow_credit_u { + mmr_t sh_xnni1_fr_iilb_intra_flow_credit_regval; + struct { + mmr_t vc0_test : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_2 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_cap : 7; + mmr_t reserved_5 : 17; + } sh_xnni1_fr_iilb_intra_flow_credit_s; +} sh_xnni1_fr_iilb_intra_flow_credit_u_t; +#else +typedef union sh_xnni1_fr_iilb_intra_flow_credit_u { + mmr_t sh_xnni1_fr_iilb_intra_flow_credit_regval; + struct { + mmr_t reserved_5 : 17; + mmr_t vc2_cap : 7; + mmr_t reserved_4 : 1; + mmr_t vc2_dyn : 7; + mmr_t reserved_3 : 1; + mmr_t vc2_test : 7; + mmr_t reserved_2 : 1; + mmr_t vc0_cap : 7; + mmr_t reserved_1 : 1; + mmr_t vc0_dyn : 7; + mmr_t reserved_0 : 1; + mmr_t vc0_test : 7; + } sh_xnni1_fr_iilb_intra_flow_credit_s; +} sh_xnni1_fr_iilb_intra_flow_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_0_INTRANI_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_0_intrani_flow_u { + mmr_t sh_xnni1_0_intrani_flow_regval; + struct { + mmr_t debit_vc0_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_1 : 56; + } sh_xnni1_0_intrani_flow_s; +} sh_xnni1_0_intrani_flow_u_t; +#else +typedef union sh_xnni1_0_intrani_flow_u { + mmr_t sh_xnni1_0_intrani_flow_regval; + struct { + mmr_t reserved_1 : 56; + mmr_t debit_vc0_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc0_withhold : 6; + } sh_xnni1_0_intrani_flow_s; +} sh_xnni1_0_intrani_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_1_INTRANI_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_1_intrani_flow_u { + mmr_t sh_xnni1_1_intrani_flow_regval; + struct { + mmr_t debit_vc1_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc1_force_cred : 1; + mmr_t reserved_1 : 56; + } sh_xnni1_1_intrani_flow_s; +} sh_xnni1_1_intrani_flow_u_t; +#else +typedef union sh_xnni1_1_intrani_flow_u { + mmr_t sh_xnni1_1_intrani_flow_regval; + struct { + mmr_t reserved_1 : 56; + mmr_t debit_vc1_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc1_withhold : 6; + } sh_xnni1_1_intrani_flow_s; +} sh_xnni1_1_intrani_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_2_INTRANI_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_2_intrani_flow_u { + mmr_t sh_xnni1_2_intrani_flow_regval; + struct { + mmr_t debit_vc2_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_1 : 56; + } sh_xnni1_2_intrani_flow_s; +} sh_xnni1_2_intrani_flow_u_t; +#else +typedef union sh_xnni1_2_intrani_flow_u { + mmr_t sh_xnni1_2_intrani_flow_regval; + struct { + mmr_t reserved_1 : 56; + mmr_t debit_vc2_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc2_withhold : 6; + } sh_xnni1_2_intrani_flow_s; +} sh_xnni1_2_intrani_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_3_INTRANI_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_3_intrani_flow_u { + mmr_t sh_xnni1_3_intrani_flow_regval; + struct { + mmr_t debit_vc3_withhold : 6; + mmr_t reserved_0 : 1; + mmr_t debit_vc3_force_cred : 1; + mmr_t reserved_1 : 56; + } sh_xnni1_3_intrani_flow_s; +} sh_xnni1_3_intrani_flow_u_t; +#else +typedef union sh_xnni1_3_intrani_flow_u { + mmr_t sh_xnni1_3_intrani_flow_regval; + struct { + mmr_t reserved_1 : 56; + mmr_t debit_vc3_force_cred : 1; + mmr_t reserved_0 : 1; + mmr_t debit_vc3_withhold : 6; + } sh_xnni1_3_intrani_flow_s; +} sh_xnni1_3_intrani_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_VCSWITCH_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_vcswitch_flow_u { + mmr_t sh_xnni1_vcswitch_flow_regval; + struct { + mmr_t ni_vcfifo_dateline_switch : 1; + mmr_t reserved_0 : 7; + mmr_t pi_vcfifo_switch : 1; + mmr_t reserved_1 : 7; + mmr_t md_vcfifo_switch : 1; + mmr_t reserved_2 : 7; + mmr_t iilb_vcfifo_switch : 1; + mmr_t reserved_3 : 7; + mmr_t disable_sync_bypass_in : 1; + mmr_t disable_sync_bypass_out : 1; + mmr_t async_fifoes : 1; + mmr_t reserved_4 : 29; + } sh_xnni1_vcswitch_flow_s; +} sh_xnni1_vcswitch_flow_u_t; +#else +typedef union sh_xnni1_vcswitch_flow_u { + mmr_t sh_xnni1_vcswitch_flow_regval; + struct { + mmr_t reserved_4 : 29; + mmr_t async_fifoes : 1; + mmr_t disable_sync_bypass_out : 1; + mmr_t disable_sync_bypass_in : 1; + mmr_t reserved_3 : 7; + mmr_t iilb_vcfifo_switch : 1; + mmr_t reserved_2 : 7; + mmr_t md_vcfifo_switch : 1; + mmr_t reserved_1 : 7; + mmr_t pi_vcfifo_switch : 1; + mmr_t reserved_0 : 7; + mmr_t ni_vcfifo_dateline_switch : 1; + } sh_xnni1_vcswitch_flow_s; +} sh_xnni1_vcswitch_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_TIMER_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_timer_reg_u { + mmr_t sh_xnni1_timer_reg_regval; + struct { + mmr_t timeout_reg : 24; + mmr_t reserved_0 : 8; + mmr_t linkcleanup_reg : 1; + mmr_t reserved_1 : 31; + } sh_xnni1_timer_reg_s; +} sh_xnni1_timer_reg_u_t; +#else +typedef union sh_xnni1_timer_reg_u { + mmr_t sh_xnni1_timer_reg_regval; + struct { + mmr_t reserved_1 : 31; + mmr_t linkcleanup_reg : 1; + mmr_t reserved_0 : 8; + mmr_t timeout_reg : 24; + } sh_xnni1_timer_reg_s; +} sh_xnni1_timer_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_FIFO02_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_fifo02_flow_u { + mmr_t sh_xnni1_fifo02_flow_regval; + struct { + mmr_t count_vc0_limit : 4; + mmr_t reserved_0 : 4; + mmr_t count_vc0_dyn : 4; + mmr_t reserved_1 : 4; + mmr_t count_vc0_cap : 4; + mmr_t reserved_2 : 4; + mmr_t count_vc2_limit : 4; + mmr_t reserved_3 : 4; + mmr_t count_vc2_dyn : 4; + mmr_t reserved_4 : 4; + mmr_t count_vc2_cap : 4; + mmr_t reserved_5 : 20; + } sh_xnni1_fifo02_flow_s; +} sh_xnni1_fifo02_flow_u_t; +#else +typedef union sh_xnni1_fifo02_flow_u { + mmr_t sh_xnni1_fifo02_flow_regval; + struct { + mmr_t reserved_5 : 20; + mmr_t count_vc2_cap : 4; + mmr_t reserved_4 : 4; + mmr_t count_vc2_dyn : 4; + mmr_t reserved_3 : 4; + mmr_t count_vc2_limit : 4; + mmr_t reserved_2 : 4; + mmr_t count_vc0_cap : 4; + mmr_t reserved_1 : 4; + mmr_t count_vc0_dyn : 4; + mmr_t reserved_0 : 4; + mmr_t count_vc0_limit : 4; + } sh_xnni1_fifo02_flow_s; +} sh_xnni1_fifo02_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_FIFO13_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_fifo13_flow_u { + mmr_t sh_xnni1_fifo13_flow_regval; + struct { + mmr_t count_vc1_limit : 4; + mmr_t reserved_0 : 4; + mmr_t count_vc1_dyn : 4; + mmr_t reserved_1 : 4; + mmr_t count_vc1_cap : 4; + mmr_t reserved_2 : 4; + mmr_t count_vc3_limit : 4; + mmr_t reserved_3 : 4; + mmr_t count_vc3_dyn : 4; + mmr_t reserved_4 : 4; + mmr_t count_vc3_cap : 4; + mmr_t reserved_5 : 20; + } sh_xnni1_fifo13_flow_s; +} sh_xnni1_fifo13_flow_u_t; +#else +typedef union sh_xnni1_fifo13_flow_u { + mmr_t sh_xnni1_fifo13_flow_regval; + struct { + mmr_t reserved_5 : 20; + mmr_t count_vc3_cap : 4; + mmr_t reserved_4 : 4; + mmr_t count_vc3_dyn : 4; + mmr_t reserved_3 : 4; + mmr_t count_vc3_limit : 4; + mmr_t reserved_2 : 4; + mmr_t count_vc1_cap : 4; + mmr_t reserved_1 : 4; + mmr_t count_vc1_dyn : 4; + mmr_t reserved_0 : 4; + mmr_t count_vc1_limit : 4; + } sh_xnni1_fifo13_flow_s; +} sh_xnni1_fifo13_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_NI_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_ni_flow_u { + mmr_t sh_xnni1_ni_flow_regval; + struct { + mmr_t vc0_limit : 4; + mmr_t reserved_0 : 4; + mmr_t vc0_dyn : 4; + mmr_t vc0_cap : 4; + mmr_t vc1_limit : 4; + mmr_t reserved_1 : 4; + mmr_t vc1_dyn : 4; + mmr_t vc1_cap : 4; + mmr_t vc2_limit : 4; + mmr_t reserved_2 : 4; + mmr_t vc2_dyn : 4; + mmr_t vc2_cap : 4; + mmr_t vc3_limit : 4; + mmr_t reserved_3 : 4; + mmr_t vc3_dyn : 4; + mmr_t vc3_cap : 4; + } sh_xnni1_ni_flow_s; +} sh_xnni1_ni_flow_u_t; +#else +typedef union sh_xnni1_ni_flow_u { + mmr_t sh_xnni1_ni_flow_regval; + struct { + mmr_t vc3_cap : 4; + mmr_t vc3_dyn : 4; + mmr_t reserved_3 : 4; + mmr_t vc3_limit : 4; + mmr_t vc2_cap : 4; + mmr_t vc2_dyn : 4; + mmr_t reserved_2 : 4; + mmr_t vc2_limit : 4; + mmr_t vc1_cap : 4; + mmr_t vc1_dyn : 4; + mmr_t reserved_1 : 4; + mmr_t vc1_limit : 4; + mmr_t vc0_cap : 4; + mmr_t vc0_dyn : 4; + mmr_t reserved_0 : 4; + mmr_t vc0_limit : 4; + } sh_xnni1_ni_flow_s; +} sh_xnni1_ni_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_DEAD_FLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_dead_flow_u { + mmr_t sh_xnni1_dead_flow_regval; + struct { + mmr_t vc0_limit : 4; + mmr_t reserved_0 : 4; + mmr_t vc0_dyn : 4; + mmr_t vc0_cap : 4; + mmr_t vc1_limit : 4; + mmr_t reserved_1 : 4; + mmr_t vc1_dyn : 4; + mmr_t vc1_cap : 4; + mmr_t vc2_limit : 4; + mmr_t reserved_2 : 4; + mmr_t vc2_dyn : 4; + mmr_t vc2_cap : 4; + mmr_t vc3_limit : 4; + mmr_t reserved_3 : 4; + mmr_t vc3_dyn : 4; + mmr_t vc3_cap : 4; + } sh_xnni1_dead_flow_s; +} sh_xnni1_dead_flow_u_t; +#else +typedef union sh_xnni1_dead_flow_u { + mmr_t sh_xnni1_dead_flow_regval; + struct { + mmr_t vc3_cap : 4; + mmr_t vc3_dyn : 4; + mmr_t reserved_3 : 4; + mmr_t vc3_limit : 4; + mmr_t vc2_cap : 4; + mmr_t vc2_dyn : 4; + mmr_t reserved_2 : 4; + mmr_t vc2_limit : 4; + mmr_t vc1_cap : 4; + mmr_t vc1_dyn : 4; + mmr_t reserved_1 : 4; + mmr_t vc1_limit : 4; + mmr_t vc0_cap : 4; + mmr_t vc0_dyn : 4; + mmr_t reserved_0 : 4; + mmr_t vc0_limit : 4; + } sh_xnni1_dead_flow_s; +} sh_xnni1_dead_flow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNNI1_INJECT_AGE" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnni1_inject_age_u { + mmr_t sh_xnni1_inject_age_regval; + struct { + mmr_t request_inject : 8; + mmr_t reply_inject : 8; + mmr_t reserved_0 : 48; + } sh_xnni1_inject_age_s; +} sh_xnni1_inject_age_u_t; +#else +typedef union sh_xnni1_inject_age_u { + mmr_t sh_xnni1_inject_age_regval; + struct { + mmr_t reserved_0 : 48; + mmr_t reply_inject : 8; + mmr_t request_inject : 8; + } sh_xnni1_inject_age_s; +} sh_xnni1_inject_age_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_DEBUG_SEL" */ +/* XN Debug Port Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_debug_sel_u { + mmr_t sh_xn_debug_sel_regval; + struct { + mmr_t nibble0_rlm_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_rlm_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_rlm_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_rlm_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_rlm_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_rlm_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_rlm_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_rlm_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t trigger_enable : 1; + } sh_xn_debug_sel_s; +} sh_xn_debug_sel_u_t; +#else +typedef union sh_xn_debug_sel_u { + mmr_t sh_xn_debug_sel_regval; + struct { + mmr_t trigger_enable : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_rlm_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_rlm_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_rlm_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_rlm_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_rlm_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_rlm_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_rlm_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_rlm_sel : 3; + } sh_xn_debug_sel_s; +} sh_xn_debug_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_DEBUG_TRIG_SEL" */ +/* XN Debug trigger Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_debug_trig_sel_u { + mmr_t sh_xn_debug_trig_sel_regval; + struct { + mmr_t trigger0_rlm_sel : 3; + mmr_t reserved_0 : 1; + mmr_t trigger0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t trigger1_rlm_sel : 3; + mmr_t reserved_2 : 1; + mmr_t trigger1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t trigger2_rlm_sel : 3; + mmr_t reserved_4 : 1; + mmr_t trigger2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t trigger3_rlm_sel : 3; + mmr_t reserved_6 : 1; + mmr_t trigger3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t trigger4_rlm_sel : 3; + mmr_t reserved_8 : 1; + mmr_t trigger4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t trigger5_rlm_sel : 3; + mmr_t reserved_10 : 1; + mmr_t trigger5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t trigger6_rlm_sel : 3; + mmr_t reserved_12 : 1; + mmr_t trigger6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t trigger7_rlm_sel : 3; + mmr_t reserved_14 : 1; + mmr_t trigger7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_xn_debug_trig_sel_s; +} sh_xn_debug_trig_sel_u_t; +#else +typedef union sh_xn_debug_trig_sel_u { + mmr_t sh_xn_debug_trig_sel_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t trigger7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t trigger7_rlm_sel : 3; + mmr_t reserved_13 : 1; + mmr_t trigger6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t trigger6_rlm_sel : 3; + mmr_t reserved_11 : 1; + mmr_t trigger5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t trigger5_rlm_sel : 3; + mmr_t reserved_9 : 1; + mmr_t trigger4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t trigger4_rlm_sel : 3; + mmr_t reserved_7 : 1; + mmr_t trigger3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t trigger3_rlm_sel : 3; + mmr_t reserved_5 : 1; + mmr_t trigger2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t trigger2_rlm_sel : 3; + mmr_t reserved_3 : 1; + mmr_t trigger1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t trigger1_rlm_sel : 3; + mmr_t reserved_1 : 1; + mmr_t trigger0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t trigger0_rlm_sel : 3; + } sh_xn_debug_trig_sel_s; +} sh_xn_debug_trig_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_TRIGGER_COMPARE" */ +/* XN Debug Compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_trigger_compare_u { + mmr_t sh_xn_trigger_compare_regval; + struct { + mmr_t mask : 32; + mmr_t reserved_0 : 32; + } sh_xn_trigger_compare_s; +} sh_xn_trigger_compare_u_t; +#else +typedef union sh_xn_trigger_compare_u { + mmr_t sh_xn_trigger_compare_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t mask : 32; + } sh_xn_trigger_compare_s; +} sh_xn_trigger_compare_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_TRIGGER_DATA" */ +/* XN Debug Compare Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_trigger_data_u { + mmr_t sh_xn_trigger_data_regval; + struct { + mmr_t compare_pattern : 32; + mmr_t reserved_0 : 32; + } sh_xn_trigger_data_s; +} sh_xn_trigger_data_u_t; +#else +typedef union sh_xn_trigger_data_u { + mmr_t sh_xn_trigger_data_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t compare_pattern : 32; + } sh_xn_trigger_data_s; +} sh_xn_trigger_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_DEBUG_SEL" */ +/* XN IILB Debug Port Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_debug_sel_u { + mmr_t sh_xn_iilb_debug_sel_regval; + struct { + mmr_t nibble0_input_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_xn_iilb_debug_sel_s; +} sh_xn_iilb_debug_sel_u_t; +#else +typedef union sh_xn_iilb_debug_sel_u { + mmr_t sh_xn_iilb_debug_sel_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_input_sel : 3; + } sh_xn_iilb_debug_sel_s; +} sh_xn_iilb_debug_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_DEBUG_SEL" */ +/* XN PI Debug Port Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_debug_sel_u { + mmr_t sh_xn_pi_debug_sel_regval; + struct { + mmr_t nibble0_input_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_xn_pi_debug_sel_s; +} sh_xn_pi_debug_sel_u_t; +#else +typedef union sh_xn_pi_debug_sel_u { + mmr_t sh_xn_pi_debug_sel_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_input_sel : 3; + } sh_xn_pi_debug_sel_s; +} sh_xn_pi_debug_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_DEBUG_SEL" */ +/* XN MD Debug Port Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_debug_sel_u { + mmr_t sh_xn_md_debug_sel_regval; + struct { + mmr_t nibble0_input_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_xn_md_debug_sel_s; +} sh_xn_md_debug_sel_u_t; +#else +typedef union sh_xn_md_debug_sel_u { + mmr_t sh_xn_md_debug_sel_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_input_sel : 3; + } sh_xn_md_debug_sel_s; +} sh_xn_md_debug_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_DEBUG_SEL" */ +/* XN NI0 Debug Port Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_debug_sel_u { + mmr_t sh_xn_ni0_debug_sel_regval; + struct { + mmr_t nibble0_input_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_xn_ni0_debug_sel_s; +} sh_xn_ni0_debug_sel_u_t; +#else +typedef union sh_xn_ni0_debug_sel_u { + mmr_t sh_xn_ni0_debug_sel_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_input_sel : 3; + } sh_xn_ni0_debug_sel_s; +} sh_xn_ni0_debug_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_DEBUG_SEL" */ +/* XN NI1 Debug Port Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_debug_sel_u { + mmr_t sh_xn_ni1_debug_sel_regval; + struct { + mmr_t nibble0_input_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_xn_ni1_debug_sel_s; +} sh_xn_ni1_debug_sel_u_t; +#else +typedef union sh_xn_ni1_debug_sel_u { + mmr_t sh_xn_ni1_debug_sel_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_input_sel : 3; + } sh_xn_ni1_debug_sel_s; +} sh_xn_ni1_debug_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_LB_CMP_EXP_DATA0" */ +/* IILB compare LB input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_lb_cmp_exp_data0_u { + mmr_t sh_xn_iilb_lb_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_lb_cmp_exp_data0_s; +} sh_xn_iilb_lb_cmp_exp_data0_u_t; +#else +typedef union sh_xn_iilb_lb_cmp_exp_data0_u { + mmr_t sh_xn_iilb_lb_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_lb_cmp_exp_data0_s; +} sh_xn_iilb_lb_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_LB_CMP_EXP_DATA1" */ +/* IILB compare LB input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_lb_cmp_exp_data1_u { + mmr_t sh_xn_iilb_lb_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_lb_cmp_exp_data1_s; +} sh_xn_iilb_lb_cmp_exp_data1_u_t; +#else +typedef union sh_xn_iilb_lb_cmp_exp_data1_u { + mmr_t sh_xn_iilb_lb_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_lb_cmp_exp_data1_s; +} sh_xn_iilb_lb_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_LB_CMP_ENABLE0" */ +/* IILB compare LB input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_lb_cmp_enable0_u { + mmr_t sh_xn_iilb_lb_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_lb_cmp_enable0_s; +} sh_xn_iilb_lb_cmp_enable0_u_t; +#else +typedef union sh_xn_iilb_lb_cmp_enable0_u { + mmr_t sh_xn_iilb_lb_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_lb_cmp_enable0_s; +} sh_xn_iilb_lb_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_LB_CMP_ENABLE1" */ +/* IILB compare LB input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_lb_cmp_enable1_u { + mmr_t sh_xn_iilb_lb_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_lb_cmp_enable1_s; +} sh_xn_iilb_lb_cmp_enable1_u_t; +#else +typedef union sh_xn_iilb_lb_cmp_enable1_u { + mmr_t sh_xn_iilb_lb_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_lb_cmp_enable1_s; +} sh_xn_iilb_lb_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_II_CMP_EXP_DATA0" */ +/* IILB compare II input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ii_cmp_exp_data0_u { + mmr_t sh_xn_iilb_ii_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ii_cmp_exp_data0_s; +} sh_xn_iilb_ii_cmp_exp_data0_u_t; +#else +typedef union sh_xn_iilb_ii_cmp_exp_data0_u { + mmr_t sh_xn_iilb_ii_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ii_cmp_exp_data0_s; +} sh_xn_iilb_ii_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_II_CMP_EXP_DATA1" */ +/* IILB compare II input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ii_cmp_exp_data1_u { + mmr_t sh_xn_iilb_ii_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ii_cmp_exp_data1_s; +} sh_xn_iilb_ii_cmp_exp_data1_u_t; +#else +typedef union sh_xn_iilb_ii_cmp_exp_data1_u { + mmr_t sh_xn_iilb_ii_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ii_cmp_exp_data1_s; +} sh_xn_iilb_ii_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_II_CMP_ENABLE0" */ +/* IILB compare II input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ii_cmp_enable0_u { + mmr_t sh_xn_iilb_ii_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ii_cmp_enable0_s; +} sh_xn_iilb_ii_cmp_enable0_u_t; +#else +typedef union sh_xn_iilb_ii_cmp_enable0_u { + mmr_t sh_xn_iilb_ii_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ii_cmp_enable0_s; +} sh_xn_iilb_ii_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_II_CMP_ENABLE1" */ +/* IILB compare II input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ii_cmp_enable1_u { + mmr_t sh_xn_iilb_ii_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ii_cmp_enable1_s; +} sh_xn_iilb_ii_cmp_enable1_u_t; +#else +typedef union sh_xn_iilb_ii_cmp_enable1_u { + mmr_t sh_xn_iilb_ii_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ii_cmp_enable1_s; +} sh_xn_iilb_ii_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_MD_CMP_EXP_DATA0" */ +/* IILB compare MD input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_md_cmp_exp_data0_u { + mmr_t sh_xn_iilb_md_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_md_cmp_exp_data0_s; +} sh_xn_iilb_md_cmp_exp_data0_u_t; +#else +typedef union sh_xn_iilb_md_cmp_exp_data0_u { + mmr_t sh_xn_iilb_md_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_md_cmp_exp_data0_s; +} sh_xn_iilb_md_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_MD_CMP_EXP_DATA1" */ +/* IILB compare MD input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_md_cmp_exp_data1_u { + mmr_t sh_xn_iilb_md_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_md_cmp_exp_data1_s; +} sh_xn_iilb_md_cmp_exp_data1_u_t; +#else +typedef union sh_xn_iilb_md_cmp_exp_data1_u { + mmr_t sh_xn_iilb_md_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_md_cmp_exp_data1_s; +} sh_xn_iilb_md_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_MD_CMP_ENABLE0" */ +/* IILB compare MD input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_md_cmp_enable0_u { + mmr_t sh_xn_iilb_md_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_md_cmp_enable0_s; +} sh_xn_iilb_md_cmp_enable0_u_t; +#else +typedef union sh_xn_iilb_md_cmp_enable0_u { + mmr_t sh_xn_iilb_md_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_md_cmp_enable0_s; +} sh_xn_iilb_md_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_MD_CMP_ENABLE1" */ +/* IILB compare MD input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_md_cmp_enable1_u { + mmr_t sh_xn_iilb_md_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_md_cmp_enable1_s; +} sh_xn_iilb_md_cmp_enable1_u_t; +#else +typedef union sh_xn_iilb_md_cmp_enable1_u { + mmr_t sh_xn_iilb_md_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_md_cmp_enable1_s; +} sh_xn_iilb_md_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_PI_CMP_EXP_DATA0" */ +/* IILB compare PI input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_pi_cmp_exp_data0_u { + mmr_t sh_xn_iilb_pi_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_pi_cmp_exp_data0_s; +} sh_xn_iilb_pi_cmp_exp_data0_u_t; +#else +typedef union sh_xn_iilb_pi_cmp_exp_data0_u { + mmr_t sh_xn_iilb_pi_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_pi_cmp_exp_data0_s; +} sh_xn_iilb_pi_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_PI_CMP_EXP_DATA1" */ +/* IILB compare PI input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_pi_cmp_exp_data1_u { + mmr_t sh_xn_iilb_pi_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_pi_cmp_exp_data1_s; +} sh_xn_iilb_pi_cmp_exp_data1_u_t; +#else +typedef union sh_xn_iilb_pi_cmp_exp_data1_u { + mmr_t sh_xn_iilb_pi_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_pi_cmp_exp_data1_s; +} sh_xn_iilb_pi_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_PI_CMP_ENABLE0" */ +/* IILB compare PI input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_pi_cmp_enable0_u { + mmr_t sh_xn_iilb_pi_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_pi_cmp_enable0_s; +} sh_xn_iilb_pi_cmp_enable0_u_t; +#else +typedef union sh_xn_iilb_pi_cmp_enable0_u { + mmr_t sh_xn_iilb_pi_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_pi_cmp_enable0_s; +} sh_xn_iilb_pi_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_PI_CMP_ENABLE1" */ +/* IILB compare PI input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_pi_cmp_enable1_u { + mmr_t sh_xn_iilb_pi_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_pi_cmp_enable1_s; +} sh_xn_iilb_pi_cmp_enable1_u_t; +#else +typedef union sh_xn_iilb_pi_cmp_enable1_u { + mmr_t sh_xn_iilb_pi_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_pi_cmp_enable1_s; +} sh_xn_iilb_pi_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI0_CMP_EXP_DATA0" */ +/* IILB compare NI0 input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ni0_cmp_exp_data0_u { + mmr_t sh_xn_iilb_ni0_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ni0_cmp_exp_data0_s; +} sh_xn_iilb_ni0_cmp_exp_data0_u_t; +#else +typedef union sh_xn_iilb_ni0_cmp_exp_data0_u { + mmr_t sh_xn_iilb_ni0_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ni0_cmp_exp_data0_s; +} sh_xn_iilb_ni0_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI0_CMP_EXP_DATA1" */ +/* IILB compare NI0 input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ni0_cmp_exp_data1_u { + mmr_t sh_xn_iilb_ni0_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ni0_cmp_exp_data1_s; +} sh_xn_iilb_ni0_cmp_exp_data1_u_t; +#else +typedef union sh_xn_iilb_ni0_cmp_exp_data1_u { + mmr_t sh_xn_iilb_ni0_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ni0_cmp_exp_data1_s; +} sh_xn_iilb_ni0_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI0_CMP_ENABLE0" */ +/* IILB compare NI0 input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ni0_cmp_enable0_u { + mmr_t sh_xn_iilb_ni0_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ni0_cmp_enable0_s; +} sh_xn_iilb_ni0_cmp_enable0_u_t; +#else +typedef union sh_xn_iilb_ni0_cmp_enable0_u { + mmr_t sh_xn_iilb_ni0_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ni0_cmp_enable0_s; +} sh_xn_iilb_ni0_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI0_CMP_ENABLE1" */ +/* IILB compare NI0 input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ni0_cmp_enable1_u { + mmr_t sh_xn_iilb_ni0_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ni0_cmp_enable1_s; +} sh_xn_iilb_ni0_cmp_enable1_u_t; +#else +typedef union sh_xn_iilb_ni0_cmp_enable1_u { + mmr_t sh_xn_iilb_ni0_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ni0_cmp_enable1_s; +} sh_xn_iilb_ni0_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI1_CMP_EXP_DATA0" */ +/* IILB compare NI1 input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ni1_cmp_exp_data0_u { + mmr_t sh_xn_iilb_ni1_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ni1_cmp_exp_data0_s; +} sh_xn_iilb_ni1_cmp_exp_data0_u_t; +#else +typedef union sh_xn_iilb_ni1_cmp_exp_data0_u { + mmr_t sh_xn_iilb_ni1_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ni1_cmp_exp_data0_s; +} sh_xn_iilb_ni1_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI1_CMP_EXP_DATA1" */ +/* IILB compare NI1 input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ni1_cmp_exp_data1_u { + mmr_t sh_xn_iilb_ni1_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ni1_cmp_exp_data1_s; +} sh_xn_iilb_ni1_cmp_exp_data1_u_t; +#else +typedef union sh_xn_iilb_ni1_cmp_exp_data1_u { + mmr_t sh_xn_iilb_ni1_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_iilb_ni1_cmp_exp_data1_s; +} sh_xn_iilb_ni1_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI1_CMP_ENABLE0" */ +/* IILB compare NI1 input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ni1_cmp_enable0_u { + mmr_t sh_xn_iilb_ni1_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ni1_cmp_enable0_s; +} sh_xn_iilb_ni1_cmp_enable0_u_t; +#else +typedef union sh_xn_iilb_ni1_cmp_enable0_u { + mmr_t sh_xn_iilb_ni1_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ni1_cmp_enable0_s; +} sh_xn_iilb_ni1_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_IILB_NI1_CMP_ENABLE1" */ +/* IILB compare NI1 input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_iilb_ni1_cmp_enable1_u { + mmr_t sh_xn_iilb_ni1_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ni1_cmp_enable1_s; +} sh_xn_iilb_ni1_cmp_enable1_u_t; +#else +typedef union sh_xn_iilb_ni1_cmp_enable1_u { + mmr_t sh_xn_iilb_ni1_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_iilb_ni1_cmp_enable1_s; +} sh_xn_iilb_ni1_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_IILB_CMP_EXP_DATA0" */ +/* MD compare IILB input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_iilb_cmp_exp_data0_u { + mmr_t sh_xn_md_iilb_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_md_iilb_cmp_exp_data0_s; +} sh_xn_md_iilb_cmp_exp_data0_u_t; +#else +typedef union sh_xn_md_iilb_cmp_exp_data0_u { + mmr_t sh_xn_md_iilb_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_md_iilb_cmp_exp_data0_s; +} sh_xn_md_iilb_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_IILB_CMP_EXP_DATA1" */ +/* MD compare IILB input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_iilb_cmp_exp_data1_u { + mmr_t sh_xn_md_iilb_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_md_iilb_cmp_exp_data1_s; +} sh_xn_md_iilb_cmp_exp_data1_u_t; +#else +typedef union sh_xn_md_iilb_cmp_exp_data1_u { + mmr_t sh_xn_md_iilb_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_md_iilb_cmp_exp_data1_s; +} sh_xn_md_iilb_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_IILB_CMP_ENABLE0" */ +/* MD compare IILB input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_iilb_cmp_enable0_u { + mmr_t sh_xn_md_iilb_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_iilb_cmp_enable0_s; +} sh_xn_md_iilb_cmp_enable0_u_t; +#else +typedef union sh_xn_md_iilb_cmp_enable0_u { + mmr_t sh_xn_md_iilb_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_iilb_cmp_enable0_s; +} sh_xn_md_iilb_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_IILB_CMP_ENABLE1" */ +/* MD compare IILB input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_iilb_cmp_enable1_u { + mmr_t sh_xn_md_iilb_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_iilb_cmp_enable1_s; +} sh_xn_md_iilb_cmp_enable1_u_t; +#else +typedef union sh_xn_md_iilb_cmp_enable1_u { + mmr_t sh_xn_md_iilb_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_iilb_cmp_enable1_s; +} sh_xn_md_iilb_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI0_CMP_EXP_DATA0" */ +/* MD compare NI0 input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_ni0_cmp_exp_data0_u { + mmr_t sh_xn_md_ni0_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_md_ni0_cmp_exp_data0_s; +} sh_xn_md_ni0_cmp_exp_data0_u_t; +#else +typedef union sh_xn_md_ni0_cmp_exp_data0_u { + mmr_t sh_xn_md_ni0_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_md_ni0_cmp_exp_data0_s; +} sh_xn_md_ni0_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI0_CMP_EXP_DATA1" */ +/* MD compare NI0 input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_ni0_cmp_exp_data1_u { + mmr_t sh_xn_md_ni0_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_md_ni0_cmp_exp_data1_s; +} sh_xn_md_ni0_cmp_exp_data1_u_t; +#else +typedef union sh_xn_md_ni0_cmp_exp_data1_u { + mmr_t sh_xn_md_ni0_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_md_ni0_cmp_exp_data1_s; +} sh_xn_md_ni0_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI0_CMP_ENABLE0" */ +/* MD compare NI0 input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_ni0_cmp_enable0_u { + mmr_t sh_xn_md_ni0_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_ni0_cmp_enable0_s; +} sh_xn_md_ni0_cmp_enable0_u_t; +#else +typedef union sh_xn_md_ni0_cmp_enable0_u { + mmr_t sh_xn_md_ni0_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_ni0_cmp_enable0_s; +} sh_xn_md_ni0_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI0_CMP_ENABLE1" */ +/* MD compare NI0 input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_ni0_cmp_enable1_u { + mmr_t sh_xn_md_ni0_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_ni0_cmp_enable1_s; +} sh_xn_md_ni0_cmp_enable1_u_t; +#else +typedef union sh_xn_md_ni0_cmp_enable1_u { + mmr_t sh_xn_md_ni0_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_ni0_cmp_enable1_s; +} sh_xn_md_ni0_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI1_CMP_EXP_DATA0" */ +/* MD compare NI1 input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_ni1_cmp_exp_data0_u { + mmr_t sh_xn_md_ni1_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_md_ni1_cmp_exp_data0_s; +} sh_xn_md_ni1_cmp_exp_data0_u_t; +#else +typedef union sh_xn_md_ni1_cmp_exp_data0_u { + mmr_t sh_xn_md_ni1_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_md_ni1_cmp_exp_data0_s; +} sh_xn_md_ni1_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI1_CMP_EXP_DATA1" */ +/* MD compare NI1 input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_ni1_cmp_exp_data1_u { + mmr_t sh_xn_md_ni1_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_md_ni1_cmp_exp_data1_s; +} sh_xn_md_ni1_cmp_exp_data1_u_t; +#else +typedef union sh_xn_md_ni1_cmp_exp_data1_u { + mmr_t sh_xn_md_ni1_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_md_ni1_cmp_exp_data1_s; +} sh_xn_md_ni1_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI1_CMP_ENABLE0" */ +/* MD compare NI1 input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_ni1_cmp_enable0_u { + mmr_t sh_xn_md_ni1_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_ni1_cmp_enable0_s; +} sh_xn_md_ni1_cmp_enable0_u_t; +#else +typedef union sh_xn_md_ni1_cmp_enable0_u { + mmr_t sh_xn_md_ni1_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_ni1_cmp_enable0_s; +} sh_xn_md_ni1_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_NI1_CMP_ENABLE1" */ +/* MD compare NI1 input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_ni1_cmp_enable1_u { + mmr_t sh_xn_md_ni1_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_ni1_cmp_enable1_s; +} sh_xn_md_ni1_cmp_enable1_u_t; +#else +typedef union sh_xn_md_ni1_cmp_enable1_u { + mmr_t sh_xn_md_ni1_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_ni1_cmp_enable1_s; +} sh_xn_md_ni1_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_EXP_HDR0" */ +/* MD compare SIC input expected header0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_exp_hdr0_u { + mmr_t sh_xn_md_sic_cmp_exp_hdr0_regval; + struct { + mmr_t data : 64; + } sh_xn_md_sic_cmp_exp_hdr0_s; +} sh_xn_md_sic_cmp_exp_hdr0_u_t; +#else +typedef union sh_xn_md_sic_cmp_exp_hdr0_u { + mmr_t sh_xn_md_sic_cmp_exp_hdr0_regval; + struct { + mmr_t data : 64; + } sh_xn_md_sic_cmp_exp_hdr0_s; +} sh_xn_md_sic_cmp_exp_hdr0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_EXP_HDR1" */ +/* MD compare SIC input expected header1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_exp_hdr1_u { + mmr_t sh_xn_md_sic_cmp_exp_hdr1_regval; + struct { + mmr_t data : 42; + mmr_t reserved_0 : 22; + } sh_xn_md_sic_cmp_exp_hdr1_s; +} sh_xn_md_sic_cmp_exp_hdr1_u_t; +#else +typedef union sh_xn_md_sic_cmp_exp_hdr1_u { + mmr_t sh_xn_md_sic_cmp_exp_hdr1_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t data : 42; + } sh_xn_md_sic_cmp_exp_hdr1_s; +} sh_xn_md_sic_cmp_exp_hdr1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0" */ +/* MD compare SIC header enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_hdr_enable0_u { + mmr_t sh_xn_md_sic_cmp_hdr_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_sic_cmp_hdr_enable0_s; +} sh_xn_md_sic_cmp_hdr_enable0_u_t; +#else +typedef union sh_xn_md_sic_cmp_hdr_enable0_u { + mmr_t sh_xn_md_sic_cmp_hdr_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_md_sic_cmp_hdr_enable0_s; +} sh_xn_md_sic_cmp_hdr_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1" */ +/* MD compare SIC header enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_hdr_enable1_u { + mmr_t sh_xn_md_sic_cmp_hdr_enable1_regval; + struct { + mmr_t enable : 42; + mmr_t reserved_0 : 22; + } sh_xn_md_sic_cmp_hdr_enable1_s; +} sh_xn_md_sic_cmp_hdr_enable1_u_t; +#else +typedef union sh_xn_md_sic_cmp_hdr_enable1_u { + mmr_t sh_xn_md_sic_cmp_hdr_enable1_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t enable : 42; + } sh_xn_md_sic_cmp_hdr_enable1_s; +} sh_xn_md_sic_cmp_hdr_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA0" */ +/* MD compare SIC data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_data0_u { + mmr_t sh_xn_md_sic_cmp_data0_regval; + struct { + mmr_t data0 : 64; + } sh_xn_md_sic_cmp_data0_s; +} sh_xn_md_sic_cmp_data0_u_t; +#else +typedef union sh_xn_md_sic_cmp_data0_u { + mmr_t sh_xn_md_sic_cmp_data0_regval; + struct { + mmr_t data0 : 64; + } sh_xn_md_sic_cmp_data0_s; +} sh_xn_md_sic_cmp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA1" */ +/* MD compare SIC data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_data1_u { + mmr_t sh_xn_md_sic_cmp_data1_regval; + struct { + mmr_t data1 : 64; + } sh_xn_md_sic_cmp_data1_s; +} sh_xn_md_sic_cmp_data1_u_t; +#else +typedef union sh_xn_md_sic_cmp_data1_u { + mmr_t sh_xn_md_sic_cmp_data1_regval; + struct { + mmr_t data1 : 64; + } sh_xn_md_sic_cmp_data1_s; +} sh_xn_md_sic_cmp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA2" */ +/* MD compare SIC data2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_data2_u { + mmr_t sh_xn_md_sic_cmp_data2_regval; + struct { + mmr_t data2 : 64; + } sh_xn_md_sic_cmp_data2_s; +} sh_xn_md_sic_cmp_data2_u_t; +#else +typedef union sh_xn_md_sic_cmp_data2_u { + mmr_t sh_xn_md_sic_cmp_data2_regval; + struct { + mmr_t data2 : 64; + } sh_xn_md_sic_cmp_data2_s; +} sh_xn_md_sic_cmp_data2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA3" */ +/* MD compare SIC data3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_data3_u { + mmr_t sh_xn_md_sic_cmp_data3_regval; + struct { + mmr_t data3 : 64; + } sh_xn_md_sic_cmp_data3_s; +} sh_xn_md_sic_cmp_data3_u_t; +#else +typedef union sh_xn_md_sic_cmp_data3_u { + mmr_t sh_xn_md_sic_cmp_data3_regval; + struct { + mmr_t data3 : 64; + } sh_xn_md_sic_cmp_data3_s; +} sh_xn_md_sic_cmp_data3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0" */ +/* MD enable compare SIC data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_data_enable0_u { + mmr_t sh_xn_md_sic_cmp_data_enable0_regval; + struct { + mmr_t data_enable0 : 64; + } sh_xn_md_sic_cmp_data_enable0_s; +} sh_xn_md_sic_cmp_data_enable0_u_t; +#else +typedef union sh_xn_md_sic_cmp_data_enable0_u { + mmr_t sh_xn_md_sic_cmp_data_enable0_regval; + struct { + mmr_t data_enable0 : 64; + } sh_xn_md_sic_cmp_data_enable0_s; +} sh_xn_md_sic_cmp_data_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1" */ +/* MD enable compare SIC data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_data_enable1_u { + mmr_t sh_xn_md_sic_cmp_data_enable1_regval; + struct { + mmr_t data_enable1 : 64; + } sh_xn_md_sic_cmp_data_enable1_s; +} sh_xn_md_sic_cmp_data_enable1_u_t; +#else +typedef union sh_xn_md_sic_cmp_data_enable1_u { + mmr_t sh_xn_md_sic_cmp_data_enable1_regval; + struct { + mmr_t data_enable1 : 64; + } sh_xn_md_sic_cmp_data_enable1_s; +} sh_xn_md_sic_cmp_data_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2" */ +/* MD enable compare SIC data2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_data_enable2_u { + mmr_t sh_xn_md_sic_cmp_data_enable2_regval; + struct { + mmr_t data_enable2 : 64; + } sh_xn_md_sic_cmp_data_enable2_s; +} sh_xn_md_sic_cmp_data_enable2_u_t; +#else +typedef union sh_xn_md_sic_cmp_data_enable2_u { + mmr_t sh_xn_md_sic_cmp_data_enable2_regval; + struct { + mmr_t data_enable2 : 64; + } sh_xn_md_sic_cmp_data_enable2_s; +} sh_xn_md_sic_cmp_data_enable2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3" */ +/* MD enable compare SIC data3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_sic_cmp_data_enable3_u { + mmr_t sh_xn_md_sic_cmp_data_enable3_regval; + struct { + mmr_t data_enable3 : 64; + } sh_xn_md_sic_cmp_data_enable3_s; +} sh_xn_md_sic_cmp_data_enable3_u_t; +#else +typedef union sh_xn_md_sic_cmp_data_enable3_u { + mmr_t sh_xn_md_sic_cmp_data_enable3_regval; + struct { + mmr_t data_enable3 : 64; + } sh_xn_md_sic_cmp_data_enable3_s; +} sh_xn_md_sic_cmp_data_enable3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_IILB_CMP_EXP_DATA0" */ +/* PI compare IILB input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_iilb_cmp_exp_data0_u { + mmr_t sh_xn_pi_iilb_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_iilb_cmp_exp_data0_s; +} sh_xn_pi_iilb_cmp_exp_data0_u_t; +#else +typedef union sh_xn_pi_iilb_cmp_exp_data0_u { + mmr_t sh_xn_pi_iilb_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_iilb_cmp_exp_data0_s; +} sh_xn_pi_iilb_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_IILB_CMP_EXP_DATA1" */ +/* PI compare IILB input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_iilb_cmp_exp_data1_u { + mmr_t sh_xn_pi_iilb_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_iilb_cmp_exp_data1_s; +} sh_xn_pi_iilb_cmp_exp_data1_u_t; +#else +typedef union sh_xn_pi_iilb_cmp_exp_data1_u { + mmr_t sh_xn_pi_iilb_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_iilb_cmp_exp_data1_s; +} sh_xn_pi_iilb_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_IILB_CMP_ENABLE0" */ +/* PI compare IILB input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_iilb_cmp_enable0_u { + mmr_t sh_xn_pi_iilb_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_iilb_cmp_enable0_s; +} sh_xn_pi_iilb_cmp_enable0_u_t; +#else +typedef union sh_xn_pi_iilb_cmp_enable0_u { + mmr_t sh_xn_pi_iilb_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_iilb_cmp_enable0_s; +} sh_xn_pi_iilb_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_IILB_CMP_ENABLE1" */ +/* PI compare IILB input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_iilb_cmp_enable1_u { + mmr_t sh_xn_pi_iilb_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_iilb_cmp_enable1_s; +} sh_xn_pi_iilb_cmp_enable1_u_t; +#else +typedef union sh_xn_pi_iilb_cmp_enable1_u { + mmr_t sh_xn_pi_iilb_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_iilb_cmp_enable1_s; +} sh_xn_pi_iilb_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI0_CMP_EXP_DATA0" */ +/* PI compare NI0 input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_ni0_cmp_exp_data0_u { + mmr_t sh_xn_pi_ni0_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_ni0_cmp_exp_data0_s; +} sh_xn_pi_ni0_cmp_exp_data0_u_t; +#else +typedef union sh_xn_pi_ni0_cmp_exp_data0_u { + mmr_t sh_xn_pi_ni0_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_ni0_cmp_exp_data0_s; +} sh_xn_pi_ni0_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI0_CMP_EXP_DATA1" */ +/* PI compare NI0 input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_ni0_cmp_exp_data1_u { + mmr_t sh_xn_pi_ni0_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_ni0_cmp_exp_data1_s; +} sh_xn_pi_ni0_cmp_exp_data1_u_t; +#else +typedef union sh_xn_pi_ni0_cmp_exp_data1_u { + mmr_t sh_xn_pi_ni0_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_ni0_cmp_exp_data1_s; +} sh_xn_pi_ni0_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI0_CMP_ENABLE0" */ +/* PI compare NI0 input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_ni0_cmp_enable0_u { + mmr_t sh_xn_pi_ni0_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_ni0_cmp_enable0_s; +} sh_xn_pi_ni0_cmp_enable0_u_t; +#else +typedef union sh_xn_pi_ni0_cmp_enable0_u { + mmr_t sh_xn_pi_ni0_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_ni0_cmp_enable0_s; +} sh_xn_pi_ni0_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI0_CMP_ENABLE1" */ +/* PI compare NI0 input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_ni0_cmp_enable1_u { + mmr_t sh_xn_pi_ni0_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_ni0_cmp_enable1_s; +} sh_xn_pi_ni0_cmp_enable1_u_t; +#else +typedef union sh_xn_pi_ni0_cmp_enable1_u { + mmr_t sh_xn_pi_ni0_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_ni0_cmp_enable1_s; +} sh_xn_pi_ni0_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI1_CMP_EXP_DATA0" */ +/* PI compare NI1 input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_ni1_cmp_exp_data0_u { + mmr_t sh_xn_pi_ni1_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_ni1_cmp_exp_data0_s; +} sh_xn_pi_ni1_cmp_exp_data0_u_t; +#else +typedef union sh_xn_pi_ni1_cmp_exp_data0_u { + mmr_t sh_xn_pi_ni1_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_ni1_cmp_exp_data0_s; +} sh_xn_pi_ni1_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI1_CMP_EXP_DATA1" */ +/* PI compare NI1 input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_ni1_cmp_exp_data1_u { + mmr_t sh_xn_pi_ni1_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_ni1_cmp_exp_data1_s; +} sh_xn_pi_ni1_cmp_exp_data1_u_t; +#else +typedef union sh_xn_pi_ni1_cmp_exp_data1_u { + mmr_t sh_xn_pi_ni1_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_ni1_cmp_exp_data1_s; +} sh_xn_pi_ni1_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI1_CMP_ENABLE0" */ +/* PI compare NI1 input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_ni1_cmp_enable0_u { + mmr_t sh_xn_pi_ni1_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_ni1_cmp_enable0_s; +} sh_xn_pi_ni1_cmp_enable0_u_t; +#else +typedef union sh_xn_pi_ni1_cmp_enable0_u { + mmr_t sh_xn_pi_ni1_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_ni1_cmp_enable0_s; +} sh_xn_pi_ni1_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_NI1_CMP_ENABLE1" */ +/* PI compare NI1 input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_ni1_cmp_enable1_u { + mmr_t sh_xn_pi_ni1_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_ni1_cmp_enable1_s; +} sh_xn_pi_ni1_cmp_enable1_u_t; +#else +typedef union sh_xn_pi_ni1_cmp_enable1_u { + mmr_t sh_xn_pi_ni1_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_ni1_cmp_enable1_s; +} sh_xn_pi_ni1_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_EXP_HDR0" */ +/* PI compare SIC input expected header0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_exp_hdr0_u { + mmr_t sh_xn_pi_sic_cmp_exp_hdr0_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_sic_cmp_exp_hdr0_s; +} sh_xn_pi_sic_cmp_exp_hdr0_u_t; +#else +typedef union sh_xn_pi_sic_cmp_exp_hdr0_u { + mmr_t sh_xn_pi_sic_cmp_exp_hdr0_regval; + struct { + mmr_t data : 64; + } sh_xn_pi_sic_cmp_exp_hdr0_s; +} sh_xn_pi_sic_cmp_exp_hdr0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_EXP_HDR1" */ +/* PI compare SIC input expected header1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_exp_hdr1_u { + mmr_t sh_xn_pi_sic_cmp_exp_hdr1_regval; + struct { + mmr_t data : 42; + mmr_t reserved_0 : 22; + } sh_xn_pi_sic_cmp_exp_hdr1_s; +} sh_xn_pi_sic_cmp_exp_hdr1_u_t; +#else +typedef union sh_xn_pi_sic_cmp_exp_hdr1_u { + mmr_t sh_xn_pi_sic_cmp_exp_hdr1_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t data : 42; + } sh_xn_pi_sic_cmp_exp_hdr1_s; +} sh_xn_pi_sic_cmp_exp_hdr1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0" */ +/* PI compare SIC header enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_hdr_enable0_u { + mmr_t sh_xn_pi_sic_cmp_hdr_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_sic_cmp_hdr_enable0_s; +} sh_xn_pi_sic_cmp_hdr_enable0_u_t; +#else +typedef union sh_xn_pi_sic_cmp_hdr_enable0_u { + mmr_t sh_xn_pi_sic_cmp_hdr_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_pi_sic_cmp_hdr_enable0_s; +} sh_xn_pi_sic_cmp_hdr_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1" */ +/* PI compare SIC header enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_hdr_enable1_u { + mmr_t sh_xn_pi_sic_cmp_hdr_enable1_regval; + struct { + mmr_t enable : 42; + mmr_t reserved_0 : 22; + } sh_xn_pi_sic_cmp_hdr_enable1_s; +} sh_xn_pi_sic_cmp_hdr_enable1_u_t; +#else +typedef union sh_xn_pi_sic_cmp_hdr_enable1_u { + mmr_t sh_xn_pi_sic_cmp_hdr_enable1_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t enable : 42; + } sh_xn_pi_sic_cmp_hdr_enable1_s; +} sh_xn_pi_sic_cmp_hdr_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA0" */ +/* PI compare SIC data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_data0_u { + mmr_t sh_xn_pi_sic_cmp_data0_regval; + struct { + mmr_t data0 : 64; + } sh_xn_pi_sic_cmp_data0_s; +} sh_xn_pi_sic_cmp_data0_u_t; +#else +typedef union sh_xn_pi_sic_cmp_data0_u { + mmr_t sh_xn_pi_sic_cmp_data0_regval; + struct { + mmr_t data0 : 64; + } sh_xn_pi_sic_cmp_data0_s; +} sh_xn_pi_sic_cmp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA1" */ +/* PI compare SIC data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_data1_u { + mmr_t sh_xn_pi_sic_cmp_data1_regval; + struct { + mmr_t data1 : 64; + } sh_xn_pi_sic_cmp_data1_s; +} sh_xn_pi_sic_cmp_data1_u_t; +#else +typedef union sh_xn_pi_sic_cmp_data1_u { + mmr_t sh_xn_pi_sic_cmp_data1_regval; + struct { + mmr_t data1 : 64; + } sh_xn_pi_sic_cmp_data1_s; +} sh_xn_pi_sic_cmp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA2" */ +/* PI compare SIC data2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_data2_u { + mmr_t sh_xn_pi_sic_cmp_data2_regval; + struct { + mmr_t data2 : 64; + } sh_xn_pi_sic_cmp_data2_s; +} sh_xn_pi_sic_cmp_data2_u_t; +#else +typedef union sh_xn_pi_sic_cmp_data2_u { + mmr_t sh_xn_pi_sic_cmp_data2_regval; + struct { + mmr_t data2 : 64; + } sh_xn_pi_sic_cmp_data2_s; +} sh_xn_pi_sic_cmp_data2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA3" */ +/* PI compare SIC data3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_data3_u { + mmr_t sh_xn_pi_sic_cmp_data3_regval; + struct { + mmr_t data3 : 64; + } sh_xn_pi_sic_cmp_data3_s; +} sh_xn_pi_sic_cmp_data3_u_t; +#else +typedef union sh_xn_pi_sic_cmp_data3_u { + mmr_t sh_xn_pi_sic_cmp_data3_regval; + struct { + mmr_t data3 : 64; + } sh_xn_pi_sic_cmp_data3_s; +} sh_xn_pi_sic_cmp_data3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0" */ +/* PI enable compare SIC data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_data_enable0_u { + mmr_t sh_xn_pi_sic_cmp_data_enable0_regval; + struct { + mmr_t data_enable0 : 64; + } sh_xn_pi_sic_cmp_data_enable0_s; +} sh_xn_pi_sic_cmp_data_enable0_u_t; +#else +typedef union sh_xn_pi_sic_cmp_data_enable0_u { + mmr_t sh_xn_pi_sic_cmp_data_enable0_regval; + struct { + mmr_t data_enable0 : 64; + } sh_xn_pi_sic_cmp_data_enable0_s; +} sh_xn_pi_sic_cmp_data_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1" */ +/* PI enable compare SIC data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_data_enable1_u { + mmr_t sh_xn_pi_sic_cmp_data_enable1_regval; + struct { + mmr_t data_enable1 : 64; + } sh_xn_pi_sic_cmp_data_enable1_s; +} sh_xn_pi_sic_cmp_data_enable1_u_t; +#else +typedef union sh_xn_pi_sic_cmp_data_enable1_u { + mmr_t sh_xn_pi_sic_cmp_data_enable1_regval; + struct { + mmr_t data_enable1 : 64; + } sh_xn_pi_sic_cmp_data_enable1_s; +} sh_xn_pi_sic_cmp_data_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2" */ +/* PI enable compare SIC data2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_data_enable2_u { + mmr_t sh_xn_pi_sic_cmp_data_enable2_regval; + struct { + mmr_t data_enable2 : 64; + } sh_xn_pi_sic_cmp_data_enable2_s; +} sh_xn_pi_sic_cmp_data_enable2_u_t; +#else +typedef union sh_xn_pi_sic_cmp_data_enable2_u { + mmr_t sh_xn_pi_sic_cmp_data_enable2_regval; + struct { + mmr_t data_enable2 : 64; + } sh_xn_pi_sic_cmp_data_enable2_s; +} sh_xn_pi_sic_cmp_data_enable2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3" */ +/* PI enable compare SIC data3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_pi_sic_cmp_data_enable3_u { + mmr_t sh_xn_pi_sic_cmp_data_enable3_regval; + struct { + mmr_t data_enable3 : 64; + } sh_xn_pi_sic_cmp_data_enable3_s; +} sh_xn_pi_sic_cmp_data_enable3_u_t; +#else +typedef union sh_xn_pi_sic_cmp_data_enable3_u { + mmr_t sh_xn_pi_sic_cmp_data_enable3_regval; + struct { + mmr_t data_enable3 : 64; + } sh_xn_pi_sic_cmp_data_enable3_s; +} sh_xn_pi_sic_cmp_data_enable3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_IILB_CMP_EXP_DATA0" */ +/* NI0 compare IILB input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_iilb_cmp_exp_data0_u { + mmr_t sh_xn_ni0_iilb_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_iilb_cmp_exp_data0_s; +} sh_xn_ni0_iilb_cmp_exp_data0_u_t; +#else +typedef union sh_xn_ni0_iilb_cmp_exp_data0_u { + mmr_t sh_xn_ni0_iilb_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_iilb_cmp_exp_data0_s; +} sh_xn_ni0_iilb_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_IILB_CMP_EXP_DATA1" */ +/* NI0 compare IILB input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_iilb_cmp_exp_data1_u { + mmr_t sh_xn_ni0_iilb_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_iilb_cmp_exp_data1_s; +} sh_xn_ni0_iilb_cmp_exp_data1_u_t; +#else +typedef union sh_xn_ni0_iilb_cmp_exp_data1_u { + mmr_t sh_xn_ni0_iilb_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_iilb_cmp_exp_data1_s; +} sh_xn_ni0_iilb_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_IILB_CMP_ENABLE0" */ +/* NI0 compare IILB input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_iilb_cmp_enable0_u { + mmr_t sh_xn_ni0_iilb_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_iilb_cmp_enable0_s; +} sh_xn_ni0_iilb_cmp_enable0_u_t; +#else +typedef union sh_xn_ni0_iilb_cmp_enable0_u { + mmr_t sh_xn_ni0_iilb_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_iilb_cmp_enable0_s; +} sh_xn_ni0_iilb_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_IILB_CMP_ENABLE1" */ +/* NI0 compare IILB input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_iilb_cmp_enable1_u { + mmr_t sh_xn_ni0_iilb_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_iilb_cmp_enable1_s; +} sh_xn_ni0_iilb_cmp_enable1_u_t; +#else +typedef union sh_xn_ni0_iilb_cmp_enable1_u { + mmr_t sh_xn_ni0_iilb_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_iilb_cmp_enable1_s; +} sh_xn_ni0_iilb_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_PI_CMP_EXP_DATA0" */ +/* NI0 compare PI input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_pi_cmp_exp_data0_u { + mmr_t sh_xn_ni0_pi_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_pi_cmp_exp_data0_s; +} sh_xn_ni0_pi_cmp_exp_data0_u_t; +#else +typedef union sh_xn_ni0_pi_cmp_exp_data0_u { + mmr_t sh_xn_ni0_pi_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_pi_cmp_exp_data0_s; +} sh_xn_ni0_pi_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_PI_CMP_EXP_DATA1" */ +/* NI0 compare PI input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_pi_cmp_exp_data1_u { + mmr_t sh_xn_ni0_pi_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_pi_cmp_exp_data1_s; +} sh_xn_ni0_pi_cmp_exp_data1_u_t; +#else +typedef union sh_xn_ni0_pi_cmp_exp_data1_u { + mmr_t sh_xn_ni0_pi_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_pi_cmp_exp_data1_s; +} sh_xn_ni0_pi_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_PI_CMP_ENABLE0" */ +/* NI0 compare PI input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_pi_cmp_enable0_u { + mmr_t sh_xn_ni0_pi_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_pi_cmp_enable0_s; +} sh_xn_ni0_pi_cmp_enable0_u_t; +#else +typedef union sh_xn_ni0_pi_cmp_enable0_u { + mmr_t sh_xn_ni0_pi_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_pi_cmp_enable0_s; +} sh_xn_ni0_pi_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_PI_CMP_ENABLE1" */ +/* NI0 compare PI input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_pi_cmp_enable1_u { + mmr_t sh_xn_ni0_pi_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_pi_cmp_enable1_s; +} sh_xn_ni0_pi_cmp_enable1_u_t; +#else +typedef union sh_xn_ni0_pi_cmp_enable1_u { + mmr_t sh_xn_ni0_pi_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_pi_cmp_enable1_s; +} sh_xn_ni0_pi_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_MD_CMP_EXP_DATA0" */ +/* NI0 compare MD input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_md_cmp_exp_data0_u { + mmr_t sh_xn_ni0_md_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_md_cmp_exp_data0_s; +} sh_xn_ni0_md_cmp_exp_data0_u_t; +#else +typedef union sh_xn_ni0_md_cmp_exp_data0_u { + mmr_t sh_xn_ni0_md_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_md_cmp_exp_data0_s; +} sh_xn_ni0_md_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_MD_CMP_EXP_DATA1" */ +/* NI0 compare MD input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_md_cmp_exp_data1_u { + mmr_t sh_xn_ni0_md_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_md_cmp_exp_data1_s; +} sh_xn_ni0_md_cmp_exp_data1_u_t; +#else +typedef union sh_xn_ni0_md_cmp_exp_data1_u { + mmr_t sh_xn_ni0_md_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_md_cmp_exp_data1_s; +} sh_xn_ni0_md_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_MD_CMP_ENABLE0" */ +/* NI0 compare MD input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_md_cmp_enable0_u { + mmr_t sh_xn_ni0_md_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_md_cmp_enable0_s; +} sh_xn_ni0_md_cmp_enable0_u_t; +#else +typedef union sh_xn_ni0_md_cmp_enable0_u { + mmr_t sh_xn_ni0_md_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_md_cmp_enable0_s; +} sh_xn_ni0_md_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_MD_CMP_ENABLE1" */ +/* NI0 compare MD input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_md_cmp_enable1_u { + mmr_t sh_xn_ni0_md_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_md_cmp_enable1_s; +} sh_xn_ni0_md_cmp_enable1_u_t; +#else +typedef union sh_xn_ni0_md_cmp_enable1_u { + mmr_t sh_xn_ni0_md_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_md_cmp_enable1_s; +} sh_xn_ni0_md_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_NI_CMP_EXP_DATA0" */ +/* NI0 compare NI input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_ni_cmp_exp_data0_u { + mmr_t sh_xn_ni0_ni_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_ni_cmp_exp_data0_s; +} sh_xn_ni0_ni_cmp_exp_data0_u_t; +#else +typedef union sh_xn_ni0_ni_cmp_exp_data0_u { + mmr_t sh_xn_ni0_ni_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_ni_cmp_exp_data0_s; +} sh_xn_ni0_ni_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_NI_CMP_EXP_DATA1" */ +/* NI0 compare NI input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_ni_cmp_exp_data1_u { + mmr_t sh_xn_ni0_ni_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_ni_cmp_exp_data1_s; +} sh_xn_ni0_ni_cmp_exp_data1_u_t; +#else +typedef union sh_xn_ni0_ni_cmp_exp_data1_u { + mmr_t sh_xn_ni0_ni_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_ni_cmp_exp_data1_s; +} sh_xn_ni0_ni_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_NI_CMP_ENABLE0" */ +/* NI0 compare NI input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_ni_cmp_enable0_u { + mmr_t sh_xn_ni0_ni_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_ni_cmp_enable0_s; +} sh_xn_ni0_ni_cmp_enable0_u_t; +#else +typedef union sh_xn_ni0_ni_cmp_enable0_u { + mmr_t sh_xn_ni0_ni_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_ni_cmp_enable0_s; +} sh_xn_ni0_ni_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_NI_CMP_ENABLE1" */ +/* NI0 compare NI input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_ni_cmp_enable1_u { + mmr_t sh_xn_ni0_ni_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_ni_cmp_enable1_s; +} sh_xn_ni0_ni_cmp_enable1_u_t; +#else +typedef union sh_xn_ni0_ni_cmp_enable1_u { + mmr_t sh_xn_ni0_ni_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_ni_cmp_enable1_s; +} sh_xn_ni0_ni_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_LLP_CMP_EXP_DATA0" */ +/* NI0 compare LLP input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_llp_cmp_exp_data0_u { + mmr_t sh_xn_ni0_llp_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_llp_cmp_exp_data0_s; +} sh_xn_ni0_llp_cmp_exp_data0_u_t; +#else +typedef union sh_xn_ni0_llp_cmp_exp_data0_u { + mmr_t sh_xn_ni0_llp_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_llp_cmp_exp_data0_s; +} sh_xn_ni0_llp_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_LLP_CMP_EXP_DATA1" */ +/* NI0 compare LLP input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_llp_cmp_exp_data1_u { + mmr_t sh_xn_ni0_llp_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_llp_cmp_exp_data1_s; +} sh_xn_ni0_llp_cmp_exp_data1_u_t; +#else +typedef union sh_xn_ni0_llp_cmp_exp_data1_u { + mmr_t sh_xn_ni0_llp_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni0_llp_cmp_exp_data1_s; +} sh_xn_ni0_llp_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_LLP_CMP_ENABLE0" */ +/* NI0 compare LLP input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_llp_cmp_enable0_u { + mmr_t sh_xn_ni0_llp_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_llp_cmp_enable0_s; +} sh_xn_ni0_llp_cmp_enable0_u_t; +#else +typedef union sh_xn_ni0_llp_cmp_enable0_u { + mmr_t sh_xn_ni0_llp_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_llp_cmp_enable0_s; +} sh_xn_ni0_llp_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI0_LLP_CMP_ENABLE1" */ +/* NI0 compare LLP input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni0_llp_cmp_enable1_u { + mmr_t sh_xn_ni0_llp_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_llp_cmp_enable1_s; +} sh_xn_ni0_llp_cmp_enable1_u_t; +#else +typedef union sh_xn_ni0_llp_cmp_enable1_u { + mmr_t sh_xn_ni0_llp_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni0_llp_cmp_enable1_s; +} sh_xn_ni0_llp_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_IILB_CMP_EXP_DATA0" */ +/* NI1 compare IILB input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_iilb_cmp_exp_data0_u { + mmr_t sh_xn_ni1_iilb_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_iilb_cmp_exp_data0_s; +} sh_xn_ni1_iilb_cmp_exp_data0_u_t; +#else +typedef union sh_xn_ni1_iilb_cmp_exp_data0_u { + mmr_t sh_xn_ni1_iilb_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_iilb_cmp_exp_data0_s; +} sh_xn_ni1_iilb_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_IILB_CMP_EXP_DATA1" */ +/* NI1 compare IILB input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_iilb_cmp_exp_data1_u { + mmr_t sh_xn_ni1_iilb_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_iilb_cmp_exp_data1_s; +} sh_xn_ni1_iilb_cmp_exp_data1_u_t; +#else +typedef union sh_xn_ni1_iilb_cmp_exp_data1_u { + mmr_t sh_xn_ni1_iilb_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_iilb_cmp_exp_data1_s; +} sh_xn_ni1_iilb_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_IILB_CMP_ENABLE0" */ +/* NI1 compare IILB input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_iilb_cmp_enable0_u { + mmr_t sh_xn_ni1_iilb_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_iilb_cmp_enable0_s; +} sh_xn_ni1_iilb_cmp_enable0_u_t; +#else +typedef union sh_xn_ni1_iilb_cmp_enable0_u { + mmr_t sh_xn_ni1_iilb_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_iilb_cmp_enable0_s; +} sh_xn_ni1_iilb_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_IILB_CMP_ENABLE1" */ +/* NI1 compare IILB input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_iilb_cmp_enable1_u { + mmr_t sh_xn_ni1_iilb_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_iilb_cmp_enable1_s; +} sh_xn_ni1_iilb_cmp_enable1_u_t; +#else +typedef union sh_xn_ni1_iilb_cmp_enable1_u { + mmr_t sh_xn_ni1_iilb_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_iilb_cmp_enable1_s; +} sh_xn_ni1_iilb_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_PI_CMP_EXP_DATA0" */ +/* NI1 compare PI input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_pi_cmp_exp_data0_u { + mmr_t sh_xn_ni1_pi_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_pi_cmp_exp_data0_s; +} sh_xn_ni1_pi_cmp_exp_data0_u_t; +#else +typedef union sh_xn_ni1_pi_cmp_exp_data0_u { + mmr_t sh_xn_ni1_pi_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_pi_cmp_exp_data0_s; +} sh_xn_ni1_pi_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_PI_CMP_EXP_DATA1" */ +/* NI1 compare PI input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_pi_cmp_exp_data1_u { + mmr_t sh_xn_ni1_pi_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_pi_cmp_exp_data1_s; +} sh_xn_ni1_pi_cmp_exp_data1_u_t; +#else +typedef union sh_xn_ni1_pi_cmp_exp_data1_u { + mmr_t sh_xn_ni1_pi_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_pi_cmp_exp_data1_s; +} sh_xn_ni1_pi_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_PI_CMP_ENABLE0" */ +/* NI1 compare PI input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_pi_cmp_enable0_u { + mmr_t sh_xn_ni1_pi_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_pi_cmp_enable0_s; +} sh_xn_ni1_pi_cmp_enable0_u_t; +#else +typedef union sh_xn_ni1_pi_cmp_enable0_u { + mmr_t sh_xn_ni1_pi_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_pi_cmp_enable0_s; +} sh_xn_ni1_pi_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_PI_CMP_ENABLE1" */ +/* NI1 compare PI input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_pi_cmp_enable1_u { + mmr_t sh_xn_ni1_pi_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_pi_cmp_enable1_s; +} sh_xn_ni1_pi_cmp_enable1_u_t; +#else +typedef union sh_xn_ni1_pi_cmp_enable1_u { + mmr_t sh_xn_ni1_pi_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_pi_cmp_enable1_s; +} sh_xn_ni1_pi_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_MD_CMP_EXP_DATA0" */ +/* NI1 compare MD input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_md_cmp_exp_data0_u { + mmr_t sh_xn_ni1_md_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_md_cmp_exp_data0_s; +} sh_xn_ni1_md_cmp_exp_data0_u_t; +#else +typedef union sh_xn_ni1_md_cmp_exp_data0_u { + mmr_t sh_xn_ni1_md_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_md_cmp_exp_data0_s; +} sh_xn_ni1_md_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_MD_CMP_EXP_DATA1" */ +/* NI1 compare MD input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_md_cmp_exp_data1_u { + mmr_t sh_xn_ni1_md_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_md_cmp_exp_data1_s; +} sh_xn_ni1_md_cmp_exp_data1_u_t; +#else +typedef union sh_xn_ni1_md_cmp_exp_data1_u { + mmr_t sh_xn_ni1_md_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_md_cmp_exp_data1_s; +} sh_xn_ni1_md_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_MD_CMP_ENABLE0" */ +/* NI1 compare MD input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_md_cmp_enable0_u { + mmr_t sh_xn_ni1_md_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_md_cmp_enable0_s; +} sh_xn_ni1_md_cmp_enable0_u_t; +#else +typedef union sh_xn_ni1_md_cmp_enable0_u { + mmr_t sh_xn_ni1_md_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_md_cmp_enable0_s; +} sh_xn_ni1_md_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_MD_CMP_ENABLE1" */ +/* NI1 compare MD input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_md_cmp_enable1_u { + mmr_t sh_xn_ni1_md_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_md_cmp_enable1_s; +} sh_xn_ni1_md_cmp_enable1_u_t; +#else +typedef union sh_xn_ni1_md_cmp_enable1_u { + mmr_t sh_xn_ni1_md_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_md_cmp_enable1_s; +} sh_xn_ni1_md_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_NI_CMP_EXP_DATA0" */ +/* NI1 compare NI input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_ni_cmp_exp_data0_u { + mmr_t sh_xn_ni1_ni_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_ni_cmp_exp_data0_s; +} sh_xn_ni1_ni_cmp_exp_data0_u_t; +#else +typedef union sh_xn_ni1_ni_cmp_exp_data0_u { + mmr_t sh_xn_ni1_ni_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_ni_cmp_exp_data0_s; +} sh_xn_ni1_ni_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_NI_CMP_EXP_DATA1" */ +/* NI1 compare NI input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_ni_cmp_exp_data1_u { + mmr_t sh_xn_ni1_ni_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_ni_cmp_exp_data1_s; +} sh_xn_ni1_ni_cmp_exp_data1_u_t; +#else +typedef union sh_xn_ni1_ni_cmp_exp_data1_u { + mmr_t sh_xn_ni1_ni_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_ni_cmp_exp_data1_s; +} sh_xn_ni1_ni_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_NI_CMP_ENABLE0" */ +/* NI1 compare NI input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_ni_cmp_enable0_u { + mmr_t sh_xn_ni1_ni_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_ni_cmp_enable0_s; +} sh_xn_ni1_ni_cmp_enable0_u_t; +#else +typedef union sh_xn_ni1_ni_cmp_enable0_u { + mmr_t sh_xn_ni1_ni_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_ni_cmp_enable0_s; +} sh_xn_ni1_ni_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_NI_CMP_ENABLE1" */ +/* NI1 compare NI input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_ni_cmp_enable1_u { + mmr_t sh_xn_ni1_ni_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_ni_cmp_enable1_s; +} sh_xn_ni1_ni_cmp_enable1_u_t; +#else +typedef union sh_xn_ni1_ni_cmp_enable1_u { + mmr_t sh_xn_ni1_ni_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_ni_cmp_enable1_s; +} sh_xn_ni1_ni_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_LLP_CMP_EXP_DATA0" */ +/* NI1 compare LLP input expected data0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_llp_cmp_exp_data0_u { + mmr_t sh_xn_ni1_llp_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_llp_cmp_exp_data0_s; +} sh_xn_ni1_llp_cmp_exp_data0_u_t; +#else +typedef union sh_xn_ni1_llp_cmp_exp_data0_u { + mmr_t sh_xn_ni1_llp_cmp_exp_data0_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_llp_cmp_exp_data0_s; +} sh_xn_ni1_llp_cmp_exp_data0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_LLP_CMP_EXP_DATA1" */ +/* NI1 compare LLP input expected data1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_llp_cmp_exp_data1_u { + mmr_t sh_xn_ni1_llp_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_llp_cmp_exp_data1_s; +} sh_xn_ni1_llp_cmp_exp_data1_u_t; +#else +typedef union sh_xn_ni1_llp_cmp_exp_data1_u { + mmr_t sh_xn_ni1_llp_cmp_exp_data1_regval; + struct { + mmr_t data : 64; + } sh_xn_ni1_llp_cmp_exp_data1_s; +} sh_xn_ni1_llp_cmp_exp_data1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_LLP_CMP_ENABLE0" */ +/* NI1 compare LLP input enable0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_llp_cmp_enable0_u { + mmr_t sh_xn_ni1_llp_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_llp_cmp_enable0_s; +} sh_xn_ni1_llp_cmp_enable0_u_t; +#else +typedef union sh_xn_ni1_llp_cmp_enable0_u { + mmr_t sh_xn_ni1_llp_cmp_enable0_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_llp_cmp_enable0_s; +} sh_xn_ni1_llp_cmp_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_NI1_LLP_CMP_ENABLE1" */ +/* NI1 compare LLP input enable1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_ni1_llp_cmp_enable1_u { + mmr_t sh_xn_ni1_llp_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_llp_cmp_enable1_s; +} sh_xn_ni1_llp_cmp_enable1_u_t; +#else +typedef union sh_xn_ni1_llp_cmp_enable1_u { + mmr_t sh_xn_ni1_llp_cmp_enable1_regval; + struct { + mmr_t enable : 64; + } sh_xn_ni1_llp_cmp_enable1_s; +} sh_xn_ni1_llp_cmp_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_ECC_INJ_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_ecc_inj_reg_u { + mmr_t sh_xnpi_ecc_inj_reg_regval; + struct { + mmr_t byte0 : 8; + mmr_t reserved_0 : 4; + mmr_t data_1shot0 : 1; + mmr_t data_cont0 : 1; + mmr_t data_cb_1shot0 : 1; + mmr_t data_cb_cont0 : 1; + mmr_t byte1 : 8; + mmr_t reserved_1 : 4; + mmr_t data_1shot1 : 1; + mmr_t data_cont1 : 1; + mmr_t data_cb_1shot1 : 1; + mmr_t data_cb_cont1 : 1; + mmr_t byte2 : 8; + mmr_t reserved_2 : 4; + mmr_t data_1shot2 : 1; + mmr_t data_cont2 : 1; + mmr_t data_cb_1shot2 : 1; + mmr_t data_cb_cont2 : 1; + mmr_t byte3 : 8; + mmr_t reserved_3 : 4; + mmr_t data_1shot3 : 1; + mmr_t data_cont3 : 1; + mmr_t data_cb_1shot3 : 1; + mmr_t data_cb_cont3 : 1; + } sh_xnpi_ecc_inj_reg_s; +} sh_xnpi_ecc_inj_reg_u_t; +#else +typedef union sh_xnpi_ecc_inj_reg_u { + mmr_t sh_xnpi_ecc_inj_reg_regval; + struct { + mmr_t data_cb_cont3 : 1; + mmr_t data_cb_1shot3 : 1; + mmr_t data_cont3 : 1; + mmr_t data_1shot3 : 1; + mmr_t reserved_3 : 4; + mmr_t byte3 : 8; + mmr_t data_cb_cont2 : 1; + mmr_t data_cb_1shot2 : 1; + mmr_t data_cont2 : 1; + mmr_t data_1shot2 : 1; + mmr_t reserved_2 : 4; + mmr_t byte2 : 8; + mmr_t data_cb_cont1 : 1; + mmr_t data_cb_1shot1 : 1; + mmr_t data_cont1 : 1; + mmr_t data_1shot1 : 1; + mmr_t reserved_1 : 4; + mmr_t byte1 : 8; + mmr_t data_cb_cont0 : 1; + mmr_t data_cb_1shot0 : 1; + mmr_t data_cont0 : 1; + mmr_t data_1shot0 : 1; + mmr_t reserved_0 : 4; + mmr_t byte0 : 8; + } sh_xnpi_ecc_inj_reg_s; +} sh_xnpi_ecc_inj_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_ECC0_INJ_MASK_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_ecc0_inj_mask_reg_u { + mmr_t sh_xnpi_ecc0_inj_mask_reg_regval; + struct { + mmr_t mask_ecc0 : 64; + } sh_xnpi_ecc0_inj_mask_reg_s; +} sh_xnpi_ecc0_inj_mask_reg_u_t; +#else +typedef union sh_xnpi_ecc0_inj_mask_reg_u { + mmr_t sh_xnpi_ecc0_inj_mask_reg_regval; + struct { + mmr_t mask_ecc0 : 64; + } sh_xnpi_ecc0_inj_mask_reg_s; +} sh_xnpi_ecc0_inj_mask_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_ECC1_INJ_MASK_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_ecc1_inj_mask_reg_u { + mmr_t sh_xnpi_ecc1_inj_mask_reg_regval; + struct { + mmr_t mask_ecc1 : 64; + } sh_xnpi_ecc1_inj_mask_reg_s; +} sh_xnpi_ecc1_inj_mask_reg_u_t; +#else +typedef union sh_xnpi_ecc1_inj_mask_reg_u { + mmr_t sh_xnpi_ecc1_inj_mask_reg_regval; + struct { + mmr_t mask_ecc1 : 64; + } sh_xnpi_ecc1_inj_mask_reg_s; +} sh_xnpi_ecc1_inj_mask_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_ECC2_INJ_MASK_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_ecc2_inj_mask_reg_u { + mmr_t sh_xnpi_ecc2_inj_mask_reg_regval; + struct { + mmr_t mask_ecc2 : 64; + } sh_xnpi_ecc2_inj_mask_reg_s; +} sh_xnpi_ecc2_inj_mask_reg_u_t; +#else +typedef union sh_xnpi_ecc2_inj_mask_reg_u { + mmr_t sh_xnpi_ecc2_inj_mask_reg_regval; + struct { + mmr_t mask_ecc2 : 64; + } sh_xnpi_ecc2_inj_mask_reg_s; +} sh_xnpi_ecc2_inj_mask_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_ECC3_INJ_MASK_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_ecc3_inj_mask_reg_u { + mmr_t sh_xnpi_ecc3_inj_mask_reg_regval; + struct { + mmr_t mask_ecc3 : 64; + } sh_xnpi_ecc3_inj_mask_reg_s; +} sh_xnpi_ecc3_inj_mask_reg_u_t; +#else +typedef union sh_xnpi_ecc3_inj_mask_reg_u { + mmr_t sh_xnpi_ecc3_inj_mask_reg_regval; + struct { + mmr_t mask_ecc3 : 64; + } sh_xnpi_ecc3_inj_mask_reg_s; +} sh_xnpi_ecc3_inj_mask_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC_INJ_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_ecc_inj_reg_u { + mmr_t sh_xnmd_ecc_inj_reg_regval; + struct { + mmr_t byte0 : 8; + mmr_t reserved_0 : 4; + mmr_t data_1shot0 : 1; + mmr_t data_cont0 : 1; + mmr_t data_cb_1shot0 : 1; + mmr_t data_cb_cont0 : 1; + mmr_t byte1 : 8; + mmr_t reserved_1 : 4; + mmr_t data_1shot1 : 1; + mmr_t data_cont1 : 1; + mmr_t data_cb_1shot1 : 1; + mmr_t data_cb_cont1 : 1; + mmr_t byte2 : 8; + mmr_t reserved_2 : 4; + mmr_t data_1shot2 : 1; + mmr_t data_cont2 : 1; + mmr_t data_cb_1shot2 : 1; + mmr_t data_cb_cont2 : 1; + mmr_t byte3 : 8; + mmr_t reserved_3 : 4; + mmr_t data_1shot3 : 1; + mmr_t data_cont3 : 1; + mmr_t data_cb_1shot3 : 1; + mmr_t data_cb_cont3 : 1; + } sh_xnmd_ecc_inj_reg_s; +} sh_xnmd_ecc_inj_reg_u_t; +#else +typedef union sh_xnmd_ecc_inj_reg_u { + mmr_t sh_xnmd_ecc_inj_reg_regval; + struct { + mmr_t data_cb_cont3 : 1; + mmr_t data_cb_1shot3 : 1; + mmr_t data_cont3 : 1; + mmr_t data_1shot3 : 1; + mmr_t reserved_3 : 4; + mmr_t byte3 : 8; + mmr_t data_cb_cont2 : 1; + mmr_t data_cb_1shot2 : 1; + mmr_t data_cont2 : 1; + mmr_t data_1shot2 : 1; + mmr_t reserved_2 : 4; + mmr_t byte2 : 8; + mmr_t data_cb_cont1 : 1; + mmr_t data_cb_1shot1 : 1; + mmr_t data_cont1 : 1; + mmr_t data_1shot1 : 1; + mmr_t reserved_1 : 4; + mmr_t byte1 : 8; + mmr_t data_cb_cont0 : 1; + mmr_t data_cb_1shot0 : 1; + mmr_t data_cont0 : 1; + mmr_t data_1shot0 : 1; + mmr_t reserved_0 : 4; + mmr_t byte0 : 8; + } sh_xnmd_ecc_inj_reg_s; +} sh_xnmd_ecc_inj_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC0_INJ_MASK_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_ecc0_inj_mask_reg_u { + mmr_t sh_xnmd_ecc0_inj_mask_reg_regval; + struct { + mmr_t mask_ecc0 : 64; + } sh_xnmd_ecc0_inj_mask_reg_s; +} sh_xnmd_ecc0_inj_mask_reg_u_t; +#else +typedef union sh_xnmd_ecc0_inj_mask_reg_u { + mmr_t sh_xnmd_ecc0_inj_mask_reg_regval; + struct { + mmr_t mask_ecc0 : 64; + } sh_xnmd_ecc0_inj_mask_reg_s; +} sh_xnmd_ecc0_inj_mask_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC1_INJ_MASK_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_ecc1_inj_mask_reg_u { + mmr_t sh_xnmd_ecc1_inj_mask_reg_regval; + struct { + mmr_t mask_ecc1 : 64; + } sh_xnmd_ecc1_inj_mask_reg_s; +} sh_xnmd_ecc1_inj_mask_reg_u_t; +#else +typedef union sh_xnmd_ecc1_inj_mask_reg_u { + mmr_t sh_xnmd_ecc1_inj_mask_reg_regval; + struct { + mmr_t mask_ecc1 : 64; + } sh_xnmd_ecc1_inj_mask_reg_s; +} sh_xnmd_ecc1_inj_mask_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC2_INJ_MASK_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_ecc2_inj_mask_reg_u { + mmr_t sh_xnmd_ecc2_inj_mask_reg_regval; + struct { + mmr_t mask_ecc2 : 64; + } sh_xnmd_ecc2_inj_mask_reg_s; +} sh_xnmd_ecc2_inj_mask_reg_u_t; +#else +typedef union sh_xnmd_ecc2_inj_mask_reg_u { + mmr_t sh_xnmd_ecc2_inj_mask_reg_regval; + struct { + mmr_t mask_ecc2 : 64; + } sh_xnmd_ecc2_inj_mask_reg_s; +} sh_xnmd_ecc2_inj_mask_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC3_INJ_MASK_REG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_ecc3_inj_mask_reg_u { + mmr_t sh_xnmd_ecc3_inj_mask_reg_regval; + struct { + mmr_t mask_ecc3 : 64; + } sh_xnmd_ecc3_inj_mask_reg_s; +} sh_xnmd_ecc3_inj_mask_reg_u_t; +#else +typedef union sh_xnmd_ecc3_inj_mask_reg_u { + mmr_t sh_xnmd_ecc3_inj_mask_reg_regval; + struct { + mmr_t mask_ecc3 : 64; + } sh_xnmd_ecc3_inj_mask_reg_s; +} sh_xnmd_ecc3_inj_mask_reg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_ECC_ERR_REPORT" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_ecc_err_report_u { + mmr_t sh_xnmd_ecc_err_report_regval; + struct { + mmr_t ecc_disable0 : 1; + mmr_t reserved_0 : 15; + mmr_t ecc_disable1 : 1; + mmr_t reserved_1 : 15; + mmr_t ecc_disable2 : 1; + mmr_t reserved_2 : 15; + mmr_t ecc_disable3 : 1; + mmr_t reserved_3 : 15; + } sh_xnmd_ecc_err_report_s; +} sh_xnmd_ecc_err_report_u_t; +#else +typedef union sh_xnmd_ecc_err_report_u { + mmr_t sh_xnmd_ecc_err_report_regval; + struct { + mmr_t reserved_3 : 15; + mmr_t ecc_disable3 : 1; + mmr_t reserved_2 : 15; + mmr_t ecc_disable2 : 1; + mmr_t reserved_1 : 15; + mmr_t ecc_disable1 : 1; + mmr_t reserved_0 : 15; + mmr_t ecc_disable0 : 1; + } sh_xnmd_ecc_err_report_s; +} sh_xnmd_ecc_err_report_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_SUMMARY_1" */ +/* ni0 Error Summary Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_error_summary_1_u { + mmr_t sh_ni0_error_summary_1_regval; + struct { + mmr_t overflow_fifo02_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc3 : 1; + } sh_ni0_error_summary_1_s; +} sh_ni0_error_summary_1_u_t; +#else +typedef union sh_ni0_error_summary_1_u { + mmr_t sh_ni0_error_summary_1_regval; + struct { + mmr_t tail_timeout_ni_vc3 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo02_debit0 : 1; + } sh_ni0_error_summary_1_s; +} sh_ni0_error_summary_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_SUMMARY_2" */ +/* ni0 Error Summary Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_error_summary_2_u { + mmr_t sh_ni0_error_summary_2_regval; + struct { + mmr_t illegal_vcni : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vciilb : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow2_vc2_credit : 1; + mmr_t reserved_0 : 10; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + mmr_t retry_timeout_error : 1; + mmr_t reserved_1 : 1; + } sh_ni0_error_summary_2_s; +} sh_ni0_error_summary_2_u_t; +#else +typedef union sh_ni0_error_summary_2_u { + mmr_t sh_ni0_error_summary_2_regval; + struct { + mmr_t reserved_1 : 1; + mmr_t retry_timeout_error : 1; + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t reserved_0 : 10; + mmr_t underflow2_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t illegal_vciilb : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcni : 1; + } sh_ni0_error_summary_2_s; +} sh_ni0_error_summary_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_OVERFLOW_1" */ +/* ni0 Error Overflow Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_error_overflow_1_u { + mmr_t sh_ni0_error_overflow_1_regval; + struct { + mmr_t overflow_fifo02_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc3 : 1; + } sh_ni0_error_overflow_1_s; +} sh_ni0_error_overflow_1_u_t; +#else +typedef union sh_ni0_error_overflow_1_u { + mmr_t sh_ni0_error_overflow_1_regval; + struct { + mmr_t tail_timeout_ni_vc3 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo02_debit0 : 1; + } sh_ni0_error_overflow_1_s; +} sh_ni0_error_overflow_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_OVERFLOW_2" */ +/* ni0 Error Overflow Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_error_overflow_2_u { + mmr_t sh_ni0_error_overflow_2_regval; + struct { + mmr_t illegal_vcni : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vciilb : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow2_vc2_credit : 1; + mmr_t reserved_0 : 10; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + mmr_t retry_timeout_error : 1; + mmr_t reserved_1 : 1; + } sh_ni0_error_overflow_2_s; +} sh_ni0_error_overflow_2_u_t; +#else +typedef union sh_ni0_error_overflow_2_u { + mmr_t sh_ni0_error_overflow_2_regval; + struct { + mmr_t reserved_1 : 1; + mmr_t retry_timeout_error : 1; + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t reserved_0 : 10; + mmr_t underflow2_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t illegal_vciilb : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcni : 1; + } sh_ni0_error_overflow_2_s; +} sh_ni0_error_overflow_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_MASK_1" */ +/* ni0 Error Mask Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_error_mask_1_u { + mmr_t sh_ni0_error_mask_1_regval; + struct { + mmr_t overflow_fifo02_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc3 : 1; + } sh_ni0_error_mask_1_s; +} sh_ni0_error_mask_1_u_t; +#else +typedef union sh_ni0_error_mask_1_u { + mmr_t sh_ni0_error_mask_1_regval; + struct { + mmr_t tail_timeout_ni_vc3 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo02_debit0 : 1; + } sh_ni0_error_mask_1_s; +} sh_ni0_error_mask_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_MASK_2" */ +/* ni0 Error Mask Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_error_mask_2_u { + mmr_t sh_ni0_error_mask_2_regval; + struct { + mmr_t illegal_vcni : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vciilb : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow2_vc2_credit : 1; + mmr_t reserved_0 : 10; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + mmr_t retry_timeout_error : 1; + mmr_t reserved_1 : 1; + } sh_ni0_error_mask_2_s; +} sh_ni0_error_mask_2_u_t; +#else +typedef union sh_ni0_error_mask_2_u { + mmr_t sh_ni0_error_mask_2_regval; + struct { + mmr_t reserved_1 : 1; + mmr_t retry_timeout_error : 1; + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t reserved_0 : 10; + mmr_t underflow2_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t illegal_vciilb : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcni : 1; + } sh_ni0_error_mask_2_s; +} sh_ni0_error_mask_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_FIRST_ERROR_1" */ +/* ni0 First Error Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_first_error_1_u { + mmr_t sh_ni0_first_error_1_regval; + struct { + mmr_t overflow_fifo02_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc3 : 1; + } sh_ni0_first_error_1_s; +} sh_ni0_first_error_1_u_t; +#else +typedef union sh_ni0_first_error_1_u { + mmr_t sh_ni0_first_error_1_regval; + struct { + mmr_t tail_timeout_ni_vc3 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo02_debit0 : 1; + } sh_ni0_first_error_1_s; +} sh_ni0_first_error_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_FIRST_ERROR_2" */ +/* ni0 First Error Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_first_error_2_u { + mmr_t sh_ni0_first_error_2_regval; + struct { + mmr_t illegal_vcni : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vciilb : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow2_vc2_credit : 1; + mmr_t reserved_0 : 10; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + mmr_t retry_timeout_error : 1; + mmr_t reserved_1 : 1; + } sh_ni0_first_error_2_s; +} sh_ni0_first_error_2_u_t; +#else +typedef union sh_ni0_first_error_2_u { + mmr_t sh_ni0_first_error_2_regval; + struct { + mmr_t reserved_1 : 1; + mmr_t retry_timeout_error : 1; + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t reserved_0 : 10; + mmr_t underflow2_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t illegal_vciilb : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcni : 1; + } sh_ni0_first_error_2_s; +} sh_ni0_first_error_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_DETAIL_1" */ +/* ni0 Chiplet no match header bits 63:0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_error_detail_1_u { + mmr_t sh_ni0_error_detail_1_regval; + struct { + mmr_t header : 64; + } sh_ni0_error_detail_1_s; +} sh_ni0_error_detail_1_u_t; +#else +typedef union sh_ni0_error_detail_1_u { + mmr_t sh_ni0_error_detail_1_regval; + struct { + mmr_t header : 64; + } sh_ni0_error_detail_1_s; +} sh_ni0_error_detail_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_DETAIL_2" */ +/* ni0 Chiplet no match header bits 127:64 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_error_detail_2_u { + mmr_t sh_ni0_error_detail_2_regval; + struct { + mmr_t header : 64; + } sh_ni0_error_detail_2_s; +} sh_ni0_error_detail_2_u_t; +#else +typedef union sh_ni0_error_detail_2_u { + mmr_t sh_ni0_error_detail_2_regval; + struct { + mmr_t header : 64; + } sh_ni0_error_detail_2_s; +} sh_ni0_error_detail_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_SUMMARY_1" */ +/* ni1 Error Summary Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_error_summary_1_u { + mmr_t sh_ni1_error_summary_1_regval; + struct { + mmr_t overflow_fifo02_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc3 : 1; + } sh_ni1_error_summary_1_s; +} sh_ni1_error_summary_1_u_t; +#else +typedef union sh_ni1_error_summary_1_u { + mmr_t sh_ni1_error_summary_1_regval; + struct { + mmr_t tail_timeout_ni_vc3 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo02_debit0 : 1; + } sh_ni1_error_summary_1_s; +} sh_ni1_error_summary_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_SUMMARY_2" */ +/* ni1 Error Summary Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_error_summary_2_u { + mmr_t sh_ni1_error_summary_2_regval; + struct { + mmr_t illegal_vcni : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vciilb : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow2_vc2_credit : 1; + mmr_t reserved_0 : 10; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + mmr_t retry_timeout_error : 1; + mmr_t reserved_1 : 1; + } sh_ni1_error_summary_2_s; +} sh_ni1_error_summary_2_u_t; +#else +typedef union sh_ni1_error_summary_2_u { + mmr_t sh_ni1_error_summary_2_regval; + struct { + mmr_t reserved_1 : 1; + mmr_t retry_timeout_error : 1; + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t reserved_0 : 10; + mmr_t underflow2_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t illegal_vciilb : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcni : 1; + } sh_ni1_error_summary_2_s; +} sh_ni1_error_summary_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_OVERFLOW_1" */ +/* ni1 Error Overflow Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_error_overflow_1_u { + mmr_t sh_ni1_error_overflow_1_regval; + struct { + mmr_t overflow_fifo02_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc3 : 1; + } sh_ni1_error_overflow_1_s; +} sh_ni1_error_overflow_1_u_t; +#else +typedef union sh_ni1_error_overflow_1_u { + mmr_t sh_ni1_error_overflow_1_regval; + struct { + mmr_t tail_timeout_ni_vc3 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo02_debit0 : 1; + } sh_ni1_error_overflow_1_s; +} sh_ni1_error_overflow_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_OVERFLOW_2" */ +/* ni1 Error Overflow Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_error_overflow_2_u { + mmr_t sh_ni1_error_overflow_2_regval; + struct { + mmr_t illegal_vcni : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vciilb : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow2_vc2_credit : 1; + mmr_t reserved_0 : 10; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + mmr_t retry_timeout_error : 1; + mmr_t reserved_1 : 1; + } sh_ni1_error_overflow_2_s; +} sh_ni1_error_overflow_2_u_t; +#else +typedef union sh_ni1_error_overflow_2_u { + mmr_t sh_ni1_error_overflow_2_regval; + struct { + mmr_t reserved_1 : 1; + mmr_t retry_timeout_error : 1; + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t reserved_0 : 10; + mmr_t underflow2_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t illegal_vciilb : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcni : 1; + } sh_ni1_error_overflow_2_s; +} sh_ni1_error_overflow_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_MASK_1" */ +/* ni1 Error Mask Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_error_mask_1_u { + mmr_t sh_ni1_error_mask_1_regval; + struct { + mmr_t overflow_fifo02_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc3 : 1; + } sh_ni1_error_mask_1_s; +} sh_ni1_error_mask_1_u_t; +#else +typedef union sh_ni1_error_mask_1_u { + mmr_t sh_ni1_error_mask_1_regval; + struct { + mmr_t tail_timeout_ni_vc3 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo02_debit0 : 1; + } sh_ni1_error_mask_1_s; +} sh_ni1_error_mask_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_MASK_2" */ +/* ni1 Error Mask Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_error_mask_2_u { + mmr_t sh_ni1_error_mask_2_regval; + struct { + mmr_t illegal_vcni : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vciilb : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow2_vc2_credit : 1; + mmr_t reserved_0 : 10; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + mmr_t retry_timeout_error : 1; + mmr_t reserved_1 : 1; + } sh_ni1_error_mask_2_s; +} sh_ni1_error_mask_2_u_t; +#else +typedef union sh_ni1_error_mask_2_u { + mmr_t sh_ni1_error_mask_2_regval; + struct { + mmr_t reserved_1 : 1; + mmr_t retry_timeout_error : 1; + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t reserved_0 : 10; + mmr_t underflow2_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t illegal_vciilb : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcni : 1; + } sh_ni1_error_mask_2_s; +} sh_ni1_error_mask_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_FIRST_ERROR_1" */ +/* ni1 First Error Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_first_error_1_u { + mmr_t sh_ni1_first_error_1_regval; + struct { + mmr_t overflow_fifo02_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc3 : 1; + } sh_ni1_first_error_1_s; +} sh_ni1_first_error_1_u_t; +#else +typedef union sh_ni1_first_error_1_u { + mmr_t sh_ni1_first_error_1_regval; + struct { + mmr_t tail_timeout_ni_vc3 : 1; + mmr_t tail_timeout_ni_vc2 : 1; + mmr_t tail_timeout_ni_vc1 : 1; + mmr_t tail_timeout_ni_vc0 : 1; + mmr_t tail_timeout_fifo13_vc3 : 1; + mmr_t tail_timeout_fifo13_vc1 : 1; + mmr_t tail_timeout_fifo02_vc2 : 1; + mmr_t tail_timeout_fifo02_vc0 : 1; + mmr_t overflow_ni_fifo_vc3_credit : 1; + mmr_t overflow_ni_fifo_vc2_credit : 1; + mmr_t overflow_ni_fifo_vc1_credit : 1; + mmr_t overflow_ni_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_credit : 1; + mmr_t overflow_md_fifo_vc0_credit : 1; + mmr_t overflow_iilb_fifo_vc2_credit : 1; + mmr_t overflow_iilb_fifo_vc0_credit : 1; + mmr_t overflow_pi_fifo_vc2_credit : 1; + mmr_t overflow_pi_fifo_vc0_credit : 1; + mmr_t overflow_md_fifo_vc2_push : 1; + mmr_t overflow_md_fifo_vc0_push : 1; + mmr_t overflow_iilb_fifo_vc2_push : 1; + mmr_t overflow_iilb_fifo_vc0_push : 1; + mmr_t overflow_pi_fifo_vc2_push : 1; + mmr_t overflow_pi_fifo_vc0_push : 1; + mmr_t overflow_ni_fifo_vc2_pop : 1; + mmr_t overflow_ni_fifo_vc0_pop : 1; + mmr_t overflow_md_fifo_vc2_pop : 1; + mmr_t overflow_md_fifo_vc0_pop : 1; + mmr_t overflow_iilb_fifo_vc2_pop : 1; + mmr_t overflow_iilb_fifo_vc0_pop : 1; + mmr_t overflow_pi_fifo_vc2_pop : 1; + mmr_t overflow_pi_fifo_vc0_pop : 1; + mmr_t overflow_ni_fifo_debit3 : 1; + mmr_t overflow_ni_fifo_debit2 : 1; + mmr_t overflow_ni_fifo_debit1 : 1; + mmr_t overflow_ni_fifo_debit0 : 1; + mmr_t overflow_md_fifo_debit2 : 1; + mmr_t overflow_md_fifo_debit0 : 1; + mmr_t overflow_iilb_fifo_debit2 : 1; + mmr_t overflow_iilb_fifo_debit0 : 1; + mmr_t overflow_pi_fifo_debit2 : 1; + mmr_t overflow_pi_fifo_debit0 : 1; + mmr_t overflow2_vc2_credit : 1; + mmr_t overflow1_vc2_credit : 1; + mmr_t overflow0_vc2_credit : 1; + mmr_t overflow2_vc0_credit : 1; + mmr_t overflow1_vc0_credit : 1; + mmr_t overflow0_vc0_credit : 1; + mmr_t overflow_fifo13_vc2_credit : 1; + mmr_t overflow_fifo13_vc0_credit : 1; + mmr_t overflow_fifo02_vc2_credit : 1; + mmr_t overflow_fifo02_vc0_credit : 1; + mmr_t overflow_fifo13_vc3_push : 1; + mmr_t overflow_fifo13_vc1_push : 1; + mmr_t overflow_fifo02_vc2_push : 1; + mmr_t overflow_fifo02_vc0_push : 1; + mmr_t overflow_fifo13_vc3_pop : 1; + mmr_t overflow_fifo13_vc1_pop : 1; + mmr_t overflow_fifo02_vc2_pop : 1; + mmr_t overflow_fifo02_vc0_pop : 1; + mmr_t overflow_fifo13_debit2 : 1; + mmr_t overflow_fifo13_debit0 : 1; + mmr_t overflow_fifo02_debit2 : 1; + mmr_t overflow_fifo02_debit0 : 1; + } sh_ni1_first_error_1_s; +} sh_ni1_first_error_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_FIRST_ERROR_2" */ +/* ni1 First Error Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_first_error_2_u { + mmr_t sh_ni1_first_error_2_regval; + struct { + mmr_t illegal_vcni : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vciilb : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow2_vc2_credit : 1; + mmr_t reserved_0 : 10; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + mmr_t retry_timeout_error : 1; + mmr_t reserved_1 : 1; + } sh_ni1_first_error_2_s; +} sh_ni1_first_error_2_u_t; +#else +typedef union sh_ni1_first_error_2_u { + mmr_t sh_ni1_first_error_2_regval; + struct { + mmr_t reserved_1 : 1; + mmr_t retry_timeout_error : 1; + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t llp_deadlock_vc3 : 1; + mmr_t llp_deadlock_vc2 : 1; + mmr_t llp_deadlock_vc1 : 1; + mmr_t llp_deadlock_vc0 : 1; + mmr_t underflow_ni_fifo_vc3_credit : 1; + mmr_t underflow_ni_fifo_vc2_credit : 1; + mmr_t underflow_ni_fifo_vc1_credit : 1; + mmr_t underflow_ni_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_credit : 1; + mmr_t underflow_md_fifo_vc0_credit : 1; + mmr_t underflow_iilb_fifo_vc2_credit : 1; + mmr_t underflow_iilb_fifo_vc0_credit : 1; + mmr_t underflow_pi_fifo_vc2_credit : 1; + mmr_t underflow_pi_fifo_vc0_credit : 1; + mmr_t underflow_md_fifo_vc2_push : 1; + mmr_t underflow_md_fifo_vc0_push : 1; + mmr_t underflow_iilb_fifo_vc2_push : 1; + mmr_t underflow_iilb_fifo_vc0_push : 1; + mmr_t underflow_pi_fifo_vc2_push : 1; + mmr_t underflow_pi_fifo_vc0_push : 1; + mmr_t underflow_ni_fifo_vc2_pop : 1; + mmr_t underflow_ni_fifo_vc0_pop : 1; + mmr_t underflow_md_fifo_vc2_pop : 1; + mmr_t underflow_md_fifo_vc0_pop : 1; + mmr_t underflow_iilb_fifo_vc2_pop : 1; + mmr_t underflow_iilb_fifo_vc0_pop : 1; + mmr_t underflow_pi_fifo_vc2_pop : 1; + mmr_t underflow_pi_fifo_vc0_pop : 1; + mmr_t reserved_0 : 10; + mmr_t underflow2_vc2_credit : 1; + mmr_t underflow1_vc2_credit : 1; + mmr_t underflow0_vc2_credit : 1; + mmr_t underflow2_vc0_credit : 1; + mmr_t underflow1_vc0_credit : 1; + mmr_t underflow0_vc0_credit : 1; + mmr_t underflow_fifo13_vc2_credit : 1; + mmr_t underflow_fifo13_vc0_credit : 1; + mmr_t underflow_fifo02_vc2_credit : 1; + mmr_t underflow_fifo02_vc0_credit : 1; + mmr_t underflow_fifo13_vc3_push : 1; + mmr_t underflow_fifo13_vc1_push : 1; + mmr_t underflow_fifo02_vc2_push : 1; + mmr_t underflow_fifo02_vc0_push : 1; + mmr_t underflow_fifo13_vc3_pop : 1; + mmr_t underflow_fifo13_vc1_pop : 1; + mmr_t underflow_fifo02_vc2_pop : 1; + mmr_t underflow_fifo02_vc0_pop : 1; + mmr_t illegal_vciilb : 1; + mmr_t illegal_vcmd : 1; + mmr_t illegal_vcpi : 1; + mmr_t illegal_vcni : 1; + } sh_ni1_first_error_2_s; +} sh_ni1_first_error_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_DETAIL_1" */ +/* ni1 Chiplet no match header bits 63:0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_error_detail_1_u { + mmr_t sh_ni1_error_detail_1_regval; + struct { + mmr_t header : 64; + } sh_ni1_error_detail_1_s; +} sh_ni1_error_detail_1_u_t; +#else +typedef union sh_ni1_error_detail_1_u { + mmr_t sh_ni1_error_detail_1_regval; + struct { + mmr_t header : 64; + } sh_ni1_error_detail_1_s; +} sh_ni1_error_detail_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_DETAIL_2" */ +/* ni1 Chiplet no match header bits 127:64 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_error_detail_2_u { + mmr_t sh_ni1_error_detail_2_regval; + struct { + mmr_t header : 64; + } sh_ni1_error_detail_2_s; +} sh_ni1_error_detail_2_u_t; +#else +typedef union sh_ni1_error_detail_2_u { + mmr_t sh_ni1_error_detail_2_regval; + struct { + mmr_t header : 64; + } sh_ni1_error_detail_2_s; +} sh_ni1_error_detail_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_CORRECTED_DETAIL_1" */ +/* Corrected error details */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_corrected_detail_1_u { + mmr_t sh_xn_corrected_detail_1_regval; + struct { + mmr_t ecc0_syndrome : 8; + mmr_t ecc0_wc : 2; + mmr_t ecc0_vc : 2; + mmr_t reserved_0 : 4; + mmr_t ecc1_syndrome : 8; + mmr_t ecc1_wc : 2; + mmr_t ecc1_vc : 2; + mmr_t reserved_1 : 4; + mmr_t ecc2_syndrome : 8; + mmr_t ecc2_wc : 2; + mmr_t ecc2_vc : 2; + mmr_t reserved_2 : 4; + mmr_t ecc3_syndrome : 8; + mmr_t ecc3_wc : 2; + mmr_t ecc3_vc : 2; + mmr_t reserved_3 : 4; + } sh_xn_corrected_detail_1_s; +} sh_xn_corrected_detail_1_u_t; +#else +typedef union sh_xn_corrected_detail_1_u { + mmr_t sh_xn_corrected_detail_1_regval; + struct { + mmr_t reserved_3 : 4; + mmr_t ecc3_vc : 2; + mmr_t ecc3_wc : 2; + mmr_t ecc3_syndrome : 8; + mmr_t reserved_2 : 4; + mmr_t ecc2_vc : 2; + mmr_t ecc2_wc : 2; + mmr_t ecc2_syndrome : 8; + mmr_t reserved_1 : 4; + mmr_t ecc1_vc : 2; + mmr_t ecc1_wc : 2; + mmr_t ecc1_syndrome : 8; + mmr_t reserved_0 : 4; + mmr_t ecc0_vc : 2; + mmr_t ecc0_wc : 2; + mmr_t ecc0_syndrome : 8; + } sh_xn_corrected_detail_1_s; +} sh_xn_corrected_detail_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_CORRECTED_DETAIL_2" */ +/* Corrected error data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_corrected_detail_2_u { + mmr_t sh_xn_corrected_detail_2_regval; + struct { + mmr_t data : 64; + } sh_xn_corrected_detail_2_s; +} sh_xn_corrected_detail_2_u_t; +#else +typedef union sh_xn_corrected_detail_2_u { + mmr_t sh_xn_corrected_detail_2_regval; + struct { + mmr_t data : 64; + } sh_xn_corrected_detail_2_s; +} sh_xn_corrected_detail_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_CORRECTED_DETAIL_3" */ +/* Corrected error header0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_corrected_detail_3_u { + mmr_t sh_xn_corrected_detail_3_regval; + struct { + mmr_t header0 : 64; + } sh_xn_corrected_detail_3_s; +} sh_xn_corrected_detail_3_u_t; +#else +typedef union sh_xn_corrected_detail_3_u { + mmr_t sh_xn_corrected_detail_3_regval; + struct { + mmr_t header0 : 64; + } sh_xn_corrected_detail_3_s; +} sh_xn_corrected_detail_3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_CORRECTED_DETAIL_4" */ +/* Corrected error header1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_corrected_detail_4_u { + mmr_t sh_xn_corrected_detail_4_regval; + struct { + mmr_t header1 : 42; + mmr_t reserved_0 : 20; + mmr_t err_group : 2; + } sh_xn_corrected_detail_4_s; +} sh_xn_corrected_detail_4_u_t; +#else +typedef union sh_xn_corrected_detail_4_u { + mmr_t sh_xn_corrected_detail_4_regval; + struct { + mmr_t err_group : 2; + mmr_t reserved_0 : 20; + mmr_t header1 : 42; + } sh_xn_corrected_detail_4_s; +} sh_xn_corrected_detail_4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_UNCORRECTED_DETAIL_1" */ +/* Uncorrected error details */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_uncorrected_detail_1_u { + mmr_t sh_xn_uncorrected_detail_1_regval; + struct { + mmr_t ecc0_syndrome : 8; + mmr_t ecc0_wc : 2; + mmr_t ecc0_vc : 2; + mmr_t reserved_0 : 4; + mmr_t ecc1_syndrome : 8; + mmr_t ecc1_wc : 2; + mmr_t ecc1_vc : 2; + mmr_t reserved_1 : 4; + mmr_t ecc2_syndrome : 8; + mmr_t ecc2_wc : 2; + mmr_t ecc2_vc : 2; + mmr_t reserved_2 : 4; + mmr_t ecc3_syndrome : 8; + mmr_t ecc3_wc : 2; + mmr_t ecc3_vc : 2; + mmr_t reserved_3 : 4; + } sh_xn_uncorrected_detail_1_s; +} sh_xn_uncorrected_detail_1_u_t; +#else +typedef union sh_xn_uncorrected_detail_1_u { + mmr_t sh_xn_uncorrected_detail_1_regval; + struct { + mmr_t reserved_3 : 4; + mmr_t ecc3_vc : 2; + mmr_t ecc3_wc : 2; + mmr_t ecc3_syndrome : 8; + mmr_t reserved_2 : 4; + mmr_t ecc2_vc : 2; + mmr_t ecc2_wc : 2; + mmr_t ecc2_syndrome : 8; + mmr_t reserved_1 : 4; + mmr_t ecc1_vc : 2; + mmr_t ecc1_wc : 2; + mmr_t ecc1_syndrome : 8; + mmr_t reserved_0 : 4; + mmr_t ecc0_vc : 2; + mmr_t ecc0_wc : 2; + mmr_t ecc0_syndrome : 8; + } sh_xn_uncorrected_detail_1_s; +} sh_xn_uncorrected_detail_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_UNCORRECTED_DETAIL_2" */ +/* Uncorrected error data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_uncorrected_detail_2_u { + mmr_t sh_xn_uncorrected_detail_2_regval; + struct { + mmr_t data : 64; + } sh_xn_uncorrected_detail_2_s; +} sh_xn_uncorrected_detail_2_u_t; +#else +typedef union sh_xn_uncorrected_detail_2_u { + mmr_t sh_xn_uncorrected_detail_2_regval; + struct { + mmr_t data : 64; + } sh_xn_uncorrected_detail_2_s; +} sh_xn_uncorrected_detail_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_UNCORRECTED_DETAIL_3" */ +/* Uncorrected error header0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_uncorrected_detail_3_u { + mmr_t sh_xn_uncorrected_detail_3_regval; + struct { + mmr_t header0 : 64; + } sh_xn_uncorrected_detail_3_s; +} sh_xn_uncorrected_detail_3_u_t; +#else +typedef union sh_xn_uncorrected_detail_3_u { + mmr_t sh_xn_uncorrected_detail_3_regval; + struct { + mmr_t header0 : 64; + } sh_xn_uncorrected_detail_3_s; +} sh_xn_uncorrected_detail_3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_UNCORRECTED_DETAIL_4" */ +/* Uncorrected error header1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_uncorrected_detail_4_u { + mmr_t sh_xn_uncorrected_detail_4_regval; + struct { + mmr_t header1 : 42; + mmr_t reserved_0 : 20; + mmr_t err_group : 2; + } sh_xn_uncorrected_detail_4_s; +} sh_xn_uncorrected_detail_4_u_t; +#else +typedef union sh_xn_uncorrected_detail_4_u { + mmr_t sh_xn_uncorrected_detail_4_regval; + struct { + mmr_t err_group : 2; + mmr_t reserved_0 : 20; + mmr_t header1 : 42; + } sh_xn_uncorrected_detail_4_s; +} sh_xn_uncorrected_detail_4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_ERROR_DETAIL_1" */ +/* Look Up Table Address (md) */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_error_detail_1_u { + mmr_t sh_xnmd_error_detail_1_regval; + struct { + mmr_t lut_addr : 11; + mmr_t reserved_0 : 53; + } sh_xnmd_error_detail_1_s; +} sh_xnmd_error_detail_1_u_t; +#else +typedef union sh_xnmd_error_detail_1_u { + mmr_t sh_xnmd_error_detail_1_regval; + struct { + mmr_t reserved_0 : 53; + mmr_t lut_addr : 11; + } sh_xnmd_error_detail_1_s; +} sh_xnmd_error_detail_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_ERROR_DETAIL_1" */ +/* Look Up Table Address (pi) */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_error_detail_1_u { + mmr_t sh_xnpi_error_detail_1_regval; + struct { + mmr_t lut_addr : 11; + mmr_t reserved_0 : 53; + } sh_xnpi_error_detail_1_s; +} sh_xnpi_error_detail_1_u_t; +#else +typedef union sh_xnpi_error_detail_1_u { + mmr_t sh_xnpi_error_detail_1_regval; + struct { + mmr_t reserved_0 : 53; + mmr_t lut_addr : 11; + } sh_xnpi_error_detail_1_s; +} sh_xnpi_error_detail_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_DETAIL_1" */ +/* Chiplet NoMatch header [63:0] */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_error_detail_1_u { + mmr_t sh_xniilb_error_detail_1_regval; + struct { + mmr_t header : 64; + } sh_xniilb_error_detail_1_s; +} sh_xniilb_error_detail_1_u_t; +#else +typedef union sh_xniilb_error_detail_1_u { + mmr_t sh_xniilb_error_detail_1_regval; + struct { + mmr_t header : 64; + } sh_xniilb_error_detail_1_s; +} sh_xniilb_error_detail_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_DETAIL_2" */ +/* Chiplet NoMatch header [127:64] */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_error_detail_2_u { + mmr_t sh_xniilb_error_detail_2_regval; + struct { + mmr_t header : 64; + } sh_xniilb_error_detail_2_s; +} sh_xniilb_error_detail_2_u_t; +#else +typedef union sh_xniilb_error_detail_2_u { + mmr_t sh_xniilb_error_detail_2_regval; + struct { + mmr_t header : 64; + } sh_xniilb_error_detail_2_s; +} sh_xniilb_error_detail_2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_DETAIL_3" */ +/* Look Up Table Address (iilb) */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_error_detail_3_u { + mmr_t sh_xniilb_error_detail_3_regval; + struct { + mmr_t lut_addr : 11; + mmr_t reserved_0 : 53; + } sh_xniilb_error_detail_3_s; +} sh_xniilb_error_detail_3_u_t; +#else +typedef union sh_xniilb_error_detail_3_u { + mmr_t sh_xniilb_error_detail_3_regval; + struct { + mmr_t reserved_0 : 53; + mmr_t lut_addr : 11; + } sh_xniilb_error_detail_3_s; +} sh_xniilb_error_detail_3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI0_ERROR_DETAIL_3" */ +/* Look Up Table Address (ni0) */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni0_error_detail_3_u { + mmr_t sh_ni0_error_detail_3_regval; + struct { + mmr_t lut_addr : 11; + mmr_t reserved_0 : 53; + } sh_ni0_error_detail_3_s; +} sh_ni0_error_detail_3_u_t; +#else +typedef union sh_ni0_error_detail_3_u { + mmr_t sh_ni0_error_detail_3_regval; + struct { + mmr_t reserved_0 : 53; + mmr_t lut_addr : 11; + } sh_ni0_error_detail_3_s; +} sh_ni0_error_detail_3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_NI1_ERROR_DETAIL_3" */ +/* Look Up Table Address (ni1) */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ni1_error_detail_3_u { + mmr_t sh_ni1_error_detail_3_regval; + struct { + mmr_t lut_addr : 11; + mmr_t reserved_0 : 53; + } sh_ni1_error_detail_3_s; +} sh_ni1_error_detail_3_u_t; +#else +typedef union sh_ni1_error_detail_3_u { + mmr_t sh_ni1_error_detail_3_regval; + struct { + mmr_t reserved_0 : 53; + mmr_t lut_addr : 11; + } sh_ni1_error_detail_3_s; +} sh_ni1_error_detail_3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_ERROR_SUMMARY" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_error_summary_u { + mmr_t sh_xn_error_summary_regval; + struct { + mmr_t ni0_pop_overflow : 1; + mmr_t ni0_push_overflow : 1; + mmr_t ni0_credit_overflow : 1; + mmr_t ni0_debit_overflow : 1; + mmr_t ni0_pop_underflow : 1; + mmr_t ni0_push_underflow : 1; + mmr_t ni0_credit_underflow : 1; + mmr_t ni0_llp_error : 1; + mmr_t ni0_pipe_error : 1; + mmr_t ni1_pop_overflow : 1; + mmr_t ni1_push_overflow : 1; + mmr_t ni1_credit_overflow : 1; + mmr_t ni1_debit_overflow : 1; + mmr_t ni1_pop_underflow : 1; + mmr_t ni1_push_underflow : 1; + mmr_t ni1_credit_underflow : 1; + mmr_t ni1_llp_error : 1; + mmr_t ni1_pipe_error : 1; + mmr_t xnmd_credit_overflow : 1; + mmr_t xnmd_debit_overflow : 1; + mmr_t xnmd_data_buff_overflow : 1; + mmr_t xnmd_credit_underflow : 1; + mmr_t xnmd_sbe_error : 1; + mmr_t xnmd_uce_error : 1; + mmr_t xnmd_lut_error : 1; + mmr_t xnpi_credit_overflow : 1; + mmr_t xnpi_debit_overflow : 1; + mmr_t xnpi_data_buff_overflow : 1; + mmr_t xnpi_credit_underflow : 1; + mmr_t xnpi_sbe_error : 1; + mmr_t xnpi_uce_error : 1; + mmr_t xnpi_lut_error : 1; + mmr_t iilb_debit_overflow : 1; + mmr_t iilb_credit_overflow : 1; + mmr_t iilb_fifo_overflow : 1; + mmr_t iilb_credit_underflow : 1; + mmr_t iilb_fifo_underflow : 1; + mmr_t iilb_chiplet_or_lut : 1; + mmr_t reserved_0 : 26; + } sh_xn_error_summary_s; +} sh_xn_error_summary_u_t; +#else +typedef union sh_xn_error_summary_u { + mmr_t sh_xn_error_summary_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t iilb_chiplet_or_lut : 1; + mmr_t iilb_fifo_underflow : 1; + mmr_t iilb_credit_underflow : 1; + mmr_t iilb_fifo_overflow : 1; + mmr_t iilb_credit_overflow : 1; + mmr_t iilb_debit_overflow : 1; + mmr_t xnpi_lut_error : 1; + mmr_t xnpi_uce_error : 1; + mmr_t xnpi_sbe_error : 1; + mmr_t xnpi_credit_underflow : 1; + mmr_t xnpi_data_buff_overflow : 1; + mmr_t xnpi_debit_overflow : 1; + mmr_t xnpi_credit_overflow : 1; + mmr_t xnmd_lut_error : 1; + mmr_t xnmd_uce_error : 1; + mmr_t xnmd_sbe_error : 1; + mmr_t xnmd_credit_underflow : 1; + mmr_t xnmd_data_buff_overflow : 1; + mmr_t xnmd_debit_overflow : 1; + mmr_t xnmd_credit_overflow : 1; + mmr_t ni1_pipe_error : 1; + mmr_t ni1_llp_error : 1; + mmr_t ni1_credit_underflow : 1; + mmr_t ni1_push_underflow : 1; + mmr_t ni1_pop_underflow : 1; + mmr_t ni1_debit_overflow : 1; + mmr_t ni1_credit_overflow : 1; + mmr_t ni1_push_overflow : 1; + mmr_t ni1_pop_overflow : 1; + mmr_t ni0_pipe_error : 1; + mmr_t ni0_llp_error : 1; + mmr_t ni0_credit_underflow : 1; + mmr_t ni0_push_underflow : 1; + mmr_t ni0_pop_underflow : 1; + mmr_t ni0_debit_overflow : 1; + mmr_t ni0_credit_overflow : 1; + mmr_t ni0_push_overflow : 1; + mmr_t ni0_pop_overflow : 1; + } sh_xn_error_summary_s; +} sh_xn_error_summary_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_ERROR_OVERFLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_error_overflow_u { + mmr_t sh_xn_error_overflow_regval; + struct { + mmr_t ni0_pop_overflow : 1; + mmr_t ni0_push_overflow : 1; + mmr_t ni0_credit_overflow : 1; + mmr_t ni0_debit_overflow : 1; + mmr_t ni0_pop_underflow : 1; + mmr_t ni0_push_underflow : 1; + mmr_t ni0_credit_underflow : 1; + mmr_t ni0_llp_error : 1; + mmr_t ni0_pipe_error : 1; + mmr_t ni1_pop_overflow : 1; + mmr_t ni1_push_overflow : 1; + mmr_t ni1_credit_overflow : 1; + mmr_t ni1_debit_overflow : 1; + mmr_t ni1_pop_underflow : 1; + mmr_t ni1_push_underflow : 1; + mmr_t ni1_credit_underflow : 1; + mmr_t ni1_llp_error : 1; + mmr_t ni1_pipe_error : 1; + mmr_t xnmd_credit_overflow : 1; + mmr_t xnmd_debit_overflow : 1; + mmr_t xnmd_data_buff_overflow : 1; + mmr_t xnmd_credit_underflow : 1; + mmr_t xnmd_sbe_error : 1; + mmr_t xnmd_uce_error : 1; + mmr_t xnmd_lut_error : 1; + mmr_t xnpi_credit_overflow : 1; + mmr_t xnpi_debit_overflow : 1; + mmr_t xnpi_data_buff_overflow : 1; + mmr_t xnpi_credit_underflow : 1; + mmr_t xnpi_sbe_error : 1; + mmr_t xnpi_uce_error : 1; + mmr_t xnpi_lut_error : 1; + mmr_t iilb_debit_overflow : 1; + mmr_t iilb_credit_overflow : 1; + mmr_t iilb_fifo_overflow : 1; + mmr_t iilb_credit_underflow : 1; + mmr_t iilb_fifo_underflow : 1; + mmr_t iilb_chiplet_or_lut : 1; + mmr_t reserved_0 : 26; + } sh_xn_error_overflow_s; +} sh_xn_error_overflow_u_t; +#else +typedef union sh_xn_error_overflow_u { + mmr_t sh_xn_error_overflow_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t iilb_chiplet_or_lut : 1; + mmr_t iilb_fifo_underflow : 1; + mmr_t iilb_credit_underflow : 1; + mmr_t iilb_fifo_overflow : 1; + mmr_t iilb_credit_overflow : 1; + mmr_t iilb_debit_overflow : 1; + mmr_t xnpi_lut_error : 1; + mmr_t xnpi_uce_error : 1; + mmr_t xnpi_sbe_error : 1; + mmr_t xnpi_credit_underflow : 1; + mmr_t xnpi_data_buff_overflow : 1; + mmr_t xnpi_debit_overflow : 1; + mmr_t xnpi_credit_overflow : 1; + mmr_t xnmd_lut_error : 1; + mmr_t xnmd_uce_error : 1; + mmr_t xnmd_sbe_error : 1; + mmr_t xnmd_credit_underflow : 1; + mmr_t xnmd_data_buff_overflow : 1; + mmr_t xnmd_debit_overflow : 1; + mmr_t xnmd_credit_overflow : 1; + mmr_t ni1_pipe_error : 1; + mmr_t ni1_llp_error : 1; + mmr_t ni1_credit_underflow : 1; + mmr_t ni1_push_underflow : 1; + mmr_t ni1_pop_underflow : 1; + mmr_t ni1_debit_overflow : 1; + mmr_t ni1_credit_overflow : 1; + mmr_t ni1_push_overflow : 1; + mmr_t ni1_pop_overflow : 1; + mmr_t ni0_pipe_error : 1; + mmr_t ni0_llp_error : 1; + mmr_t ni0_credit_underflow : 1; + mmr_t ni0_push_underflow : 1; + mmr_t ni0_pop_underflow : 1; + mmr_t ni0_debit_overflow : 1; + mmr_t ni0_credit_overflow : 1; + mmr_t ni0_push_overflow : 1; + mmr_t ni0_pop_overflow : 1; + } sh_xn_error_overflow_s; +} sh_xn_error_overflow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_ERROR_MASK" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_error_mask_u { + mmr_t sh_xn_error_mask_regval; + struct { + mmr_t ni0_pop_overflow : 1; + mmr_t ni0_push_overflow : 1; + mmr_t ni0_credit_overflow : 1; + mmr_t ni0_debit_overflow : 1; + mmr_t ni0_pop_underflow : 1; + mmr_t ni0_push_underflow : 1; + mmr_t ni0_credit_underflow : 1; + mmr_t ni0_llp_error : 1; + mmr_t ni0_pipe_error : 1; + mmr_t ni1_pop_overflow : 1; + mmr_t ni1_push_overflow : 1; + mmr_t ni1_credit_overflow : 1; + mmr_t ni1_debit_overflow : 1; + mmr_t ni1_pop_underflow : 1; + mmr_t ni1_push_underflow : 1; + mmr_t ni1_credit_underflow : 1; + mmr_t ni1_llp_error : 1; + mmr_t ni1_pipe_error : 1; + mmr_t xnmd_credit_overflow : 1; + mmr_t xnmd_debit_overflow : 1; + mmr_t xnmd_data_buff_overflow : 1; + mmr_t xnmd_credit_underflow : 1; + mmr_t xnmd_sbe_error : 1; + mmr_t xnmd_uce_error : 1; + mmr_t xnmd_lut_error : 1; + mmr_t xnpi_credit_overflow : 1; + mmr_t xnpi_debit_overflow : 1; + mmr_t xnpi_data_buff_overflow : 1; + mmr_t xnpi_credit_underflow : 1; + mmr_t xnpi_sbe_error : 1; + mmr_t xnpi_uce_error : 1; + mmr_t xnpi_lut_error : 1; + mmr_t iilb_debit_overflow : 1; + mmr_t iilb_credit_overflow : 1; + mmr_t iilb_fifo_overflow : 1; + mmr_t iilb_credit_underflow : 1; + mmr_t iilb_fifo_underflow : 1; + mmr_t iilb_chiplet_or_lut : 1; + mmr_t reserved_0 : 26; + } sh_xn_error_mask_s; +} sh_xn_error_mask_u_t; +#else +typedef union sh_xn_error_mask_u { + mmr_t sh_xn_error_mask_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t iilb_chiplet_or_lut : 1; + mmr_t iilb_fifo_underflow : 1; + mmr_t iilb_credit_underflow : 1; + mmr_t iilb_fifo_overflow : 1; + mmr_t iilb_credit_overflow : 1; + mmr_t iilb_debit_overflow : 1; + mmr_t xnpi_lut_error : 1; + mmr_t xnpi_uce_error : 1; + mmr_t xnpi_sbe_error : 1; + mmr_t xnpi_credit_underflow : 1; + mmr_t xnpi_data_buff_overflow : 1; + mmr_t xnpi_debit_overflow : 1; + mmr_t xnpi_credit_overflow : 1; + mmr_t xnmd_lut_error : 1; + mmr_t xnmd_uce_error : 1; + mmr_t xnmd_sbe_error : 1; + mmr_t xnmd_credit_underflow : 1; + mmr_t xnmd_data_buff_overflow : 1; + mmr_t xnmd_debit_overflow : 1; + mmr_t xnmd_credit_overflow : 1; + mmr_t ni1_pipe_error : 1; + mmr_t ni1_llp_error : 1; + mmr_t ni1_credit_underflow : 1; + mmr_t ni1_push_underflow : 1; + mmr_t ni1_pop_underflow : 1; + mmr_t ni1_debit_overflow : 1; + mmr_t ni1_credit_overflow : 1; + mmr_t ni1_push_overflow : 1; + mmr_t ni1_pop_overflow : 1; + mmr_t ni0_pipe_error : 1; + mmr_t ni0_llp_error : 1; + mmr_t ni0_credit_underflow : 1; + mmr_t ni0_push_underflow : 1; + mmr_t ni0_pop_underflow : 1; + mmr_t ni0_debit_overflow : 1; + mmr_t ni0_credit_overflow : 1; + mmr_t ni0_push_overflow : 1; + mmr_t ni0_pop_overflow : 1; + } sh_xn_error_mask_s; +} sh_xn_error_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_FIRST_ERROR" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_first_error_u { + mmr_t sh_xn_first_error_regval; + struct { + mmr_t ni0_pop_overflow : 1; + mmr_t ni0_push_overflow : 1; + mmr_t ni0_credit_overflow : 1; + mmr_t ni0_debit_overflow : 1; + mmr_t ni0_pop_underflow : 1; + mmr_t ni0_push_underflow : 1; + mmr_t ni0_credit_underflow : 1; + mmr_t ni0_llp_error : 1; + mmr_t ni0_pipe_error : 1; + mmr_t ni1_pop_overflow : 1; + mmr_t ni1_push_overflow : 1; + mmr_t ni1_credit_overflow : 1; + mmr_t ni1_debit_overflow : 1; + mmr_t ni1_pop_underflow : 1; + mmr_t ni1_push_underflow : 1; + mmr_t ni1_credit_underflow : 1; + mmr_t ni1_llp_error : 1; + mmr_t ni1_pipe_error : 1; + mmr_t xnmd_credit_overflow : 1; + mmr_t xnmd_debit_overflow : 1; + mmr_t xnmd_data_buff_overflow : 1; + mmr_t xnmd_credit_underflow : 1; + mmr_t xnmd_sbe_error : 1; + mmr_t xnmd_uce_error : 1; + mmr_t xnmd_lut_error : 1; + mmr_t xnpi_credit_overflow : 1; + mmr_t xnpi_debit_overflow : 1; + mmr_t xnpi_data_buff_overflow : 1; + mmr_t xnpi_credit_underflow : 1; + mmr_t xnpi_sbe_error : 1; + mmr_t xnpi_uce_error : 1; + mmr_t xnpi_lut_error : 1; + mmr_t iilb_debit_overflow : 1; + mmr_t iilb_credit_overflow : 1; + mmr_t iilb_fifo_overflow : 1; + mmr_t iilb_credit_underflow : 1; + mmr_t iilb_fifo_underflow : 1; + mmr_t iilb_chiplet_or_lut : 1; + mmr_t reserved_0 : 26; + } sh_xn_first_error_s; +} sh_xn_first_error_u_t; +#else +typedef union sh_xn_first_error_u { + mmr_t sh_xn_first_error_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t iilb_chiplet_or_lut : 1; + mmr_t iilb_fifo_underflow : 1; + mmr_t iilb_credit_underflow : 1; + mmr_t iilb_fifo_overflow : 1; + mmr_t iilb_credit_overflow : 1; + mmr_t iilb_debit_overflow : 1; + mmr_t xnpi_lut_error : 1; + mmr_t xnpi_uce_error : 1; + mmr_t xnpi_sbe_error : 1; + mmr_t xnpi_credit_underflow : 1; + mmr_t xnpi_data_buff_overflow : 1; + mmr_t xnpi_debit_overflow : 1; + mmr_t xnpi_credit_overflow : 1; + mmr_t xnmd_lut_error : 1; + mmr_t xnmd_uce_error : 1; + mmr_t xnmd_sbe_error : 1; + mmr_t xnmd_credit_underflow : 1; + mmr_t xnmd_data_buff_overflow : 1; + mmr_t xnmd_debit_overflow : 1; + mmr_t xnmd_credit_overflow : 1; + mmr_t ni1_pipe_error : 1; + mmr_t ni1_llp_error : 1; + mmr_t ni1_credit_underflow : 1; + mmr_t ni1_push_underflow : 1; + mmr_t ni1_pop_underflow : 1; + mmr_t ni1_debit_overflow : 1; + mmr_t ni1_credit_overflow : 1; + mmr_t ni1_push_overflow : 1; + mmr_t ni1_pop_overflow : 1; + mmr_t ni0_pipe_error : 1; + mmr_t ni0_llp_error : 1; + mmr_t ni0_credit_underflow : 1; + mmr_t ni0_push_underflow : 1; + mmr_t ni0_pop_underflow : 1; + mmr_t ni0_debit_overflow : 1; + mmr_t ni0_credit_overflow : 1; + mmr_t ni0_push_overflow : 1; + mmr_t ni0_pop_overflow : 1; + } sh_xn_first_error_s; +} sh_xn_first_error_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_SUMMARY" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_error_summary_u { + mmr_t sh_xniilb_error_summary_regval; + struct { + mmr_t overflow_ii_debit0 : 1; + mmr_t overflow_ii_debit2 : 1; + mmr_t overflow_lb_debit0 : 1; + mmr_t overflow_lb_debit2 : 1; + mmr_t overflow_ii_vc0 : 1; + mmr_t overflow_ii_vc2 : 1; + mmr_t underflow_ii_vc0 : 1; + mmr_t underflow_ii_vc2 : 1; + mmr_t overflow_lb_vc0 : 1; + mmr_t overflow_lb_vc2 : 1; + mmr_t underflow_lb_vc0 : 1; + mmr_t underflow_lb_vc2 : 1; + mmr_t overflow_pi_vc0_credit_in : 1; + mmr_t overflow_iilb_vc0_credit_in : 1; + mmr_t overflow_md_vc0_credit_in : 1; + mmr_t overflow_ni0_vc0_credit_in : 1; + mmr_t overflow_ni1_vc0_credit_in : 1; + mmr_t overflow_pi_vc2_credit_in : 1; + mmr_t overflow_iilb_vc2_credit_in : 1; + mmr_t overflow_md_vc2_credit_in : 1; + mmr_t overflow_ni0_vc2_credit_in : 1; + mmr_t overflow_ni1_vc2_credit_in : 1; + mmr_t underflow_pi_vc0_credit_in : 1; + mmr_t underflow_iilb_vc0_credit_in : 1; + mmr_t underflow_md_vc0_credit_in : 1; + mmr_t underflow_ni0_vc0_credit_in : 1; + mmr_t underflow_ni1_vc0_credit_in : 1; + mmr_t underflow_pi_vc2_credit_in : 1; + mmr_t underflow_iilb_vc2_credit_in : 1; + mmr_t underflow_md_vc2_credit_in : 1; + mmr_t underflow_ni0_vc2_credit_in : 1; + mmr_t underflow_ni1_vc2_credit_in : 1; + mmr_t overflow_pi_debit0 : 1; + mmr_t overflow_pi_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_md_debit0 : 1; + mmr_t overflow_md_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_pi_vc0_credit_out : 1; + mmr_t overflow_pi_vc2_credit_out : 1; + mmr_t overflow_md_vc0_credit_out : 1; + mmr_t overflow_md_vc2_credit_out : 1; + mmr_t overflow_iilb_vc0_credit_out : 1; + mmr_t overflow_iilb_vc2_credit_out : 1; + mmr_t overflow_ni0_vc0_credit_out : 1; + mmr_t overflow_ni0_vc2_credit_out : 1; + mmr_t overflow_ni1_vc0_credit_out : 1; + mmr_t overflow_ni1_vc2_credit_out : 1; + mmr_t underflow_pi_vc0_credit_out : 1; + mmr_t underflow_pi_vc2_credit_out : 1; + mmr_t underflow_md_vc0_credit_out : 1; + mmr_t underflow_md_vc2_credit_out : 1; + mmr_t underflow_iilb_vc0_credit_out : 1; + mmr_t underflow_iilb_vc2_credit_out : 1; + mmr_t underflow_ni0_vc0_credit_out : 1; + mmr_t underflow_ni0_vc2_credit_out : 1; + mmr_t underflow_ni1_vc0_credit_out : 1; + mmr_t underflow_ni1_vc2_credit_out : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + } sh_xniilb_error_summary_s; +} sh_xniilb_error_summary_u_t; +#else +typedef union sh_xniilb_error_summary_u { + mmr_t sh_xniilb_error_summary_regval; + struct { + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t underflow_ni1_vc2_credit_out : 1; + mmr_t underflow_ni1_vc0_credit_out : 1; + mmr_t underflow_ni0_vc2_credit_out : 1; + mmr_t underflow_ni0_vc0_credit_out : 1; + mmr_t underflow_iilb_vc2_credit_out : 1; + mmr_t underflow_iilb_vc0_credit_out : 1; + mmr_t underflow_md_vc2_credit_out : 1; + mmr_t underflow_md_vc0_credit_out : 1; + mmr_t underflow_pi_vc2_credit_out : 1; + mmr_t underflow_pi_vc0_credit_out : 1; + mmr_t overflow_ni1_vc2_credit_out : 1; + mmr_t overflow_ni1_vc0_credit_out : 1; + mmr_t overflow_ni0_vc2_credit_out : 1; + mmr_t overflow_ni0_vc0_credit_out : 1; + mmr_t overflow_iilb_vc2_credit_out : 1; + mmr_t overflow_iilb_vc0_credit_out : 1; + mmr_t overflow_md_vc2_credit_out : 1; + mmr_t overflow_md_vc0_credit_out : 1; + mmr_t overflow_pi_vc2_credit_out : 1; + mmr_t overflow_pi_vc0_credit_out : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_md_debit2 : 1; + mmr_t overflow_md_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_pi_debit2 : 1; + mmr_t overflow_pi_debit0 : 1; + mmr_t underflow_ni1_vc2_credit_in : 1; + mmr_t underflow_ni0_vc2_credit_in : 1; + mmr_t underflow_md_vc2_credit_in : 1; + mmr_t underflow_iilb_vc2_credit_in : 1; + mmr_t underflow_pi_vc2_credit_in : 1; + mmr_t underflow_ni1_vc0_credit_in : 1; + mmr_t underflow_ni0_vc0_credit_in : 1; + mmr_t underflow_md_vc0_credit_in : 1; + mmr_t underflow_iilb_vc0_credit_in : 1; + mmr_t underflow_pi_vc0_credit_in : 1; + mmr_t overflow_ni1_vc2_credit_in : 1; + mmr_t overflow_ni0_vc2_credit_in : 1; + mmr_t overflow_md_vc2_credit_in : 1; + mmr_t overflow_iilb_vc2_credit_in : 1; + mmr_t overflow_pi_vc2_credit_in : 1; + mmr_t overflow_ni1_vc0_credit_in : 1; + mmr_t overflow_ni0_vc0_credit_in : 1; + mmr_t overflow_md_vc0_credit_in : 1; + mmr_t overflow_iilb_vc0_credit_in : 1; + mmr_t overflow_pi_vc0_credit_in : 1; + mmr_t underflow_lb_vc2 : 1; + mmr_t underflow_lb_vc0 : 1; + mmr_t overflow_lb_vc2 : 1; + mmr_t overflow_lb_vc0 : 1; + mmr_t underflow_ii_vc2 : 1; + mmr_t underflow_ii_vc0 : 1; + mmr_t overflow_ii_vc2 : 1; + mmr_t overflow_ii_vc0 : 1; + mmr_t overflow_lb_debit2 : 1; + mmr_t overflow_lb_debit0 : 1; + mmr_t overflow_ii_debit2 : 1; + mmr_t overflow_ii_debit0 : 1; + } sh_xniilb_error_summary_s; +} sh_xniilb_error_summary_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_OVERFLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_error_overflow_u { + mmr_t sh_xniilb_error_overflow_regval; + struct { + mmr_t overflow_ii_debit0 : 1; + mmr_t overflow_ii_debit2 : 1; + mmr_t overflow_lb_debit0 : 1; + mmr_t overflow_lb_debit2 : 1; + mmr_t overflow_ii_vc0 : 1; + mmr_t overflow_ii_vc2 : 1; + mmr_t underflow_ii_vc0 : 1; + mmr_t underflow_ii_vc2 : 1; + mmr_t overflow_lb_vc0 : 1; + mmr_t overflow_lb_vc2 : 1; + mmr_t underflow_lb_vc0 : 1; + mmr_t underflow_lb_vc2 : 1; + mmr_t overflow_pi_vc0_credit_in : 1; + mmr_t overflow_iilb_vc0_credit_in : 1; + mmr_t overflow_md_vc0_credit_in : 1; + mmr_t overflow_ni0_vc0_credit_in : 1; + mmr_t overflow_ni1_vc0_credit_in : 1; + mmr_t overflow_pi_vc2_credit_in : 1; + mmr_t overflow_iilb_vc2_credit_in : 1; + mmr_t overflow_md_vc2_credit_in : 1; + mmr_t overflow_ni0_vc2_credit_in : 1; + mmr_t overflow_ni1_vc2_credit_in : 1; + mmr_t underflow_pi_vc0_credit_in : 1; + mmr_t underflow_iilb_vc0_credit_in : 1; + mmr_t underflow_md_vc0_credit_in : 1; + mmr_t underflow_ni0_vc0_credit_in : 1; + mmr_t underflow_ni1_vc0_credit_in : 1; + mmr_t underflow_pi_vc2_credit_in : 1; + mmr_t underflow_iilb_vc2_credit_in : 1; + mmr_t underflow_md_vc2_credit_in : 1; + mmr_t underflow_ni0_vc2_credit_in : 1; + mmr_t underflow_ni1_vc2_credit_in : 1; + mmr_t overflow_pi_debit0 : 1; + mmr_t overflow_pi_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_md_debit0 : 1; + mmr_t overflow_md_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_pi_vc0_credit_out : 1; + mmr_t overflow_pi_vc2_credit_out : 1; + mmr_t overflow_md_vc0_credit_out : 1; + mmr_t overflow_md_vc2_credit_out : 1; + mmr_t overflow_iilb_vc0_credit_out : 1; + mmr_t overflow_iilb_vc2_credit_out : 1; + mmr_t overflow_ni0_vc0_credit_out : 1; + mmr_t overflow_ni0_vc2_credit_out : 1; + mmr_t overflow_ni1_vc0_credit_out : 1; + mmr_t overflow_ni1_vc2_credit_out : 1; + mmr_t underflow_pi_vc0_credit_out : 1; + mmr_t underflow_pi_vc2_credit_out : 1; + mmr_t underflow_md_vc0_credit_out : 1; + mmr_t underflow_md_vc2_credit_out : 1; + mmr_t underflow_iilb_vc0_credit_out : 1; + mmr_t underflow_iilb_vc2_credit_out : 1; + mmr_t underflow_ni0_vc0_credit_out : 1; + mmr_t underflow_ni0_vc2_credit_out : 1; + mmr_t underflow_ni1_vc0_credit_out : 1; + mmr_t underflow_ni1_vc2_credit_out : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + } sh_xniilb_error_overflow_s; +} sh_xniilb_error_overflow_u_t; +#else +typedef union sh_xniilb_error_overflow_u { + mmr_t sh_xniilb_error_overflow_regval; + struct { + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t underflow_ni1_vc2_credit_out : 1; + mmr_t underflow_ni1_vc0_credit_out : 1; + mmr_t underflow_ni0_vc2_credit_out : 1; + mmr_t underflow_ni0_vc0_credit_out : 1; + mmr_t underflow_iilb_vc2_credit_out : 1; + mmr_t underflow_iilb_vc0_credit_out : 1; + mmr_t underflow_md_vc2_credit_out : 1; + mmr_t underflow_md_vc0_credit_out : 1; + mmr_t underflow_pi_vc2_credit_out : 1; + mmr_t underflow_pi_vc0_credit_out : 1; + mmr_t overflow_ni1_vc2_credit_out : 1; + mmr_t overflow_ni1_vc0_credit_out : 1; + mmr_t overflow_ni0_vc2_credit_out : 1; + mmr_t overflow_ni0_vc0_credit_out : 1; + mmr_t overflow_iilb_vc2_credit_out : 1; + mmr_t overflow_iilb_vc0_credit_out : 1; + mmr_t overflow_md_vc2_credit_out : 1; + mmr_t overflow_md_vc0_credit_out : 1; + mmr_t overflow_pi_vc2_credit_out : 1; + mmr_t overflow_pi_vc0_credit_out : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_md_debit2 : 1; + mmr_t overflow_md_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_pi_debit2 : 1; + mmr_t overflow_pi_debit0 : 1; + mmr_t underflow_ni1_vc2_credit_in : 1; + mmr_t underflow_ni0_vc2_credit_in : 1; + mmr_t underflow_md_vc2_credit_in : 1; + mmr_t underflow_iilb_vc2_credit_in : 1; + mmr_t underflow_pi_vc2_credit_in : 1; + mmr_t underflow_ni1_vc0_credit_in : 1; + mmr_t underflow_ni0_vc0_credit_in : 1; + mmr_t underflow_md_vc0_credit_in : 1; + mmr_t underflow_iilb_vc0_credit_in : 1; + mmr_t underflow_pi_vc0_credit_in : 1; + mmr_t overflow_ni1_vc2_credit_in : 1; + mmr_t overflow_ni0_vc2_credit_in : 1; + mmr_t overflow_md_vc2_credit_in : 1; + mmr_t overflow_iilb_vc2_credit_in : 1; + mmr_t overflow_pi_vc2_credit_in : 1; + mmr_t overflow_ni1_vc0_credit_in : 1; + mmr_t overflow_ni0_vc0_credit_in : 1; + mmr_t overflow_md_vc0_credit_in : 1; + mmr_t overflow_iilb_vc0_credit_in : 1; + mmr_t overflow_pi_vc0_credit_in : 1; + mmr_t underflow_lb_vc2 : 1; + mmr_t underflow_lb_vc0 : 1; + mmr_t overflow_lb_vc2 : 1; + mmr_t overflow_lb_vc0 : 1; + mmr_t underflow_ii_vc2 : 1; + mmr_t underflow_ii_vc0 : 1; + mmr_t overflow_ii_vc2 : 1; + mmr_t overflow_ii_vc0 : 1; + mmr_t overflow_lb_debit2 : 1; + mmr_t overflow_lb_debit0 : 1; + mmr_t overflow_ii_debit2 : 1; + mmr_t overflow_ii_debit0 : 1; + } sh_xniilb_error_overflow_s; +} sh_xniilb_error_overflow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_ERROR_MASK" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_error_mask_u { + mmr_t sh_xniilb_error_mask_regval; + struct { + mmr_t overflow_ii_debit0 : 1; + mmr_t overflow_ii_debit2 : 1; + mmr_t overflow_lb_debit0 : 1; + mmr_t overflow_lb_debit2 : 1; + mmr_t overflow_ii_vc0 : 1; + mmr_t overflow_ii_vc2 : 1; + mmr_t underflow_ii_vc0 : 1; + mmr_t underflow_ii_vc2 : 1; + mmr_t overflow_lb_vc0 : 1; + mmr_t overflow_lb_vc2 : 1; + mmr_t underflow_lb_vc0 : 1; + mmr_t underflow_lb_vc2 : 1; + mmr_t overflow_pi_vc0_credit_in : 1; + mmr_t overflow_iilb_vc0_credit_in : 1; + mmr_t overflow_md_vc0_credit_in : 1; + mmr_t overflow_ni0_vc0_credit_in : 1; + mmr_t overflow_ni1_vc0_credit_in : 1; + mmr_t overflow_pi_vc2_credit_in : 1; + mmr_t overflow_iilb_vc2_credit_in : 1; + mmr_t overflow_md_vc2_credit_in : 1; + mmr_t overflow_ni0_vc2_credit_in : 1; + mmr_t overflow_ni1_vc2_credit_in : 1; + mmr_t underflow_pi_vc0_credit_in : 1; + mmr_t underflow_iilb_vc0_credit_in : 1; + mmr_t underflow_md_vc0_credit_in : 1; + mmr_t underflow_ni0_vc0_credit_in : 1; + mmr_t underflow_ni1_vc0_credit_in : 1; + mmr_t underflow_pi_vc2_credit_in : 1; + mmr_t underflow_iilb_vc2_credit_in : 1; + mmr_t underflow_md_vc2_credit_in : 1; + mmr_t underflow_ni0_vc2_credit_in : 1; + mmr_t underflow_ni1_vc2_credit_in : 1; + mmr_t overflow_pi_debit0 : 1; + mmr_t overflow_pi_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_md_debit0 : 1; + mmr_t overflow_md_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_pi_vc0_credit_out : 1; + mmr_t overflow_pi_vc2_credit_out : 1; + mmr_t overflow_md_vc0_credit_out : 1; + mmr_t overflow_md_vc2_credit_out : 1; + mmr_t overflow_iilb_vc0_credit_out : 1; + mmr_t overflow_iilb_vc2_credit_out : 1; + mmr_t overflow_ni0_vc0_credit_out : 1; + mmr_t overflow_ni0_vc2_credit_out : 1; + mmr_t overflow_ni1_vc0_credit_out : 1; + mmr_t overflow_ni1_vc2_credit_out : 1; + mmr_t underflow_pi_vc0_credit_out : 1; + mmr_t underflow_pi_vc2_credit_out : 1; + mmr_t underflow_md_vc0_credit_out : 1; + mmr_t underflow_md_vc2_credit_out : 1; + mmr_t underflow_iilb_vc0_credit_out : 1; + mmr_t underflow_iilb_vc2_credit_out : 1; + mmr_t underflow_ni0_vc0_credit_out : 1; + mmr_t underflow_ni0_vc2_credit_out : 1; + mmr_t underflow_ni1_vc0_credit_out : 1; + mmr_t underflow_ni1_vc2_credit_out : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + } sh_xniilb_error_mask_s; +} sh_xniilb_error_mask_u_t; +#else +typedef union sh_xniilb_error_mask_u { + mmr_t sh_xniilb_error_mask_regval; + struct { + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t underflow_ni1_vc2_credit_out : 1; + mmr_t underflow_ni1_vc0_credit_out : 1; + mmr_t underflow_ni0_vc2_credit_out : 1; + mmr_t underflow_ni0_vc0_credit_out : 1; + mmr_t underflow_iilb_vc2_credit_out : 1; + mmr_t underflow_iilb_vc0_credit_out : 1; + mmr_t underflow_md_vc2_credit_out : 1; + mmr_t underflow_md_vc0_credit_out : 1; + mmr_t underflow_pi_vc2_credit_out : 1; + mmr_t underflow_pi_vc0_credit_out : 1; + mmr_t overflow_ni1_vc2_credit_out : 1; + mmr_t overflow_ni1_vc0_credit_out : 1; + mmr_t overflow_ni0_vc2_credit_out : 1; + mmr_t overflow_ni0_vc0_credit_out : 1; + mmr_t overflow_iilb_vc2_credit_out : 1; + mmr_t overflow_iilb_vc0_credit_out : 1; + mmr_t overflow_md_vc2_credit_out : 1; + mmr_t overflow_md_vc0_credit_out : 1; + mmr_t overflow_pi_vc2_credit_out : 1; + mmr_t overflow_pi_vc0_credit_out : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_md_debit2 : 1; + mmr_t overflow_md_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_pi_debit2 : 1; + mmr_t overflow_pi_debit0 : 1; + mmr_t underflow_ni1_vc2_credit_in : 1; + mmr_t underflow_ni0_vc2_credit_in : 1; + mmr_t underflow_md_vc2_credit_in : 1; + mmr_t underflow_iilb_vc2_credit_in : 1; + mmr_t underflow_pi_vc2_credit_in : 1; + mmr_t underflow_ni1_vc0_credit_in : 1; + mmr_t underflow_ni0_vc0_credit_in : 1; + mmr_t underflow_md_vc0_credit_in : 1; + mmr_t underflow_iilb_vc0_credit_in : 1; + mmr_t underflow_pi_vc0_credit_in : 1; + mmr_t overflow_ni1_vc2_credit_in : 1; + mmr_t overflow_ni0_vc2_credit_in : 1; + mmr_t overflow_md_vc2_credit_in : 1; + mmr_t overflow_iilb_vc2_credit_in : 1; + mmr_t overflow_pi_vc2_credit_in : 1; + mmr_t overflow_ni1_vc0_credit_in : 1; + mmr_t overflow_ni0_vc0_credit_in : 1; + mmr_t overflow_md_vc0_credit_in : 1; + mmr_t overflow_iilb_vc0_credit_in : 1; + mmr_t overflow_pi_vc0_credit_in : 1; + mmr_t underflow_lb_vc2 : 1; + mmr_t underflow_lb_vc0 : 1; + mmr_t overflow_lb_vc2 : 1; + mmr_t overflow_lb_vc0 : 1; + mmr_t underflow_ii_vc2 : 1; + mmr_t underflow_ii_vc0 : 1; + mmr_t overflow_ii_vc2 : 1; + mmr_t overflow_ii_vc0 : 1; + mmr_t overflow_lb_debit2 : 1; + mmr_t overflow_lb_debit0 : 1; + mmr_t overflow_ii_debit2 : 1; + mmr_t overflow_ii_debit0 : 1; + } sh_xniilb_error_mask_s; +} sh_xniilb_error_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNIILB_FIRST_ERROR" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xniilb_first_error_u { + mmr_t sh_xniilb_first_error_regval; + struct { + mmr_t overflow_ii_debit0 : 1; + mmr_t overflow_ii_debit2 : 1; + mmr_t overflow_lb_debit0 : 1; + mmr_t overflow_lb_debit2 : 1; + mmr_t overflow_ii_vc0 : 1; + mmr_t overflow_ii_vc2 : 1; + mmr_t underflow_ii_vc0 : 1; + mmr_t underflow_ii_vc2 : 1; + mmr_t overflow_lb_vc0 : 1; + mmr_t overflow_lb_vc2 : 1; + mmr_t underflow_lb_vc0 : 1; + mmr_t underflow_lb_vc2 : 1; + mmr_t overflow_pi_vc0_credit_in : 1; + mmr_t overflow_iilb_vc0_credit_in : 1; + mmr_t overflow_md_vc0_credit_in : 1; + mmr_t overflow_ni0_vc0_credit_in : 1; + mmr_t overflow_ni1_vc0_credit_in : 1; + mmr_t overflow_pi_vc2_credit_in : 1; + mmr_t overflow_iilb_vc2_credit_in : 1; + mmr_t overflow_md_vc2_credit_in : 1; + mmr_t overflow_ni0_vc2_credit_in : 1; + mmr_t overflow_ni1_vc2_credit_in : 1; + mmr_t underflow_pi_vc0_credit_in : 1; + mmr_t underflow_iilb_vc0_credit_in : 1; + mmr_t underflow_md_vc0_credit_in : 1; + mmr_t underflow_ni0_vc0_credit_in : 1; + mmr_t underflow_ni1_vc0_credit_in : 1; + mmr_t underflow_pi_vc2_credit_in : 1; + mmr_t underflow_iilb_vc2_credit_in : 1; + mmr_t underflow_md_vc2_credit_in : 1; + mmr_t underflow_ni0_vc2_credit_in : 1; + mmr_t underflow_ni1_vc2_credit_in : 1; + mmr_t overflow_pi_debit0 : 1; + mmr_t overflow_pi_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_md_debit0 : 1; + mmr_t overflow_md_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_pi_vc0_credit_out : 1; + mmr_t overflow_pi_vc2_credit_out : 1; + mmr_t overflow_md_vc0_credit_out : 1; + mmr_t overflow_md_vc2_credit_out : 1; + mmr_t overflow_iilb_vc0_credit_out : 1; + mmr_t overflow_iilb_vc2_credit_out : 1; + mmr_t overflow_ni0_vc0_credit_out : 1; + mmr_t overflow_ni0_vc2_credit_out : 1; + mmr_t overflow_ni1_vc0_credit_out : 1; + mmr_t overflow_ni1_vc2_credit_out : 1; + mmr_t underflow_pi_vc0_credit_out : 1; + mmr_t underflow_pi_vc2_credit_out : 1; + mmr_t underflow_md_vc0_credit_out : 1; + mmr_t underflow_md_vc2_credit_out : 1; + mmr_t underflow_iilb_vc0_credit_out : 1; + mmr_t underflow_iilb_vc2_credit_out : 1; + mmr_t underflow_ni0_vc0_credit_out : 1; + mmr_t underflow_ni0_vc2_credit_out : 1; + mmr_t underflow_ni1_vc0_credit_out : 1; + mmr_t underflow_ni1_vc2_credit_out : 1; + mmr_t chiplet_nomatch : 1; + mmr_t lut_read_error : 1; + } sh_xniilb_first_error_s; +} sh_xniilb_first_error_u_t; +#else +typedef union sh_xniilb_first_error_u { + mmr_t sh_xniilb_first_error_regval; + struct { + mmr_t lut_read_error : 1; + mmr_t chiplet_nomatch : 1; + mmr_t underflow_ni1_vc2_credit_out : 1; + mmr_t underflow_ni1_vc0_credit_out : 1; + mmr_t underflow_ni0_vc2_credit_out : 1; + mmr_t underflow_ni0_vc0_credit_out : 1; + mmr_t underflow_iilb_vc2_credit_out : 1; + mmr_t underflow_iilb_vc0_credit_out : 1; + mmr_t underflow_md_vc2_credit_out : 1; + mmr_t underflow_md_vc0_credit_out : 1; + mmr_t underflow_pi_vc2_credit_out : 1; + mmr_t underflow_pi_vc0_credit_out : 1; + mmr_t overflow_ni1_vc2_credit_out : 1; + mmr_t overflow_ni1_vc0_credit_out : 1; + mmr_t overflow_ni0_vc2_credit_out : 1; + mmr_t overflow_ni0_vc0_credit_out : 1; + mmr_t overflow_iilb_vc2_credit_out : 1; + mmr_t overflow_iilb_vc0_credit_out : 1; + mmr_t overflow_md_vc2_credit_out : 1; + mmr_t overflow_md_vc0_credit_out : 1; + mmr_t overflow_pi_vc2_credit_out : 1; + mmr_t overflow_pi_vc0_credit_out : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_md_debit2 : 1; + mmr_t overflow_md_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_pi_debit2 : 1; + mmr_t overflow_pi_debit0 : 1; + mmr_t underflow_ni1_vc2_credit_in : 1; + mmr_t underflow_ni0_vc2_credit_in : 1; + mmr_t underflow_md_vc2_credit_in : 1; + mmr_t underflow_iilb_vc2_credit_in : 1; + mmr_t underflow_pi_vc2_credit_in : 1; + mmr_t underflow_ni1_vc0_credit_in : 1; + mmr_t underflow_ni0_vc0_credit_in : 1; + mmr_t underflow_md_vc0_credit_in : 1; + mmr_t underflow_iilb_vc0_credit_in : 1; + mmr_t underflow_pi_vc0_credit_in : 1; + mmr_t overflow_ni1_vc2_credit_in : 1; + mmr_t overflow_ni0_vc2_credit_in : 1; + mmr_t overflow_md_vc2_credit_in : 1; + mmr_t overflow_iilb_vc2_credit_in : 1; + mmr_t overflow_pi_vc2_credit_in : 1; + mmr_t overflow_ni1_vc0_credit_in : 1; + mmr_t overflow_ni0_vc0_credit_in : 1; + mmr_t overflow_md_vc0_credit_in : 1; + mmr_t overflow_iilb_vc0_credit_in : 1; + mmr_t overflow_pi_vc0_credit_in : 1; + mmr_t underflow_lb_vc2 : 1; + mmr_t underflow_lb_vc0 : 1; + mmr_t overflow_lb_vc2 : 1; + mmr_t overflow_lb_vc0 : 1; + mmr_t underflow_ii_vc2 : 1; + mmr_t underflow_ii_vc0 : 1; + mmr_t overflow_ii_vc2 : 1; + mmr_t overflow_ii_vc0 : 1; + mmr_t overflow_lb_debit2 : 1; + mmr_t overflow_lb_debit0 : 1; + mmr_t overflow_ii_debit2 : 1; + mmr_t overflow_ii_debit0 : 1; + } sh_xniilb_first_error_s; +} sh_xniilb_first_error_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_ERROR_SUMMARY" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_error_summary_u { + mmr_t sh_xnpi_error_summary_regval; + struct { + mmr_t underflow_ni0_vc0 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t lut_read_error : 1; + mmr_t single_bit_error0 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error3 : 1; + mmr_t uncor_error0 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error3 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t reserved_0 : 14; + } sh_xnpi_error_summary_s; +} sh_xnpi_error_summary_u_t; +#else +typedef union sh_xnpi_error_summary_u { + mmr_t sh_xnpi_error_summary_regval; + struct { + mmr_t reserved_0 : 14; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t uncor_error3 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error0 : 1; + mmr_t single_bit_error3 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error0 : 1; + mmr_t lut_read_error : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc0 : 1; + } sh_xnpi_error_summary_s; +} sh_xnpi_error_summary_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_ERROR_OVERFLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_error_overflow_u { + mmr_t sh_xnpi_error_overflow_regval; + struct { + mmr_t underflow_ni0_vc0 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t lut_read_error : 1; + mmr_t single_bit_error0 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error3 : 1; + mmr_t uncor_error0 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error3 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t reserved_0 : 14; + } sh_xnpi_error_overflow_s; +} sh_xnpi_error_overflow_u_t; +#else +typedef union sh_xnpi_error_overflow_u { + mmr_t sh_xnpi_error_overflow_regval; + struct { + mmr_t reserved_0 : 14; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t uncor_error3 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error0 : 1; + mmr_t single_bit_error3 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error0 : 1; + mmr_t lut_read_error : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc0 : 1; + } sh_xnpi_error_overflow_s; +} sh_xnpi_error_overflow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_ERROR_MASK" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_error_mask_u { + mmr_t sh_xnpi_error_mask_regval; + struct { + mmr_t underflow_ni0_vc0 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t lut_read_error : 1; + mmr_t single_bit_error0 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error3 : 1; + mmr_t uncor_error0 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error3 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t reserved_0 : 14; + } sh_xnpi_error_mask_s; +} sh_xnpi_error_mask_u_t; +#else +typedef union sh_xnpi_error_mask_u { + mmr_t sh_xnpi_error_mask_regval; + struct { + mmr_t reserved_0 : 14; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t uncor_error3 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error0 : 1; + mmr_t single_bit_error3 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error0 : 1; + mmr_t lut_read_error : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc0 : 1; + } sh_xnpi_error_mask_s; +} sh_xnpi_error_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNPI_FIRST_ERROR" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnpi_first_error_u { + mmr_t sh_xnpi_first_error_regval; + struct { + mmr_t underflow_ni0_vc0 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t lut_read_error : 1; + mmr_t single_bit_error0 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error3 : 1; + mmr_t uncor_error0 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error3 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t reserved_0 : 14; + } sh_xnpi_first_error_s; +} sh_xnpi_first_error_u_t; +#else +typedef union sh_xnpi_first_error_u { + mmr_t sh_xnpi_first_error_regval; + struct { + mmr_t reserved_0 : 14; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t uncor_error3 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error0 : 1; + mmr_t single_bit_error3 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error0 : 1; + mmr_t lut_read_error : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc0 : 1; + } sh_xnpi_first_error_s; +} sh_xnpi_first_error_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_ERROR_SUMMARY" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_error_summary_u { + mmr_t sh_xnmd_error_summary_regval; + struct { + mmr_t underflow_ni0_vc0 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t lut_read_error : 1; + mmr_t single_bit_error0 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error3 : 1; + mmr_t uncor_error0 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error3 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t reserved_0 : 14; + } sh_xnmd_error_summary_s; +} sh_xnmd_error_summary_u_t; +#else +typedef union sh_xnmd_error_summary_u { + mmr_t sh_xnmd_error_summary_regval; + struct { + mmr_t reserved_0 : 14; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t uncor_error3 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error0 : 1; + mmr_t single_bit_error3 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error0 : 1; + mmr_t lut_read_error : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc0 : 1; + } sh_xnmd_error_summary_s; +} sh_xnmd_error_summary_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_ERROR_OVERFLOW" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_error_overflow_u { + mmr_t sh_xnmd_error_overflow_regval; + struct { + mmr_t underflow_ni0_vc0 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t lut_read_error : 1; + mmr_t single_bit_error0 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error3 : 1; + mmr_t uncor_error0 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error3 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t reserved_0 : 14; + } sh_xnmd_error_overflow_s; +} sh_xnmd_error_overflow_u_t; +#else +typedef union sh_xnmd_error_overflow_u { + mmr_t sh_xnmd_error_overflow_regval; + struct { + mmr_t reserved_0 : 14; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t uncor_error3 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error0 : 1; + mmr_t single_bit_error3 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error0 : 1; + mmr_t lut_read_error : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc0 : 1; + } sh_xnmd_error_overflow_s; +} sh_xnmd_error_overflow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_ERROR_MASK" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_error_mask_u { + mmr_t sh_xnmd_error_mask_regval; + struct { + mmr_t underflow_ni0_vc0 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t lut_read_error : 1; + mmr_t single_bit_error0 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error3 : 1; + mmr_t uncor_error0 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error3 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t reserved_0 : 14; + } sh_xnmd_error_mask_s; +} sh_xnmd_error_mask_u_t; +#else +typedef union sh_xnmd_error_mask_u { + mmr_t sh_xnmd_error_mask_regval; + struct { + mmr_t reserved_0 : 14; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t uncor_error3 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error0 : 1; + mmr_t single_bit_error3 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error0 : 1; + mmr_t lut_read_error : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc0 : 1; + } sh_xnmd_error_mask_s; +} sh_xnmd_error_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XNMD_FIRST_ERROR" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xnmd_first_error_u { + mmr_t sh_xnmd_first_error_regval; + struct { + mmr_t underflow_ni0_vc0 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t lut_read_error : 1; + mmr_t single_bit_error0 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error3 : 1; + mmr_t uncor_error0 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error3 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t reserved_0 : 14; + } sh_xnmd_first_error_s; +} sh_xnmd_first_error_u_t; +#else +typedef union sh_xnmd_first_error_u { + mmr_t sh_xnmd_first_error_regval; + struct { + mmr_t reserved_0 : 14; + mmr_t overflow_header_cancel_fifo : 1; + mmr_t overflow_iilb_vc2_credit : 1; + mmr_t underflow_iilb_vc2_credit : 1; + mmr_t overflow_iilb_vc0_credit : 1; + mmr_t underflow_iilb_vc0_credit : 1; + mmr_t overflow_ni1_vc2_credit : 1; + mmr_t underflow_ni1_vc2_credit : 1; + mmr_t overflow_ni1_vc0_credit : 1; + mmr_t underflow_ni1_vc0_credit : 1; + mmr_t overflow_ni0_vc2_credit : 1; + mmr_t underflow_ni0_vc2_credit : 1; + mmr_t overflow_ni0_vc0_credit : 1; + mmr_t underflow_ni0_vc0_credit : 1; + mmr_t overflow_iilb_debit2 : 1; + mmr_t overflow_iilb_debit0 : 1; + mmr_t overflow_ni1_debit2 : 1; + mmr_t overflow_ni1_debit0 : 1; + mmr_t overflow_ni0_debit2 : 1; + mmr_t overflow_ni0_debit0 : 1; + mmr_t overflow_sic_cntr2 : 1; + mmr_t underflow_sic_cntr2 : 1; + mmr_t overflow_sic_cntr0 : 1; + mmr_t underflow_sic_cntr0 : 1; + mmr_t uncor_error3 : 1; + mmr_t uncor_error2 : 1; + mmr_t uncor_error1 : 1; + mmr_t uncor_error0 : 1; + mmr_t single_bit_error3 : 1; + mmr_t single_bit_error2 : 1; + mmr_t single_bit_error1 : 1; + mmr_t single_bit_error0 : 1; + mmr_t lut_read_error : 1; + mmr_t overflow_databuff_vc2 : 1; + mmr_t overflow_databuff_vc0 : 1; + mmr_t overflow_vc2_credit : 1; + mmr_t underflow_vc2_credit : 1; + mmr_t overflow_vc0_credit : 1; + mmr_t underflow_vc0_credit : 1; + mmr_t overflow_iilb_vc2 : 1; + mmr_t underflow_iilb_vc2 : 1; + mmr_t overflow_iilb_vc0 : 1; + mmr_t underflow_iilb_vc0 : 1; + mmr_t overflow_ni1_vc2 : 1; + mmr_t underflow_ni1_vc2 : 1; + mmr_t overflow_ni1_vc0 : 1; + mmr_t underflow_ni1_vc0 : 1; + mmr_t overflow_ni0_vc2 : 1; + mmr_t underflow_ni0_vc2 : 1; + mmr_t overflow_ni0_vc0 : 1; + mmr_t underflow_ni0_vc0 : 1; + } sh_xnmd_first_error_s; +} sh_xnmd_first_error_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_AUTO_REPLY_ENABLE0" */ +/* Automatic Maintenance Reply Enable 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_auto_reply_enable0_u { + mmr_t sh_auto_reply_enable0_regval; + struct { + mmr_t enable0 : 64; + } sh_auto_reply_enable0_s; +} sh_auto_reply_enable0_u_t; +#else +typedef union sh_auto_reply_enable0_u { + mmr_t sh_auto_reply_enable0_regval; + struct { + mmr_t enable0 : 64; + } sh_auto_reply_enable0_s; +} sh_auto_reply_enable0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_AUTO_REPLY_ENABLE1" */ +/* Automatic Maintenance Reply Enable 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_auto_reply_enable1_u { + mmr_t sh_auto_reply_enable1_regval; + struct { + mmr_t enable1 : 64; + } sh_auto_reply_enable1_s; +} sh_auto_reply_enable1_u_t; +#else +typedef union sh_auto_reply_enable1_u { + mmr_t sh_auto_reply_enable1_regval; + struct { + mmr_t enable1 : 64; + } sh_auto_reply_enable1_s; +} sh_auto_reply_enable1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_AUTO_REPLY_HEADER0" */ +/* Automatic Maintenance Reply Header 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_auto_reply_header0_u { + mmr_t sh_auto_reply_header0_regval; + struct { + mmr_t header0 : 64; + } sh_auto_reply_header0_s; +} sh_auto_reply_header0_u_t; +#else +typedef union sh_auto_reply_header0_u { + mmr_t sh_auto_reply_header0_regval; + struct { + mmr_t header0 : 64; + } sh_auto_reply_header0_s; +} sh_auto_reply_header0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_AUTO_REPLY_HEADER1" */ +/* Automatic Maintenance Reply Header 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_auto_reply_header1_u { + mmr_t sh_auto_reply_header1_regval; + struct { + mmr_t header1 : 64; + } sh_auto_reply_header1_s; +} sh_auto_reply_header1_u_t; +#else +typedef union sh_auto_reply_header1_u { + mmr_t sh_auto_reply_header1_regval; + struct { + mmr_t header1 : 64; + } sh_auto_reply_header1_s; +} sh_auto_reply_header1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_ENABLE_RP_AUTO_REPLY" */ +/* Enable Automatic Maintenance Reply From Reply Queue */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_enable_rp_auto_reply_u { + mmr_t sh_enable_rp_auto_reply_regval; + struct { + mmr_t enable : 1; + mmr_t reserved_0 : 63; + } sh_enable_rp_auto_reply_s; +} sh_enable_rp_auto_reply_u_t; +#else +typedef union sh_enable_rp_auto_reply_u { + mmr_t sh_enable_rp_auto_reply_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t enable : 1; + } sh_enable_rp_auto_reply_s; +} sh_enable_rp_auto_reply_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_ENABLE_RQ_AUTO_REPLY" */ +/* Enable Automatic Maintenance Reply From Request Queue */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_enable_rq_auto_reply_u { + mmr_t sh_enable_rq_auto_reply_regval; + struct { + mmr_t enable : 1; + mmr_t reserved_0 : 63; + } sh_enable_rq_auto_reply_s; +} sh_enable_rq_auto_reply_u_t; +#else +typedef union sh_enable_rq_auto_reply_u { + mmr_t sh_enable_rq_auto_reply_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t enable : 1; + } sh_enable_rq_auto_reply_s; +} sh_enable_rq_auto_reply_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_REDIRECT_INVAL" */ +/* Redirect invalidate to LB instead of PI */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_redirect_inval_u { + mmr_t sh_redirect_inval_regval; + struct { + mmr_t redirect : 1; + mmr_t reserved_0 : 63; + } sh_redirect_inval_s; +} sh_redirect_inval_u_t; +#else +typedef union sh_redirect_inval_u { + mmr_t sh_redirect_inval_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t redirect : 1; + } sh_redirect_inval_s; +} sh_redirect_inval_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_CNTRL" */ +/* Diagnostic Message Control Register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_cntrl_u { + mmr_t sh_diag_msg_cntrl_regval; + struct { + mmr_t msg_length : 6; + mmr_t error_inject_point : 6; + mmr_t error_inject_enable : 1; + mmr_t port : 1; + mmr_t reserved_0 : 48; + mmr_t start : 1; + mmr_t busy : 1; + } sh_diag_msg_cntrl_s; +} sh_diag_msg_cntrl_u_t; +#else +typedef union sh_diag_msg_cntrl_u { + mmr_t sh_diag_msg_cntrl_regval; + struct { + mmr_t busy : 1; + mmr_t start : 1; + mmr_t reserved_0 : 48; + mmr_t port : 1; + mmr_t error_inject_enable : 1; + mmr_t error_inject_point : 6; + mmr_t msg_length : 6; + } sh_diag_msg_cntrl_s; +} sh_diag_msg_cntrl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA0L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data0l_u { + mmr_t sh_diag_msg_data0l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data0l_s; +} sh_diag_msg_data0l_u_t; +#else +typedef union sh_diag_msg_data0l_u { + mmr_t sh_diag_msg_data0l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data0l_s; +} sh_diag_msg_data0l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA0U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data0u_u { + mmr_t sh_diag_msg_data0u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data0u_s; +} sh_diag_msg_data0u_u_t; +#else +typedef union sh_diag_msg_data0u_u { + mmr_t sh_diag_msg_data0u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data0u_s; +} sh_diag_msg_data0u_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA1L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data1l_u { + mmr_t sh_diag_msg_data1l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data1l_s; +} sh_diag_msg_data1l_u_t; +#else +typedef union sh_diag_msg_data1l_u { + mmr_t sh_diag_msg_data1l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data1l_s; +} sh_diag_msg_data1l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA1U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data1u_u { + mmr_t sh_diag_msg_data1u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data1u_s; +} sh_diag_msg_data1u_u_t; +#else +typedef union sh_diag_msg_data1u_u { + mmr_t sh_diag_msg_data1u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data1u_s; +} sh_diag_msg_data1u_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA2L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data2l_u { + mmr_t sh_diag_msg_data2l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data2l_s; +} sh_diag_msg_data2l_u_t; +#else +typedef union sh_diag_msg_data2l_u { + mmr_t sh_diag_msg_data2l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data2l_s; +} sh_diag_msg_data2l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA2U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data2u_u { + mmr_t sh_diag_msg_data2u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data2u_s; +} sh_diag_msg_data2u_u_t; +#else +typedef union sh_diag_msg_data2u_u { + mmr_t sh_diag_msg_data2u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data2u_s; +} sh_diag_msg_data2u_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA3L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data3l_u { + mmr_t sh_diag_msg_data3l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data3l_s; +} sh_diag_msg_data3l_u_t; +#else +typedef union sh_diag_msg_data3l_u { + mmr_t sh_diag_msg_data3l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data3l_s; +} sh_diag_msg_data3l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA3U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data3u_u { + mmr_t sh_diag_msg_data3u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data3u_s; +} sh_diag_msg_data3u_u_t; +#else +typedef union sh_diag_msg_data3u_u { + mmr_t sh_diag_msg_data3u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data3u_s; +} sh_diag_msg_data3u_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA4L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data4l_u { + mmr_t sh_diag_msg_data4l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data4l_s; +} sh_diag_msg_data4l_u_t; +#else +typedef union sh_diag_msg_data4l_u { + mmr_t sh_diag_msg_data4l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data4l_s; +} sh_diag_msg_data4l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA4U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data4u_u { + mmr_t sh_diag_msg_data4u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data4u_s; +} sh_diag_msg_data4u_u_t; +#else +typedef union sh_diag_msg_data4u_u { + mmr_t sh_diag_msg_data4u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data4u_s; +} sh_diag_msg_data4u_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA5L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data5l_u { + mmr_t sh_diag_msg_data5l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data5l_s; +} sh_diag_msg_data5l_u_t; +#else +typedef union sh_diag_msg_data5l_u { + mmr_t sh_diag_msg_data5l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data5l_s; +} sh_diag_msg_data5l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA5U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data5u_u { + mmr_t sh_diag_msg_data5u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data5u_s; +} sh_diag_msg_data5u_u_t; +#else +typedef union sh_diag_msg_data5u_u { + mmr_t sh_diag_msg_data5u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data5u_s; +} sh_diag_msg_data5u_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA6L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data6l_u { + mmr_t sh_diag_msg_data6l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data6l_s; +} sh_diag_msg_data6l_u_t; +#else +typedef union sh_diag_msg_data6l_u { + mmr_t sh_diag_msg_data6l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data6l_s; +} sh_diag_msg_data6l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA6U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data6u_u { + mmr_t sh_diag_msg_data6u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data6u_s; +} sh_diag_msg_data6u_u_t; +#else +typedef union sh_diag_msg_data6u_u { + mmr_t sh_diag_msg_data6u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data6u_s; +} sh_diag_msg_data6u_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA7L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data7l_u { + mmr_t sh_diag_msg_data7l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data7l_s; +} sh_diag_msg_data7l_u_t; +#else +typedef union sh_diag_msg_data7l_u { + mmr_t sh_diag_msg_data7l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data7l_s; +} sh_diag_msg_data7l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA7U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data7u_u { + mmr_t sh_diag_msg_data7u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data7u_s; +} sh_diag_msg_data7u_u_t; +#else +typedef union sh_diag_msg_data7u_u { + mmr_t sh_diag_msg_data7u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data7u_s; +} sh_diag_msg_data7u_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA8L" */ +/* Diagnostic Data, lower 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data8l_u { + mmr_t sh_diag_msg_data8l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data8l_s; +} sh_diag_msg_data8l_u_t; +#else +typedef union sh_diag_msg_data8l_u { + mmr_t sh_diag_msg_data8l_regval; + struct { + mmr_t data_lower : 64; + } sh_diag_msg_data8l_s; +} sh_diag_msg_data8l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_DATA8U" */ +/* Diagnostice Data, upper 64 bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_data8u_u { + mmr_t sh_diag_msg_data8u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data8u_s; +} sh_diag_msg_data8u_u_t; +#else +typedef union sh_diag_msg_data8u_u { + mmr_t sh_diag_msg_data8u_regval; + struct { + mmr_t data_upper : 64; + } sh_diag_msg_data8u_s; +} sh_diag_msg_data8u_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_HDR0" */ +/* Diagnostice Data, lower 64 bits of header */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_hdr0_u { + mmr_t sh_diag_msg_hdr0_regval; + struct { + mmr_t header0 : 64; + } sh_diag_msg_hdr0_s; +} sh_diag_msg_hdr0_u_t; +#else +typedef union sh_diag_msg_hdr0_u { + mmr_t sh_diag_msg_hdr0_regval; + struct { + mmr_t header0 : 64; + } sh_diag_msg_hdr0_s; +} sh_diag_msg_hdr0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIAG_MSG_HDR1" */ +/* Diagnostice Data, upper 64 bits of header */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_diag_msg_hdr1_u { + mmr_t sh_diag_msg_hdr1_regval; + struct { + mmr_t header1 : 64; + } sh_diag_msg_hdr1_s; +} sh_diag_msg_hdr1_u_t; +#else +typedef union sh_diag_msg_hdr1_u { + mmr_t sh_diag_msg_hdr1_regval; + struct { + mmr_t header1 : 64; + } sh_diag_msg_hdr1_s; +} sh_diag_msg_hdr1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DEBUG_SELECT" */ +/* SHub Debug Port Select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_debug_select_u { + mmr_t sh_debug_select_regval; + struct { + mmr_t nibble0_nibble_sel : 3; + mmr_t nibble0_chiplet_sel : 3; + mmr_t nibble1_nibble_sel : 3; + mmr_t nibble1_chiplet_sel : 3; + mmr_t nibble2_nibble_sel : 3; + mmr_t nibble2_chiplet_sel : 3; + mmr_t nibble3_nibble_sel : 3; + mmr_t nibble3_chiplet_sel : 3; + mmr_t nibble4_nibble_sel : 3; + mmr_t nibble4_chiplet_sel : 3; + mmr_t nibble5_nibble_sel : 3; + mmr_t nibble5_chiplet_sel : 3; + mmr_t nibble6_nibble_sel : 3; + mmr_t nibble6_chiplet_sel : 3; + mmr_t nibble7_nibble_sel : 3; + mmr_t nibble7_chiplet_sel : 3; + mmr_t debug_ii_sel : 3; + mmr_t sel_ii : 9; + mmr_t reserved_0 : 3; + mmr_t trigger_enable : 1; + } sh_debug_select_s; +} sh_debug_select_u_t; +#else +typedef union sh_debug_select_u { + mmr_t sh_debug_select_regval; + struct { + mmr_t trigger_enable : 1; + mmr_t reserved_0 : 3; + mmr_t sel_ii : 9; + mmr_t debug_ii_sel : 3; + mmr_t nibble7_chiplet_sel : 3; + mmr_t nibble7_nibble_sel : 3; + mmr_t nibble6_chiplet_sel : 3; + mmr_t nibble6_nibble_sel : 3; + mmr_t nibble5_chiplet_sel : 3; + mmr_t nibble5_nibble_sel : 3; + mmr_t nibble4_chiplet_sel : 3; + mmr_t nibble4_nibble_sel : 3; + mmr_t nibble3_chiplet_sel : 3; + mmr_t nibble3_nibble_sel : 3; + mmr_t nibble2_chiplet_sel : 3; + mmr_t nibble2_nibble_sel : 3; + mmr_t nibble1_chiplet_sel : 3; + mmr_t nibble1_nibble_sel : 3; + mmr_t nibble0_chiplet_sel : 3; + mmr_t nibble0_nibble_sel : 3; + } sh_debug_select_s; +} sh_debug_select_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TRIGGER_COMPARE_MASK" */ +/* SHub Trigger Compare Mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_trigger_compare_mask_u { + mmr_t sh_trigger_compare_mask_regval; + struct { + mmr_t mask : 32; + mmr_t reserved_0 : 32; + } sh_trigger_compare_mask_s; +} sh_trigger_compare_mask_u_t; +#else +typedef union sh_trigger_compare_mask_u { + mmr_t sh_trigger_compare_mask_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t mask : 32; + } sh_trigger_compare_mask_s; +} sh_trigger_compare_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TRIGGER_COMPARE_PATTERN" */ +/* SHub Trigger Compare Pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_trigger_compare_pattern_u { + mmr_t sh_trigger_compare_pattern_regval; + struct { + mmr_t data : 32; + mmr_t reserved_0 : 32; + } sh_trigger_compare_pattern_s; +} sh_trigger_compare_pattern_u_t; +#else +typedef union sh_trigger_compare_pattern_u { + mmr_t sh_trigger_compare_pattern_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t data : 32; + } sh_trigger_compare_pattern_s; +} sh_trigger_compare_pattern_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TRIGGER_SEL" */ +/* Trigger select for SHUB debug port */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_trigger_sel_u { + mmr_t sh_trigger_sel_regval; + struct { + mmr_t nibble0_input_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_15 : 1; + } sh_trigger_sel_s; +} sh_trigger_sel_u_t; +#else +typedef union sh_trigger_sel_u { + mmr_t sh_trigger_sel_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t nibble7_nibble_sel : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_input_sel : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble_sel : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_input_sel : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble_sel : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_input_sel : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble_sel : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_input_sel : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_input_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_input_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_input_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_input_sel : 3; + } sh_trigger_sel_s; +} sh_trigger_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_STOP_CLK_CONTROL" */ +/* Stop Clock Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_stop_clk_control_u { + mmr_t sh_stop_clk_control_regval; + struct { + mmr_t stimulus : 5; + mmr_t event : 1; + mmr_t polarity : 1; + mmr_t mode : 1; + mmr_t reserved_0 : 56; + } sh_stop_clk_control_s; +} sh_stop_clk_control_u_t; +#else +typedef union sh_stop_clk_control_u { + mmr_t sh_stop_clk_control_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t mode : 1; + mmr_t polarity : 1; + mmr_t event : 1; + mmr_t stimulus : 5; + } sh_stop_clk_control_s; +} sh_stop_clk_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_STOP_CLK_DELAY_PHASE" */ +/* Stop Clock Delay Phase */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_stop_clk_delay_phase_u { + mmr_t sh_stop_clk_delay_phase_regval; + struct { + mmr_t delay : 8; + mmr_t reserved_0 : 56; + } sh_stop_clk_delay_phase_s; +} sh_stop_clk_delay_phase_u_t; +#else +typedef union sh_stop_clk_delay_phase_u { + mmr_t sh_stop_clk_delay_phase_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t delay : 8; + } sh_stop_clk_delay_phase_s; +} sh_stop_clk_delay_phase_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_ARM_MASK" */ +/* Trigger sequencing facility arm mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_arm_mask_u { + mmr_t sh_tsf_arm_mask_regval; + struct { + mmr_t mask : 64; + } sh_tsf_arm_mask_s; +} sh_tsf_arm_mask_u_t; +#else +typedef union sh_tsf_arm_mask_u { + mmr_t sh_tsf_arm_mask_regval; + struct { + mmr_t mask : 64; + } sh_tsf_arm_mask_s; +} sh_tsf_arm_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_COUNTER_PRESETS" */ +/* Trigger sequencing facility counter presets */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_counter_presets_u { + mmr_t sh_tsf_counter_presets_regval; + struct { + mmr_t count_32 : 32; + mmr_t count_16 : 16; + mmr_t count_8b : 8; + mmr_t count_8a : 8; + } sh_tsf_counter_presets_s; +} sh_tsf_counter_presets_u_t; +#else +typedef union sh_tsf_counter_presets_u { + mmr_t sh_tsf_counter_presets_regval; + struct { + mmr_t count_8a : 8; + mmr_t count_8b : 8; + mmr_t count_16 : 16; + mmr_t count_32 : 32; + } sh_tsf_counter_presets_s; +} sh_tsf_counter_presets_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_DECREMENT_CTL" */ +/* Trigger sequencing facility counter decrement control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_decrement_ctl_u { + mmr_t sh_tsf_decrement_ctl_regval; + struct { + mmr_t ctl : 16; + mmr_t reserved_0 : 48; + } sh_tsf_decrement_ctl_s; +} sh_tsf_decrement_ctl_u_t; +#else +typedef union sh_tsf_decrement_ctl_u { + mmr_t sh_tsf_decrement_ctl_regval; + struct { + mmr_t reserved_0 : 48; + mmr_t ctl : 16; + } sh_tsf_decrement_ctl_s; +} sh_tsf_decrement_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_DIAG_MSG_CTL" */ +/* Trigger sequencing facility diagnostic message control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_diag_msg_ctl_u { + mmr_t sh_tsf_diag_msg_ctl_regval; + struct { + mmr_t enable : 8; + mmr_t reserved_0 : 56; + } sh_tsf_diag_msg_ctl_s; +} sh_tsf_diag_msg_ctl_u_t; +#else +typedef union sh_tsf_diag_msg_ctl_u { + mmr_t sh_tsf_diag_msg_ctl_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t enable : 8; + } sh_tsf_diag_msg_ctl_s; +} sh_tsf_diag_msg_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_DISARM_MASK" */ +/* Trigger sequencing facility disarm mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_disarm_mask_u { + mmr_t sh_tsf_disarm_mask_regval; + struct { + mmr_t mask : 64; + } sh_tsf_disarm_mask_s; +} sh_tsf_disarm_mask_u_t; +#else +typedef union sh_tsf_disarm_mask_u { + mmr_t sh_tsf_disarm_mask_regval; + struct { + mmr_t mask : 64; + } sh_tsf_disarm_mask_s; +} sh_tsf_disarm_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_ENABLE_CTL" */ +/* Trigger sequencing facility counter enable control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_enable_ctl_u { + mmr_t sh_tsf_enable_ctl_regval; + struct { + mmr_t ctl : 16; + mmr_t reserved_0 : 48; + } sh_tsf_enable_ctl_s; +} sh_tsf_enable_ctl_u_t; +#else +typedef union sh_tsf_enable_ctl_u { + mmr_t sh_tsf_enable_ctl_regval; + struct { + mmr_t reserved_0 : 48; + mmr_t ctl : 16; + } sh_tsf_enable_ctl_s; +} sh_tsf_enable_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_SOFTWARE_ARM" */ +/* Trigger sequencing facility software arm */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_software_arm_u { + mmr_t sh_tsf_software_arm_regval; + struct { + mmr_t bit0 : 1; + mmr_t bit1 : 1; + mmr_t bit2 : 1; + mmr_t bit3 : 1; + mmr_t bit4 : 1; + mmr_t bit5 : 1; + mmr_t bit6 : 1; + mmr_t bit7 : 1; + mmr_t reserved_0 : 56; + } sh_tsf_software_arm_s; +} sh_tsf_software_arm_u_t; +#else +typedef union sh_tsf_software_arm_u { + mmr_t sh_tsf_software_arm_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t bit7 : 1; + mmr_t bit6 : 1; + mmr_t bit5 : 1; + mmr_t bit4 : 1; + mmr_t bit3 : 1; + mmr_t bit2 : 1; + mmr_t bit1 : 1; + mmr_t bit0 : 1; + } sh_tsf_software_arm_s; +} sh_tsf_software_arm_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_SOFTWARE_DISARM" */ +/* Trigger sequencing facility software disarm */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_software_disarm_u { + mmr_t sh_tsf_software_disarm_regval; + struct { + mmr_t bit0 : 1; + mmr_t bit1 : 1; + mmr_t bit2 : 1; + mmr_t bit3 : 1; + mmr_t bit4 : 1; + mmr_t bit5 : 1; + mmr_t bit6 : 1; + mmr_t bit7 : 1; + mmr_t reserved_0 : 56; + } sh_tsf_software_disarm_s; +} sh_tsf_software_disarm_u_t; +#else +typedef union sh_tsf_software_disarm_u { + mmr_t sh_tsf_software_disarm_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t bit7 : 1; + mmr_t bit6 : 1; + mmr_t bit5 : 1; + mmr_t bit4 : 1; + mmr_t bit3 : 1; + mmr_t bit2 : 1; + mmr_t bit1 : 1; + mmr_t bit0 : 1; + } sh_tsf_software_disarm_s; +} sh_tsf_software_disarm_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_SOFTWARE_TRIGGERED" */ +/* Trigger sequencing facility software triggered */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_software_triggered_u { + mmr_t sh_tsf_software_triggered_regval; + struct { + mmr_t bit0 : 1; + mmr_t bit1 : 1; + mmr_t bit2 : 1; + mmr_t bit3 : 1; + mmr_t bit4 : 1; + mmr_t bit5 : 1; + mmr_t bit6 : 1; + mmr_t bit7 : 1; + mmr_t reserved_0 : 56; + } sh_tsf_software_triggered_s; +} sh_tsf_software_triggered_u_t; +#else +typedef union sh_tsf_software_triggered_u { + mmr_t sh_tsf_software_triggered_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t bit7 : 1; + mmr_t bit6 : 1; + mmr_t bit5 : 1; + mmr_t bit4 : 1; + mmr_t bit3 : 1; + mmr_t bit2 : 1; + mmr_t bit1 : 1; + mmr_t bit0 : 1; + } sh_tsf_software_triggered_s; +} sh_tsf_software_triggered_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_TRIGGER_MASK" */ +/* Trigger sequencing facility trigger mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_trigger_mask_u { + mmr_t sh_tsf_trigger_mask_regval; + struct { + mmr_t mask : 64; + } sh_tsf_trigger_mask_s; +} sh_tsf_trigger_mask_u_t; +#else +typedef union sh_tsf_trigger_mask_u { + mmr_t sh_tsf_trigger_mask_regval; + struct { + mmr_t mask : 64; + } sh_tsf_trigger_mask_s; +} sh_tsf_trigger_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_VEC_DATA" */ +/* Vector Write Request Message Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_vec_data_u { + mmr_t sh_vec_data_regval; + struct { + mmr_t data : 64; + } sh_vec_data_s; +} sh_vec_data_u_t; +#else +typedef union sh_vec_data_u { + mmr_t sh_vec_data_regval; + struct { + mmr_t data : 64; + } sh_vec_data_s; +} sh_vec_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_VEC_PARMS" */ +/* Vector Message Parameters Register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_vec_parms_u { + mmr_t sh_vec_parms_regval; + struct { + mmr_t type : 1; + mmr_t ni_port : 1; + mmr_t reserved_0 : 1; + mmr_t address : 32; + mmr_t pio_id : 11; + mmr_t reserved_1 : 16; + mmr_t start : 1; + mmr_t busy : 1; + } sh_vec_parms_s; +} sh_vec_parms_u_t; +#else +typedef union sh_vec_parms_u { + mmr_t sh_vec_parms_regval; + struct { + mmr_t busy : 1; + mmr_t start : 1; + mmr_t reserved_1 : 16; + mmr_t pio_id : 11; + mmr_t address : 32; + mmr_t reserved_0 : 1; + mmr_t ni_port : 1; + mmr_t type : 1; + } sh_vec_parms_s; +} sh_vec_parms_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_VEC_ROUTE" */ +/* Vector Request Message Route */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_vec_route_u { + mmr_t sh_vec_route_regval; + struct { + mmr_t route : 64; + } sh_vec_route_s; +} sh_vec_route_u_t; +#else +typedef union sh_vec_route_u { + mmr_t sh_vec_route_regval; + struct { + mmr_t route : 64; + } sh_vec_route_s; +} sh_vec_route_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_CPU_PERM" */ +/* CPU MMR Access Permission Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_cpu_perm_u { + mmr_t sh_cpu_perm_regval; + struct { + mmr_t access_bits : 64; + } sh_cpu_perm_s; +} sh_cpu_perm_u_t; +#else +typedef union sh_cpu_perm_u { + mmr_t sh_cpu_perm_regval; + struct { + mmr_t access_bits : 64; + } sh_cpu_perm_s; +} sh_cpu_perm_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_CPU_PERM_OVR" */ +/* CPU MMR Access Permission Override */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_cpu_perm_ovr_u { + mmr_t sh_cpu_perm_ovr_regval; + struct { + mmr_t override : 64; + } sh_cpu_perm_ovr_s; +} sh_cpu_perm_ovr_u_t; +#else +typedef union sh_cpu_perm_ovr_u { + mmr_t sh_cpu_perm_ovr_regval; + struct { + mmr_t override : 64; + } sh_cpu_perm_ovr_s; +} sh_cpu_perm_ovr_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_EXT_IO_PERM" */ +/* External IO MMR Access Permission Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ext_io_perm_u { + mmr_t sh_ext_io_perm_regval; + struct { + mmr_t access_bits : 64; + } sh_ext_io_perm_s; +} sh_ext_io_perm_u_t; +#else +typedef union sh_ext_io_perm_u { + mmr_t sh_ext_io_perm_regval; + struct { + mmr_t access_bits : 64; + } sh_ext_io_perm_s; +} sh_ext_io_perm_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_EXT_IOI_ACCESS" */ +/* External IO Interrupt Access Permission Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ext_ioi_access_u { + mmr_t sh_ext_ioi_access_regval; + struct { + mmr_t access_bits : 64; + } sh_ext_ioi_access_s; +} sh_ext_ioi_access_u_t; +#else +typedef union sh_ext_ioi_access_u { + mmr_t sh_ext_ioi_access_regval; + struct { + mmr_t access_bits : 64; + } sh_ext_ioi_access_s; +} sh_ext_ioi_access_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GC_FIL_CTRL" */ +/* SHub Global Clock Filter Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gc_fil_ctrl_u { + mmr_t sh_gc_fil_ctrl_regval; + struct { + mmr_t offset : 5; + mmr_t reserved_0 : 3; + mmr_t mask_counter : 12; + mmr_t mask_enable : 1; + mmr_t reserved_1 : 3; + mmr_t dropout_counter : 10; + mmr_t reserved_2 : 2; + mmr_t dropout_thresh : 10; + mmr_t reserved_3 : 2; + mmr_t error_counter : 10; + mmr_t reserved_4 : 6; + } sh_gc_fil_ctrl_s; +} sh_gc_fil_ctrl_u_t; +#else +typedef union sh_gc_fil_ctrl_u { + mmr_t sh_gc_fil_ctrl_regval; + struct { + mmr_t reserved_4 : 6; + mmr_t error_counter : 10; + mmr_t reserved_3 : 2; + mmr_t dropout_thresh : 10; + mmr_t reserved_2 : 2; + mmr_t dropout_counter : 10; + mmr_t reserved_1 : 3; + mmr_t mask_enable : 1; + mmr_t mask_counter : 12; + mmr_t reserved_0 : 3; + mmr_t offset : 5; + } sh_gc_fil_ctrl_s; +} sh_gc_fil_ctrl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_GC_SRC_CTRL" */ +/* SHub Global Clock Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_gc_src_ctrl_u { + mmr_t sh_gc_src_ctrl_regval; + struct { + mmr_t enable_counter : 1; + mmr_t reserved_0 : 3; + mmr_t max_count : 10; + mmr_t reserved_1 : 2; + mmr_t counter : 10; + mmr_t reserved_2 : 2; + mmr_t toggle_bit : 1; + mmr_t reserved_3 : 3; + mmr_t source_sel : 2; + mmr_t reserved_4 : 30; + } sh_gc_src_ctrl_s; +} sh_gc_src_ctrl_u_t; +#else +typedef union sh_gc_src_ctrl_u { + mmr_t sh_gc_src_ctrl_regval; + struct { + mmr_t reserved_4 : 30; + mmr_t source_sel : 2; + mmr_t reserved_3 : 3; + mmr_t toggle_bit : 1; + mmr_t reserved_2 : 2; + mmr_t counter : 10; + mmr_t reserved_1 : 2; + mmr_t max_count : 10; + mmr_t reserved_0 : 3; + mmr_t enable_counter : 1; + } sh_gc_src_ctrl_s; +} sh_gc_src_ctrl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_HARD_RESET" */ +/* SHub Hard Reset */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_hard_reset_u { + mmr_t sh_hard_reset_regval; + struct { + mmr_t hard_reset : 1; + mmr_t reserved_0 : 63; + } sh_hard_reset_s; +} sh_hard_reset_u_t; +#else +typedef union sh_hard_reset_u { + mmr_t sh_hard_reset_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t hard_reset : 1; + } sh_hard_reset_s; +} sh_hard_reset_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_IO_PERM" */ +/* II MMR Access Permission Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_io_perm_u { + mmr_t sh_io_perm_regval; + struct { + mmr_t access_bits : 64; + } sh_io_perm_s; +} sh_io_perm_u_t; +#else +typedef union sh_io_perm_u { + mmr_t sh_io_perm_regval; + struct { + mmr_t access_bits : 64; + } sh_io_perm_s; +} sh_io_perm_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_IOI_ACCESS" */ +/* II Interrupt Access Permission Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ioi_access_u { + mmr_t sh_ioi_access_regval; + struct { + mmr_t access_bits : 64; + } sh_ioi_access_s; +} sh_ioi_access_u_t; +#else +typedef union sh_ioi_access_u { + mmr_t sh_ioi_access_regval; + struct { + mmr_t access_bits : 64; + } sh_ioi_access_s; +} sh_ioi_access_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_IPI_ACCESS" */ +/* CPU interrupt Access Permission Bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ipi_access_u { + mmr_t sh_ipi_access_regval; + struct { + mmr_t access_bits : 64; + } sh_ipi_access_s; +} sh_ipi_access_u_t; +#else +typedef union sh_ipi_access_u { + mmr_t sh_ipi_access_regval; + struct { + mmr_t access_bits : 64; + } sh_ipi_access_s; +} sh_ipi_access_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_JTAG_CONFIG" */ +/* SHub JTAG configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_jtag_config_u { + mmr_t sh_jtag_config_regval; + struct { + mmr_t md_clk_sel : 2; + mmr_t ni_clk_sel : 1; + mmr_t ii_clk_sel : 2; + mmr_t wrt90_target : 14; + mmr_t wrt90_overrider : 1; + mmr_t wrt90_override : 1; + mmr_t jtag_mci_reset_delay : 4; + mmr_t jtag_mci_target : 14; + mmr_t jtag_mci_override : 1; + mmr_t fsb_config_ioq_depth : 1; + mmr_t fsb_config_sample_binit : 1; + mmr_t fsb_config_enable_bus_parking : 1; + mmr_t fsb_config_clock_ratio : 5; + mmr_t fsb_config_output_tristate : 4; + mmr_t fsb_config_enable_bist : 1; + mmr_t fsb_config_aux : 2; + mmr_t gtl_config_re : 1; + mmr_t reserved_0 : 8; + } sh_jtag_config_s; +} sh_jtag_config_u_t; +#else +typedef union sh_jtag_config_u { + mmr_t sh_jtag_config_regval; + struct { + mmr_t reserved_0 : 8; + mmr_t gtl_config_re : 1; + mmr_t fsb_config_aux : 2; + mmr_t fsb_config_enable_bist : 1; + mmr_t fsb_config_output_tristate : 4; + mmr_t fsb_config_clock_ratio : 5; + mmr_t fsb_config_enable_bus_parking : 1; + mmr_t fsb_config_sample_binit : 1; + mmr_t fsb_config_ioq_depth : 1; + mmr_t jtag_mci_override : 1; + mmr_t jtag_mci_target : 14; + mmr_t jtag_mci_reset_delay : 4; + mmr_t wrt90_override : 1; + mmr_t wrt90_overrider : 1; + mmr_t wrt90_target : 14; + mmr_t ii_clk_sel : 2; + mmr_t ni_clk_sel : 1; + mmr_t md_clk_sel : 2; + } sh_jtag_config_s; +} sh_jtag_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_SHUB_ID" */ +/* SHub ID Number */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_shub_id_u { + mmr_t sh_shub_id_regval; + struct { + mmr_t force1 : 1; + mmr_t manufacturer : 11; + mmr_t part_number : 16; + mmr_t revision : 4; + mmr_t node_id : 11; + mmr_t reserved_0 : 1; + mmr_t sharing_mode : 2; + mmr_t reserved_1 : 2; + mmr_t nodes_per_bit : 5; + mmr_t reserved_2 : 3; + mmr_t ni_port : 1; + mmr_t reserved_3 : 7; + } sh_shub_id_s; +} sh_shub_id_u_t; +#else +typedef union sh_shub_id_u { + mmr_t sh_shub_id_regval; + struct { + mmr_t reserved_3 : 7; + mmr_t ni_port : 1; + mmr_t reserved_2 : 3; + mmr_t nodes_per_bit : 5; + mmr_t reserved_1 : 2; + mmr_t sharing_mode : 2; + mmr_t reserved_0 : 1; + mmr_t node_id : 11; + mmr_t revision : 4; + mmr_t part_number : 16; + mmr_t manufacturer : 11; + mmr_t force1 : 1; + } sh_shub_id_s; +} sh_shub_id_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_SHUBS_PRESENT0" */ +/* Shubs 0 - 63 Present. Used for invalidate generation */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_shubs_present0_u { + mmr_t sh_shubs_present0_regval; + struct { + mmr_t shubs_present0 : 64; + } sh_shubs_present0_s; +} sh_shubs_present0_u_t; +#else +typedef union sh_shubs_present0_u { + mmr_t sh_shubs_present0_regval; + struct { + mmr_t shubs_present0 : 64; + } sh_shubs_present0_s; +} sh_shubs_present0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_SHUBS_PRESENT1" */ +/* Shubs 64 - 127 Present. Used for invalidate generation */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_shubs_present1_u { + mmr_t sh_shubs_present1_regval; + struct { + mmr_t shubs_present1 : 64; + } sh_shubs_present1_s; +} sh_shubs_present1_u_t; +#else +typedef union sh_shubs_present1_u { + mmr_t sh_shubs_present1_regval; + struct { + mmr_t shubs_present1 : 64; + } sh_shubs_present1_s; +} sh_shubs_present1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_SHUBS_PRESENT2" */ +/* Shubs 128 - 191 Present. Used for invalidate generation */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_shubs_present2_u { + mmr_t sh_shubs_present2_regval; + struct { + mmr_t shubs_present2 : 64; + } sh_shubs_present2_s; +} sh_shubs_present2_u_t; +#else +typedef union sh_shubs_present2_u { + mmr_t sh_shubs_present2_regval; + struct { + mmr_t shubs_present2 : 64; + } sh_shubs_present2_s; +} sh_shubs_present2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_SHUBS_PRESENT3" */ +/* Shubs 192 - 255 Present. Used for invalidate generation */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_shubs_present3_u { + mmr_t sh_shubs_present3_regval; + struct { + mmr_t shubs_present3 : 64; + } sh_shubs_present3_s; +} sh_shubs_present3_u_t; +#else +typedef union sh_shubs_present3_u { + mmr_t sh_shubs_present3_regval; + struct { + mmr_t shubs_present3 : 64; + } sh_shubs_present3_s; +} sh_shubs_present3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_SOFT_RESET" */ +/* SHub Soft Reset */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_soft_reset_u { + mmr_t sh_soft_reset_regval; + struct { + mmr_t soft_reset : 1; + mmr_t reserved_0 : 63; + } sh_soft_reset_s; +} sh_soft_reset_u_t; +#else +typedef union sh_soft_reset_u { + mmr_t sh_soft_reset_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t soft_reset : 1; + } sh_soft_reset_s; +} sh_soft_reset_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_FIRST_ERROR" */ +/* Shub Global First Error Flags */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_first_error_u { + mmr_t sh_first_error_regval; + struct { + mmr_t first_error : 19; + mmr_t reserved_0 : 45; + } sh_first_error_s; +} sh_first_error_u_t; +#else +typedef union sh_first_error_u { + mmr_t sh_first_error_regval; + struct { + mmr_t reserved_0 : 45; + mmr_t first_error : 19; + } sh_first_error_s; +} sh_first_error_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_II_HW_TIME_STAMP" */ +/* II hardware error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ii_hw_time_stamp_u { + mmr_t sh_ii_hw_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_ii_hw_time_stamp_s; +} sh_ii_hw_time_stamp_u_t; +#else +typedef union sh_ii_hw_time_stamp_u { + mmr_t sh_ii_hw_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_ii_hw_time_stamp_s; +} sh_ii_hw_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_HW_TIME_STAMP" */ +/* LB hardware error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_hw_time_stamp_u { + mmr_t sh_lb_hw_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_lb_hw_time_stamp_s; +} sh_lb_hw_time_stamp_u_t; +#else +typedef union sh_lb_hw_time_stamp_u { + mmr_t sh_lb_hw_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_lb_hw_time_stamp_s; +} sh_lb_hw_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_COR_TIME_STAMP" */ +/* MD correctable error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_cor_time_stamp_u { + mmr_t sh_md_cor_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_md_cor_time_stamp_s; +} sh_md_cor_time_stamp_u_t; +#else +typedef union sh_md_cor_time_stamp_u { + mmr_t sh_md_cor_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_md_cor_time_stamp_s; +} sh_md_cor_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_HW_TIME_STAMP" */ +/* MD hardware error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_hw_time_stamp_u { + mmr_t sh_md_hw_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_md_hw_time_stamp_s; +} sh_md_hw_time_stamp_u_t; +#else +typedef union sh_md_hw_time_stamp_u { + mmr_t sh_md_hw_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_md_hw_time_stamp_s; +} sh_md_hw_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_UNCOR_TIME_STAMP" */ +/* MD uncorrectable error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_uncor_time_stamp_u { + mmr_t sh_md_uncor_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_md_uncor_time_stamp_s; +} sh_md_uncor_time_stamp_u_t; +#else +typedef union sh_md_uncor_time_stamp_u { + mmr_t sh_md_uncor_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_md_uncor_time_stamp_s; +} sh_md_uncor_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_COR_TIME_STAMP" */ +/* PI correctable error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_cor_time_stamp_u { + mmr_t sh_pi_cor_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_pi_cor_time_stamp_s; +} sh_pi_cor_time_stamp_u_t; +#else +typedef union sh_pi_cor_time_stamp_u { + mmr_t sh_pi_cor_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_pi_cor_time_stamp_s; +} sh_pi_cor_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_HW_TIME_STAMP" */ +/* PI hardware error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_hw_time_stamp_u { + mmr_t sh_pi_hw_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_pi_hw_time_stamp_s; +} sh_pi_hw_time_stamp_u_t; +#else +typedef union sh_pi_hw_time_stamp_u { + mmr_t sh_pi_hw_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_pi_hw_time_stamp_s; +} sh_pi_hw_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_UNCOR_TIME_STAMP" */ +/* PI uncorrectable error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_uncor_time_stamp_u { + mmr_t sh_pi_uncor_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_pi_uncor_time_stamp_s; +} sh_pi_uncor_time_stamp_u_t; +#else +typedef union sh_pi_uncor_time_stamp_u { + mmr_t sh_pi_uncor_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_pi_uncor_time_stamp_s; +} sh_pi_uncor_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC0_ADV_TIME_STAMP" */ +/* Proc 0 advisory time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc0_adv_time_stamp_u { + mmr_t sh_proc0_adv_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_proc0_adv_time_stamp_s; +} sh_proc0_adv_time_stamp_u_t; +#else +typedef union sh_proc0_adv_time_stamp_u { + mmr_t sh_proc0_adv_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_proc0_adv_time_stamp_s; +} sh_proc0_adv_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC0_ERR_TIME_STAMP" */ +/* Proc 0 error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc0_err_time_stamp_u { + mmr_t sh_proc0_err_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_proc0_err_time_stamp_s; +} sh_proc0_err_time_stamp_u_t; +#else +typedef union sh_proc0_err_time_stamp_u { + mmr_t sh_proc0_err_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_proc0_err_time_stamp_s; +} sh_proc0_err_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC1_ADV_TIME_STAMP" */ +/* Proc 1 advisory time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc1_adv_time_stamp_u { + mmr_t sh_proc1_adv_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_proc1_adv_time_stamp_s; +} sh_proc1_adv_time_stamp_u_t; +#else +typedef union sh_proc1_adv_time_stamp_u { + mmr_t sh_proc1_adv_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_proc1_adv_time_stamp_s; +} sh_proc1_adv_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC1_ERR_TIME_STAMP" */ +/* Proc 1 error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc1_err_time_stamp_u { + mmr_t sh_proc1_err_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_proc1_err_time_stamp_s; +} sh_proc1_err_time_stamp_u_t; +#else +typedef union sh_proc1_err_time_stamp_u { + mmr_t sh_proc1_err_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_proc1_err_time_stamp_s; +} sh_proc1_err_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC2_ADV_TIME_STAMP" */ +/* Proc 2 advisory time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc2_adv_time_stamp_u { + mmr_t sh_proc2_adv_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_proc2_adv_time_stamp_s; +} sh_proc2_adv_time_stamp_u_t; +#else +typedef union sh_proc2_adv_time_stamp_u { + mmr_t sh_proc2_adv_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_proc2_adv_time_stamp_s; +} sh_proc2_adv_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC2_ERR_TIME_STAMP" */ +/* Proc 2 error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc2_err_time_stamp_u { + mmr_t sh_proc2_err_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_proc2_err_time_stamp_s; +} sh_proc2_err_time_stamp_u_t; +#else +typedef union sh_proc2_err_time_stamp_u { + mmr_t sh_proc2_err_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_proc2_err_time_stamp_s; +} sh_proc2_err_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC3_ADV_TIME_STAMP" */ +/* Proc 3 advisory time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc3_adv_time_stamp_u { + mmr_t sh_proc3_adv_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_proc3_adv_time_stamp_s; +} sh_proc3_adv_time_stamp_u_t; +#else +typedef union sh_proc3_adv_time_stamp_u { + mmr_t sh_proc3_adv_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_proc3_adv_time_stamp_s; +} sh_proc3_adv_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROC3_ERR_TIME_STAMP" */ +/* Proc 3 error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_proc3_err_time_stamp_u { + mmr_t sh_proc3_err_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_proc3_err_time_stamp_s; +} sh_proc3_err_time_stamp_u_t; +#else +typedef union sh_proc3_err_time_stamp_u { + mmr_t sh_proc3_err_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_proc3_err_time_stamp_s; +} sh_proc3_err_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_COR_TIME_STAMP" */ +/* XN correctable error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_cor_time_stamp_u { + mmr_t sh_xn_cor_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_xn_cor_time_stamp_s; +} sh_xn_cor_time_stamp_u_t; +#else +typedef union sh_xn_cor_time_stamp_u { + mmr_t sh_xn_cor_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_xn_cor_time_stamp_s; +} sh_xn_cor_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_HW_TIME_STAMP" */ +/* XN hardware error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_hw_time_stamp_u { + mmr_t sh_xn_hw_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_xn_hw_time_stamp_s; +} sh_xn_hw_time_stamp_u_t; +#else +typedef union sh_xn_hw_time_stamp_u { + mmr_t sh_xn_hw_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_xn_hw_time_stamp_s; +} sh_xn_hw_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_UNCOR_TIME_STAMP" */ +/* XN uncorrectable error time stamp */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_uncor_time_stamp_u { + mmr_t sh_xn_uncor_time_stamp_regval; + struct { + mmr_t time : 63; + mmr_t valid : 1; + } sh_xn_uncor_time_stamp_s; +} sh_xn_uncor_time_stamp_u_t; +#else +typedef union sh_xn_uncor_time_stamp_u { + mmr_t sh_xn_uncor_time_stamp_regval; + struct { + mmr_t valid : 1; + mmr_t time : 63; + } sh_xn_uncor_time_stamp_s; +} sh_xn_uncor_time_stamp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DEBUG_PORT" */ +/* SHub Debug Port */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_debug_port_u { + mmr_t sh_debug_port_regval; + struct { + mmr_t debug_nibble0 : 4; + mmr_t debug_nibble1 : 4; + mmr_t debug_nibble2 : 4; + mmr_t debug_nibble3 : 4; + mmr_t debug_nibble4 : 4; + mmr_t debug_nibble5 : 4; + mmr_t debug_nibble6 : 4; + mmr_t debug_nibble7 : 4; + mmr_t reserved_0 : 32; + } sh_debug_port_s; +} sh_debug_port_u_t; +#else +typedef union sh_debug_port_u { + mmr_t sh_debug_port_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t debug_nibble7 : 4; + mmr_t debug_nibble6 : 4; + mmr_t debug_nibble5 : 4; + mmr_t debug_nibble4 : 4; + mmr_t debug_nibble3 : 4; + mmr_t debug_nibble2 : 4; + mmr_t debug_nibble1 : 4; + mmr_t debug_nibble0 : 4; + } sh_debug_port_s; +} sh_debug_port_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_II_DEBUG_DATA" */ +/* II Debug Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ii_debug_data_u { + mmr_t sh_ii_debug_data_regval; + struct { + mmr_t ii_data : 32; + mmr_t reserved_0 : 32; + } sh_ii_debug_data_s; +} sh_ii_debug_data_u_t; +#else +typedef union sh_ii_debug_data_u { + mmr_t sh_ii_debug_data_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t ii_data : 32; + } sh_ii_debug_data_s; +} sh_ii_debug_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_II_WRAP_DEBUG_DATA" */ +/* SHub II Wrapper Debug Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ii_wrap_debug_data_u { + mmr_t sh_ii_wrap_debug_data_regval; + struct { + mmr_t ii_wrap_data : 32; + mmr_t reserved_0 : 32; + } sh_ii_wrap_debug_data_s; +} sh_ii_wrap_debug_data_u_t; +#else +typedef union sh_ii_wrap_debug_data_u { + mmr_t sh_ii_wrap_debug_data_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t ii_wrap_data : 32; + } sh_ii_wrap_debug_data_s; +} sh_ii_wrap_debug_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_LB_DEBUG_DATA" */ +/* SHub LB Debug Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_lb_debug_data_u { + mmr_t sh_lb_debug_data_regval; + struct { + mmr_t lb_data : 32; + mmr_t reserved_0 : 32; + } sh_lb_debug_data_s; +} sh_lb_debug_data_u_t; +#else +typedef union sh_lb_debug_data_u { + mmr_t sh_lb_debug_data_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t lb_data : 32; + } sh_lb_debug_data_s; +} sh_lb_debug_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DEBUG_DATA" */ +/* SHub MD Debug Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_debug_data_u { + mmr_t sh_md_debug_data_regval; + struct { + mmr_t md_data : 32; + mmr_t reserved_0 : 32; + } sh_md_debug_data_s; +} sh_md_debug_data_u_t; +#else +typedef union sh_md_debug_data_u { + mmr_t sh_md_debug_data_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t md_data : 32; + } sh_md_debug_data_s; +} sh_md_debug_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_DEBUG_DATA" */ +/* SHub PI Debug Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_debug_data_u { + mmr_t sh_pi_debug_data_regval; + struct { + mmr_t pi_data : 32; + mmr_t reserved_0 : 32; + } sh_pi_debug_data_s; +} sh_pi_debug_data_u_t; +#else +typedef union sh_pi_debug_data_u { + mmr_t sh_pi_debug_data_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t pi_data : 32; + } sh_pi_debug_data_s; +} sh_pi_debug_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_DEBUG_DATA" */ +/* SHub XN Debug Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_debug_data_u { + mmr_t sh_xn_debug_data_regval; + struct { + mmr_t xn_data : 32; + mmr_t reserved_0 : 32; + } sh_xn_debug_data_s; +} sh_xn_debug_data_u_t; +#else +typedef union sh_xn_debug_data_u { + mmr_t sh_xn_debug_data_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t xn_data : 32; + } sh_xn_debug_data_s; +} sh_xn_debug_data_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_ARMED_STATE" */ +/* Trigger sequencing facility arm state */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_armed_state_u { + mmr_t sh_tsf_armed_state_regval; + struct { + mmr_t state : 8; + mmr_t reserved_0 : 56; + } sh_tsf_armed_state_s; +} sh_tsf_armed_state_u_t; +#else +typedef union sh_tsf_armed_state_u { + mmr_t sh_tsf_armed_state_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t state : 8; + } sh_tsf_armed_state_s; +} sh_tsf_armed_state_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_COUNTER_VALUE" */ +/* Trigger sequencing facility counter value */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_counter_value_u { + mmr_t sh_tsf_counter_value_regval; + struct { + mmr_t count_32 : 32; + mmr_t count_16 : 16; + mmr_t count_8b : 8; + mmr_t count_8a : 8; + } sh_tsf_counter_value_s; +} sh_tsf_counter_value_u_t; +#else +typedef union sh_tsf_counter_value_u { + mmr_t sh_tsf_counter_value_regval; + struct { + mmr_t count_8a : 8; + mmr_t count_8b : 8; + mmr_t count_16 : 16; + mmr_t count_32 : 32; + } sh_tsf_counter_value_s; +} sh_tsf_counter_value_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_TSF_TRIGGERED_STATE" */ +/* Trigger sequencing facility triggered state */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_tsf_triggered_state_u { + mmr_t sh_tsf_triggered_state_regval; + struct { + mmr_t state : 8; + mmr_t reserved_0 : 56; + } sh_tsf_triggered_state_s; +} sh_tsf_triggered_state_u_t; +#else +typedef union sh_tsf_triggered_state_u { + mmr_t sh_tsf_triggered_state_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t state : 8; + } sh_tsf_triggered_state_s; +} sh_tsf_triggered_state_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_VEC_RDDATA" */ +/* Vector Reply Message Data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_vec_rddata_u { + mmr_t sh_vec_rddata_regval; + struct { + mmr_t data : 64; + } sh_vec_rddata_s; +} sh_vec_rddata_u_t; +#else +typedef union sh_vec_rddata_u { + mmr_t sh_vec_rddata_regval; + struct { + mmr_t data : 64; + } sh_vec_rddata_s; +} sh_vec_rddata_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_VEC_RETURN" */ +/* Vector Reply Message Return Route */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_vec_return_u { + mmr_t sh_vec_return_regval; + struct { + mmr_t route : 64; + } sh_vec_return_s; +} sh_vec_return_u_t; +#else +typedef union sh_vec_return_u { + mmr_t sh_vec_return_regval; + struct { + mmr_t route : 64; + } sh_vec_return_s; +} sh_vec_return_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_VEC_STATUS" */ +/* Vector Reply Message Status */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_vec_status_u { + mmr_t sh_vec_status_regval; + struct { + mmr_t type : 3; + mmr_t address : 32; + mmr_t pio_id : 11; + mmr_t source : 14; + mmr_t reserved_0 : 2; + mmr_t overrun : 1; + mmr_t status_valid : 1; + } sh_vec_status_s; +} sh_vec_status_u_t; +#else +typedef union sh_vec_status_u { + mmr_t sh_vec_status_regval; + struct { + mmr_t status_valid : 1; + mmr_t overrun : 1; + mmr_t reserved_0 : 2; + mmr_t source : 14; + mmr_t pio_id : 11; + mmr_t address : 32; + mmr_t type : 3; + } sh_vec_status_s; +} sh_vec_status_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT0_CONTROL" */ +/* Performance Counter 0 Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_count0_control_u { + mmr_t sh_performance_count0_control_regval; + struct { + mmr_t up_stimulus : 5; + mmr_t up_event : 1; + mmr_t up_polarity : 1; + mmr_t up_mode : 1; + mmr_t dn_stimulus : 5; + mmr_t dn_event : 1; + mmr_t dn_polarity : 1; + mmr_t dn_mode : 1; + mmr_t inc_enable : 1; + mmr_t dec_enable : 1; + mmr_t peak_det_enable : 1; + mmr_t reserved_0 : 45; + } sh_performance_count0_control_s; +} sh_performance_count0_control_u_t; +#else +typedef union sh_performance_count0_control_u { + mmr_t sh_performance_count0_control_regval; + struct { + mmr_t reserved_0 : 45; + mmr_t peak_det_enable : 1; + mmr_t dec_enable : 1; + mmr_t inc_enable : 1; + mmr_t dn_mode : 1; + mmr_t dn_polarity : 1; + mmr_t dn_event : 1; + mmr_t dn_stimulus : 5; + mmr_t up_mode : 1; + mmr_t up_polarity : 1; + mmr_t up_event : 1; + mmr_t up_stimulus : 5; + } sh_performance_count0_control_s; +} sh_performance_count0_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT1_CONTROL" */ +/* Performance Counter 1 Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_count1_control_u { + mmr_t sh_performance_count1_control_regval; + struct { + mmr_t up_stimulus : 5; + mmr_t up_event : 1; + mmr_t up_polarity : 1; + mmr_t up_mode : 1; + mmr_t dn_stimulus : 5; + mmr_t dn_event : 1; + mmr_t dn_polarity : 1; + mmr_t dn_mode : 1; + mmr_t inc_enable : 1; + mmr_t dec_enable : 1; + mmr_t peak_det_enable : 1; + mmr_t reserved_0 : 45; + } sh_performance_count1_control_s; +} sh_performance_count1_control_u_t; +#else +typedef union sh_performance_count1_control_u { + mmr_t sh_performance_count1_control_regval; + struct { + mmr_t reserved_0 : 45; + mmr_t peak_det_enable : 1; + mmr_t dec_enable : 1; + mmr_t inc_enable : 1; + mmr_t dn_mode : 1; + mmr_t dn_polarity : 1; + mmr_t dn_event : 1; + mmr_t dn_stimulus : 5; + mmr_t up_mode : 1; + mmr_t up_polarity : 1; + mmr_t up_event : 1; + mmr_t up_stimulus : 5; + } sh_performance_count1_control_s; +} sh_performance_count1_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT2_CONTROL" */ +/* Performance Counter 2 Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_count2_control_u { + mmr_t sh_performance_count2_control_regval; + struct { + mmr_t up_stimulus : 5; + mmr_t up_event : 1; + mmr_t up_polarity : 1; + mmr_t up_mode : 1; + mmr_t dn_stimulus : 5; + mmr_t dn_event : 1; + mmr_t dn_polarity : 1; + mmr_t dn_mode : 1; + mmr_t inc_enable : 1; + mmr_t dec_enable : 1; + mmr_t peak_det_enable : 1; + mmr_t reserved_0 : 45; + } sh_performance_count2_control_s; +} sh_performance_count2_control_u_t; +#else +typedef union sh_performance_count2_control_u { + mmr_t sh_performance_count2_control_regval; + struct { + mmr_t reserved_0 : 45; + mmr_t peak_det_enable : 1; + mmr_t dec_enable : 1; + mmr_t inc_enable : 1; + mmr_t dn_mode : 1; + mmr_t dn_polarity : 1; + mmr_t dn_event : 1; + mmr_t dn_stimulus : 5; + mmr_t up_mode : 1; + mmr_t up_polarity : 1; + mmr_t up_event : 1; + mmr_t up_stimulus : 5; + } sh_performance_count2_control_s; +} sh_performance_count2_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT3_CONTROL" */ +/* Performance Counter 3 Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_count3_control_u { + mmr_t sh_performance_count3_control_regval; + struct { + mmr_t up_stimulus : 5; + mmr_t up_event : 1; + mmr_t up_polarity : 1; + mmr_t up_mode : 1; + mmr_t dn_stimulus : 5; + mmr_t dn_event : 1; + mmr_t dn_polarity : 1; + mmr_t dn_mode : 1; + mmr_t inc_enable : 1; + mmr_t dec_enable : 1; + mmr_t peak_det_enable : 1; + mmr_t reserved_0 : 45; + } sh_performance_count3_control_s; +} sh_performance_count3_control_u_t; +#else +typedef union sh_performance_count3_control_u { + mmr_t sh_performance_count3_control_regval; + struct { + mmr_t reserved_0 : 45; + mmr_t peak_det_enable : 1; + mmr_t dec_enable : 1; + mmr_t inc_enable : 1; + mmr_t dn_mode : 1; + mmr_t dn_polarity : 1; + mmr_t dn_event : 1; + mmr_t dn_stimulus : 5; + mmr_t up_mode : 1; + mmr_t up_polarity : 1; + mmr_t up_event : 1; + mmr_t up_stimulus : 5; + } sh_performance_count3_control_s; +} sh_performance_count3_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT4_CONTROL" */ +/* Performance Counter 4 Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_count4_control_u { + mmr_t sh_performance_count4_control_regval; + struct { + mmr_t up_stimulus : 5; + mmr_t up_event : 1; + mmr_t up_polarity : 1; + mmr_t up_mode : 1; + mmr_t dn_stimulus : 5; + mmr_t dn_event : 1; + mmr_t dn_polarity : 1; + mmr_t dn_mode : 1; + mmr_t inc_enable : 1; + mmr_t dec_enable : 1; + mmr_t peak_det_enable : 1; + mmr_t reserved_0 : 45; + } sh_performance_count4_control_s; +} sh_performance_count4_control_u_t; +#else +typedef union sh_performance_count4_control_u { + mmr_t sh_performance_count4_control_regval; + struct { + mmr_t reserved_0 : 45; + mmr_t peak_det_enable : 1; + mmr_t dec_enable : 1; + mmr_t inc_enable : 1; + mmr_t dn_mode : 1; + mmr_t dn_polarity : 1; + mmr_t dn_event : 1; + mmr_t dn_stimulus : 5; + mmr_t up_mode : 1; + mmr_t up_polarity : 1; + mmr_t up_event : 1; + mmr_t up_stimulus : 5; + } sh_performance_count4_control_s; +} sh_performance_count4_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT5_CONTROL" */ +/* Performance Counter 5 Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_count5_control_u { + mmr_t sh_performance_count5_control_regval; + struct { + mmr_t up_stimulus : 5; + mmr_t up_event : 1; + mmr_t up_polarity : 1; + mmr_t up_mode : 1; + mmr_t dn_stimulus : 5; + mmr_t dn_event : 1; + mmr_t dn_polarity : 1; + mmr_t dn_mode : 1; + mmr_t inc_enable : 1; + mmr_t dec_enable : 1; + mmr_t peak_det_enable : 1; + mmr_t reserved_0 : 45; + } sh_performance_count5_control_s; +} sh_performance_count5_control_u_t; +#else +typedef union sh_performance_count5_control_u { + mmr_t sh_performance_count5_control_regval; + struct { + mmr_t reserved_0 : 45; + mmr_t peak_det_enable : 1; + mmr_t dec_enable : 1; + mmr_t inc_enable : 1; + mmr_t dn_mode : 1; + mmr_t dn_polarity : 1; + mmr_t dn_event : 1; + mmr_t dn_stimulus : 5; + mmr_t up_mode : 1; + mmr_t up_polarity : 1; + mmr_t up_event : 1; + mmr_t up_stimulus : 5; + } sh_performance_count5_control_s; +} sh_performance_count5_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT6_CONTROL" */ +/* Performance Counter 6 Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_count6_control_u { + mmr_t sh_performance_count6_control_regval; + struct { + mmr_t up_stimulus : 5; + mmr_t up_event : 1; + mmr_t up_polarity : 1; + mmr_t up_mode : 1; + mmr_t dn_stimulus : 5; + mmr_t dn_event : 1; + mmr_t dn_polarity : 1; + mmr_t dn_mode : 1; + mmr_t inc_enable : 1; + mmr_t dec_enable : 1; + mmr_t peak_det_enable : 1; + mmr_t reserved_0 : 45; + } sh_performance_count6_control_s; +} sh_performance_count6_control_u_t; +#else +typedef union sh_performance_count6_control_u { + mmr_t sh_performance_count6_control_regval; + struct { + mmr_t reserved_0 : 45; + mmr_t peak_det_enable : 1; + mmr_t dec_enable : 1; + mmr_t inc_enable : 1; + mmr_t dn_mode : 1; + mmr_t dn_polarity : 1; + mmr_t dn_event : 1; + mmr_t dn_stimulus : 5; + mmr_t up_mode : 1; + mmr_t up_polarity : 1; + mmr_t up_event : 1; + mmr_t up_stimulus : 5; + } sh_performance_count6_control_s; +} sh_performance_count6_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNT7_CONTROL" */ +/* Performance Counter 7 Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_count7_control_u { + mmr_t sh_performance_count7_control_regval; + struct { + mmr_t up_stimulus : 5; + mmr_t up_event : 1; + mmr_t up_polarity : 1; + mmr_t up_mode : 1; + mmr_t dn_stimulus : 5; + mmr_t dn_event : 1; + mmr_t dn_polarity : 1; + mmr_t dn_mode : 1; + mmr_t inc_enable : 1; + mmr_t dec_enable : 1; + mmr_t peak_det_enable : 1; + mmr_t reserved_0 : 45; + } sh_performance_count7_control_s; +} sh_performance_count7_control_u_t; +#else +typedef union sh_performance_count7_control_u { + mmr_t sh_performance_count7_control_regval; + struct { + mmr_t reserved_0 : 45; + mmr_t peak_det_enable : 1; + mmr_t dec_enable : 1; + mmr_t inc_enable : 1; + mmr_t dn_mode : 1; + mmr_t dn_polarity : 1; + mmr_t dn_event : 1; + mmr_t dn_stimulus : 5; + mmr_t up_mode : 1; + mmr_t up_polarity : 1; + mmr_t up_event : 1; + mmr_t up_stimulus : 5; + } sh_performance_count7_control_s; +} sh_performance_count7_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROFILE_DN_CONTROL" */ +/* Profile Counter Down Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_profile_dn_control_u { + mmr_t sh_profile_dn_control_regval; + struct { + mmr_t stimulus : 5; + mmr_t event : 1; + mmr_t polarity : 1; + mmr_t mode : 1; + mmr_t reserved_0 : 56; + } sh_profile_dn_control_s; +} sh_profile_dn_control_u_t; +#else +typedef union sh_profile_dn_control_u { + mmr_t sh_profile_dn_control_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t mode : 1; + mmr_t polarity : 1; + mmr_t event : 1; + mmr_t stimulus : 5; + } sh_profile_dn_control_s; +} sh_profile_dn_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROFILE_PEAK_CONTROL" */ +/* Profile Counter Peak Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_profile_peak_control_u { + mmr_t sh_profile_peak_control_regval; + struct { + mmr_t reserved_0 : 3; + mmr_t stimulus : 1; + mmr_t reserved_1 : 1; + mmr_t event : 1; + mmr_t polarity : 1; + mmr_t reserved_2 : 57; + } sh_profile_peak_control_s; +} sh_profile_peak_control_u_t; +#else +typedef union sh_profile_peak_control_u { + mmr_t sh_profile_peak_control_regval; + struct { + mmr_t reserved_2 : 57; + mmr_t polarity : 1; + mmr_t event : 1; + mmr_t reserved_1 : 1; + mmr_t stimulus : 1; + mmr_t reserved_0 : 3; + } sh_profile_peak_control_s; +} sh_profile_peak_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROFILE_RANGE" */ +/* Profile Counter Range */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_profile_range_u { + mmr_t sh_profile_range_regval; + struct { + mmr_t range0 : 8; + mmr_t range1 : 8; + mmr_t range2 : 8; + mmr_t range3 : 8; + mmr_t range4 : 8; + mmr_t range5 : 8; + mmr_t range6 : 8; + mmr_t range7 : 8; + } sh_profile_range_s; +} sh_profile_range_u_t; +#else +typedef union sh_profile_range_u { + mmr_t sh_profile_range_regval; + struct { + mmr_t range7 : 8; + mmr_t range6 : 8; + mmr_t range5 : 8; + mmr_t range4 : 8; + mmr_t range3 : 8; + mmr_t range2 : 8; + mmr_t range1 : 8; + mmr_t range0 : 8; + } sh_profile_range_s; +} sh_profile_range_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROFILE_UP_CONTROL" */ +/* Profile Counter Up Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_profile_up_control_u { + mmr_t sh_profile_up_control_regval; + struct { + mmr_t stimulus : 5; + mmr_t event : 1; + mmr_t polarity : 1; + mmr_t mode : 1; + mmr_t reserved_0 : 56; + } sh_profile_up_control_s; +} sh_profile_up_control_u_t; +#else +typedef union sh_profile_up_control_u { + mmr_t sh_profile_up_control_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t mode : 1; + mmr_t polarity : 1; + mmr_t event : 1; + mmr_t stimulus : 5; + } sh_profile_up_control_s; +} sh_profile_up_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER0" */ +/* Performance Counter 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_counter0_u { + mmr_t sh_performance_counter0_regval; + struct { + mmr_t count : 32; + mmr_t reserved_0 : 32; + } sh_performance_counter0_s; +} sh_performance_counter0_u_t; +#else +typedef union sh_performance_counter0_u { + mmr_t sh_performance_counter0_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t count : 32; + } sh_performance_counter0_s; +} sh_performance_counter0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER1" */ +/* Performance Counter 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_counter1_u { + mmr_t sh_performance_counter1_regval; + struct { + mmr_t count : 32; + mmr_t reserved_0 : 32; + } sh_performance_counter1_s; +} sh_performance_counter1_u_t; +#else +typedef union sh_performance_counter1_u { + mmr_t sh_performance_counter1_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t count : 32; + } sh_performance_counter1_s; +} sh_performance_counter1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER2" */ +/* Performance Counter 2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_counter2_u { + mmr_t sh_performance_counter2_regval; + struct { + mmr_t count : 32; + mmr_t reserved_0 : 32; + } sh_performance_counter2_s; +} sh_performance_counter2_u_t; +#else +typedef union sh_performance_counter2_u { + mmr_t sh_performance_counter2_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t count : 32; + } sh_performance_counter2_s; +} sh_performance_counter2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER3" */ +/* Performance Counter 3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_counter3_u { + mmr_t sh_performance_counter3_regval; + struct { + mmr_t count : 32; + mmr_t reserved_0 : 32; + } sh_performance_counter3_s; +} sh_performance_counter3_u_t; +#else +typedef union sh_performance_counter3_u { + mmr_t sh_performance_counter3_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t count : 32; + } sh_performance_counter3_s; +} sh_performance_counter3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER4" */ +/* Performance Counter 4 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_counter4_u { + mmr_t sh_performance_counter4_regval; + struct { + mmr_t count : 32; + mmr_t reserved_0 : 32; + } sh_performance_counter4_s; +} sh_performance_counter4_u_t; +#else +typedef union sh_performance_counter4_u { + mmr_t sh_performance_counter4_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t count : 32; + } sh_performance_counter4_s; +} sh_performance_counter4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER5" */ +/* Performance Counter 5 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_counter5_u { + mmr_t sh_performance_counter5_regval; + struct { + mmr_t count : 32; + mmr_t reserved_0 : 32; + } sh_performance_counter5_s; +} sh_performance_counter5_u_t; +#else +typedef union sh_performance_counter5_u { + mmr_t sh_performance_counter5_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t count : 32; + } sh_performance_counter5_s; +} sh_performance_counter5_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER6" */ +/* Performance Counter 6 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_counter6_u { + mmr_t sh_performance_counter6_regval; + struct { + mmr_t count : 32; + mmr_t reserved_0 : 32; + } sh_performance_counter6_s; +} sh_performance_counter6_u_t; +#else +typedef union sh_performance_counter6_u { + mmr_t sh_performance_counter6_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t count : 32; + } sh_performance_counter6_s; +} sh_performance_counter6_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PERFORMANCE_COUNTER7" */ +/* Performance Counter 7 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_performance_counter7_u { + mmr_t sh_performance_counter7_regval; + struct { + mmr_t count : 32; + mmr_t reserved_0 : 32; + } sh_performance_counter7_s; +} sh_performance_counter7_u_t; +#else +typedef union sh_performance_counter7_u { + mmr_t sh_performance_counter7_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t count : 32; + } sh_performance_counter7_s; +} sh_performance_counter7_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROFILE_COUNTER" */ +/* Profile Counter */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_profile_counter_u { + mmr_t sh_profile_counter_regval; + struct { + mmr_t counter : 8; + mmr_t reserved_0 : 56; + } sh_profile_counter_s; +} sh_profile_counter_u_t; +#else +typedef union sh_profile_counter_u { + mmr_t sh_profile_counter_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t counter : 8; + } sh_profile_counter_s; +} sh_profile_counter_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PROFILE_PEAK" */ +/* Profile Peak Counter */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_profile_peak_u { + mmr_t sh_profile_peak_regval; + struct { + mmr_t counter : 8; + mmr_t reserved_0 : 56; + } sh_profile_peak_s; +} sh_profile_peak_u_t; +#else +typedef union sh_profile_peak_u { + mmr_t sh_profile_peak_regval; + struct { + mmr_t reserved_0 : 56; + mmr_t counter : 8; + } sh_profile_peak_s; +} sh_profile_peak_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PTC_0" */ +/* Puge Translation Cache Message Configuration Information */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ptc_0_u { + mmr_t sh_ptc_0_regval; + struct { + mmr_t a : 1; + mmr_t reserved_0 : 1; + mmr_t ps : 6; + mmr_t rid : 24; + mmr_t reserved_1 : 31; + mmr_t start : 1; + } sh_ptc_0_s; +} sh_ptc_0_u_t; +#else +typedef union sh_ptc_0_u { + mmr_t sh_ptc_0_regval; + struct { + mmr_t start : 1; + mmr_t reserved_1 : 31; + mmr_t rid : 24; + mmr_t ps : 6; + mmr_t reserved_0 : 1; + mmr_t a : 1; + } sh_ptc_0_s; +} sh_ptc_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PTC_1" */ +/* Puge Translation Cache Message Configuration Information */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ptc_1_u { + mmr_t sh_ptc_1_regval; + struct { + mmr_t reserved_0 : 12; + mmr_t vpn : 49; + mmr_t reserved_1 : 2; + mmr_t start : 1; + } sh_ptc_1_s; +} sh_ptc_1_u_t; +#else +typedef union sh_ptc_1_u { + mmr_t sh_ptc_1_regval; + struct { + mmr_t start : 1; + mmr_t reserved_1 : 2; + mmr_t vpn : 49; + mmr_t reserved_0 : 12; + } sh_ptc_1_s; +} sh_ptc_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PTC_PARMS" */ +/* PTC Time-out parmaeters */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_ptc_parms_u { + mmr_t sh_ptc_parms_regval; + struct { + mmr_t ptc_to_wrap : 24; + mmr_t ptc_to_val : 12; + mmr_t reserved_0 : 28; + } sh_ptc_parms_s; +} sh_ptc_parms_u_t; +#else +typedef union sh_ptc_parms_u { + mmr_t sh_ptc_parms_regval; + struct { + mmr_t reserved_0 : 28; + mmr_t ptc_to_val : 12; + mmr_t ptc_to_wrap : 24; + } sh_ptc_parms_s; +} sh_ptc_parms_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_INT_CMPA" */ +/* RTC Compare Value for Processor A */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_int_cmpa_u { + mmr_t sh_int_cmpa_regval; + struct { + mmr_t real_time_cmpa : 55; + mmr_t reserved_0 : 9; + } sh_int_cmpa_s; +} sh_int_cmpa_u_t; +#else +typedef union sh_int_cmpa_u { + mmr_t sh_int_cmpa_regval; + struct { + mmr_t reserved_0 : 9; + mmr_t real_time_cmpa : 55; + } sh_int_cmpa_s; +} sh_int_cmpa_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_INT_CMPB" */ +/* RTC Compare Value for Processor B */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_int_cmpb_u { + mmr_t sh_int_cmpb_regval; + struct { + mmr_t real_time_cmpb : 55; + mmr_t reserved_0 : 9; + } sh_int_cmpb_s; +} sh_int_cmpb_u_t; +#else +typedef union sh_int_cmpb_u { + mmr_t sh_int_cmpb_regval; + struct { + mmr_t reserved_0 : 9; + mmr_t real_time_cmpb : 55; + } sh_int_cmpb_s; +} sh_int_cmpb_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_INT_CMPC" */ +/* RTC Compare Value for Processor C */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_int_cmpc_u { + mmr_t sh_int_cmpc_regval; + struct { + mmr_t real_time_cmpc : 55; + mmr_t reserved_0 : 9; + } sh_int_cmpc_s; +} sh_int_cmpc_u_t; +#else +typedef union sh_int_cmpc_u { + mmr_t sh_int_cmpc_regval; + struct { + mmr_t reserved_0 : 9; + mmr_t real_time_cmpc : 55; + } sh_int_cmpc_s; +} sh_int_cmpc_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_INT_CMPD" */ +/* RTC Compare Value for Processor D */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_int_cmpd_u { + mmr_t sh_int_cmpd_regval; + struct { + mmr_t real_time_cmpd : 55; + mmr_t reserved_0 : 9; + } sh_int_cmpd_s; +} sh_int_cmpd_u_t; +#else +typedef union sh_int_cmpd_u { + mmr_t sh_int_cmpd_regval; + struct { + mmr_t reserved_0 : 9; + mmr_t real_time_cmpd : 55; + } sh_int_cmpd_s; +} sh_int_cmpd_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_INT_PROF" */ +/* Profile Compare Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_int_prof_u { + mmr_t sh_int_prof_regval; + struct { + mmr_t profile_compare : 32; + mmr_t reserved_0 : 32; + } sh_int_prof_s; +} sh_int_prof_u_t; +#else +typedef union sh_int_prof_u { + mmr_t sh_int_prof_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t profile_compare : 32; + } sh_int_prof_s; +} sh_int_prof_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_RTC" */ +/* Real-time Clock */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_rtc_u { + mmr_t sh_rtc_regval; + struct { + mmr_t real_time_clock : 55; + mmr_t reserved_0 : 9; + } sh_rtc_s; +} sh_rtc_u_t; +#else +typedef union sh_rtc_u { + mmr_t sh_rtc_regval; + struct { + mmr_t reserved_0 : 9; + mmr_t real_time_clock : 55; + } sh_rtc_s; +} sh_rtc_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_SCRATCH0" */ +/* Scratch Register 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_scratch0_u { + mmr_t sh_scratch0_regval; + struct { + mmr_t scratch0 : 64; + } sh_scratch0_s; +} sh_scratch0_u_t; +#else +typedef union sh_scratch0_u { + mmr_t sh_scratch0_regval; + struct { + mmr_t scratch0 : 64; + } sh_scratch0_s; +} sh_scratch0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_SCRATCH1" */ +/* Scratch Register 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_scratch1_u { + mmr_t sh_scratch1_regval; + struct { + mmr_t scratch1 : 64; + } sh_scratch1_s; +} sh_scratch1_u_t; +#else +typedef union sh_scratch1_u { + mmr_t sh_scratch1_regval; + struct { + mmr_t scratch1 : 64; + } sh_scratch1_s; +} sh_scratch1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_SCRATCH2" */ +/* Scratch Register 2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_scratch2_u { + mmr_t sh_scratch2_regval; + struct { + mmr_t scratch2 : 64; + } sh_scratch2_s; +} sh_scratch2_u_t; +#else +typedef union sh_scratch2_u { + mmr_t sh_scratch2_regval; + struct { + mmr_t scratch2 : 64; + } sh_scratch2_s; +} sh_scratch2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_SCRATCH3" */ +/* Scratch Register 3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_scratch3_u { + mmr_t sh_scratch3_regval; + struct { + mmr_t scratch3 : 1; + mmr_t reserved_0 : 63; + } sh_scratch3_s; +} sh_scratch3_u_t; +#else +typedef union sh_scratch3_u { + mmr_t sh_scratch3_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t scratch3 : 1; + } sh_scratch3_s; +} sh_scratch3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_SCRATCH4" */ +/* Scratch Register 4 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_scratch4_u { + mmr_t sh_scratch4_regval; + struct { + mmr_t scratch4 : 1; + mmr_t reserved_0 : 63; + } sh_scratch4_s; +} sh_scratch4_u_t; +#else +typedef union sh_scratch4_u { + mmr_t sh_scratch4_regval; + struct { + mmr_t reserved_0 : 63; + mmr_t scratch4 : 1; + } sh_scratch4_s; +} sh_scratch4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_CRB_MESSAGE_CONTROL" */ +/* Coherent Request Buffer Message Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_crb_message_control_u { + mmr_t sh_crb_message_control_regval; + struct { + mmr_t system_coherence_enable : 1; + mmr_t local_speculative_message_enable : 1; + mmr_t remote_speculative_message_enable : 1; + mmr_t message_color : 1; + mmr_t message_color_enable : 1; + mmr_t rrb_attribute_mismatch_fsb_enable : 1; + mmr_t wrb_attribute_mismatch_fsb_enable : 1; + mmr_t irb_attribute_mismatch_fsb_enable : 1; + mmr_t rrb_attribute_mismatch_xb_enable : 1; + mmr_t wrb_attribute_mismatch_xb_enable : 1; + mmr_t suppress_bogus_writes : 1; + mmr_t enable_ivack_consolidation : 1; + mmr_t reserved_0 : 20; + mmr_t ivack_stall_count : 16; + mmr_t ivack_throttle_control : 16; + } sh_crb_message_control_s; +} sh_crb_message_control_u_t; +#else +typedef union sh_crb_message_control_u { + mmr_t sh_crb_message_control_regval; + struct { + mmr_t ivack_throttle_control : 16; + mmr_t ivack_stall_count : 16; + mmr_t reserved_0 : 20; + mmr_t enable_ivack_consolidation : 1; + mmr_t suppress_bogus_writes : 1; + mmr_t wrb_attribute_mismatch_xb_enable : 1; + mmr_t rrb_attribute_mismatch_xb_enable : 1; + mmr_t irb_attribute_mismatch_fsb_enable : 1; + mmr_t wrb_attribute_mismatch_fsb_enable : 1; + mmr_t rrb_attribute_mismatch_fsb_enable : 1; + mmr_t message_color_enable : 1; + mmr_t message_color : 1; + mmr_t remote_speculative_message_enable : 1; + mmr_t local_speculative_message_enable : 1; + mmr_t system_coherence_enable : 1; + } sh_crb_message_control_s; +} sh_crb_message_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_CRB_NACK_LIMIT" */ +/* CRB Nack Limit */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_crb_nack_limit_u { + mmr_t sh_crb_nack_limit_regval; + struct { + mmr_t limit : 12; + mmr_t pri_freq : 4; + mmr_t reserved_0 : 47; + mmr_t enable : 1; + } sh_crb_nack_limit_s; +} sh_crb_nack_limit_u_t; +#else +typedef union sh_crb_nack_limit_u { + mmr_t sh_crb_nack_limit_regval; + struct { + mmr_t enable : 1; + mmr_t reserved_0 : 47; + mmr_t pri_freq : 4; + mmr_t limit : 12; + } sh_crb_nack_limit_s; +} sh_crb_nack_limit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_CRB_TIMEOUT_PRESCALE" */ +/* Coherent Request Buffer Timeout Prescale */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_crb_timeout_prescale_u { + mmr_t sh_crb_timeout_prescale_regval; + struct { + mmr_t scaling_factor : 32; + mmr_t reserved_0 : 32; + } sh_crb_timeout_prescale_s; +} sh_crb_timeout_prescale_u_t; +#else +typedef union sh_crb_timeout_prescale_u { + mmr_t sh_crb_timeout_prescale_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t scaling_factor : 32; + } sh_crb_timeout_prescale_s; +} sh_crb_timeout_prescale_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_CRB_TIMEOUT_SKID" */ +/* Coherent Request Buffer Timeout Skid Limit */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_crb_timeout_skid_u { + mmr_t sh_crb_timeout_skid_regval; + struct { + mmr_t skid : 6; + mmr_t reserved_0 : 57; + mmr_t reset_skid_count : 1; + } sh_crb_timeout_skid_s; +} sh_crb_timeout_skid_u_t; +#else +typedef union sh_crb_timeout_skid_u { + mmr_t sh_crb_timeout_skid_regval; + struct { + mmr_t reset_skid_count : 1; + mmr_t reserved_0 : 57; + mmr_t skid : 6; + } sh_crb_timeout_skid_s; +} sh_crb_timeout_skid_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MEMORY_WRITE_STATUS_0" */ +/* Memory Write Status for CPU 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_memory_write_status_0_u { + mmr_t sh_memory_write_status_0_regval; + struct { + mmr_t pending_write_count : 6; + mmr_t reserved_0 : 58; + } sh_memory_write_status_0_s; +} sh_memory_write_status_0_u_t; +#else +typedef union sh_memory_write_status_0_u { + mmr_t sh_memory_write_status_0_regval; + struct { + mmr_t reserved_0 : 58; + mmr_t pending_write_count : 6; + } sh_memory_write_status_0_s; +} sh_memory_write_status_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MEMORY_WRITE_STATUS_1" */ +/* Memory Write Status for CPU 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_memory_write_status_1_u { + mmr_t sh_memory_write_status_1_regval; + struct { + mmr_t pending_write_count : 6; + mmr_t reserved_0 : 58; + } sh_memory_write_status_1_s; +} sh_memory_write_status_1_u_t; +#else +typedef union sh_memory_write_status_1_u { + mmr_t sh_memory_write_status_1_regval; + struct { + mmr_t reserved_0 : 58; + mmr_t pending_write_count : 6; + } sh_memory_write_status_1_s; +} sh_memory_write_status_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PIO_WRITE_STATUS_0" */ +/* PIO Write Status for CPU 0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pio_write_status_0_u { + mmr_t sh_pio_write_status_0_regval; + struct { + mmr_t multi_write_error : 1; + mmr_t write_deadlock : 1; + mmr_t write_error : 1; + mmr_t write_error_address : 47; + mmr_t reserved_0 : 6; + mmr_t pending_write_count : 6; + mmr_t reserved_1 : 1; + mmr_t writes_ok : 1; + } sh_pio_write_status_0_s; +} sh_pio_write_status_0_u_t; +#else +typedef union sh_pio_write_status_0_u { + mmr_t sh_pio_write_status_0_regval; + struct { + mmr_t writes_ok : 1; + mmr_t reserved_1 : 1; + mmr_t pending_write_count : 6; + mmr_t reserved_0 : 6; + mmr_t write_error_address : 47; + mmr_t write_error : 1; + mmr_t write_deadlock : 1; + mmr_t multi_write_error : 1; + } sh_pio_write_status_0_s; +} sh_pio_write_status_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PIO_WRITE_STATUS_1" */ +/* PIO Write Status for CPU 1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pio_write_status_1_u { + mmr_t sh_pio_write_status_1_regval; + struct { + mmr_t multi_write_error : 1; + mmr_t write_deadlock : 1; + mmr_t write_error : 1; + mmr_t write_error_address : 47; + mmr_t reserved_0 : 6; + mmr_t pending_write_count : 6; + mmr_t reserved_1 : 1; + mmr_t writes_ok : 1; + } sh_pio_write_status_1_s; +} sh_pio_write_status_1_u_t; +#else +typedef union sh_pio_write_status_1_u { + mmr_t sh_pio_write_status_1_regval; + struct { + mmr_t writes_ok : 1; + mmr_t reserved_1 : 1; + mmr_t pending_write_count : 6; + mmr_t reserved_0 : 6; + mmr_t write_error_address : 47; + mmr_t write_error : 1; + mmr_t write_deadlock : 1; + mmr_t multi_write_error : 1; + } sh_pio_write_status_1_s; +} sh_pio_write_status_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MEMORY_WRITE_STATUS_NON_USER_0" */ +/* Memory Write Status for CPU 0. OS access only */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_memory_write_status_non_user_0_u { + mmr_t sh_memory_write_status_non_user_0_regval; + struct { + mmr_t pending_write_count : 6; + mmr_t reserved_0 : 57; + mmr_t clear : 1; + } sh_memory_write_status_non_user_0_s; +} sh_memory_write_status_non_user_0_u_t; +#else +typedef union sh_memory_write_status_non_user_0_u { + mmr_t sh_memory_write_status_non_user_0_regval; + struct { + mmr_t clear : 1; + mmr_t reserved_0 : 57; + mmr_t pending_write_count : 6; + } sh_memory_write_status_non_user_0_s; +} sh_memory_write_status_non_user_0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MEMORY_WRITE_STATUS_NON_USER_1" */ +/* Memory Write Status for CPU 1. OS access only */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_memory_write_status_non_user_1_u { + mmr_t sh_memory_write_status_non_user_1_regval; + struct { + mmr_t pending_write_count : 6; + mmr_t reserved_0 : 57; + mmr_t clear : 1; + } sh_memory_write_status_non_user_1_s; +} sh_memory_write_status_non_user_1_u_t; +#else +typedef union sh_memory_write_status_non_user_1_u { + mmr_t sh_memory_write_status_non_user_1_regval; + struct { + mmr_t clear : 1; + mmr_t reserved_0 : 57; + mmr_t pending_write_count : 6; + } sh_memory_write_status_non_user_1_s; +} sh_memory_write_status_non_user_1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MMRBIST_ERR" */ +/* Error capture for bist read errors */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_mmrbist_err_u { + mmr_t sh_mmrbist_err_regval; + struct { + mmr_t addr : 33; + mmr_t reserved_0 : 3; + mmr_t detected : 1; + mmr_t multiple_detected : 1; + mmr_t cancelled : 1; + mmr_t reserved_1 : 25; + } sh_mmrbist_err_s; +} sh_mmrbist_err_u_t; +#else +typedef union sh_mmrbist_err_u { + mmr_t sh_mmrbist_err_regval; + struct { + mmr_t reserved_1 : 25; + mmr_t cancelled : 1; + mmr_t multiple_detected : 1; + mmr_t detected : 1; + mmr_t reserved_0 : 3; + mmr_t addr : 33; + } sh_mmrbist_err_s; +} sh_mmrbist_err_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MISC_ERR_HDR_LOWER" */ +/* Header capture register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_misc_err_hdr_lower_u { + mmr_t sh_misc_err_hdr_lower_regval; + struct { + mmr_t reserved_0 : 3; + mmr_t addr : 33; + mmr_t cmd : 8; + mmr_t src : 14; + mmr_t reserved_1 : 2; + mmr_t write : 1; + mmr_t reserved_2 : 2; + mmr_t valid : 1; + } sh_misc_err_hdr_lower_s; +} sh_misc_err_hdr_lower_u_t; +#else +typedef union sh_misc_err_hdr_lower_u { + mmr_t sh_misc_err_hdr_lower_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_2 : 2; + mmr_t write : 1; + mmr_t reserved_1 : 2; + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t addr : 33; + mmr_t reserved_0 : 3; + } sh_misc_err_hdr_lower_s; +} sh_misc_err_hdr_lower_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MISC_ERR_HDR_UPPER" */ +/* Error header capture packet and protocol errors */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_misc_err_hdr_upper_u { + mmr_t sh_misc_err_hdr_upper_regval; + struct { + mmr_t dir_protocol : 1; + mmr_t illegal_cmd : 1; + mmr_t nonexist_addr : 1; + mmr_t rmw_uc : 1; + mmr_t rmw_cor : 1; + mmr_t dir_acc : 1; + mmr_t pi_pkt_size : 1; + mmr_t xn_pkt_size : 1; + mmr_t reserved_0 : 12; + mmr_t echo : 9; + mmr_t reserved_1 : 35; + } sh_misc_err_hdr_upper_s; +} sh_misc_err_hdr_upper_u_t; +#else +typedef union sh_misc_err_hdr_upper_u { + mmr_t sh_misc_err_hdr_upper_regval; + struct { + mmr_t reserved_1 : 35; + mmr_t echo : 9; + mmr_t reserved_0 : 12; + mmr_t xn_pkt_size : 1; + mmr_t pi_pkt_size : 1; + mmr_t dir_acc : 1; + mmr_t rmw_cor : 1; + mmr_t rmw_uc : 1; + mmr_t nonexist_addr : 1; + mmr_t illegal_cmd : 1; + mmr_t dir_protocol : 1; + } sh_misc_err_hdr_upper_s; +} sh_misc_err_hdr_upper_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIR_UC_ERR_HDR_LOWER" */ +/* Header capture register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_dir_uc_err_hdr_lower_u { + mmr_t sh_dir_uc_err_hdr_lower_regval; + struct { + mmr_t reserved_0 : 3; + mmr_t addr : 33; + mmr_t cmd : 8; + mmr_t src : 14; + mmr_t reserved_1 : 2; + mmr_t write : 1; + mmr_t reserved_2 : 2; + mmr_t valid : 1; + } sh_dir_uc_err_hdr_lower_s; +} sh_dir_uc_err_hdr_lower_u_t; +#else +typedef union sh_dir_uc_err_hdr_lower_u { + mmr_t sh_dir_uc_err_hdr_lower_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_2 : 2; + mmr_t write : 1; + mmr_t reserved_1 : 2; + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t addr : 33; + mmr_t reserved_0 : 3; + } sh_dir_uc_err_hdr_lower_s; +} sh_dir_uc_err_hdr_lower_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIR_UC_ERR_HDR_UPPER" */ +/* Error header capture packet and protocol errors */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_dir_uc_err_hdr_upper_u { + mmr_t sh_dir_uc_err_hdr_upper_regval; + struct { + mmr_t reserved_0 : 3; + mmr_t dir_uc : 1; + mmr_t reserved_1 : 16; + mmr_t echo : 9; + mmr_t reserved_2 : 35; + } sh_dir_uc_err_hdr_upper_s; +} sh_dir_uc_err_hdr_upper_u_t; +#else +typedef union sh_dir_uc_err_hdr_upper_u { + mmr_t sh_dir_uc_err_hdr_upper_regval; + struct { + mmr_t reserved_2 : 35; + mmr_t echo : 9; + mmr_t reserved_1 : 16; + mmr_t dir_uc : 1; + mmr_t reserved_0 : 3; + } sh_dir_uc_err_hdr_upper_s; +} sh_dir_uc_err_hdr_upper_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIR_COR_ERR_HDR_LOWER" */ +/* Header capture register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_dir_cor_err_hdr_lower_u { + mmr_t sh_dir_cor_err_hdr_lower_regval; + struct { + mmr_t reserved_0 : 3; + mmr_t addr : 33; + mmr_t cmd : 8; + mmr_t src : 14; + mmr_t reserved_1 : 2; + mmr_t write : 1; + mmr_t reserved_2 : 2; + mmr_t valid : 1; + } sh_dir_cor_err_hdr_lower_s; +} sh_dir_cor_err_hdr_lower_u_t; +#else +typedef union sh_dir_cor_err_hdr_lower_u { + mmr_t sh_dir_cor_err_hdr_lower_regval; + struct { + mmr_t valid : 1; + mmr_t reserved_2 : 2; + mmr_t write : 1; + mmr_t reserved_1 : 2; + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t addr : 33; + mmr_t reserved_0 : 3; + } sh_dir_cor_err_hdr_lower_s; +} sh_dir_cor_err_hdr_lower_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_DIR_COR_ERR_HDR_UPPER" */ +/* Error header capture packet and protocol errors */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_dir_cor_err_hdr_upper_u { + mmr_t sh_dir_cor_err_hdr_upper_regval; + struct { + mmr_t reserved_0 : 8; + mmr_t dir_cor : 1; + mmr_t reserved_1 : 11; + mmr_t echo : 9; + mmr_t reserved_2 : 35; + } sh_dir_cor_err_hdr_upper_s; +} sh_dir_cor_err_hdr_upper_u_t; +#else +typedef union sh_dir_cor_err_hdr_upper_u { + mmr_t sh_dir_cor_err_hdr_upper_regval; + struct { + mmr_t reserved_2 : 35; + mmr_t echo : 9; + mmr_t reserved_1 : 11; + mmr_t dir_cor : 1; + mmr_t reserved_0 : 8; + } sh_dir_cor_err_hdr_upper_s; +} sh_dir_cor_err_hdr_upper_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MEM_ERROR_SUMMARY" */ +/* Memory error flags */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_mem_error_summary_u { + mmr_t sh_mem_error_summary_regval; + struct { + mmr_t illegal_cmd : 1; + mmr_t nonexist_addr : 1; + mmr_t dqlp_dir_perr : 1; + mmr_t dqrp_dir_perr : 1; + mmr_t dqlp_dir_uc : 1; + mmr_t dqlp_dir_cor : 1; + mmr_t dqrp_dir_uc : 1; + mmr_t dqrp_dir_cor : 1; + mmr_t acx_int_hw : 1; + mmr_t acy_int_hw : 1; + mmr_t dir_acc : 1; + mmr_t reserved_0 : 1; + mmr_t dqlp_int_uc : 1; + mmr_t dqlp_int_cor : 1; + mmr_t dqlp_int_hw : 1; + mmr_t reserved_1 : 1; + mmr_t dqls_int_uc : 1; + mmr_t dqls_int_cor : 1; + mmr_t dqls_int_hw : 1; + mmr_t reserved_2 : 1; + mmr_t dqrp_int_uc : 1; + mmr_t dqrp_int_cor : 1; + mmr_t dqrp_int_hw : 1; + mmr_t reserved_3 : 1; + mmr_t dqrs_int_uc : 1; + mmr_t dqrs_int_cor : 1; + mmr_t dqrs_int_hw : 1; + mmr_t reserved_4 : 1; + mmr_t pi_reply_overflow : 1; + mmr_t xn_reply_overflow : 1; + mmr_t pi_request_overflow : 1; + mmr_t xn_request_overflow : 1; + mmr_t red_black_err_timeout : 1; + mmr_t pi_pkt_size : 1; + mmr_t xn_pkt_size : 1; + mmr_t reserved_5 : 29; + } sh_mem_error_summary_s; +} sh_mem_error_summary_u_t; +#else +typedef union sh_mem_error_summary_u { + mmr_t sh_mem_error_summary_regval; + struct { + mmr_t reserved_5 : 29; + mmr_t xn_pkt_size : 1; + mmr_t pi_pkt_size : 1; + mmr_t red_black_err_timeout : 1; + mmr_t xn_request_overflow : 1; + mmr_t pi_request_overflow : 1; + mmr_t xn_reply_overflow : 1; + mmr_t pi_reply_overflow : 1; + mmr_t reserved_4 : 1; + mmr_t dqrs_int_hw : 1; + mmr_t dqrs_int_cor : 1; + mmr_t dqrs_int_uc : 1; + mmr_t reserved_3 : 1; + mmr_t dqrp_int_hw : 1; + mmr_t dqrp_int_cor : 1; + mmr_t dqrp_int_uc : 1; + mmr_t reserved_2 : 1; + mmr_t dqls_int_hw : 1; + mmr_t dqls_int_cor : 1; + mmr_t dqls_int_uc : 1; + mmr_t reserved_1 : 1; + mmr_t dqlp_int_hw : 1; + mmr_t dqlp_int_cor : 1; + mmr_t dqlp_int_uc : 1; + mmr_t reserved_0 : 1; + mmr_t dir_acc : 1; + mmr_t acy_int_hw : 1; + mmr_t acx_int_hw : 1; + mmr_t dqrp_dir_cor : 1; + mmr_t dqrp_dir_uc : 1; + mmr_t dqlp_dir_cor : 1; + mmr_t dqlp_dir_uc : 1; + mmr_t dqrp_dir_perr : 1; + mmr_t dqlp_dir_perr : 1; + mmr_t nonexist_addr : 1; + mmr_t illegal_cmd : 1; + } sh_mem_error_summary_s; +} sh_mem_error_summary_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MEM_ERROR_OVERFLOW" */ +/* Memory error flags */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_mem_error_overflow_u { + mmr_t sh_mem_error_overflow_regval; + struct { + mmr_t illegal_cmd : 1; + mmr_t nonexist_addr : 1; + mmr_t dqlp_dir_perr : 1; + mmr_t dqrp_dir_perr : 1; + mmr_t dqlp_dir_uc : 1; + mmr_t dqlp_dir_cor : 1; + mmr_t dqrp_dir_uc : 1; + mmr_t dqrp_dir_cor : 1; + mmr_t acx_int_hw : 1; + mmr_t acy_int_hw : 1; + mmr_t dir_acc : 1; + mmr_t reserved_0 : 1; + mmr_t dqlp_int_uc : 1; + mmr_t dqlp_int_cor : 1; + mmr_t dqlp_int_hw : 1; + mmr_t reserved_1 : 1; + mmr_t dqls_int_uc : 1; + mmr_t dqls_int_cor : 1; + mmr_t dqls_int_hw : 1; + mmr_t reserved_2 : 1; + mmr_t dqrp_int_uc : 1; + mmr_t dqrp_int_cor : 1; + mmr_t dqrp_int_hw : 1; + mmr_t reserved_3 : 1; + mmr_t dqrs_int_uc : 1; + mmr_t dqrs_int_cor : 1; + mmr_t dqrs_int_hw : 1; + mmr_t reserved_4 : 1; + mmr_t pi_reply_overflow : 1; + mmr_t xn_reply_overflow : 1; + mmr_t pi_request_overflow : 1; + mmr_t xn_request_overflow : 1; + mmr_t red_black_err_timeout : 1; + mmr_t pi_pkt_size : 1; + mmr_t xn_pkt_size : 1; + mmr_t reserved_5 : 29; + } sh_mem_error_overflow_s; +} sh_mem_error_overflow_u_t; +#else +typedef union sh_mem_error_overflow_u { + mmr_t sh_mem_error_overflow_regval; + struct { + mmr_t reserved_5 : 29; + mmr_t xn_pkt_size : 1; + mmr_t pi_pkt_size : 1; + mmr_t red_black_err_timeout : 1; + mmr_t xn_request_overflow : 1; + mmr_t pi_request_overflow : 1; + mmr_t xn_reply_overflow : 1; + mmr_t pi_reply_overflow : 1; + mmr_t reserved_4 : 1; + mmr_t dqrs_int_hw : 1; + mmr_t dqrs_int_cor : 1; + mmr_t dqrs_int_uc : 1; + mmr_t reserved_3 : 1; + mmr_t dqrp_int_hw : 1; + mmr_t dqrp_int_cor : 1; + mmr_t dqrp_int_uc : 1; + mmr_t reserved_2 : 1; + mmr_t dqls_int_hw : 1; + mmr_t dqls_int_cor : 1; + mmr_t dqls_int_uc : 1; + mmr_t reserved_1 : 1; + mmr_t dqlp_int_hw : 1; + mmr_t dqlp_int_cor : 1; + mmr_t dqlp_int_uc : 1; + mmr_t reserved_0 : 1; + mmr_t dir_acc : 1; + mmr_t acy_int_hw : 1; + mmr_t acx_int_hw : 1; + mmr_t dqrp_dir_cor : 1; + mmr_t dqrp_dir_uc : 1; + mmr_t dqlp_dir_cor : 1; + mmr_t dqlp_dir_uc : 1; + mmr_t dqrp_dir_perr : 1; + mmr_t dqlp_dir_perr : 1; + mmr_t nonexist_addr : 1; + mmr_t illegal_cmd : 1; + } sh_mem_error_overflow_s; +} sh_mem_error_overflow_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MEM_ERROR_MASK" */ +/* Memory error flags */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_mem_error_mask_u { + mmr_t sh_mem_error_mask_regval; + struct { + mmr_t illegal_cmd : 1; + mmr_t nonexist_addr : 1; + mmr_t dqlp_dir_perr : 1; + mmr_t dqrp_dir_perr : 1; + mmr_t dqlp_dir_uc : 1; + mmr_t dqlp_dir_cor : 1; + mmr_t dqrp_dir_uc : 1; + mmr_t dqrp_dir_cor : 1; + mmr_t acx_int_hw : 1; + mmr_t acy_int_hw : 1; + mmr_t dir_acc : 1; + mmr_t reserved_0 : 1; + mmr_t dqlp_int_uc : 1; + mmr_t dqlp_int_cor : 1; + mmr_t dqlp_int_hw : 1; + mmr_t reserved_1 : 1; + mmr_t dqls_int_uc : 1; + mmr_t dqls_int_cor : 1; + mmr_t dqls_int_hw : 1; + mmr_t reserved_2 : 1; + mmr_t dqrp_int_uc : 1; + mmr_t dqrp_int_cor : 1; + mmr_t dqrp_int_hw : 1; + mmr_t reserved_3 : 1; + mmr_t dqrs_int_uc : 1; + mmr_t dqrs_int_cor : 1; + mmr_t dqrs_int_hw : 1; + mmr_t reserved_4 : 1; + mmr_t pi_reply_overflow : 1; + mmr_t xn_reply_overflow : 1; + mmr_t pi_request_overflow : 1; + mmr_t xn_request_overflow : 1; + mmr_t red_black_err_timeout : 1; + mmr_t pi_pkt_size : 1; + mmr_t xn_pkt_size : 1; + mmr_t reserved_5 : 29; + } sh_mem_error_mask_s; +} sh_mem_error_mask_u_t; +#else +typedef union sh_mem_error_mask_u { + mmr_t sh_mem_error_mask_regval; + struct { + mmr_t reserved_5 : 29; + mmr_t xn_pkt_size : 1; + mmr_t pi_pkt_size : 1; + mmr_t red_black_err_timeout : 1; + mmr_t xn_request_overflow : 1; + mmr_t pi_request_overflow : 1; + mmr_t xn_reply_overflow : 1; + mmr_t pi_reply_overflow : 1; + mmr_t reserved_4 : 1; + mmr_t dqrs_int_hw : 1; + mmr_t dqrs_int_cor : 1; + mmr_t dqrs_int_uc : 1; + mmr_t reserved_3 : 1; + mmr_t dqrp_int_hw : 1; + mmr_t dqrp_int_cor : 1; + mmr_t dqrp_int_uc : 1; + mmr_t reserved_2 : 1; + mmr_t dqls_int_hw : 1; + mmr_t dqls_int_cor : 1; + mmr_t dqls_int_uc : 1; + mmr_t reserved_1 : 1; + mmr_t dqlp_int_hw : 1; + mmr_t dqlp_int_cor : 1; + mmr_t dqlp_int_uc : 1; + mmr_t reserved_0 : 1; + mmr_t dir_acc : 1; + mmr_t acy_int_hw : 1; + mmr_t acx_int_hw : 1; + mmr_t dqrp_dir_cor : 1; + mmr_t dqrp_dir_uc : 1; + mmr_t dqlp_dir_cor : 1; + mmr_t dqlp_dir_uc : 1; + mmr_t dqrp_dir_perr : 1; + mmr_t dqlp_dir_perr : 1; + mmr_t nonexist_addr : 1; + mmr_t illegal_cmd : 1; + } sh_mem_error_mask_s; +} sh_mem_error_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_DIMM_CFG" */ +/* AC Mem Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_dimm_cfg_u { + mmr_t sh_x_dimm_cfg_regval; + struct { + mmr_t dimm0_size : 3; + mmr_t dimm0_2bk : 1; + mmr_t dimm0_rev : 1; + mmr_t dimm0_cs : 2; + mmr_t reserved_0 : 1; + mmr_t dimm1_size : 3; + mmr_t dimm1_2bk : 1; + mmr_t dimm1_rev : 1; + mmr_t dimm1_cs : 2; + mmr_t reserved_1 : 1; + mmr_t dimm2_size : 3; + mmr_t dimm2_2bk : 1; + mmr_t dimm2_rev : 1; + mmr_t dimm2_cs : 2; + mmr_t reserved_2 : 1; + mmr_t dimm3_size : 3; + mmr_t dimm3_2bk : 1; + mmr_t dimm3_rev : 1; + mmr_t dimm3_cs : 2; + mmr_t reserved_3 : 1; + mmr_t freq : 4; + mmr_t reserved_4 : 28; + } sh_x_dimm_cfg_s; +} sh_x_dimm_cfg_u_t; +#else +typedef union sh_x_dimm_cfg_u { + mmr_t sh_x_dimm_cfg_regval; + struct { + mmr_t reserved_4 : 28; + mmr_t freq : 4; + mmr_t reserved_3 : 1; + mmr_t dimm3_cs : 2; + mmr_t dimm3_rev : 1; + mmr_t dimm3_2bk : 1; + mmr_t dimm3_size : 3; + mmr_t reserved_2 : 1; + mmr_t dimm2_cs : 2; + mmr_t dimm2_rev : 1; + mmr_t dimm2_2bk : 1; + mmr_t dimm2_size : 3; + mmr_t reserved_1 : 1; + mmr_t dimm1_cs : 2; + mmr_t dimm1_rev : 1; + mmr_t dimm1_2bk : 1; + mmr_t dimm1_size : 3; + mmr_t reserved_0 : 1; + mmr_t dimm0_cs : 2; + mmr_t dimm0_rev : 1; + mmr_t dimm0_2bk : 1; + mmr_t dimm0_size : 3; + } sh_x_dimm_cfg_s; +} sh_x_dimm_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_DIMM_CFG" */ +/* AC Mem Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_dimm_cfg_u { + mmr_t sh_y_dimm_cfg_regval; + struct { + mmr_t dimm0_size : 3; + mmr_t dimm0_2bk : 1; + mmr_t dimm0_rev : 1; + mmr_t dimm0_cs : 2; + mmr_t reserved_0 : 1; + mmr_t dimm1_size : 3; + mmr_t dimm1_2bk : 1; + mmr_t dimm1_rev : 1; + mmr_t dimm1_cs : 2; + mmr_t reserved_1 : 1; + mmr_t dimm2_size : 3; + mmr_t dimm2_2bk : 1; + mmr_t dimm2_rev : 1; + mmr_t dimm2_cs : 2; + mmr_t reserved_2 : 1; + mmr_t dimm3_size : 3; + mmr_t dimm3_2bk : 1; + mmr_t dimm3_rev : 1; + mmr_t dimm3_cs : 2; + mmr_t reserved_3 : 1; + mmr_t freq : 4; + mmr_t reserved_4 : 28; + } sh_y_dimm_cfg_s; +} sh_y_dimm_cfg_u_t; +#else +typedef union sh_y_dimm_cfg_u { + mmr_t sh_y_dimm_cfg_regval; + struct { + mmr_t reserved_4 : 28; + mmr_t freq : 4; + mmr_t reserved_3 : 1; + mmr_t dimm3_cs : 2; + mmr_t dimm3_rev : 1; + mmr_t dimm3_2bk : 1; + mmr_t dimm3_size : 3; + mmr_t reserved_2 : 1; + mmr_t dimm2_cs : 2; + mmr_t dimm2_rev : 1; + mmr_t dimm2_2bk : 1; + mmr_t dimm2_size : 3; + mmr_t reserved_1 : 1; + mmr_t dimm1_cs : 2; + mmr_t dimm1_rev : 1; + mmr_t dimm1_2bk : 1; + mmr_t dimm1_size : 3; + mmr_t reserved_0 : 1; + mmr_t dimm0_cs : 2; + mmr_t dimm0_rev : 1; + mmr_t dimm0_2bk : 1; + mmr_t dimm0_size : 3; + } sh_y_dimm_cfg_s; +} sh_y_dimm_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_JNR_DIMM_CFG" */ +/* AC Mem Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_jnr_dimm_cfg_u { + mmr_t sh_jnr_dimm_cfg_regval; + struct { + mmr_t dimm0_size : 3; + mmr_t dimm0_2bk : 1; + mmr_t dimm0_rev : 1; + mmr_t dimm0_cs : 2; + mmr_t reserved_0 : 1; + mmr_t dimm1_size : 3; + mmr_t dimm1_2bk : 1; + mmr_t dimm1_rev : 1; + mmr_t dimm1_cs : 2; + mmr_t reserved_1 : 1; + mmr_t dimm2_size : 3; + mmr_t dimm2_2bk : 1; + mmr_t dimm2_rev : 1; + mmr_t dimm2_cs : 2; + mmr_t reserved_2 : 1; + mmr_t dimm3_size : 3; + mmr_t dimm3_2bk : 1; + mmr_t dimm3_rev : 1; + mmr_t dimm3_cs : 2; + mmr_t reserved_3 : 1; + mmr_t freq : 4; + mmr_t reserved_4 : 28; + } sh_jnr_dimm_cfg_s; +} sh_jnr_dimm_cfg_u_t; +#else +typedef union sh_jnr_dimm_cfg_u { + mmr_t sh_jnr_dimm_cfg_regval; + struct { + mmr_t reserved_4 : 28; + mmr_t freq : 4; + mmr_t reserved_3 : 1; + mmr_t dimm3_cs : 2; + mmr_t dimm3_rev : 1; + mmr_t dimm3_2bk : 1; + mmr_t dimm3_size : 3; + mmr_t reserved_2 : 1; + mmr_t dimm2_cs : 2; + mmr_t dimm2_rev : 1; + mmr_t dimm2_2bk : 1; + mmr_t dimm2_size : 3; + mmr_t reserved_1 : 1; + mmr_t dimm1_cs : 2; + mmr_t dimm1_rev : 1; + mmr_t dimm1_2bk : 1; + mmr_t dimm1_size : 3; + mmr_t reserved_0 : 1; + mmr_t dimm0_cs : 2; + mmr_t dimm0_rev : 1; + mmr_t dimm0_2bk : 1; + mmr_t dimm0_size : 3; + } sh_jnr_dimm_cfg_s; +} sh_jnr_dimm_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_PHASE_CFG" */ +/* AC Phase Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_phase_cfg_u { + mmr_t sh_x_phase_cfg_regval; + struct { + mmr_t ld_a : 5; + mmr_t ld_b : 5; + mmr_t dq_ld_a : 5; + mmr_t dq_ld_b : 5; + mmr_t hold : 5; + mmr_t hold_req : 5; + mmr_t add_cp : 5; + mmr_t bubble_en : 5; + mmr_t pha_bubble : 3; + mmr_t phb_bubble : 3; + mmr_t phc_bubble : 3; + mmr_t phd_bubble : 3; + mmr_t phe_bubble : 3; + mmr_t sel_a : 4; + mmr_t dq_sel_a : 4; + mmr_t reserved_0 : 1; + } sh_x_phase_cfg_s; +} sh_x_phase_cfg_u_t; +#else +typedef union sh_x_phase_cfg_u { + mmr_t sh_x_phase_cfg_regval; + struct { + mmr_t reserved_0 : 1; + mmr_t dq_sel_a : 4; + mmr_t sel_a : 4; + mmr_t phe_bubble : 3; + mmr_t phd_bubble : 3; + mmr_t phc_bubble : 3; + mmr_t phb_bubble : 3; + mmr_t pha_bubble : 3; + mmr_t bubble_en : 5; + mmr_t add_cp : 5; + mmr_t hold_req : 5; + mmr_t hold : 5; + mmr_t dq_ld_b : 5; + mmr_t dq_ld_a : 5; + mmr_t ld_b : 5; + mmr_t ld_a : 5; + } sh_x_phase_cfg_s; +} sh_x_phase_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_CFG" */ +/* AC Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_cfg_u { + mmr_t sh_x_cfg_regval; + struct { + mmr_t mode_serial : 1; + mmr_t dirc_random_replacement : 1; + mmr_t dir_counter_init : 6; + mmr_t ta_dlys : 32; + mmr_t da_bb_clr : 4; + mmr_t dc_bb_clr : 4; + mmr_t wt_bb_clr : 4; + mmr_t sso_wt_en : 1; + mmr_t trcd2_en : 1; + mmr_t trcd4_en : 1; + mmr_t req_cntr_dis : 1; + mmr_t req_cntr_val : 6; + mmr_t inv_cas_addr : 1; + mmr_t clr_dir_cache : 1; + } sh_x_cfg_s; +} sh_x_cfg_u_t; +#else +typedef union sh_x_cfg_u { + mmr_t sh_x_cfg_regval; + struct { + mmr_t clr_dir_cache : 1; + mmr_t inv_cas_addr : 1; + mmr_t req_cntr_val : 6; + mmr_t req_cntr_dis : 1; + mmr_t trcd4_en : 1; + mmr_t trcd2_en : 1; + mmr_t sso_wt_en : 1; + mmr_t wt_bb_clr : 4; + mmr_t dc_bb_clr : 4; + mmr_t da_bb_clr : 4; + mmr_t ta_dlys : 32; + mmr_t dir_counter_init : 6; + mmr_t dirc_random_replacement : 1; + mmr_t mode_serial : 1; + } sh_x_cfg_s; +} sh_x_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_DQCT_CFG" */ +/* AC Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_dqct_cfg_u { + mmr_t sh_x_dqct_cfg_regval; + struct { + mmr_t rd_sel : 4; + mmr_t wt_sel : 4; + mmr_t dta_rd_sel : 4; + mmr_t dta_wt_sel : 4; + mmr_t dir_rd_sel : 4; + mmr_t mdir_rd_sel : 4; + mmr_t reserved_0 : 40; + } sh_x_dqct_cfg_s; +} sh_x_dqct_cfg_u_t; +#else +typedef union sh_x_dqct_cfg_u { + mmr_t sh_x_dqct_cfg_regval; + struct { + mmr_t reserved_0 : 40; + mmr_t mdir_rd_sel : 4; + mmr_t dir_rd_sel : 4; + mmr_t dta_wt_sel : 4; + mmr_t dta_rd_sel : 4; + mmr_t wt_sel : 4; + mmr_t rd_sel : 4; + } sh_x_dqct_cfg_s; +} sh_x_dqct_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_REFRESH_CONTROL" */ +/* Refresh Control Register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_refresh_control_u { + mmr_t sh_x_refresh_control_regval; + struct { + mmr_t enable : 8; + mmr_t interval : 9; + mmr_t hold : 6; + mmr_t interleave : 1; + mmr_t half_rate : 4; + mmr_t reserved_0 : 36; + } sh_x_refresh_control_s; +} sh_x_refresh_control_u_t; +#else +typedef union sh_x_refresh_control_u { + mmr_t sh_x_refresh_control_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t half_rate : 4; + mmr_t interleave : 1; + mmr_t hold : 6; + mmr_t interval : 9; + mmr_t enable : 8; + } sh_x_refresh_control_s; +} sh_x_refresh_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_PHASE_CFG" */ +/* AC Phase Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_phase_cfg_u { + mmr_t sh_y_phase_cfg_regval; + struct { + mmr_t ld_a : 5; + mmr_t ld_b : 5; + mmr_t dq_ld_a : 5; + mmr_t dq_ld_b : 5; + mmr_t hold : 5; + mmr_t hold_req : 5; + mmr_t add_cp : 5; + mmr_t bubble_en : 5; + mmr_t pha_bubble : 3; + mmr_t phb_bubble : 3; + mmr_t phc_bubble : 3; + mmr_t phd_bubble : 3; + mmr_t phe_bubble : 3; + mmr_t sel_a : 4; + mmr_t dq_sel_a : 4; + mmr_t reserved_0 : 1; + } sh_y_phase_cfg_s; +} sh_y_phase_cfg_u_t; +#else +typedef union sh_y_phase_cfg_u { + mmr_t sh_y_phase_cfg_regval; + struct { + mmr_t reserved_0 : 1; + mmr_t dq_sel_a : 4; + mmr_t sel_a : 4; + mmr_t phe_bubble : 3; + mmr_t phd_bubble : 3; + mmr_t phc_bubble : 3; + mmr_t phb_bubble : 3; + mmr_t pha_bubble : 3; + mmr_t bubble_en : 5; + mmr_t add_cp : 5; + mmr_t hold_req : 5; + mmr_t hold : 5; + mmr_t dq_ld_b : 5; + mmr_t dq_ld_a : 5; + mmr_t ld_b : 5; + mmr_t ld_a : 5; + } sh_y_phase_cfg_s; +} sh_y_phase_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_CFG" */ +/* AC Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_cfg_u { + mmr_t sh_y_cfg_regval; + struct { + mmr_t mode_serial : 1; + mmr_t dirc_random_replacement : 1; + mmr_t dir_counter_init : 6; + mmr_t ta_dlys : 32; + mmr_t da_bb_clr : 4; + mmr_t dc_bb_clr : 4; + mmr_t wt_bb_clr : 4; + mmr_t sso_wt_en : 1; + mmr_t trcd2_en : 1; + mmr_t trcd4_en : 1; + mmr_t req_cntr_dis : 1; + mmr_t req_cntr_val : 6; + mmr_t inv_cas_addr : 1; + mmr_t clr_dir_cache : 1; + } sh_y_cfg_s; +} sh_y_cfg_u_t; +#else +typedef union sh_y_cfg_u { + mmr_t sh_y_cfg_regval; + struct { + mmr_t clr_dir_cache : 1; + mmr_t inv_cas_addr : 1; + mmr_t req_cntr_val : 6; + mmr_t req_cntr_dis : 1; + mmr_t trcd4_en : 1; + mmr_t trcd2_en : 1; + mmr_t sso_wt_en : 1; + mmr_t wt_bb_clr : 4; + mmr_t dc_bb_clr : 4; + mmr_t da_bb_clr : 4; + mmr_t ta_dlys : 32; + mmr_t dir_counter_init : 6; + mmr_t dirc_random_replacement : 1; + mmr_t mode_serial : 1; + } sh_y_cfg_s; +} sh_y_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_DQCT_CFG" */ +/* AC Config Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_dqct_cfg_u { + mmr_t sh_y_dqct_cfg_regval; + struct { + mmr_t rd_sel : 4; + mmr_t wt_sel : 4; + mmr_t dta_rd_sel : 4; + mmr_t dta_wt_sel : 4; + mmr_t dir_rd_sel : 4; + mmr_t mdir_rd_sel : 4; + mmr_t reserved_0 : 40; + } sh_y_dqct_cfg_s; +} sh_y_dqct_cfg_u_t; +#else +typedef union sh_y_dqct_cfg_u { + mmr_t sh_y_dqct_cfg_regval; + struct { + mmr_t reserved_0 : 40; + mmr_t mdir_rd_sel : 4; + mmr_t dir_rd_sel : 4; + mmr_t dta_wt_sel : 4; + mmr_t dta_rd_sel : 4; + mmr_t wt_sel : 4; + mmr_t rd_sel : 4; + } sh_y_dqct_cfg_s; +} sh_y_dqct_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_REFRESH_CONTROL" */ +/* Refresh Control Register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_refresh_control_u { + mmr_t sh_y_refresh_control_regval; + struct { + mmr_t enable : 8; + mmr_t interval : 9; + mmr_t hold : 6; + mmr_t interleave : 1; + mmr_t half_rate : 4; + mmr_t reserved_0 : 36; + } sh_y_refresh_control_s; +} sh_y_refresh_control_u_t; +#else +typedef union sh_y_refresh_control_u { + mmr_t sh_y_refresh_control_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t half_rate : 4; + mmr_t interleave : 1; + mmr_t hold : 6; + mmr_t interval : 9; + mmr_t enable : 8; + } sh_y_refresh_control_s; +} sh_y_refresh_control_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MEM_RED_BLACK" */ +/* MD fairness watchdog timers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_mem_red_black_u { + mmr_t sh_mem_red_black_regval; + struct { + mmr_t time : 16; + mmr_t err_time : 36; + mmr_t reserved_0 : 12; + } sh_mem_red_black_s; +} sh_mem_red_black_u_t; +#else +typedef union sh_mem_red_black_u { + mmr_t sh_mem_red_black_regval; + struct { + mmr_t reserved_0 : 12; + mmr_t err_time : 36; + mmr_t time : 16; + } sh_mem_red_black_s; +} sh_mem_red_black_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MISC_MEM_CFG" */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_misc_mem_cfg_u { + mmr_t sh_misc_mem_cfg_regval; + struct { + mmr_t express_header_enable : 1; + mmr_t spec_header_enable : 1; + mmr_t jnr_bypass_enable : 1; + mmr_t xn_rd_same_as_pi : 1; + mmr_t low_write_buffer_threshold : 6; + mmr_t reserved_0 : 2; + mmr_t low_victim_buffer_threshold : 6; + mmr_t reserved_1 : 2; + mmr_t throttle_cnt : 8; + mmr_t disabled_read_tnums : 5; + mmr_t reserved_2 : 3; + mmr_t disabled_write_tnums : 5; + mmr_t reserved_3 : 3; + mmr_t disabled_victims : 6; + mmr_t reserved_4 : 2; + mmr_t alternate_xn_rp_plane : 1; + mmr_t reserved_5 : 11; + } sh_misc_mem_cfg_s; +} sh_misc_mem_cfg_u_t; +#else +typedef union sh_misc_mem_cfg_u { + mmr_t sh_misc_mem_cfg_regval; + struct { + mmr_t reserved_5 : 11; + mmr_t alternate_xn_rp_plane : 1; + mmr_t reserved_4 : 2; + mmr_t disabled_victims : 6; + mmr_t reserved_3 : 3; + mmr_t disabled_write_tnums : 5; + mmr_t reserved_2 : 3; + mmr_t disabled_read_tnums : 5; + mmr_t throttle_cnt : 8; + mmr_t reserved_1 : 2; + mmr_t low_victim_buffer_threshold : 6; + mmr_t reserved_0 : 2; + mmr_t low_write_buffer_threshold : 6; + mmr_t xn_rd_same_as_pi : 1; + mmr_t jnr_bypass_enable : 1; + mmr_t spec_header_enable : 1; + mmr_t express_header_enable : 1; + } sh_misc_mem_cfg_s; +} sh_misc_mem_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PIO_RQ_CRD_CTL" */ +/* pio_rq Credit Circulation Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pio_rq_crd_ctl_u { + mmr_t sh_pio_rq_crd_ctl_regval; + struct { + mmr_t depth : 6; + mmr_t reserved_0 : 58; + } sh_pio_rq_crd_ctl_s; +} sh_pio_rq_crd_ctl_u_t; +#else +typedef union sh_pio_rq_crd_ctl_u { + mmr_t sh_pio_rq_crd_ctl_regval; + struct { + mmr_t reserved_0 : 58; + mmr_t depth : 6; + } sh_pio_rq_crd_ctl_s; +} sh_pio_rq_crd_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_MD_RQ_CRD_CTL" */ +/* pi_md_rq Credit Circulation Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_md_rq_crd_ctl_u { + mmr_t sh_pi_md_rq_crd_ctl_regval; + struct { + mmr_t depth : 6; + mmr_t reserved_0 : 58; + } sh_pi_md_rq_crd_ctl_s; +} sh_pi_md_rq_crd_ctl_u_t; +#else +typedef union sh_pi_md_rq_crd_ctl_u { + mmr_t sh_pi_md_rq_crd_ctl_regval; + struct { + mmr_t reserved_0 : 58; + mmr_t depth : 6; + } sh_pi_md_rq_crd_ctl_s; +} sh_pi_md_rq_crd_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_PI_MD_RP_CRD_CTL" */ +/* pi_md_rp Credit Circulation Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_pi_md_rp_crd_ctl_u { + mmr_t sh_pi_md_rp_crd_ctl_regval; + struct { + mmr_t depth : 6; + mmr_t reserved_0 : 58; + } sh_pi_md_rp_crd_ctl_s; +} sh_pi_md_rp_crd_ctl_u_t; +#else +typedef union sh_pi_md_rp_crd_ctl_u { + mmr_t sh_pi_md_rp_crd_ctl_regval; + struct { + mmr_t reserved_0 : 58; + mmr_t depth : 6; + } sh_pi_md_rp_crd_ctl_s; +} sh_pi_md_rp_crd_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_RQ_CRD_CTL" */ +/* xn_md_rq Credit Circulation Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_rq_crd_ctl_u { + mmr_t sh_xn_md_rq_crd_ctl_regval; + struct { + mmr_t depth : 6; + mmr_t reserved_0 : 58; + } sh_xn_md_rq_crd_ctl_s; +} sh_xn_md_rq_crd_ctl_u_t; +#else +typedef union sh_xn_md_rq_crd_ctl_u { + mmr_t sh_xn_md_rq_crd_ctl_regval; + struct { + mmr_t reserved_0 : 58; + mmr_t depth : 6; + } sh_xn_md_rq_crd_ctl_s; +} sh_xn_md_rq_crd_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_XN_MD_RP_CRD_CTL" */ +/* xn_md_rp Credit Circulation Control */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_xn_md_rp_crd_ctl_u { + mmr_t sh_xn_md_rp_crd_ctl_regval; + struct { + mmr_t depth : 6; + mmr_t reserved_0 : 58; + } sh_xn_md_rp_crd_ctl_s; +} sh_xn_md_rp_crd_ctl_u_t; +#else +typedef union sh_xn_md_rp_crd_ctl_u { + mmr_t sh_xn_md_rp_crd_ctl_regval; + struct { + mmr_t reserved_0 : 58; + mmr_t depth : 6; + } sh_xn_md_rp_crd_ctl_s; +} sh_xn_md_rp_crd_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_TAG0" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_tag0_u { + mmr_t sh_x_tag0_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_x_tag0_s; +} sh_x_tag0_u_t; +#else +typedef union sh_x_tag0_u { + mmr_t sh_x_tag0_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_x_tag0_s; +} sh_x_tag0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_TAG1" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_tag1_u { + mmr_t sh_x_tag1_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_x_tag1_s; +} sh_x_tag1_u_t; +#else +typedef union sh_x_tag1_u { + mmr_t sh_x_tag1_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_x_tag1_s; +} sh_x_tag1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_TAG2" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_tag2_u { + mmr_t sh_x_tag2_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_x_tag2_s; +} sh_x_tag2_u_t; +#else +typedef union sh_x_tag2_u { + mmr_t sh_x_tag2_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_x_tag2_s; +} sh_x_tag2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_TAG3" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_tag3_u { + mmr_t sh_x_tag3_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_x_tag3_s; +} sh_x_tag3_u_t; +#else +typedef union sh_x_tag3_u { + mmr_t sh_x_tag3_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_x_tag3_s; +} sh_x_tag3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_TAG4" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_tag4_u { + mmr_t sh_x_tag4_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_x_tag4_s; +} sh_x_tag4_u_t; +#else +typedef union sh_x_tag4_u { + mmr_t sh_x_tag4_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_x_tag4_s; +} sh_x_tag4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_TAG5" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_tag5_u { + mmr_t sh_x_tag5_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_x_tag5_s; +} sh_x_tag5_u_t; +#else +typedef union sh_x_tag5_u { + mmr_t sh_x_tag5_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_x_tag5_s; +} sh_x_tag5_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_TAG6" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_tag6_u { + mmr_t sh_x_tag6_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_x_tag6_s; +} sh_x_tag6_u_t; +#else +typedef union sh_x_tag6_u { + mmr_t sh_x_tag6_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_x_tag6_s; +} sh_x_tag6_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_TAG7" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_tag7_u { + mmr_t sh_x_tag7_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_x_tag7_s; +} sh_x_tag7_u_t; +#else +typedef union sh_x_tag7_u { + mmr_t sh_x_tag7_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_x_tag7_s; +} sh_x_tag7_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_TAG0" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_tag0_u { + mmr_t sh_y_tag0_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_y_tag0_s; +} sh_y_tag0_u_t; +#else +typedef union sh_y_tag0_u { + mmr_t sh_y_tag0_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_y_tag0_s; +} sh_y_tag0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_TAG1" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_tag1_u { + mmr_t sh_y_tag1_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_y_tag1_s; +} sh_y_tag1_u_t; +#else +typedef union sh_y_tag1_u { + mmr_t sh_y_tag1_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_y_tag1_s; +} sh_y_tag1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_TAG2" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_tag2_u { + mmr_t sh_y_tag2_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_y_tag2_s; +} sh_y_tag2_u_t; +#else +typedef union sh_y_tag2_u { + mmr_t sh_y_tag2_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_y_tag2_s; +} sh_y_tag2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_TAG3" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_tag3_u { + mmr_t sh_y_tag3_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_y_tag3_s; +} sh_y_tag3_u_t; +#else +typedef union sh_y_tag3_u { + mmr_t sh_y_tag3_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_y_tag3_s; +} sh_y_tag3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_TAG4" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_tag4_u { + mmr_t sh_y_tag4_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_y_tag4_s; +} sh_y_tag4_u_t; +#else +typedef union sh_y_tag4_u { + mmr_t sh_y_tag4_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_y_tag4_s; +} sh_y_tag4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_TAG5" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_tag5_u { + mmr_t sh_y_tag5_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_y_tag5_s; +} sh_y_tag5_u_t; +#else +typedef union sh_y_tag5_u { + mmr_t sh_y_tag5_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_y_tag5_s; +} sh_y_tag5_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_TAG6" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_tag6_u { + mmr_t sh_y_tag6_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_y_tag6_s; +} sh_y_tag6_u_t; +#else +typedef union sh_y_tag6_u { + mmr_t sh_y_tag6_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_y_tag6_s; +} sh_y_tag6_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_TAG7" */ +/* AC tag Registers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_tag7_u { + mmr_t sh_y_tag7_regval; + struct { + mmr_t tag : 20; + mmr_t reserved_0 : 44; + } sh_y_tag7_s; +} sh_y_tag7_u_t; +#else +typedef union sh_y_tag7_u { + mmr_t sh_y_tag7_regval; + struct { + mmr_t reserved_0 : 44; + mmr_t tag : 20; + } sh_y_tag7_s; +} sh_y_tag7_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MMRBIST_BASE" */ +/* mmr/bist base address */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_mmrbist_base_u { + mmr_t sh_mmrbist_base_regval; + struct { + mmr_t reserved_0 : 3; + mmr_t dword_addr : 47; + mmr_t reserved_1 : 14; + } sh_mmrbist_base_s; +} sh_mmrbist_base_u_t; +#else +typedef union sh_mmrbist_base_u { + mmr_t sh_mmrbist_base_regval; + struct { + mmr_t reserved_1 : 14; + mmr_t dword_addr : 47; + mmr_t reserved_0 : 3; + } sh_mmrbist_base_s; +} sh_mmrbist_base_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MMRBIST_CTL" */ +/* Bist base address */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_mmrbist_ctl_u { + mmr_t sh_mmrbist_ctl_regval; + struct { + mmr_t block_length : 31; + mmr_t reserved_0 : 1; + mmr_t cmd : 7; + mmr_t reserved_1 : 1; + mmr_t in_progress : 1; + mmr_t fail : 1; + mmr_t mem_idle : 1; + mmr_t reserved_2 : 1; + mmr_t reset_state : 1; + mmr_t reserved_3 : 19; + } sh_mmrbist_ctl_s; +} sh_mmrbist_ctl_u_t; +#else +typedef union sh_mmrbist_ctl_u { + mmr_t sh_mmrbist_ctl_regval; + struct { + mmr_t reserved_3 : 19; + mmr_t reset_state : 1; + mmr_t reserved_2 : 1; + mmr_t mem_idle : 1; + mmr_t fail : 1; + mmr_t in_progress : 1; + mmr_t reserved_1 : 1; + mmr_t cmd : 7; + mmr_t reserved_0 : 1; + mmr_t block_length : 31; + } sh_mmrbist_ctl_s; +} sh_mmrbist_ctl_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DBUG_DATA_CFG" */ +/* configuration for md debug data muxes */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dbug_data_cfg_u { + mmr_t sh_md_dbug_data_cfg_regval; + struct { + mmr_t nibble0_chiplet : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_chiplet : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_chiplet : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_chiplet : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_chiplet : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_chiplet : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_chiplet : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_chiplet : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble : 3; + mmr_t reserved_15 : 1; + } sh_md_dbug_data_cfg_s; +} sh_md_dbug_data_cfg_u_t; +#else +typedef union sh_md_dbug_data_cfg_u { + mmr_t sh_md_dbug_data_cfg_regval; + struct { + mmr_t reserved_15 : 1; + mmr_t nibble7_nibble : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_chiplet : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_chiplet : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_chiplet : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_chiplet : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_chiplet : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_chiplet : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_chiplet : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_chiplet : 3; + } sh_md_dbug_data_cfg_s; +} sh_md_dbug_data_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DBUG_TRIGGER_CFG" */ +/* configuration for md debug triggers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dbug_trigger_cfg_u { + mmr_t sh_md_dbug_trigger_cfg_regval; + struct { + mmr_t nibble0_chiplet : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_nibble : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_chiplet : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_nibble : 3; + mmr_t reserved_3 : 1; + mmr_t nibble2_chiplet : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_nibble : 3; + mmr_t reserved_5 : 1; + mmr_t nibble3_chiplet : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_nibble : 3; + mmr_t reserved_7 : 1; + mmr_t nibble4_chiplet : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_nibble : 3; + mmr_t reserved_9 : 1; + mmr_t nibble5_chiplet : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_nibble : 3; + mmr_t reserved_11 : 1; + mmr_t nibble6_chiplet : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_nibble : 3; + mmr_t reserved_13 : 1; + mmr_t nibble7_chiplet : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_nibble : 3; + mmr_t enable : 1; + } sh_md_dbug_trigger_cfg_s; +} sh_md_dbug_trigger_cfg_u_t; +#else +typedef union sh_md_dbug_trigger_cfg_u { + mmr_t sh_md_dbug_trigger_cfg_regval; + struct { + mmr_t enable : 1; + mmr_t nibble7_nibble : 3; + mmr_t reserved_14 : 1; + mmr_t nibble7_chiplet : 3; + mmr_t reserved_13 : 1; + mmr_t nibble6_nibble : 3; + mmr_t reserved_12 : 1; + mmr_t nibble6_chiplet : 3; + mmr_t reserved_11 : 1; + mmr_t nibble5_nibble : 3; + mmr_t reserved_10 : 1; + mmr_t nibble5_chiplet : 3; + mmr_t reserved_9 : 1; + mmr_t nibble4_nibble : 3; + mmr_t reserved_8 : 1; + mmr_t nibble4_chiplet : 3; + mmr_t reserved_7 : 1; + mmr_t nibble3_nibble : 3; + mmr_t reserved_6 : 1; + mmr_t nibble3_chiplet : 3; + mmr_t reserved_5 : 1; + mmr_t nibble2_nibble : 3; + mmr_t reserved_4 : 1; + mmr_t nibble2_chiplet : 3; + mmr_t reserved_3 : 1; + mmr_t nibble1_nibble : 3; + mmr_t reserved_2 : 1; + mmr_t nibble1_chiplet : 3; + mmr_t reserved_1 : 1; + mmr_t nibble0_nibble : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_chiplet : 3; + } sh_md_dbug_trigger_cfg_s; +} sh_md_dbug_trigger_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DBUG_COMPARE" */ +/* md debug compare pattern and mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dbug_compare_u { + mmr_t sh_md_dbug_compare_regval; + struct { + mmr_t pattern : 32; + mmr_t mask : 32; + } sh_md_dbug_compare_s; +} sh_md_dbug_compare_u_t; +#else +typedef union sh_md_dbug_compare_u { + mmr_t sh_md_dbug_compare_regval; + struct { + mmr_t mask : 32; + mmr_t pattern : 32; + } sh_md_dbug_compare_s; +} sh_md_dbug_compare_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_MOD_DBUG_SEL" */ +/* MD acx debug select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_mod_dbug_sel_u { + mmr_t sh_x_mod_dbug_sel_regval; + struct { + mmr_t tag_sel : 8; + mmr_t wbq_sel : 8; + mmr_t arb_sel : 8; + mmr_t atl_sel : 11; + mmr_t atr_sel : 11; + mmr_t dql_sel : 6; + mmr_t dqr_sel : 6; + mmr_t reserved_0 : 6; + } sh_x_mod_dbug_sel_s; +} sh_x_mod_dbug_sel_u_t; +#else +typedef union sh_x_mod_dbug_sel_u { + mmr_t sh_x_mod_dbug_sel_regval; + struct { + mmr_t reserved_0 : 6; + mmr_t dqr_sel : 6; + mmr_t dql_sel : 6; + mmr_t atr_sel : 11; + mmr_t atl_sel : 11; + mmr_t arb_sel : 8; + mmr_t wbq_sel : 8; + mmr_t tag_sel : 8; + } sh_x_mod_dbug_sel_s; +} sh_x_mod_dbug_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_DBUG_SEL" */ +/* MD acx debug select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_dbug_sel_u { + mmr_t sh_x_dbug_sel_regval; + struct { + mmr_t dbg_sel : 24; + mmr_t reserved_0 : 40; + } sh_x_dbug_sel_s; +} sh_x_dbug_sel_u_t; +#else +typedef union sh_x_dbug_sel_u { + mmr_t sh_x_dbug_sel_regval; + struct { + mmr_t reserved_0 : 40; + mmr_t dbg_sel : 24; + } sh_x_dbug_sel_s; +} sh_x_dbug_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_LADDR_CMP" */ +/* MD acx address compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_laddr_cmp_u { + mmr_t sh_x_laddr_cmp_regval; + struct { + mmr_t cmp_val : 28; + mmr_t reserved_0 : 4; + mmr_t mask_val : 28; + mmr_t reserved_1 : 4; + } sh_x_laddr_cmp_s; +} sh_x_laddr_cmp_u_t; +#else +typedef union sh_x_laddr_cmp_u { + mmr_t sh_x_laddr_cmp_regval; + struct { + mmr_t reserved_1 : 4; + mmr_t mask_val : 28; + mmr_t reserved_0 : 4; + mmr_t cmp_val : 28; + } sh_x_laddr_cmp_s; +} sh_x_laddr_cmp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_RADDR_CMP" */ +/* MD acx address compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_raddr_cmp_u { + mmr_t sh_x_raddr_cmp_regval; + struct { + mmr_t cmp_val : 28; + mmr_t reserved_0 : 4; + mmr_t mask_val : 28; + mmr_t reserved_1 : 4; + } sh_x_raddr_cmp_s; +} sh_x_raddr_cmp_u_t; +#else +typedef union sh_x_raddr_cmp_u { + mmr_t sh_x_raddr_cmp_regval; + struct { + mmr_t reserved_1 : 4; + mmr_t mask_val : 28; + mmr_t reserved_0 : 4; + mmr_t cmp_val : 28; + } sh_x_raddr_cmp_s; +} sh_x_raddr_cmp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_TAG_CMP" */ +/* MD acx tagmgr compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_tag_cmp_u { + mmr_t sh_x_tag_cmp_regval; + struct { + mmr_t cmd : 8; + mmr_t addr : 33; + mmr_t src : 14; + mmr_t reserved_0 : 9; + } sh_x_tag_cmp_s; +} sh_x_tag_cmp_u_t; +#else +typedef union sh_x_tag_cmp_u { + mmr_t sh_x_tag_cmp_regval; + struct { + mmr_t reserved_0 : 9; + mmr_t src : 14; + mmr_t addr : 33; + mmr_t cmd : 8; + } sh_x_tag_cmp_s; +} sh_x_tag_cmp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_X_TAG_MASK" */ +/* MD acx tagmgr mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_x_tag_mask_u { + mmr_t sh_x_tag_mask_regval; + struct { + mmr_t cmd : 8; + mmr_t addr : 33; + mmr_t src : 14; + mmr_t reserved_0 : 9; + } sh_x_tag_mask_s; +} sh_x_tag_mask_u_t; +#else +typedef union sh_x_tag_mask_u { + mmr_t sh_x_tag_mask_regval; + struct { + mmr_t reserved_0 : 9; + mmr_t src : 14; + mmr_t addr : 33; + mmr_t cmd : 8; + } sh_x_tag_mask_s; +} sh_x_tag_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_MOD_DBUG_SEL" */ +/* MD acy debug select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_mod_dbug_sel_u { + mmr_t sh_y_mod_dbug_sel_regval; + struct { + mmr_t tag_sel : 8; + mmr_t wbq_sel : 8; + mmr_t arb_sel : 8; + mmr_t atl_sel : 11; + mmr_t atr_sel : 11; + mmr_t dql_sel : 6; + mmr_t dqr_sel : 6; + mmr_t reserved_0 : 6; + } sh_y_mod_dbug_sel_s; +} sh_y_mod_dbug_sel_u_t; +#else +typedef union sh_y_mod_dbug_sel_u { + mmr_t sh_y_mod_dbug_sel_regval; + struct { + mmr_t reserved_0 : 6; + mmr_t dqr_sel : 6; + mmr_t dql_sel : 6; + mmr_t atr_sel : 11; + mmr_t atl_sel : 11; + mmr_t arb_sel : 8; + mmr_t wbq_sel : 8; + mmr_t tag_sel : 8; + } sh_y_mod_dbug_sel_s; +} sh_y_mod_dbug_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_DBUG_SEL" */ +/* MD acy debug select */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_dbug_sel_u { + mmr_t sh_y_dbug_sel_regval; + struct { + mmr_t dbg_sel : 24; + mmr_t reserved_0 : 40; + } sh_y_dbug_sel_s; +} sh_y_dbug_sel_u_t; +#else +typedef union sh_y_dbug_sel_u { + mmr_t sh_y_dbug_sel_regval; + struct { + mmr_t reserved_0 : 40; + mmr_t dbg_sel : 24; + } sh_y_dbug_sel_s; +} sh_y_dbug_sel_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_LADDR_CMP" */ +/* MD acy address compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_laddr_cmp_u { + mmr_t sh_y_laddr_cmp_regval; + struct { + mmr_t cmp_val : 28; + mmr_t reserved_0 : 4; + mmr_t mask_val : 28; + mmr_t reserved_1 : 4; + } sh_y_laddr_cmp_s; +} sh_y_laddr_cmp_u_t; +#else +typedef union sh_y_laddr_cmp_u { + mmr_t sh_y_laddr_cmp_regval; + struct { + mmr_t reserved_1 : 4; + mmr_t mask_val : 28; + mmr_t reserved_0 : 4; + mmr_t cmp_val : 28; + } sh_y_laddr_cmp_s; +} sh_y_laddr_cmp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_RADDR_CMP" */ +/* MD acy address compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_raddr_cmp_u { + mmr_t sh_y_raddr_cmp_regval; + struct { + mmr_t cmp_val : 28; + mmr_t reserved_0 : 4; + mmr_t mask_val : 28; + mmr_t reserved_1 : 4; + } sh_y_raddr_cmp_s; +} sh_y_raddr_cmp_u_t; +#else +typedef union sh_y_raddr_cmp_u { + mmr_t sh_y_raddr_cmp_regval; + struct { + mmr_t reserved_1 : 4; + mmr_t mask_val : 28; + mmr_t reserved_0 : 4; + mmr_t cmp_val : 28; + } sh_y_raddr_cmp_s; +} sh_y_raddr_cmp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_TAG_CMP" */ +/* MD acy tagmgr compare */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_tag_cmp_u { + mmr_t sh_y_tag_cmp_regval; + struct { + mmr_t cmd : 8; + mmr_t addr : 33; + mmr_t src : 14; + mmr_t reserved_0 : 9; + } sh_y_tag_cmp_s; +} sh_y_tag_cmp_u_t; +#else +typedef union sh_y_tag_cmp_u { + mmr_t sh_y_tag_cmp_regval; + struct { + mmr_t reserved_0 : 9; + mmr_t src : 14; + mmr_t addr : 33; + mmr_t cmd : 8; + } sh_y_tag_cmp_s; +} sh_y_tag_cmp_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_Y_TAG_MASK" */ +/* MD acy tagmgr mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_y_tag_mask_u { + mmr_t sh_y_tag_mask_regval; + struct { + mmr_t cmd : 8; + mmr_t addr : 33; + mmr_t src : 14; + mmr_t reserved_0 : 9; + } sh_y_tag_mask_s; +} sh_y_tag_mask_u_t; +#else +typedef union sh_y_tag_mask_u { + mmr_t sh_y_tag_mask_regval; + struct { + mmr_t reserved_0 : 9; + mmr_t src : 14; + mmr_t addr : 33; + mmr_t cmd : 8; + } sh_y_tag_mask_s; +} sh_y_tag_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_JNR_DBUG_DATA_CFG" */ +/* configuration for md jnr debug data muxes */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_jnr_dbug_data_cfg_u { + mmr_t sh_md_jnr_dbug_data_cfg_regval; + struct { + mmr_t nibble0_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble1_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble2_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble3_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble4_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble5_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble6_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble7_sel : 3; + mmr_t reserved_7 : 33; + } sh_md_jnr_dbug_data_cfg_s; +} sh_md_jnr_dbug_data_cfg_u_t; +#else +typedef union sh_md_jnr_dbug_data_cfg_u { + mmr_t sh_md_jnr_dbug_data_cfg_regval; + struct { + mmr_t reserved_7 : 33; + mmr_t nibble7_sel : 3; + mmr_t reserved_6 : 1; + mmr_t nibble6_sel : 3; + mmr_t reserved_5 : 1; + mmr_t nibble5_sel : 3; + mmr_t reserved_4 : 1; + mmr_t nibble4_sel : 3; + mmr_t reserved_3 : 1; + mmr_t nibble3_sel : 3; + mmr_t reserved_2 : 1; + mmr_t nibble2_sel : 3; + mmr_t reserved_1 : 1; + mmr_t nibble1_sel : 3; + mmr_t reserved_0 : 1; + mmr_t nibble0_sel : 3; + } sh_md_jnr_dbug_data_cfg_s; +} sh_md_jnr_dbug_data_cfg_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_LAST_CREDIT" */ +/* captures last credit values on reset */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_last_credit_u { + mmr_t sh_md_last_credit_regval; + struct { + mmr_t rq_to_pi : 6; + mmr_t reserved_0 : 2; + mmr_t rp_to_pi : 6; + mmr_t reserved_1 : 2; + mmr_t rq_to_xn : 6; + mmr_t reserved_2 : 2; + mmr_t rp_to_xn : 6; + mmr_t reserved_3 : 2; + mmr_t to_lb : 6; + mmr_t reserved_4 : 26; + } sh_md_last_credit_s; +} sh_md_last_credit_u_t; +#else +typedef union sh_md_last_credit_u { + mmr_t sh_md_last_credit_regval; + struct { + mmr_t reserved_4 : 26; + mmr_t to_lb : 6; + mmr_t reserved_3 : 2; + mmr_t rp_to_xn : 6; + mmr_t reserved_2 : 2; + mmr_t rq_to_xn : 6; + mmr_t reserved_1 : 2; + mmr_t rp_to_pi : 6; + mmr_t reserved_0 : 2; + mmr_t rq_to_pi : 6; + } sh_md_last_credit_s; +} sh_md_last_credit_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MEM_CAPTURE_ADDR" */ +/* Address capture address register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_mem_capture_addr_u { + mmr_t sh_mem_capture_addr_regval; + struct { + mmr_t reserved_0 : 3; + mmr_t addr : 33; + mmr_t cmd : 8; + mmr_t reserved_1 : 20; + } sh_mem_capture_addr_s; +} sh_mem_capture_addr_u_t; +#else +typedef union sh_mem_capture_addr_u { + mmr_t sh_mem_capture_addr_regval; + struct { + mmr_t reserved_1 : 20; + mmr_t cmd : 8; + mmr_t addr : 33; + mmr_t reserved_0 : 3; + } sh_mem_capture_addr_s; +} sh_mem_capture_addr_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MEM_CAPTURE_MASK" */ +/* Address capture mask register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_mem_capture_mask_u { + mmr_t sh_mem_capture_mask_regval; + struct { + mmr_t reserved_0 : 3; + mmr_t addr : 33; + mmr_t cmd : 8; + mmr_t enable_local : 1; + mmr_t enable_remote : 1; + mmr_t reserved_1 : 18; + } sh_mem_capture_mask_s; +} sh_mem_capture_mask_u_t; +#else +typedef union sh_mem_capture_mask_u { + mmr_t sh_mem_capture_mask_regval; + struct { + mmr_t reserved_1 : 18; + mmr_t enable_remote : 1; + mmr_t enable_local : 1; + mmr_t cmd : 8; + mmr_t addr : 33; + mmr_t reserved_0 : 3; + } sh_mem_capture_mask_s; +} sh_mem_capture_mask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MEM_CAPTURE_HDR" */ +/* Address capture header register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_mem_capture_hdr_u { + mmr_t sh_mem_capture_hdr_regval; + struct { + mmr_t reserved_0 : 3; + mmr_t addr : 33; + mmr_t cmd : 8; + mmr_t src : 14; + mmr_t cntr : 6; + } sh_mem_capture_hdr_s; +} sh_mem_capture_hdr_u_t; +#else +typedef union sh_mem_capture_hdr_u { + mmr_t sh_mem_capture_hdr_regval; + struct { + mmr_t cntr : 6; + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t addr : 33; + mmr_t reserved_0 : 3; + } sh_mem_capture_hdr_s; +} sh_mem_capture_hdr_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_CONFIG" */ +/* DQ directory config register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_config_u { + mmr_t sh_md_dqlp_mmr_dir_config_regval; + struct { + mmr_t sys_size : 3; + mmr_t en_direcc : 1; + mmr_t en_dirpois : 1; + mmr_t reserved_0 : 59; + } sh_md_dqlp_mmr_dir_config_s; +} sh_md_dqlp_mmr_dir_config_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_config_u { + mmr_t sh_md_dqlp_mmr_dir_config_regval; + struct { + mmr_t reserved_0 : 59; + mmr_t en_dirpois : 1; + mmr_t en_direcc : 1; + mmr_t sys_size : 3; + } sh_md_dqlp_mmr_dir_config_s; +} sh_md_dqlp_mmr_dir_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC0" */ +/* node [63:0] presence bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_presvec0_u { + mmr_t sh_md_dqlp_mmr_dir_presvec0_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_presvec0_s; +} sh_md_dqlp_mmr_dir_presvec0_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_presvec0_u { + mmr_t sh_md_dqlp_mmr_dir_presvec0_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_presvec0_s; +} sh_md_dqlp_mmr_dir_presvec0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC1" */ +/* node [127:64] presence bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_presvec1_u { + mmr_t sh_md_dqlp_mmr_dir_presvec1_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_presvec1_s; +} sh_md_dqlp_mmr_dir_presvec1_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_presvec1_u { + mmr_t sh_md_dqlp_mmr_dir_presvec1_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_presvec1_s; +} sh_md_dqlp_mmr_dir_presvec1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC2" */ +/* node [191:128] presence bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_presvec2_u { + mmr_t sh_md_dqlp_mmr_dir_presvec2_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_presvec2_s; +} sh_md_dqlp_mmr_dir_presvec2_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_presvec2_u { + mmr_t sh_md_dqlp_mmr_dir_presvec2_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_presvec2_s; +} sh_md_dqlp_mmr_dir_presvec2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRESVEC3" */ +/* node [255:192] presence bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_presvec3_u { + mmr_t sh_md_dqlp_mmr_dir_presvec3_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_presvec3_s; +} sh_md_dqlp_mmr_dir_presvec3_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_presvec3_u { + mmr_t sh_md_dqlp_mmr_dir_presvec3_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_presvec3_s; +} sh_md_dqlp_mmr_dir_presvec3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC0" */ +/* local vector for acc=0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_locvec0_u { + mmr_t sh_md_dqlp_mmr_dir_locvec0_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec0_s; +} sh_md_dqlp_mmr_dir_locvec0_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_locvec0_u { + mmr_t sh_md_dqlp_mmr_dir_locvec0_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec0_s; +} sh_md_dqlp_mmr_dir_locvec0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC1" */ +/* local vector for acc=1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_locvec1_u { + mmr_t sh_md_dqlp_mmr_dir_locvec1_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec1_s; +} sh_md_dqlp_mmr_dir_locvec1_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_locvec1_u { + mmr_t sh_md_dqlp_mmr_dir_locvec1_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec1_s; +} sh_md_dqlp_mmr_dir_locvec1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC2" */ +/* local vector for acc=2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_locvec2_u { + mmr_t sh_md_dqlp_mmr_dir_locvec2_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec2_s; +} sh_md_dqlp_mmr_dir_locvec2_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_locvec2_u { + mmr_t sh_md_dqlp_mmr_dir_locvec2_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec2_s; +} sh_md_dqlp_mmr_dir_locvec2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC3" */ +/* local vector for acc=3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_locvec3_u { + mmr_t sh_md_dqlp_mmr_dir_locvec3_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec3_s; +} sh_md_dqlp_mmr_dir_locvec3_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_locvec3_u { + mmr_t sh_md_dqlp_mmr_dir_locvec3_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec3_s; +} sh_md_dqlp_mmr_dir_locvec3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC4" */ +/* local vector for acc=4 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_locvec4_u { + mmr_t sh_md_dqlp_mmr_dir_locvec4_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec4_s; +} sh_md_dqlp_mmr_dir_locvec4_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_locvec4_u { + mmr_t sh_md_dqlp_mmr_dir_locvec4_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec4_s; +} sh_md_dqlp_mmr_dir_locvec4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC5" */ +/* local vector for acc=5 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_locvec5_u { + mmr_t sh_md_dqlp_mmr_dir_locvec5_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec5_s; +} sh_md_dqlp_mmr_dir_locvec5_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_locvec5_u { + mmr_t sh_md_dqlp_mmr_dir_locvec5_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec5_s; +} sh_md_dqlp_mmr_dir_locvec5_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC6" */ +/* local vector for acc=6 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_locvec6_u { + mmr_t sh_md_dqlp_mmr_dir_locvec6_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec6_s; +} sh_md_dqlp_mmr_dir_locvec6_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_locvec6_u { + mmr_t sh_md_dqlp_mmr_dir_locvec6_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec6_s; +} sh_md_dqlp_mmr_dir_locvec6_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_LOCVEC7" */ +/* local vector for acc=7 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_locvec7_u { + mmr_t sh_md_dqlp_mmr_dir_locvec7_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec7_s; +} sh_md_dqlp_mmr_dir_locvec7_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_locvec7_u { + mmr_t sh_md_dqlp_mmr_dir_locvec7_regval; + struct { + mmr_t vec : 64; + } sh_md_dqlp_mmr_dir_locvec7_s; +} sh_md_dqlp_mmr_dir_locvec7_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ +/* privilege vector for acc=0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_privec0_u { + mmr_t sh_md_dqlp_mmr_dir_privec0_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqlp_mmr_dir_privec0_s; +} sh_md_dqlp_mmr_dir_privec0_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_privec0_u { + mmr_t sh_md_dqlp_mmr_dir_privec0_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqlp_mmr_dir_privec0_s; +} sh_md_dqlp_mmr_dir_privec0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC1" */ +/* privilege vector for acc=1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_privec1_u { + mmr_t sh_md_dqlp_mmr_dir_privec1_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqlp_mmr_dir_privec1_s; +} sh_md_dqlp_mmr_dir_privec1_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_privec1_u { + mmr_t sh_md_dqlp_mmr_dir_privec1_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqlp_mmr_dir_privec1_s; +} sh_md_dqlp_mmr_dir_privec1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC2" */ +/* privilege vector for acc=2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_privec2_u { + mmr_t sh_md_dqlp_mmr_dir_privec2_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqlp_mmr_dir_privec2_s; +} sh_md_dqlp_mmr_dir_privec2_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_privec2_u { + mmr_t sh_md_dqlp_mmr_dir_privec2_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqlp_mmr_dir_privec2_s; +} sh_md_dqlp_mmr_dir_privec2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC3" */ +/* privilege vector for acc=3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_privec3_u { + mmr_t sh_md_dqlp_mmr_dir_privec3_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqlp_mmr_dir_privec3_s; +} sh_md_dqlp_mmr_dir_privec3_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_privec3_u { + mmr_t sh_md_dqlp_mmr_dir_privec3_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqlp_mmr_dir_privec3_s; +} sh_md_dqlp_mmr_dir_privec3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC4" */ +/* privilege vector for acc=4 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_privec4_u { + mmr_t sh_md_dqlp_mmr_dir_privec4_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqlp_mmr_dir_privec4_s; +} sh_md_dqlp_mmr_dir_privec4_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_privec4_u { + mmr_t sh_md_dqlp_mmr_dir_privec4_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqlp_mmr_dir_privec4_s; +} sh_md_dqlp_mmr_dir_privec4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC5" */ +/* privilege vector for acc=5 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_privec5_u { + mmr_t sh_md_dqlp_mmr_dir_privec5_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqlp_mmr_dir_privec5_s; +} sh_md_dqlp_mmr_dir_privec5_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_privec5_u { + mmr_t sh_md_dqlp_mmr_dir_privec5_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqlp_mmr_dir_privec5_s; +} sh_md_dqlp_mmr_dir_privec5_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC6" */ +/* privilege vector for acc=6 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_privec6_u { + mmr_t sh_md_dqlp_mmr_dir_privec6_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqlp_mmr_dir_privec6_s; +} sh_md_dqlp_mmr_dir_privec6_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_privec6_u { + mmr_t sh_md_dqlp_mmr_dir_privec6_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqlp_mmr_dir_privec6_s; +} sh_md_dqlp_mmr_dir_privec6_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC7" */ +/* privilege vector for acc=7 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_privec7_u { + mmr_t sh_md_dqlp_mmr_dir_privec7_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqlp_mmr_dir_privec7_s; +} sh_md_dqlp_mmr_dir_privec7_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_privec7_u { + mmr_t sh_md_dqlp_mmr_dir_privec7_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqlp_mmr_dir_privec7_s; +} sh_md_dqlp_mmr_dir_privec7_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_TIMER" */ +/* MD SXRO timer */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_timer_u { + mmr_t sh_md_dqlp_mmr_dir_timer_regval; + struct { + mmr_t timer_div : 12; + mmr_t timer_en : 1; + mmr_t timer_cur : 9; + mmr_t reserved_0 : 42; + } sh_md_dqlp_mmr_dir_timer_s; +} sh_md_dqlp_mmr_dir_timer_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_timer_u { + mmr_t sh_md_dqlp_mmr_dir_timer_regval; + struct { + mmr_t reserved_0 : 42; + mmr_t timer_cur : 9; + mmr_t timer_en : 1; + mmr_t timer_div : 12; + } sh_md_dqlp_mmr_dir_timer_s; +} sh_md_dqlp_mmr_dir_timer_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY" */ +/* directory pio write data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_piowd_dir_entry_u { + mmr_t sh_md_dqlp_mmr_piowd_dir_entry_regval; + struct { + mmr_t dira : 26; + mmr_t dirb : 26; + mmr_t pri : 3; + mmr_t acc : 3; + mmr_t reserved_0 : 6; + } sh_md_dqlp_mmr_piowd_dir_entry_s; +} sh_md_dqlp_mmr_piowd_dir_entry_u_t; +#else +typedef union sh_md_dqlp_mmr_piowd_dir_entry_u { + mmr_t sh_md_dqlp_mmr_piowd_dir_entry_regval; + struct { + mmr_t reserved_0 : 6; + mmr_t acc : 3; + mmr_t pri : 3; + mmr_t dirb : 26; + mmr_t dira : 26; + } sh_md_dqlp_mmr_piowd_dir_entry_s; +} sh_md_dqlp_mmr_piowd_dir_entry_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC" */ +/* directory ecc register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u { + mmr_t sh_md_dqlp_mmr_piowd_dir_ecc_regval; + struct { + mmr_t ecca : 7; + mmr_t eccb : 7; + mmr_t reserved_0 : 50; + } sh_md_dqlp_mmr_piowd_dir_ecc_s; +} sh_md_dqlp_mmr_piowd_dir_ecc_u_t; +#else +typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u { + mmr_t sh_md_dqlp_mmr_piowd_dir_ecc_regval; + struct { + mmr_t reserved_0 : 50; + mmr_t eccb : 7; + mmr_t ecca : 7; + } sh_md_dqlp_mmr_piowd_dir_ecc_s; +} sh_md_dqlp_mmr_piowd_dir_ecc_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY" */ +/* x directory pio read data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u { + mmr_t sh_md_dqlp_mmr_xpiord_xdir_entry_regval; + struct { + mmr_t dira : 26; + mmr_t dirb : 26; + mmr_t pri : 3; + mmr_t acc : 3; + mmr_t cor : 1; + mmr_t unc : 1; + mmr_t reserved_0 : 4; + } sh_md_dqlp_mmr_xpiord_xdir_entry_s; +} sh_md_dqlp_mmr_xpiord_xdir_entry_u_t; +#else +typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u { + mmr_t sh_md_dqlp_mmr_xpiord_xdir_entry_regval; + struct { + mmr_t reserved_0 : 4; + mmr_t unc : 1; + mmr_t cor : 1; + mmr_t acc : 3; + mmr_t pri : 3; + mmr_t dirb : 26; + mmr_t dira : 26; + } sh_md_dqlp_mmr_xpiord_xdir_entry_s; +} sh_md_dqlp_mmr_xpiord_xdir_entry_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC" */ +/* x directory ecc */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u { + mmr_t sh_md_dqlp_mmr_xpiord_xdir_ecc_regval; + struct { + mmr_t ecca : 7; + mmr_t eccb : 7; + mmr_t reserved_0 : 50; + } sh_md_dqlp_mmr_xpiord_xdir_ecc_s; +} sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t; +#else +typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u { + mmr_t sh_md_dqlp_mmr_xpiord_xdir_ecc_regval; + struct { + mmr_t reserved_0 : 50; + mmr_t eccb : 7; + mmr_t ecca : 7; + } sh_md_dqlp_mmr_xpiord_xdir_ecc_s; +} sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY" */ +/* y directory pio read data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u { + mmr_t sh_md_dqlp_mmr_ypiord_ydir_entry_regval; + struct { + mmr_t dira : 26; + mmr_t dirb : 26; + mmr_t pri : 3; + mmr_t acc : 3; + mmr_t cor : 1; + mmr_t unc : 1; + mmr_t reserved_0 : 4; + } sh_md_dqlp_mmr_ypiord_ydir_entry_s; +} sh_md_dqlp_mmr_ypiord_ydir_entry_u_t; +#else +typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u { + mmr_t sh_md_dqlp_mmr_ypiord_ydir_entry_regval; + struct { + mmr_t reserved_0 : 4; + mmr_t unc : 1; + mmr_t cor : 1; + mmr_t acc : 3; + mmr_t pri : 3; + mmr_t dirb : 26; + mmr_t dira : 26; + } sh_md_dqlp_mmr_ypiord_ydir_entry_s; +} sh_md_dqlp_mmr_ypiord_ydir_entry_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC" */ +/* y directory ecc */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u { + mmr_t sh_md_dqlp_mmr_ypiord_ydir_ecc_regval; + struct { + mmr_t ecca : 7; + mmr_t eccb : 7; + mmr_t reserved_0 : 50; + } sh_md_dqlp_mmr_ypiord_ydir_ecc_s; +} sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t; +#else +typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u { + mmr_t sh_md_dqlp_mmr_ypiord_ydir_ecc_regval; + struct { + mmr_t reserved_0 : 50; + mmr_t eccb : 7; + mmr_t ecca : 7; + } sh_md_dqlp_mmr_ypiord_ydir_ecc_s; +} sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XCERR1" */ +/* correctable dir ecc group 1 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_xcerr1_u { + mmr_t sh_md_dqlp_mmr_xcerr1_regval; + struct { + mmr_t grp1 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 25; + } sh_md_dqlp_mmr_xcerr1_s; +} sh_md_dqlp_mmr_xcerr1_u_t; +#else +typedef union sh_md_dqlp_mmr_xcerr1_u { + mmr_t sh_md_dqlp_mmr_xcerr1_regval; + struct { + mmr_t reserved_0 : 25; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp1 : 36; + } sh_md_dqlp_mmr_xcerr1_s; +} sh_md_dqlp_mmr_xcerr1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XCERR2" */ +/* correctable dir ecc group 2 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_xcerr2_u { + mmr_t sh_md_dqlp_mmr_xcerr2_regval; + struct { + mmr_t grp2 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 26; + } sh_md_dqlp_mmr_xcerr2_s; +} sh_md_dqlp_mmr_xcerr2_u_t; +#else +typedef union sh_md_dqlp_mmr_xcerr2_u { + mmr_t sh_md_dqlp_mmr_xcerr2_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp2 : 36; + } sh_md_dqlp_mmr_xcerr2_s; +} sh_md_dqlp_mmr_xcerr2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XUERR1" */ +/* uncorrectable dir ecc group 1 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_xuerr1_u { + mmr_t sh_md_dqlp_mmr_xuerr1_regval; + struct { + mmr_t grp1 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 25; + } sh_md_dqlp_mmr_xuerr1_s; +} sh_md_dqlp_mmr_xuerr1_u_t; +#else +typedef union sh_md_dqlp_mmr_xuerr1_u { + mmr_t sh_md_dqlp_mmr_xuerr1_regval; + struct { + mmr_t reserved_0 : 25; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp1 : 36; + } sh_md_dqlp_mmr_xuerr1_s; +} sh_md_dqlp_mmr_xuerr1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XUERR2" */ +/* uncorrectable dir ecc group 2 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_xuerr2_u { + mmr_t sh_md_dqlp_mmr_xuerr2_regval; + struct { + mmr_t grp2 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 26; + } sh_md_dqlp_mmr_xuerr2_s; +} sh_md_dqlp_mmr_xuerr2_u_t; +#else +typedef union sh_md_dqlp_mmr_xuerr2_u { + mmr_t sh_md_dqlp_mmr_xuerr2_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp2 : 36; + } sh_md_dqlp_mmr_xuerr2_s; +} sh_md_dqlp_mmr_xuerr2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XPERR" */ +/* protocol error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_xperr_u { + mmr_t sh_md_dqlp_mmr_xperr_regval; + struct { + mmr_t dir : 26; + mmr_t cmd : 8; + mmr_t src : 14; + mmr_t prige : 1; + mmr_t priv : 1; + mmr_t cor : 1; + mmr_t unc : 1; + mmr_t mybit : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 1; + } sh_md_dqlp_mmr_xperr_s; +} sh_md_dqlp_mmr_xperr_u_t; +#else +typedef union sh_md_dqlp_mmr_xperr_u { + mmr_t sh_md_dqlp_mmr_xperr_regval; + struct { + mmr_t reserved_0 : 1; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t mybit : 8; + mmr_t unc : 1; + mmr_t cor : 1; + mmr_t priv : 1; + mmr_t prige : 1; + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t dir : 26; + } sh_md_dqlp_mmr_xperr_s; +} sh_md_dqlp_mmr_xperr_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YCERR1" */ +/* correctable dir ecc group 1 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_ycerr1_u { + mmr_t sh_md_dqlp_mmr_ycerr1_regval; + struct { + mmr_t grp1 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 25; + } sh_md_dqlp_mmr_ycerr1_s; +} sh_md_dqlp_mmr_ycerr1_u_t; +#else +typedef union sh_md_dqlp_mmr_ycerr1_u { + mmr_t sh_md_dqlp_mmr_ycerr1_regval; + struct { + mmr_t reserved_0 : 25; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp1 : 36; + } sh_md_dqlp_mmr_ycerr1_s; +} sh_md_dqlp_mmr_ycerr1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YCERR2" */ +/* correctable dir ecc group 2 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_ycerr2_u { + mmr_t sh_md_dqlp_mmr_ycerr2_regval; + struct { + mmr_t grp2 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 26; + } sh_md_dqlp_mmr_ycerr2_s; +} sh_md_dqlp_mmr_ycerr2_u_t; +#else +typedef union sh_md_dqlp_mmr_ycerr2_u { + mmr_t sh_md_dqlp_mmr_ycerr2_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp2 : 36; + } sh_md_dqlp_mmr_ycerr2_s; +} sh_md_dqlp_mmr_ycerr2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YUERR1" */ +/* uncorrectable dir ecc group 1 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_yuerr1_u { + mmr_t sh_md_dqlp_mmr_yuerr1_regval; + struct { + mmr_t grp1 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 25; + } sh_md_dqlp_mmr_yuerr1_s; +} sh_md_dqlp_mmr_yuerr1_u_t; +#else +typedef union sh_md_dqlp_mmr_yuerr1_u { + mmr_t sh_md_dqlp_mmr_yuerr1_regval; + struct { + mmr_t reserved_0 : 25; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp1 : 36; + } sh_md_dqlp_mmr_yuerr1_s; +} sh_md_dqlp_mmr_yuerr1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YUERR2" */ +/* uncorrectable dir ecc group 2 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_yuerr2_u { + mmr_t sh_md_dqlp_mmr_yuerr2_regval; + struct { + mmr_t grp2 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 26; + } sh_md_dqlp_mmr_yuerr2_s; +} sh_md_dqlp_mmr_yuerr2_u_t; +#else +typedef union sh_md_dqlp_mmr_yuerr2_u { + mmr_t sh_md_dqlp_mmr_yuerr2_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp2 : 36; + } sh_md_dqlp_mmr_yuerr2_s; +} sh_md_dqlp_mmr_yuerr2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YPERR" */ +/* protocol error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_yperr_u { + mmr_t sh_md_dqlp_mmr_yperr_regval; + struct { + mmr_t dir : 26; + mmr_t cmd : 8; + mmr_t src : 14; + mmr_t prige : 1; + mmr_t priv : 1; + mmr_t cor : 1; + mmr_t unc : 1; + mmr_t mybit : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 1; + } sh_md_dqlp_mmr_yperr_s; +} sh_md_dqlp_mmr_yperr_u_t; +#else +typedef union sh_md_dqlp_mmr_yperr_u { + mmr_t sh_md_dqlp_mmr_yperr_regval; + struct { + mmr_t reserved_0 : 1; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t mybit : 8; + mmr_t unc : 1; + mmr_t cor : 1; + mmr_t priv : 1; + mmr_t prige : 1; + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t dir : 26; + } sh_md_dqlp_mmr_yperr_s; +} sh_md_dqlp_mmr_yperr_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_CMDTRIG" */ +/* cmd triggers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_cmdtrig_u { + mmr_t sh_md_dqlp_mmr_dir_cmdtrig_regval; + struct { + mmr_t cmd0 : 8; + mmr_t cmd1 : 8; + mmr_t cmd2 : 8; + mmr_t cmd3 : 8; + mmr_t reserved_0 : 32; + } sh_md_dqlp_mmr_dir_cmdtrig_s; +} sh_md_dqlp_mmr_dir_cmdtrig_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_cmdtrig_u { + mmr_t sh_md_dqlp_mmr_dir_cmdtrig_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t cmd3 : 8; + mmr_t cmd2 : 8; + mmr_t cmd1 : 8; + mmr_t cmd0 : 8; + } sh_md_dqlp_mmr_dir_cmdtrig_s; +} sh_md_dqlp_mmr_dir_cmdtrig_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_TBLTRIG" */ +/* dir table trigger */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_tbltrig_u { + mmr_t sh_md_dqlp_mmr_dir_tbltrig_regval; + struct { + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t acc : 2; + mmr_t prige : 1; + mmr_t dirst : 9; + mmr_t mybit : 8; + mmr_t reserved_0 : 22; + } sh_md_dqlp_mmr_dir_tbltrig_s; +} sh_md_dqlp_mmr_dir_tbltrig_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_tbltrig_u { + mmr_t sh_md_dqlp_mmr_dir_tbltrig_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t mybit : 8; + mmr_t dirst : 9; + mmr_t prige : 1; + mmr_t acc : 2; + mmr_t cmd : 8; + mmr_t src : 14; + } sh_md_dqlp_mmr_dir_tbltrig_s; +} sh_md_dqlp_mmr_dir_tbltrig_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_TBLMASK" */ +/* dir table trigger mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_dir_tblmask_u { + mmr_t sh_md_dqlp_mmr_dir_tblmask_regval; + struct { + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t acc : 2; + mmr_t prige : 1; + mmr_t dirst : 9; + mmr_t mybit : 8; + mmr_t reserved_0 : 22; + } sh_md_dqlp_mmr_dir_tblmask_s; +} sh_md_dqlp_mmr_dir_tblmask_u_t; +#else +typedef union sh_md_dqlp_mmr_dir_tblmask_u { + mmr_t sh_md_dqlp_mmr_dir_tblmask_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t mybit : 8; + mmr_t dirst : 9; + mmr_t prige : 1; + mmr_t acc : 2; + mmr_t cmd : 8; + mmr_t src : 14; + } sh_md_dqlp_mmr_dir_tblmask_s; +} sh_md_dqlp_mmr_dir_tblmask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_xbist_h_u { + mmr_t sh_md_dqlp_mmr_xbist_h_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t arm : 1; + mmr_t reserved_1 : 21; + } sh_md_dqlp_mmr_xbist_h_s; +} sh_md_dqlp_mmr_xbist_h_u_t; +#else +typedef union sh_md_dqlp_mmr_xbist_h_u { + mmr_t sh_md_dqlp_mmr_xbist_h_regval; + struct { + mmr_t reserved_1 : 21; + mmr_t arm : 1; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqlp_mmr_xbist_h_s; +} sh_md_dqlp_mmr_xbist_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_xbist_l_u { + mmr_t sh_md_dqlp_mmr_xbist_l_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t reserved_1 : 22; + } sh_md_dqlp_mmr_xbist_l_s; +} sh_md_dqlp_mmr_xbist_l_u_t; +#else +typedef union sh_md_dqlp_mmr_xbist_l_u { + mmr_t sh_md_dqlp_mmr_xbist_l_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqlp_mmr_xbist_l_s; +} sh_md_dqlp_mmr_xbist_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_xbist_err_h_u { + mmr_t sh_md_dqlp_mmr_xbist_err_h_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_1 : 22; + } sh_md_dqlp_mmr_xbist_err_h_s; +} sh_md_dqlp_mmr_xbist_err_h_u_t; +#else +typedef union sh_md_dqlp_mmr_xbist_err_h_u { + mmr_t sh_md_dqlp_mmr_xbist_err_h_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqlp_mmr_xbist_err_h_s; +} sh_md_dqlp_mmr_xbist_err_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_XBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_xbist_err_l_u { + mmr_t sh_md_dqlp_mmr_xbist_err_l_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_1 : 22; + } sh_md_dqlp_mmr_xbist_err_l_s; +} sh_md_dqlp_mmr_xbist_err_l_u_t; +#else +typedef union sh_md_dqlp_mmr_xbist_err_l_u { + mmr_t sh_md_dqlp_mmr_xbist_err_l_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqlp_mmr_xbist_err_l_s; +} sh_md_dqlp_mmr_xbist_err_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_ybist_h_u { + mmr_t sh_md_dqlp_mmr_ybist_h_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t arm : 1; + mmr_t reserved_1 : 21; + } sh_md_dqlp_mmr_ybist_h_s; +} sh_md_dqlp_mmr_ybist_h_u_t; +#else +typedef union sh_md_dqlp_mmr_ybist_h_u { + mmr_t sh_md_dqlp_mmr_ybist_h_regval; + struct { + mmr_t reserved_1 : 21; + mmr_t arm : 1; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqlp_mmr_ybist_h_s; +} sh_md_dqlp_mmr_ybist_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_ybist_l_u { + mmr_t sh_md_dqlp_mmr_ybist_l_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t reserved_1 : 22; + } sh_md_dqlp_mmr_ybist_l_s; +} sh_md_dqlp_mmr_ybist_l_u_t; +#else +typedef union sh_md_dqlp_mmr_ybist_l_u { + mmr_t sh_md_dqlp_mmr_ybist_l_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqlp_mmr_ybist_l_s; +} sh_md_dqlp_mmr_ybist_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_ybist_err_h_u { + mmr_t sh_md_dqlp_mmr_ybist_err_h_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_1 : 22; + } sh_md_dqlp_mmr_ybist_err_h_s; +} sh_md_dqlp_mmr_ybist_err_h_u_t; +#else +typedef union sh_md_dqlp_mmr_ybist_err_h_u { + mmr_t sh_md_dqlp_mmr_ybist_err_h_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqlp_mmr_ybist_err_h_s; +} sh_md_dqlp_mmr_ybist_err_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_YBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqlp_mmr_ybist_err_l_u { + mmr_t sh_md_dqlp_mmr_ybist_err_l_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_1 : 22; + } sh_md_dqlp_mmr_ybist_err_l_s; +} sh_md_dqlp_mmr_ybist_err_l_u_t; +#else +typedef union sh_md_dqlp_mmr_ybist_err_l_u { + mmr_t sh_md_dqlp_mmr_ybist_err_l_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqlp_mmr_ybist_err_l_s; +} sh_md_dqlp_mmr_ybist_err_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_XBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqls_mmr_xbist_h_u { + mmr_t sh_md_dqls_mmr_xbist_h_regval; + struct { + mmr_t pat : 40; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 21; + } sh_md_dqls_mmr_xbist_h_s; +} sh_md_dqls_mmr_xbist_h_u_t; +#else +typedef union sh_md_dqls_mmr_xbist_h_u { + mmr_t sh_md_dqls_mmr_xbist_h_regval; + struct { + mmr_t reserved_0 : 21; + mmr_t arm : 1; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t pat : 40; + } sh_md_dqls_mmr_xbist_h_s; +} sh_md_dqls_mmr_xbist_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_XBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqls_mmr_xbist_l_u { + mmr_t sh_md_dqls_mmr_xbist_l_regval; + struct { + mmr_t pat : 40; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t reserved_0 : 22; + } sh_md_dqls_mmr_xbist_l_s; +} sh_md_dqls_mmr_xbist_l_u_t; +#else +typedef union sh_md_dqls_mmr_xbist_l_u { + mmr_t sh_md_dqls_mmr_xbist_l_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t pat : 40; + } sh_md_dqls_mmr_xbist_l_s; +} sh_md_dqls_mmr_xbist_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_XBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqls_mmr_xbist_err_h_u { + mmr_t sh_md_dqls_mmr_xbist_err_h_regval; + struct { + mmr_t pat : 40; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 22; + } sh_md_dqls_mmr_xbist_err_h_s; +} sh_md_dqls_mmr_xbist_err_h_u_t; +#else +typedef union sh_md_dqls_mmr_xbist_err_h_u { + mmr_t sh_md_dqls_mmr_xbist_err_h_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t pat : 40; + } sh_md_dqls_mmr_xbist_err_h_s; +} sh_md_dqls_mmr_xbist_err_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_XBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqls_mmr_xbist_err_l_u { + mmr_t sh_md_dqls_mmr_xbist_err_l_regval; + struct { + mmr_t pat : 40; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 22; + } sh_md_dqls_mmr_xbist_err_l_s; +} sh_md_dqls_mmr_xbist_err_l_u_t; +#else +typedef union sh_md_dqls_mmr_xbist_err_l_u { + mmr_t sh_md_dqls_mmr_xbist_err_l_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t pat : 40; + } sh_md_dqls_mmr_xbist_err_l_s; +} sh_md_dqls_mmr_xbist_err_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_YBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqls_mmr_ybist_h_u { + mmr_t sh_md_dqls_mmr_ybist_h_regval; + struct { + mmr_t pat : 40; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 21; + } sh_md_dqls_mmr_ybist_h_s; +} sh_md_dqls_mmr_ybist_h_u_t; +#else +typedef union sh_md_dqls_mmr_ybist_h_u { + mmr_t sh_md_dqls_mmr_ybist_h_regval; + struct { + mmr_t reserved_0 : 21; + mmr_t arm : 1; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t pat : 40; + } sh_md_dqls_mmr_ybist_h_s; +} sh_md_dqls_mmr_ybist_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_YBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqls_mmr_ybist_l_u { + mmr_t sh_md_dqls_mmr_ybist_l_regval; + struct { + mmr_t pat : 40; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t reserved_0 : 22; + } sh_md_dqls_mmr_ybist_l_s; +} sh_md_dqls_mmr_ybist_l_u_t; +#else +typedef union sh_md_dqls_mmr_ybist_l_u { + mmr_t sh_md_dqls_mmr_ybist_l_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t pat : 40; + } sh_md_dqls_mmr_ybist_l_s; +} sh_md_dqls_mmr_ybist_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_YBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqls_mmr_ybist_err_h_u { + mmr_t sh_md_dqls_mmr_ybist_err_h_regval; + struct { + mmr_t pat : 40; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 22; + } sh_md_dqls_mmr_ybist_err_h_s; +} sh_md_dqls_mmr_ybist_err_h_u_t; +#else +typedef union sh_md_dqls_mmr_ybist_err_h_u { + mmr_t sh_md_dqls_mmr_ybist_err_h_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t pat : 40; + } sh_md_dqls_mmr_ybist_err_h_s; +} sh_md_dqls_mmr_ybist_err_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_YBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqls_mmr_ybist_err_l_u { + mmr_t sh_md_dqls_mmr_ybist_err_l_regval; + struct { + mmr_t pat : 40; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 22; + } sh_md_dqls_mmr_ybist_err_l_s; +} sh_md_dqls_mmr_ybist_err_l_u_t; +#else +typedef union sh_md_dqls_mmr_ybist_err_l_u { + mmr_t sh_md_dqls_mmr_ybist_err_l_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t pat : 40; + } sh_md_dqls_mmr_ybist_err_l_s; +} sh_md_dqls_mmr_ybist_err_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_JNR_DEBUG" */ +/* joiner/fct debug configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqls_mmr_jnr_debug_u { + mmr_t sh_md_dqls_mmr_jnr_debug_regval; + struct { + mmr_t px : 1; + mmr_t rw : 1; + mmr_t reserved_0 : 62; + } sh_md_dqls_mmr_jnr_debug_s; +} sh_md_dqls_mmr_jnr_debug_u_t; +#else +typedef union sh_md_dqls_mmr_jnr_debug_u { + mmr_t sh_md_dqls_mmr_jnr_debug_regval; + struct { + mmr_t reserved_0 : 62; + mmr_t rw : 1; + mmr_t px : 1; + } sh_md_dqls_mmr_jnr_debug_s; +} sh_md_dqls_mmr_jnr_debug_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQLS_MMR_XAMOPW_ERR" */ +/* amo/partial rmw ecc error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqls_mmr_xamopw_err_u { + mmr_t sh_md_dqls_mmr_xamopw_err_regval; + struct { + mmr_t ssyn : 8; + mmr_t scor : 1; + mmr_t sunc : 1; + mmr_t reserved_0 : 6; + mmr_t rsyn : 8; + mmr_t rcor : 1; + mmr_t runc : 1; + mmr_t reserved_1 : 6; + mmr_t arm : 1; + mmr_t reserved_2 : 31; + } sh_md_dqls_mmr_xamopw_err_s; +} sh_md_dqls_mmr_xamopw_err_u_t; +#else +typedef union sh_md_dqls_mmr_xamopw_err_u { + mmr_t sh_md_dqls_mmr_xamopw_err_regval; + struct { + mmr_t reserved_2 : 31; + mmr_t arm : 1; + mmr_t reserved_1 : 6; + mmr_t runc : 1; + mmr_t rcor : 1; + mmr_t rsyn : 8; + mmr_t reserved_0 : 6; + mmr_t sunc : 1; + mmr_t scor : 1; + mmr_t ssyn : 8; + } sh_md_dqls_mmr_xamopw_err_s; +} sh_md_dqls_mmr_xamopw_err_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_CONFIG" */ +/* DQ directory config register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_config_u { + mmr_t sh_md_dqrp_mmr_dir_config_regval; + struct { + mmr_t sys_size : 3; + mmr_t en_direcc : 1; + mmr_t en_dirpois : 1; + mmr_t reserved_0 : 59; + } sh_md_dqrp_mmr_dir_config_s; +} sh_md_dqrp_mmr_dir_config_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_config_u { + mmr_t sh_md_dqrp_mmr_dir_config_regval; + struct { + mmr_t reserved_0 : 59; + mmr_t en_dirpois : 1; + mmr_t en_direcc : 1; + mmr_t sys_size : 3; + } sh_md_dqrp_mmr_dir_config_s; +} sh_md_dqrp_mmr_dir_config_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC0" */ +/* node [63:0] presence bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_presvec0_u { + mmr_t sh_md_dqrp_mmr_dir_presvec0_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_presvec0_s; +} sh_md_dqrp_mmr_dir_presvec0_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_presvec0_u { + mmr_t sh_md_dqrp_mmr_dir_presvec0_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_presvec0_s; +} sh_md_dqrp_mmr_dir_presvec0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC1" */ +/* node [127:64] presence bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_presvec1_u { + mmr_t sh_md_dqrp_mmr_dir_presvec1_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_presvec1_s; +} sh_md_dqrp_mmr_dir_presvec1_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_presvec1_u { + mmr_t sh_md_dqrp_mmr_dir_presvec1_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_presvec1_s; +} sh_md_dqrp_mmr_dir_presvec1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC2" */ +/* node [191:128] presence bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_presvec2_u { + mmr_t sh_md_dqrp_mmr_dir_presvec2_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_presvec2_s; +} sh_md_dqrp_mmr_dir_presvec2_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_presvec2_u { + mmr_t sh_md_dqrp_mmr_dir_presvec2_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_presvec2_s; +} sh_md_dqrp_mmr_dir_presvec2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRESVEC3" */ +/* node [255:192] presence bits */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_presvec3_u { + mmr_t sh_md_dqrp_mmr_dir_presvec3_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_presvec3_s; +} sh_md_dqrp_mmr_dir_presvec3_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_presvec3_u { + mmr_t sh_md_dqrp_mmr_dir_presvec3_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_presvec3_s; +} sh_md_dqrp_mmr_dir_presvec3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC0" */ +/* local vector for acc=0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_locvec0_u { + mmr_t sh_md_dqrp_mmr_dir_locvec0_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec0_s; +} sh_md_dqrp_mmr_dir_locvec0_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_locvec0_u { + mmr_t sh_md_dqrp_mmr_dir_locvec0_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec0_s; +} sh_md_dqrp_mmr_dir_locvec0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC1" */ +/* local vector for acc=1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_locvec1_u { + mmr_t sh_md_dqrp_mmr_dir_locvec1_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec1_s; +} sh_md_dqrp_mmr_dir_locvec1_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_locvec1_u { + mmr_t sh_md_dqrp_mmr_dir_locvec1_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec1_s; +} sh_md_dqrp_mmr_dir_locvec1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC2" */ +/* local vector for acc=2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_locvec2_u { + mmr_t sh_md_dqrp_mmr_dir_locvec2_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec2_s; +} sh_md_dqrp_mmr_dir_locvec2_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_locvec2_u { + mmr_t sh_md_dqrp_mmr_dir_locvec2_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec2_s; +} sh_md_dqrp_mmr_dir_locvec2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC3" */ +/* local vector for acc=3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_locvec3_u { + mmr_t sh_md_dqrp_mmr_dir_locvec3_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec3_s; +} sh_md_dqrp_mmr_dir_locvec3_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_locvec3_u { + mmr_t sh_md_dqrp_mmr_dir_locvec3_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec3_s; +} sh_md_dqrp_mmr_dir_locvec3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC4" */ +/* local vector for acc=4 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_locvec4_u { + mmr_t sh_md_dqrp_mmr_dir_locvec4_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec4_s; +} sh_md_dqrp_mmr_dir_locvec4_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_locvec4_u { + mmr_t sh_md_dqrp_mmr_dir_locvec4_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec4_s; +} sh_md_dqrp_mmr_dir_locvec4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC5" */ +/* local vector for acc=5 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_locvec5_u { + mmr_t sh_md_dqrp_mmr_dir_locvec5_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec5_s; +} sh_md_dqrp_mmr_dir_locvec5_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_locvec5_u { + mmr_t sh_md_dqrp_mmr_dir_locvec5_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec5_s; +} sh_md_dqrp_mmr_dir_locvec5_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC6" */ +/* local vector for acc=6 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_locvec6_u { + mmr_t sh_md_dqrp_mmr_dir_locvec6_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec6_s; +} sh_md_dqrp_mmr_dir_locvec6_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_locvec6_u { + mmr_t sh_md_dqrp_mmr_dir_locvec6_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec6_s; +} sh_md_dqrp_mmr_dir_locvec6_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_LOCVEC7" */ +/* local vector for acc=7 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_locvec7_u { + mmr_t sh_md_dqrp_mmr_dir_locvec7_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec7_s; +} sh_md_dqrp_mmr_dir_locvec7_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_locvec7_u { + mmr_t sh_md_dqrp_mmr_dir_locvec7_regval; + struct { + mmr_t vec : 64; + } sh_md_dqrp_mmr_dir_locvec7_s; +} sh_md_dqrp_mmr_dir_locvec7_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ +/* privilege vector for acc=0 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_privec0_u { + mmr_t sh_md_dqrp_mmr_dir_privec0_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqrp_mmr_dir_privec0_s; +} sh_md_dqrp_mmr_dir_privec0_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_privec0_u { + mmr_t sh_md_dqrp_mmr_dir_privec0_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqrp_mmr_dir_privec0_s; +} sh_md_dqrp_mmr_dir_privec0_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC1" */ +/* privilege vector for acc=1 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_privec1_u { + mmr_t sh_md_dqrp_mmr_dir_privec1_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqrp_mmr_dir_privec1_s; +} sh_md_dqrp_mmr_dir_privec1_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_privec1_u { + mmr_t sh_md_dqrp_mmr_dir_privec1_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqrp_mmr_dir_privec1_s; +} sh_md_dqrp_mmr_dir_privec1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC2" */ +/* privilege vector for acc=2 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_privec2_u { + mmr_t sh_md_dqrp_mmr_dir_privec2_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqrp_mmr_dir_privec2_s; +} sh_md_dqrp_mmr_dir_privec2_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_privec2_u { + mmr_t sh_md_dqrp_mmr_dir_privec2_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqrp_mmr_dir_privec2_s; +} sh_md_dqrp_mmr_dir_privec2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC3" */ +/* privilege vector for acc=3 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_privec3_u { + mmr_t sh_md_dqrp_mmr_dir_privec3_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqrp_mmr_dir_privec3_s; +} sh_md_dqrp_mmr_dir_privec3_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_privec3_u { + mmr_t sh_md_dqrp_mmr_dir_privec3_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqrp_mmr_dir_privec3_s; +} sh_md_dqrp_mmr_dir_privec3_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC4" */ +/* privilege vector for acc=4 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_privec4_u { + mmr_t sh_md_dqrp_mmr_dir_privec4_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqrp_mmr_dir_privec4_s; +} sh_md_dqrp_mmr_dir_privec4_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_privec4_u { + mmr_t sh_md_dqrp_mmr_dir_privec4_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqrp_mmr_dir_privec4_s; +} sh_md_dqrp_mmr_dir_privec4_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC5" */ +/* privilege vector for acc=5 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_privec5_u { + mmr_t sh_md_dqrp_mmr_dir_privec5_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqrp_mmr_dir_privec5_s; +} sh_md_dqrp_mmr_dir_privec5_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_privec5_u { + mmr_t sh_md_dqrp_mmr_dir_privec5_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqrp_mmr_dir_privec5_s; +} sh_md_dqrp_mmr_dir_privec5_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC6" */ +/* privilege vector for acc=6 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_privec6_u { + mmr_t sh_md_dqrp_mmr_dir_privec6_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqrp_mmr_dir_privec6_s; +} sh_md_dqrp_mmr_dir_privec6_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_privec6_u { + mmr_t sh_md_dqrp_mmr_dir_privec6_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqrp_mmr_dir_privec6_s; +} sh_md_dqrp_mmr_dir_privec6_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC7" */ +/* privilege vector for acc=7 */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_privec7_u { + mmr_t sh_md_dqrp_mmr_dir_privec7_regval; + struct { + mmr_t in : 14; + mmr_t out : 14; + mmr_t reserved_0 : 36; + } sh_md_dqrp_mmr_dir_privec7_s; +} sh_md_dqrp_mmr_dir_privec7_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_privec7_u { + mmr_t sh_md_dqrp_mmr_dir_privec7_regval; + struct { + mmr_t reserved_0 : 36; + mmr_t out : 14; + mmr_t in : 14; + } sh_md_dqrp_mmr_dir_privec7_s; +} sh_md_dqrp_mmr_dir_privec7_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_TIMER" */ +/* MD SXRO timer */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_timer_u { + mmr_t sh_md_dqrp_mmr_dir_timer_regval; + struct { + mmr_t timer_div : 12; + mmr_t timer_en : 1; + mmr_t timer_cur : 9; + mmr_t reserved_0 : 42; + } sh_md_dqrp_mmr_dir_timer_s; +} sh_md_dqrp_mmr_dir_timer_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_timer_u { + mmr_t sh_md_dqrp_mmr_dir_timer_regval; + struct { + mmr_t reserved_0 : 42; + mmr_t timer_cur : 9; + mmr_t timer_en : 1; + mmr_t timer_div : 12; + } sh_md_dqrp_mmr_dir_timer_s; +} sh_md_dqrp_mmr_dir_timer_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY" */ +/* directory pio write data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_piowd_dir_entry_u { + mmr_t sh_md_dqrp_mmr_piowd_dir_entry_regval; + struct { + mmr_t dira : 26; + mmr_t dirb : 26; + mmr_t pri : 3; + mmr_t acc : 3; + mmr_t reserved_0 : 6; + } sh_md_dqrp_mmr_piowd_dir_entry_s; +} sh_md_dqrp_mmr_piowd_dir_entry_u_t; +#else +typedef union sh_md_dqrp_mmr_piowd_dir_entry_u { + mmr_t sh_md_dqrp_mmr_piowd_dir_entry_regval; + struct { + mmr_t reserved_0 : 6; + mmr_t acc : 3; + mmr_t pri : 3; + mmr_t dirb : 26; + mmr_t dira : 26; + } sh_md_dqrp_mmr_piowd_dir_entry_s; +} sh_md_dqrp_mmr_piowd_dir_entry_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC" */ +/* directory ecc register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u { + mmr_t sh_md_dqrp_mmr_piowd_dir_ecc_regval; + struct { + mmr_t ecca : 7; + mmr_t eccb : 7; + mmr_t reserved_0 : 50; + } sh_md_dqrp_mmr_piowd_dir_ecc_s; +} sh_md_dqrp_mmr_piowd_dir_ecc_u_t; +#else +typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u { + mmr_t sh_md_dqrp_mmr_piowd_dir_ecc_regval; + struct { + mmr_t reserved_0 : 50; + mmr_t eccb : 7; + mmr_t ecca : 7; + } sh_md_dqrp_mmr_piowd_dir_ecc_s; +} sh_md_dqrp_mmr_piowd_dir_ecc_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY" */ +/* x directory pio read data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u { + mmr_t sh_md_dqrp_mmr_xpiord_xdir_entry_regval; + struct { + mmr_t dira : 26; + mmr_t dirb : 26; + mmr_t pri : 3; + mmr_t acc : 3; + mmr_t cor : 1; + mmr_t unc : 1; + mmr_t reserved_0 : 4; + } sh_md_dqrp_mmr_xpiord_xdir_entry_s; +} sh_md_dqrp_mmr_xpiord_xdir_entry_u_t; +#else +typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u { + mmr_t sh_md_dqrp_mmr_xpiord_xdir_entry_regval; + struct { + mmr_t reserved_0 : 4; + mmr_t unc : 1; + mmr_t cor : 1; + mmr_t acc : 3; + mmr_t pri : 3; + mmr_t dirb : 26; + mmr_t dira : 26; + } sh_md_dqrp_mmr_xpiord_xdir_entry_s; +} sh_md_dqrp_mmr_xpiord_xdir_entry_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC" */ +/* x directory ecc */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u { + mmr_t sh_md_dqrp_mmr_xpiord_xdir_ecc_regval; + struct { + mmr_t ecca : 7; + mmr_t eccb : 7; + mmr_t reserved_0 : 50; + } sh_md_dqrp_mmr_xpiord_xdir_ecc_s; +} sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t; +#else +typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u { + mmr_t sh_md_dqrp_mmr_xpiord_xdir_ecc_regval; + struct { + mmr_t reserved_0 : 50; + mmr_t eccb : 7; + mmr_t ecca : 7; + } sh_md_dqrp_mmr_xpiord_xdir_ecc_s; +} sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY" */ +/* y directory pio read data */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u { + mmr_t sh_md_dqrp_mmr_ypiord_ydir_entry_regval; + struct { + mmr_t dira : 26; + mmr_t dirb : 26; + mmr_t pri : 3; + mmr_t acc : 3; + mmr_t cor : 1; + mmr_t unc : 1; + mmr_t reserved_0 : 4; + } sh_md_dqrp_mmr_ypiord_ydir_entry_s; +} sh_md_dqrp_mmr_ypiord_ydir_entry_u_t; +#else +typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u { + mmr_t sh_md_dqrp_mmr_ypiord_ydir_entry_regval; + struct { + mmr_t reserved_0 : 4; + mmr_t unc : 1; + mmr_t cor : 1; + mmr_t acc : 3; + mmr_t pri : 3; + mmr_t dirb : 26; + mmr_t dira : 26; + } sh_md_dqrp_mmr_ypiord_ydir_entry_s; +} sh_md_dqrp_mmr_ypiord_ydir_entry_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC" */ +/* y directory ecc */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u { + mmr_t sh_md_dqrp_mmr_ypiord_ydir_ecc_regval; + struct { + mmr_t ecca : 7; + mmr_t eccb : 7; + mmr_t reserved_0 : 50; + } sh_md_dqrp_mmr_ypiord_ydir_ecc_s; +} sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t; +#else +typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u { + mmr_t sh_md_dqrp_mmr_ypiord_ydir_ecc_regval; + struct { + mmr_t reserved_0 : 50; + mmr_t eccb : 7; + mmr_t ecca : 7; + } sh_md_dqrp_mmr_ypiord_ydir_ecc_s; +} sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XCERR1" */ +/* correctable dir ecc group 1 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_xcerr1_u { + mmr_t sh_md_dqrp_mmr_xcerr1_regval; + struct { + mmr_t grp1 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 25; + } sh_md_dqrp_mmr_xcerr1_s; +} sh_md_dqrp_mmr_xcerr1_u_t; +#else +typedef union sh_md_dqrp_mmr_xcerr1_u { + mmr_t sh_md_dqrp_mmr_xcerr1_regval; + struct { + mmr_t reserved_0 : 25; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp1 : 36; + } sh_md_dqrp_mmr_xcerr1_s; +} sh_md_dqrp_mmr_xcerr1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XCERR2" */ +/* correctable dir ecc group 2 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_xcerr2_u { + mmr_t sh_md_dqrp_mmr_xcerr2_regval; + struct { + mmr_t grp2 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 26; + } sh_md_dqrp_mmr_xcerr2_s; +} sh_md_dqrp_mmr_xcerr2_u_t; +#else +typedef union sh_md_dqrp_mmr_xcerr2_u { + mmr_t sh_md_dqrp_mmr_xcerr2_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp2 : 36; + } sh_md_dqrp_mmr_xcerr2_s; +} sh_md_dqrp_mmr_xcerr2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XUERR1" */ +/* uncorrectable dir ecc group 1 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_xuerr1_u { + mmr_t sh_md_dqrp_mmr_xuerr1_regval; + struct { + mmr_t grp1 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 25; + } sh_md_dqrp_mmr_xuerr1_s; +} sh_md_dqrp_mmr_xuerr1_u_t; +#else +typedef union sh_md_dqrp_mmr_xuerr1_u { + mmr_t sh_md_dqrp_mmr_xuerr1_regval; + struct { + mmr_t reserved_0 : 25; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp1 : 36; + } sh_md_dqrp_mmr_xuerr1_s; +} sh_md_dqrp_mmr_xuerr1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XUERR2" */ +/* uncorrectable dir ecc group 2 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_xuerr2_u { + mmr_t sh_md_dqrp_mmr_xuerr2_regval; + struct { + mmr_t grp2 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 26; + } sh_md_dqrp_mmr_xuerr2_s; +} sh_md_dqrp_mmr_xuerr2_u_t; +#else +typedef union sh_md_dqrp_mmr_xuerr2_u { + mmr_t sh_md_dqrp_mmr_xuerr2_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp2 : 36; + } sh_md_dqrp_mmr_xuerr2_s; +} sh_md_dqrp_mmr_xuerr2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XPERR" */ +/* protocol error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_xperr_u { + mmr_t sh_md_dqrp_mmr_xperr_regval; + struct { + mmr_t dir : 26; + mmr_t cmd : 8; + mmr_t src : 14; + mmr_t prige : 1; + mmr_t priv : 1; + mmr_t cor : 1; + mmr_t unc : 1; + mmr_t mybit : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 1; + } sh_md_dqrp_mmr_xperr_s; +} sh_md_dqrp_mmr_xperr_u_t; +#else +typedef union sh_md_dqrp_mmr_xperr_u { + mmr_t sh_md_dqrp_mmr_xperr_regval; + struct { + mmr_t reserved_0 : 1; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t mybit : 8; + mmr_t unc : 1; + mmr_t cor : 1; + mmr_t priv : 1; + mmr_t prige : 1; + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t dir : 26; + } sh_md_dqrp_mmr_xperr_s; +} sh_md_dqrp_mmr_xperr_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YCERR1" */ +/* correctable dir ecc group 1 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_ycerr1_u { + mmr_t sh_md_dqrp_mmr_ycerr1_regval; + struct { + mmr_t grp1 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 25; + } sh_md_dqrp_mmr_ycerr1_s; +} sh_md_dqrp_mmr_ycerr1_u_t; +#else +typedef union sh_md_dqrp_mmr_ycerr1_u { + mmr_t sh_md_dqrp_mmr_ycerr1_regval; + struct { + mmr_t reserved_0 : 25; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp1 : 36; + } sh_md_dqrp_mmr_ycerr1_s; +} sh_md_dqrp_mmr_ycerr1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YCERR2" */ +/* correctable dir ecc group 2 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_ycerr2_u { + mmr_t sh_md_dqrp_mmr_ycerr2_regval; + struct { + mmr_t grp2 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 26; + } sh_md_dqrp_mmr_ycerr2_s; +} sh_md_dqrp_mmr_ycerr2_u_t; +#else +typedef union sh_md_dqrp_mmr_ycerr2_u { + mmr_t sh_md_dqrp_mmr_ycerr2_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp2 : 36; + } sh_md_dqrp_mmr_ycerr2_s; +} sh_md_dqrp_mmr_ycerr2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YUERR1" */ +/* uncorrectable dir ecc group 1 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_yuerr1_u { + mmr_t sh_md_dqrp_mmr_yuerr1_regval; + struct { + mmr_t grp1 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 25; + } sh_md_dqrp_mmr_yuerr1_s; +} sh_md_dqrp_mmr_yuerr1_u_t; +#else +typedef union sh_md_dqrp_mmr_yuerr1_u { + mmr_t sh_md_dqrp_mmr_yuerr1_regval; + struct { + mmr_t reserved_0 : 25; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp1 : 36; + } sh_md_dqrp_mmr_yuerr1_s; +} sh_md_dqrp_mmr_yuerr1_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YUERR2" */ +/* uncorrectable dir ecc group 2 error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_yuerr2_u { + mmr_t sh_md_dqrp_mmr_yuerr2_regval; + struct { + mmr_t grp2 : 36; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 26; + } sh_md_dqrp_mmr_yuerr2_s; +} sh_md_dqrp_mmr_yuerr2_u_t; +#else +typedef union sh_md_dqrp_mmr_yuerr2_u { + mmr_t sh_md_dqrp_mmr_yuerr2_regval; + struct { + mmr_t reserved_0 : 26; + mmr_t more : 1; + mmr_t val : 1; + mmr_t grp2 : 36; + } sh_md_dqrp_mmr_yuerr2_s; +} sh_md_dqrp_mmr_yuerr2_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YPERR" */ +/* protocol error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_yperr_u { + mmr_t sh_md_dqrp_mmr_yperr_regval; + struct { + mmr_t dir : 26; + mmr_t cmd : 8; + mmr_t src : 14; + mmr_t prige : 1; + mmr_t priv : 1; + mmr_t cor : 1; + mmr_t unc : 1; + mmr_t mybit : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 1; + } sh_md_dqrp_mmr_yperr_s; +} sh_md_dqrp_mmr_yperr_u_t; +#else +typedef union sh_md_dqrp_mmr_yperr_u { + mmr_t sh_md_dqrp_mmr_yperr_regval; + struct { + mmr_t reserved_0 : 1; + mmr_t arm : 1; + mmr_t more : 1; + mmr_t val : 1; + mmr_t mybit : 8; + mmr_t unc : 1; + mmr_t cor : 1; + mmr_t priv : 1; + mmr_t prige : 1; + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t dir : 26; + } sh_md_dqrp_mmr_yperr_s; +} sh_md_dqrp_mmr_yperr_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_CMDTRIG" */ +/* cmd triggers */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_cmdtrig_u { + mmr_t sh_md_dqrp_mmr_dir_cmdtrig_regval; + struct { + mmr_t cmd0 : 8; + mmr_t cmd1 : 8; + mmr_t cmd2 : 8; + mmr_t cmd3 : 8; + mmr_t reserved_0 : 32; + } sh_md_dqrp_mmr_dir_cmdtrig_s; +} sh_md_dqrp_mmr_dir_cmdtrig_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_cmdtrig_u { + mmr_t sh_md_dqrp_mmr_dir_cmdtrig_regval; + struct { + mmr_t reserved_0 : 32; + mmr_t cmd3 : 8; + mmr_t cmd2 : 8; + mmr_t cmd1 : 8; + mmr_t cmd0 : 8; + } sh_md_dqrp_mmr_dir_cmdtrig_s; +} sh_md_dqrp_mmr_dir_cmdtrig_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_TBLTRIG" */ +/* dir table trigger */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_tbltrig_u { + mmr_t sh_md_dqrp_mmr_dir_tbltrig_regval; + struct { + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t acc : 2; + mmr_t prige : 1; + mmr_t dirst : 9; + mmr_t mybit : 8; + mmr_t reserved_0 : 22; + } sh_md_dqrp_mmr_dir_tbltrig_s; +} sh_md_dqrp_mmr_dir_tbltrig_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_tbltrig_u { + mmr_t sh_md_dqrp_mmr_dir_tbltrig_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t mybit : 8; + mmr_t dirst : 9; + mmr_t prige : 1; + mmr_t acc : 2; + mmr_t cmd : 8; + mmr_t src : 14; + } sh_md_dqrp_mmr_dir_tbltrig_s; +} sh_md_dqrp_mmr_dir_tbltrig_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_TBLMASK" */ +/* dir table trigger mask */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_dir_tblmask_u { + mmr_t sh_md_dqrp_mmr_dir_tblmask_regval; + struct { + mmr_t src : 14; + mmr_t cmd : 8; + mmr_t acc : 2; + mmr_t prige : 1; + mmr_t dirst : 9; + mmr_t mybit : 8; + mmr_t reserved_0 : 22; + } sh_md_dqrp_mmr_dir_tblmask_s; +} sh_md_dqrp_mmr_dir_tblmask_u_t; +#else +typedef union sh_md_dqrp_mmr_dir_tblmask_u { + mmr_t sh_md_dqrp_mmr_dir_tblmask_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t mybit : 8; + mmr_t dirst : 9; + mmr_t prige : 1; + mmr_t acc : 2; + mmr_t cmd : 8; + mmr_t src : 14; + } sh_md_dqrp_mmr_dir_tblmask_s; +} sh_md_dqrp_mmr_dir_tblmask_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_xbist_h_u { + mmr_t sh_md_dqrp_mmr_xbist_h_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t arm : 1; + mmr_t reserved_1 : 21; + } sh_md_dqrp_mmr_xbist_h_s; +} sh_md_dqrp_mmr_xbist_h_u_t; +#else +typedef union sh_md_dqrp_mmr_xbist_h_u { + mmr_t sh_md_dqrp_mmr_xbist_h_regval; + struct { + mmr_t reserved_1 : 21; + mmr_t arm : 1; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqrp_mmr_xbist_h_s; +} sh_md_dqrp_mmr_xbist_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_xbist_l_u { + mmr_t sh_md_dqrp_mmr_xbist_l_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t reserved_1 : 22; + } sh_md_dqrp_mmr_xbist_l_s; +} sh_md_dqrp_mmr_xbist_l_u_t; +#else +typedef union sh_md_dqrp_mmr_xbist_l_u { + mmr_t sh_md_dqrp_mmr_xbist_l_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqrp_mmr_xbist_l_s; +} sh_md_dqrp_mmr_xbist_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_xbist_err_h_u { + mmr_t sh_md_dqrp_mmr_xbist_err_h_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_1 : 22; + } sh_md_dqrp_mmr_xbist_err_h_s; +} sh_md_dqrp_mmr_xbist_err_h_u_t; +#else +typedef union sh_md_dqrp_mmr_xbist_err_h_u { + mmr_t sh_md_dqrp_mmr_xbist_err_h_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqrp_mmr_xbist_err_h_s; +} sh_md_dqrp_mmr_xbist_err_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_XBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_xbist_err_l_u { + mmr_t sh_md_dqrp_mmr_xbist_err_l_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_1 : 22; + } sh_md_dqrp_mmr_xbist_err_l_s; +} sh_md_dqrp_mmr_xbist_err_l_u_t; +#else +typedef union sh_md_dqrp_mmr_xbist_err_l_u { + mmr_t sh_md_dqrp_mmr_xbist_err_l_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqrp_mmr_xbist_err_l_s; +} sh_md_dqrp_mmr_xbist_err_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_ybist_h_u { + mmr_t sh_md_dqrp_mmr_ybist_h_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t arm : 1; + mmr_t reserved_1 : 21; + } sh_md_dqrp_mmr_ybist_h_s; +} sh_md_dqrp_mmr_ybist_h_u_t; +#else +typedef union sh_md_dqrp_mmr_ybist_h_u { + mmr_t sh_md_dqrp_mmr_ybist_h_regval; + struct { + mmr_t reserved_1 : 21; + mmr_t arm : 1; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqrp_mmr_ybist_h_s; +} sh_md_dqrp_mmr_ybist_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_ybist_l_u { + mmr_t sh_md_dqrp_mmr_ybist_l_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t reserved_1 : 22; + } sh_md_dqrp_mmr_ybist_l_s; +} sh_md_dqrp_mmr_ybist_l_u_t; +#else +typedef union sh_md_dqrp_mmr_ybist_l_u { + mmr_t sh_md_dqrp_mmr_ybist_l_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqrp_mmr_ybist_l_s; +} sh_md_dqrp_mmr_ybist_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_ybist_err_h_u { + mmr_t sh_md_dqrp_mmr_ybist_err_h_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_1 : 22; + } sh_md_dqrp_mmr_ybist_err_h_s; +} sh_md_dqrp_mmr_ybist_err_h_u_t; +#else +typedef union sh_md_dqrp_mmr_ybist_err_h_u { + mmr_t sh_md_dqrp_mmr_ybist_err_h_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqrp_mmr_ybist_err_h_s; +} sh_md_dqrp_mmr_ybist_err_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_YBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrp_mmr_ybist_err_l_u { + mmr_t sh_md_dqrp_mmr_ybist_err_l_regval; + struct { + mmr_t pat : 32; + mmr_t reserved_0 : 8; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_1 : 22; + } sh_md_dqrp_mmr_ybist_err_l_s; +} sh_md_dqrp_mmr_ybist_err_l_u_t; +#else +typedef union sh_md_dqrp_mmr_ybist_err_l_u { + mmr_t sh_md_dqrp_mmr_ybist_err_l_regval; + struct { + mmr_t reserved_1 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t reserved_0 : 8; + mmr_t pat : 32; + } sh_md_dqrp_mmr_ybist_err_l_s; +} sh_md_dqrp_mmr_ybist_err_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_XBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrs_mmr_xbist_h_u { + mmr_t sh_md_dqrs_mmr_xbist_h_regval; + struct { + mmr_t pat : 40; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 21; + } sh_md_dqrs_mmr_xbist_h_s; +} sh_md_dqrs_mmr_xbist_h_u_t; +#else +typedef union sh_md_dqrs_mmr_xbist_h_u { + mmr_t sh_md_dqrs_mmr_xbist_h_regval; + struct { + mmr_t reserved_0 : 21; + mmr_t arm : 1; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t pat : 40; + } sh_md_dqrs_mmr_xbist_h_s; +} sh_md_dqrs_mmr_xbist_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_XBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrs_mmr_xbist_l_u { + mmr_t sh_md_dqrs_mmr_xbist_l_regval; + struct { + mmr_t pat : 40; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t reserved_0 : 22; + } sh_md_dqrs_mmr_xbist_l_s; +} sh_md_dqrs_mmr_xbist_l_u_t; +#else +typedef union sh_md_dqrs_mmr_xbist_l_u { + mmr_t sh_md_dqrs_mmr_xbist_l_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t pat : 40; + } sh_md_dqrs_mmr_xbist_l_s; +} sh_md_dqrs_mmr_xbist_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_XBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrs_mmr_xbist_err_h_u { + mmr_t sh_md_dqrs_mmr_xbist_err_h_regval; + struct { + mmr_t pat : 40; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 22; + } sh_md_dqrs_mmr_xbist_err_h_s; +} sh_md_dqrs_mmr_xbist_err_h_u_t; +#else +typedef union sh_md_dqrs_mmr_xbist_err_h_u { + mmr_t sh_md_dqrs_mmr_xbist_err_h_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t pat : 40; + } sh_md_dqrs_mmr_xbist_err_h_s; +} sh_md_dqrs_mmr_xbist_err_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_XBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrs_mmr_xbist_err_l_u { + mmr_t sh_md_dqrs_mmr_xbist_err_l_regval; + struct { + mmr_t pat : 40; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 22; + } sh_md_dqrs_mmr_xbist_err_l_s; +} sh_md_dqrs_mmr_xbist_err_l_u_t; +#else +typedef union sh_md_dqrs_mmr_xbist_err_l_u { + mmr_t sh_md_dqrs_mmr_xbist_err_l_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t pat : 40; + } sh_md_dqrs_mmr_xbist_err_l_s; +} sh_md_dqrs_mmr_xbist_err_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_YBIST_H" */ +/* rising edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrs_mmr_ybist_h_u { + mmr_t sh_md_dqrs_mmr_ybist_h_regval; + struct { + mmr_t pat : 40; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t arm : 1; + mmr_t reserved_0 : 21; + } sh_md_dqrs_mmr_ybist_h_s; +} sh_md_dqrs_mmr_ybist_h_u_t; +#else +typedef union sh_md_dqrs_mmr_ybist_h_u { + mmr_t sh_md_dqrs_mmr_ybist_h_regval; + struct { + mmr_t reserved_0 : 21; + mmr_t arm : 1; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t pat : 40; + } sh_md_dqrs_mmr_ybist_h_s; +} sh_md_dqrs_mmr_ybist_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_YBIST_L" */ +/* falling edge bist/fill pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrs_mmr_ybist_l_u { + mmr_t sh_md_dqrs_mmr_ybist_l_regval; + struct { + mmr_t pat : 40; + mmr_t inv : 1; + mmr_t rot : 1; + mmr_t reserved_0 : 22; + } sh_md_dqrs_mmr_ybist_l_s; +} sh_md_dqrs_mmr_ybist_l_u_t; +#else +typedef union sh_md_dqrs_mmr_ybist_l_u { + mmr_t sh_md_dqrs_mmr_ybist_l_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t rot : 1; + mmr_t inv : 1; + mmr_t pat : 40; + } sh_md_dqrs_mmr_ybist_l_s; +} sh_md_dqrs_mmr_ybist_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_YBIST_ERR_H" */ +/* rising edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrs_mmr_ybist_err_h_u { + mmr_t sh_md_dqrs_mmr_ybist_err_h_regval; + struct { + mmr_t pat : 40; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 22; + } sh_md_dqrs_mmr_ybist_err_h_s; +} sh_md_dqrs_mmr_ybist_err_h_u_t; +#else +typedef union sh_md_dqrs_mmr_ybist_err_h_u { + mmr_t sh_md_dqrs_mmr_ybist_err_h_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t pat : 40; + } sh_md_dqrs_mmr_ybist_err_h_s; +} sh_md_dqrs_mmr_ybist_err_h_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_YBIST_ERR_L" */ +/* falling edge bist error pattern */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrs_mmr_ybist_err_l_u { + mmr_t sh_md_dqrs_mmr_ybist_err_l_regval; + struct { + mmr_t pat : 40; + mmr_t val : 1; + mmr_t more : 1; + mmr_t reserved_0 : 22; + } sh_md_dqrs_mmr_ybist_err_l_s; +} sh_md_dqrs_mmr_ybist_err_l_u_t; +#else +typedef union sh_md_dqrs_mmr_ybist_err_l_u { + mmr_t sh_md_dqrs_mmr_ybist_err_l_regval; + struct { + mmr_t reserved_0 : 22; + mmr_t more : 1; + mmr_t val : 1; + mmr_t pat : 40; + } sh_md_dqrs_mmr_ybist_err_l_s; +} sh_md_dqrs_mmr_ybist_err_l_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_JNR_DEBUG" */ +/* joiner/fct debug configuration */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrs_mmr_jnr_debug_u { + mmr_t sh_md_dqrs_mmr_jnr_debug_regval; + struct { + mmr_t px : 1; + mmr_t rw : 1; + mmr_t reserved_0 : 62; + } sh_md_dqrs_mmr_jnr_debug_s; +} sh_md_dqrs_mmr_jnr_debug_u_t; +#else +typedef union sh_md_dqrs_mmr_jnr_debug_u { + mmr_t sh_md_dqrs_mmr_jnr_debug_regval; + struct { + mmr_t reserved_0 : 62; + mmr_t rw : 1; + mmr_t px : 1; + } sh_md_dqrs_mmr_jnr_debug_s; +} sh_md_dqrs_mmr_jnr_debug_u_t; +#endif + +/* ==================================================================== */ +/* Register "SH_MD_DQRS_MMR_YAMOPW_ERR" */ +/* amo/partial rmw ecc error register */ +/* ==================================================================== */ + +#ifdef LITTLE_ENDIAN +typedef union sh_md_dqrs_mmr_yamopw_err_u { + mmr_t sh_md_dqrs_mmr_yamopw_err_regval; + struct { + mmr_t ssyn : 8; + mmr_t scor : 1; + mmr_t sunc : 1; + mmr_t reserved_0 : 6; + mmr_t rsyn : 8; + mmr_t rcor : 1; + mmr_t runc : 1; + mmr_t reserved_1 : 6; + mmr_t arm : 1; + mmr_t reserved_2 : 31; + } sh_md_dqrs_mmr_yamopw_err_s; +} sh_md_dqrs_mmr_yamopw_err_u_t; +#else +typedef union sh_md_dqrs_mmr_yamopw_err_u { + mmr_t sh_md_dqrs_mmr_yamopw_err_regval; + struct { + mmr_t reserved_2 : 31; + mmr_t arm : 1; + mmr_t reserved_1 : 6; + mmr_t runc : 1; + mmr_t rcor : 1; + mmr_t rsyn : 8; + mmr_t reserved_0 : 6; + mmr_t sunc : 1; + mmr_t scor : 1; + mmr_t ssyn : 8; + } sh_md_dqrs_mmr_yamopw_err_s; +} sh_md_dqrs_mmr_yamopw_err_u_t; +#endif + + +#endif /* _ASM_IA64_SN_SN2_SHUB_MMR_T_H */ diff --git a/include/asm-ia64/sn/sn2/shubio.h b/include/asm-ia64/sn/sn2/shubio.h new file mode 100644 index 000000000000..6d8edac60bb4 --- /dev/null +++ b/include/asm-ia64/sn/sn2/shubio.h @@ -0,0 +1,3639 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_SN_SN2_SHUBIO_H +#define _ASM_IA64_SN_SN2_SHUBIO_H + +#include <asm/sn/arch.h> + +#define HUB_WIDGET_ID_MAX 0xf +#define IIO_NUM_ITTES 7 +#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) + +#define IIO_WID 0x00400000 /* Crosstalk Widget Identification */ + /* This register is also accessible from + * Crosstalk at address 0x0. */ +#define IIO_WSTAT 0x00400008 /* Crosstalk Widget Status */ +#define IIO_WCR 0x00400020 /* Crosstalk Widget Control Register */ +#define IIO_ILAPR 0x00400100 /* IO Local Access Protection Register */ +#define IIO_ILAPO 0x00400108 /* IO Local Access Protection Override */ +#define IIO_IOWA 0x00400110 /* IO Outbound Widget Access */ +#define IIO_IIWA 0x00400118 /* IO Inbound Widget Access */ +#define IIO_IIDEM 0x00400120 /* IO Inbound Device Error Mask */ +#define IIO_ILCSR 0x00400128 /* IO LLP Control and Status Register */ +#define IIO_ILLR 0x00400130 /* IO LLP Log Register */ +#define IIO_IIDSR 0x00400138 /* IO Interrupt Destination */ + +#define IIO_IGFX0 0x00400140 /* IO Graphics Node-Widget Map 0 */ +#define IIO_IGFX1 0x00400148 /* IO Graphics Node-Widget Map 1 */ + +#define IIO_ISCR0 0x00400150 /* IO Scratch Register 0 */ +#define IIO_ISCR1 0x00400158 /* IO Scratch Register 1 */ + +#define IIO_ITTE1 0x00400160 /* IO Translation Table Entry 1 */ +#define IIO_ITTE2 0x00400168 /* IO Translation Table Entry 2 */ +#define IIO_ITTE3 0x00400170 /* IO Translation Table Entry 3 */ +#define IIO_ITTE4 0x00400178 /* IO Translation Table Entry 4 */ +#define IIO_ITTE5 0x00400180 /* IO Translation Table Entry 5 */ +#define IIO_ITTE6 0x00400188 /* IO Translation Table Entry 6 */ +#define IIO_ITTE7 0x00400190 /* IO Translation Table Entry 7 */ + +#define IIO_IPRB0 0x00400198 /* IO PRB Entry 0 */ +#define IIO_IPRB8 0x004001A0 /* IO PRB Entry 8 */ +#define IIO_IPRB9 0x004001A8 /* IO PRB Entry 9 */ +#define IIO_IPRBA 0x004001B0 /* IO PRB Entry A */ +#define IIO_IPRBB 0x004001B8 /* IO PRB Entry B */ +#define IIO_IPRBC 0x004001C0 /* IO PRB Entry C */ +#define IIO_IPRBD 0x004001C8 /* IO PRB Entry D */ +#define IIO_IPRBE 0x004001D0 /* IO PRB Entry E */ +#define IIO_IPRBF 0x004001D8 /* IO PRB Entry F */ + +#define IIO_IXCC 0x004001E0 /* IO Crosstalk Credit Count Timeout */ +#define IIO_IMEM 0x004001E8 /* IO Miscellaneous Error Mask */ +#define IIO_IXTT 0x004001F0 /* IO Crosstalk Timeout Threshold */ +#define IIO_IECLR 0x004001F8 /* IO Error Clear Register */ +#define IIO_IBCR 0x00400200 /* IO BTE Control Register */ + +#define IIO_IXSM 0x00400208 /* IO Crosstalk Spurious Message */ +#define IIO_IXSS 0x00400210 /* IO Crosstalk Spurious Sideband */ + +#define IIO_ILCT 0x00400218 /* IO LLP Channel Test */ + +#define IIO_IIEPH1 0x00400220 /* IO Incoming Error Packet Header, Part 1 */ +#define IIO_IIEPH2 0x00400228 /* IO Incoming Error Packet Header, Part 2 */ + + +#define IIO_ISLAPR 0x00400230 /* IO SXB Local Access Protection Regster */ +#define IIO_ISLAPO 0x00400238 /* IO SXB Local Access Protection Override */ + +#define IIO_IWI 0x00400240 /* IO Wrapper Interrupt Register */ +#define IIO_IWEL 0x00400248 /* IO Wrapper Error Log Register */ +#define IIO_IWC 0x00400250 /* IO Wrapper Control Register */ +#define IIO_IWS 0x00400258 /* IO Wrapper Status Register */ +#define IIO_IWEIM 0x00400260 /* IO Wrapper Error Interrupt Masking Register */ + +#define IIO_IPCA 0x00400300 /* IO PRB Counter Adjust */ + +#define IIO_IPRTE0_A 0x00400308 /* IO PIO Read Address Table Entry 0, Part A */ +#define IIO_IPRTE1_A 0x00400310 /* IO PIO Read Address Table Entry 1, Part A */ +#define IIO_IPRTE2_A 0x00400318 /* IO PIO Read Address Table Entry 2, Part A */ +#define IIO_IPRTE3_A 0x00400320 /* IO PIO Read Address Table Entry 3, Part A */ +#define IIO_IPRTE4_A 0x00400328 /* IO PIO Read Address Table Entry 4, Part A */ +#define IIO_IPRTE5_A 0x00400330 /* IO PIO Read Address Table Entry 5, Part A */ +#define IIO_IPRTE6_A 0x00400338 /* IO PIO Read Address Table Entry 6, Part A */ +#define IIO_IPRTE7_A 0x00400340 /* IO PIO Read Address Table Entry 7, Part A */ + +#define IIO_IPRTE0_B 0x00400348 /* IO PIO Read Address Table Entry 0, Part B */ +#define IIO_IPRTE1_B 0x00400350 /* IO PIO Read Address Table Entry 1, Part B */ +#define IIO_IPRTE2_B 0x00400358 /* IO PIO Read Address Table Entry 2, Part B */ +#define IIO_IPRTE3_B 0x00400360 /* IO PIO Read Address Table Entry 3, Part B */ +#define IIO_IPRTE4_B 0x00400368 /* IO PIO Read Address Table Entry 4, Part B */ +#define IIO_IPRTE5_B 0x00400370 /* IO PIO Read Address Table Entry 5, Part B */ +#define IIO_IPRTE6_B 0x00400378 /* IO PIO Read Address Table Entry 6, Part B */ +#define IIO_IPRTE7_B 0x00400380 /* IO PIO Read Address Table Entry 7, Part B */ + +#define IIO_IPDR 0x00400388 /* IO PIO Deallocation Register */ +#define IIO_ICDR 0x00400390 /* IO CRB Entry Deallocation Register */ +#define IIO_IFDR 0x00400398 /* IO IOQ FIFO Depth Register */ +#define IIO_IIAP 0x004003A0 /* IO IIQ Arbitration Parameters */ +#define IIO_ICMR 0x004003A8 /* IO CRB Management Register */ +#define IIO_ICCR 0x004003B0 /* IO CRB Control Register */ +#define IIO_ICTO 0x004003B8 /* IO CRB Timeout */ +#define IIO_ICTP 0x004003C0 /* IO CRB Timeout Prescalar */ + +#define IIO_ICRB0_A 0x00400400 /* IO CRB Entry 0_A */ +#define IIO_ICRB0_B 0x00400408 /* IO CRB Entry 0_B */ +#define IIO_ICRB0_C 0x00400410 /* IO CRB Entry 0_C */ +#define IIO_ICRB0_D 0x00400418 /* IO CRB Entry 0_D */ +#define IIO_ICRB0_E 0x00400420 /* IO CRB Entry 0_E */ + +#define IIO_ICRB1_A 0x00400430 /* IO CRB Entry 1_A */ +#define IIO_ICRB1_B 0x00400438 /* IO CRB Entry 1_B */ +#define IIO_ICRB1_C 0x00400440 /* IO CRB Entry 1_C */ +#define IIO_ICRB1_D 0x00400448 /* IO CRB Entry 1_D */ +#define IIO_ICRB1_E 0x00400450 /* IO CRB Entry 1_E */ + +#define IIO_ICRB2_A 0x00400460 /* IO CRB Entry 2_A */ +#define IIO_ICRB2_B 0x00400468 /* IO CRB Entry 2_B */ +#define IIO_ICRB2_C 0x00400470 /* IO CRB Entry 2_C */ +#define IIO_ICRB2_D 0x00400478 /* IO CRB Entry 2_D */ +#define IIO_ICRB2_E 0x00400480 /* IO CRB Entry 2_E */ + +#define IIO_ICRB3_A 0x00400490 /* IO CRB Entry 3_A */ +#define IIO_ICRB3_B 0x00400498 /* IO CRB Entry 3_B */ +#define IIO_ICRB3_C 0x004004a0 /* IO CRB Entry 3_C */ +#define IIO_ICRB3_D 0x004004a8 /* IO CRB Entry 3_D */ +#define IIO_ICRB3_E 0x004004b0 /* IO CRB Entry 3_E */ + +#define IIO_ICRB4_A 0x004004c0 /* IO CRB Entry 4_A */ +#define IIO_ICRB4_B 0x004004c8 /* IO CRB Entry 4_B */ +#define IIO_ICRB4_C 0x004004d0 /* IO CRB Entry 4_C */ +#define IIO_ICRB4_D 0x004004d8 /* IO CRB Entry 4_D */ +#define IIO_ICRB4_E 0x004004e0 /* IO CRB Entry 4_E */ + +#define IIO_ICRB5_A 0x004004f0 /* IO CRB Entry 5_A */ +#define IIO_ICRB5_B 0x004004f8 /* IO CRB Entry 5_B */ +#define IIO_ICRB5_C 0x00400500 /* IO CRB Entry 5_C */ +#define IIO_ICRB5_D 0x00400508 /* IO CRB Entry 5_D */ +#define IIO_ICRB5_E 0x00400510 /* IO CRB Entry 5_E */ + +#define IIO_ICRB6_A 0x00400520 /* IO CRB Entry 6_A */ +#define IIO_ICRB6_B 0x00400528 /* IO CRB Entry 6_B */ +#define IIO_ICRB6_C 0x00400530 /* IO CRB Entry 6_C */ +#define IIO_ICRB6_D 0x00400538 /* IO CRB Entry 6_D */ +#define IIO_ICRB6_E 0x00400540 /* IO CRB Entry 6_E */ + +#define IIO_ICRB7_A 0x00400550 /* IO CRB Entry 7_A */ +#define IIO_ICRB7_B 0x00400558 /* IO CRB Entry 7_B */ +#define IIO_ICRB7_C 0x00400560 /* IO CRB Entry 7_C */ +#define IIO_ICRB7_D 0x00400568 /* IO CRB Entry 7_D */ +#define IIO_ICRB7_E 0x00400570 /* IO CRB Entry 7_E */ + +#define IIO_ICRB8_A 0x00400580 /* IO CRB Entry 8_A */ +#define IIO_ICRB8_B 0x00400588 /* IO CRB Entry 8_B */ +#define IIO_ICRB8_C 0x00400590 /* IO CRB Entry 8_C */ +#define IIO_ICRB8_D 0x00400598 /* IO CRB Entry 8_D */ +#define IIO_ICRB8_E 0x004005a0 /* IO CRB Entry 8_E */ + +#define IIO_ICRB9_A 0x004005b0 /* IO CRB Entry 9_A */ +#define IIO_ICRB9_B 0x004005b8 /* IO CRB Entry 9_B */ +#define IIO_ICRB9_C 0x004005c0 /* IO CRB Entry 9_C */ +#define IIO_ICRB9_D 0x004005c8 /* IO CRB Entry 9_D */ +#define IIO_ICRB9_E 0x004005d0 /* IO CRB Entry 9_E */ + +#define IIO_ICRBA_A 0x004005e0 /* IO CRB Entry A_A */ +#define IIO_ICRBA_B 0x004005e8 /* IO CRB Entry A_B */ +#define IIO_ICRBA_C 0x004005f0 /* IO CRB Entry A_C */ +#define IIO_ICRBA_D 0x004005f8 /* IO CRB Entry A_D */ +#define IIO_ICRBA_E 0x00400600 /* IO CRB Entry A_E */ + +#define IIO_ICRBB_A 0x00400610 /* IO CRB Entry B_A */ +#define IIO_ICRBB_B 0x00400618 /* IO CRB Entry B_B */ +#define IIO_ICRBB_C 0x00400620 /* IO CRB Entry B_C */ +#define IIO_ICRBB_D 0x00400628 /* IO CRB Entry B_D */ +#define IIO_ICRBB_E 0x00400630 /* IO CRB Entry B_E */ + +#define IIO_ICRBC_A 0x00400640 /* IO CRB Entry C_A */ +#define IIO_ICRBC_B 0x00400648 /* IO CRB Entry C_B */ +#define IIO_ICRBC_C 0x00400650 /* IO CRB Entry C_C */ +#define IIO_ICRBC_D 0x00400658 /* IO CRB Entry C_D */ +#define IIO_ICRBC_E 0x00400660 /* IO CRB Entry C_E */ + +#define IIO_ICRBD_A 0x00400670 /* IO CRB Entry D_A */ +#define IIO_ICRBD_B 0x00400678 /* IO CRB Entry D_B */ +#define IIO_ICRBD_C 0x00400680 /* IO CRB Entry D_C */ +#define IIO_ICRBD_D 0x00400688 /* IO CRB Entry D_D */ +#define IIO_ICRBD_E 0x00400690 /* IO CRB Entry D_E */ + +#define IIO_ICRBE_A 0x004006a0 /* IO CRB Entry E_A */ +#define IIO_ICRBE_B 0x004006a8 /* IO CRB Entry E_B */ +#define IIO_ICRBE_C 0x004006b0 /* IO CRB Entry E_C */ +#define IIO_ICRBE_D 0x004006b8 /* IO CRB Entry E_D */ +#define IIO_ICRBE_E 0x004006c0 /* IO CRB Entry E_E */ + +#define IIO_ICSML 0x00400700 /* IO CRB Spurious Message Low */ +#define IIO_ICSMM 0x00400708 /* IO CRB Spurious Message Middle */ +#define IIO_ICSMH 0x00400710 /* IO CRB Spurious Message High */ + +#define IIO_IDBSS 0x00400718 /* IO Debug Submenu Select */ + +#define IIO_IBLS0 0x00410000 /* IO BTE Length Status 0 */ +#define IIO_IBSA0 0x00410008 /* IO BTE Source Address 0 */ +#define IIO_IBDA0 0x00410010 /* IO BTE Destination Address 0 */ +#define IIO_IBCT0 0x00410018 /* IO BTE Control Terminate 0 */ +#define IIO_IBNA0 0x00410020 /* IO BTE Notification Address 0 */ +#define IIO_IBIA0 0x00410028 /* IO BTE Interrupt Address 0 */ +#define IIO_IBLS1 0x00420000 /* IO BTE Length Status 1 */ +#define IIO_IBSA1 0x00420008 /* IO BTE Source Address 1 */ +#define IIO_IBDA1 0x00420010 /* IO BTE Destination Address 1 */ +#define IIO_IBCT1 0x00420018 /* IO BTE Control Terminate 1 */ +#define IIO_IBNA1 0x00420020 /* IO BTE Notification Address 1 */ +#define IIO_IBIA1 0x00420028 /* IO BTE Interrupt Address 1 */ + +#define IIO_IPCR 0x00430000 /* IO Performance Control */ +#define IIO_IPPR 0x00430008 /* IO Performance Profiling */ + + +#ifndef __ASSEMBLY__ + +/************************************************************************ + * * + * Description: This register echoes some information from the * + * LB_REV_ID register. It is available through Crosstalk as described * + * above. The REV_NUM and MFG_NUM fields receive their values from * + * the REVISION and MANUFACTURER fields in the LB_REV_ID register. * + * The PART_NUM field's value is the Crosstalk device ID number that * + * Steve Miller assigned to the SHub chip. * + * * + ************************************************************************/ + +typedef union ii_wid_u { + shubreg_t ii_wid_regval; + struct { + shubreg_t w_rsvd_1 : 1; + shubreg_t w_mfg_num : 11; + shubreg_t w_part_num : 16; + shubreg_t w_rev_num : 4; + shubreg_t w_rsvd : 32; + } ii_wid_fld_s; +} ii_wid_u_t; + + +/************************************************************************ + * * + * The fields in this register are set upon detection of an error * + * and cleared by various mechanisms, as explained in the * + * description. * + * * + ************************************************************************/ + +typedef union ii_wstat_u { + shubreg_t ii_wstat_regval; + struct { + shubreg_t w_pending : 4; + shubreg_t w_xt_crd_to : 1; + shubreg_t w_xt_tail_to : 1; + shubreg_t w_rsvd_3 : 3; + shubreg_t w_tx_mx_rty : 1; + shubreg_t w_rsvd_2 : 6; + shubreg_t w_llp_tx_cnt : 8; + shubreg_t w_rsvd_1 : 8; + shubreg_t w_crazy : 1; + shubreg_t w_rsvd : 31; + } ii_wstat_fld_s; +} ii_wstat_u_t; + + +/************************************************************************ + * * + * Description: This is a read-write enabled register. It controls * + * various aspects of the Crosstalk flow control. * + * * + ************************************************************************/ + +typedef union ii_wcr_u { + shubreg_t ii_wcr_regval; + struct { + shubreg_t w_wid : 4; + shubreg_t w_tag : 1; + shubreg_t w_rsvd_1 : 8; + shubreg_t w_dst_crd : 3; + shubreg_t w_f_bad_pkt : 1; + shubreg_t w_dir_con : 1; + shubreg_t w_e_thresh : 5; + shubreg_t w_rsvd : 41; + } ii_wcr_fld_s; +} ii_wcr_u_t; + + +/************************************************************************ + * * + * Description: This register's value is a bit vector that guards * + * access to local registers within the II as well as to external * + * Crosstalk widgets. Each bit in the register corresponds to a * + * particular region in the system; a region consists of one, two or * + * four nodes (depending on the value of the REGION_SIZE field in the * + * LB_REV_ID register, which is documented in Section 8.3.1.1). The * + * protection provided by this register applies to PIO read * + * operations as well as PIO write operations. The II will perform a * + * PIO read or write request only if the bit for the requestor's * + * region is set; otherwise, the II will not perform the requested * + * operation and will return an error response. When a PIO read or * + * write request targets an external Crosstalk widget, then not only * + * must the bit for the requestor's region be set in the ILAPR, but * + * also the target widget's bit in the IOWA register must be set in * + * order for the II to perform the requested operation; otherwise, * + * the II will return an error response. Hence, the protection * + * provided by the IOWA register supplements the protection provided * + * by the ILAPR for requests that target external Crosstalk widgets. * + * This register itself can be accessed only by the nodes whose * + * region ID bits are enabled in this same register. It can also be * + * accessed through the IAlias space by the local processors. * + * The reset value of this register allows access by all nodes. * + * * + ************************************************************************/ + +typedef union ii_ilapr_u { + shubreg_t ii_ilapr_regval; + struct { + shubreg_t i_region : 64; + } ii_ilapr_fld_s; +} ii_ilapr_u_t; + + + + +/************************************************************************ + * * + * Description: A write to this register of the 64-bit value * + * "SGIrules" in ASCII, will cause the bit in the ILAPR register * + * corresponding to the region of the requestor to be set (allow * + * access). A write of any other value will be ignored. Access * + * protection for this register is "SGIrules". * + * This register can also be accessed through the IAlias space. * + * However, this access will not change the access permissions in the * + * ILAPR. * + * * + ************************************************************************/ + +typedef union ii_ilapo_u { + shubreg_t ii_ilapo_regval; + struct { + shubreg_t i_io_ovrride : 64; + } ii_ilapo_fld_s; +} ii_ilapo_u_t; + + + +/************************************************************************ + * * + * This register qualifies all the PIO and Graphics writes launched * + * from the SHUB towards a widget. * + * * + ************************************************************************/ + +typedef union ii_iowa_u { + shubreg_t ii_iowa_regval; + struct { + shubreg_t i_w0_oac : 1; + shubreg_t i_rsvd_1 : 7; + shubreg_t i_wx_oac : 8; + shubreg_t i_rsvd : 48; + } ii_iowa_fld_s; +} ii_iowa_u_t; + + +/************************************************************************ + * * + * Description: This register qualifies all the requests launched * + * from a widget towards the Shub. This register is intended to be * + * used by software in case of misbehaving widgets. * + * * + * * + ************************************************************************/ + +typedef union ii_iiwa_u { + shubreg_t ii_iiwa_regval; + struct { + shubreg_t i_w0_iac : 1; + shubreg_t i_rsvd_1 : 7; + shubreg_t i_wx_iac : 8; + shubreg_t i_rsvd : 48; + } ii_iiwa_fld_s; +} ii_iiwa_u_t; + + + +/************************************************************************ + * * + * Description: This register qualifies all the operations launched * + * from a widget towards the SHub. It allows individual access * + * control for up to 8 devices per widget. A device refers to * + * individual DMA master hosted by a widget. * + * The bits in each field of this register are cleared by the Shub * + * upon detection of an error which requires the device to be * + * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric * + * Crosstalk). Whether or not a device has access rights to this * + * Shub is determined by an AND of the device enable bit in the * + * appropriate field of this register and the corresponding bit in * + * the Wx_IAC field (for the widget which this device belongs to). * + * The bits in this field are set by writing a 1 to them. Incoming * + * replies from Crosstalk are not subject to this access control * + * mechanism. * + * * + ************************************************************************/ + +typedef union ii_iidem_u { + shubreg_t ii_iidem_regval; + struct { + shubreg_t i_w8_dxs : 8; + shubreg_t i_w9_dxs : 8; + shubreg_t i_wa_dxs : 8; + shubreg_t i_wb_dxs : 8; + shubreg_t i_wc_dxs : 8; + shubreg_t i_wd_dxs : 8; + shubreg_t i_we_dxs : 8; + shubreg_t i_wf_dxs : 8; + } ii_iidem_fld_s; +} ii_iidem_u_t; + + +/************************************************************************ + * * + * This register contains the various programmable fields necessary * + * for controlling and observing the LLP signals. * + * * + ************************************************************************/ + +typedef union ii_ilcsr_u { + shubreg_t ii_ilcsr_regval; + struct { + shubreg_t i_nullto : 6; + shubreg_t i_rsvd_4 : 2; + shubreg_t i_wrmrst : 1; + shubreg_t i_rsvd_3 : 1; + shubreg_t i_llp_en : 1; + shubreg_t i_bm8 : 1; + shubreg_t i_llp_stat : 2; + shubreg_t i_remote_power : 1; + shubreg_t i_rsvd_2 : 1; + shubreg_t i_maxrtry : 10; + shubreg_t i_d_avail_sel : 2; + shubreg_t i_rsvd_1 : 4; + shubreg_t i_maxbrst : 10; + shubreg_t i_rsvd : 22; + + } ii_ilcsr_fld_s; +} ii_ilcsr_u_t; + + +/************************************************************************ + * * + * This is simply a status registers that monitors the LLP error * + * rate. * + * * + ************************************************************************/ + +typedef union ii_illr_u { + shubreg_t ii_illr_regval; + struct { + shubreg_t i_sn_cnt : 16; + shubreg_t i_cb_cnt : 16; + shubreg_t i_rsvd : 32; + } ii_illr_fld_s; +} ii_illr_u_t; + + +/************************************************************************ + * * + * Description: All II-detected non-BTE error interrupts are * + * specified via this register. * + * NOTE: The PI interrupt register address is hardcoded in the II. If * + * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI * + * packet) to address offset 0x0180_0090 within the local register * + * address space of PI0 on the node specified by the NODE field. If * + * PI_ID==1, then the II sends the interrupt request to address * + * offset 0x01A0_0090 within the local register address space of PI1 * + * on the node specified by the NODE field. * + * * + ************************************************************************/ + +typedef union ii_iidsr_u { + shubreg_t ii_iidsr_regval; + struct { + shubreg_t i_level : 8; + shubreg_t i_pi_id : 1; + shubreg_t i_node : 11; + shubreg_t i_rsvd_3 : 4; + shubreg_t i_enable : 1; + shubreg_t i_rsvd_2 : 3; + shubreg_t i_int_sent : 1; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_pi0_forward_int : 1; + shubreg_t i_pi1_forward_int : 1; + shubreg_t i_rsvd : 30; + } ii_iidsr_fld_s; +} ii_iidsr_u_t; + + + +/************************************************************************ + * * + * There are two instances of this register. This register is used * + * for matching up the incoming responses from the graphics widget to * + * the processor that initiated the graphics operation. The * + * write-responses are converted to graphics credits and returned to * + * the processor so that the processor interface can manage the flow * + * control. * + * * + ************************************************************************/ + +typedef union ii_igfx0_u { + shubreg_t ii_igfx0_regval; + struct { + shubreg_t i_w_num : 4; + shubreg_t i_pi_id : 1; + shubreg_t i_n_num : 12; + shubreg_t i_p_num : 1; + shubreg_t i_rsvd : 46; + } ii_igfx0_fld_s; +} ii_igfx0_u_t; + + +/************************************************************************ + * * + * There are two instances of this register. This register is used * + * for matching up the incoming responses from the graphics widget to * + * the processor that initiated the graphics operation. The * + * write-responses are converted to graphics credits and returned to * + * the processor so that the processor interface can manage the flow * + * control. * + * * + ************************************************************************/ + +typedef union ii_igfx1_u { + shubreg_t ii_igfx1_regval; + struct { + shubreg_t i_w_num : 4; + shubreg_t i_pi_id : 1; + shubreg_t i_n_num : 12; + shubreg_t i_p_num : 1; + shubreg_t i_rsvd : 46; + } ii_igfx1_fld_s; +} ii_igfx1_u_t; + + +/************************************************************************ + * * + * There are two instances of this registers. These registers are * + * used as scratch registers for software use. * + * * + ************************************************************************/ + +typedef union ii_iscr0_u { + shubreg_t ii_iscr0_regval; + struct { + shubreg_t i_scratch : 64; + } ii_iscr0_fld_s; +} ii_iscr0_u_t; + + + +/************************************************************************ + * * + * There are two instances of this registers. These registers are * + * used as scratch registers for software use. * + * * + ************************************************************************/ + +typedef union ii_iscr1_u { + shubreg_t ii_iscr1_regval; + struct { + shubreg_t i_scratch : 64; + } ii_iscr1_fld_s; +} ii_iscr1_u_t; + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Shub Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the SHub is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the Shub is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + +typedef union ii_itte1_u { + shubreg_t ii_itte1_regval; + struct { + shubreg_t i_offset : 5; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_w_num : 4; + shubreg_t i_iosp : 1; + shubreg_t i_rsvd : 51; + } ii_itte1_fld_s; +} ii_itte1_u_t; + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Shub Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Shub is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the Shub is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + +typedef union ii_itte2_u { + shubreg_t ii_itte2_regval; + struct { + shubreg_t i_offset : 5; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_w_num : 4; + shubreg_t i_iosp : 1; + shubreg_t i_rsvd : 51; + } ii_itte2_fld_s; +} ii_itte2_u_t; + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Shub Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Shub is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the SHub is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + +typedef union ii_itte3_u { + shubreg_t ii_itte3_regval; + struct { + shubreg_t i_offset : 5; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_w_num : 4; + shubreg_t i_iosp : 1; + shubreg_t i_rsvd : 51; + } ii_itte3_fld_s; +} ii_itte3_u_t; + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a SHub Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the SHub is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the SHub is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + +typedef union ii_itte4_u { + shubreg_t ii_itte4_regval; + struct { + shubreg_t i_offset : 5; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_w_num : 4; + shubreg_t i_iosp : 1; + shubreg_t i_rsvd : 51; + } ii_itte4_fld_s; +} ii_itte4_u_t; + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a SHub Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Shub is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the Shub is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + +typedef union ii_itte5_u { + shubreg_t ii_itte5_regval; + struct { + shubreg_t i_offset : 5; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_w_num : 4; + shubreg_t i_iosp : 1; + shubreg_t i_rsvd : 51; + } ii_itte5_fld_s; +} ii_itte5_u_t; + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Shub Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Shub is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the Shub is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + +typedef union ii_itte6_u { + shubreg_t ii_itte6_regval; + struct { + shubreg_t i_offset : 5; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_w_num : 4; + shubreg_t i_iosp : 1; + shubreg_t i_rsvd : 51; + } ii_itte6_fld_s; +} ii_itte6_u_t; + + +/************************************************************************ + * * + * Description: There are seven instances of translation table entry * + * registers. Each register maps a Shub Big Window to a 48-bit * + * address on Crosstalk. * + * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window * + * number) are used to select one of these 7 registers. The Widget * + * number field is then derived from the W_NUM field for synthesizing * + * a Crosstalk packet. The 5 bits of OFFSET are concatenated with * + * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34] * + * are padded with zeros. Although the maximum Crosstalk space * + * addressable by the Shub is thus the lower 16 GBytes per widget * + * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this * + * space can be accessed. * + * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big * + * Window number) are used to select one of these 7 registers. The * + * Widget number field is then derived from the W_NUM field for * + * synthesizing a Crosstalk packet. The 5 bits of OFFSET are * + * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP * + * field is used as Crosstalk[47], and remainder of the Crosstalk * + * address bits (Crosstalk[46:34]) are always zero. While the maximum * + * Crosstalk space addressable by the SHub is thus the lower * + * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB> * + * of this space can be accessed. * + * * + ************************************************************************/ + +typedef union ii_itte7_u { + shubreg_t ii_itte7_regval; + struct { + shubreg_t i_offset : 5; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_w_num : 4; + shubreg_t i_iosp : 1; + shubreg_t i_rsvd : 51; + } ii_itte7_fld_s; +} ii_itte7_u_t; + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of SHub and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + +typedef union ii_iprb0_u { + shubreg_t ii_iprb0_regval; + struct { + shubreg_t i_c : 8; + shubreg_t i_na : 14; + shubreg_t i_rsvd_2 : 2; + shubreg_t i_nb : 14; + shubreg_t i_rsvd_1 : 2; + shubreg_t i_m : 2; + shubreg_t i_f : 1; + shubreg_t i_of_cnt : 5; + shubreg_t i_error : 1; + shubreg_t i_rd_to : 1; + shubreg_t i_spur_wr : 1; + shubreg_t i_spur_rd : 1; + shubreg_t i_rsvd : 11; + shubreg_t i_mult_err : 1; + } ii_iprb0_fld_s; +} ii_iprb0_u_t; + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of SHub and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + +typedef union ii_iprb8_u { + shubreg_t ii_iprb8_regval; + struct { + shubreg_t i_c : 8; + shubreg_t i_na : 14; + shubreg_t i_rsvd_2 : 2; + shubreg_t i_nb : 14; + shubreg_t i_rsvd_1 : 2; + shubreg_t i_m : 2; + shubreg_t i_f : 1; + shubreg_t i_of_cnt : 5; + shubreg_t i_error : 1; + shubreg_t i_rd_to : 1; + shubreg_t i_spur_wr : 1; + shubreg_t i_spur_rd : 1; + shubreg_t i_rsvd : 11; + shubreg_t i_mult_err : 1; + } ii_iprb8_fld_s; +} ii_iprb8_u_t; + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of SHub and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + +typedef union ii_iprb9_u { + shubreg_t ii_iprb9_regval; + struct { + shubreg_t i_c : 8; + shubreg_t i_na : 14; + shubreg_t i_rsvd_2 : 2; + shubreg_t i_nb : 14; + shubreg_t i_rsvd_1 : 2; + shubreg_t i_m : 2; + shubreg_t i_f : 1; + shubreg_t i_of_cnt : 5; + shubreg_t i_error : 1; + shubreg_t i_rd_to : 1; + shubreg_t i_spur_wr : 1; + shubreg_t i_spur_rd : 1; + shubreg_t i_rsvd : 11; + shubreg_t i_mult_err : 1; + } ii_iprb9_fld_s; +} ii_iprb9_u_t; + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of SHub and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * * + * * + ************************************************************************/ + +typedef union ii_iprba_u { + shubreg_t ii_iprba_regval; + struct { + shubreg_t i_c : 8; + shubreg_t i_na : 14; + shubreg_t i_rsvd_2 : 2; + shubreg_t i_nb : 14; + shubreg_t i_rsvd_1 : 2; + shubreg_t i_m : 2; + shubreg_t i_f : 1; + shubreg_t i_of_cnt : 5; + shubreg_t i_error : 1; + shubreg_t i_rd_to : 1; + shubreg_t i_spur_wr : 1; + shubreg_t i_spur_rd : 1; + shubreg_t i_rsvd : 11; + shubreg_t i_mult_err : 1; + } ii_iprba_fld_s; +} ii_iprba_u_t; + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of SHub and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + +typedef union ii_iprbb_u { + shubreg_t ii_iprbb_regval; + struct { + shubreg_t i_c : 8; + shubreg_t i_na : 14; + shubreg_t i_rsvd_2 : 2; + shubreg_t i_nb : 14; + shubreg_t i_rsvd_1 : 2; + shubreg_t i_m : 2; + shubreg_t i_f : 1; + shubreg_t i_of_cnt : 5; + shubreg_t i_error : 1; + shubreg_t i_rd_to : 1; + shubreg_t i_spur_wr : 1; + shubreg_t i_spur_rd : 1; + shubreg_t i_rsvd : 11; + shubreg_t i_mult_err : 1; + } ii_iprbb_fld_s; +} ii_iprbb_u_t; + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of SHub and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + +typedef union ii_iprbc_u { + shubreg_t ii_iprbc_regval; + struct { + shubreg_t i_c : 8; + shubreg_t i_na : 14; + shubreg_t i_rsvd_2 : 2; + shubreg_t i_nb : 14; + shubreg_t i_rsvd_1 : 2; + shubreg_t i_m : 2; + shubreg_t i_f : 1; + shubreg_t i_of_cnt : 5; + shubreg_t i_error : 1; + shubreg_t i_rd_to : 1; + shubreg_t i_spur_wr : 1; + shubreg_t i_spur_rd : 1; + shubreg_t i_rsvd : 11; + shubreg_t i_mult_err : 1; + } ii_iprbc_fld_s; +} ii_iprbc_u_t; + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of SHub and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + +typedef union ii_iprbd_u { + shubreg_t ii_iprbd_regval; + struct { + shubreg_t i_c : 8; + shubreg_t i_na : 14; + shubreg_t i_rsvd_2 : 2; + shubreg_t i_nb : 14; + shubreg_t i_rsvd_1 : 2; + shubreg_t i_m : 2; + shubreg_t i_f : 1; + shubreg_t i_of_cnt : 5; + shubreg_t i_error : 1; + shubreg_t i_rd_to : 1; + shubreg_t i_spur_wr : 1; + shubreg_t i_spur_rd : 1; + shubreg_t i_rsvd : 11; + shubreg_t i_mult_err : 1; + } ii_iprbd_fld_s; +} ii_iprbd_u_t; + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of SHub and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + +typedef union ii_iprbe_u { + shubreg_t ii_iprbe_regval; + struct { + shubreg_t i_c : 8; + shubreg_t i_na : 14; + shubreg_t i_rsvd_2 : 2; + shubreg_t i_nb : 14; + shubreg_t i_rsvd_1 : 2; + shubreg_t i_m : 2; + shubreg_t i_f : 1; + shubreg_t i_of_cnt : 5; + shubreg_t i_error : 1; + shubreg_t i_rd_to : 1; + shubreg_t i_spur_wr : 1; + shubreg_t i_spur_rd : 1; + shubreg_t i_rsvd : 11; + shubreg_t i_mult_err : 1; + } ii_iprbe_fld_s; +} ii_iprbe_u_t; + + +/************************************************************************ + * * + * Description: There are 9 instances of this register, one per * + * actual widget in this implementation of Shub and Crossbow. * + * Note: Crossbow only has ports for Widgets 8 through F, widget 0 * + * refers to Crossbow's internal space. * + * This register contains the state elements per widget that are * + * necessary to manage the PIO flow control on Crosstalk and on the * + * Router Network. See the PIO Flow Control chapter for a complete * + * description of this register * + * The SPUR_WR bit requires some explanation. When this register is * + * written, the new value of the C field is captured in an internal * + * register so the hardware can remember what the programmer wrote * + * into the credit counter. The SPUR_WR bit sets whenever the C field * + * increments above this stored value, which indicates that there * + * have been more responses received than requests sent. The SPUR_WR * + * bit cannot be cleared until a value is written to the IPRBx * + * register; the write will correct the C field and capture its new * + * value in the internal register. Even if IECLR[E_PRB_x] is set, the * + * SPUR_WR bit will persist if IPRBx hasn't yet been written. * + * . * + * * + ************************************************************************/ + +typedef union ii_iprbf_u { + shubreg_t ii_iprbf_regval; + struct { + shubreg_t i_c : 8; + shubreg_t i_na : 14; + shubreg_t i_rsvd_2 : 2; + shubreg_t i_nb : 14; + shubreg_t i_rsvd_1 : 2; + shubreg_t i_m : 2; + shubreg_t i_f : 1; + shubreg_t i_of_cnt : 5; + shubreg_t i_error : 1; + shubreg_t i_rd_to : 1; + shubreg_t i_spur_wr : 1; + shubreg_t i_spur_rd : 1; + shubreg_t i_rsvd : 11; + shubreg_t i_mult_err : 1; + } ii_iprbe_fld_s; +} ii_iprbf_u_t; + + +/************************************************************************ + * * + * This register specifies the timeout value to use for monitoring * + * Crosstalk credits which are used outbound to Crosstalk. An * + * internal counter called the Crosstalk Credit Timeout Counter * + * increments every 128 II clocks. The counter starts counting * + * anytime the credit count drops below a threshold, and resets to * + * zero (stops counting) anytime the credit count is at or above the * + * threshold. The threshold is 1 credit in direct connect mode and 2 * + * in Crossbow connect mode. When the internal Crosstalk Credit * + * Timeout Counter reaches the value programmed in this register, a * + * Crosstalk Credit Timeout has occurred. The internal counter is not * + * readable from software, and stops counting at its maximum value, * + * so it cannot cause more than one interrupt. * + * * + ************************************************************************/ + +typedef union ii_ixcc_u { + shubreg_t ii_ixcc_regval; + struct { + shubreg_t i_time_out : 26; + shubreg_t i_rsvd : 38; + } ii_ixcc_fld_s; +} ii_ixcc_u_t; + + +/************************************************************************ + * * + * Description: This register qualifies all the PIO and DMA * + * operations launched from widget 0 towards the SHub. In * + * addition, it also qualifies accesses by the BTE streams. * + * The bits in each field of this register are cleared by the SHub * + * upon detection of an error which requires widget 0 or the BTE * + * streams to be terminated. Whether or not widget x has access * + * rights to this SHub is determined by an AND of the device * + * enable bit in the appropriate field of this register and bit 0 in * + * the Wx_IAC field. The bits in this field are set by writing a 1 to * + * them. Incoming replies from Crosstalk are not subject to this * + * access control mechanism. * + * * + ************************************************************************/ + +typedef union ii_imem_u { + shubreg_t ii_imem_regval; + struct { + shubreg_t i_w0_esd : 1; + shubreg_t i_rsvd_3 : 3; + shubreg_t i_b0_esd : 1; + shubreg_t i_rsvd_2 : 3; + shubreg_t i_b1_esd : 1; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_clr_precise : 1; + shubreg_t i_rsvd : 51; + } ii_imem_fld_s; +} ii_imem_u_t; + + + +/************************************************************************ + * * + * Description: This register specifies the timeout value to use for * + * monitoring Crosstalk tail flits coming into the Shub in the * + * TAIL_TO field. An internal counter associated with this register * + * is incremented every 128 II internal clocks (7 bits). The counter * + * starts counting anytime a header micropacket is received and stops * + * counting (and resets to zero) any time a micropacket with a Tail * + * bit is received. Once the counter reaches the threshold value * + * programmed in this register, it generates an interrupt to the * + * processor that is programmed into the IIDSR. The counter saturates * + * (does not roll over) at its maximum value, so it cannot cause * + * another interrupt until after it is cleared. * + * The register also contains the Read Response Timeout values. The * + * Prescalar is 23 bits, and counts II clocks. An internal counter * + * increments on every II clock and when it reaches the value in the * + * Prescalar field, all IPRTE registers with their valid bits set * + * have their Read Response timers bumped. Whenever any of them match * + * the value in the RRSP_TO field, a Read Response Timeout has * + * occurred, and error handling occurs as described in the Error * + * Handling section of this document. * + * * + ************************************************************************/ + +typedef union ii_ixtt_u { + shubreg_t ii_ixtt_regval; + struct { + shubreg_t i_tail_to : 26; + shubreg_t i_rsvd_1 : 6; + shubreg_t i_rrsp_ps : 23; + shubreg_t i_rrsp_to : 5; + shubreg_t i_rsvd : 4; + } ii_ixtt_fld_s; +} ii_ixtt_u_t; + + +/************************************************************************ + * * + * Writing a 1 to the fields of this register clears the appropriate * + * error bits in other areas of SHub. Note that when the * + * E_PRB_x bits are used to clear error bits in PRB registers, * + * SPUR_RD and SPUR_WR may persist, because they require additional * + * action to clear them. See the IPRBx and IXSS Register * + * specifications. * + * * + ************************************************************************/ + +typedef union ii_ieclr_u { + shubreg_t ii_ieclr_regval; + struct { + shubreg_t i_e_prb_0 : 1; + shubreg_t i_rsvd : 7; + shubreg_t i_e_prb_8 : 1; + shubreg_t i_e_prb_9 : 1; + shubreg_t i_e_prb_a : 1; + shubreg_t i_e_prb_b : 1; + shubreg_t i_e_prb_c : 1; + shubreg_t i_e_prb_d : 1; + shubreg_t i_e_prb_e : 1; + shubreg_t i_e_prb_f : 1; + shubreg_t i_e_crazy : 1; + shubreg_t i_e_bte_0 : 1; + shubreg_t i_e_bte_1 : 1; + shubreg_t i_reserved_1 : 10; + shubreg_t i_spur_rd_hdr : 1; + shubreg_t i_cam_intr_to : 1; + shubreg_t i_cam_overflow : 1; + shubreg_t i_cam_read_miss : 1; + shubreg_t i_ioq_rep_underflow : 1; + shubreg_t i_ioq_req_underflow : 1; + shubreg_t i_ioq_rep_overflow : 1; + shubreg_t i_ioq_req_overflow : 1; + shubreg_t i_iiq_rep_overflow : 1; + shubreg_t i_iiq_req_overflow : 1; + shubreg_t i_ii_xn_rep_cred_overflow : 1; + shubreg_t i_ii_xn_req_cred_overflow : 1; + shubreg_t i_ii_xn_invalid_cmd : 1; + shubreg_t i_xn_ii_invalid_cmd : 1; + shubreg_t i_reserved_2 : 21; + } ii_ieclr_fld_s; +} ii_ieclr_u_t; + + +/************************************************************************ + * * + * This register controls both BTEs. SOFT_RESET is intended for * + * recovery after an error. COUNT controls the total number of CRBs * + * that both BTEs (combined) can use, which affects total BTE * + * bandwidth. * + * * + ************************************************************************/ + +typedef union ii_ibcr_u { + shubreg_t ii_ibcr_regval; + struct { + shubreg_t i_count : 4; + shubreg_t i_rsvd_1 : 4; + shubreg_t i_soft_reset : 1; + shubreg_t i_rsvd : 55; + } ii_ibcr_fld_s; +} ii_ibcr_u_t; + + +/************************************************************************ + * * + * This register contains the header of a spurious read response * + * received from Crosstalk. A spurious read response is defined as a * + * read response received by II from a widget for which (1) the SIDN * + * has a value between 1 and 7, inclusive (II never sends requests to * + * these widgets (2) there is no valid IPRTE register which * + * corresponds to the TNUM, or (3) the widget indicated in SIDN is * + * not the same as the widget recorded in the IPRTE register * + * referenced by the TNUM. If this condition is true, and if the * + * IXSS[VALID] bit is clear, then the header of the spurious read * + * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The * + * errant header is thereby captured, and no further spurious read * + * respones are captured until IXSS[VALID] is cleared by setting the * + * appropriate bit in IECLR.Everytime a spurious read response is * + * detected, the SPUR_RD bit of the PRB corresponding to the incoming * + * message's SIDN field is set. This always happens, regarless of * + * whether a header is captured. The programmer should check * + * IXSM[SIDN] to determine which widget sent the spurious response, * + * because there may be more than one SPUR_RD bit set in the PRB * + * registers. The widget indicated by IXSM[SIDN] was the first * + * spurious read response to be received since the last time * + * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB * + * will be set. Any SPUR_RD bits in any other PRB registers indicate * + * spurious messages from other widets which were detected after the * + * header was captured.. * + * * + ************************************************************************/ + +typedef union ii_ixsm_u { + shubreg_t ii_ixsm_regval; + struct { + shubreg_t i_byte_en : 32; + shubreg_t i_reserved : 1; + shubreg_t i_tag : 3; + shubreg_t i_alt_pactyp : 4; + shubreg_t i_bo : 1; + shubreg_t i_error : 1; + shubreg_t i_vbpm : 1; + shubreg_t i_gbr : 1; + shubreg_t i_ds : 2; + shubreg_t i_ct : 1; + shubreg_t i_tnum : 5; + shubreg_t i_pactyp : 4; + shubreg_t i_sidn : 4; + shubreg_t i_didn : 4; + } ii_ixsm_fld_s; +} ii_ixsm_u_t; + + +/************************************************************************ + * * + * This register contains the sideband bits of a spurious read * + * response received from Crosstalk. * + * * + ************************************************************************/ + +typedef union ii_ixss_u { + shubreg_t ii_ixss_regval; + struct { + shubreg_t i_sideband : 8; + shubreg_t i_rsvd : 55; + shubreg_t i_valid : 1; + } ii_ixss_fld_s; +} ii_ixss_u_t; + + +/************************************************************************ + * * + * This register enables software to access the II LLP's test port. * + * Refer to the LLP 2.5 documentation for an explanation of the test * + * port. Software can write to this register to program the values * + * for the control fields (TestErrCapture, TestClear, TestFlit, * + * TestMask and TestSeed). Similarly, software can read from this * + * register to obtain the values of the test port's status outputs * + * (TestCBerr, TestValid and TestData). * + * * + ************************************************************************/ + +typedef union ii_ilct_u { + shubreg_t ii_ilct_regval; + struct { + shubreg_t i_test_seed : 20; + shubreg_t i_test_mask : 8; + shubreg_t i_test_data : 20; + shubreg_t i_test_valid : 1; + shubreg_t i_test_cberr : 1; + shubreg_t i_test_flit : 3; + shubreg_t i_test_clear : 1; + shubreg_t i_test_err_capture : 1; + shubreg_t i_rsvd : 9; + } ii_ilct_fld_s; +} ii_ilct_u_t; + + +/************************************************************************ + * * + * If the II detects an illegal incoming Duplonet packet (request or * + * reply) when VALID==0 in the IIEPH1 register, then it saves the * + * contents of the packet's header flit in the IIEPH1 and IIEPH2 * + * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit, * + * and assigns a value to the ERR_TYPE field which indicates the * + * specific nature of the error. The II recognizes four different * + * types of errors: short request packets (ERR_TYPE==2), short reply * + * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long * + * reply packets (ERR_TYPE==5). The encodings for these types of * + * errors were chosen to be consistent with the same types of errors * + * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in * + * the LB unit). If the II detects an illegal incoming Duplonet * + * packet when VALID==1 in the IIEPH1 register, then it merely sets * + * the OVERRUN bit to indicate that a subsequent error has happened, * + * and does nothing further. * + * * + ************************************************************************/ + +typedef union ii_iieph1_u { + shubreg_t ii_iieph1_regval; + struct { + shubreg_t i_command : 7; + shubreg_t i_rsvd_5 : 1; + shubreg_t i_suppl : 14; + shubreg_t i_rsvd_4 : 1; + shubreg_t i_source : 14; + shubreg_t i_rsvd_3 : 1; + shubreg_t i_err_type : 4; + shubreg_t i_rsvd_2 : 4; + shubreg_t i_overrun : 1; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_valid : 1; + shubreg_t i_rsvd : 13; + } ii_iieph1_fld_s; +} ii_iieph1_u_t; + + +/************************************************************************ + * * + * This register holds the Address field from the header flit of an * + * incoming erroneous Duplonet packet, along with the tail bit which * + * accompanied this header flit. This register is essentially an * + * extension of IIEPH1. Two registers were necessary because the 64 * + * bits available in only a single register were insufficient to * + * capture the entire header flit of an erroneous packet. * + * * + ************************************************************************/ + +typedef union ii_iieph2_u { + shubreg_t ii_iieph2_regval; + struct { + shubreg_t i_rsvd_0 : 3; + shubreg_t i_address : 47; + shubreg_t i_rsvd_1 : 10; + shubreg_t i_tail : 1; + shubreg_t i_rsvd : 3; + } ii_iieph2_fld_s; +} ii_iieph2_u_t; + + +/******************************/ + + + +/************************************************************************ + * * + * This register's value is a bit vector that guards access from SXBs * + * to local registers within the II as well as to external Crosstalk * + * widgets * + * * + ************************************************************************/ + +typedef union ii_islapr_u { + shubreg_t ii_islapr_regval; + struct { + shubreg_t i_region : 64; + } ii_islapr_fld_s; +} ii_islapr_u_t; + + +/************************************************************************ + * * + * A write to this register of the 56-bit value "Pup+Bun" will cause * + * the bit in the ISLAPR register corresponding to the region of the * + * requestor to be set (access allowed). ( + * * + ************************************************************************/ + +typedef union ii_islapo_u { + shubreg_t ii_islapo_regval; + struct { + shubreg_t i_io_sbx_ovrride : 56; + shubreg_t i_rsvd : 8; + } ii_islapo_fld_s; +} ii_islapo_u_t; + +/************************************************************************ + * * + * Determines how long the wrapper will wait aftr an interrupt is * + * initially issued from the II before it times out the outstanding * + * interrupt and drops it from the interrupt queue. * + * * + ************************************************************************/ + +typedef union ii_iwi_u { + shubreg_t ii_iwi_regval; + struct { + shubreg_t i_prescale : 24; + shubreg_t i_rsvd : 8; + shubreg_t i_timeout : 8; + shubreg_t i_rsvd1 : 8; + shubreg_t i_intrpt_retry_period : 8; + shubreg_t i_rsvd2 : 8; + } ii_iwi_fld_s; +} ii_iwi_u_t; + +/************************************************************************ + * * + * Log errors which have occurred in the II wrapper. The errors are * + * cleared by writing to the IECLR register. * + * * + ************************************************************************/ + +typedef union ii_iwel_u { + shubreg_t ii_iwel_regval; + struct { + shubreg_t i_intr_timed_out : 1; + shubreg_t i_rsvd : 7; + shubreg_t i_cam_overflow : 1; + shubreg_t i_cam_read_miss : 1; + shubreg_t i_rsvd1 : 2; + shubreg_t i_ioq_rep_underflow : 1; + shubreg_t i_ioq_req_underflow : 1; + shubreg_t i_ioq_rep_overflow : 1; + shubreg_t i_ioq_req_overflow : 1; + shubreg_t i_iiq_rep_overflow : 1; + shubreg_t i_iiq_req_overflow : 1; + shubreg_t i_rsvd2 : 6; + shubreg_t i_ii_xn_rep_cred_over_under: 1; + shubreg_t i_ii_xn_req_cred_over_under: 1; + shubreg_t i_rsvd3 : 6; + shubreg_t i_ii_xn_invalid_cmd : 1; + shubreg_t i_xn_ii_invalid_cmd : 1; + shubreg_t i_rsvd4 : 30; + } ii_iwel_fld_s; +} ii_iwel_u_t; + +/************************************************************************ + * * + * Controls the II wrapper. * + * * + ************************************************************************/ + +typedef union ii_iwc_u { + shubreg_t ii_iwc_regval; + struct { + shubreg_t i_dma_byte_swap : 1; + shubreg_t i_rsvd : 3; + shubreg_t i_cam_read_lines_reset : 1; + shubreg_t i_rsvd1 : 3; + shubreg_t i_ii_xn_cred_over_under_log: 1; + shubreg_t i_rsvd2 : 19; + shubreg_t i_xn_rep_iq_depth : 5; + shubreg_t i_rsvd3 : 3; + shubreg_t i_xn_req_iq_depth : 5; + shubreg_t i_rsvd4 : 3; + shubreg_t i_iiq_depth : 6; + shubreg_t i_rsvd5 : 12; + shubreg_t i_force_rep_cred : 1; + shubreg_t i_force_req_cred : 1; + } ii_iwc_fld_s; +} ii_iwc_u_t; + +/************************************************************************ + * * + * Status in the II wrapper. * + * * + ************************************************************************/ + +typedef union ii_iws_u { + shubreg_t ii_iws_regval; + struct { + shubreg_t i_xn_rep_iq_credits : 5; + shubreg_t i_rsvd : 3; + shubreg_t i_xn_req_iq_credits : 5; + shubreg_t i_rsvd1 : 51; + } ii_iws_fld_s; +} ii_iws_u_t; + +/************************************************************************ + * * + * Masks errors in the IWEL register. * + * * + ************************************************************************/ + +typedef union ii_iweim_u { + shubreg_t ii_iweim_regval; + struct { + shubreg_t i_intr_timed_out : 1; + shubreg_t i_rsvd : 7; + shubreg_t i_cam_overflow : 1; + shubreg_t i_cam_read_miss : 1; + shubreg_t i_rsvd1 : 2; + shubreg_t i_ioq_rep_underflow : 1; + shubreg_t i_ioq_req_underflow : 1; + shubreg_t i_ioq_rep_overflow : 1; + shubreg_t i_ioq_req_overflow : 1; + shubreg_t i_iiq_rep_overflow : 1; + shubreg_t i_iiq_req_overflow : 1; + shubreg_t i_rsvd2 : 6; + shubreg_t i_ii_xn_rep_cred_overflow : 1; + shubreg_t i_ii_xn_req_cred_overflow : 1; + shubreg_t i_rsvd3 : 6; + shubreg_t i_ii_xn_invalid_cmd : 1; + shubreg_t i_xn_ii_invalid_cmd : 1; + shubreg_t i_rsvd4 : 30; + } ii_iweim_fld_s; +} ii_iweim_u_t; + + +/************************************************************************ + * * + * A write to this register causes a particular field in the * + * corresponding widget's PRB entry to be adjusted up or down by 1. * + * This counter should be used when recovering from error and reset * + * conditions. Note that software would be capable of causing * + * inadvertent overflow or underflow of these counters. * + * * + ************************************************************************/ + +typedef union ii_ipca_u { + shubreg_t ii_ipca_regval; + struct { + shubreg_t i_wid : 4; + shubreg_t i_adjust : 1; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_field : 2; + shubreg_t i_rsvd : 54; + } ii_ipca_fld_s; +} ii_ipca_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + + +typedef union ii_iprte0a_u { + shubreg_t ii_iprte0a_regval; + struct { + shubreg_t i_rsvd_1 : 54; + shubreg_t i_widget : 4; + shubreg_t i_to_cnt : 5; + shubreg_t i_vld : 1; + } ii_iprte0a_fld_s; +} ii_iprte0a_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte1a_u { + shubreg_t ii_iprte1a_regval; + struct { + shubreg_t i_rsvd_1 : 54; + shubreg_t i_widget : 4; + shubreg_t i_to_cnt : 5; + shubreg_t i_vld : 1; + } ii_iprte1a_fld_s; +} ii_iprte1a_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte2a_u { + shubreg_t ii_iprte2a_regval; + struct { + shubreg_t i_rsvd_1 : 54; + shubreg_t i_widget : 4; + shubreg_t i_to_cnt : 5; + shubreg_t i_vld : 1; + } ii_iprte2a_fld_s; +} ii_iprte2a_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte3a_u { + shubreg_t ii_iprte3a_regval; + struct { + shubreg_t i_rsvd_1 : 54; + shubreg_t i_widget : 4; + shubreg_t i_to_cnt : 5; + shubreg_t i_vld : 1; + } ii_iprte3a_fld_s; +} ii_iprte3a_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte4a_u { + shubreg_t ii_iprte4a_regval; + struct { + shubreg_t i_rsvd_1 : 54; + shubreg_t i_widget : 4; + shubreg_t i_to_cnt : 5; + shubreg_t i_vld : 1; + } ii_iprte4a_fld_s; +} ii_iprte4a_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte5a_u { + shubreg_t ii_iprte5a_regval; + struct { + shubreg_t i_rsvd_1 : 54; + shubreg_t i_widget : 4; + shubreg_t i_to_cnt : 5; + shubreg_t i_vld : 1; + } ii_iprte5a_fld_s; +} ii_iprte5a_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte6a_u { + shubreg_t ii_iprte6a_regval; + struct { + shubreg_t i_rsvd_1 : 54; + shubreg_t i_widget : 4; + shubreg_t i_to_cnt : 5; + shubreg_t i_vld : 1; + } ii_iprte6a_fld_s; +} ii_iprte6a_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte7a_u { + shubreg_t ii_iprte7a_regval; + struct { + shubreg_t i_rsvd_1 : 54; + shubreg_t i_widget : 4; + shubreg_t i_to_cnt : 5; + shubreg_t i_vld : 1; + } ii_iprtea7_fld_s; +} ii_iprte7a_u_t; + + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + + +typedef union ii_iprte0b_u { + shubreg_t ii_iprte0b_regval; + struct { + shubreg_t i_rsvd_1 : 3; + shubreg_t i_address : 47; + shubreg_t i_init : 3; + shubreg_t i_source : 11; + } ii_iprte0b_fld_s; +} ii_iprte0b_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte1b_u { + shubreg_t ii_iprte1b_regval; + struct { + shubreg_t i_rsvd_1 : 3; + shubreg_t i_address : 47; + shubreg_t i_init : 3; + shubreg_t i_source : 11; + } ii_iprte1b_fld_s; +} ii_iprte1b_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte2b_u { + shubreg_t ii_iprte2b_regval; + struct { + shubreg_t i_rsvd_1 : 3; + shubreg_t i_address : 47; + shubreg_t i_init : 3; + shubreg_t i_source : 11; + } ii_iprte2b_fld_s; +} ii_iprte2b_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte3b_u { + shubreg_t ii_iprte3b_regval; + struct { + shubreg_t i_rsvd_1 : 3; + shubreg_t i_address : 47; + shubreg_t i_init : 3; + shubreg_t i_source : 11; + } ii_iprte3b_fld_s; +} ii_iprte3b_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte4b_u { + shubreg_t ii_iprte4b_regval; + struct { + shubreg_t i_rsvd_1 : 3; + shubreg_t i_address : 47; + shubreg_t i_init : 3; + shubreg_t i_source : 11; + } ii_iprte4b_fld_s; +} ii_iprte4b_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte5b_u { + shubreg_t ii_iprte5b_regval; + struct { + shubreg_t i_rsvd_1 : 3; + shubreg_t i_address : 47; + shubreg_t i_init : 3; + shubreg_t i_source : 11; + } ii_iprte5b_fld_s; +} ii_iprte5b_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte6b_u { + shubreg_t ii_iprte6b_regval; + struct { + shubreg_t i_rsvd_1 : 3; + shubreg_t i_address : 47; + shubreg_t i_init : 3; + shubreg_t i_source : 11; + + } ii_iprte6b_fld_s; +} ii_iprte6b_u_t; + + +/************************************************************************ + * * + * There are 8 instances of this register. This register contains * + * the information that the II has to remember once it has launched a * + * PIO Read operation. The contents are used to form the correct * + * Router Network packet and direct the Crosstalk reply to the * + * appropriate processor. * + * * + ************************************************************************/ + +typedef union ii_iprte7b_u { + shubreg_t ii_iprte7b_regval; + struct { + shubreg_t i_rsvd_1 : 3; + shubreg_t i_address : 47; + shubreg_t i_init : 3; + shubreg_t i_source : 11; + } ii_iprte7b_fld_s; +} ii_iprte7b_u_t; + + +/************************************************************************ + * * + * Description: SHub II contains a feature which did not exist in * + * the Hub which automatically cleans up after a Read Response * + * timeout, including deallocation of the IPRTE and recovery of IBuf * + * space. The inclusion of this register in SHub is for backward * + * compatibility * + * A write to this register causes an entry from the table of * + * outstanding PIO Read Requests to be freed and returned to the * + * stack of free entries. This register is used in handling the * + * timeout errors that result in a PIO Reply never returning from * + * Crosstalk. * + * Note that this register does not affect the contents of the IPRTE * + * registers. The Valid bits in those registers have to be * + * specifically turned off by software. * + * * + ************************************************************************/ + +typedef union ii_ipdr_u { + shubreg_t ii_ipdr_regval; + struct { + shubreg_t i_te : 3; + shubreg_t i_rsvd_1 : 1; + shubreg_t i_pnd : 1; + shubreg_t i_init_rpcnt : 1; + shubreg_t i_rsvd : 58; + } ii_ipdr_fld_s; +} ii_ipdr_u_t; + + +/************************************************************************ + * * + * A write to this register causes a CRB entry to be returned to the * + * queue of free CRBs. The entry should have previously been cleared * + * (mark bit) via backdoor access to the pertinent CRB entry. This * + * register is used in the last step of handling the errors that are * + * captured and marked in CRB entries. Briefly: 1) first error for * + * DMA write from a particular device, and first error for a * + * particular BTE stream, lead to a marked CRB entry, and processor * + * interrupt, 2) software reads the error information captured in the * + * CRB entry, and presumably takes some corrective action, 3) * + * software clears the mark bit, and finally 4) software writes to * + * the ICDR register to return the CRB entry to the list of free CRB * + * entries. * + * * + ************************************************************************/ + +typedef union ii_icdr_u { + shubreg_t ii_icdr_regval; + struct { + shubreg_t i_crb_num : 4; + shubreg_t i_pnd : 1; + shubreg_t i_rsvd : 59; + } ii_icdr_fld_s; +} ii_icdr_u_t; + + +/************************************************************************ + * * + * This register provides debug access to two FIFOs inside of II. * + * Both IOQ_MAX* fields of this register contain the instantaneous * + * depth (in units of the number of available entries) of the * + * associated IOQ FIFO. A read of this register will return the * + * number of free entries on each FIFO at the time of the read. So * + * when a FIFO is idle, the associated field contains the maximum * + * depth of the FIFO. This register is writable for debug reasons * + * and is intended to be written with the maximum desired FIFO depth * + * while the FIFO is idle. Software must assure that II is idle when * + * this register is written. If there are any active entries in any * + * of these FIFOs when this register is written, the results are * + * undefined. * + * * + ************************************************************************/ + +typedef union ii_ifdr_u { + shubreg_t ii_ifdr_regval; + struct { + shubreg_t i_ioq_max_rq : 7; + shubreg_t i_set_ioq_rq : 1; + shubreg_t i_ioq_max_rp : 7; + shubreg_t i_set_ioq_rp : 1; + shubreg_t i_rsvd : 48; + } ii_ifdr_fld_s; +} ii_ifdr_u_t; + + +/************************************************************************ + * * + * This register allows the II to become sluggish in removing * + * messages from its inbound queue (IIQ). This will cause messages to * + * back up in either virtual channel. Disabling the "molasses" mode * + * subsequently allows the II to be tested under stress. In the * + * sluggish ("Molasses") mode, the localized effects of congestion * + * can be observed. * + * * + ************************************************************************/ + +typedef union ii_iiap_u { + shubreg_t ii_iiap_regval; + struct { + shubreg_t i_rq_mls : 6; + shubreg_t i_rsvd_1 : 2; + shubreg_t i_rp_mls : 6; + shubreg_t i_rsvd : 50; + } ii_iiap_fld_s; +} ii_iiap_u_t; + + +/************************************************************************ + * * + * This register allows several parameters of CRB operation to be * + * set. Note that writing to this register can have catastrophic side * + * effects, if the CRB is not quiescent, i.e. if the CRB is * + * processing protocol messages when the write occurs. * + * * + ************************************************************************/ + +typedef union ii_icmr_u { + shubreg_t ii_icmr_regval; + struct { + shubreg_t i_sp_msg : 1; + shubreg_t i_rd_hdr : 1; + shubreg_t i_rsvd_4 : 2; + shubreg_t i_c_cnt : 4; + shubreg_t i_rsvd_3 : 4; + shubreg_t i_clr_rqpd : 1; + shubreg_t i_clr_rppd : 1; + shubreg_t i_rsvd_2 : 2; + shubreg_t i_fc_cnt : 4; + shubreg_t i_crb_vld : 15; + shubreg_t i_crb_mark : 15; + shubreg_t i_rsvd_1 : 2; + shubreg_t i_precise : 1; + shubreg_t i_rsvd : 11; + } ii_icmr_fld_s; +} ii_icmr_u_t; + + +/************************************************************************ + * * + * This register allows control of the table portion of the CRB * + * logic via software. Control operations from this register have * + * priority over all incoming Crosstalk or BTE requests. * + * * + ************************************************************************/ + +typedef union ii_iccr_u { + shubreg_t ii_iccr_regval; + struct { + shubreg_t i_crb_num : 4; + shubreg_t i_rsvd_1 : 4; + shubreg_t i_cmd : 8; + shubreg_t i_pending : 1; + shubreg_t i_rsvd : 47; + } ii_iccr_fld_s; +} ii_iccr_u_t; + + +/************************************************************************ + * * + * This register allows the maximum timeout value to be programmed. * + * * + ************************************************************************/ + +typedef union ii_icto_u { + shubreg_t ii_icto_regval; + struct { + shubreg_t i_timeout : 8; + shubreg_t i_rsvd : 56; + } ii_icto_fld_s; +} ii_icto_u_t; + + +/************************************************************************ + * * + * This register allows the timeout prescalar to be programmed. An * + * internal counter is associated with this register. When the * + * internal counter reaches the value of the PRESCALE field, the * + * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT] * + * field). The internal counter resets to zero, and then continues * + * counting. * + * * + ************************************************************************/ + +typedef union ii_ictp_u { + shubreg_t ii_ictp_regval; + struct { + shubreg_t i_prescale : 24; + shubreg_t i_rsvd : 40; + } ii_ictp_fld_s; +} ii_ictp_u_t; + + +/************************************************************************ + * * + * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * + * used for Crosstalk operations (both cacheline and partial * + * operations) or BTE/IO. Because the CRB entries are very wide, five * + * registers (_A to _E) are required to read and write each entry. * + * The CRB Entry registers can be conceptualized as rows and columns * + * (illustrated in the table above). Each row contains the 4 * + * registers required for a single CRB Entry. The first doubleword * + * (column) for each entry is labeled A, and the second doubleword * + * (higher address) is labeled B, the third doubleword is labeled C, * + * the fourth doubleword is labeled D and the fifth doubleword is * + * labeled E. All CRB entries have their addresses on a quarter * + * cacheline aligned boundary. * + * Upon reset, only the following fields are initialized: valid * + * (VLD), priority count, timeout, timeout valid, and context valid. * + * All other bits should be cleared by software before use (after * + * recovering any potential error state from before the reset). * + * The following four tables summarize the format for the four * + * registers that are used for each ICRB# Entry. * + * * + ************************************************************************/ + +typedef union ii_icrb0_a_u { + shubreg_t ii_icrb0_a_regval; + struct { + shubreg_t ia_iow : 1; + shubreg_t ia_vld : 1; + shubreg_t ia_addr : 47; + shubreg_t ia_tnum : 5; + shubreg_t ia_sidn : 4; + shubreg_t ia_rsvd : 6; + } ii_icrb0_a_fld_s; +} ii_icrb0_a_u_t; + + +/************************************************************************ + * * + * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * + * used for Crosstalk operations (both cacheline and partial * + * operations) or BTE/IO. Because the CRB entries are very wide, five * + * registers (_A to _E) are required to read and write each entry. * + * * + ************************************************************************/ + +typedef union ii_icrb0_b_u { + shubreg_t ii_icrb0_b_regval; + struct { + shubreg_t ib_xt_err : 1; + shubreg_t ib_mark : 1; + shubreg_t ib_ln_uce : 1; + shubreg_t ib_errcode : 3; + shubreg_t ib_error : 1; + shubreg_t ib_stall__bte_1 : 1; + shubreg_t ib_stall__bte_0 : 1; + shubreg_t ib_stall__intr : 1; + shubreg_t ib_stall_ib : 1; + shubreg_t ib_intvn : 1; + shubreg_t ib_wb : 1; + shubreg_t ib_hold : 1; + shubreg_t ib_ack : 1; + shubreg_t ib_resp : 1; + shubreg_t ib_ack_cnt : 11; + shubreg_t ib_rsvd : 7; + shubreg_t ib_exc : 5; + shubreg_t ib_init : 3; + shubreg_t ib_imsg : 8; + shubreg_t ib_imsgtype : 2; + shubreg_t ib_use_old : 1; + shubreg_t ib_rsvd_1 : 11; + } ii_icrb0_b_fld_s; +} ii_icrb0_b_u_t; + + +/************************************************************************ + * * + * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * + * used for Crosstalk operations (both cacheline and partial * + * operations) or BTE/IO. Because the CRB entries are very wide, five * + * registers (_A to _E) are required to read and write each entry. * + * * + ************************************************************************/ + +typedef union ii_icrb0_c_u { + shubreg_t ii_icrb0_c_regval; + struct { + shubreg_t ic_source : 15; + shubreg_t ic_size : 2; + shubreg_t ic_ct : 1; + shubreg_t ic_bte_num : 1; + shubreg_t ic_gbr : 1; + shubreg_t ic_resprqd : 1; + shubreg_t ic_bo : 1; + shubreg_t ic_suppl : 15; + shubreg_t ic_rsvd : 27; + } ii_icrb0_c_fld_s; +} ii_icrb0_c_u_t; + + +/************************************************************************ + * * + * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * + * used for Crosstalk operations (both cacheline and partial * + * operations) or BTE/IO. Because the CRB entries are very wide, five * + * registers (_A to _E) are required to read and write each entry. * + * * + ************************************************************************/ + +typedef union ii_icrb0_d_u { + shubreg_t ii_icrb0_d_regval; + struct { + shubreg_t id_pa_be : 43; + shubreg_t id_bte_op : 1; + shubreg_t id_pr_psc : 4; + shubreg_t id_pr_cnt : 4; + shubreg_t id_sleep : 1; + shubreg_t id_rsvd : 11; + } ii_icrb0_d_fld_s; +} ii_icrb0_d_u_t; + + +/************************************************************************ + * * + * Description: There are 15 CRB Entries (ICRB0 to ICRBE) that are * + * used for Crosstalk operations (both cacheline and partial * + * operations) or BTE/IO. Because the CRB entries are very wide, five * + * registers (_A to _E) are required to read and write each entry. * + * * + ************************************************************************/ + +typedef union ii_icrb0_e_u { + shubreg_t ii_icrb0_e_regval; + struct { + shubreg_t ie_timeout : 8; + shubreg_t ie_context : 15; + shubreg_t ie_rsvd : 1; + shubreg_t ie_tvld : 1; + shubreg_t ie_cvld : 1; + shubreg_t ie_rsvd_0 : 38; + } ii_icrb0_e_fld_s; +} ii_icrb0_e_u_t; + + +/************************************************************************ + * * + * This register contains the lower 64 bits of the header of the * + * spurious message captured by II. Valid when the SP_MSG bit in ICMR * + * register is set. * + * * + ************************************************************************/ + +typedef union ii_icsml_u { + shubreg_t ii_icsml_regval; + struct { + shubreg_t i_tt_addr : 47; + shubreg_t i_newsuppl_ex : 14; + shubreg_t i_reserved : 2; + shubreg_t i_overflow : 1; + } ii_icsml_fld_s; +} ii_icsml_u_t; + + +/************************************************************************ + * * + * This register contains the middle 64 bits of the header of the * + * spurious message captured by II. Valid when the SP_MSG bit in ICMR * + * register is set. * + * * + ************************************************************************/ + +typedef union ii_icsmm_u { + shubreg_t ii_icsmm_regval; + struct { + shubreg_t i_tt_ack_cnt : 11; + shubreg_t i_reserved : 53; + } ii_icsmm_fld_s; +} ii_icsmm_u_t; + + +/************************************************************************ + * * + * This register contains the microscopic state, all the inputs to * + * the protocol table, captured with the spurious message. Valid when * + * the SP_MSG bit in the ICMR register is set. * + * * + ************************************************************************/ + +typedef union ii_icsmh_u { + shubreg_t ii_icsmh_regval; + struct { + shubreg_t i_tt_vld : 1; + shubreg_t i_xerr : 1; + shubreg_t i_ft_cwact_o : 1; + shubreg_t i_ft_wact_o : 1; + shubreg_t i_ft_active_o : 1; + shubreg_t i_sync : 1; + shubreg_t i_mnusg : 1; + shubreg_t i_mnusz : 1; + shubreg_t i_plusz : 1; + shubreg_t i_plusg : 1; + shubreg_t i_tt_exc : 5; + shubreg_t i_tt_wb : 1; + shubreg_t i_tt_hold : 1; + shubreg_t i_tt_ack : 1; + shubreg_t i_tt_resp : 1; + shubreg_t i_tt_intvn : 1; + shubreg_t i_g_stall_bte1 : 1; + shubreg_t i_g_stall_bte0 : 1; + shubreg_t i_g_stall_il : 1; + shubreg_t i_g_stall_ib : 1; + shubreg_t i_tt_imsg : 8; + shubreg_t i_tt_imsgtype : 2; + shubreg_t i_tt_use_old : 1; + shubreg_t i_tt_respreqd : 1; + shubreg_t i_tt_bte_num : 1; + shubreg_t i_cbn : 1; + shubreg_t i_match : 1; + shubreg_t i_rpcnt_lt_34 : 1; + shubreg_t i_rpcnt_ge_34 : 1; + shubreg_t i_rpcnt_lt_18 : 1; + shubreg_t i_rpcnt_ge_18 : 1; + shubreg_t i_rpcnt_lt_2 : 1; + shubreg_t i_rpcnt_ge_2 : 1; + shubreg_t i_rqcnt_lt_18 : 1; + shubreg_t i_rqcnt_ge_18 : 1; + shubreg_t i_rqcnt_lt_2 : 1; + shubreg_t i_rqcnt_ge_2 : 1; + shubreg_t i_tt_device : 7; + shubreg_t i_tt_init : 3; + shubreg_t i_reserved : 5; + } ii_icsmh_fld_s; +} ii_icsmh_u_t; + + +/************************************************************************ + * * + * The Shub DEBUG unit provides a 3-bit selection signal to the * + * II core and a 3-bit selection signal to the fsbclk domain in the II * + * wrapper. * + * * + ************************************************************************/ + +typedef union ii_idbss_u { + shubreg_t ii_idbss_regval; + struct { + shubreg_t i_iioclk_core_submenu : 3; + shubreg_t i_rsvd : 5; + shubreg_t i_fsbclk_wrapper_submenu : 3; + shubreg_t i_rsvd_1 : 5; + shubreg_t i_iioclk_menu : 5; + shubreg_t i_rsvd_2 : 43; + } ii_idbss_fld_s; +} ii_idbss_u_t; + + +/************************************************************************ + * * + * Description: This register is used to set up the length for a * + * transfer and then to monitor the progress of that transfer. This * + * register needs to be initialized before a transfer is started. A * + * legitimate write to this register will set the Busy bit, clear the * + * Error bit, and initialize the length to the value desired. * + * While the transfer is in progress, hardware will decrement the * + * length field with each successful block that is copied. Once the * + * transfer completes, hardware will clear the Busy bit. The length * + * field will also contain the number of cache lines left to be * + * transferred. * + * * + ************************************************************************/ + +typedef union ii_ibls0_u { + shubreg_t ii_ibls0_regval; + struct { + shubreg_t i_length : 16; + shubreg_t i_error : 1; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_busy : 1; + shubreg_t i_rsvd : 43; + } ii_ibls0_fld_s; +} ii_ibls0_u_t; + + +/************************************************************************ + * * + * This register should be loaded before a transfer is started. The * + * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * + * address as described in Section 1.3, Figure2 and Figure3. Since * + * the bottom 7 bits of the address are always taken to be zero, BTE * + * transfers are always cacheline-aligned. * + * * + ************************************************************************/ + +typedef union ii_ibsa0_u { + shubreg_t ii_ibsa0_regval; + struct { + shubreg_t i_rsvd_1 : 7; + shubreg_t i_addr : 42; + shubreg_t i_rsvd : 15; + } ii_ibsa0_fld_s; +} ii_ibsa0_u_t; + + +/************************************************************************ + * * + * This register should be loaded before a transfer is started. The * + * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * + * address as described in Section 1.3, Figure2 and Figure3. Since * + * the bottom 7 bits of the address are always taken to be zero, BTE * + * transfers are always cacheline-aligned. * + * * + ************************************************************************/ + +typedef union ii_ibda0_u { + shubreg_t ii_ibda0_regval; + struct { + shubreg_t i_rsvd_1 : 7; + shubreg_t i_addr : 42; + shubreg_t i_rsvd : 15; + } ii_ibda0_fld_s; +} ii_ibda0_u_t; + + +/************************************************************************ + * * + * Writing to this register sets up the attributes of the transfer * + * and initiates the transfer operation. Reading this register has * + * the side effect of terminating any transfer in progress. Note: * + * stopping a transfer midstream could have an adverse impact on the * + * other BTE. If a BTE stream has to be stopped (due to error * + * handling for example), both BTE streams should be stopped and * + * their transfers discarded. * + * * + ************************************************************************/ + +typedef union ii_ibct0_u { + shubreg_t ii_ibct0_regval; + struct { + shubreg_t i_zerofill : 1; + shubreg_t i_rsvd_2 : 3; + shubreg_t i_notify : 1; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_poison : 1; + shubreg_t i_rsvd : 55; + } ii_ibct0_fld_s; +} ii_ibct0_u_t; + + +/************************************************************************ + * * + * This register contains the address to which the WINV is sent. * + * This address has to be cache line aligned. * + * * + ************************************************************************/ + +typedef union ii_ibna0_u { + shubreg_t ii_ibna0_regval; + struct { + shubreg_t i_rsvd_1 : 7; + shubreg_t i_addr : 42; + shubreg_t i_rsvd : 15; + } ii_ibna0_fld_s; +} ii_ibna0_u_t; + + +/************************************************************************ + * * + * This register contains the programmable level as well as the node * + * ID and PI unit of the processor to which the interrupt will be * + * sent. * + * * + ************************************************************************/ + +typedef union ii_ibia0_u { + shubreg_t ii_ibia0_regval; + struct { + shubreg_t i_rsvd_2 : 1; + shubreg_t i_node_id : 11; + shubreg_t i_rsvd_1 : 4; + shubreg_t i_level : 7; + shubreg_t i_rsvd : 41; + } ii_ibia0_fld_s; +} ii_ibia0_u_t; + + +/************************************************************************ + * * + * Description: This register is used to set up the length for a * + * transfer and then to monitor the progress of that transfer. This * + * register needs to be initialized before a transfer is started. A * + * legitimate write to this register will set the Busy bit, clear the * + * Error bit, and initialize the length to the value desired. * + * While the transfer is in progress, hardware will decrement the * + * length field with each successful block that is copied. Once the * + * transfer completes, hardware will clear the Busy bit. The length * + * field will also contain the number of cache lines left to be * + * transferred. * + * * + ************************************************************************/ + +typedef union ii_ibls1_u { + shubreg_t ii_ibls1_regval; + struct { + shubreg_t i_length : 16; + shubreg_t i_error : 1; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_busy : 1; + shubreg_t i_rsvd : 43; + } ii_ibls1_fld_s; +} ii_ibls1_u_t; + + +/************************************************************************ + * * + * This register should be loaded before a transfer is started. The * + * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * + * address as described in Section 1.3, Figure2 and Figure3. Since * + * the bottom 7 bits of the address are always taken to be zero, BTE * + * transfers are always cacheline-aligned. * + * * + ************************************************************************/ + +typedef union ii_ibsa1_u { + shubreg_t ii_ibsa1_regval; + struct { + shubreg_t i_rsvd_1 : 7; + shubreg_t i_addr : 33; + shubreg_t i_rsvd : 24; + } ii_ibsa1_fld_s; +} ii_ibsa1_u_t; + + +/************************************************************************ + * * + * This register should be loaded before a transfer is started. The * + * address to be loaded in bits 39:0 is the 40-bit TRex+ physical * + * address as described in Section 1.3, Figure2 and Figure3. Since * + * the bottom 7 bits of the address are always taken to be zero, BTE * + * transfers are always cacheline-aligned. * + * * + ************************************************************************/ + +typedef union ii_ibda1_u { + shubreg_t ii_ibda1_regval; + struct { + shubreg_t i_rsvd_1 : 7; + shubreg_t i_addr : 33; + shubreg_t i_rsvd : 24; + } ii_ibda1_fld_s; +} ii_ibda1_u_t; + + +/************************************************************************ + * * + * Writing to this register sets up the attributes of the transfer * + * and initiates the transfer operation. Reading this register has * + * the side effect of terminating any transfer in progress. Note: * + * stopping a transfer midstream could have an adverse impact on the * + * other BTE. If a BTE stream has to be stopped (due to error * + * handling for example), both BTE streams should be stopped and * + * their transfers discarded. * + * * + ************************************************************************/ + +typedef union ii_ibct1_u { + shubreg_t ii_ibct1_regval; + struct { + shubreg_t i_zerofill : 1; + shubreg_t i_rsvd_2 : 3; + shubreg_t i_notify : 1; + shubreg_t i_rsvd_1 : 3; + shubreg_t i_poison : 1; + shubreg_t i_rsvd : 55; + } ii_ibct1_fld_s; +} ii_ibct1_u_t; + + +/************************************************************************ + * * + * This register contains the address to which the WINV is sent. * + * This address has to be cache line aligned. * + * * + ************************************************************************/ + +typedef union ii_ibna1_u { + shubreg_t ii_ibna1_regval; + struct { + shubreg_t i_rsvd_1 : 7; + shubreg_t i_addr : 33; + shubreg_t i_rsvd : 24; + } ii_ibna1_fld_s; +} ii_ibna1_u_t; + + +/************************************************************************ + * * + * This register contains the programmable level as well as the node * + * ID and PI unit of the processor to which the interrupt will be * + * sent. * + * * + ************************************************************************/ + +typedef union ii_ibia1_u { + shubreg_t ii_ibia1_regval; + struct { + shubreg_t i_pi_id : 1; + shubreg_t i_node_id : 8; + shubreg_t i_rsvd_1 : 7; + shubreg_t i_level : 7; + shubreg_t i_rsvd : 41; + } ii_ibia1_fld_s; +} ii_ibia1_u_t; + + +/************************************************************************ + * * + * This register defines the resources that feed information into * + * the two performance counters located in the IO Performance * + * Profiling Register. There are 17 different quantities that can be * + * measured. Given these 17 different options, the two performance * + * counters have 15 of them in common; menu selections 0 through 0xE * + * are identical for each performance counter. As for the other two * + * options, one is available from one performance counter and the * + * other is available from the other performance counter. Hence, the * + * II supports all 17*16=272 possible combinations of quantities to * + * measure. * + * * + ************************************************************************/ + +typedef union ii_ipcr_u { + shubreg_t ii_ipcr_regval; + struct { + shubreg_t i_ippr0_c : 4; + shubreg_t i_ippr1_c : 4; + shubreg_t i_icct : 8; + shubreg_t i_rsvd : 48; + } ii_ipcr_fld_s; +} ii_ipcr_u_t; + + +/************************************************************************ + * * + * * + * * + ************************************************************************/ + +typedef union ii_ippr_u { + shubreg_t ii_ippr_regval; + struct { + shubreg_t i_ippr0 : 32; + shubreg_t i_ippr1 : 32; + } ii_ippr_fld_s; +} ii_ippr_u_t; + + +#endif /* __ASSEMBLY__ */ + +/************************************************************************** + * * + * The following defines which were not formed into structures are * + * probably indentical to another register, and the name of the * + * register is provided against each of these registers. This * + * information needs to be checked carefully * + * * + * IIO_ICRB1_A IIO_ICRB0_A * + * IIO_ICRB1_B IIO_ICRB0_B * + * IIO_ICRB1_C IIO_ICRB0_C * + * IIO_ICRB1_D IIO_ICRB0_D * + * IIO_ICRB1_E IIO_ICRB0_E * + * IIO_ICRB2_A IIO_ICRB0_A * + * IIO_ICRB2_B IIO_ICRB0_B * + * IIO_ICRB2_C IIO_ICRB0_C * + * IIO_ICRB2_D IIO_ICRB0_D * + * IIO_ICRB2_E IIO_ICRB0_E * + * IIO_ICRB3_A IIO_ICRB0_A * + * IIO_ICRB3_B IIO_ICRB0_B * + * IIO_ICRB3_C IIO_ICRB0_C * + * IIO_ICRB3_D IIO_ICRB0_D * + * IIO_ICRB3_E IIO_ICRB0_E * + * IIO_ICRB4_A IIO_ICRB0_A * + * IIO_ICRB4_B IIO_ICRB0_B * + * IIO_ICRB4_C IIO_ICRB0_C * + * IIO_ICRB4_D IIO_ICRB0_D * + * IIO_ICRB4_E IIO_ICRB0_E * + * IIO_ICRB5_A IIO_ICRB0_A * + * IIO_ICRB5_B IIO_ICRB0_B * + * IIO_ICRB5_C IIO_ICRB0_C * + * IIO_ICRB5_D IIO_ICRB0_D * + * IIO_ICRB5_E IIO_ICRB0_E * + * IIO_ICRB6_A IIO_ICRB0_A * + * IIO_ICRB6_B IIO_ICRB0_B * + * IIO_ICRB6_C IIO_ICRB0_C * + * IIO_ICRB6_D IIO_ICRB0_D * + * IIO_ICRB6_E IIO_ICRB0_E * + * IIO_ICRB7_A IIO_ICRB0_A * + * IIO_ICRB7_B IIO_ICRB0_B * + * IIO_ICRB7_C IIO_ICRB0_C * + * IIO_ICRB7_D IIO_ICRB0_D * + * IIO_ICRB7_E IIO_ICRB0_E * + * IIO_ICRB8_A IIO_ICRB0_A * + * IIO_ICRB8_B IIO_ICRB0_B * + * IIO_ICRB8_C IIO_ICRB0_C * + * IIO_ICRB8_D IIO_ICRB0_D * + * IIO_ICRB8_E IIO_ICRB0_E * + * IIO_ICRB9_A IIO_ICRB0_A * + * IIO_ICRB9_B IIO_ICRB0_B * + * IIO_ICRB9_C IIO_ICRB0_C * + * IIO_ICRB9_D IIO_ICRB0_D * + * IIO_ICRB9_E IIO_ICRB0_E * + * IIO_ICRBA_A IIO_ICRB0_A * + * IIO_ICRBA_B IIO_ICRB0_B * + * IIO_ICRBA_C IIO_ICRB0_C * + * IIO_ICRBA_D IIO_ICRB0_D * + * IIO_ICRBA_E IIO_ICRB0_E * + * IIO_ICRBB_A IIO_ICRB0_A * + * IIO_ICRBB_B IIO_ICRB0_B * + * IIO_ICRBB_C IIO_ICRB0_C * + * IIO_ICRBB_D IIO_ICRB0_D * + * IIO_ICRBB_E IIO_ICRB0_E * + * IIO_ICRBC_A IIO_ICRB0_A * + * IIO_ICRBC_B IIO_ICRB0_B * + * IIO_ICRBC_C IIO_ICRB0_C * + * IIO_ICRBC_D IIO_ICRB0_D * + * IIO_ICRBC_E IIO_ICRB0_E * + * IIO_ICRBD_A IIO_ICRB0_A * + * IIO_ICRBD_B IIO_ICRB0_B * + * IIO_ICRBD_C IIO_ICRB0_C * + * IIO_ICRBD_D IIO_ICRB0_D * + * IIO_ICRBD_E IIO_ICRB0_E * + * IIO_ICRBE_A IIO_ICRB0_A * + * IIO_ICRBE_B IIO_ICRB0_B * + * IIO_ICRBE_C IIO_ICRB0_C * + * IIO_ICRBE_D IIO_ICRB0_D * + * IIO_ICRBE_E IIO_ICRB0_E * + * * + **************************************************************************/ + + +/* + * Slightly friendlier names for some common registers. + */ +#define IIO_WIDGET IIO_WID /* Widget identification */ +#define IIO_WIDGET_STAT IIO_WSTAT /* Widget status register */ +#define IIO_WIDGET_CTRL IIO_WCR /* Widget control register */ +#define IIO_PROTECT IIO_ILAPR /* IO interface protection */ +#define IIO_PROTECT_OVRRD IIO_ILAPO /* IO protect override */ +#define IIO_OUTWIDGET_ACCESS IIO_IOWA /* Outbound widget access */ +#define IIO_INWIDGET_ACCESS IIO_IIWA /* Inbound widget access */ +#define IIO_INDEV_ERR_MASK IIO_IIDEM /* Inbound device error mask */ +#define IIO_LLP_CSR IIO_ILCSR /* LLP control and status */ +#define IIO_LLP_LOG IIO_ILLR /* LLP log */ +#define IIO_XTALKCC_TOUT IIO_IXCC /* Xtalk credit count timeout*/ +#define IIO_XTALKTT_TOUT IIO_IXTT /* Xtalk tail timeout */ +#define IIO_IO_ERR_CLR IIO_IECLR /* IO error clear */ +#define IIO_IGFX_0 IIO_IGFX0 +#define IIO_IGFX_1 IIO_IGFX1 +#define IIO_IBCT_0 IIO_IBCT0 +#define IIO_IBCT_1 IIO_IBCT1 +#define IIO_IBLS_0 IIO_IBLS0 +#define IIO_IBLS_1 IIO_IBLS1 +#define IIO_IBSA_0 IIO_IBSA0 +#define IIO_IBSA_1 IIO_IBSA1 +#define IIO_IBDA_0 IIO_IBDA0 +#define IIO_IBDA_1 IIO_IBDA1 +#define IIO_IBNA_0 IIO_IBNA0 +#define IIO_IBNA_1 IIO_IBNA1 +#define IIO_IBIA_0 IIO_IBIA0 +#define IIO_IBIA_1 IIO_IBIA1 +#define IIO_IOPRB_0 IIO_IPRB0 + +#define IIO_PRTE_A(_x) (IIO_IPRTE0_A + (8 * (_x))) +#define IIO_PRTE_B(_x) (IIO_IPRTE0_B + (8 * (_x))) +#define IIO_NUM_PRTES 8 /* Total number of PRB table entries */ +#define IIO_WIDPRTE_A(x) IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */ +#define IIO_WIDPRTE_B(x) IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */ + +#define IIO_NUM_IPRBS (9) + +#define IIO_LLP_CSR_IS_UP 0x00002000 +#define IIO_LLP_CSR_LLP_STAT_MASK 0x00003000 +#define IIO_LLP_CSR_LLP_STAT_SHFT 12 + +#define IIO_LLP_CB_MAX 0xffff /* in ILLR CB_CNT, Max Check Bit errors */ +#define IIO_LLP_SN_MAX 0xffff /* in ILLR SN_CNT, Max Sequence Number errors */ + +/* key to IIO_PROTECT_OVRRD */ +#define IIO_PROTECT_OVRRD_KEY 0x53474972756c6573ull /* "SGIrules" */ + +/* BTE register names */ +#define IIO_BTE_STAT_0 IIO_IBLS_0 /* Also BTE length/status 0 */ +#define IIO_BTE_SRC_0 IIO_IBSA_0 /* Also BTE source address 0 */ +#define IIO_BTE_DEST_0 IIO_IBDA_0 /* Also BTE dest. address 0 */ +#define IIO_BTE_CTRL_0 IIO_IBCT_0 /* Also BTE control/terminate 0 */ +#define IIO_BTE_NOTIFY_0 IIO_IBNA_0 /* Also BTE notification 0 */ +#define IIO_BTE_INT_0 IIO_IBIA_0 /* Also BTE interrupt 0 */ +#define IIO_BTE_OFF_0 0 /* Base offset from BTE 0 regs. */ +#define IIO_BTE_OFF_1 (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */ + +/* BTE register offsets from base */ +#define BTEOFF_STAT 0 +#define BTEOFF_SRC (IIO_BTE_SRC_0 - IIO_BTE_STAT_0) +#define BTEOFF_DEST (IIO_BTE_DEST_0 - IIO_BTE_STAT_0) +#define BTEOFF_CTRL (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0) +#define BTEOFF_NOTIFY (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0) +#define BTEOFF_INT (IIO_BTE_INT_0 - IIO_BTE_STAT_0) + + +/* names used in shub diags */ +#define IIO_BASE_BTE0 IIO_IBLS_0 +#define IIO_BASE_BTE1 IIO_IBLS_1 + +/* + * Macro which takes the widget number, and returns the + * IO PRB address of that widget. + * value _x is expected to be a widget number in the range + * 0, 8 - 0xF + */ +#define IIO_IOPRB(_x) (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \ + (_x) : \ + (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) ) + + +/* GFX Flow Control Node/Widget Register */ +#define IIO_IGFX_W_NUM_BITS 4 /* size of widget num field */ +#define IIO_IGFX_W_NUM_MASK ((1<<IIO_IGFX_W_NUM_BITS)-1) +#define IIO_IGFX_W_NUM_SHIFT 0 +#define IIO_IGFX_PI_NUM_BITS 1 /* size of PI num field */ +#define IIO_IGFX_PI_NUM_MASK ((1<<IIO_IGFX_PI_NUM_BITS)-1) +#define IIO_IGFX_PI_NUM_SHIFT 4 +#define IIO_IGFX_N_NUM_BITS 8 /* size of node num field */ +#define IIO_IGFX_N_NUM_MASK ((1<<IIO_IGFX_N_NUM_BITS)-1) +#define IIO_IGFX_N_NUM_SHIFT 5 +#define IIO_IGFX_P_NUM_BITS 1 /* size of processor num field */ +#define IIO_IGFX_P_NUM_MASK ((1<<IIO_IGFX_P_NUM_BITS)-1) +#define IIO_IGFX_P_NUM_SHIFT 16 +#define IIO_IGFX_INIT(widget, pi, node, cpu) (\ + (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) | \ + (((pi) & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)| \ + (((node) & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) | \ + (((cpu) & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT)) + + +/* Scratch registers (all bits available) */ +#define IIO_SCRATCH_REG0 IIO_ISCR0 +#define IIO_SCRATCH_REG1 IIO_ISCR1 +#define IIO_SCRATCH_MASK 0xffffffffffffffff + +#define IIO_SCRATCH_BIT0_0 0x0000000000000001 +#define IIO_SCRATCH_BIT0_1 0x0000000000000002 +#define IIO_SCRATCH_BIT0_2 0x0000000000000004 +#define IIO_SCRATCH_BIT0_3 0x0000000000000008 +#define IIO_SCRATCH_BIT0_4 0x0000000000000010 +#define IIO_SCRATCH_BIT0_5 0x0000000000000020 +#define IIO_SCRATCH_BIT0_6 0x0000000000000040 +#define IIO_SCRATCH_BIT0_7 0x0000000000000080 +#define IIO_SCRATCH_BIT0_8 0x0000000000000100 +#define IIO_SCRATCH_BIT0_9 0x0000000000000200 +#define IIO_SCRATCH_BIT0_A 0x0000000000000400 + +#define IIO_SCRATCH_BIT1_0 0x0000000000000001 +#define IIO_SCRATCH_BIT1_1 0x0000000000000002 +/* IO Translation Table Entries */ +#define IIO_NUM_ITTES 7 /* ITTEs numbered 0..6 */ + /* Hw manuals number them 1..7! */ +/* + * IIO_IMEM Register fields. + */ +#define IIO_IMEM_W0ESD 0x1 /* Widget 0 shut down due to error */ +#define IIO_IMEM_B0ESD (1 << 4) /* BTE 0 shut down due to error */ +#define IIO_IMEM_B1ESD (1 << 8) /* BTE 1 Shut down due to error */ + +/* + * As a permanent workaround for a bug in the PI side of the shub, we've + * redefined big window 7 as small window 0. + XXX does this still apply for SN1?? + */ +#define HUB_NUM_BIG_WINDOW (IIO_NUM_ITTES - 1) + +/* + * Use the top big window as a surrogate for the first small window + */ +#define SWIN0_BIGWIN HUB_NUM_BIG_WINDOW + +#define ILCSR_WARM_RESET 0x100 + +/* + * CRB manipulation macros + * The CRB macros are slightly complicated, since there are up to + * four registers associated with each CRB entry. + */ +#define IIO_NUM_CRBS 15 /* Number of CRBs */ +#define IIO_NUM_PC_CRBS 4 /* Number of partial cache CRBs */ +#define IIO_ICRB_OFFSET 8 +#define IIO_ICRB_0 IIO_ICRB0_A +#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */ +/* XXX - This is now tuneable: + #define IIO_FIRST_PC_ENTRY 12 + */ + +#define IIO_ICRB_A(_x) (IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))) +#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET) +#define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET) +#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET) +#define IIO_ICRB_E(_x) (IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET) + +#define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7) + +/* + * values for "ecode" field + */ +#define IIO_ICRB_ECODE_DERR 0 /* Directory error due to IIO access */ +#define IIO_ICRB_ECODE_PERR 1 /* Poison error on IO access */ +#define IIO_ICRB_ECODE_WERR 2 /* Write error by IIO access + * e.g. WINV to a Read only line. */ +#define IIO_ICRB_ECODE_AERR 3 /* Access error caused by IIO access */ +#define IIO_ICRB_ECODE_PWERR 4 /* Error on partial write */ +#define IIO_ICRB_ECODE_PRERR 5 /* Error on partial read */ +#define IIO_ICRB_ECODE_TOUT 6 /* CRB timeout before deallocating */ +#define IIO_ICRB_ECODE_XTERR 7 /* Incoming xtalk pkt had error bit */ + +/* + * Values for field imsgtype + */ +#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ +#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ +#define IIO_ICRB_IMSGT_SN1NET 2 /* Incoming message from SN1 net */ +#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ + +/* + * values for field initiator. + */ +#define IIO_ICRB_INIT_XTALK 0 /* Message originated in xtalk */ +#define IIO_ICRB_INIT_BTE0 0x1 /* Message originated in BTE 0 */ +#define IIO_ICRB_INIT_SN1NET 0x2 /* Message originated in SN1net */ +#define IIO_ICRB_INIT_CRB 0x3 /* Message originated in CRB ? */ +#define IIO_ICRB_INIT_BTE1 0x5 /* MEssage originated in BTE 1 */ + +/* + * Number of credits Hub widget has while sending req/response to + * xbow. + * Value of 3 is required by Xbow 1.1 + * We may be able to increase this to 4 with Xbow 1.2. + */ +#define HUBII_XBOW_CREDIT 3 +#define HUBII_XBOW_REV2_CREDIT 4 + +/* + * Number of credits that xtalk devices should use when communicating + * with a SHub (depth of SHub's queue). + */ +#define HUB_CREDIT 4 + +/* + * Some IIO_PRB fields + */ +#define IIO_PRB_MULTI_ERR (1LL << 63) +#define IIO_PRB_SPUR_RD (1LL << 51) +#define IIO_PRB_SPUR_WR (1LL << 50) +#define IIO_PRB_RD_TO (1LL << 49) +#define IIO_PRB_ERROR (1LL << 48) + +/************************************************************************* + + Some of the IIO field masks and shifts are defined here. + This is in order to maintain compatibility in SN0 and SN1 code + +**************************************************************************/ + +/* + * ICMR register fields + * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not + * present in SHub) + */ + +#define IIO_ICMR_CRB_VLD_SHFT 20 +#define IIO_ICMR_CRB_VLD_MASK (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT) + +#define IIO_ICMR_FC_CNT_SHFT 16 +#define IIO_ICMR_FC_CNT_MASK (0xf << IIO_ICMR_FC_CNT_SHFT) + +#define IIO_ICMR_C_CNT_SHFT 4 +#define IIO_ICMR_C_CNT_MASK (0xf << IIO_ICMR_C_CNT_SHFT) + +#define IIO_ICMR_PRECISE (1UL << 52) +#define IIO_ICMR_CLR_RPPD (1UL << 13) +#define IIO_ICMR_CLR_RQPD (1UL << 12) + +/* + * IIO PIO Deallocation register field masks : (IIO_IPDR) + XXX present but not needed in bedrock? See the manual. + */ +#define IIO_IPDR_PND (1 << 4) + +/* + * IIO CRB deallocation register field masks: (IIO_ICDR) + */ +#define IIO_ICDR_PND (1 << 4) + +/* + * IO BTE Length/Status (IIO_IBLS) register bit field definitions + */ +#define IBLS_BUSY (0x1 << 20) +#define IBLS_ERROR_SHFT 16 +#define IBLS_ERROR (0x1 << IBLS_ERROR_SHFT) +#define IBLS_LENGTH_MASK 0xffff + +/* + * IO BTE Control/Terminate register (IBCT) register bit field definitions + */ +#define IBCT_POISON (0x1 << 8) +#define IBCT_NOTIFY (0x1 << 4) +#define IBCT_ZFIL_MODE (0x1 << 0) + +/* + * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2) + */ +#define IIEPH1_VALID (1 << 44) +#define IIEPH1_OVERRUN (1 << 40) +#define IIEPH1_ERR_TYPE_SHFT 32 +#define IIEPH1_ERR_TYPE_MASK 0xf +#define IIEPH1_SOURCE_SHFT 20 +#define IIEPH1_SOURCE_MASK 11 +#define IIEPH1_SUPPL_SHFT 8 +#define IIEPH1_SUPPL_MASK 11 +#define IIEPH1_CMD_SHFT 0 +#define IIEPH1_CMD_MASK 7 + +#define IIEPH2_TAIL (1 << 40) +#define IIEPH2_ADDRESS_SHFT 0 +#define IIEPH2_ADDRESS_MASK 38 + +#define IIEPH1_ERR_SHORT_REQ 2 +#define IIEPH1_ERR_SHORT_REPLY 3 +#define IIEPH1_ERR_LONG_REQ 4 +#define IIEPH1_ERR_LONG_REPLY 5 + +/* + * IO Error Clear register bit field definitions + */ +#define IECLR_PI1_FWD_INT (1 << 31) /* clear PI1_FORWARD_INT in iidsr */ +#define IECLR_PI0_FWD_INT (1 << 30) /* clear PI0_FORWARD_INT in iidsr */ +#define IECLR_SPUR_RD_HDR (1 << 29) /* clear valid bit in ixss reg */ +#define IECLR_BTE1 (1 << 18) /* clear bte error 1 */ +#define IECLR_BTE0 (1 << 17) /* clear bte error 0 */ +#define IECLR_CRAZY (1 << 16) /* clear crazy bit in wstat reg */ +#define IECLR_PRB_F (1 << 15) /* clear err bit in PRB_F reg */ +#define IECLR_PRB_E (1 << 14) /* clear err bit in PRB_E reg */ +#define IECLR_PRB_D (1 << 13) /* clear err bit in PRB_D reg */ +#define IECLR_PRB_C (1 << 12) /* clear err bit in PRB_C reg */ +#define IECLR_PRB_B (1 << 11) /* clear err bit in PRB_B reg */ +#define IECLR_PRB_A (1 << 10) /* clear err bit in PRB_A reg */ +#define IECLR_PRB_9 (1 << 9) /* clear err bit in PRB_9 reg */ +#define IECLR_PRB_8 (1 << 8) /* clear err bit in PRB_8 reg */ +#define IECLR_PRB_0 (1 << 0) /* clear err bit in PRB_0 reg */ + +/* + * IIO CRB control register Fields: IIO_ICCR + */ +#define IIO_ICCR_PENDING (0x10000) +#define IIO_ICCR_CMD_MASK (0xFF) +#define IIO_ICCR_CMD_SHFT (7) +#define IIO_ICCR_CMD_NOP (0x0) /* No Op */ +#define IIO_ICCR_CMD_WAKE (0x100) /* Reactivate CRB entry and process */ +#define IIO_ICCR_CMD_TIMEOUT (0x200) /* Make CRB timeout & mark invalid */ +#define IIO_ICCR_CMD_EJECT (0x400) /* Contents of entry written to memory + * via a WB + */ +#define IIO_ICCR_CMD_FLUSH (0x800) + +/* + * + * CRB Register description. + * + * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING + * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING + * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING + * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING + * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING + * + * Many of the fields in CRB are status bits used by hardware + * for implementation of the protocol. It's very dangerous to + * mess around with the CRB registers. + * + * It's OK to read the CRB registers and try to make sense out of the + * fields in CRB. + * + * Updating CRB requires all activities in Hub IIO to be quiesced. + * otherwise, a write to CRB could corrupt other CRB entries. + * CRBs are here only as a back door peek to shub IIO's status. + * Quiescing implies no dmas no PIOs + * either directly from the cpu or from sn0net. + * this is not something that can be done easily. So, AVOID updating + * CRBs. + */ + +#ifndef __ASSEMBLY__ + +/* + * Easy access macros for CRBs, all 4 registers (A-D) + */ +typedef ii_icrb0_a_u_t icrba_t; +#define a_lnetuce ii_icrb0_a_fld_s.ia_ln_uce +#define a_mark ii_icrb0_a_fld_s.ia_mark +#define a_xerr ii_icrb0_a_fld_s.ia_xt_err +#define a_sidn ii_icrb0_a_fld_s.ia_sidn +#define a_tnum ii_icrb0_a_fld_s.ia_tnum +#define a_addr ii_icrb0_a_fld_s.ia_addr +#define a_valid ii_icrb0_a_fld_s.ia_vld +#define a_iow ii_icrb0_a_fld_s.ia_iow +#define a_regvalue ii_icrb0_a_regval + +typedef ii_icrb0_b_u_t icrbb_t; +#define b_error ii_icrb0_b_fld_s.ib_error +#define b_ecode ii_icrb0_b_fld_s.ib_errcode +#define b_cohtrans ii_icrb0_b_fld_s.ib_ct +#define b_xtsize ii_icrb0_b_fld_s.ib_size +#define b_source ii_icrb0_b_fld_s.ib_source +#define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype +#define b_imsg ii_icrb0_b_fld_s.ib_imsg +#define b_initiator ii_icrb0_b_fld_s.ib_init +#define b_regvalue ii_icrb0_b_regval + +typedef ii_icrb0_c_u_t icrbc_t; +#define c_btenum ii_icrb0_c_fld_s.ic_bte_num +#define c_pricnt ii_icrb0_c_fld_s.ic_pr_cnt +#define c_pripsc ii_icrb0_c_fld_s.ic_pr_psc +#define c_bteaddr ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/ +#define c_benable ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/ +#define c_suppl ii_icrb0_c_fld_s.ic_suppl +#define c_barrop ii_icrb0_c_fld_s.ic_bo +#define c_doresp ii_icrb0_c_fld_s.ic_resprqd +#define c_gbr ii_icrb0_c_fld_s.ic_gbr +#define c_regvalue ii_icrb0_c_regval + +typedef ii_icrb0_d_u_t icrbd_t; +#define d_bteop ii_icrb0_d_fld_s.id_bte_op +#define icrbd_ctxtvld ii_icrb0_d_fld_s.id_cvld +#define icrbd_toutvld ii_icrb0_d_fld_s.id_tvld +#define icrbd_context ii_icrb0_d_fld_s.id_context +#define d_regvalue ii_icrb0_d_regval + +#endif /* __ASSEMBLY__ */ + +/* Number of widgets supported by shub */ +#define HUB_NUM_WIDGET 9 +#define HUB_WIDGET_ID_MIN 0x8 +#define HUB_WIDGET_ID_MAX 0xf + +#define HUB_WIDGET_PART_NUM 0xc120 +#define MAX_HUBS_PER_XBOW 2 + +#ifndef __ASSEMBLY__ +/* A few more #defines for backwards compatibility */ +#define iprb_t ii_iprb0_u_t +#define iprb_regval ii_iprb0_regval +#define iprb_mult_err ii_iprb0_fld_s.i_mult_err +#define iprb_spur_rd ii_iprb0_fld_s.i_spur_rd +#define iprb_spur_wr ii_iprb0_fld_s.i_spur_wr +#define iprb_rd_to ii_iprb0_fld_s.i_rd_to +#define iprb_ovflow ii_iprb0_fld_s.i_of_cnt +#define iprb_error ii_iprb0_fld_s.i_error +#define iprb_ff ii_iprb0_fld_s.i_f +#define iprb_mode ii_iprb0_fld_s.i_m +#define iprb_bnakctr ii_iprb0_fld_s.i_nb +#define iprb_anakctr ii_iprb0_fld_s.i_na +#define iprb_xtalkctr ii_iprb0_fld_s.i_c +#endif + +#define LNK_STAT_WORKING 0x2 /* LLP is working */ + +#define IIO_WSTAT_ECRAZY (1ULL << 32) /* Hub gone crazy */ +#define IIO_WSTAT_TXRETRY (1ULL << 9) /* Hub Tx Retry timeout */ +#define IIO_WSTAT_TXRETRY_MASK (0x7F) /* should be 0xFF?? */ +#define IIO_WSTAT_TXRETRY_SHFT (16) +#define IIO_WSTAT_TXRETRY_CNT(w) (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \ + IIO_WSTAT_TXRETRY_MASK) + +/* Number of II perf. counters we can multiplex at once */ + +#define IO_PERF_SETS 32 + +#if __KERNEL__ +#ifndef __ASSEMBLY__ +#include <asm/sn/alenlist.h> +#include <asm/sn/dmamap.h> +#include <asm/sn/driver.h> +#include <asm/sn/xtalk/xtalk.h> + +/* Bit for the widget in inbound access register */ +#define IIO_IIWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) +/* Bit for the widget in outbound access register */ +#define IIO_IOWA_WIDGET(_w) ((uint64_t)(1ULL << _w)) + +/* NOTE: The following define assumes that we are going to get + * widget numbers from 8 thru F and the device numbers within + * widget from 0 thru 7. + */ +#define IIO_IIDEM_WIDGETDEV_MASK(w, d) ((uint64_t)(1ULL << (8 * ((w) - 8) + (d)))) + +/* IO Interrupt Destination Register */ +#define IIO_IIDSR_SENT_SHIFT 28 +#define IIO_IIDSR_SENT_MASK 0x10000000 +#define IIO_IIDSR_ENB_SHIFT 24 +#define IIO_IIDSR_ENB_MASK 0x01000000 +#define IIO_IIDSR_NODE_SHIFT 8 +#define IIO_IIDSR_NODE_MASK 0x0000ff00 +#define IIO_IIDSR_PI_ID_SHIFT 8 +#define IIO_IIDSR_PI_ID_MASK 0x00000010 +#define IIO_IIDSR_LVL_SHIFT 0 +#define IIO_IIDSR_LVL_MASK 0x0000007f + +/* Xtalk timeout threshhold register (IIO_IXTT) */ +#define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ +#define IXTT_RRSP_TO_MASK (0x1FULL << IXTT_RRSP_TO_SHFT) +#define IXTT_RRSP_PS_SHFT 32 /* read responsed TO prescalar */ +#define IXTT_RRSP_PS_MASK (0x7FFFFFULL << IXTT_RRSP_PS_SHFT) +#define IXTT_TAIL_TO_SHFT 0 /* tail timeout counter threshold */ +#define IXTT_TAIL_TO_MASK (0x3FFFFFFULL << IXTT_TAIL_TO_SHFT) + +/* + * The IO LLP control status register and widget control register + */ + +typedef union hubii_wcr_u { + uint64_t wcr_reg_value; + struct { + uint64_t wcr_widget_id: 4, /* LLP crossbar credit */ + wcr_tag_mode: 1, /* Tag mode */ + wcr_rsvd1: 8, /* Reserved */ + wcr_xbar_crd: 3, /* LLP crossbar credit */ + wcr_f_bad_pkt: 1, /* Force bad llp pkt enable */ + wcr_dir_con: 1, /* widget direct connect */ + wcr_e_thresh: 5, /* elasticity threshold */ + wcr_rsvd: 41; /* unused */ + } wcr_fields_s; +} hubii_wcr_t; + +#define iwcr_dir_con wcr_fields_s.wcr_dir_con + +/* The structures below are defined to extract and modify the ii +performance registers */ + +/* io_perf_sel allows the caller to specify what tests will be + performed */ + +typedef union io_perf_sel { + uint64_t perf_sel_reg; + struct { + uint64_t perf_ippr0 : 4, + perf_ippr1 : 4, + perf_icct : 8, + perf_rsvd : 48; + } perf_sel_bits; +} io_perf_sel_t; + +/* io_perf_cnt is to extract the count from the shub registers. Due to + hardware problems there is only one counter, not two. */ + +typedef union io_perf_cnt { + uint64_t perf_cnt; + struct { + uint64_t perf_cnt : 20, + perf_rsvd2 : 12, + perf_rsvd1 : 32; + } perf_cnt_bits; + +} io_perf_cnt_t; + +typedef union iprte_a { + shubreg_t entry; + struct { + shubreg_t i_rsvd_1 : 3; + shubreg_t i_addr : 38; + shubreg_t i_init : 3; + shubreg_t i_source : 8; + shubreg_t i_rsvd : 2; + shubreg_t i_widget : 4; + shubreg_t i_to_cnt : 5; + shubreg_t i_vld : 1; + } iprte_fields; +} iprte_a_t; + + +/* PIO MANAGEMENT */ +typedef struct hub_piomap_s *hub_piomap_t; + +extern hub_piomap_t +hub_piomap_alloc(devfs_handle_t dev, /* set up mapping for this device */ + device_desc_t dev_desc, /* device descriptor */ + iopaddr_t xtalk_addr, /* map for this xtalk_addr range */ + size_t byte_count, + size_t byte_count_max, /* maximum size of a mapping */ + unsigned flags); /* defined in sys/pio.h */ + +extern void hub_piomap_free(hub_piomap_t hub_piomap); + +extern caddr_t +hub_piomap_addr(hub_piomap_t hub_piomap, /* mapping resources */ + iopaddr_t xtalk_addr, /* map for this xtalk addr */ + size_t byte_count); /* map this many bytes */ + +extern void +hub_piomap_done(hub_piomap_t hub_piomap); + +extern caddr_t +hub_piotrans_addr( devfs_handle_t dev, /* translate to this device */ + device_desc_t dev_desc, /* device descriptor */ + iopaddr_t xtalk_addr, /* Crosstalk address */ + size_t byte_count, /* map this many bytes */ + unsigned flags); /* (currently unused) */ + +/* DMA MANAGEMENT */ +typedef struct hub_dmamap_s *hub_dmamap_t; + +extern hub_dmamap_t +hub_dmamap_alloc( devfs_handle_t dev, /* set up mappings for dev */ + device_desc_t dev_desc, /* device descriptor */ + size_t byte_count_max, /* max size of a mapping */ + unsigned flags); /* defined in dma.h */ + +extern void +hub_dmamap_free(hub_dmamap_t dmamap); + +extern iopaddr_t +hub_dmamap_addr( hub_dmamap_t dmamap, /* use mapping resources */ + paddr_t paddr, /* map for this address */ + size_t byte_count); /* map this many bytes */ + +extern alenlist_t +hub_dmamap_list( hub_dmamap_t dmamap, /* use mapping resources */ + alenlist_t alenlist, /* map this Addr/Length List */ + unsigned flags); + +extern void +hub_dmamap_done( hub_dmamap_t dmamap); /* done w/ mapping resources */ + +extern iopaddr_t +hub_dmatrans_addr( devfs_handle_t dev, /* translate for this device */ + device_desc_t dev_desc, /* device descriptor */ + paddr_t paddr, /* system physical address */ + size_t byte_count, /* length */ + unsigned flags); /* defined in dma.h */ + +extern alenlist_t +hub_dmatrans_list( devfs_handle_t dev, /* translate for this device */ + device_desc_t dev_desc, /* device descriptor */ + alenlist_t palenlist, /* system addr/length list */ + unsigned flags); /* defined in dma.h */ + +extern void +hub_dmamap_drain( hub_dmamap_t map); + +extern void +hub_dmaaddr_drain( devfs_handle_t vhdl, + paddr_t addr, + size_t bytes); + +extern void +hub_dmalist_drain( devfs_handle_t vhdl, + alenlist_t list); + + +/* INTERRUPT MANAGEMENT */ +typedef struct hub_intr_s *hub_intr_t; + +extern hub_intr_t +hub_intr_alloc( devfs_handle_t dev, /* which device */ + device_desc_t dev_desc, /* device descriptor */ + devfs_handle_t owner_dev); /* owner of this interrupt */ + +extern hub_intr_t +hub_intr_alloc_nothd(devfs_handle_t dev, /* which device */ + device_desc_t dev_desc, /* device descriptor */ + devfs_handle_t owner_dev); /* owner of this interrupt */ + +extern void +hub_intr_free(hub_intr_t intr_hdl); + +extern int +hub_intr_connect( hub_intr_t intr_hdl, /* xtalk intr resource hndl */ + xtalk_intr_setfunc_t setfunc, + /* func to set intr hw */ + void *setfunc_arg); /* arg to setfunc */ + +extern void +hub_intr_disconnect(hub_intr_t intr_hdl); + +extern devfs_handle_t +hub_intr_cpu_get(hub_intr_t intr_hdl); + +/* CONFIGURATION MANAGEMENT */ + +extern void +hub_provider_startup(devfs_handle_t hub); + +extern void +hub_provider_shutdown(devfs_handle_t hub); + +#define HUB_PIO_CONVEYOR 0x1 /* PIO in conveyor belt mode */ +#define HUB_PIO_FIRE_N_FORGET 0x2 /* PIO in fire-and-forget mode */ + +/* Flags that make sense to hub_widget_flags_set */ +#define HUB_WIDGET_FLAGS ( \ + HUB_PIO_CONVEYOR | \ + HUB_PIO_FIRE_N_FORGET \ + ) + + +typedef int hub_widget_flags_t; + +/* Set the PIO mode for a widget. These two functions perform the + * same operation, but hub_device_flags_set() takes a hardware graph + * vertex while hub_widget_flags_set() takes a nasid and widget + * number. In most cases, hub_device_flags_set() should be used. + */ +extern int hub_widget_flags_set(nasid_t nasid, + xwidgetnum_t widget_num, + hub_widget_flags_t flags); + +/* Depending on the flags set take the appropriate actions */ +extern int hub_device_flags_set(devfs_handle_t widget_dev, + hub_widget_flags_t flags); + + +/* Error Handling. */ +extern int hub_ioerror_handler(devfs_handle_t, int, int, struct io_error_s *); +extern int kl_ioerror_handler(cnodeid_t, cnodeid_t, cpuid_t, + int, paddr_t, caddr_t, ioerror_mode_t); +extern void hub_widget_reset(devfs_handle_t, xwidgetnum_t); +extern int hub_error_devenable(devfs_handle_t, int, int); +extern void hub_widgetdev_enable(devfs_handle_t, int); +extern void hub_widgetdev_shutdown(devfs_handle_t, int); +extern int hub_dma_enabled(devfs_handle_t); + +/* hubdev */ +extern void hubdev_init(void); +extern void hubdev_register(int (*attach_method)(devfs_handle_t)); +extern int hubdev_unregister(int (*attach_method)(devfs_handle_t)); +extern int hubdev_docallouts(devfs_handle_t hub); + +extern caddr_t hubdev_prombase_get(devfs_handle_t hub); +extern cnodeid_t hubdev_cnodeid_get(devfs_handle_t hub); + +#endif /* __ASSEMBLY__ */ +#endif /* _KERNEL */ +#endif /* _ASM_IA64_SN_SN2_SHUBIO_H */ + diff --git a/include/asm-ia64/sn/sn2/slotnum.h b/include/asm-ia64/sn/sn2/slotnum.h new file mode 100644 index 000000000000..3ebb4ba93a44 --- /dev/null +++ b/include/asm-ia64/sn/sn2/slotnum.h @@ -0,0 +1,41 @@ +/* + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (c) 1992 - 1997,2001 Silicon Graphics, Inc. All rights reserved. + */ + +#ifndef _ASM_IA64_SN_SN2_SLOTNUM_H +#define _ASM_IA64_SN_SN2_SLOTNUM_H + +#define SLOTNUM_MAXLENGTH 16 + +/* + * This file defines IO widget to slot/device assignments. + */ + + +/* This determines module to pnode mapping. */ + +#define NODESLOTS_PER_MODULE 1 +#define NODESLOTS_PER_MODULE_SHFT 1 + +#define SLOTNUM_NODE_CLASS 0x00 /* Node */ +#define SLOTNUM_ROUTER_CLASS 0x10 /* Router */ +#define SLOTNUM_XTALK_CLASS 0x20 /* Xtalk */ +#define SLOTNUM_MIDPLANE_CLASS 0x30 /* Midplane */ +#define SLOTNUM_XBOW_CLASS 0x40 /* Xbow */ +#define SLOTNUM_KNODE_CLASS 0x50 /* Kego node */ +#define SLOTNUM_PCI_CLASS 0x60 /* PCI widgets on XBridge */ +#define SLOTNUM_INVALID_CLASS 0xf0 /* Invalid */ + +#define SLOTNUM_CLASS_MASK 0xf0 +#define SLOTNUM_SLOT_MASK 0x0f + +#define SLOTNUM_GETCLASS(_sn) ((_sn) & SLOTNUM_CLASS_MASK) +#define SLOTNUM_GETSLOT(_sn) ((_sn) & SLOTNUM_SLOT_MASK) + + +#endif /* _ASM_IA64_SN_SN2_SLOTNUM_H */ diff --git a/include/asm-ia64/sn/sn2/sn_private.h b/include/asm-ia64/sn/sn2/sn_private.h new file mode 100644 index 000000000000..ba58d5ed28b8 --- /dev/null +++ b/include/asm-ia64/sn/sn2/sn_private.h @@ -0,0 +1,251 @@ +/* $Id$ + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. + */ +#ifndef _ASM_IA64_SN_SN2_SN_PRIVATE_H +#define _ASM_IA64_SN_SN2_SN_PRIVATE_H + +#include <asm/sn/nodepda.h> +#include <asm/sn/io.h> +#include <asm/sn/xtalk/xwidget.h> +#include <asm/sn/xtalk/xtalk_private.h> + +extern nasid_t master_nasid; + +/* promif.c */ +extern void he_arcs_set_vectors(void); +extern void mem_init(void); +extern void cpu_unenable(cpuid_t); +extern nasid_t get_lowest_nasid(void); +extern __psunsigned_t get_master_bridge_base(void); +extern void set_master_bridge_base(void); +extern int check_nasid_equiv(nasid_t, nasid_t); +extern nasid_t get_console_nasid(void); +extern char get_console_pcislot(void); + +extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid); + +/* memsupport.c */ +extern void poison_state_alter_range(__psunsigned_t start, int len, int poison); +extern int memory_present(paddr_t); +extern int memory_read_accessible(paddr_t); +extern int memory_write_accessible(paddr_t); +extern void memory_set_access(paddr_t, int, int); +extern void show_dir_state(paddr_t, void (*)(char *, ...)); +extern void check_dir_state(nasid_t, int, void (*)(char *, ...)); +extern void set_dir_owner(paddr_t, int); +extern void set_dir_state(paddr_t, int); +extern void set_dir_state_POISONED(paddr_t); +extern void set_dir_state_UNOWNED(paddr_t); +extern int is_POISONED_dir_state(paddr_t); +extern int is_UNOWNED_dir_state(paddr_t); +extern void get_dir_ent(paddr_t paddr, int *state, + uint64_t *vec_ptr, hubreg_t *elo); + +/* intr.c */ +extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name); +extern void intr_unreserve_level(cpuid_t cpu, int level); +extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, + intr_func_t intr_prefunc); +extern int intr_disconnect_level(cpuid_t cpu, int bit); +extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc, + int req_bit,int intr_resflags,devfs_handle_t owner_dev, + char *intr_name,int *resp_bit); +extern void intr_block_bit(cpuid_t cpu, int bit); +extern void intr_unblock_bit(cpuid_t cpu, int bit); +extern void setrtvector(intr_func_t); +extern void install_cpuintr(cpuid_t cpu); +extern void install_dbgintr(cpuid_t cpu); +extern void install_tlbintr(cpuid_t cpu); +extern void hub_migrintr_init(cnodeid_t /*cnode*/); +extern int cause_intr_connect(int level, intr_func_t handler, uint intr_spl_mask); +extern int cause_intr_disconnect(int level); +extern void intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...)); + +/* error_dump.c */ +extern char *hub_rrb_err_type[]; +extern char *hub_wrb_err_type[]; + +void nmi_dump(void); +void install_cpu_nmi_handler(int slice); + +/* klclock.c */ +extern void hub_rtc_init(cnodeid_t); + +/* bte.c */ +void bte_lateinit(void); +void bte_wait_for_xfer_completion(void *); + +/* klgraph.c */ +void klhwg_add_all_nodes(devfs_handle_t); +void klhwg_add_all_modules(devfs_handle_t); + +/* klidbg.c */ +void install_klidbg_functions(void); + +/* klnuma.c */ +extern void replicate_kernel_text(int numnodes); +extern __psunsigned_t get_freemem_start(cnodeid_t cnode); +extern void setup_replication_mask(int maxnodes); + +/* init.c */ +extern cnodeid_t get_compact_nodeid(void); /* get compact node id */ +extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node); +extern void init_platform_pda(cpuid_t cpu); +extern void per_cpu_init(void); +extern int is_fine_dirmode(void); +extern void update_node_information(cnodeid_t); + +/* shubio.c */ +extern void hubio_init(void); +extern void hub_merge_clean(nasid_t nasid); +extern void hub_set_piomode(nasid_t nasid, int conveyor); + +/* shuberror.c */ +extern void hub_error_init(cnodeid_t); +extern void dump_error_spool(cpuid_t cpu, void (*pf)(char *, ...)); +extern void hubni_error_handler(char *, int); +extern int check_ni_errors(void); + +/* Used for debugger to signal upper software a breakpoint has taken place */ + +extern void *debugger_update; +extern __psunsigned_t debugger_stopped; + +/* + * piomap, created by shub_pio_alloc. + * xtalk_info MUST BE FIRST, since this structure is cast to a + * xtalk_piomap_s by generic xtalk routines. + */ +struct hub_piomap_s { + struct xtalk_piomap_s hpio_xtalk_info;/* standard crosstalk pio info */ + devfs_handle_t hpio_hub; /* which shub's mapping registers are set up */ + short hpio_holdcnt; /* count of current users of bigwin mapping */ + char hpio_bigwin_num;/* if big window map, which one */ + int hpio_flags; /* defined below */ +}; +/* hub_piomap flags */ +#define HUB_PIOMAP_IS_VALID 0x1 +#define HUB_PIOMAP_IS_BIGWINDOW 0x2 +#define HUB_PIOMAP_IS_FIXED 0x4 + +#define hub_piomap_xt_piomap(hp) (&hp->hpio_xtalk_info) +#define hub_piomap_hub_v(hp) (hp->hpio_hub) +#define hub_piomap_winnum(hp) (hp->hpio_bigwin_num) + +/* + * dmamap, created by shub_pio_alloc. + * xtalk_info MUST BE FIRST, since this structure is cast to a + * xtalk_dmamap_s by generic xtalk routines. + */ +struct hub_dmamap_s { + struct xtalk_dmamap_s hdma_xtalk_info;/* standard crosstalk dma info */ + devfs_handle_t hdma_hub; /* which shub we go through */ + int hdma_flags; /* defined below */ +}; +/* shub_dmamap flags */ +#define HUB_DMAMAP_IS_VALID 0x1 +#define HUB_DMAMAP_USED 0x2 +#define HUB_DMAMAP_IS_FIXED 0x4 + +/* + * interrupt handle, created by shub_intr_alloc. + * xtalk_info MUST BE FIRST, since this structure is cast to a + * xtalk_intr_s by generic xtalk routines. + */ +struct hub_intr_s { + struct xtalk_intr_s i_xtalk_info; /* standard crosstalk intr info */ + ilvl_t i_swlevel; /* software level for blocking intr */ + cpuid_t i_cpuid; /* which cpu */ + int i_bit; /* which bit */ + int i_flags; +}; +/* flag values */ +#define HUB_INTR_IS_ALLOCED 0x1 /* for debug: allocated */ +#define HUB_INTR_IS_CONNECTED 0x4 /* for debug: connected to a software driver */ + +typedef struct hubinfo_s { + nodepda_t *h_nodepda; /* pointer to node's private data area */ + cnodeid_t h_cnodeid; /* compact nodeid */ + nasid_t h_nasid; /* nasid */ + + /* structures for PIO management */ + xwidgetnum_t h_widgetid; /* my widget # (as viewed from xbow) */ + struct hub_piomap_s h_small_window_piomap[HUB_WIDGET_ID_MAX+1]; + sv_t h_bwwait; /* wait for big window to free */ + spinlock_t h_bwlock; /* guard big window piomap's */ + spinlock_t h_crblock; /* gaurd CRB error handling */ + int h_num_big_window_fixed; /* count number of FIXED maps */ + struct hub_piomap_s h_big_window_piomap[HUB_NUM_BIG_WINDOW]; + hub_intr_t hub_ii_errintr; +} *hubinfo_t; + +#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \ + (vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr)) + +#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \ + (vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr) + +#define hubinfo_to_hubv(hinfo, hub_v) (hinfo->h_nodepda->node_vertex) + +/* + * Hub info PIO map access functions. + */ +#define hubinfo_bwin_piomap_get(hinfo, win) \ + (&hinfo->h_big_window_piomap[win]) +#define hubinfo_swin_piomap_get(hinfo, win) \ + (&hinfo->h_small_window_piomap[win]) + +/* cpu-specific information stored under INFO_LBL_CPU_INFO */ +typedef struct cpuinfo_s { + cpuid_t ci_cpuid; /* CPU ID */ +} *cpuinfo_t; + +#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \ + (vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr)) + +#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \ + (vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr) + +/* Special initialization function for xswitch vertices created during startup. */ +extern void xswitch_vertex_init(devfs_handle_t xswitch); + +extern xtalk_provider_t hub_provider; + +/* du.c */ +int ducons_write(char *buf, int len); + +/* memerror.c */ + +extern void install_eccintr(cpuid_t cpu); +extern void memerror_get_stats(cnodeid_t cnode, + int *bank_stats, int *bank_stats_max); +extern void probe_md_errors(nasid_t); +/* sysctlr.c */ +extern void sysctlr_init(void); +extern void sysctlr_power_off(int sdonly); +extern void sysctlr_keepalive(void); + +#define valid_cpuid(_x) (((_x) >= 0) && ((_x) < maxcpus)) + +/* Useful definitions to get the memory dimm given a physical + * address. + */ +#define paddr_dimm(_pa) ((_pa & MD_BANK_MASK) >> MD_BANK_SHFT) +#define paddr_cnode(_pa) (NASID_TO_COMPACT_NODEID(NASID_GET(_pa))) +extern void membank_pathname_get(paddr_t,char *); + +/* To redirect the output into the error buffer */ +#define errbuf_print(_s) printf("#%s",_s) + +extern void crbx(nasid_t nasid, void (*pf)(char *, ...)); +void bootstrap(void); + +/* sndrv.c */ +extern int sndrv_attach(devfs_handle_t vertex); + +#endif /* _ASM_IA64_SN_SN2_SN_PRIVATE_H */ diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h index 6404f078966f..b8832a060939 100644 --- a/include/asm-ia64/sn/sn_cpuid.h +++ b/include/asm-ia64/sn/sn_cpuid.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com) + * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. */ @@ -13,8 +12,13 @@ #define _ASM_IA64_SN_SN_CPUID_H #include <linux/config.h> -#include <asm/processor.h> -#include <asm/sn/mmzone_sn1.h> +#include <linux/smp.h> +#include <linux/sched.h> +#include <linux/mmzone.h> +#include <asm/sn/types.h> +#include <asm/current.h> +#include <asm/nodedata.h> + /* * Functions for converting between cpuids, nodeids and NASIDs. @@ -46,10 +50,15 @@ * * not real efficient - dont use in perf critical code * * LID - processor defined register (see PRM V2). + * + * On SN1 * 31:24 - id Contains the NASID * 23:16 - eid Contains 0-3 to identify the cpu on the node * bit 17 - synergy number * bit 16 - FSB slot number + * On SN2 + * 31:28 - id Contains 0-3 to identify the cpu on the node + * 27:16 - eid Contains the NASID * * * @@ -70,15 +79,15 @@ * | | * ------- ------- * | | | | - * | 0 | | 1 | SYNERGY + * | 0 | | 1 | SYNERGY (SN1 only) * | | | | * ------- ------- * | | * | | * ------------------------------- * | | - * | BEDROCK | NASID (0..127) - * | | CNODEID (0..numnodes-1) + * | BEDROCK / SHUB | NASID (0..MAX_NASIDS) + * | | CNODEID (0..num_compact_nodes-1) * | | * | | * ------------------------------- @@ -91,10 +100,25 @@ #define cpu_physical_id(cpuid) ((ia64_get_lid() >> 16) & 0xffff) #endif +#ifdef CONFIG_IA64_SGI_SN1 +/* + * macros for some of these exist in sn/addrs.h & sn/arch.h, etc. However, + * trying #include these files here causes circular dependencies. + */ #define cpu_physical_id_to_nasid(cpi) ((cpi) >> 8) #define cpu_physical_id_to_synergy(cpi) (((cpi) >> 1) & 1) #define cpu_physical_id_to_fsb_slot(cpi) ((cpi) & 1) #define cpu_physical_id_to_slice(cpi) ((cpi) & 3) +#define get_nasid() ((ia64_get_lid() >> 24)) +#define get_slice() ((ia64_get_lid() >> 16) & 3) +#define get_node_number(addr) (((unsigned long)(addr)>>33) & 0x7f) +#else +#define cpu_physical_id_to_nasid(cpi) ((cpi) &0xfff) +#define cpu_physical_id_to_slice(cpi) ((cpi>>12) & 3) +#define get_nasid() ((ia64_get_lid() >> 16) & 0xfff) +#define get_slice() ((ia64_get_lid() >> 28) & 0xf) +#define get_node_number(addr) (((unsigned long)(addr)>>38) & 0x7ff) +#endif /* * NOTE: id & eid refer to Intels definitions of the LID register @@ -118,15 +142,12 @@ extern sn_sapicid_info_t sn_sapicid_info[]; /* indexed by cpuid */ +#ifdef CONFIG_IA64_SGI_SN1 /* * cpuid_to_fsb_slot - convert a cpuid to the fsb slot number that it is in. * (there are 2 cpus per FSB. This function returns 0 or 1) */ -static __inline__ int -cpuid_to_fsb_slot(int cpuid) -{ - return cpu_physical_id_to_fsb_slot(cpu_physical_id(cpuid)); -} +#define cpuid_to_fsb_slot(cpuid) (cpu_physical_id_to_fsb_slot(cpu_physical_id(cpuid))) /* @@ -134,108 +155,75 @@ cpuid_to_fsb_slot(int cpuid) * (there are 2 synergies per node. Function returns 0 or 1 to * specify which synergy the cpu is on) */ -static __inline__ int -cpuid_to_synergy(int cpuid) -{ - return cpu_physical_id_to_synergy(cpu_physical_id(cpuid)); -} +#define cpuid_to_synergy(cpuid) (cpu_physical_id_to_synergy(cpu_physical_id(cpuid))) +#endif /* * cpuid_to_slice - convert a cpuid to the slice that it resides on * There are 4 cpus per node. This function returns 0 .. 3) */ -static __inline__ int -cpuid_to_slice(int cpuid) -{ - return cpu_physical_id_to_slice(cpu_physical_id(cpuid)); -} +#define cpuid_to_slice(cpuid) (cpu_physical_id_to_slice(cpu_physical_id(cpuid))) /* * cpuid_to_nasid - convert a cpuid to the NASID that it resides on */ -static __inline__ int -cpuid_to_nasid(int cpuid) -{ - return cpu_physical_id_to_nasid(cpu_physical_id(cpuid)); -} +#define cpuid_to_nasid(cpuid) (cpu_physical_id_to_nasid(cpu_physical_id(cpuid))) /* * cpuid_to_cnodeid - convert a cpuid to the cnode that it resides on */ -static __inline__ int -cpuid_to_cnodeid(int cpuid) -{ - return nasid_map[cpuid_to_nasid(cpuid)]; -} +#define cpuid_to_cnodeid(cpuid) (local_node_data->physical_node_map[cpuid_to_nasid(cpuid)]) + /* * cnodeid_to_nasid - convert a cnodeid to a NASID + * Macro relies on pg_data for a node being on the node itself. + * Just extract the NASID from the pointer. + * */ -static __inline__ int -cnodeid_to_nasid(int cnodeid) -{ - if (nasid_map[cnodeid_map[cnodeid]] != cnodeid) - panic("cnodeid_to_nasid, cnode = %d", cnodeid); - return cnodeid_map[cnodeid]; -} +#define cnodeid_to_nasid(cnodeid) (get_node_number(local_node_data->pg_data_ptrs[cnodeid])) + /* * nasid_to_cnodeid - convert a NASID to a cnodeid */ -static __inline__ int -nasid_to_cnodeid(int nasid) -{ - if (cnodeid_map[nasid_map[nasid]] != nasid) - panic("nasid_to_cnodeid"); - return nasid_map[nasid]; -} +#define nasid_to_cnodeid(nasid) (local_node_data->physical_node_map[nasid]) /* * cnode_slice_to_cpuid - convert a codeid & slice to a cpuid */ -static __inline__ int -cnode_slice_to_cpuid(int cnodeid, int slice) { - return(id_eid_to_cpuid(cnodeid_to_nasid(cnodeid),slice)); -} +#define cnode_slice_to_cpuid(cnodeid,slice) (id_eid_to_cpuid(cnodeid_to_nasid(cnodeid),(slice))) + /* * cpuid_to_subnode - convert a cpuid to the subnode it resides on. * slice 0 & 1 are on subnode 0 * slice 2 & 3 are on subnode 1. */ -static __inline__ int -cpuid_to_subnode(int cpuid) { - int ret = cpuid_to_slice(cpuid); - if (ret < 2) return 0; - else return 1; -} +#define cpuid_to_subnode(cpuid) ((cpuid_to_slice(cpuid)<2) ? 0 : 1) + /* * cpuid_to_localslice - convert a cpuid to a local slice * slice 0 & 2 are local slice 0 * slice 1 & 3 are local slice 1 */ -static __inline__ int -cpuid_to_localslice(int cpuid) { - return(cpuid_to_slice(cpuid) & 1); -} +#define cpuid_to_localslice(cpuid) (cpuid_to_slice(cpuid) & 1) + + +#define smp_physical_node_id() (cpuid_to_nasid(smp_processor_id())) -static __inline__ int -cnodeid_to_cpuid(int cnode) { - int cpu; - for (cpu = 0; cpu < smp_num_cpus; cpu++) { - if (cpuid_to_cnodeid(cpu) == cnode) { - break; - } - } - if (cpu == smp_num_cpus) cpu = -1; - return cpu; -} +/* + * cnodeid_to_cpuid - convert a cnode to a cpuid of a cpu on the node. + * returns -1 if no cpus exist on the node + */ +extern int cnodeid_to_cpuid(int cnode); #endif /* _ASM_IA64_SN_SN_CPUID_H */ + diff --git a/include/asm-ia64/sn/sn_fru.h b/include/asm-ia64/sn/sn_fru.h index e98324a779b5..f2800c178054 100644 --- a/include/asm-ia64/sn/sn_fru.h +++ b/include/asm-ia64/sn/sn_fru.h @@ -4,11 +4,11 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 1999-2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Patrick Gefre + * Copyright (C) 1992 - 1997, 1999-2001 Silicon Graphics, Inc. + * All rights reserved. */ -#ifndef _ASM_SN_SN_FRU_H -#define _ASM_SN_SN_FRU_H +#ifndef _ASM_IA64_SN_SN_FRU_H +#define _ASM_IA64_SN_SN_FRU_H #define MAX_DIMMS 8 /* max # of dimm banks */ #define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */ @@ -42,5 +42,5 @@ typedef struct kf_pci_bus_s { } kf_pci_bus_t; -#endif /* _ASM_SN_SN_FRU_H */ +#endif /* _ASM_IA64_SN_SN_FRU_H */ diff --git a/include/asm-ia64/sn/sn_pio_sync.h b/include/asm-ia64/sn/sn_pio_sync.h new file mode 100644 index 000000000000..1fc590447eef --- /dev/null +++ b/include/asm-ia64/sn/sn_pio_sync.h @@ -0,0 +1,53 @@ +/* + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved. + */ + + +#ifndef _ASM_IA64_SN_SN_PIO_WRITE_SYNC_H +#define _ASM_IA64_SN_SN_PIO_WRITE_SYNC_H + +#include <linux/config.h> +#ifdef CONFIG_IA64_SGI_SN2 +#include <asm/sn/sn_cpuid.h> +#include <asm/sn/sn2/addrs.h> +#include <asm/sn/sn2/shub_mmr.h> +#include <asm/sn/sn2/shub_mmr_t.h> + +/* + * This macro flushes all outstanding PIOs performed by this cpu to the + * intended destination SHUB. This in essence ensures that all PIO's + * issues by this cpu has landed at it's destination. + * + * This macro expects the caller: + * 1. The thread is locked. + * 2. All prior PIO operations has been fenced with __ia64_mf_a(). + * + * The expectation is that get_slice() will return either 0 or 2. + * When we have multi-core cpu's, the expectation is get_slice() will + * return either 0,1 or 2,3. + */ + +#define SN_PIO_WRITE_SYNC \ + { \ + volatile unsigned long sn_pio_writes_done; \ + do { \ + sn_pio_writes_done = (volatile unsigned long) (SH_PIO_WRITE_STATUS_0_WRITES_OK_MASK & HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(get_nasid(), (get_slice() < 2) ? SH_PIO_WRITE_STATUS_0 : SH_PIO_WRITE_STATUS_1 ))); \ + } while (!sn_pio_writes_done); \ + __ia64_mf_a(); \ + } +#else + +/* + * For all ARCHITECTURE type, this is a NOOP. + */ + +#define SN_PIO_WRITE_SYNC + +#endif + +#endif /* _ASM_IA64_SN_SN_PIO_WRITE_SYNC_H */ diff --git a/include/asm-ia64/sn/sn_private.h b/include/asm-ia64/sn/sn_private.h index 1ee95b3b17be..e382cb5d80e2 100644 --- a/include/asm-ia64/sn/sn_private.h +++ b/include/asm-ia64/sn/sn_private.h @@ -4,299 +4,20 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_PRIVATE_H -#define _ASM_SN_PRIVATE_H +#ifndef _ASM_IA64_SN_SN_PRIVATE_H +#define _ASM_IA64_SN_SN_PRIVATE_H +#include <linux/config.h> #include <asm/sn/nodepda.h> #include <asm/sn/xtalk/xwidget.h> #include <asm/sn/xtalk/xtalk_private.h> -extern nasid_t master_nasid; - -extern hubreg_t get_region(cnodeid_t); -extern hubreg_t nasid_to_region(nasid_t); -/* promif.c */ -#ifdef LATER -extern cpuid_t cpu_node_probe(cpumask_t *cpumask, int *numnodes); -#endif -extern void he_arcs_set_vectors(void); -extern void mem_init(void); -#ifdef LATER -extern int cpu_enabled(cpuid_t); -#endif -extern void cpu_unenable(cpuid_t); -extern nasid_t get_lowest_nasid(void); -extern __psunsigned_t get_master_bridge_base(void); -extern void set_master_bridge_base(void); -extern int check_nasid_equiv(nasid_t, nasid_t); -extern nasid_t get_console_nasid(void); -extern char get_console_pcislot(void); -#ifdef LATER -extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int); -#endif - -extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid); - -/* memsupport.c */ -extern void poison_state_alter_range(__psunsigned_t start, int len, int poison); -extern int memory_present(paddr_t); -extern int memory_read_accessible(paddr_t); -extern int memory_write_accessible(paddr_t); -extern void memory_set_access(paddr_t, int, int); -extern void show_dir_state(paddr_t, void (*)(char *, ...)); -extern void check_dir_state(nasid_t, int, void (*)(char *, ...)); -extern void set_dir_owner(paddr_t, int); -extern void set_dir_state(paddr_t, int); -extern void set_dir_state_POISONED(paddr_t); -extern void set_dir_state_UNOWNED(paddr_t); -extern int is_POISONED_dir_state(paddr_t); -extern int is_UNOWNED_dir_state(paddr_t); -extern void get_dir_ent(paddr_t paddr, int *state, - uint64_t *vec_ptr, hubreg_t *elo); - -/* intr.c */ -#if defined(NEW_INTERRUPTS) -extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name); -extern void intr_unreserve_level(cpuid_t cpu, int level); -extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, - intr_func_t intr_func, void *intr_arg, - intr_func_t intr_prefunc); -extern int intr_disconnect_level(cpuid_t cpu, int bit); -extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc, - int req_bit,int intr_resflags,devfs_handle_t owner_dev, - char *intr_name,int *resp_bit); -#endif /* NEW_INTERRUPTS */ -extern void intr_block_bit(cpuid_t cpu, int bit); -extern void intr_unblock_bit(cpuid_t cpu, int bit); -extern void setrtvector(intr_func_t); -extern void install_cpuintr(cpuid_t cpu); -extern void install_dbgintr(cpuid_t cpu); -extern void install_tlbintr(cpuid_t cpu); -extern void hub_migrintr_init(cnodeid_t /*cnode*/); -extern int cause_intr_connect(int level, intr_func_t handler, uint intr_spl_mask); -extern int cause_intr_disconnect(int level); -extern void intr_reserve_hardwired(cnodeid_t); -extern void intr_clear_all(nasid_t); -extern void intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...)); -extern int protected_broadcast(hubreg_t intrbit); - -/* error_dump.c */ -extern char *hub_rrb_err_type[]; -extern char *hub_wrb_err_type[]; - -void nmi_dump(void); -void install_cpu_nmi_handler(int slice); - -/* klclock.c */ -extern void hub_rtc_init(cnodeid_t); - -/* bte.c */ -void bte_lateinit(void); -void bte_wait_for_xfer_completion(void *); - -/* klgraph.c */ -void klhwg_add_all_nodes(devfs_handle_t); -void klhwg_add_all_modules(devfs_handle_t); - -/* klidbg.c */ -void install_klidbg_functions(void); - -/* klnuma.c */ -extern void replicate_kernel_text(int numnodes); -extern __psunsigned_t get_freemem_start(cnodeid_t cnode); -extern void setup_replication_mask(int maxnodes); - -/* init.c */ -extern cnodeid_t get_compact_nodeid(void); /* get compact node id */ -#ifdef LATER -extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node); -extern void init_platform_pda(pda_t *ppda, cpuid_t cpu); +#if defined(CONFIG_IA64_SGI_SN1) +#include <asm/sn/sn1/sn_private.h> +#elif defined(CONFIG_IA64_SGI_SN2) +#include <asm/sn/sn2/sn_private.h> #endif -extern void per_cpu_init(void); -extern void per_hub_init(cnodeid_t); -#ifdef LATER -extern cpumask_t boot_cpumask; -#endif -extern int is_fine_dirmode(void); -extern void update_node_information(cnodeid_t); - -#ifdef LATER -/* clksupport.c */ -extern void early_counter_intr(eframe_t *); -#endif - -/* hubio.c */ -extern void hubio_init(void); -extern void hub_merge_clean(nasid_t nasid); -extern void hub_set_piomode(nasid_t nasid, int conveyor); - -/* huberror.c */ -extern void hub_error_init(cnodeid_t); -extern void dump_error_spool(cpuid_t cpu, void (*pf)(char *, ...)); -extern void hubni_error_handler(char *, int); -extern int check_ni_errors(void); - -/* Used for debugger to signal upper software a breakpoint has taken place */ - -extern void *debugger_update; -extern __psunsigned_t debugger_stopped; - -/* - * IP27 piomap, created by hub_pio_alloc. - * xtalk_info MUST BE FIRST, since this structure is cast to a - * xtalk_piomap_s by generic xtalk routines. - */ -struct hub_piomap_s { - struct xtalk_piomap_s hpio_xtalk_info;/* standard crosstalk pio info */ - devfs_handle_t hpio_hub; /* which hub's mapping registers are set up */ - short hpio_holdcnt; /* count of current users of bigwin mapping */ - char hpio_bigwin_num;/* if big window map, which one */ - int hpio_flags; /* defined below */ -}; -/* hub_piomap flags */ -#define HUB_PIOMAP_IS_VALID 0x1 -#define HUB_PIOMAP_IS_BIGWINDOW 0x2 -#define HUB_PIOMAP_IS_FIXED 0x4 - -#define hub_piomap_xt_piomap(hp) (&hp->hpio_xtalk_info) -#define hub_piomap_hub_v(hp) (hp->hpio_hub) -#define hub_piomap_winnum(hp) (hp->hpio_bigwin_num) - -#if TBD - /* Ensure that hpio_xtalk_info is first */ - #assert (&(((struct hub_piomap_s *)0)->hpio_xtalk_info) == 0) -#endif - - -/* - * IP27 dmamap, created by hub_pio_alloc. - * xtalk_info MUST BE FIRST, since this structure is cast to a - * xtalk_dmamap_s by generic xtalk routines. - */ -struct hub_dmamap_s { - struct xtalk_dmamap_s hdma_xtalk_info;/* standard crosstalk dma info */ - devfs_handle_t hdma_hub; /* which hub we go through */ - int hdma_flags; /* defined below */ -}; -/* hub_dmamap flags */ -#define HUB_DMAMAP_IS_VALID 0x1 -#define HUB_DMAMAP_USED 0x2 -#define HUB_DMAMAP_IS_FIXED 0x4 - -#if TBD - /* Ensure that hdma_xtalk_info is first */ - #assert (&(((struct hub_dmamap_s *)0)->hdma_xtalk_info) == 0) -#endif - -/* - * IP27 interrupt handle, created by hub_intr_alloc. - * xtalk_info MUST BE FIRST, since this structure is cast to a - * xtalk_intr_s by generic xtalk routines. - */ -struct hub_intr_s { - struct xtalk_intr_s i_xtalk_info; /* standard crosstalk intr info */ - ilvl_t i_swlevel; /* software level for blocking intr */ - cpuid_t i_cpuid; /* which cpu */ - int i_bit; /* which bit */ - int i_flags; -}; -/* flag values */ -#define HUB_INTR_IS_ALLOCED 0x1 /* for debug: allocated */ -#define HUB_INTR_IS_CONNECTED 0x4 /* for debug: connected to a software driver */ - -#if TBD - /* Ensure that i_xtalk_info is first */ - #assert (&(((struct hub_intr_s *)0)->i_xtalk_info) == 0) -#endif - - -/* IP27 hub-specific information stored under INFO_LBL_HUB_INFO */ -/* TBD: IP27-dependent stuff currently in nodepda.h should be here */ -typedef struct hubinfo_s { - nodepda_t *h_nodepda; /* pointer to node's private data area */ - cnodeid_t h_cnodeid; /* compact nodeid */ - nasid_t h_nasid; /* nasid */ - - /* structures for PIO management */ - xwidgetnum_t h_widgetid; /* my widget # (as viewed from xbow) */ - struct hub_piomap_s h_small_window_piomap[HUB_WIDGET_ID_MAX+1]; - sv_t h_bwwait; /* wait for big window to free */ - spinlock_t h_bwlock; /* guard big window piomap's */ - spinlock_t h_crblock; /* gaurd CRB error handling */ - int h_num_big_window_fixed; /* count number of FIXED maps */ - struct hub_piomap_s h_big_window_piomap[HUB_NUM_BIG_WINDOW]; - hub_intr_t hub_ii_errintr; -} *hubinfo_t; - -#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \ - (vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr)) - -#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \ - (vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr) - -#define hubinfo_to_hubv(hinfo, hub_v) (hinfo->h_nodepda->node_vertex) - -/* - * Hub info PIO map access functions. - */ -#define hubinfo_bwin_piomap_get(hinfo, win) \ - (&hinfo->h_big_window_piomap[win]) -#define hubinfo_swin_piomap_get(hinfo, win) \ - (&hinfo->h_small_window_piomap[win]) - -/* IP27 cpu-specific information stored under INFO_LBL_CPU_INFO */ -/* TBD: IP27-dependent stuff currently in pda.h should be here */ -typedef struct cpuinfo_s { -#ifdef LATER - pda_t *ci_cpupda; /* pointer to CPU's private data area */ -#endif - cpuid_t ci_cpuid; /* CPU ID */ -} *cpuinfo_t; - -#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \ - (vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr)) - -#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \ - (vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr) - -/* Special initialization function for xswitch vertices created during startup. */ -extern void xswitch_vertex_init(devfs_handle_t xswitch); - -extern xtalk_provider_t hub_provider; - -/* du.c */ -int ducons_write(char *buf, int len); - -/* memerror.c */ - -extern void install_eccintr(cpuid_t cpu); -extern void memerror_get_stats(cnodeid_t cnode, - int *bank_stats, int *bank_stats_max); -extern void probe_md_errors(nasid_t); -/* sysctlr.c */ -extern void sysctlr_init(void); -extern void sysctlr_power_off(int sdonly); -extern void sysctlr_keepalive(void); - -#define valid_cpuid(_x) (((_x) >= 0) && ((_x) < maxcpus)) - -/* Useful definitions to get the memory dimm given a physical - * address. - */ -#define paddr_dimm(_pa) ((_pa & MD_BANK_MASK) >> MD_BANK_SHFT) -#define paddr_cnode(_pa) (NASID_TO_COMPACT_NODEID(NASID_GET(_pa))) -extern void membank_pathname_get(paddr_t,char *); - -/* To redirect the output into the error buffer */ -#define errbuf_print(_s) printf("#%s",_s) - -extern void crbx(nasid_t nasid, void (*pf)(char *, ...)); -void bootstrap(void); - -/* sndrv.c */ -extern int sndrv_attach(devfs_handle_t vertex); -#endif /* _ASM_SN_PRIVATE_H */ +#endif /* _ASM_IA64_SN_SN_PRIVATE_H */ diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h index 9c350d122a6b..a92e7b1c2355 100644 --- a/include/asm-ia64/sn/sn_sal.h +++ b/include/asm-ia64/sn/sn_sal.h @@ -1,25 +1,81 @@ -#ifndef _ASM_IA64_SN_SAL_H -#define _ASM_IA64_SN_SAL_H +#ifndef _ASM_IA64_SN_SN_SAL_H +#define _ASM_IA64_SN_SN_SAL_H /* * System Abstraction Layer definitions for IA64 * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * - * Copyright (C) 2000, Silicon Graphics. - * Copyright (C) 2000. Jack Steiner (steiner@sgi.com) + * Copyright (c) 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include <asm/sal.h> +#include <asm/sn/sn_cpuid.h> // SGI Specific Calls #define SN_SAL_POD_MODE 0x02000001 #define SN_SAL_SYSTEM_RESET 0x02000002 #define SN_SAL_PROBE 0x02000003 +#define SN_SAL_GET_CONSOLE_NASID 0x02000004 +#define SN_SAL_GET_KLCONFIG_ADDR 0x02000005 +#define SN_SAL_LOG_CE 0x02000006 +#define SN_SAL_REGISTER_CE 0x02000007 u64 ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr); +/* + * Returns the master console nasid, if the call fails, return an illegal + * value. + */ +static inline u64 +ia64_sn_get_console_nasid(void) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + SAL_CALL(ret_stuff, SN_SAL_GET_CONSOLE_NASID, 0, 0, 0, 0, 0, 0, 0); + + if (ret_stuff.status < 0) + return ret_stuff.status; + + /* Master console nasid is in 'v0' */ + return ret_stuff.v0; +} + +static inline u64 +ia64_sn_get_klconfig_addr(nasid_t nasid) +{ + struct ia64_sal_retval ret_stuff; + extern u64 klgraph_addr[]; + int cnodeid; + + cnodeid = nasid_to_cnodeid(nasid); + if (klgraph_addr[cnodeid] == 0) { + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0); + + /* + * We should panic if a valid cnode nasid does not produce + * a klconfig address. + */ + if (ret_stuff.status != 0) { + panic("ia64_sn_get_klconfig_addr: Returned error %lx\n", ret_stuff.status); + } + + klgraph_addr[cnodeid] = ret_stuff.v0; + } + return(klgraph_addr[cnodeid]); -#endif /* _ASM_IA64_SN_SN1_SAL_H */ +} +#endif /* _ASM_IA64_SN_SN_SAL_H */ diff --git a/include/asm-ia64/sn/snconfig.h b/include/asm-ia64/sn/snconfig.h new file mode 100644 index 000000000000..0ea7f49d1ccb --- /dev/null +++ b/include/asm-ia64/sn/snconfig.h @@ -0,0 +1,18 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000-2001 Silicon Graphics, Inc. + */ +#ifndef _ASM_IA64_SN_SNCONFIG_H +#define _ASM_IA64_SN_SNCONFIG_H + +#include <linux/config.h> + +#if defined(CONFIG_IA64_SGI_SN1) +#include <asm/sn/sn1/ip27config.h> +#elif defined(CONFIG_IA64_SGI_SN2) +#endif + +#endif /* _ASM_IA64_SN_SNCONFIG_H */ diff --git a/include/asm-ia64/sn/sndrv.h b/include/asm-ia64/sn/sndrv.h new file mode 100644 index 000000000000..10664979659e --- /dev/null +++ b/include/asm-ia64/sn/sndrv.h @@ -0,0 +1,39 @@ +#ifndef _ASM_IA64_SN_SNDRV_H +#define _ASM_IA64_SN_SNDRV_H + +/* ioctl commands */ +#define SNDRV_GET_ROUTERINFO 1 +#define SNDRV_GET_INFOSIZE 2 +#define SNDRV_GET_HUBINFO 3 +#define SNDRV_GET_FLASHLOGSIZE 4 +#define SNDRV_SET_FLASHSYNC 5 +#define SNDRV_GET_FLASHLOGDATA 6 +#define SNDRV_GET_FLASHLOGALL 7 + +#define SNDRV_SET_HISTOGRAM_TYPE 14 + +#define SNDRV_ELSC_COMMAND 19 +#define SNDRV_CLEAR_LOG 20 +#define SNDRV_INIT_LOG 21 +#define SNDRV_GET_PIMM_PSC 22 +#define SNDRV_SET_PARTITION 23 +#define SNDRV_GET_PARTITION 24 + +/* see synergy_perf_ioctl() */ +#define SNDRV_GET_SYNERGY_VERSION 30 +#define SNDRV_GET_SYNERGY_STATUS 31 +#define SNDRV_GET_SYNERGYINFO 32 +#define SNDRV_SYNERGY_APPEND 33 +#define SNDRV_SYNERGY_ENABLE 34 +#define SNDRV_SYNERGY_FREQ 35 + +/* Devices */ +#define SNDRV_UKNOWN_DEVICE -1 +#define SNDRV_ROUTER_DEVICE 1 +#define SNDRV_HUB_DEVICE 2 +#define SNDRV_ELSC_NVRAM_DEVICE 3 +#define SNDRV_ELSC_CONTROLLER_DEVICE 4 +#define SNDRV_SYSCTL_SUBCH 5 +#define SNDRV_SYNERGY_DEVICE 6 + +#endif /* _ASM_IA64_SN_SNDRV_H */ diff --git a/include/asm-ia64/sn/sv.h b/include/asm-ia64/sn/sv.h index 0b5a0fd79f07..044659de2ed6 100644 --- a/include/asm-ia64/sn/sv.h +++ b/include/asm-ia64/sn/sv.h @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2000 Silicon Graphics, Inc. All rights reserved + * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved * * This implemenation of synchronization variables is heavily based on * one done by Steve Lord <lord@sgi.com> @@ -11,8 +11,8 @@ * Paul Cassella <pwc@sgi.com> */ -#ifndef SV_H -#define SV_H +#ifndef _ASM_IA64_SN_SV_H +#define _ASM_IA64_SN_SV_H #include <linux/spinlock.h> #include <asm/semaphore.h> @@ -150,4 +150,4 @@ void sv_destroy(sv_t *sv); #undef _SV_ASSERT #endif -#endif +#endif /* _ASM_IA64_SN_SV_H */ diff --git a/include/asm-ia64/sn/systeminfo.h b/include/asm-ia64/sn/systeminfo.h index 9ac52b247646..819e2a043f38 100644 --- a/include/asm-ia64/sn/systeminfo.h +++ b/include/asm-ia64/sn/systeminfo.h @@ -4,11 +4,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SYSTEMINFO_H -#define _ASM_SN_SYSTEMINFO_H +#ifndef _ASM_IA64_SN_SYSTEMINFO_H +#define _ASM_IA64_SN_SYSTEMINFO_H + +#include <linux/types.h> #ifdef __cplusplus extern "C" { @@ -69,4 +70,4 @@ int get_module_info(int, module_info_t *, size_t); } #endif -#endif /* _ASM_SN_SYSTEMINFO_H */ +#endif /* _ASM_IA64_SN_SYSTEMINFO_H */ diff --git a/include/asm-ia64/sn/types.h b/include/asm-ia64/sn/types.h index 448d6a31c3af..f28b5255c471 100644 --- a/include/asm-ia64/sn/types.h +++ b/include/asm-ia64/sn/types.h @@ -3,30 +3,27 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All Rights Reserved. * Copyright (C) 1999 by Ralf Baechle */ -#ifndef _ASM_SN_TYPES_H -#define _ASM_SN_TYPES_H +#ifndef _ASM_IA64_SN_TYPES_H +#define _ASM_IA64_SN_TYPES_H #include <linux/types.h> typedef unsigned long cpuid_t; typedef unsigned long cpumask_t; -/* typedef unsigned long cnodemask_t; */ typedef signed short nasid_t; /* node id in numa-as-id space */ -typedef signed short cnodeid_t; /* node id in compact-id space */ typedef signed char partid_t; /* partition ID type */ typedef signed short moduleid_t; /* user-visible module number type */ typedef signed short cmoduleid_t; /* kernel compact module id type */ typedef unsigned char clusterid_t; /* Clusterid of the cell */ -#define __psunsigned_t uint64_t -#define lock_t uint64_t +typedef uint64_t __psunsigned_t; typedef unsigned long iopaddr_t; typedef unsigned char uchar_t; typedef unsigned long paddr_t; typedef unsigned long pfn_t; -#endif /* _ASM_SN_TYPES_H */ +#endif /* _ASM_IA64_SN_TYPES_H */ diff --git a/include/asm-ia64/sn/sn1/uart16550.h b/include/asm-ia64/sn/uart16550.h index 749840dfeb29..e7f9251a5ce6 100644 --- a/include/asm-ia64/sn/sn1/uart16550.h +++ b/include/asm-ia64/sn/uart16550.h @@ -1,15 +1,14 @@ -/* $Id$ +/* * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_SN1_UART16550_H -#define _ASM_SN_SN1_UART16550_H +#ifndef _ASM_IA64_SN_UART16550_H +#define _ASM_IA64_SN_UART16550_H /* @@ -225,4 +224,4 @@ #define INC_RING_POINTER(x) \ ( ((x & 0xffe0) < 4064) ? (x += 32) : 0 ) -#endif /* _ASM_SN_SN1_UART16550_H */ +#endif /* _ASM_IA64_SN_UART16550_H */ diff --git a/include/asm-ia64/sn/vector.h b/include/asm-ia64/sn/vector.h index 9b064ac3d26e..bba730c55b07 100644 --- a/include/asm-ia64/sn/vector.h +++ b/include/asm-ia64/sn/vector.h @@ -4,11 +4,10 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ -#ifndef _ASM_SN_VECTOR_H -#define _ASM_SN_VECTOR_H +#ifndef _ASM_IA64_SN_VECTOR_H +#define _ASM_IA64_SN_VECTOR_H #include <linux/config.h> @@ -37,7 +36,7 @@ #endif /* RTL */ -#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) +#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) #define VECTOR_PARMS LB_VECTOR_PARMS #define VECTOR_ROUTE LB_VECTOR_ROUTE #define VECTOR_DATA LB_VECTOR_DATA @@ -66,19 +65,22 @@ #define VS_ERROR_MASK LVS_ERROR_MASK #endif -#define NET_ERROR_NONE 0 /* No error */ -#define NET_ERROR_HARDWARE -1 /* Hardware error */ -#define NET_ERROR_OVERRUN -2 /* Extra response(s) */ -#define NET_ERROR_REPLY -3 /* Reply parms mismatch */ -#define NET_ERROR_ADDRESS -4 /* Addr error response */ -#define NET_ERROR_COMMAND -5 /* Cmd error response */ -#define NET_ERROR_PROT -6 /* Prot error response */ -#define NET_ERROR_TIMEOUT -7 /* Too many retries */ -#define NET_ERROR_VECTOR -8 /* Invalid vector/path */ -#define NET_ERROR_ROUTERLOCK -9 /* Timeout locking rtr */ -#define NET_ERROR_INVAL -10 /* Invalid vector request */ - -#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS) +#define NET_ERROR_NONE 0 /* No error */ +#define NET_ERROR_HARDWARE (-1) /* Hardware error */ +#define NET_ERROR_OVERRUN (-2) /* Extra response(s) */ +#define NET_ERROR_REPLY (-3) /* Reply parms mismatch */ +#define NET_ERROR_ADDRESS (-4) /* Addr error response */ +#define NET_ERROR_COMMAND (-5) /* Cmd error response */ +#define NET_ERROR_PROT (-6) /* Prot error response */ +#define NET_ERROR_TIMEOUT (-7) /* Too many retries */ +#define NET_ERROR_VECTOR (-8) /* Invalid vector/path */ +#define NET_ERROR_ROUTERLOCK (-9) /* Timeout locking rtr */ +#define NET_ERROR_INVAL (-10) /* Invalid vector request */ + +#ifndef __ASSEMBLY__ +#include <linux/types.h> +#include <asm/sn/types.h> + typedef uint64_t net_reg_t; typedef uint64_t net_vec_t; @@ -114,6 +116,6 @@ int hub_vector_read(cnodeid_t cnode, net_vec_t vector, int writeid, int addr, net_reg_t *value); #endif -#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */ +#endif /* __ASSEMBLY__ */ -#endif /* _ASM_SN_VECTOR_H */ +#endif /* _ASM_IA64_SN_VECTOR_H */ diff --git a/include/asm-ia64/sn/xtalk/xbow.h b/include/asm-ia64/sn/xtalk/xbow.h index a15419dcd586..49aee311a4ed 100644 --- a/include/asm-ia64/sn/xtalk/xbow.h +++ b/include/asm-ia64/sn/xtalk/xbow.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. * Copyright (C) 2000 by Colin Ngam */ #ifndef _ASM_SN_SN_XTALK_XBOW_H @@ -17,7 +17,7 @@ #include <asm/sn/xtalk/xtalk.h> #include <asm/sn/xtalk/xwidget.h> #include <asm/sn/xtalk/xswitch.h> -#ifdef LANGUAGE_C +#ifndef __ASSEMBLY__ #include <asm/sn/xtalk/xbow_info.h> #endif @@ -46,7 +46,7 @@ #define MAX_XBOW_NAME 16 -#if LANGUAGE_C +#ifndef __ASSEMBLY__ typedef uint32_t xbowreg_t; #define XBOWCONST (xbowreg_t) @@ -236,7 +236,7 @@ typedef struct xbow_cfg_s { /* offset of arbitration register, given source widget id */ #define XBOW_ARB_OFF(wid) (XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24) -#endif /* LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ #define XBOW_WID_ID WIDGET_ID #define XBOW_WID_STAT WIDGET_STATUS @@ -402,7 +402,7 @@ typedef struct xbow_cfg_s { (XWIDGET_PART_NUM(XWIDGET_ID_READ(nasid, 0)) == XXBOW_WIDGET_PART_NUM) -#ifdef _LANGUAGE_C +#ifndef __ASSEMBLY__ /* * XBOW Widget 0 Register formats. * Format for many of these registers are similar to the standard @@ -891,5 +891,5 @@ struct macrofield_s xbow_macrofield[] = #endif /* MACROFIELD_LINE */ -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ #endif /* _ASM_SN_SN_XTALK_XBOW_H */ diff --git a/include/asm-ia64/sn/xtalk/xbow_info.h b/include/asm-ia64/sn/xtalk/xbow_info.h index 2d00840311d2..c4b32bb98a26 100644 --- a/include/asm-ia64/sn/xtalk/xbow_info.h +++ b/include/asm-ia64/sn/xtalk/xbow_info.h @@ -4,12 +4,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_XTALK_XBOW_INFO_H #define _ASM_SN_XTALK_XBOW_INFO_H +#include <linux/types.h> +#include <linux/devfs_fs_kernel.h> + #define XBOW_PERF_MODES 0x03 #define XBOW_PERF_COUNTERS 0x02 diff --git a/include/asm-ia64/sn/xtalk/xswitch.h b/include/asm-ia64/sn/xtalk/xswitch.h index 8ca7fbc40e0b..beb44a0271ec 100644 --- a/include/asm-ia64/sn/xtalk/xswitch.h +++ b/include/asm-ia64/sn/xtalk/xswitch.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_XTALK_XSWITCH_H #define _ASM_SN_XTALK_XSWITCH_H @@ -16,7 +15,10 @@ * xtalk bus providers. */ -#if LANGUAGE_C +#ifndef __ASSEMBLY__ + +#include <linux/devfs_fs_kernel.h> +#include <asm/sn/xtalk/xtalk.h> typedef struct xswitch_info_s *xswitch_info_t; @@ -54,6 +56,6 @@ extern devfs_handle_t xswitch_info_master_assignment_get(xswitch_info_t xswi extern int xswitch_id_get(devfs_handle_t vhdl); extern void xswitch_id_set(devfs_handle_t vhdl,int xbow_num); -#endif /* LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ #endif /* _ASM_SN_XTALK_XSWITCH_H */ diff --git a/include/asm-ia64/sn/xtalk/xtalk.h b/include/asm-ia64/sn/xtalk/xtalk.h index f14e8534d566..95ab7af95f9c 100644 --- a/include/asm-ia64/sn/xtalk/xtalk.h +++ b/include/asm-ia64/sn/xtalk/xtalk.h @@ -4,8 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_XTALK_XTALK_H #define _ASM_SN_XTALK_XTALK_H @@ -18,19 +17,19 @@ */ typedef char xwidgetnum_t; /* xtalk widget number (0..15) */ -#define XWIDGET_NONE -1 +#define XWIDGET_NONE (-1) typedef int xwidget_part_num_t; /* xtalk widget part number */ -#define XWIDGET_PART_NUM_NONE -1 +#define XWIDGET_PART_NUM_NONE (-1) typedef int xwidget_rev_num_t; /* xtalk widget revision number */ -#define XWIDGET_REV_NUM_NONE -1 +#define XWIDGET_REV_NUM_NONE (-1) typedef int xwidget_mfg_num_t; /* xtalk widget manufacturing ID */ -#define XWIDGET_MFG_NUM_NONE -1 +#define XWIDGET_MFG_NUM_NONE (-1) typedef struct xtalk_piomap_s *xtalk_piomap_t; @@ -57,7 +56,7 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t; #include <asm/sn/types.h> #include <asm/sn/alenlist.h> #include <asm/sn/ioerror.h> -#include <asm/sn/iobus.h> +#include <asm/sn/driver.h> #include <asm/sn/dmamap.h> struct xwidget_hwid_s; @@ -205,14 +204,8 @@ xtalk_intr_free_f (xtalk_intr_t intr_hdl); typedef int xtalk_intr_connect_f (xtalk_intr_t intr_hdl, /* xtalk intr resource handle */ - intr_func_t intr_func, /* xtalk intr handler */ - void *intr_arg, /* arg to intr handler */ xtalk_intr_setfunc_f *setfunc, /* func to set intr hw */ - void *setfunc_arg, /* arg to setfunc. This must be */ - /* sufficient to determine which */ - /* interrupt on which board needs */ - /* to be set. */ - void *thread); /* which intr thread to use */ + void *setfunc_arg); /* arg to setfunc */ typedef void xtalk_intr_disconnect_f (xtalk_intr_t intr_hdl); @@ -400,7 +393,6 @@ extern void xtalk_iterate(char *prefix, xtalk_iter_f *func); extern int xtalk_device_powerup(devfs_handle_t, xwidgetnum_t); extern int xtalk_device_shutdown(devfs_handle_t, xwidgetnum_t); -extern int xtalk_device_inquiry(devfs_handle_t, xwidgetnum_t); #endif /* __KERNEL__ */ #endif /* _ASM_SN_XTALK_XTALK_H */ diff --git a/include/asm-ia64/sn/xtalk/xtalk_private.h b/include/asm-ia64/sn/xtalk/xtalk_private.h index c82a5c995e27..14c024929d27 100644 --- a/include/asm-ia64/sn/xtalk/xtalk_private.h +++ b/include/asm-ia64/sn/xtalk/xtalk_private.h @@ -4,13 +4,15 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. - * Copyright (C) 2000 by Colin Ngam + * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc. All Rights Reserved. */ #ifndef _ASM_SN_XTALK_XTALK_PRIVATE_H #define _ASM_SN_XTALK_XTALK_PRIVATE_H #include <asm/sn/ioerror.h> /* for error function and arg types */ +#include <linux/devfs_fs_kernel.h> +#include <asm/sn/xtalk/xwidget.h> +#include <asm/sn/xtalk/xtalk.h> /* * xtalk_private.h -- private definitions for xtalk diff --git a/include/asm-ia64/sn/xtalk/xtalkaddrs.h b/include/asm-ia64/sn/xtalk/xtalkaddrs.h index d47d248ad64e..0f2069c90007 100644 --- a/include/asm-ia64/sn/xtalk/xtalkaddrs.h +++ b/include/asm-ia64/sn/xtalk/xtalkaddrs.h @@ -4,13 +4,12 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. * Copyright (C) 2000 by Colin Ngam */ #ifndef _ASM_SN_XTALK_XTALKADDRS_H #define _ASM_SN_XTALK_XTALKADDRS_H -#include <linux/config.h> /* * CrossTalk to SN0 Hub addressing support @@ -60,19 +59,15 @@ * This looks very much like a REMOTE_HUB access, except the nodeID * is in a different place, and the highest xtalk bit is set. */ - /* Hub-specific xtalk definitions */ #define HX_MEM_BIT 0L /* Hub's idea of xtalk memory access */ #define HX_IO_BIT 1L /* Hub's idea of xtalk register access */ #define HX_ACCTYPE_SHIFT 47 -#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC #define HX_NODE_SHIFT 39 -#endif #define HX_BIGWIN_SHIFT 28 - #define HX_SWIN_SHIFT 23 #define HX_LOCACC 0L /* local access */ diff --git a/include/asm-ia64/sn/xtalk/xwidget.h b/include/asm-ia64/sn/xtalk/xwidget.h index da74fc3d01ca..2331d636eb6a 100644 --- a/include/asm-ia64/sn/xtalk/xwidget.h +++ b/include/asm-ia64/sn/xtalk/xwidget.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc. + * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. * Copyright (C) 2000 by Colin Ngam */ #ifndef __ASM_SN_XTALK_XWIDGET_H__ @@ -15,9 +15,9 @@ */ #include <asm/sn/xtalk/xtalk.h> -#if LANGUAGE_C +#ifndef __ASSEMBLY__ #include <asm/sn/cdl.h> -#endif /* LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ #ifdef LITTLE_ENDIAN #define WIDGET_ID 0x00 @@ -115,7 +115,7 @@ * widget target flush register are widget dependent thus will not be * defined here */ -#if _LANGUAGE_C +#ifndef __ASSEMBLY__ typedef uint32_t widgetreg_t; /* widget configuration registers */ @@ -267,9 +267,6 @@ extern int xwidget_register(struct xwidget_hwid_s *hwid, async_attach_t aa); extern int xwidget_unregister(devfs_handle_t); -extern void xwidget_error_register(devfs_handle_t xwidget, - error_handler_f * efunc, - error_handler_arg_t einfo); extern void xwidget_reset(devfs_handle_t xwidget); extern void xwidget_gfx_reset(devfs_handle_t xwidget); @@ -289,6 +286,9 @@ extern xwidget_part_num_t xwidget_info_part_num_get(xwidget_info_t xwidget_info) extern xwidget_rev_num_t xwidget_info_rev_num_get(xwidget_info_t xwidget_info); extern xwidget_mfg_num_t xwidget_info_mfg_num_get(xwidget_info_t xwidget_info); +extern xwidgetnum_t hub_widget_id(nasid_t); + + /* * TBD: DELETE THIS ENTIRE STRUCTURE! Equivalent is now in @@ -303,6 +303,6 @@ typedef struct v_widget_s { } v_widget_t; #endif /* _KERNEL */ -#endif /* _LANGUAGE_C */ +#endif /* __ASSEMBLY__ */ #endif /* __ASM_SN_XTALK_XWIDGET_H__ */ diff --git a/include/asm-ia64/softirq.h b/include/asm-ia64/softirq.h index 8a833ab7c235..3f3864bf42fe 100644 --- a/include/asm-ia64/softirq.h +++ b/include/asm-ia64/softirq.h @@ -3,21 +3,21 @@ /* * Copyright (C) 1998-2001 Hewlett-Packard Co - * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com> + * David Mosberger-Tang <davidm@hpl.hp.com> */ #include <asm/hardirq.h> -#define __local_bh_enable() do { barrier(); local_bh_count()--; } while (0) +#define __local_bh_enable() do { barrier(); really_local_bh_count()--; } while (0) -#define local_bh_disable() do { local_bh_count()++; barrier(); } while (0) +#define local_bh_disable() do { really_local_bh_count()++; barrier(); } while (0) #define local_bh_enable() \ do { \ __local_bh_enable(); \ - if (__builtin_expect(local_softirq_pending(), 0) && local_bh_count() == 0) \ + if (__builtin_expect(local_softirq_pending(), 0) && really_local_bh_count() == 0) \ do_softirq(); \ } while (0) -#define in_softirq() (local_bh_count() != 0) +#define in_softirq() (really_local_bh_count() != 0) #endif /* _ASM_IA64_SOFTIRQ_H */ diff --git a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h index 7e4d3863ce19..12bf7ef3b853 100644 --- a/include/asm-ia64/spinlock.h +++ b/include/asm-ia64/spinlock.h @@ -2,8 +2,8 @@ #define _ASM_IA64_SPINLOCK_H /* - * Copyright (C) 1998-2001 Hewlett-Packard Co - * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com> + * Copyright (C) 1998-2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> * * This file is used for SMP configurations only. @@ -31,7 +31,7 @@ typedef struct { * rather than a simple xchg to avoid writing the cache-line when * there is contention. */ -#define spin_lock(x) \ +#define _raw_spin_lock(x) \ { \ register char *addr __asm__ ("r31") = (char *) &(x)->lock; \ \ @@ -49,7 +49,7 @@ typedef struct { : "ar.ccv", "ar.pfs", "b7", "p15", "r28", "r29", "r30", "memory"); \ } -#define spin_trylock(x) \ +#define _raw_spin_trylock(x) \ ({ \ register long result; \ \ @@ -62,7 +62,7 @@ typedef struct { }) #define spin_is_locked(x) ((x)->lock != 0) -#define spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0;} while (0) +#define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0;} while (0) #define spin_unlock_wait(x) do { barrier(); } while ((x)->lock) #else /* !NEW_LOCK */ @@ -79,7 +79,7 @@ typedef struct { * rather than a simple xchg to avoid writing the cache-line when * there is contention. */ -#define spin_lock(x) __asm__ __volatile__ ( \ +#define _raw_spin_lock(x) __asm__ __volatile__ ( \ "mov ar.ccv = r0\n" \ "mov r29 = 1\n" \ ";;\n" \ @@ -93,11 +93,11 @@ typedef struct { "cmp4.eq p0,p7 = r0, r2\n" \ "(p7) br.cond.spnt.few 1b\n" \ ";;\n" \ - :: "r"(&(x)->lock) : "r2", "r29", "memory") + :: "r"(&(x)->lock) : "ar.ccv", "p7", "r2", "r29", "memory") #define spin_is_locked(x) ((x)->lock != 0) -#define spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0) -#define spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0) +#define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0) +#define _raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0) #define spin_unlock_wait(x) do { barrier(); } while ((x)->lock) #endif /* !NEW_LOCK */ @@ -110,7 +110,7 @@ typedef struct { #define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0) -#define read_lock(rw) \ +#define _raw_read_lock(rw) \ do { \ int tmp = 0; \ __asm__ __volatile__ ("1:\tfetchadd4.acq %0 = [%1], 1\n" \ @@ -128,10 +128,10 @@ do { \ ";;\n" \ ".previous\n" \ : "=&r" (tmp) \ - : "r" (rw): "memory"); \ + : "r" (rw) : "p6", "memory"); \ } while(0) -#define read_unlock(rw) \ +#define _raw_read_unlock(rw) \ do { \ int tmp = 0; \ __asm__ __volatile__ ("fetchadd4.rel %0 = [%1], -1\n" \ @@ -140,7 +140,7 @@ do { \ : "memory"); \ } while(0) -#define write_lock(rw) \ +#define _raw_write_lock(rw) \ do { \ __asm__ __volatile__ ( \ "mov ar.ccv = r0\n" \ @@ -156,13 +156,13 @@ do { \ "cmp4.eq p0,p7 = r0, r2\n" \ "(p7) br.cond.spnt.few 1b\n" \ ";;\n" \ - :: "r"(rw) : "r2", "r29", "memory"); \ + :: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory"); \ } while(0) -/* - * clear_bit() has "acq" semantics; we're really need "rel" semantics, - * but for simplicity, we simply do a fence for now... - */ -#define write_unlock(x) ({clear_bit(31, (x)); mb();}) +#define _raw_write_unlock(x) \ +({ \ + smp_mb__before_clear_bit(); /* need barrier before releasing lock... */ \ + clear_bit(31, (x)); \ +}) #endif /* _ASM_IA64_SPINLOCK_H */ diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h index 777e2ab81080..5cbf1dac47b3 100644 --- a/include/asm-ia64/system.h +++ b/include/asm-ia64/system.h @@ -7,8 +7,8 @@ * on information published in the Processor Abstraction Layer * and the System Abstraction Layer manual. * - * Copyright (C) 1998-2001 Hewlett-Packard Co - * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com> + * Copyright (C) 1998-2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> */ @@ -232,7 +232,7 @@ extern unsigned long __bad_increment_for_ia64_fetch_and_add (void); _tmp = __bad_increment_for_ia64_fetch_and_add(); \ break; \ } \ - (__typeof__(*v)) (_tmp + (i)); /* return new value */ \ + (__typeof__(*(v))) (_tmp + (i)); /* return new value */ \ }) /* @@ -373,19 +373,27 @@ extern long __cmpxchg_called_with_bad_pointer(void); * newly created thread returns directly to * ia64_ret_from_syscall_clear_r8. */ -extern struct task_struct *ia64_switch_to (void *next_task); +extern void ia64_switch_to (void *next_task); + +struct task_struct; extern void ia64_save_extra (struct task_struct *task); extern void ia64_load_extra (struct task_struct *task); -#define __switch_to(prev,next,last) do { \ +#if defined(CONFIG_SMP) && defined(CONFIG_PERFMON) +# define PERFMON_IS_SYSWIDE() (local_cpu_data->pfm_syst_wide != 0) +#else +# define PERFMON_IS_SYSWIDE() (0) +#endif + +#define __switch_to(prev,next) do { \ if (((prev)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID)) \ - || IS_IA32_PROCESS(ia64_task_regs(prev))) \ + || IS_IA32_PROCESS(ia64_task_regs(prev)) || PERFMON_IS_SYSWIDE()) \ ia64_save_extra(prev); \ if (((next)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID)) \ - || IS_IA32_PROCESS(ia64_task_regs(next))) \ + || IS_IA32_PROCESS(ia64_task_regs(next)) || PERFMON_IS_SYSWIDE()) \ ia64_load_extra(next); \ - (last) = ia64_switch_to((next)); \ + ia64_switch_to((next)); \ } while (0) #ifdef CONFIG_SMP @@ -396,19 +404,19 @@ extern void ia64_load_extra (struct task_struct *task); * task->thread.fph, avoiding the complication of having to fetch * the latest fph state from another CPU. */ -# define switch_to(prev,next,last) do { \ +# define switch_to(prev,next) do { \ if (ia64_psr(ia64_task_regs(prev))->mfh) { \ ia64_psr(ia64_task_regs(prev))->mfh = 0; \ (prev)->thread.flags |= IA64_THREAD_FPH_VALID; \ __ia64_save_fpu((prev)->thread.fph); \ } \ ia64_psr(ia64_task_regs(prev))->dfh = 1; \ - __switch_to(prev,next,last); \ + __switch_to(prev,next); \ } while (0) #else -# define switch_to(prev,next,last) do { \ +# define switch_to(prev,next) do { \ ia64_psr(ia64_task_regs(next))->dfh = (ia64_get_fpu_owner() != (next)); \ - __switch_to(prev,next,last); \ + __switch_to(prev,next); \ } while (0) #endif diff --git a/include/asm-ia64/thread_info.h b/include/asm-ia64/thread_info.h new file mode 100644 index 000000000000..6c6b9e143f20 --- /dev/null +++ b/include/asm-ia64/thread_info.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> + */ +#ifndef _ASM_IA64_THREAD_INFO_H +#define _ASM_IA64_THREAD_INFO_H + +#include <asm/offsets.h> +#include <asm/processor.h> +#include <asm/ptrace.h> + +#define TI_EXEC_DOMAIN 0x00 +#define TI_FLAGS 0x08 +#define TI_CPU 0x0c +#define TI_ADDR_LIMI 0x10 + +#ifndef __ASSEMBLY__ + +/* + * On IA-64, we want to keep the task structure and kernel stack together, so they can be + * mapped by a single TLB entry and so they can be addressed by the "current" pointer + * without having to do pointer masking. + */ +struct thread_info { + struct exec_domain *exec_domain;/* execution domain */ + __u32 flags; /* thread_info flags (see TIF_*) */ + __u32 cpu; /* current CPU */ + mm_segment_t addr_limit; /* user-level address space limit */ +}; + +#define INIT_THREAD_SIZE /* tell sched.h not to declare the thread_union */ +#define THREAD_SIZE KERNEL_STACK_SIZE + +#define INIT_THREAD_INFO(ti) \ +{ \ + exec_domain: &default_exec_domain, \ + flags: 0, \ + cpu: 0, \ + addr_limit: KERNEL_DS, \ +} + +/* how to get the thread information struct from C */ +#define current_thread_info() ((struct thread_info *) ((char *) current + IA64_TASK_SIZE)) + +#endif /* !__ASSEMBLY */ + +/* + * thread information flags + * - these are process state flags that various assembly files may need to access + * - pending work-to-be-done flags are in least-significant 16 bits, other flags + * in top 16 bits + */ +#define TIF_NOTIFY_RESUME 0 /* resumption notification requested */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_SYSCALL_TRACE 3 /* syscall trace active */ +#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */ + +#define TIF_WORK_MASK 0x7 /* like TIF_ALLWORK_BITS but sans TIF_SYSCALL_TRACE */ +#define TIF_ALLWORK_MASK 0xf /* bits 0..3 are "work to do on user-return" bits */ + +#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) +#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME) +#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) +#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) +#define _TIF_USEDFPU (1 << TIF_USEDFPU) +#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) + +#endif /* _ASM_IA64_THREAD_INFO_H */ diff --git a/include/asm-ia64/uaccess.h b/include/asm-ia64/uaccess.h index 6e136ae35105..b53b244d80e2 100644 --- a/include/asm-ia64/uaccess.h +++ b/include/asm-ia64/uaccess.h @@ -26,8 +26,8 @@ * associated and, if so, sets r8 to -EFAULT and clears r9 to 0 and * then resumes execution at the continuation point. * - * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co - * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang <davidm@hpl.hp.com> + * Copyright (C) 1998, 1999, 2001-2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> */ #include <linux/errno.h> @@ -45,8 +45,8 @@ #define VERIFY_WRITE 1 #define get_ds() (KERNEL_DS) -#define get_fs() (current->addr_limit) -#define set_fs(x) (current->addr_limit = (x)) +#define get_fs() (current_thread_info()->addr_limit) +#define set_fs(x) (current_thread_info()->addr_limit = (x)) #define segment_eq(a,b) ((a).seg == (b).seg) diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h index f594a382db4e..f0dd2bfcc58f 100644 --- a/include/asm-ia64/unistd.h +++ b/include/asm-ia64/unistd.h @@ -4,7 +4,7 @@ /* * IA-64 Linux syscall numbers and inline-functions. * - * Copyright (C) 1998-2001 Hewlett-Packard Co + * Copyright (C) 1998-2002 Hewlett-Packard Co * David Mosberger-Tang <davidm@hpl.hp.com> */ @@ -109,9 +109,9 @@ #define __NR_syslog 1117 #define __NR_setitimer 1118 #define __NR_getitimer 1119 -#define __NR_old_stat 1120 -#define __NR_old_lstat 1121 -#define __NR_old_fstat 1122 +/* 1120 was __NR_old_stat */ +/* 1121 was __NR_old_lstat */ +/* 1122 was __NR_old_fstat */ #define __NR_vhangup 1123 #define __NR_lchown 1124 #define __NR_vm86 1125 @@ -206,7 +206,19 @@ #define __NR_getdents64 1214 #define __NR_getunwind 1215 #define __NR_readahead 1216 -#define __NR_tkill 1217 +#define __NR_setxattr 1217 +#define __NR_lsetxattr 1218 +#define __NR_fsetxattr 1219 +#define __NR_getxattr 1220 +#define __NR_lgetxattr 1221 +#define __NR_fgetxattr 1222 +#define __NR_listxattr 1223 +#define __NR_llistxattr 1224 +#define __NR_flistxattr 1225 +#define __NR_removexattr 1226 +#define __NR_lremovexattr 1227 +#define __NR_fremovexattr 1228 +#define __NR_tkill 1229 #if !defined(__ASSEMBLY__) && !defined(ASSEMBLER) @@ -282,6 +294,8 @@ name (type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \ #ifdef __KERNEL_SYSCALLS__ +struct rusage; + static inline _syscall0(int,sync) static inline _syscall0(pid_t,setsid) static inline _syscall3(int,write,int,fd,const char *,buf,off_t,count) diff --git a/include/linux/mm.h b/include/linux/mm.h index 543c93e1eb7a..35ea7c71b53e 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -104,7 +104,7 @@ struct vm_area_struct { #define VM_DONTEXPAND 0x00040000 /* Cannot expand with mremap() */ #define VM_RESERVED 0x00080000 /* Don't unmap it from swap_out */ -#define VM_STACK_FLAGS 0x00000177 +#define VM_STACK_FLAGS (0x00000100 | VM_DATA_DEFAULT_FLAGS) #define VM_READHINTMASK (VM_SEQ_READ | VM_RAND_READ) #define VM_ClearReadHint(v) (v)->vm_flags &= ~VM_READHINTMASK |