diff options
| author | Dave Jones <davej@codemonkey.org.uk> | 2002-11-20 20:24:53 -0800 |
|---|---|---|
| committer | Dave Jones <davej@codemonkey.org.uk> | 2002-11-20 20:24:53 -0800 |
| commit | 7d7f493a6545cd171e4601b47d5aabccf89c66e2 (patch) | |
| tree | ed645276abccf360d4fc556b2ebae9d1e9090229 /include | |
| parent | d04e13f07b945e4f2ff99f1e721964b266df602d (diff) | |
[PATCH] A new Athlon 'bug'.
Very recent Athlons (Model 8 stepping 1 and above) (XPs/MPs and mobiles)
have an interesting problem. Certain bits in the CLK_CTL register need
to be programmed differently to those in earlier models. The problem arises
when people plug these new CPUs into boards running BIOSes that are unaware
of this fact.
The fix is to reprogram CLK_CTL to 200xxxxx instead of 0x600xxxxx as it was
in previous models. The AMD folks have found that this improves stability.
The patch below does this reprogramming if an affected model/bios is
detected.
I'm interested if someone with an affected model could run some
benchmarks before and after to also see if this affects performance.
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-i386/msr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h index 8eefc078d95e..f8819948d629 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-i386/msr.h @@ -107,6 +107,7 @@ #define MSR_K7_PERFCTR2 0xC0010006 #define MSR_K7_PERFCTR3 0xC0010007 #define MSR_K7_HWCR 0xC0010015 +#define MSR_K7_CLK_CTL 0xC001001b #define MSR_K7_FID_VID_CTL 0xC0010041 #define MSR_K7_VID_STATUS 0xC0010042 |