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| author | Stephen Boyd <sboyd@kernel.org> | 2025-01-07 11:42:23 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2025-01-07 11:42:23 -0800 |
| commit | 83f6c3dea942d1f2032cfc67edf30cd448fd54ad (patch) | |
| tree | eeee4ec7680acfdf5307985b865ebfd4ca2e4ee8 /include | |
| parent | 39a72b4fedd0669ff49d0051efc763e729da56bf (diff) | |
| parent | e91609f1c3b0ce06d80b1b3bd0e6b942782be016 (diff) | |
Merge tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the RZ/G3E (R9A09G047) SoC
- Add Module Stop (MSTOP) support on RZ/V2H
- Add Image Signal Processor helper block (FCPVX and VSPX) clocks on
R-Car V4H SoC
- Add System Controller (SYS) reset and Generic Interrupt Controller
(GIC) clock and reset entries on RZ/V2H
* tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard
clk: renesas: r9a09g057: Add clock and reset entries for GIC
clk: renesas: r9a09g057: Add reset entry for SYS
clk: renesas: r8a779g0: Add VSPX clocks
clk: renesas: r8a779g0: Add FCPVX clocks
clk: renesas: r9a09g047: Add I2C clocks/resets
clk: renesas: r9a09g047: Add CA55 core clocks
clk: renesas: rzv2h: Add support for RZ/G3E SoC
clk: renesas: rzv2h: Add MSTOP support
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a08g045-vbattb.h | 6 | ||||
| -rw-r--r-- | include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 21 |
2 files changed, 24 insertions, 3 deletions
diff --git a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h index 67774eafad06..4cc8fc34b23c 100644 --- a/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h +++ b/include/dt-bindings/clock/renesas,r9a08g045-vbattb.h @@ -2,12 +2,12 @@ * * Copyright (C) 2024 Renesas Electronics Corp. */ -#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ -#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__ #define VBATTB_XC 0 #define VBATTB_XBYP 1 #define VBATTB_MUX 2 #define VBATTB_VBATTCLK 3 -#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */ +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A08G045_VBATTB_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h new file mode 100644 index 000000000000..1d031bf6bf03 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* Core Clock list */ +#define R9A09G047_SYS_0_PCLK 0 +#define R9A09G047_CA55_0_CORECLK0 1 +#define R9A09G047_CA55_0_CORECLK1 2 +#define R9A09G047_CA55_0_CORECLK2 3 +#define R9A09G047_CA55_0_CORECLK3 4 +#define R9A09G047_CA55_0_PERIPHCLK 5 +#define R9A09G047_CM33_CLK0 6 +#define R9A09G047_CST_0_SWCLKTCK 7 +#define R9A09G047_IOTOP_0_SHCLK 8 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */ |