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authorAndi Kleen <ak@muc.de>2002-12-27 19:54:22 -0800
committerLinus Torvalds <torvalds@home.transmeta.com>2002-12-27 19:54:22 -0800
commit8b3c4cbfc0e727c76b53e55f22610d814e44dc97 (patch)
tree5c6a529bba4f0e4b3ac8bda8e993a056722ae9b2 /include
parent1e1144fdf0e2d624e641e8017737f230480289c1 (diff)
[PATCH] Add AMD K8 support to 2.5.53.
Add support for the AMD Opteron/Athlon64/Hammer/K8 line to the 32bit kernel. Mostly just reusing Athlon code with some changed CPU model checks. The Hammer has model number 15. I also fixed rmb()/mb() to use the SSE2 mfence/lfence instructions on P4 and Hammer. They are somewhat cheaper than the locked cycle.
Diffstat (limited to 'include')
-rw-r--r--include/asm-i386/bugs.h5
-rw-r--r--include/asm-i386/cpufeature.h1
-rw-r--r--include/asm-i386/system.h6
3 files changed, 11 insertions, 1 deletions
diff --git a/include/asm-i386/bugs.h b/include/asm-i386/bugs.h
index f236e21749ab..5410e84760e6 100644
--- a/include/asm-i386/bugs.h
+++ b/include/asm-i386/bugs.h
@@ -193,6 +193,11 @@ static void __init check_config(void)
&& (boot_cpu_data.x86_mask < 6 || boot_cpu_data.x86_mask == 11))
panic("Kernel compiled for PMMX+, assumes a local APIC without the read-before-write bug!");
#endif
+
+#ifdef CONFIG_X86_SSE2
+ if (!cpu_has_sse2)
+ panic("Kernel compiled for SSE2, CPU doesn't have it.");
+#endif
}
static void __init check_bugs(void)
diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h
index 92ff7f79dee4..5f019713fa4c 100644
--- a/include/asm-i386/cpufeature.h
+++ b/include/asm-i386/cpufeature.h
@@ -75,6 +75,7 @@
#define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
#define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE)
#define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
+#define cpu_has_sse2 boot_cpu_has(X86_FEATURE_XMM2)
#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
#define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h
index fc8f116430bc..e085e51e9d25 100644
--- a/include/asm-i386/system.h
+++ b/include/asm-i386/system.h
@@ -288,9 +288,13 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
* nop for these.
*/
+#ifdef CONFIG_X86_SSE2
+#define mb() asm volatile("mfence" ::: "memory")
+#define rmb() asm volatile("lfence" ::: "memory")
+#else
#define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
#define rmb() mb()
-
+#endif
/**
* read_barrier_depends - Flush all pending reads that subsequents reads
* depend on.