Merge bk://ppc.bkbits.net/for-linus-ppc

into ppc970.osdl.org:/home/torvalds/v2.5/linux

8 files changed, 441 insertions, 170 deletions

diff --git a/include/asm-ppc/dma-mapping.h b/include/asm-ppc/dma-mapping.h
index e7e16901f686..d38cd112c1c4 100644
--- a/include/asm-ppc/dma-mapping.h
+++ b/include/asm-ppc/dma-mapping.h
@@ -1 +1,153 @@
-#include <asm-generic/dma-mapping.h>
+/*
+ * This is based on both include/asm-sh/dma-mapping.h and
+ * include/asm-ppc/pci.h
+ */
+#ifndef __ASM_PPC_DMA_MAPPING_H
+#define __ASM_PPC_DMA_MAPPING_H
+
+#include <linux/config.h>
+/* we implement the API below in terms of the existing PCI one,
+ * so include it */
+#include <linux/pci.h>
+/* need struct page definitions */
+#include <linux/mm.h>
+#include <linux/device.h>
+#include <asm/scatterlist.h>
+#include <asm/io.h>
+
+#define dma_supported(dev, mask)	(1)
+
+static inline int dma_set_mask(struct device *dev, u64 dma_mask)
+{
+	if (!dev->dma_mask || !dma_supported(dev, mask))
+		return -EIO;
+
+	*dev->dma_mask = dma_mask;
+
+	return 0;
+}
+
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+				       dma_addr_t * dma_handle, int flag)
+{
+#ifdef CONFIG_PCI
+	if (dev && dev->bus == &pci_bus_type)
+		return pci_alloc_consistent(to_pci_dev(dev), size, dma_handle);
+#endif
+
+	return consistent_alloc(flag, size, dma_handle);
+}
+
+static inline void
+dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+		  dma_addr_t dma_handle)
+{
+#ifdef CONFIG_PCI
+	if (dev && dev->bus == &pci_bus_type) {
+		pci_free_consistent(to_pci_dev(dev), size, vaddr, dma_handle);
+		return;
+	}
+#endif
+
+	consistent_free(vaddr);
+}
+
+static inline dma_addr_t
+dma_map_single(struct device *dev, void *ptr, size_t size,
+	       enum dma_data_direction direction)
+{
+	BUG_ON(direction == DMA_NONE);
+
+	consistent_sync(ptr, size, direction);
+
+	return virt_to_bus(ptr);
+}
+
+/* We do nothing. */
+#define dma_unmap_single(dev, addr, size, dir)	do { } while (0)
+
+static inline dma_addr_t
+dma_map_page(struct device *dev, struct page *page,
+	     unsigned long offset, size_t size,
+	     enum dma_data_direction direction)
+{
+	BUG_ON(direction == DMA_NONE);
+	consistent_sync_page(page, offset, size, direction);
+	return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset;
+}
+
+/* We do nothing. */
+#define dma_unmap_single(dev, addr, size, dir)	do { } while (0)
+
+static inline int
+dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+	   enum dma_data_direction direction)
+{
+	int i;
+
+	BUG_ON(direction == DMA_NONE);
+
+	for (i = 0; i < nents; i++, sg++) {
+		BUG_ON(!sg->page);
+		consistent_sync_page(sg->page, sg->offset,
+				     sg->length, direction);
+		sg->dma_address = page_to_bus(sg->page) + sg->offset;
+	}
+
+	return nents;
+}
+
+/* We don't do anything here. */
+#define dma_unmap_sg(dev, sg, nents, dir)	do { } while (0)
+
+static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
+				   size_t size,
+				   enum dma_data_direction direction)
+{
+	BUG_ON(direction == DMA_NONE);
+
+	consistent_sync(bus_to_virt(dma_handle), size, direction);
+}
+
+static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
+			       int nelems, enum dma_data_direction direction)
+{
+	int i;
+
+	BUG_ON(direction == DMA_NONE);
+
+	for (i = 0; i < nelems; i++, sg++)
+		consistent_sync_page(sg->page, sg->offset,
+				     sg->length, direction);
+}
+
+/* Now for the API extensions over the pci_ one */
+
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+#define dma_is_consistent(d)	(1)
+
+static inline int dma_get_cache_alignment(void)
+{
+	/*
+	 * Each processor family will define its own L1_CACHE_SHIFT,
+	 * L1_CACHE_BYTES wraps to this, so this is always safe.
+	 */
+	return L1_CACHE_BYTES;
+}
+
+static inline void
+dma_sync_single_range(struct device *dev, dma_addr_t dma_handle,
+		      unsigned long offset, size_t size,
+		      enum dma_data_direction direction)
+{
+	/* just sync everything, that's all the pci API can do */
+	dma_sync_single(dev, dma_handle, offset + size, direction);
+}
+
+static inline void dma_cache_sync(void *vaddr, size_t size,
+				  enum dma_data_direction direction)
+{
+	consistent_sync(vaddr, size, (int)direction);
+}
+#endif				/* __ASM_PPC_DMA_MAPPING_H */
diff --git a/include/asm-ppc/hawk.h b/include/asm-ppc/hawk.h
new file mode 100644
index 000000000000..a6569106af91
--- /dev/null
+++ b/include/asm-ppc/hawk.h
@@ -0,0 +1,32 @@
+/*
+ * include/asm-ppc/hawk.h
+ *
+ * Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
+ *
+ * Author: Mark A. Greer
+ *         mgreer@mvista.com
+ *
+ * Modified by Randy Vinson (rvinson@mvista.com)
+ *
+ * 2001,2004 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ASMPPC_HAWK_H
+#define __ASMPPC_HAWK_H
+
+#include <asm/pci-bridge.h>
+#include <asm/hawk_defs.h>
+
+extern int hawk_init(struct pci_controller *hose,
+	      unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
+	      unsigned long processor_pci_mem_end,
+	      unsigned long processor_pci_io_start,
+	      unsigned long processor_pci_io_end,
+	      unsigned long processor_mpic_base);
+extern unsigned long hawk_get_mem_size(unsigned int smc_base);
+extern int hawk_mpic_init(unsigned int pci_mem_offset);
+
+#endif				/* __ASMPPC_PPLUS_H */
diff --git a/include/asm-ppc/hawk_defs.h b/include/asm-ppc/hawk_defs.h
new file mode 100644
index 000000000000..6d1d2baf648c
--- /dev/null
+++ b/include/asm-ppc/hawk_defs.h
@@ -0,0 +1,76 @@
+/*
+ * include/asm-ppc/hawk_defs.h
+ *
+ * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
+ *
+ * Author: Mark A. Greer
+ *         mgreer@mvista.com
+ *
+ * Modified by Randy Vinson (rvinson@mvista.com)
+ *
+ * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ASMPPC_HAWK_DEFS_H
+#define __ASMPPC_HAWK_DEFS_H
+
+#include <asm/pci-bridge.h>
+
+/*
+ * The Falcon/Raven and HAWK have 4 sets of registers:
+ *   1) PPC Registers which define the mappings from PPC bus to PCI bus,
+ *      etc.
+ *   2) PCI Registers which define the mappings from PCI bus to PPC bus and the
+ *      MPIC base address.
+ *   3) MPIC registers
+ *   4) System Memory Controller (SMC) registers.
+ */
+
+#define HAWK_PCI_CONFIG_ADDR_OFF	0x00000cf8
+#define HAWK_PCI_CONFIG_DATA_OFF	0x00000cfc
+
+#define HAWK_MPIC_SIZE			0x00040000U
+#define HAWK_SMC_SIZE			0x00001000U
+
+/*
+ * Define PPC register offsets.
+ */
+#define HAWK_PPC_XSADD0_OFF			0x40
+#define HAWK_PPC_XSOFF0_OFF			0x44
+#define HAWK_PPC_XSADD1_OFF			0x48
+#define HAWK_PPC_XSOFF1_OFF			0x4c
+#define HAWK_PPC_XSADD2_OFF			0x50
+#define HAWK_PPC_XSOFF2_OFF			0x54
+#define HAWK_PPC_XSADD3_OFF			0x58
+#define HAWK_PPC_XSOFF3_OFF			0x5c
+
+/*
+ * Define PCI register offsets.
+ */
+#define HAWK_PCI_PSADD0_OFF			0x80
+#define HAWK_PCI_PSOFF0_OFF			0x84
+#define HAWK_PCI_PSADD1_OFF			0x88
+#define HAWK_PCI_PSOFF1_OFF			0x8c
+#define HAWK_PCI_PSADD2_OFF			0x90
+#define HAWK_PCI_PSOFF2_OFF			0x94
+#define HAWK_PCI_PSADD3_OFF			0x98
+#define HAWK_PCI_PSOFF3_OFF			0x9c
+
+/*
+ * Define the System Memory Controller (SMC) register offsets.
+ */
+#define HAWK_SMC_RAM_A_SIZE_REG_OFF		0x10
+#define HAWK_SMC_RAM_B_SIZE_REG_OFF		0x11
+#define HAWK_SMC_RAM_C_SIZE_REG_OFF		0x12
+#define HAWK_SMC_RAM_D_SIZE_REG_OFF		0x13
+#define HAWK_SMC_RAM_E_SIZE_REG_OFF		0xc0	/* HAWK Only */
+#define HAWK_SMC_RAM_F_SIZE_REG_OFF		0xc1	/* HAWK Only */
+#define HAWK_SMC_RAM_G_SIZE_REG_OFF		0xc2	/* HAWK Only */
+#define HAWK_SMC_RAM_H_SIZE_REG_OFF		0xc3	/* HAWK Only */
+
+#define FALCON_SMC_REG_COUNT			4
+#define HAWK_SMC_REG_COUNT			8
+#endif				/* __ASMPPC_HAWK_DEFS_H */
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 0c78d0c505c7..8bfae09098eb 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -82,7 +82,6 @@ extern unsigned long pci_dram_offset;
 #define insl(port, buf, nl)	_insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
 #define outsl(port, buf, nl)	_outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
 
-#ifdef CONFIG_PPC_PMAC
 /*
  * On powermacs, we will get a machine check exception if we
  * try to read data from a non-existent I/O port.  Because the
@@ -94,7 +93,7 @@ extern unsigned long pci_dram_offset;
  * all PPC implementations tested so far.  The twi and isync are
  * needed on the 601 (in fact twi; sync works too), the isync and
  * nop are needed on 604[e|r], and any of twi, sync or isync will
- * work on 603[e], 750, 74x0.
+ * work on 603[e], 750, 74xx.
  * The twi creates an explicit data dependency on the returned
  * value which seems to be needed to make the 601 wait for the
  * load to finish.
@@ -140,27 +139,17 @@ extern __inline__ void name(unsigned int val, unsigned int port) \
 }
 
 __do_in_asm(inb, "lbzx")
+__do_out_asm(outb, "stbx")
+#ifdef CONFIG_APUS
+__do_in_asm(inw, "lhz%U1%X1")
+__do_in_asm(inl, "lwz%U1%X1")
+__do_out_asm(outl,"stw%U0%X0")
+__do_out_asm(outw, "sth%U0%X0")
+#else
 __do_in_asm(inw, "lhbrx")
 __do_in_asm(inl, "lwbrx")
-__do_out_asm(outb, "stbx")
 __do_out_asm(outw, "sthbrx")
 __do_out_asm(outl, "stwbrx")
-
-#elif defined(CONFIG_APUS)
-#define inb(port)		in_8((u8 *)((port)+_IO_BASE))
-#define outb(val, port)		out_8((u8 *)((port)+_IO_BASE), (val))
-#define inw(port)		in_be16((u16 *)((port)+_IO_BASE))
-#define outw(val, port)		out_be16((u16 *)((port)+_IO_BASE), (val))
-#define inl(port)		in_be32((u32 *)((port)+_IO_BASE))
-#define outl(val, port)		out_be32((u32 *)((port)+_IO_BASE), (val))
-
-#else /* not APUS or PMAC */
-#define inb(port)		in_8((u8 *)((port)+_IO_BASE))
-#define outb(val, port)		out_8((u8 *)((port)+_IO_BASE), (val))
-#define inw(port)		in_le16((u16 *)((port)+_IO_BASE))
-#define outw(val, port)		out_le16((u16 *)((port)+_IO_BASE), (val))
-#define inl(port)		in_le32((u32 *)((port)+_IO_BASE))
-#define outl(val, port)		out_le32((u32 *)((port)+_IO_BASE), (val))
 #endif
 
 #define inb_p(port)		inb((port))
@@ -291,12 +280,19 @@ extern inline void eieio(void)
 
 /*
  * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ *
+ * Read operations have additional twi & isync to make sure the read
+ * is actually performed (i.e. the data has come back) before we start
+ * executing any following instructions.
  */
 extern inline int in_8(volatile unsigned char *addr)
 {
 	int ret;
 
-	__asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+	__asm__ __volatile__(
+		"lbz%U1%X1 %0,%1;\n"
+		"twi 0,%0,0;\n"
+		"isync" : "=r" (ret) : "m" (*addr));
 	return ret;
 }
 
@@ -309,7 +305,9 @@ extern inline int in_le16(volatile unsigned short *addr)
 {
 	int ret;
 
-	__asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
+	__asm__ __volatile__("lhbrx %0,0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) :
 			      "r" (addr), "m" (*addr));
 	return ret;
 }
@@ -318,7 +316,9 @@ extern inline int in_be16(volatile unsigned short *addr)
 {
 	int ret;
 
-	__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+	__asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) : "m" (*addr));
 	return ret;
 }
 
@@ -337,7 +337,9 @@ extern inline unsigned in_le32(volatile unsigned *addr)
 {
 	unsigned ret;
 
-	__asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
+	__asm__ __volatile__("lwbrx %0,0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) :
 			     "r" (addr), "m" (*addr));
 	return ret;
 }
@@ -346,7 +348,9 @@ extern inline unsigned in_be32(volatile unsigned *addr)
 {
 	unsigned ret;
 
-	__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
+	__asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
+			     "twi 0,%0,0;\n"
+			     "isync" : "=r" (ret) : "m" (*addr));
 	return ret;
 }
 
@@ -417,7 +421,7 @@ extern void consistent_sync_page(struct page *page, unsigned long offset,
 #define dma_cache_wback_inv(_start,_size)	do { } while (0)
 
 #define consistent_alloc(gfp, size, handle)	NULL
-#define consistent_free(addr, size)		do { } while (0)
+#define consistent_free(addr)			do { } while (0)
 #define consistent_sync(addr, size, rw)		do { } while (0)
 #define consistent_sync_page(pg, off, sz, rw)	do { } while (0)
 
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h
index e9c800d8fc09..4ace72fc4e7b 100644
--- a/include/asm-ppc/machdep.h
+++ b/include/asm-ppc/machdep.h
@@ -43,6 +43,8 @@ struct machdep_calls {
 	long		(*time_init)(void); /* Optional, may be NULL */
 	int		(*set_rtc_time)(unsigned long nowtime);
 	unsigned long	(*get_rtc_time)(void);
+	unsigned char 	(*rtc_read_val)(int addr);
+	void		(*rtc_write_val)(int addr, unsigned char val);
 	void		(*calibrate_decr)(void);
 
 	void		(*heartbeat)(void);
diff --git a/include/asm-ppc/pplus.h b/include/asm-ppc/pplus.h
deleted file mode 100644
index 0a3f11e40de8..000000000000
--- a/include/asm-ppc/pplus.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * include/asm-ppc/pplus.h
- *
- * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
- *
- * Author: Mark A. Greer
- *         mgreer@mvista.com
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASMPPC_PPLUS_H
-#define __ASMPPC_PPLUS_H
-
-#include <asm/pci-bridge.h>
-
-/*
- * The Falcon/Raven and HAWK have 4 sets of registers:
- *   1) PPC Registers which define the mappings from PPC bus to PCI bus,
- *      etc.
- *   2) PCI Registers which define the mappings from PCI bus to PPC bus and the
- *      MPIC base address.
- *   3) MPIC registers
- *   4) System Memory Controller (SMC) registers.
- */
-
-#define	PPLUS_RAVEN_VEND_DEV_ID		0x48011057
-#define	PPLUS_HAWK_VEND_DEV_ID		0x48031057
-
-#define	PPLUS_PCI_CONFIG_ADDR_OFF	0x00000cf8
-#define	PPLUS_PCI_CONFIG_DATA_OFF	0x00000cfc
-
-#define PPLUS_MPIC_SIZE			0x00040000U
-#define PPLUS_SMC_SIZE			0x00001000U
-
-/*
- * Define PPC register offsets.
- */
-#define PPLUS_PPC_XSADD0_OFF			0x40
-#define PPLUS_PPC_XSOFF0_OFF			0x44
-#define PPLUS_PPC_XSADD1_OFF			0x48
-#define PPLUS_PPC_XSOFF1_OFF			0x4c
-#define PPLUS_PPC_XSADD2_OFF			0x50
-#define PPLUS_PPC_XSOFF2_OFF			0x54
-#define PPLUS_PPC_XSADD3_OFF			0x58
-#define PPLUS_PPC_XSOFF3_OFF			0x5c
-
-/*
- * Define PCI register offsets.
- */
-#define PPLUS_PCI_PSADD0_OFF			0x80
-#define PPLUS_PCI_PSOFF0_OFF			0x84
-#define PPLUS_PCI_PSADD1_OFF			0x88
-#define PPLUS_PCI_PSOFF1_OFF			0x8c
-#define PPLUS_PCI_PSADD2_OFF			0x90
-#define PPLUS_PCI_PSOFF2_OFF			0x94
-#define PPLUS_PCI_PSADD3_OFF			0x98
-#define PPLUS_PCI_PSOFF3_OFF			0x9c
-
-/*
- * Define the System Memory Controller (SMC) register offsets.
- */
-#define PPLUS_SMC_RAM_A_SIZE_REG_OFF		0x10
-#define PPLUS_SMC_RAM_B_SIZE_REG_OFF		0x11
-#define PPLUS_SMC_RAM_C_SIZE_REG_OFF		0x12
-#define PPLUS_SMC_RAM_D_SIZE_REG_OFF		0x13
-#define PPLUS_SMC_RAM_E_SIZE_REG_OFF		0xc0	/* HAWK Only */
-#define PPLUS_SMC_RAM_F_SIZE_REG_OFF		0xc1	/* HAWK Only */
-#define PPLUS_SMC_RAM_G_SIZE_REG_OFF		0xc2	/* HAWK Only */
-#define PPLUS_SMC_RAM_H_SIZE_REG_OFF		0xc3	/* HAWK Only */
-
-#define	PPLUS_FALCON_SMC_REG_COUNT		4
-#define	PPLUS_HAWK_SMC_REG_COUNT		8
-
-
-
-int pplus_init(struct pci_controller *hose,
-		 uint ppc_reg_base,
-		 ulong processor_pci_mem_start,
-		 ulong processor_pci_mem_end,
-		 ulong processor_pci_io_start,
-		 ulong processor_pci_io_end,
-		 ulong processor_mpic_base);
-
-unsigned long pplus_get_mem_size(uint smc_base);
-
-int pplus_mpic_init(unsigned int pci_mem_offset);
-
-#endif /* __ASMPPC_PPLUS_H */
diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h
index 98e82863a72b..a9422c20d311 100644
--- a/include/asm-ppc/serial.h
+++ b/include/asm-ppc/serial.h
@@ -27,7 +27,7 @@
 #elif defined(CONFIG_SANDPOINT)
 #include <platforms/sandpoint.h>
 #elif defined(CONFIG_SPRUCE)
-#include <platforms/spruce_serial.h>
+#include <platforms/spruce.h>
 #elif defined(CONFIG_4xx)
 #include <asm/ibm4xx.h>
 #else
diff --git a/include/asm-ppc/todc.h b/include/asm-ppc/todc.h
index 5a9e53c21eba..30abf319b425 100644
--- a/include/asm-ppc/todc.h
+++ b/include/asm-ppc/todc.h
@@ -29,9 +29,9 @@ typedef struct {
 	 * Following are the addresses of the AS0, AS1, and DATA registers
 	 * of these chips.  Note that these are board-specific.
 	 */
-	unsigned char *nvram_as0;
-	unsigned char *nvram_as1;
-	unsigned char *nvram_data;
+	unsigned int nvram_as0;
+	unsigned int nvram_as1;
+	unsigned int nvram_data;
 
 	/*
 	 * Define bits to stop external set of regs from changing so
@@ -46,6 +46,9 @@ typedef struct {
 	 */
 	int as0_bits;
 
+	int nvram_size;	/* Size of NVRAM on chip */
+	int sw_flags;	/* Software control flags */
+
 	/* Following are the register offsets for the particular chip */
 	int year;
 	int month;
@@ -64,6 +67,14 @@ typedef struct {
 	int alarm_seconds;
 	int century;
 	int flags;
+
+	/*
+	 * Some RTC chips have their NVRAM buried behind a addr/data pair of
+	 * regs on the first level/clock registers.  The following fields
+	 * are the addresses for those addr/data regs.
+	 */
+	int nvram_addr_reg;
+	int nvram_data_reg;
 } todc_info_t;
 
 /*
@@ -86,7 +97,8 @@ typedef struct {
 #define TODC_TYPE_DS1643		9	/* Dallas DS1643 RTC */
 #define TODC_TYPE_PC97307		10	/* PC97307 internal RTC */
 #define TODC_TYPE_DS1557		11	/* Dallas DS1557 RTC */
-#define	TODC_TYPE_MC146818		100	/* Leave room for more m48txx's */
+#define TODC_TYPE_DS17285		12	/* Dallas DS17285 RTC */
+#define	TODC_TYPE_MC146818		100	/* Leave room for m48txx's */
 
 /*
  * Bit to clear/set to enable reads/writes to the chip
@@ -98,9 +110,18 @@ typedef struct {
 #define	TODC_DS1501_CNTL_B_TE		0x80
 
 /*
+ * Define flag bits used by todc routines.
+ */
+#define	TODC_FLAG_2_LEVEL_NVRAM		0x00000001
+
+/*
  * Define the values for the various RTC's that should to into the todc_info
  * table.
+ * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
+ * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
  */
+#define	TODC_TYPE_MK48T35_NVRAM_SIZE		0x7ff8
+#define	TODC_TYPE_MK48T35_SW_FLAGS		0
 #define	TODC_TYPE_MK48T35_YEAR			0x7fff
 #define	TODC_TYPE_MK48T35_MONTH			0x7ffe
 #define	TODC_TYPE_MK48T35_DOM			0x7ffd	/* Day of Month */
@@ -118,7 +139,11 @@ typedef struct {
 #define	TODC_TYPE_MK48T35_ALARM_SECONDS		0x0000
 #define	TODC_TYPE_MK48T35_CENTURY		0x0000
 #define	TODC_TYPE_MK48T35_FLAGS			0x0000
+#define	TODC_TYPE_MK48T35_NVRAM_ADDR_REG	0
+#define	TODC_TYPE_MK48T35_NVRAM_DATA_REG	0
 
+#define	TODC_TYPE_MK48T37_NVRAM_SIZE		0x7ff0
+#define	TODC_TYPE_MK48T37_SW_FLAGS		0
 #define	TODC_TYPE_MK48T37_YEAR			0x7fff
 #define	TODC_TYPE_MK48T37_MONTH			0x7ffe
 #define	TODC_TYPE_MK48T37_DOM			0x7ffd	/* Day of Month */
@@ -136,7 +161,11 @@ typedef struct {
 #define	TODC_TYPE_MK48T37_ALARM_SECONDS		0x7ff2
 #define	TODC_TYPE_MK48T37_CENTURY		0x7ff1
 #define	TODC_TYPE_MK48T37_FLAGS			0x7ff0
+#define	TODC_TYPE_MK48T37_NVRAM_ADDR_REG	0
+#define	TODC_TYPE_MK48T37_NVRAM_DATA_REG	0
 
+#define	TODC_TYPE_MK48T59_NVRAM_SIZE		0x1ff0
+#define	TODC_TYPE_MK48T59_SW_FLAGS		0
 #define	TODC_TYPE_MK48T59_YEAR			0x1fff
 #define	TODC_TYPE_MK48T59_MONTH			0x1ffe
 #define	TODC_TYPE_MK48T59_DOM			0x1ffd	/* Day of Month */
@@ -154,25 +183,33 @@ typedef struct {
 #define	TODC_TYPE_MK48T59_ALARM_SECONDS		0x1fff
 #define	TODC_TYPE_MK48T59_CENTURY		0x1fff
 #define	TODC_TYPE_MK48T59_FLAGS			0x1fff
+#define	TODC_TYPE_MK48T59_NVRAM_ADDR_REG	0
+#define	TODC_TYPE_MK48T59_NVRAM_DATA_REG	0
 
-#define	TODC_TYPE_DS1501_YEAR			0x06
-#define	TODC_TYPE_DS1501_MONTH			0x05
-#define	TODC_TYPE_DS1501_DOM			0x04	/* Day of Month */
-#define	TODC_TYPE_DS1501_DOW			0x03	/* Day of Week */
-#define	TODC_TYPE_DS1501_HOURS			0x02
-#define	TODC_TYPE_DS1501_MINUTES		0x01
-#define	TODC_TYPE_DS1501_SECONDS		0x00
-#define	TODC_TYPE_DS1501_CNTL_B			0x0f
-#define	TODC_TYPE_DS1501_CNTL_A			0x0f
-#define	TODC_TYPE_DS1501_WATCHDOG		0xff
-#define	TODC_TYPE_DS1501_INTERRUPTS		0xff
-#define	TODC_TYPE_DS1501_ALARM_DATE		0x0b
-#define	TODC_TYPE_DS1501_ALARM_HOUR		0x0a
-#define	TODC_TYPE_DS1501_ALARM_MINUTES		0x09
-#define	TODC_TYPE_DS1501_ALARM_SECONDS		0x08
-#define	TODC_TYPE_DS1501_CENTURY		0x07
-#define	TODC_TYPE_DS1501_FLAGS			0xff
+#define	TODC_TYPE_DS1501_NVRAM_SIZE	0x100
+#define	TODC_TYPE_DS1501_SW_FLAGS	TODC_FLAG_2_LEVEL_NVRAM
+#define	TODC_TYPE_DS1501_YEAR		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
+#define	TODC_TYPE_DS1501_MONTH		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
+#define	TODC_TYPE_DS1501_DOM		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
+#define	TODC_TYPE_DS1501_DOW		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
+#define	TODC_TYPE_DS1501_HOURS		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
+#define	TODC_TYPE_DS1501_MINUTES	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
+#define	TODC_TYPE_DS1501_SECONDS	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
+#define	TODC_TYPE_DS1501_CNTL_B		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
+#define	TODC_TYPE_DS1501_CNTL_A		(TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
+#define	TODC_TYPE_DS1501_WATCHDOG	(TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define	TODC_TYPE_DS1501_INTERRUPTS	(TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define	TODC_TYPE_DS1501_ALARM_DATE	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
+#define	TODC_TYPE_DS1501_ALARM_HOUR	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
+#define	TODC_TYPE_DS1501_ALARM_MINUTES	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
+#define	TODC_TYPE_DS1501_ALARM_SECONDS	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
+#define	TODC_TYPE_DS1501_CENTURY	(TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
+#define	TODC_TYPE_DS1501_FLAGS		(TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define	TODC_TYPE_DS1501_NVRAM_ADDR_REG	0x10
+#define	TODC_TYPE_DS1501_NVRAM_DATA_REG	0x13
 
+#define	TODC_TYPE_DS1557_NVRAM_SIZE		0x7fff0
+#define	TODC_TYPE_DS1557_SW_FLAGS		0
 #define	TODC_TYPE_DS1557_YEAR			0x7ffff
 #define	TODC_TYPE_DS1557_MONTH			0x7fffe
 #define	TODC_TYPE_DS1557_DOM			0x7fffd	/* Day of Month */
@@ -190,7 +227,11 @@ typedef struct {
 #define	TODC_TYPE_DS1557_ALARM_SECONDS		0x7fff2
 #define	TODC_TYPE_DS1557_CENTURY		0x7fff8
 #define	TODC_TYPE_DS1557_FLAGS			0x7fff0
+#define	TODC_TYPE_DS1557_NVRAM_ADDR_REG		0
+#define	TODC_TYPE_DS1557_NVRAM_DATA_REG		0
 
+#define	TODC_TYPE_DS1643_NVRAM_SIZE		0x1ff8
+#define	TODC_TYPE_DS1643_SW_FLAGS		0
 #define	TODC_TYPE_DS1643_YEAR			0x1fff
 #define	TODC_TYPE_DS1643_MONTH			0x1ffe
 #define	TODC_TYPE_DS1643_DOM			0x1ffd	/* Day of Month */
@@ -208,7 +249,11 @@ typedef struct {
 #define	TODC_TYPE_DS1643_ALARM_SECONDS		0x1fff
 #define	TODC_TYPE_DS1643_CENTURY		0x1ff8
 #define	TODC_TYPE_DS1643_FLAGS			0x1fff
+#define	TODC_TYPE_DS1643_NVRAM_ADDR_REG		0
+#define	TODC_TYPE_DS1643_NVRAM_DATA_REG		0
 
+#define	TODC_TYPE_DS1693_NVRAM_SIZE		0 /* Not handled yet */
+#define	TODC_TYPE_DS1693_SW_FLAGS		0
 #define	TODC_TYPE_DS1693_YEAR			0x09
 #define	TODC_TYPE_DS1693_MONTH			0x08
 #define	TODC_TYPE_DS1693_DOM			0x07	/* Day of Month */
@@ -226,7 +271,11 @@ typedef struct {
 #define	TODC_TYPE_DS1693_ALARM_SECONDS		0x01
 #define	TODC_TYPE_DS1693_CENTURY		0x48
 #define	TODC_TYPE_DS1693_FLAGS			0xff
+#define	TODC_TYPE_DS1693_NVRAM_ADDR_REG		0
+#define	TODC_TYPE_DS1693_NVRAM_DATA_REG		0
 
+#define	TODC_TYPE_DS1743_NVRAM_SIZE		0x1ff8
+#define	TODC_TYPE_DS1743_SW_FLAGS		0
 #define	TODC_TYPE_DS1743_YEAR			0x1fff
 #define	TODC_TYPE_DS1743_MONTH			0x1ffe
 #define	TODC_TYPE_DS1743_DOM			0x1ffd	/* Day of Month */
@@ -244,7 +293,11 @@ typedef struct {
 #define	TODC_TYPE_DS1743_ALARM_SECONDS		0x1fff
 #define	TODC_TYPE_DS1743_CENTURY		0x1ff8
 #define	TODC_TYPE_DS1743_FLAGS			0x1fff
+#define	TODC_TYPE_DS1743_NVRAM_ADDR_REG		0
+#define	TODC_TYPE_DS1743_NVRAM_DATA_REG		0
 
+#define	TODC_TYPE_DS1746_NVRAM_SIZE		0x1fff8
+#define	TODC_TYPE_DS1746_SW_FLAGS		0
 #define	TODC_TYPE_DS1746_YEAR			0x1ffff
 #define	TODC_TYPE_DS1746_MONTH			0x1fffe
 #define	TODC_TYPE_DS1746_DOM			0x1fffd	/* Day of Month */
@@ -262,16 +315,20 @@ typedef struct {
 #define	TODC_TYPE_DS1746_ALARM_SECONDS		0x00000
 #define	TODC_TYPE_DS1746_CENTURY		0x00000
 #define	TODC_TYPE_DS1746_FLAGS			0x00000
+#define	TODC_TYPE_DS1746_NVRAM_ADDR_REG		0
+#define	TODC_TYPE_DS1746_NVRAM_DATA_REG		0
 
-#define	TODC_TYPE_DS1747_YEAR			0x1ffff
-#define	TODC_TYPE_DS1747_MONTH			0x1fffe
-#define	TODC_TYPE_DS1747_DOM			0x1fffd	/* Day of Month */
-#define	TODC_TYPE_DS1747_DOW			0x1fffc	/* Day of Week */
-#define	TODC_TYPE_DS1747_HOURS			0x1fffb
-#define	TODC_TYPE_DS1747_MINUTES		0x1fffa
-#define	TODC_TYPE_DS1747_SECONDS		0x1fff9
-#define	TODC_TYPE_DS1747_CNTL_B			0x1fff9
-#define	TODC_TYPE_DS1747_CNTL_A			0x1fff8	/* control_a R/W regs */
+#define	TODC_TYPE_DS1747_NVRAM_SIZE		0x7fff8
+#define	TODC_TYPE_DS1747_SW_FLAGS		0
+#define	TODC_TYPE_DS1747_YEAR			0x7ffff
+#define	TODC_TYPE_DS1747_MONTH			0x7fffe
+#define	TODC_TYPE_DS1747_DOM			0x7fffd	/* Day of Month */
+#define	TODC_TYPE_DS1747_DOW			0x7fffc	/* Day of Week */
+#define	TODC_TYPE_DS1747_HOURS			0x7fffb
+#define	TODC_TYPE_DS1747_MINUTES		0x7fffa
+#define	TODC_TYPE_DS1747_SECONDS		0x7fff9
+#define	TODC_TYPE_DS1747_CNTL_B			0x7fff9
+#define	TODC_TYPE_DS1747_CNTL_A			0x7fff8	/* control_a R/W regs */
 #define	TODC_TYPE_DS1747_WATCHDOG		0x00000
 #define	TODC_TYPE_DS1747_INTERRUPTS		0x00000
 #define	TODC_TYPE_DS1747_ALARM_DATE		0x00000
@@ -280,7 +337,35 @@ typedef struct {
 #define	TODC_TYPE_DS1747_ALARM_SECONDS		0x00000
 #define	TODC_TYPE_DS1747_CENTURY		0x00000
 #define	TODC_TYPE_DS1747_FLAGS			0x00000
+#define	TODC_TYPE_DS1747_NVRAM_ADDR_REG		0
+#define	TODC_TYPE_DS1747_NVRAM_DATA_REG		0
 
+#define TODC_TYPE_DS17285_NVRAM_SIZE		(0x1000-0x80)    /* 4Kx8 NVRAM (minus RTC regs) */
+#define TODC_TYPE_DS17285_SW_FLAGS		TODC_FLAG_2_LEVEL_NVRAM
+#define TODC_TYPE_DS17285_SECONDS		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
+#define TODC_TYPE_DS17285_ALARM_SECONDS		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
+#define TODC_TYPE_DS17285_MINUTES		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
+#define TODC_TYPE_DS17285_ALARM_MINUTES		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
+#define TODC_TYPE_DS17285_HOURS			(TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
+#define TODC_TYPE_DS17285_ALARM_HOUR		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
+#define TODC_TYPE_DS17285_DOW			(TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
+#define TODC_TYPE_DS17285_DOM			(TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
+#define TODC_TYPE_DS17285_MONTH			(TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
+#define TODC_TYPE_DS17285_YEAR			(TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
+#define TODC_TYPE_DS17285_CNTL_A		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
+#define TODC_TYPE_DS17285_CNTL_B		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
+#define TODC_TYPE_DS17285_CNTL_C		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
+#define TODC_TYPE_DS17285_CNTL_D		(TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
+#define TODC_TYPE_DS17285_WATCHDOG		0
+#define TODC_TYPE_DS17285_INTERRUPTS		0
+#define TODC_TYPE_DS17285_ALARM_DATE		0
+#define TODC_TYPE_DS17285_CENTURY		0
+#define TODC_TYPE_DS17285_FLAGS			0
+#define TODC_TYPE_DS17285_NVRAM_ADDR_REG	0x50
+#define TODC_TYPE_DS17285_NVRAM_DATA_REG	0x53
+ 
+#define	TODC_TYPE_MC146818_NVRAM_SIZE		0	/* XXXX */
+#define	TODC_TYPE_MC146818_SW_FLAGS		0
 #define	TODC_TYPE_MC146818_YEAR			0x09
 #define	TODC_TYPE_MC146818_MONTH		0x08
 #define	TODC_TYPE_MC146818_DOM			0x07	/* Day of Month */
@@ -298,7 +383,11 @@ typedef struct {
 #define	TODC_TYPE_MC146818_ALARM_SECONDS	0x01
 #define	TODC_TYPE_MC146818_CENTURY		0xff
 #define	TODC_TYPE_MC146818_FLAGS		0xff
-
+#define	TODC_TYPE_MC146818_NVRAM_ADDR_REG	0
+#define	TODC_TYPE_MC146818_NVRAM_DATA_REG	0
+  
+#define	TODC_TYPE_PC97307_NVRAM_SIZE		0	/* No NVRAM? */
+#define	TODC_TYPE_PC97307_SW_FLAGS		0
 #define	TODC_TYPE_PC97307_YEAR			0x09
 #define	TODC_TYPE_PC97307_MONTH			0x08
 #define	TODC_TYPE_PC97307_DOM			0x07	/* Day of Month */
@@ -316,6 +405,8 @@ typedef struct {
 #define	TODC_TYPE_PC97307_ALARM_SECONDS		0x01
 #define	TODC_TYPE_PC97307_CENTURY		0xff
 #define	TODC_TYPE_PC97307_FLAGS			0xff
+#define	TODC_TYPE_PC97307_NVRAM_ADDR_REG	0
+#define	TODC_TYPE_PC97307_NVRAM_DATA_REG	0
 
 /*
  * Define macros to allocate and init the todc_info_t table that will
@@ -328,29 +419,35 @@ typedef struct {
 #define	TODC_INIT(clock_type, as0, as1, data, bits) {			\
 	todc_info->rtc_type = clock_type;				\
 									\
-	todc_info->nvram_as0  = (unsigned char *)(as0);			\
-	todc_info->nvram_as1  = (unsigned char *)(as1);			\
-	todc_info->nvram_data = (unsigned char *)(data);			\
+	todc_info->nvram_as0  = (unsigned int)(as0);			\
+	todc_info->nvram_as1  = (unsigned int)(as1);			\
+	todc_info->nvram_data = (unsigned int)(data);			\
 									\
 	todc_info->as0_bits = (bits);					\
 									\
-	todc_info->year          = clock_type ##_YEAR;			\
-	todc_info->month         = clock_type ##_MONTH;			\
-	todc_info->day_of_month  = clock_type ##_DOM;			\
-	todc_info->day_of_week   = clock_type ##_DOW;			\
-	todc_info->hours         = clock_type ##_HOURS;			\
-	todc_info->minutes       = clock_type ##_MINUTES;		\
-	todc_info->seconds       = clock_type ##_SECONDS;		\
-	todc_info->control_b     = clock_type ##_CNTL_B;		\
-	todc_info->control_a     = clock_type ##_CNTL_A;		\
-	todc_info->watchdog      = clock_type ##_WATCHDOG;		\
-	todc_info->interrupts    = clock_type ##_INTERRUPTS;		\
-	todc_info->alarm_date    = clock_type ##_ALARM_DATE;		\
-	todc_info->alarm_hour    = clock_type ##_ALARM_HOUR;		\
-	todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES;		\
-	todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS;		\
-	todc_info->century       = clock_type ##_CENTURY;		\
-	todc_info->flags         = clock_type ##_FLAGS;			\
+	todc_info->nvram_size     = clock_type ##_NVRAM_SIZE;		\
+	todc_info->sw_flags       = clock_type ##_SW_FLAGS;		\
+									\
+	todc_info->year           = clock_type ##_YEAR;			\
+	todc_info->month          = clock_type ##_MONTH;		\
+	todc_info->day_of_month   = clock_type ##_DOM;			\
+	todc_info->day_of_week    = clock_type ##_DOW;			\
+	todc_info->hours          = clock_type ##_HOURS;		\
+	todc_info->minutes        = clock_type ##_MINUTES;		\
+	todc_info->seconds        = clock_type ##_SECONDS;		\
+	todc_info->control_b      = clock_type ##_CNTL_B;		\
+	todc_info->control_a      = clock_type ##_CNTL_A;		\
+	todc_info->watchdog       = clock_type ##_WATCHDOG;		\
+	todc_info->interrupts     = clock_type ##_INTERRUPTS;		\
+	todc_info->alarm_date     = clock_type ##_ALARM_DATE;		\
+	todc_info->alarm_hour     = clock_type ##_ALARM_HOUR;		\
+	todc_info->alarm_minutes  = clock_type ##_ALARM_MINUTES;	\
+	todc_info->alarm_seconds  = clock_type ##_ALARM_SECONDS;	\
+	todc_info->century        = clock_type ##_CENTURY;		\
+	todc_info->flags          = clock_type ##_FLAGS;		\
+									\
+	todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG;	\
+	todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG;	\
 }
 
 extern todc_info_t *todc_info;