diff options
| author | Paul Mackerras <paulus@samba.org> | 2002-12-23 19:47:41 +1100 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2002-12-23 19:47:41 +1100 |
| commit | aeb24f2986ff9471fd062e50815466b0c6415b52 (patch) | |
| tree | f1015dc5aeeff1df6f7540b590f8084de0c6fa42 /include | |
| parent | c261322433a7e8f2f0b0c2d1ff8af089e39d5597 (diff) | |
| parent | 4e375211e20eff9ad5382e3bfe2e7408907fd971 (diff) | |
Merge samba.org:/home/paulus/kernel/linux-2.5
into samba.org:/home/paulus/kernel/for-linus-ppc
Diffstat (limited to 'include')
154 files changed, 4141 insertions, 1764 deletions
diff --git a/include/asm-alpha/dma-mapping.h b/include/asm-alpha/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-alpha/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-arm/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-cris/dma-mapping.h b/include/asm-cris/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-cris/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-generic/dma-mapping.h b/include/asm-generic/dma-mapping.h new file mode 100644 index 000000000000..f1aa41ee93d9 --- /dev/null +++ b/include/asm-generic/dma-mapping.h @@ -0,0 +1,154 @@ +/* Copyright (C) 2002 by James.Bottomley@HansenPartnership.com + * + * Implements the generic device dma API via the existing pci_ one + * for unconverted architectures + */ + +#ifndef _ASM_GENERIC_DMA_MAPPING_H +#define _ASM_GENERIC_DMA_MAPPING_H + +/* we implement the API below in terms of the existing PCI one, + * so include it */ +#include <linux/pci.h> + +static inline int +dma_supported(struct device *dev, u64 mask) +{ + BUG_ON(dev->bus != &pci_bus_type); + + return pci_dma_supported(to_pci_dev(dev), mask); +} + +static inline int +dma_set_mask(struct device *dev, u64 dma_mask) +{ + BUG_ON(dev->bus != &pci_bus_type); + + return pci_set_dma_mask(to_pci_dev(dev), dma_mask); +} + +static inline void * +dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle) +{ + BUG_ON(dev->bus != &pci_bus_type); + + return pci_alloc_consistent(to_pci_dev(dev), size, dma_handle); +} + +static inline void +dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t dma_handle) +{ + BUG_ON(dev->bus != &pci_bus_type); + + pci_free_consistent(to_pci_dev(dev), size, cpu_addr, dma_handle); +} + +static inline dma_addr_t +dma_map_single(struct device *dev, void *cpu_addr, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(dev->bus != &pci_bus_type); + + return pci_map_single(to_pci_dev(dev), cpu_addr, size, (int)direction); +} + +static inline void +dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(dev->bus != &pci_bus_type); + + pci_unmap_single(to_pci_dev(dev), dma_addr, size, (int)direction); +} + +static inline dma_addr_t +dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(dev->bus != &pci_bus_type); + + return pci_map_page(to_pci_dev(dev), page, offset, size, (int)direction); +} + +static inline void +dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(dev->bus != &pci_bus_type); + + pci_unmap_page(to_pci_dev(dev), dma_address, size, (int)direction); +} + +static inline int +dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction direction) +{ + BUG_ON(dev->bus != &pci_bus_type); + + return pci_map_sg(to_pci_dev(dev), sg, nents, (int)direction); +} + +static inline void +dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, + enum dma_data_direction direction) +{ + BUG_ON(dev->bus != &pci_bus_type); + + pci_unmap_sg(to_pci_dev(dev), sg, nhwentries, (int)direction); +} + +static inline void +dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(dev->bus != &pci_bus_type); + + pci_dma_sync_single(to_pci_dev(dev), dma_handle, size, (int)direction); +} + +static inline void +dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction) +{ + BUG_ON(dev->bus != &pci_bus_type); + + pci_dma_sync_sg(to_pci_dev(dev), sg, nelems, (int)direction); +} + +/* Now for the API extensions over the pci_ one */ + +#define dma_alloc_noncoherent(d, s, h) dma_alloc_coherent(d, s, h) +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) +#define dma_is_consistent(d) (1) + +static inline int +dma_get_cache_alignment(void) +{ + /* no easy way to get cache size on all processors, so return + * the maximum possible, to be safe */ + return (1 << L1_CACHE_SHIFT_MAX); +} + +static inline void +dma_sync_single_range(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + /* just sync everything, that's all the pci API can do */ + dma_sync_single(dev, dma_handle, offset+size, direction); +} + +static inline void +dma_cache_sync(void *vaddr, size_t size, + enum dma_data_direction direction) +{ + /* could define this in terms of the dma_cache ... operations, + * but if you get this on a platform, you should convert the platform + * to using the generic device DMA API */ + BUG(); +} + +#endif + diff --git a/include/asm-i386/cpufeature.h b/include/asm-i386/cpufeature.h index f0becf88e4a0..92ff7f79dee4 100644 --- a/include/asm-i386/cpufeature.h +++ b/include/asm-i386/cpufeature.h @@ -7,6 +7,8 @@ #ifndef __ASM_I386_CPUFEATURE_H #define __ASM_I386_CPUFEATURE_H +#include <linux/bitops.h> + #define NCAPINTS 4 /* Currently we have 4 32-bit words worth of info */ /* Intel-defined CPU features, CPUID level 0x00000001, word 0 */ @@ -74,6 +76,7 @@ #define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE) #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE) #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) +#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP) #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR) #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX) #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) diff --git a/include/asm-i386/dma-mapping.h b/include/asm-i386/dma-mapping.h new file mode 100644 index 000000000000..8599f2ced8ff --- /dev/null +++ b/include/asm-i386/dma-mapping.h @@ -0,0 +1,137 @@ +#ifndef _ASM_I386_DMA_MAPPING_H +#define _ASM_I386_DMA_MAPPING_H + +#include <asm/cache.h> + +#define dma_alloc_noncoherent(d, s, h) dma_alloc_coherent(d, s, h) +#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h) + +void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle); + +void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle); + +static inline dma_addr_t +dma_map_single(struct device *dev, void *ptr, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); + flush_write_buffers(); + return virt_to_phys(ptr); +} + +static inline void +dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); +} + +static inline int +dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction direction) +{ + int i; + + BUG_ON(direction == DMA_NONE); + + for (i = 0; i < nents; i++ ) { + BUG_ON(!sg[i].page); + + sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset; + } + + flush_write_buffers(); + return nents; +} + +static inline dma_addr_t +dma_map_page(struct device *dev, struct page *page, unsigned long offset, + size_t size, enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); + return (dma_addr_t)(page_to_pfn(page)) * PAGE_SIZE + offset; +} + +static inline void +dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); +} + + +static inline void +dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries, + enum dma_data_direction direction) +{ + BUG_ON(direction == DMA_NONE); +} + +static inline void +dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size, + enum dma_data_direction direction) +{ + flush_write_buffers(); +} + +static inline void +dma_sync_single_range(struct device *dev, dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction direction) +{ + flush_write_buffers(); +} + + +static inline void +dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems, + enum dma_data_direction direction) +{ + flush_write_buffers(); +} + +static inline int +dma_supported(struct device *dev, u64 mask) +{ + /* + * we fall back to GFP_DMA when the mask isn't all 1s, + * so we can't guarantee allocations that must be + * within a tighter range than GFP_DMA.. + */ + if(mask < 0x00ffffff) + return 0; + + return 1; +} + +static inline int +dma_set_mask(struct device *dev, u64 mask) +{ + if(!dev->dma_mask || !dma_supported(dev, mask)) + return -EIO; + + *dev->dma_mask = mask; + + return 0; +} + +static inline int +dma_get_cache_alignment(void) +{ + /* no easy way to get cache size on all x86, so return the + * maximum possible, to be safe */ + return (1 << L1_CACHE_SHIFT_MAX); +} + +#define dma_is_consistent(d) (1) + +static inline void +dma_cache_sync(void *vaddr, size_t size, + enum dma_data_direction direction) +{ + flush_write_buffers(); +} + +#endif diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h index f8819948d629..6e7572e46d1f 100644 --- a/include/asm-i386/msr.h +++ b/include/asm-i386/msr.h @@ -53,6 +53,10 @@ #define MSR_IA32_BBL_CR_CTL 0x119 +#define MSR_IA32_SYSENTER_CS 0x174 +#define MSR_IA32_SYSENTER_ESP 0x175 +#define MSR_IA32_SYSENTER_EIP 0x176 + #define MSR_IA32_MCG_CAP 0x179 #define MSR_IA32_MCG_STATUS 0x17a #define MSR_IA32_MCG_CTL 0x17b diff --git a/include/asm-i386/mtrr.h b/include/asm-i386/mtrr.h index f2727e61fe63..46c5561cb643 100644 --- a/include/asm-i386/mtrr.h +++ b/include/asm-i386/mtrr.h @@ -31,7 +31,7 @@ struct mtrr_sentry { unsigned long base; /* Base address */ - unsigned long size; /* Size of region */ + unsigned int size; /* Size of region */ unsigned int type; /* Type of region */ }; @@ -39,7 +39,7 @@ struct mtrr_gentry { unsigned int regnum; /* Register number */ unsigned long base; /* Base address */ - unsigned long size; /* Size of region */ + unsigned int size; /* Size of region */ unsigned int type; /* Type of region */ }; @@ -65,21 +65,10 @@ struct mtrr_gentry #define MTRR_TYPE_WRBACK 6 #define MTRR_NUM_TYPES 7 -#ifdef MTRR_NEED_STRINGS -static char *mtrr_strings[MTRR_NUM_TYPES] = -{ - "uncachable", /* 0 */ - "write-combining", /* 1 */ - "?", /* 2 */ - "?", /* 3 */ - "write-through", /* 4 */ - "write-protect", /* 5 */ - "write-back", /* 6 */ -}; -#endif - #ifdef __KERNEL__ +extern char *mtrr_strings[]; + /* The following functions are for use by other drivers */ # ifdef CONFIG_MTRR extern int mtrr_add (unsigned long base, unsigned long size, diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h index 3fe171683048..48a0dc93ffdc 100644 --- a/include/asm-i386/pci.h +++ b/include/asm-i386/pci.h @@ -6,6 +6,9 @@ #ifdef __KERNEL__ #include <linux/mm.h> /* for struct page */ +/* we support the new DMA API, but still provide the old one */ +#define PCI_NEW_DMA_COMPAT_API 1 + /* Can be used to override the logic in pci_scan_bus for skipping already-configured bus numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the loader */ @@ -46,78 +49,6 @@ struct pci_dev; */ #define PCI_DMA_BUS_IS_PHYS (1) -/* Allocate and map kernel buffer using consistent mode DMA for a device. - * hwdev should be valid struct pci_dev pointer for PCI devices, - * NULL for PCI-like buses (ISA, EISA). - * Returns non-NULL cpu-view pointer to the buffer if successful and - * sets *dma_addrp to the pci side dma address as well, else *dma_addrp - * is undefined. - */ -extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, - dma_addr_t *dma_handle); - -/* Free and unmap a consistent DMA buffer. - * cpu_addr is what was returned from pci_alloc_consistent, - * size must be the same as what as passed into pci_alloc_consistent, - * and likewise dma_addr must be the same as what *dma_addrp was set to. - * - * References to the memory and mappings associated with cpu_addr/dma_addr - * past this call are illegal. - */ -extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, - void *vaddr, dma_addr_t dma_handle); - -/* Map a single buffer of the indicated size for DMA in streaming mode. - * The 32-bit bus address to use is returned. - * - * Once the device is given the dma address, the device owns this memory - * until either pci_unmap_single or pci_dma_sync_single is performed. - */ -static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, - size_t size, int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); - flush_write_buffers(); - return virt_to_phys(ptr); -} - -/* Unmap a single streaming mode DMA translation. The dma_addr and size - * must match what was provided for in a previous pci_map_single call. All - * other usages are undefined. - * - * After this call, reads by the cpu to the buffer are guarenteed to see - * whatever the device wrote there. - */ -static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, - size_t size, int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); - /* Nothing to do */ -} - -/* - * pci_{map,unmap}_single_page maps a kernel page to a dma_addr_t. identical - * to pci_map_single, but takes a struct page instead of a virtual address - */ -static inline dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page, - unsigned long offset, size_t size, int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); - - return (dma_addr_t)(page_to_pfn(page)) * PAGE_SIZE + offset; -} - -static inline void pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address, - size_t size, int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); - /* Nothing to do */ -} - /* pci_unmap_{page,single} is a nop so... */ #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) #define DECLARE_PCI_UNMAP_LEN(LEN_NAME) @@ -126,103 +57,6 @@ static inline void pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address, #define pci_unmap_len(PTR, LEN_NAME) (0) #define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) -/* Map a set of buffers described by scatterlist in streaming - * mode for DMA. This is the scather-gather version of the - * above pci_map_single interface. Here the scatter gather list - * elements are each tagged with the appropriate dma address - * and length. They are obtained via sg_dma_{address,length}(SG). - * - * NOTE: An implementation may be able to use a smaller number of - * DMA address/length pairs than there are SG table elements. - * (for example via virtual mapping capabilities) - * The routine returns the number of addr/length pairs actually - * used, at most nents. - * - * Device ownership issues as mentioned above for pci_map_single are - * the same here. - */ -static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, - int nents, int direction) -{ - int i; - - if (direction == PCI_DMA_NONE) - BUG(); - - for (i = 0; i < nents; i++ ) { - if (!sg[i].page) - BUG(); - - sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset; - } - - flush_write_buffers(); - return nents; -} - -/* Unmap a set of streaming mode DMA translations. - * Again, cpu read rules concerning calls here are the same as for - * pci_unmap_single() above. - */ -static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, - int nents, int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); - /* Nothing to do */ -} - -/* Make physical memory consistent for a single - * streaming mode DMA translation after a transfer. - * - * If you perform a pci_map_single() but wish to interrogate the - * buffer using the cpu, yet do not wish to teardown the PCI dma - * mapping, you must call this function before doing so. At the - * next point you give the PCI dma address back to the card, the - * device again owns the buffer. - */ -static inline void pci_dma_sync_single(struct pci_dev *hwdev, - dma_addr_t dma_handle, - size_t size, int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); - flush_write_buffers(); -} - -/* Make physical memory consistent for a set of streaming - * mode DMA translations after a transfer. - * - * The same as pci_dma_sync_single but for a scatter-gather list, - * same rules and usage. - */ -static inline void pci_dma_sync_sg(struct pci_dev *hwdev, - struct scatterlist *sg, - int nelems, int direction) -{ - if (direction == PCI_DMA_NONE) - BUG(); - flush_write_buffers(); -} - -/* Return whether the given PCI device DMA address mask can - * be supported properly. For example, if your device can - * only drive the low 24-bits during PCI bus mastering, then - * you would pass 0x00ffffff as the mask to this function. - */ -static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if(mask < 0x00ffffff) - return 0; - - return 1; -} - /* This is always fine. */ #define pci_dac_dma_supported(pci_dev, mask) (1) diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index ec17e06a6df0..ac467d123706 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h @@ -14,6 +14,7 @@ #include <asm/types.h> #include <asm/sigcontext.h> #include <asm/cpufeature.h> +#include <asm/msr.h> #include <linux/cache.h> #include <linux/config.h> #include <linux/threads.h> @@ -416,6 +417,21 @@ struct thread_struct { {~0, } /* ioperm */ \ } +static inline void load_esp0(struct tss_struct *tss, unsigned long esp0) +{ + tss->esp0 = esp0; + if (cpu_has_sep) { + wrmsr(MSR_IA32_SYSENTER_CS, __KERNEL_CS, 0); + wrmsr(MSR_IA32_SYSENTER_ESP, esp0, 0); + } +} + +static inline void disable_sysenter(void) +{ + if (cpu_has_sep) + wrmsr(MSR_IA32_SYSENTER_CS, 0, 0); +} + #define start_thread(regs, new_eip, new_esp) do { \ __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \ set_fs(USER_DS); \ diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h index 90a21fae9a74..bbd4e9f89369 100644 --- a/include/asm-ia64/acpi.h +++ b/include/asm-ia64/acpi.h @@ -56,7 +56,7 @@ #define ACPI_ACQUIRE_GLOBAL_LOCK(GLptr, Acq) \ do { \ - __asm__ volatile ("1: ld4 r29=%1\n" \ + __asm__ volatile ("1: ld4 r29=[%1]\n" \ ";;\n" \ "mov ar.ccv=r29\n" \ "mov r2=r29\n" \ @@ -68,7 +68,7 @@ ";;\n" \ "add r29=r29,r30\n" \ ";;\n" \ - "cmpxchg4.acq r30=%1,r29,ar.ccv\n" \ + "cmpxchg4.acq r30=[%1],r29,ar.ccv\n" \ ";;\n" \ "cmp.eq p6,p7=r2,r30\n" \ "(p7) br.dpnt.few 1b\n" \ @@ -76,24 +76,24 @@ ";;\n" \ "(p8) mov %0=-1\n" \ "(p9) mov %0=r0\n" \ - :"=r"(Acq):"m"(GLptr):"r2","r29","r30","memory"); \ + :"=r"(Acq):"r"(GLptr):"r2","r29","r30","memory"); \ } while (0) #define ACPI_RELEASE_GLOBAL_LOCK(GLptr, Acq) \ do { \ - __asm__ volatile ("1: ld4 r29=%1\n" \ + __asm__ volatile ("1: ld4 r29=[%1]\n" \ ";;\n" \ "mov ar.ccv=r29\n" \ "mov r2=r29\n" \ "and r29=-4,r29\n" \ ";;\n" \ - "cmpxchg4.acq r30=%1,r29,ar.ccv\n" \ + "cmpxchg4.acq r30=[%1],r29,ar.ccv\n" \ ";;\n" \ "cmp.eq p6,p7=r2,r30\n" \ "(p7) br.dpnt.few 1b\n" \ "and %0=1,r2\n" \ ";;\n" \ - :"=r"(Acq):"m"(GLptr):"r2","r29","r30","memory"); \ + :"=r"(Acq):"r"(GLptr):"r2","r29","r30","memory"); \ } while (0) const char *acpi_get_sysname (void); diff --git a/include/asm-ia64/atomic.h b/include/asm-ia64/atomic.h index 7e56a421e6bc..69d171ada574 100644 --- a/include/asm-ia64/atomic.h +++ b/include/asm-ia64/atomic.h @@ -14,7 +14,7 @@ */ #include <linux/types.h> -#include <asm/system.h> +#include <asm/intrinsics.h> /* * On IA-64, counter must always be volatile to ensure that that the diff --git a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h index 9ec001ebd341..325bec339c3b 100644 --- a/include/asm-ia64/bitops.h +++ b/include/asm-ia64/bitops.h @@ -9,9 +9,10 @@ * scheduler patch */ +#include <linux/compiler.h> #include <linux/types.h> -#include <asm/system.h> +#include <asm/intrinsics.h> /** * set_bit - Atomically set a bit in memory diff --git a/include/asm-ia64/compat.h b/include/asm-ia64/compat.h new file mode 100644 index 000000000000..a01babfd700e --- /dev/null +++ b/include/asm-ia64/compat.h @@ -0,0 +1,56 @@ +#ifndef _ASM_IA64_COMPAT_H +#define _ASM_IA64_COMPAT_H +/* + * Architecture specific compatibility types + */ +#include <linux/types.h> + +#define COMPAT_USER_HZ 100 + +typedef u32 compat_size_t; +typedef s32 compat_ssize_t; +typedef s32 compat_time_t; +typedef s32 compat_clock_t; +typedef s32 compat_pid_t; +typedef u16 compat_uid_t; +typedef u16 compat_gid_t; +typedef u16 compat_mode_t; +typedef u32 compat_ino_t; +typedef u16 compat_dev_t; +typedef s32 compat_off_t; +typedef u16 compat_nlink_t; + +struct compat_timespec { + compat_time_t tv_sec; + s32 tv_nsec; +}; + +struct compat_timeval { + compat_time_t tv_sec; + s32 tv_usec; +}; + +struct compat_stat { + compat_dev_t st_dev; + u16 __pad1; + compat_ino_t st_ino; + compat_mode_t st_mode; + compat_nlink_t st_nlink; + compat_uid_t st_uid; + compat_gid_t st_gid; + compat_dev_t st_rdev; + u16 __pad2; + u32 st_size; + u32 st_blksize; + u32 st_blocks; + u32 st_atime; + u32 st_atime_nsec; + u32 st_mtime; + u32 st_mtime_nsec; + u32 st_ctime; + u32 st_ctime_nsec; + u32 __unused4; + u32 __unused5; +}; + +#endif /* _ASM_IA64_COMPAT_H */ diff --git a/include/asm-ia64/dma-mapping.h b/include/asm-ia64/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-ia64/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-ia64/ia32.h b/include/asm-ia64/ia32.h index e96985d193a1..1c23e5189319 100644 --- a/include/asm-ia64/ia32.h +++ b/include/asm-ia64/ia32.h @@ -6,30 +6,19 @@ #ifdef CONFIG_IA32_SUPPORT #include <linux/binfmts.h> +#include <linux/compat.h> /* * 32 bit structures for IA32 support. */ /* 32bit compatibility types */ -typedef unsigned int __kernel_size_t32; -typedef int __kernel_ssize_t32; -typedef int __kernel_ptrdiff_t32; -typedef int __kernel_time_t32; -typedef int __kernel_clock_t32; -typedef int __kernel_pid_t32; typedef unsigned short __kernel_ipc_pid_t32; -typedef unsigned short __kernel_uid_t32; typedef unsigned int __kernel_uid32_t32; -typedef unsigned short __kernel_gid_t32; typedef unsigned int __kernel_gid32_t32; -typedef unsigned short __kernel_dev_t32; -typedef unsigned int __kernel_ino_t32; -typedef unsigned short __kernel_mode_t32; typedef unsigned short __kernel_umode_t32; typedef short __kernel_nlink_t32; typedef int __kernel_daddr_t32; -typedef int __kernel_off_t32; typedef unsigned int __kernel_caddr_t32; typedef long __kernel_loff_t32; typedef __kernel_fsid_t __kernel_fsid_t32; @@ -39,20 +28,14 @@ typedef __kernel_fsid_t __kernel_fsid_t32; #define IA32_PAGE_MASK (~(IA32_PAGE_SIZE - 1)) #define IA32_PAGE_ALIGN(addr) (((addr) + IA32_PAGE_SIZE - 1) & IA32_PAGE_MASK) #define IA32_CLOCKS_PER_SEC 100 /* Cast in stone for IA32 Linux */ -#define IA32_TICK(tick) ((unsigned long long)(tick) * IA32_CLOCKS_PER_SEC / CLOCKS_PER_SEC) - -struct timespec32 { - int tv_sec; - int tv_nsec; -}; /* fcntl.h */ struct flock32 { short l_type; short l_whence; - __kernel_off_t32 l_start; - __kernel_off_t32 l_len; - __kernel_pid_t32 l_pid; + compat_off_t l_start; + compat_off_t l_len; + compat_pid_t l_pid; }; #define F_GETLK64 12 @@ -130,6 +113,44 @@ struct sigcontext_ia32 { unsigned int cr2; }; +/* user.h */ +/* + * IA32 (Pentium III/4) FXSR, SSE support + * + * Provide support for the GDB 5.0+ PTRACE_{GET|SET}FPXREGS requests for + * interacting with the FXSR-format floating point environment. Floating + * point data can be accessed in the regular format in the usual manner, + * and both the standard and SIMD floating point data can be accessed via + * the new ptrace requests. In either case, changes to the FPU environment + * will be reflected in the task's state as expected. + */ +struct ia32_user_i387_struct { + int cwd; + int swd; + int twd; + int fip; + int fcs; + int foo; + int fos; + int st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */ +}; + +struct ia32_user_fxsr_struct { + unsigned short cwd; + unsigned short swd; + unsigned short twd; + unsigned short fop; + int fip; + int fcs; + int foo; + int fos; + int mxcsr; + int reserved; + int st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */ + int xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */ + int padding[56]; +}; + /* signal.h */ #define _IA32_NSIG 64 #define _IA32_NSIG_BPW 32 @@ -177,29 +198,6 @@ struct ucontext_ia32 { sigset_t uc_sigmask; /* mask last for extensibility */ }; -struct stat32 { - unsigned short st_dev; - unsigned short __pad1; - unsigned int st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned short __pad2; - unsigned int st_size; - unsigned int st_blksize; - unsigned int st_blocks; - unsigned int st_atime; - unsigned int __unused1; - unsigned int st_mtime; - unsigned int __unused2; - unsigned int st_ctime; - unsigned int __unused3; - unsigned int __unused4; - unsigned int __unused5; -}; - struct stat64 { unsigned short st_dev; unsigned char __pad0[10]; @@ -216,11 +214,11 @@ struct stat64 { unsigned int st_blocks; /* Number 512-byte blocks allocated. */ unsigned int __pad4; /* future possible st_blocks high bits */ unsigned int st_atime; - unsigned int __pad5; + unsigned int st_atime_nsec; unsigned int st_mtime; - unsigned int __pad6; + unsigned int st_mtime_nsec; unsigned int st_ctime; - unsigned int __pad7; /* will be high 32 bits of ctime someday */ + unsigned int st_ctime_nsec; unsigned int st_ino_lo; unsigned int st_ino_hi; }; @@ -275,8 +273,8 @@ typedef struct siginfo32 { unsigned int _pid; /* which child */ unsigned int _uid; /* sender's uid */ int _status; /* exit code */ - __kernel_clock_t32 _utime; - __kernel_clock_t32 _stime; + compat_clock_t _utime; + compat_clock_t _stime; } _sigchld; /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ @@ -462,6 +460,8 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; #define IA32_PTRACE_SETREGS 13 #define IA32_PTRACE_GETFPREGS 14 #define IA32_PTRACE_SETFPREGS 15 +#define IA32_PTRACE_GETFPXREGS 18 +#define IA32_PTRACE_SETFPXREGS 19 #define ia32_start_thread(regs,new_ip,new_sp) do { \ set_fs(USER_DS); \ diff --git a/include/asm-ia64/intrinsics.h b/include/asm-ia64/intrinsics.h new file mode 100644 index 000000000000..d2977f600f80 --- /dev/null +++ b/include/asm-ia64/intrinsics.h @@ -0,0 +1,174 @@ +#ifndef _ASM_IA64_INTRINSICS_H +#define _ASM_IA64_INTRINSICS_H + +/* + * Compiler-dependent intrinsics. + * + * Copyright (C) 2002 Hewlett-Packard Co + * David Mosberger-Tang <davidm@hpl.hp.com> + */ + +/* + * Force an unresolved reference if someone tries to use + * ia64_fetch_and_add() with a bad value. + */ +extern unsigned long __bad_size_for_ia64_fetch_and_add (void); +extern unsigned long __bad_increment_for_ia64_fetch_and_add (void); + +#define IA64_FETCHADD(tmp,v,n,sz) \ +({ \ + switch (sz) { \ + case 4: \ + __asm__ __volatile__ ("fetchadd4.rel %0=[%1],%2" \ + : "=r"(tmp) : "r"(v), "i"(n) : "memory"); \ + break; \ + \ + case 8: \ + __asm__ __volatile__ ("fetchadd8.rel %0=[%1],%2" \ + : "=r"(tmp) : "r"(v), "i"(n) : "memory"); \ + break; \ + \ + default: \ + __bad_size_for_ia64_fetch_and_add(); \ + } \ +}) + +#define ia64_fetch_and_add(i,v) \ +({ \ + __u64 _tmp; \ + volatile __typeof__(*(v)) *_v = (v); \ + switch (i) { \ + case -16: IA64_FETCHADD(_tmp, _v, -16, sizeof(*(v))); break; \ + case -8: IA64_FETCHADD(_tmp, _v, -8, sizeof(*(v))); break; \ + case -4: IA64_FETCHADD(_tmp, _v, -4, sizeof(*(v))); break; \ + case -1: IA64_FETCHADD(_tmp, _v, -1, sizeof(*(v))); break; \ + case 1: IA64_FETCHADD(_tmp, _v, 1, sizeof(*(v))); break; \ + case 4: IA64_FETCHADD(_tmp, _v, 4, sizeof(*(v))); break; \ + case 8: IA64_FETCHADD(_tmp, _v, 8, sizeof(*(v))); break; \ + case 16: IA64_FETCHADD(_tmp, _v, 16, sizeof(*(v))); break; \ + default: \ + _tmp = __bad_increment_for_ia64_fetch_and_add(); \ + break; \ + } \ + (__typeof__(*(v))) (_tmp + (i)); /* return new value */ \ +}) + +/* + * This function doesn't exist, so you'll get a linker error if + * something tries to do an invalid xchg(). + */ +extern void __xchg_called_with_bad_pointer (void); + +static __inline__ unsigned long +__xchg (unsigned long x, volatile void *ptr, int size) +{ + unsigned long result; + + switch (size) { + case 1: + __asm__ __volatile ("xchg1 %0=[%1],%2" : "=r" (result) + : "r" (ptr), "r" (x) : "memory"); + return result; + + case 2: + __asm__ __volatile ("xchg2 %0=[%1],%2" : "=r" (result) + : "r" (ptr), "r" (x) : "memory"); + return result; + + case 4: + __asm__ __volatile ("xchg4 %0=[%1],%2" : "=r" (result) + : "r" (ptr), "r" (x) : "memory"); + return result; + + case 8: + __asm__ __volatile ("xchg8 %0=[%1],%2" : "=r" (result) + : "r" (ptr), "r" (x) : "memory"); + return result; + } + __xchg_called_with_bad_pointer(); + return x; +} + +#define xchg(ptr,x) \ + ((__typeof__(*(ptr))) __xchg ((unsigned long) (x), (ptr), sizeof(*(ptr)))) + +/* + * Atomic compare and exchange. Compare OLD with MEM, if identical, + * store NEW in MEM. Return the initial value in MEM. Success is + * indicated by comparing RETURN with OLD. + */ + +#define __HAVE_ARCH_CMPXCHG 1 + +/* + * This function doesn't exist, so you'll get a linker error + * if something tries to do an invalid cmpxchg(). + */ +extern long __cmpxchg_called_with_bad_pointer(void); + +#define ia64_cmpxchg(sem,ptr,old,new,size) \ +({ \ + __typeof__(ptr) _p_ = (ptr); \ + __typeof__(new) _n_ = (new); \ + __u64 _o_, _r_; \ + \ + switch (size) { \ + case 1: _o_ = (__u8 ) (long) (old); break; \ + case 2: _o_ = (__u16) (long) (old); break; \ + case 4: _o_ = (__u32) (long) (old); break; \ + case 8: _o_ = (__u64) (long) (old); break; \ + default: break; \ + } \ + __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(_o_)); \ + switch (size) { \ + case 1: \ + __asm__ __volatile__ ("cmpxchg1."sem" %0=[%1],%2,ar.ccv" \ + : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ + break; \ + \ + case 2: \ + __asm__ __volatile__ ("cmpxchg2."sem" %0=[%1],%2,ar.ccv" \ + : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ + break; \ + \ + case 4: \ + __asm__ __volatile__ ("cmpxchg4."sem" %0=[%1],%2,ar.ccv" \ + : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ + break; \ + \ + case 8: \ + __asm__ __volatile__ ("cmpxchg8."sem" %0=[%1],%2,ar.ccv" \ + : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ + break; \ + \ + default: \ + _r_ = __cmpxchg_called_with_bad_pointer(); \ + break; \ + } \ + (__typeof__(old)) _r_; \ +}) + +#define cmpxchg_acq(ptr,o,n) ia64_cmpxchg("acq", (ptr), (o), (n), sizeof(*(ptr))) +#define cmpxchg_rel(ptr,o,n) ia64_cmpxchg("rel", (ptr), (o), (n), sizeof(*(ptr))) + +/* for compatibility with other platforms: */ +#define cmpxchg(ptr,o,n) cmpxchg_acq(ptr,o,n) + +#ifdef CONFIG_IA64_DEBUG_CMPXCHG +# define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128; +# define CMPXCHG_BUGCHECK(v) \ + do { \ + if (_cmpxchg_bugcheck_count-- <= 0) { \ + void *ip; \ + extern int printk(const char *fmt, ...); \ + asm ("mov %0=ip" : "=r"(ip)); \ + printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v)); \ + break; \ + } \ + } while (0) +#else /* !CONFIG_IA64_DEBUG_CMPXCHG */ +# define CMPXCHG_BUGCHECK_DECL +# define CMPXCHG_BUGCHECK(v) +#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */ + +#endif /* _ASM_IA64_INTRINSICS_H */ diff --git a/include/asm-ia64/machvec_sn2.h b/include/asm-ia64/machvec_sn2.h index 2e015dec31eb..1330d0ad1b26 100644 --- a/include/asm-ia64/machvec_sn2.h +++ b/include/asm-ia64/machvec_sn2.h @@ -33,34 +33,33 @@ #ifndef _ASM_IA64_MACHVEC_SN2_H #define _ASM_IA64_MACHVEC_SN2_H -extern ia64_mv_setup_t sn1_setup; +extern ia64_mv_setup_t sn_setup; extern ia64_mv_cpu_init_t sn_cpu_init; -extern ia64_mv_irq_init_t sn1_irq_init; +extern ia64_mv_irq_init_t sn_irq_init; extern ia64_mv_map_nr_t sn2_map_nr; extern ia64_mv_send_ipi_t sn2_send_IPI; extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge; -extern ia64_mv_irq_desc sn1_irq_desc; -extern ia64_mv_irq_to_vector sn1_irq_to_vector; -extern ia64_mv_local_vector_to_irq sn1_local_vector_to_irq; -extern ia64_mv_valid_irq sn1_valid_irq; -extern ia64_mv_pci_fixup_t sn1_pci_fixup; -#ifdef Colin /* We are using the same is Generic IA64 calls defined in io.h */ -extern ia64_mv_inb_t sn1_inb; -extern ia64_mv_inw_t sn1_inw; -extern ia64_mv_inl_t sn1_inl; -extern ia64_mv_outb_t sn1_outb; -extern ia64_mv_outw_t sn1_outw; -extern ia64_mv_outl_t sn1_outl; -#endif -extern ia64_mv_pci_alloc_consistent sn1_pci_alloc_consistent; -extern ia64_mv_pci_free_consistent sn1_pci_free_consistent; -extern ia64_mv_pci_map_single sn1_pci_map_single; -extern ia64_mv_pci_unmap_single sn1_pci_unmap_single; -extern ia64_mv_pci_map_sg sn1_pci_map_sg; -extern ia64_mv_pci_unmap_sg sn1_pci_unmap_sg; -extern ia64_mv_pci_dma_sync_single sn1_pci_dma_sync_single; -extern ia64_mv_pci_dma_sync_sg sn1_pci_dma_sync_sg; -extern ia64_mv_pci_dma_address sn1_dma_address; +extern ia64_mv_irq_desc sn_irq_desc; +extern ia64_mv_irq_to_vector sn_irq_to_vector; +extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq; +extern ia64_mv_pci_fixup_t sn_pci_fixup; +extern ia64_mv_inb_t sn_inb; +extern ia64_mv_inw_t sn_inw; +extern ia64_mv_inl_t sn_inl; +extern ia64_mv_outb_t sn_outb; +extern ia64_mv_outw_t sn_outw; +extern ia64_mv_outl_t sn_outl; +extern ia64_mv_mmiob_t sn2_mmiob; +extern ia64_mv_pci_alloc_consistent sn_pci_alloc_consistent; +extern ia64_mv_pci_free_consistent sn_pci_free_consistent; +extern ia64_mv_pci_map_single sn_pci_map_single; +extern ia64_mv_pci_unmap_single sn_pci_unmap_single; +extern ia64_mv_pci_map_sg sn_pci_map_sg; +extern ia64_mv_pci_unmap_sg sn_pci_unmap_sg; +extern ia64_mv_pci_dma_sync_single sn_pci_dma_sync_single; +extern ia64_mv_pci_dma_sync_sg sn_pci_dma_sync_sg; +extern ia64_mv_pci_dma_address sn_dma_address; +extern ia64_mv_pci_dma_supported sn_pci_dma_supported; /* * This stuff has dual use! @@ -69,33 +68,34 @@ extern ia64_mv_pci_dma_address sn1_dma_address; * platform's machvec structure. When compiling a non-generic kernel, * the macros are used directly. */ -#define platform_name "sn2" -#define platform_setup sn1_setup -#define platform_cpu_init sn_cpu_init -#define platform_irq_init sn1_irq_init -#define platform_send_ipi sn2_send_IPI +#define platform_name "sn2" +#define platform_setup sn_setup +#define platform_cpu_init sn_cpu_init +#define platform_irq_init sn_irq_init +#define platform_map_nr sn2_map_nr +#define platform_send_ipi sn2_send_IPI #define platform_global_tlb_purge sn2_global_tlb_purge -#ifdef Colin /* We are using the same is Generic IA64 calls defined in io.h */ -#define platform_inb sn1_inb -#define platform_inw sn1_inw -#define platform_inl sn1_inl -#define platform_outb sn1_outb -#define platform_outw sn1_outw -#define platform_outl sn1_outl -#endif -#define platform_irq_desc sn1_irq_desc -#define platform_irq_to_vector sn1_irq_to_vector -#define platform_local_vector_to_irq sn1_local_vector_to_irq -#define platform_valid_irq sn1_valid_irq -#define platform_pci_dma_init machvec_noop -#define platform_pci_alloc_consistent sn1_pci_alloc_consistent -#define platform_pci_free_consistent sn1_pci_free_consistent -#define platform_pci_map_single sn1_pci_map_single -#define platform_pci_unmap_single sn1_pci_unmap_single -#define platform_pci_map_sg sn1_pci_map_sg -#define platform_pci_unmap_sg sn1_pci_unmap_sg -#define platform_pci_dma_sync_single sn1_pci_dma_sync_single -#define platform_pci_dma_sync_sg sn1_pci_dma_sync_sg -#define platform_pci_dma_address sn1_dma_address +#define platform_pci_fixup sn_pci_fixup +#define platform_inb sn_inb +#define platform_inw sn_inw +#define platform_inl sn_inl +#define platform_outb sn_outb +#define platform_outw sn_outw +#define platform_outl sn_outl +#define platform_mmiob sn2_mmiob +#define platform_irq_desc sn_irq_desc +#define platform_irq_to_vector sn_irq_to_vector +#define platform_local_vector_to_irq sn_local_vector_to_irq +#define platform_pci_dma_init machvec_noop +#define platform_pci_alloc_consistent sn_pci_alloc_consistent +#define platform_pci_free_consistent sn_pci_free_consistent +#define platform_pci_map_single sn_pci_map_single +#define platform_pci_unmap_single sn_pci_unmap_single +#define platform_pci_map_sg sn_pci_map_sg +#define platform_pci_unmap_sg sn_pci_unmap_sg +#define platform_pci_dma_sync_single sn_pci_dma_sync_single +#define platform_pci_dma_sync_sg sn_pci_dma_sync_sg +#define platform_pci_dma_address sn_dma_address +#define platform_pci_dma_supported sn_pci_dma_supported #endif /* _ASM_IA64_MACHVEC_SN2_H */ diff --git a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h index b3ccbc2cd59e..a42ec7f97a21 100644 --- a/include/asm-ia64/mca.h +++ b/include/asm-ia64/mca.h @@ -103,6 +103,8 @@ enum { IA64_MCA_NEW_CONTEXT = -1 /* SAL to return to new context */ }; +#define MIN_STATE_AREA_SIZE 57 + typedef struct ia64_mca_os_to_sal_state_s { u64 imots_os_status; /* OS status to SAL as to what happened * with the MCA handling. @@ -133,7 +135,7 @@ extern void ia64_mca_cmc_int_handler(int,void *,struct pt_regs *); extern void ia64_mca_cpe_int_handler(int,void *,struct pt_regs *); extern int ia64_log_print(int,prfunc_t); extern void ia64_mca_cmc_vector_setup(void); -extern void ia64_mca_check_errors( void ); +extern int ia64_mca_check_errors(void); extern u64 ia64_log_get(int, prfunc_t); #define PLATFORM_CALL(fn, args) printk("Platform call TBD\n") diff --git a/include/asm-ia64/mca_asm.h b/include/asm-ia64/mca_asm.h index 4d41dae31a3e..104c938b2e5b 100644 --- a/include/asm-ia64/mca_asm.h +++ b/include/asm-ia64/mca_asm.h @@ -16,6 +16,7 @@ #define PSR_I 14 #define PSR_DT 17 #define PSR_RT 27 +#define PSR_MC 35 #define PSR_IT 36 #define PSR_BN 44 @@ -107,6 +108,8 @@ ;; \ dep temp1 = 0, temp1, PSR_IC, 1; \ ;; \ + dep temp1 = -1, temp1, PSR_MC, 1; \ + ;; \ movl temp2 = start_addr; \ mov cr.ipsr = temp1; \ ;; \ diff --git a/include/asm-ia64/mman.h b/include/asm-ia64/mman.h index 88c81a1fcfba..698871eeff2d 100644 --- a/include/asm-ia64/mman.h +++ b/include/asm-ia64/mman.h @@ -18,12 +18,14 @@ #define MAP_FIXED 0x10 /* Interpret addr exactly */ #define MAP_ANONYMOUS 0x20 /* don't use a file */ -#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ -#define MAP_GROWSUP 0x0200 /* register stack-like segment */ -#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ -#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ -#define MAP_LOCKED 0x2000 /* pages are locked */ -#define MAP_NORESERVE 0x4000 /* don't check for reservations */ +#define MAP_GROWSDOWN 0x00100 /* stack-like segment */ +#define MAP_GROWSUP 0x00200 /* register stack-like segment */ +#define MAP_DENYWRITE 0x00800 /* ETXTBSY */ +#define MAP_EXECUTABLE 0x01000 /* mark it as an executable */ +#define MAP_LOCKED 0x02000 /* pages are locked */ +#define MAP_NORESERVE 0x04000 /* don't check for reservations */ +#define MAP_POPULATE 0x08000 /* populate (prefault) pagetables */ +#define MAP_NONBLOCK 0x10000 /* do not block on IO */ #define MS_ASYNC 1 /* sync memory asynchronously */ #define MS_INVALIDATE 2 /* invalidate the caches */ diff --git a/include/asm-ia64/mmu.h b/include/asm-ia64/mmu.h index ccd36d26615a..ae1525352a25 100644 --- a/include/asm-ia64/mmu.h +++ b/include/asm-ia64/mmu.h @@ -1,7 +1,11 @@ #ifndef __MMU_H #define __MMU_H -/* Default "unsigned long" context */ -typedef unsigned long mm_context_t; +/* + * Type for a context number. We declare it volatile to ensure proper ordering when it's + * accessed outside of spinlock'd critical sections (e.g., as done in activate_mm() and + * init_new_context()). + */ +typedef volatile unsigned long mm_context_t; #endif diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h index c136636f6896..9316945bd04f 100644 --- a/include/asm-ia64/mmu_context.h +++ b/include/asm-ia64/mmu_context.h @@ -54,33 +54,40 @@ enter_lazy_tlb (struct mm_struct *mm, struct task_struct *tsk, unsigned cpu) static inline void delayed_tlb_flush (void) { - extern void __flush_tlb_all (void); + extern void local_flush_tlb_all (void); if (unlikely(__get_cpu_var(ia64_need_tlb_flush))) { - __flush_tlb_all(); + local_flush_tlb_all(); __get_cpu_var(ia64_need_tlb_flush) = 0; } } -static inline void -get_new_mmu_context (struct mm_struct *mm) +static inline mm_context_t +get_mmu_context (struct mm_struct *mm) { + mm_context_t context = mm->context; + + if (context) + return context; + spin_lock(&ia64_ctx.lock); { - if (ia64_ctx.next >= ia64_ctx.limit) - wrap_mmu_context(mm); - mm->context = ia64_ctx.next++; + /* re-check, now that we've got the lock: */ + context = mm->context; + if (context == 0) { + if (ia64_ctx.next >= ia64_ctx.limit) + wrap_mmu_context(mm); + mm->context = context = ia64_ctx.next++; + } } spin_unlock(&ia64_ctx.lock); + return context; } -static inline void -get_mmu_context (struct mm_struct *mm) -{ - if (mm->context == 0) - get_new_mmu_context(mm); -} - +/* + * Initialize context number to some sane value. MM is guaranteed to be a brand-new + * address-space, so no TLB flushing is needed, ever. + */ static inline int init_new_context (struct task_struct *p, struct mm_struct *mm) { @@ -95,13 +102,13 @@ destroy_context (struct mm_struct *mm) } static inline void -reload_context (struct mm_struct *mm) +reload_context (mm_context_t context) { unsigned long rid; unsigned long rid_incr = 0; unsigned long rr0, rr1, rr2, rr3, rr4; - rid = mm->context << 3; /* make space for encoding the region number */ + rid = context << 3; /* make space for encoding the region number */ rid_incr = 1 << 8; /* encode the region id, preferred page size, and VHPT enable bit: */ @@ -124,6 +131,18 @@ reload_context (struct mm_struct *mm) ia64_insn_group_barrier(); } +static inline void +activate_context (struct mm_struct *mm) +{ + mm_context_t context; + + do { + context = get_mmu_context(mm); + reload_context(context); + /* in the unlikely event of a TLB-flush by another thread, redo the load: */ + } while (unlikely(context != mm->context)); +} + /* * Switch from address space PREV to address space NEXT. */ @@ -133,12 +152,11 @@ activate_mm (struct mm_struct *prev, struct mm_struct *next) delayed_tlb_flush(); /* - * We may get interrupts here, but that's OK because interrupt - * handlers cannot touch user-space. + * We may get interrupts here, but that's OK because interrupt handlers cannot + * touch user-space. */ ia64_set_kr(IA64_KR_PT_BASE, __pa(next->pgd)); - get_mmu_context(next); - reload_context(next); + activate_context(next); } #define switch_mm(prev_mm,next_mm,next_task,cpu) activate_mm(prev_mm, next_mm) diff --git a/include/asm-ia64/mmzone.h b/include/asm-ia64/mmzone.h index 8c408af0aaa7..50ce45597d9f 100644 --- a/include/asm-ia64/mmzone.h +++ b/include/asm-ia64/mmzone.h @@ -104,12 +104,22 @@ extern unsigned long max_low_pfn; /* * Bank definitions. - * Current settings for DIG: 512MB/bank, 16GB/node. + * Configurable settings for DIG: 512MB/bank: 16GB/node, + * 2048MB/bank: 64GB/node, + * 8192MB/bank: 256GB/node. */ #define NR_BANKS_PER_NODE 32 -#define BANK_OFFSET(addr) ((unsigned long)(addr) & (BANKSIZE-1)) -#define DIG_BANKSHIFT 29 +#if defined(CONFIG_IA64_NODESIZE_16GB) +# define DIG_BANKSHIFT 29 +#elif defined(CONFIG_IA64_NODESIZE_64GB) +# define DIG_BANKSHIFT 31 +#elif defined(CONFIG_IA64_NODESIZE_256GB) +# define DIG_BANKSHIFT 33 +#else +# error Unsupported bank and nodesize! +#endif #define BANKSIZE (1UL << DIG_BANKSHIFT) +#define BANK_OFFSET(addr) ((unsigned long)(addr) & (BANKSIZE-1)) #define NR_BANKS (NR_BANKS_PER_NODE * NR_NODES) /* diff --git a/include/asm-ia64/module.h b/include/asm-ia64/module.h index beab8670ffa7..93c32e28600f 100644 --- a/include/asm-ia64/module.h +++ b/include/asm-ia64/module.h @@ -1,111 +1,6 @@ #ifndef _ASM_IA64_MODULE_H #define _ASM_IA64_MODULE_H -/* - * This file contains the ia64 architecture specific module code. - * - * Copyright (C) 2000 Intel Corporation. - * Copyright (C) 2000 Mike Stephens <mike.stephens@intel.com> - */ -#include <linux/module.h> -#include <linux/vmalloc.h> -#include <asm/unwind.h> - -#define module_map(x) vmalloc(x) -#define module_unmap(x) ia64_module_unmap(x) -#define module_arch_init(x) ia64_module_init(x) - -/* - * This must match in size and layout the data created by - * modutils/obj/obj-ia64.c - */ -struct archdata { - const char *unw_table; - const char *segment_base; - const char *unw_start; - const char *unw_end; - const char *gp; -}; - -static inline void -arch_init_modules (struct module *kmod) -{ - static struct archdata archdata; - register char *kernel_gp asm ("gp"); - - archdata.gp = kernel_gp; - kmod->archdata_start = (const char *) &archdata; - kmod->archdata_end = (const char *) (&archdata + 1); -} - -/* - * functions to add/remove a modules unwind info when - * it is loaded or unloaded. - */ -static inline int -ia64_module_init (struct module *mod) -{ - struct archdata *archdata; - - if (!mod_member_present(mod, archdata_start) || !mod->archdata_start) - return 0; - archdata = (struct archdata *)(mod->archdata_start); - - if (archdata->unw_start == 0) - return 0; - - /* - * Make sure the unwind pointers are sane. - */ - - if (archdata->unw_table) { - printk(KERN_ERR "module_arch_init: archdata->unw_table must be zero.\n"); - return 1; - } - if (!mod_bound(archdata->gp, 0, mod)) { - printk(KERN_ERR "module_arch_init: archdata->gp out of bounds.\n"); - return 1; - } - if (!mod_bound(archdata->unw_start, 0, mod)) { - printk(KERN_ERR "module_arch_init: archdata->unw_start out of bounds.\n"); - return 1; - } - if (!mod_bound(archdata->unw_end, 0, mod)) { - printk(KERN_ERR "module_arch_init: archdata->unw_end out of bounds.\n"); - return 1; - } - if (!mod_bound(archdata->segment_base, 0, mod)) { - printk(KERN_ERR "module_arch_init: archdata->segment_base out of bounds.\n"); - return 1; - } - - /* - * Pointers are reasonable, add the module unwind table - */ - archdata->unw_table = unw_add_unwind_table(mod->name, - (unsigned long) archdata->segment_base, - (unsigned long) archdata->gp, - archdata->unw_start, archdata->unw_end); - return 0; -} - -static inline void -ia64_module_unmap (void * addr) -{ - struct module *mod = (struct module *) addr; - struct archdata *archdata; - - /* - * Before freeing the module memory remove the unwind table entry - */ - if (mod_member_present(mod, archdata_start) && mod->archdata_start) { - archdata = (struct archdata *)(mod->archdata_start); - - if (archdata->unw_table != NULL) - unw_remove_unwind_table((void *) archdata->unw_table); - } - - vfree(addr); -} +/* Module support currently broken (due to in-kernel module loader). */ #endif /* _ASM_IA64_MODULE_H */ diff --git a/include/asm-ia64/numa.h b/include/asm-ia64/numa.h index df9160f89df0..a6a87c92689f 100644 --- a/include/asm-ia64/numa.h +++ b/include/asm-ia64/numa.h @@ -62,6 +62,8 @@ extern u8 numa_slit[NR_NODES * NR_NODES]; extern int paddr_to_nid(unsigned long paddr); +#define local_nodeid (cpu_to_node_map[smp_processor_id()]) + #endif /* CONFIG_NUMA */ #endif /* _ASM_IA64_NUMA_H */ diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h index 37011ca30459..b4a59a5173cb 100644 --- a/include/asm-ia64/processor.h +++ b/include/asm-ia64/processor.h @@ -17,7 +17,6 @@ #include <asm/ptrace.h> #include <asm/kregs.h> -#include <asm/system.h> #include <asm/types.h> #define IA64_NUM_DBG_REGS 8 @@ -79,12 +78,12 @@ #include <linux/cache.h> #include <linux/compiler.h> -#include <linux/percpu.h> #include <linux/threads.h> #include <asm/fpu.h> #include <asm/offsets.h> #include <asm/page.h> +#include <asm/percpu.h> #include <asm/rse.h> #include <asm/unwind.h> #include <asm/atomic.h> diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h index 8794070da0ab..fa31d2fff5ff 100644 --- a/include/asm-ia64/sn/addrs.h +++ b/include/asm-ia64/sn/addrs.h @@ -58,14 +58,14 @@ #define NODE_OFFSET(_n) (UINT64_CAST (_n) << NODE_SIZE_BITS) #endif -#define NODE_CAC_BASE(_n) (CAC_BASE + NODE_OFFSET(_n)) +#define NODE_CAC_BASE(_n) (CAC_BASE + NODE_OFFSET(_n)) #define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n)) #define NODE_IO_BASE(_n) (IO_BASE + NODE_OFFSET(_n)) #define NODE_MSPEC_BASE(_n) (MSPEC_BASE + NODE_OFFSET(_n)) #define NODE_UNCAC_BASE(_n) (UNCAC_BASE + NODE_OFFSET(_n)) #define TO_NODE(_n, _x) (NODE_OFFSET(_n) | ((_x) )) -#define TO_NODE_CAC(_n, _x) (NODE_CAC_BASE(_n) | ((_x) & TO_PHYS_MASK)) +#define TO_NODE_CAC(_n, _x) (NODE_CAC_BASE(_n) | ((_x) & TO_PHYS_MASK)) #define TO_NODE_UNCAC(_n, _x) (NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK)) #define TO_NODE_MSPEC(_n, _x) (NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK)) #define TO_NODE_HSPEC(_n, _x) (NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK)) @@ -227,8 +227,8 @@ #ifndef __ASSEMBLY__ -#define HUB_L(_a) *(_a) -#define HUB_S(_a, _d) *(_a) = (_d) +#define HUB_L(_a) (*((volatile typeof(*_a) *)_a)) +#define HUB_S(_a, _d) (*((volatile typeof(*_a) *)_a) = (_d)) #define LOCAL_HUB_L(_r) HUB_L(LOCAL_HUB_ADDR(_r)) #define LOCAL_HUB_S(_r, _d) HUB_S(LOCAL_HUB_ADDR(_r), (_d)) @@ -326,7 +326,7 @@ #define GDA_SIZE(nasid) KLD_GDA(nasid)->size #define NODE_OFFSET_TO_K0(_nasid, _off) \ - (PAGE_OFFSET | NODE_OFFSET(_nasid) | (_off)) + (CACHEABLE_MEM_SPACE | NODE_OFFSET(_nasid) | (_off)) #endif /* __ASSEMBLY__ */ diff --git a/include/asm-ia64/sn/alenlist.h b/include/asm-ia64/sn/alenlist.h index 55189f1631a5..81243e7c2445 100644 --- a/include/asm-ia64/sn/alenlist.h +++ b/include/asm-ia64/sn/alenlist.h @@ -15,7 +15,7 @@ /* * An Address/Length List is used when setting up for an I/O DMA operation. - * A driver creates an Address/Length List that describes to the DMA + * A driver creates an Address/Length List that describes to the the DMA * interface where in memory the DMA should go. The bus interface sets up * mapping registers, if required, and returns a suitable list of "physical * addresses" or "I/O address" to the driver. The driver then uses these diff --git a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h index 0feec4e8df6a..85fadf519f99 100644 --- a/include/asm-ia64/sn/arch.h +++ b/include/asm-ia64/sn/arch.h @@ -33,6 +33,7 @@ typedef u64 shubreg_t; typedef u64 hubreg_t; typedef u64 mmr_t; typedef u64 nic_t; +typedef char cnodeid_t; #define CNODE_TO_CPU_BASE(_cnode) (NODEPDA(_cnode)->node_first_cpu) @@ -43,6 +44,7 @@ typedef u64 nic_t; #define INVALID_NASID ((nasid_t)-1) #define INVALID_CNODEID ((cnodeid_t)-1) #define INVALID_PNODEID ((pnodeid_t)-1) +#define INVALID_SLAB (slabid_t)-1 #define INVALID_MODULE ((moduleid_t)-1) #define INVALID_PARTID ((partid_t)-1) diff --git a/include/asm-ia64/sn/ate_utils.h b/include/asm-ia64/sn/ate_utils.h index 9cba288cfd3c..02bd7cd678c6 100644 --- a/include/asm-ia64/sn/ate_utils.h +++ b/include/asm-ia64/sn/ate_utils.h @@ -1,7 +1,7 @@ #ifndef _ASM_IA64_SN_ATE_UTILS_H #define _ASM_IA64_SN_ATE_UTILS_H -/* $Id$ +/* $Id: ate_utils.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h index 3de9f909edac..5cc1eb60b48b 100644 --- a/include/asm-ia64/sn/bte.h +++ b/include/asm-ia64/sn/bte.h @@ -1,26 +1,52 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * + * + * Copyright (c) 2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: * - * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + * http://www.sgi.com + * + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/NoticeExplan */ + #ifndef _ASM_IA64_SN_BTE_H #define _ASM_IA64_SN_BTE_H -#ident "$Revision: $" +#ident "$Revision: 1.1 $" #include <linux/spinlock.h> #include <linux/cache.h> #include <asm/sn/io.h> -#define L1_CACHE_MASK (L1_CACHE_BYTES - 1) /* Mask to retrieve - * the offset into this - * cache line.*/ - /* BTE status register only supports 16 bits for length field */ -#define BTE_LEN_MASK ((1 << 16) - 1) +#define BTE_LEN_BITS (16) +#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1) +#define BTE_MAX_XFER ((1 << BTE_LEN_BITS) * L1_CACHE_BYTES) + /* * Constants used in determining the best and worst case transfer @@ -68,13 +94,14 @@ typedef struct bteinfo_s { u64 volatile notify ____cacheline_aligned; char *bte_base_addr ____cacheline_aligned; spinlock_t spinlock; - u64 idealTransferTimeout; - u64 idealTransferTimeoutReached; - u64 mostRecentSrc; - u64 mostRecentDest; - u64 mostRecentLen; - u64 mostRecentMode; - u64 volatile *mostRecentNotification; + u64 ideal_xfr_tmo; /* Time out */ + u64 ideal_xfr_tmo_cnt; + /* u64 most_recent_src; + * u64 most_recent_dest; + * u64 most_recent_len; + * u64 most_recent_mode; */ + u64 volatile *most_rcnt_na; + void *bte_test_buf; } bteinfo_t; /* Possible results from bte_copy and bte_unaligned_copy */ @@ -85,4 +112,6 @@ typedef enum { BTEFAIL_DIR /* Diretory error */ } bte_result_t; +void bte_reset_nasid(nasid_t); + #endif /* _ASM_IA64_SN_BTE_H */ diff --git a/include/asm-ia64/sn/bte_copy.h b/include/asm-ia64/sn/bte_copy.h index 48c817e10865..51c45ea15269 100644 --- a/include/asm-ia64/sn/bte_copy.h +++ b/include/asm-ia64/sn/bte_copy.h @@ -1,31 +1,79 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * + * + * Copyright (c) 2000-2002 Silicon Graphics, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it would be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * Further, this software is distributed without any warranty that it is + * free of the rightful claim of any third person regarding infringement + * or the like. Any license provided herein, whether implied or + * otherwise, applies only to this software file. Patent licenses, if + * any, provided herein do not apply to combinations of this program with + * other software, or any other product whatsoever. * - * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. + * You should have received a copy of the GNU General Public + * License along with this program; if not, write the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, + * Mountain View, CA 94043, or: + * + * http://www.sgi.com + * + * For further information regarding this notice, see: + * + * http://oss.sgi.com/projects/GenInfo/NoticeExplan */ #ifndef _ASM_IA64_SN_BTE_COPY_H #define _ASM_IA64_SN_BTE_COPY_H -#ident "$Revision: $" +#ident "$Revision: 1.1 $" +#include <linux/timer.h> +#include <linux/cache.h> #include <asm/sn/bte.h> #include <asm/sn/sgi.h> #include <asm/sn/pda.h> #include <asm/delay.h> +#define L1_CACHE_MASK (L1_CACHE_BYTES - 1) + /* - * BTE_LOCKING support - Undefining the following line will - * adapt the bte_copy code to support one bte per cpu in + * BTE_LOCKING support - When CONFIG_IA64_SGI_BTE_LOCKING is + * not defined, the bte_copy code supports one bte per cpu in * synchronous mode. Even if bte_copy is called with a * notify address, the bte will spin and wait for the transfer * to complete. By defining the following, spin_locks and * busy checks are placed around the initiation of a BTE * transfer and multiple bte's per cpu are supported. */ +#if 0 #define CONFIG_IA64_SGI_BTE_LOCKING 1 +#endif + +/* + * Handle locking of the bte interfaces. + * + * All transfers spinlock the interface before setting up the SHUB + * registers. Sync transfers hold the lock until all processing is + * complete. Async transfers release the lock as soon as the transfer + * is initiated. + * + * To determine if an interface is available, we must check both the + * busy bit and the spinlock for that interface. + */ +#define BTE_LOCK_IF_AVAIL(_x) (\ + (*pda.cpu_bte_if[_x]->most_rcnt_na & IBLS_BUSY) && \ + (!(spin_trylock(&(pda.cpu_bte_if[_x]->spinlock)))) \ + ) /* * Some macros to simplify reading. @@ -33,39 +81,71 @@ * Start with macros to locate the BTE control registers. */ -#define BTEREG_LNSTAT_ADDR (bte->bte_base_addr) -#define BTEREG_SOURCE_ADDR (bte->bte_base_addr + IIO_IBSA0 - IIO_IBLS0) -#define BTEREG_DEST_ADDR (bte->bte_base_addr + IIO_IBDA0 - IIO_IBLS0) -#define BTEREG_CTRL_ADDR (bte->bte_base_addr + IIO_IBCT0 - IIO_IBLS0) -#define BTEREG_NOTIF_ADDR (bte->bte_base_addr + IIO_IBNA0 - IIO_IBLS0) +#define BTEREG_LNSTAT_ADDR ((u64 *)(bte->bte_base_addr)) +#define BTEREG_SRC_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_SRC)) +#define BTEREG_DEST_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_DEST)) +#define BTEREG_CTRL_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_CTRL)) +#define BTEREG_NOTIF_ADDR ((u64 *)(bte->bte_base_addr + BTEOFF_NOTIFY)) /* Some macros to force the IBCT0 value valid. */ #define BTE_VALID_MODES BTE_NOTIFY #define BTE_VLD_MODE(x) (x & BTE_VALID_MODES) -// #define DEBUG_BTE -// #define DEBUG_BTE_VERBOSE -// #define DEBUG_TIME_BTE +// #define BTE_DEBUG +// #define BTE_DEBUG_VERBOSE +// #define BTE_TIME -#ifdef DEBUG_BTE -# define DPRINTK(x) printk x // Terse -# ifdef DEBUG_BTE_VERBOSE -# define DPRINTKV(x) printk x // Verbose +#ifdef BTE_DEBUG +# define BTE_PRINTK(x) printk x /* Terse */ +# ifdef BTE_DEBUG_VERBOSE +# define BTE_PRINTKV(x) printk x /* Verbose */ # else -# define DPRINTKV(x) -# endif +# define BTE_PRINTKV(x) +# endif /* BTE_DEBUG_VERBOSE */ #else -# define DPRINTK(x) -# define DPRINTKV(x) -#endif - -#ifdef DEBUG_TIME_BTE -extern u64 BteSetupTime; -extern u64 BteTransferTime; -extern u64 BteTeardownTime; -extern u64 BteExecuteTime; -#endif +# define BTE_PRINTK(x) +# define BTE_PRINTKV(x) +#endif /* BTE_DEBUG */ + +#define BTE_IDEAL_TMO(x) (jiffies + \ + (HZ / BTE_MAXT_LINES_PER_SECOND * x)) + +#ifdef BTE_TIME +volatile extern u64 bte_setup_time; +volatile extern u64 bte_transfer_time; +volatile extern u64 bte_tear_down_time; +volatile extern u64 bte_execute_time; + +#define BTE_TIME_DECLARE() \ + u64 btcp_strt_tm = 0; \ + u64 btcp_cplt_tm = 0; \ + u64 xfr_strt_tm = 0; \ + u64 xfr_cplt_tm = 0; \ + +#define BTE_TIME_START() \ + btcp_strt_tm = xfr_strt_tm = xfr_cplt_tm = ia64_get_itc(); + +#define BTE_TIME_XFR_START() \ + xfr_strt_tm = ia64_get_itc(); + +#define BTE_TIME_XFR_STOP() \ + xfr_cplt_tm = ia64_get_itc(); + +#define BTE_TIME_STOP() \ + btcp_cplt_tm = ia64_get_itc(); \ + bte_setup_time = xfr_strt_tm - btcp_strt_tm; \ + bte_transfer_time = xfr_cplt_tm - xfr_strt_tm; \ + bte_tear_down_time = btcp_cplt_tm - xfr_cplt_tm; \ + bte_execute_time = btcp_cplt_tm - btcp_strt_tm; \ + +#else /* BTE_TIME */ +#define BTE_TIME_DECLARE() +#define BTE_TIME_START() +#define BTE_TIME_XFR_START() +#define BTE_TIME_XFR_STOP() +#define BTE_TIME_STOP() +#endif /* BTE_TIME */ /* * bte_copy(src, dest, len, mode, notification) @@ -91,25 +171,19 @@ bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification) { #ifdef CONFIG_IA64_SGI_BTE_LOCKING int bte_to_use; -#endif - -#ifdef DEBUG_TIME_BTE - u64 invokeTime = 0; - u64 completeTime = 0; - u64 xferStartTime = 0; - u64 xferCompleteTime = 0; -#endif - u64 transferSize; +#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ + u64 transfer_size; + u64 lines_remaining; bteinfo_t *bte; + BTE_TIME_DECLARE(); -#ifdef DEBUG_TIME_BTE - invokeTime = ia64_get_itc(); -#endif + BTE_TIME_START(); - DPRINTK(("bte_copy (0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)\n", - src, dest, len, mode, notification)); + BTE_PRINTK(("bte_copy (0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)\n", + src, dest, len, mode, notification)); if (len == 0) { + BTE_TIME_STOP(); return (BTE_SUCCESS); } @@ -123,17 +197,15 @@ bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification) bte_to_use = 0; /* Attempt to lock one of the BTE interfaces */ - while ((*pda.cpubte[bte_to_use]-> - mostRecentNotification & IBLS_BUSY) - && - (!(spin_trylock - (&(pda.cpubte[bte_to_use]->spinlock)))) - && (bte_to_use < BTES_PER_NODE)) { + while ((bte_to_use < BTES_PER_NODE) && + BTE_LOCK_IF_AVAIL(bte_to_use)) { + bte_to_use++; } if ((bte_to_use >= BTES_PER_NODE) && !(mode & BTE_WACQUIRE)) { + BTE_TIME_STOP(); return (BTEFAIL_NOTAVAIL); } @@ -141,12 +213,12 @@ bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification) } while (bte_to_use >= BTES_PER_NODE); - bte = pda.cpubte[bte_to_use]; - DPRINTKV(("Got a lock on bte %d\n", bte_to_use)); + bte = pda.cpu_bte_if[bte_to_use]; + BTE_PRINTKV(("Got a lock on bte %d\n", bte_to_use)); #else /* Assuming one BTE per CPU. */ - bte = pda.cpubte[0]; -#endif + bte = pda->cpu_bte_if[0]; +#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ /* * The following are removed for optimization but is @@ -160,65 +232,51 @@ bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification) */ if (notification == NULL) { /* User does not want to be notified. */ - bte->mostRecentNotification = &bte->notify; + bte->most_rcnt_na = &bte->notify; } else { - bte->mostRecentNotification = notification; + bte->most_rcnt_na = notification; } /* Calculate the number of cache lines to transfer. */ - transferSize = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK); + transfer_size = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK); - DPRINTKV(("Calculated transfer size of %d cache lines\n", - transferSize)); + BTE_PRINTKV(("Calculated transfer size of %d cache lines\n", + transfer_size)); /* Initialize the notification to a known value. */ - *bte->mostRecentNotification = -1L; + *bte->most_rcnt_na = -1L; - DPRINTKV(("Before, status is 0x%lx and notify is 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - *bte->mostRecentNotification)); + BTE_PRINTKV(("Before, status is 0x%lx and notify is 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + *bte->most_rcnt_na)); /* Set the status reg busy bit and transfer length */ - DPRINTKV(("IBLS - HUB_S(0x%lx, 0x%lx)\n", - BTEREG_LNSTAT_ADDR, IBLS_BUSY | transferSize)); - HUB_S(BTEREG_LNSTAT_ADDR, IBLS_BUSY | transferSize); - - - DPRINTKV(("After setting status, status is 0x%lx and notify is 0x%lx\n", HUB_L(BTEREG_LNSTAT_ADDR), *bte->mostRecentNotification)); + BTE_PRINTKV(("IBLS - HUB_S(0x%lx, 0x%lx)\n", + BTEREG_LNSTAT_ADDR, IBLS_BUSY | transfer_size)); + HUB_S(BTEREG_LNSTAT_ADDR, (IBLS_BUSY | transfer_size)); /* Set the source and destination registers */ - DPRINTKV(("IBSA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_SOURCE_ADDR, - src)); - HUB_S(BTEREG_SOURCE_ADDR, src); - DPRINTKV(("IBDA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_DEST_ADDR, dest)); - HUB_S(BTEREG_DEST_ADDR, dest); - + BTE_PRINTKV(("IBSA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_SRC_ADDR, + (TO_PHYS(src)))); + HUB_S(BTEREG_SRC_ADDR, (TO_PHYS(src))); + BTE_PRINTKV(("IBDA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_DEST_ADDR, + (TO_PHYS(dest)))); + HUB_S(BTEREG_DEST_ADDR, (TO_PHYS(dest))); /* Set the notification register */ - DPRINTKV(("IBNA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_NOTIF_ADDR, - __pa(bte->mostRecentNotification))); - HUB_S(BTEREG_NOTIF_ADDR, (__pa(bte->mostRecentNotification))); - - - DPRINTKV(("Set Notify, status is 0x%lx and notify is 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - *bte->mostRecentNotification)); + BTE_PRINTKV(("IBNA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_NOTIF_ADDR, + (TO_PHYS(__pa(bte->most_rcnt_na))))); + HUB_S(BTEREG_NOTIF_ADDR, (TO_PHYS(__pa(bte->most_rcnt_na)))); /* Initiate the transfer */ - DPRINTKV(("IBCT - HUB_S(0x%lx, 0x%lx)\n", BTEREG_CTRL_ADDR, mode)); -#ifdef DEBUG_TIME_BTE - xferStartTime = ia64_get_itc(); -#endif + BTE_PRINTKV(("IBCT - HUB_S(0x%lx, 0x%lx)\n", BTEREG_CTRL_ADDR, mode)); + BTE_TIME_XFR_START(); HUB_S(BTEREG_CTRL_ADDR, BTE_VLD_MODE(mode)); - DPRINTKV(("Initiated, status is 0x%lx and notify is 0x%lx\n", - HUB_L(BTEREG_LNSTAT_ADDR), - *bte->mostRecentNotification)); - - // >>> Temporarily work around not getting a notification - // from medusa. - // *bte->mostRecentNotification = HUB_L(bte->bte_base_addr); + BTE_PRINTKV(("Initiated, status is 0x%lx and notify is 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + *bte->most_rcnt_na)); if (notification == NULL) { /* @@ -240,56 +298,75 @@ bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification) * delay from hardware completing our request and * our detecting the failure. */ - bte->idealTransferTimeout = jiffies + - (HZ / BTE_MAXT_LINES_PER_SECOND * transferSize); + bte->ideal_xfr_tmo = BTE_IDEAL_TMO(transfer_size); - while ((IBLS_BUSY & bte->notify)) { + while (bte->notify == -1UL) { /* * Notification Workaround: When the max * theoretical time has elapsed, read the hub * status register into the notification area. * This fakes the shub performing the copy. */ - if (time_after(jiffies, bte->idealTransferTimeout)) { - bte->notify = HUB_L(bte->bte_base_addr); - bte->idealTransferTimeoutReached++; - bte->idealTransferTimeout = jiffies + - (HZ / BTE_MAXT_LINES_PER_SECOND * - (bte->notify & BTE_LEN_MASK)); + BTE_PRINTKV((" Timing. IBLS = 0x%lx, " + "notify= 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + bte->notify)); + if (time_after(jiffies, bte->ideal_xfr_tmo)) { + lines_remaining = HUB_L(BTEREG_LNSTAT_ADDR) & + BTE_LEN_MASK; + bte->ideal_xfr_tmo_cnt++; + bte->ideal_xfr_tmo = + BTE_IDEAL_TMO(lines_remaining); + + BTE_PRINTKV((" Timeout. cpu %d " + "IBLS = 0x%lx, " + "notify= 0x%lx, " + "Lines remaining = %d. " + "New timeout = %d.\n", + smp_processor_id(), + HUB_L(BTEREG_LNSTAT_ADDR), + bte->notify, + lines_remaining, + bte->ideal_xfr_tmo)); } } -#ifdef DEBUG_TIME_BTE - xferCompleteTime = ia64_get_itc(); -#endif + BTE_PRINTKV((" Delay Done. IBLS = 0x%lx, notify= 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + bte->notify)); + BTE_TIME_XFR_STOP(); if (bte->notify & IBLS_ERROR) { /* >>> Need to do real error checking. */ - transferSize = 0; + transfer_size = 0; #ifdef CONFIG_IA64_SGI_BTE_LOCKING spin_unlock(&(bte->spinlock)); -#endif +#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ + BTE_PRINTKV(("Erroring status is 0x%lx and " + "notify is 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + bte->notify)); + + BTE_TIME_STOP(); + bte->notify = 0L; return (BTEFAIL_ERROR); } } #ifdef CONFIG_IA64_SGI_BTE_LOCKING spin_unlock(&(bte->spinlock)); -#endif -#ifdef DEBUG_TIME_BTE - completeTime = ia64_get_itc(); +#endif /* CONFIG_IA64_SGI_BTE_LOCKING */ + BTE_TIME_STOP(); + BTE_PRINTKV(("Returning status is 0x%lx and notify is 0x%lx\n", + HUB_L(BTEREG_LNSTAT_ADDR), + *bte->most_rcnt_na)); - BteSetupTime = xferStartTime - invokeTime; - BteTransferTime = xferCompleteTime - xferStartTime; - BteTeardownTime = completeTime - xferCompleteTime; - BteExecuteTime = completeTime - invokeTime; -#endif return (BTE_SUCCESS); } /* * Define the bte_unaligned_copy as an extern. */ -extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64, char *); +extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64); /* * The following is the prefered way of calling bte_unaligned_copy @@ -299,13 +376,10 @@ extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64, char *); * until the transfer is complete. In order to get the asynch * version of bte_copy, you must perform this check yourself. */ -#define BTE_UNALIGNED_COPY(src, dest, len, mode, bteBlock) \ - if ((len & L1_CACHE_MASK) || \ - (src & L1_CACHE_MASK) || \ - (dest & L1_CACHE_MASK)) { \ - bte_unaligned_copy (src, dest, len, mode, bteBlock); \ - } else { \ - bte_copy(src, dest, len, mode, NULL); \ - } +#define BTE_UNALIGNED_COPY(src, dest, len, mode) \ + (((len & L1_CACHE_MASK) || (src & L1_CACHE_MASK) || \ + (dest & L1_CACHE_MASK)) ? \ + bte_unaligned_copy(src, dest, len, mode) : \ + bte_copy(src, dest, len, mode, NULL)) -#endif /* _ASM_IA64_SN_BTE_COPY_H */ +#endif /* _ASM_IA64_SN_BTE_COPY_H */ diff --git a/include/asm-ia64/sn/clksupport.h b/include/asm-ia64/sn/clksupport.h index 57a7fd97cd87..98b9cac4d284 100644 --- a/include/asm-ia64/sn/clksupport.h +++ b/include/asm-ia64/sn/clksupport.h @@ -29,22 +29,30 @@ #include <asm/sn/addrs.h> typedef long clkreg_t; -extern long sn_rtc_cycles_per_second; +extern unsigned long sn_rtc_cycles_per_second; #if defined(CONFIG_IA64_SGI_SN1) #include <asm/sn/sn1/bedrock.h> #include <asm/sn/sn1/hubpi_next.h> + +extern nasid_t master_nasid; + +#define RTC_MASK (0x007fffffffffffff) /* clocks are not synchronized yet on SN1 - used node 0 (problem if no NASID 0) */ -#define RTC_COUNTER_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COUNTER)) -#define RTC_COMPARE_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COMPARE_A)) -#define RTC_COMPARE_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COMPARE_B)) -#define RTC_INT_PENDING_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_PEND_A)) -#define RTC_INT_PENDING_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_PEND_B)) -#define RTC_INT_ENABLED_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_EN_A)) -#define RTC_INT_ENABLED_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_EN_B)) -#else +#define RTC_COUNTER_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_COUNTER)) +#define RTC_COMPARE_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_COMPARE_A)) +#define RTC_COMPARE_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_COMPARE_B)) +#define RTC_INT_PENDING_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_PEND_A)) +#define RTC_INT_PENDING_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_PEND_B)) +#define RTC_INT_ENABLED_A_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_EN_A)) +#define RTC_INT_ENABLED_B_ADDR ((clkreg_t*)REMOTE_HUB_ADDR(master_nasid, PI_RT_INT_EN_B)) +#else /* !CONFIG_IA64_SGI_SN1 */ +#include <asm/sn/addrs.h> +#include <asm/sn/sn2/addrs.h> +#include <asm/sn/sn2/shubio.h> #include <asm/sn/sn2/shub_mmr.h> +#define RTC_MASK (SH_RTC_MASK) #define RTC_COUNTER_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_COMPARE_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_COMPARE_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) @@ -52,7 +60,7 @@ extern long sn_rtc_cycles_per_second; #define RTC_INT_PENDING_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_INT_ENABLED_A_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) #define RTC_INT_ENABLED_B_ADDR ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC)) -#endif +#endif /* CONFIG_IA64_SGI_SN1 */ #define GET_RTC_COUNTER() (*RTC_COUNTER_ADDR) diff --git a/include/asm-ia64/sn/eeprom.h b/include/asm-ia64/sn/eeprom.h index bf481c64d0f9..b89d68cfcf6a 100644 --- a/include/asm-ia64/sn/eeprom.h +++ b/include/asm-ia64/sn/eeprom.h @@ -11,6 +11,7 @@ #ifndef _ASM_IA64_SN_EEPROM_H #define _ASM_IA64_SN_EEPROM_H +#include <linux/config.h> #include <asm/sn/sgi.h> #include <asm/sn/vector.h> #include <asm/sn/xtalk/xbow.h> @@ -291,6 +292,8 @@ typedef struct eeprom_brd_record_t /* functions & macros for obtaining "NIC-like" strings from EEPROMs */ +#ifdef CONFIG_IA64_SGI_SN1 + int eeprom_str( char *nic_str, nasid_t nasid, int component ); int vector_eeprom_str( char *nic_str, nasid_t nasid, int component, net_vec_t path ); @@ -300,6 +303,7 @@ int vector_eeprom_str( char *nic_str, nasid_t nasid, #define RBRICK_EEPROM_STR(s,n,p) vector_eeprom_str((s),(n),R_BRICK,p) #define VECTOR_EEPROM_STR(s,n,p) vector_eeprom_str((s),(n),VECTOR,p) +#endif /* CONFIG_IA64_SGI_SN1 */ /* functions for obtaining formatted records from EEPROMs @@ -313,13 +317,6 @@ int vector_eeprom_read( eeprom_brd_record_t *buf, nasid_t nasid, net_vec_t path, int component ); -/* functions providing unique id's for duplonet and i/o discovery - */ - -int cbrick_uid_get( nasid_t nasid, uint64_t *uid ); -int rbrick_uid_get( nasid_t nasid, net_vec_t path, uint64_t *uid ); -int iobrick_uid_get( nasid_t nasid, uint64_t *uid ); - /* retrieve the ethernet MAC address for an I-brick */ @@ -384,8 +381,4 @@ int is_iobrick( int nasid, int widget_num ); ( IO_BRICK, NASID_GET((r)), (v), 0 ) \ : nic_bridge_vertex_info((v), (r)) ) -#define HUB_UID_GET(n,v,p) cbrick_uid_get((n),(p)) -#define ROUTER_UID_GET(d,p) rbrick_uid_get(get_nasid(),(d),(p)) -#define XBOW_UID_GET(n,p) iobrick_uid_get((n),(p)) - #endif /* _ASM_IA64_SN_EEPROM_H */ diff --git a/include/asm-ia64/sn/fetchop.h b/include/asm-ia64/sn/fetchop.h index 7d43ea29f85e..53b7b4f3fbb4 100644 --- a/include/asm-ia64/sn/fetchop.h +++ b/include/asm-ia64/sn/fetchop.h @@ -7,10 +7,11 @@ * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. */ - #ifndef _ASM_IA64_SN_FETCHOP_H #define _ASM_IA64_SN_FETCHOP_H +#include <linux/config.h> + #define FETCHOP_BASENAME "sgi_fetchop" #define FETCHOP_FULLNAME "/dev/sgi_fetchop" @@ -30,11 +31,71 @@ #define FETCHOP_CLEAR_CACHE 56 #define FETCHOP_LOAD_OP(addr, op) ( \ - *(long *)((char*) (addr) + (op))) + *(volatile long *)((char*) (addr) + (op))) #define FETCHOP_STORE_OP(addr, op, x) ( \ - *(long *)((char*) (addr) + (op)) = \ - (long) (x)) + *(volatile long *)((char*) (addr) + (op)) = (long) (x)) + +#ifdef __KERNEL__ + +/* + * Initialize a FETCHOP line. The argument should point to the beginning + * of the line. + * SN1 - region mask is in word 0, data in word 1 + * SN2 - no region mask. Data in word 0 + */ +#ifdef CONFIG_IA64_SGI_SN1 +#define FETCHOP_INIT_LINE(p) *(p) = 0xffffffffffffffffUL +#elif CONFIG_IA64_SGI_SN2 +#define FETCHOP_INIT_LINE(p) +#endif + +/* + * Convert a region 7 (kaddr) address to the address of the fetchop variable + */ +#define FETCHOP_KADDR_TO_MSPEC_ADDR(kaddr) TO_MSPEC(kaddr) + +/* + * Convert a page struct (page) address to the address of the first + * fetchop variable in the page + */ +#define FETCHOP_PAGE_TO_MSPEC_ADDR(page) FETCHOP_KADDR_TO_MSPEC_ADDR(__pa(page_address(page))) + + +/* + * Each Atomic Memory Operation (AMO formerly known as fetchop) + * variable is 64 bytes long. The first 8 bytes are used. The + * remaining 56 bytes are unaddressable due to the operation taking + * that portion of the address. + * + * NOTE: The AMO_t _MUST_ be placed in either the first or second half + * of the cache line. The cache line _MUST NOT_ be used for anything + * other than additional AMO_t entries. This is because there are two + * addresses which reference the same physical cache line. One will + * be a cached entry with the memory type bits all set. This address + * may be loaded into processor cache. The AMO_t will be referenced + * uncached via the memory special memory type. If any portion of the + * cached cache-line is modified, when that line is flushed, it will + * overwrite the uncached value in physical memory and lead to + * inconsistency. + */ +typedef struct { + +#ifdef CONFIG_IA64_SGI_SN1 + u64 permissions; +#endif + u64 variable; + +#ifdef CONFIG_IA64_SGI_SN1 + u64 unused[6]; +#else + u64 unused[7]; +#endif + +} AMO_t; + + +#endif /* __KERNEL__ */ #endif /* _ASM_IA64_SN_FETCHOP_H */ diff --git a/include/asm-ia64/sn/hack.h b/include/asm-ia64/sn/hack.h index 6632872c9b22..b4f8a8f28931 100644 --- a/include/asm-ia64/sn/hack.h +++ b/include/asm-ia64/sn/hack.h @@ -11,6 +11,8 @@ #ifndef _ASM_IA64_SN_HACK_H #define _ASM_IA64_SN_HACK_H +#include <linux/mmzone.h> +#include <asm/sn/arch.h> #include <asm/sn/types.h> #include <asm/uaccess.h> /* for copy_??_user */ @@ -22,9 +24,6 @@ typedef int cred_t; /* This is for compilation reasons */ struct cred { int x; }; -#define mrlock(_s, _t, _u) -#define mrunlock(_s) - /* * Hardware Graph routines that are currently stubbed! */ @@ -60,9 +59,9 @@ typedef int (*splfunc_t)(void); extern void * snia_kmem_alloc_node(register size_t, register int, cnodeid_t); extern void * snia_kmem_zalloc(size_t, int); extern void * snia_kmem_zalloc_node(register size_t, register int, cnodeid_t ); -extern void * snia_kmem_zone_alloc(register zone_t *, int); -extern zone_t * snia_kmem_zone_init(register int , char *); -extern void snia_kmem_zone_free(register zone_t *, void *); +extern void * snia_kmem_zone_alloc(register struct zone *, int); +extern struct zone * snia_kmem_zone_init(register int , char *); +extern void snia_kmem_zone_free(register struct zone *, void *); extern int is_specified(char *); extern int cap_able(uint64_t); extern int compare_and_swap_ptr(void **, void *, void *); diff --git a/include/asm-ia64/sn/idle.h b/include/asm-ia64/sn/idle.h index cc0c84d36869..c1f5688457bd 100644 --- a/include/asm-ia64/sn/idle.h +++ b/include/asm-ia64/sn/idle.h @@ -15,13 +15,13 @@ static __inline__ void snidle(void) { - +#if 0 #ifdef CONFIG_IA64_SGI_AUTOTEST { extern int autotest_enabled; if (autotest_enabled) { - extern void llsc_main(int, long, long); - llsc_main(smp_processor_id(), 0xe000000000000000LL, 0xe000000001000000LL); + extern void llsc_main(int); + llsc_main(smp_processor_id()); } } #endif @@ -39,16 +39,19 @@ snidle(void) { #endif pda.idle_flag = 1; +#endif } static __inline__ void snidleoff(void) { +#if 0 /* * Turn the activity LED on. */ set_led_bits(LED_CPU_ACTIVITY, LED_CPU_ACTIVITY); pda.idle_flag = 0; +#endif } #endif /* _ASM_IA64_SN_IDLE_H */ diff --git a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h index 89fe0da603d9..36e3af325cc9 100644 --- a/include/asm-ia64/sn/intr.h +++ b/include/asm-ia64/sn/intr.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_INTR_H #define _ASM_IA64_SN_INTR_H @@ -17,4 +17,8 @@ #include <asm/sn/sn2/intr.h> #endif +extern void sn_send_IPI_phys(long, int, int); + +#define CPU_VECTOR_TO_IRQ(cpuid,vector) ((cpuid) << 8 | (vector)) + #endif /* _ASM_IA64_SN_INTR_H */ diff --git a/include/asm-ia64/sn/ioerror.h b/include/asm-ia64/sn/ioerror.h index b44b035d8316..391bf62d7a36 100644 --- a/include/asm-ia64/sn/ioerror.h +++ b/include/asm-ia64/sn/ioerror.h @@ -121,7 +121,7 @@ */ typedef struct io_error_s { - /* Bit fields indicating which sturcture fields are valid */ + /* Bit fields indicating which structure fields are valid */ union { struct { unsigned ievb_errortype:1; @@ -138,6 +138,7 @@ typedef struct io_error_s { unsigned ievb_memaddr:1; unsigned ievb_epc:1; unsigned ievb_ef:1; + unsigned ievb_tnum:1; } iev_b; unsigned iev_a; } ie_v; @@ -156,13 +157,14 @@ typedef struct io_error_s { paddr_t ie_memaddr; /* Physical memory address */ caddr_t ie_epc; /* pc when error reported */ caddr_t ie_ef; /* eframe when error reported */ - + short ie_tnum; /* Xtalk TNUM field */ } ioerror_t; #define IOERROR_INIT(e) do { (e)->ie_v.iev_a = 0; } while (0) #define IOERROR_SETVALUE(e,f,v) do { (e)->ie_ ## f = (v); (e)->ie_v.iev_b.ievb_ ## f = 1; } while (0) -#define IOERROR_FIELDVALID(e,f) (((e)->ie_v.iev_b.ievb_ ## f) != 0) -#define IOERROR_GETVALUE(e,f) (ASSERT(IOERROR_FIELDVALID(e,f)),((e)->ie_ ## f)) +#define IOERROR_FIELDVALID(e,f) ((unsigned long long)((e)->ie_v.iev_b.ievb_ ## f) != (unsigned long long) 0) +#define IOERROR_NOGETVALUE(e,f) (ASSERT(IOERROR_FIELDVALID(e,f)), ((e)->ie_ ## f)) +#define IOERROR_GETVALUE(p,e,f) ASSERT(IOERROR_FIELDVALID(e,f)); p=((e)->ie_ ## f) /* hub code likes to call the SysAD address "hubaddr" ... */ #define ie_hubaddr ie_sysioaddr diff --git a/include/asm-ia64/sn/iograph.h b/include/asm-ia64/sn/iograph.h index 046d6cd5e7a7..d6a6f62ba347 100644 --- a/include/asm-ia64/sn/iograph.h +++ b/include/asm-ia64/sn/iograph.h @@ -32,6 +32,7 @@ #define EDGE_LBL_CONTROLLER "controller" #define EDGE_LBL_CPU "cpu" #define EDGE_LBL_CPUNUM "cpunum" +#define EDGE_LBL_DIRECT "direct" #define EDGE_LBL_DISABLED "disabled" #define EDGE_LBL_DISK "disk" #define EDGE_LBL_DMA_ENGINE "dma_engine" /* Only available on @@ -67,6 +68,7 @@ #define EDGE_LBL_HPC "hpc" #define EDGE_LBL_GFX "gfx" #define EDGE_LBL_HUB "hub" /* For SN0 */ +#define EDGE_LBL_HW "hw" #define EDGE_LBL_SYNERGY "synergy" /* For SNIA only */ #define EDGE_LBL_IBUS "ibus" /* For EVEREST */ #define EDGE_LBL_INTERCONNECT "link" @@ -74,6 +76,8 @@ #define EDGE_LBL_IO4 "io4" /* For EVEREST */ #define EDGE_LBL_IOC3 "ioc3" #define EDGE_LBL_LUN "lun" +#define EDGE_LBL_LINUX "linux" +#define EDGE_LBL_LINUX_BUS EDGE_LBL_LINUX "/busnum" #define EDGE_LBL_MACE "mace" /* O2 mace */ #define EDGE_LBL_MACHDEP "machdep" /* Platform depedent devices */ #define EDGE_LBL_MASTER ".master" @@ -86,6 +90,9 @@ #define EDGE_LBL_NVRAM "nvram" #define EDGE_LBL_PARTITION "partition" #define EDGE_LBL_PCI "pci" +#define EDGE_LBL_PCIX "pci-x" +#define EDGE_LBL_PCIX_0 EDGE_LBL_PCIX "/0" +#define EDGE_LBL_PCIX_1 EDGE_LBL_PCIX "/1" #define EDGE_LBL_PORT "port" #define EDGE_LBL_PROM "prom" #define EDGE_LBL_RACK "rack" @@ -112,6 +119,7 @@ #define EDGE_LBL_XPLINK "xplink" /* Cross partition */ #define EDGE_LBL_XPLINK_NET "net" /* XP network devs */ #define EDGE_LBL_XPLINK_RAW "raw" /* XP Raw devs */ +#define EDGE_LBL_SLAB "slab" /* Slab of a module */ #define EDGE_LBL_XPLINK_KERNEL "kernel" /* XP kernel devs */ #define EDGE_LBL_XPLINK_ADMIN "admin" /* Partition admin */ #define EDGE_LBL_KAIO "kaio" /* Kernel async i/o poll */ @@ -202,7 +210,7 @@ void init_all_devices(void); #include <asm/sn/xtalk/xbow.h> /* For get MAX_PORT_NUM */ -int io_brick_map_widget(char, int); +int io_brick_map_widget(int, int); int io_path_map_widget(devfs_handle_t); /* @@ -210,8 +218,7 @@ int io_path_map_widget(devfs_handle_t); */ struct io_brick_map_s { - char ibm_type; /* brick type, e.g. */ - /* 'I' for Ibrick */ + int ibm_type; /* brick type */ int ibm_map_wid[MAX_PORT_NUM]; /* wid to int map */ }; diff --git a/include/asm-ia64/sn/klclock.h b/include/asm-ia64/sn/klclock.h index 5244401ef708..702460435f68 100644 --- a/include/asm-ia64/sn/klclock.h +++ b/include/asm-ia64/sn/klclock.h @@ -10,6 +10,7 @@ #define _ASM_IA64_SN_KLCLOCK_H #include <asm/sn/ioc3.h> +#include <asm/sn/ioc4.h> #define RTC_BASE_ADDR (unsigned char *)(nvram_base) diff --git a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h index 733ed89a4325..697ff4cd8a43 100644 --- a/include/asm-ia64/sn/klconfig.h +++ b/include/asm-ia64/sn/klconfig.h @@ -55,6 +55,10 @@ #include <asm/sn/sn2/shub_md.h> #endif +#ifdef CONFIG_IA64_SGI_SN2 +#include <asm/sn/geo.h> +#endif + #define KLCFGINFO_MAGIC 0xbeedbabe typedef s32 klconf_off_t; @@ -335,8 +339,8 @@ typedef struct kl_config_hdr { #define KLCLASS_IOBRICK 0x70 /* IP35 iobrick */ -#define KLCLASS_MAX 7 /* Bump this if a new CLASS is added */ -#define KLTYPE_MAX 10 /* Bump this if a new CLASS is added */ +#define KLCLASS_MAX 8 /* Bump this if a new CLASS is added */ +#define KLTYPE_MAX 11 /* Bump this if a new CLASS is added */ #define KLCLASS_UNKNOWN 0xf0 @@ -353,7 +357,7 @@ typedef struct kl_config_hdr { #define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0) #define KLTYPE_SNIA (KLCLASS_CPU | 0x1) -#define KLTYPE_WEIRDIO (KLCLASS_IO | 0x0) +#define KLTYPE_WEIRDIO (KLCLASS_IOBRICK | 0x0) #define KLTYPE_BASEIO (KLCLASS_IO | 0x1) /* IOC3, SuperIO, Bridge, SCSI */ #define KLTYPE_IO6 KLTYPE_BASEIO /* Additional name */ #define KLTYPE_4CHSCSI (KLCLASS_IO | 0x2) @@ -433,7 +437,11 @@ typedef struct lboard_s { unsigned char brd_flags; /* Enabled, Disabled etc */ unsigned char brd_slot; /* slot number */ unsigned short brd_debugsw; /* Debug switches */ +#ifdef CONFIG_IA64_SGI_SN2 + geoid_t brd_geoid; /* geo id */ +#else moduleid_t brd_module; /* module to which it belongs */ +#endif partid_t brd_partition; /* Partition number */ unsigned short brd_diagval; /* diagnostic value */ unsigned short brd_diagparm; /* diagnostic parameter */ @@ -448,6 +456,9 @@ typedef struct lboard_s { confidence_t brd_confidence; /* confidence that the board is bad */ nasid_t brd_owner; /* who owns this board */ unsigned char brd_nic_flags; /* To handle 8 more NICs */ +#ifdef CONFIG_IA64_SGI_SN2 + char pad[32]; /* future expansion */ +#endif char brd_name[32]; } lboard_t; @@ -570,6 +581,10 @@ typedef struct klinfo_s { /* Generic info */ #define KLSTRUCT_USB 34 #define KLSTRUCT_USBKBD 35 #define KLSTRUCT_USBMS 36 +#define KLSTRUCT_SCSI_CTLR 37 +#define KLSTRUCT_PEBRICK 38 +#define KLSTRUCT_GIGE 39 +#define KLSTRUCT_IDE 40 /* * These are the indices of various components within a lboard structure. @@ -611,6 +626,9 @@ typedef struct klport_s { nasid_t port_nasid; unsigned char port_flag; klconf_off_t port_offset; +#ifdef CONFIG_IA64_SGI_SN2 + short port_num; +#endif } klport_t; typedef struct klcpu_s { /* CPU */ @@ -620,6 +638,9 @@ typedef struct klcpu_s { /* CPU */ unsigned short cpu_speed; /* Speed in MHZ */ unsigned short cpu_scachesz; /* secondary cache size in MB */ unsigned short cpu_scachespeed;/* secondary cache speed in MHz */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klcpu_t ; #define CPU_STRUCT_VERSION 2 @@ -627,16 +648,28 @@ typedef struct klcpu_s { /* CPU */ typedef struct klhub_s { /* HUB */ klinfo_t hub_info; uint hub_flags; /* PCFG_HUB_xxx flags */ +#ifdef CONFIG_IA64_SGI_SN2 +#define MAX_NI_PORTS 2 + klport_t hub_port[MAX_NI_PORTS + 1];/* hub is connected to this */ +#else klport_t hub_port; /* hub is connected to this */ +#endif nic_t hub_box_nic; /* nic of containing box */ klconf_off_t hub_mfg_nic; /* MFG NIC string */ u64 hub_speed; /* Speed of hub in HZ */ +#ifdef CONFIG_IA64_SGI_SN2 + moduleid_t hub_io_module; /* attached io module */ + unsigned long pad; +#endif } klhub_t ; typedef struct klhub_uart_s { /* HUB */ klinfo_t hubuart_info; uint hubuart_flags; /* PCFG_HUB_xxx flags */ nic_t hubuart_box_nic; /* nic of containing box */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klhub_uart_t ; #define MEMORY_STRUCT_VERSION 2 @@ -647,6 +680,9 @@ typedef struct klmembnk_s { /* MEMORY BANK */ short membnk_dimm_select; /* bank to physical addr mapping*/ short membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */ short membnk_attr; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klmembnk_t ; #define KLCONFIG_MEMBNK_SIZE(_info, _bank) \ @@ -665,6 +701,9 @@ typedef struct klmod_serial_num_s { char snum_str[MAX_SERIAL_NUM_SIZE]; unsigned long long snum_int; } snum; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klmod_serial_num_t; /* Macros needed to access serial number structure in lboard_t. @@ -682,6 +721,9 @@ typedef struct klxbow_s { /* XBOW */ klport_t xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */ int xbow_master_hub_link; /* type of brd connected+component struct ptr+flags */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klxbow_t ; #define MAX_PCI_SLOTS 8 @@ -700,6 +742,9 @@ typedef struct klbri_s { /* BRIDGE */ pci_t pci_specific ; /* PCI Board config info */ klpci_device_t bri_devices[MAX_PCI_DEVS] ; /* PCI IDs */ klconf_off_t bri_mfg_nic ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klbri_t ; #define MAX_IOC3_TTY 2 @@ -713,6 +758,9 @@ typedef struct klioc3_s { /* IOC3 */ klinfo_t ioc3_enet ; klconf_off_t ioc3_enet_off ; klconf_off_t ioc3_kbd_off ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klioc3_t ; #define MAX_VME_SLOTS 8 @@ -721,12 +769,18 @@ typedef struct klvmeb_s { /* VME BRIDGE - PCI CTLR */ klinfo_t vmeb_info ; vmeb_t vmeb_specific ; klconf_off_t vmeb_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klvmeb_t ; typedef struct klvmed_s { /* VME DEVICE - VME BOARD */ klinfo_t vmed_info ; vmed_t vmed_specific ; klconf_off_t vmed_brdinfo[MAX_VME_SLOTS] ; /* VME Board config info */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klvmed_t ; #define ROUTER_VECTOR_VERS 2 @@ -739,6 +793,9 @@ typedef struct klrou_s { /* ROUTER */ klport_t rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */ klconf_off_t rou_mfg_nic ; /* MFG NIC string */ u64 rou_vector; /* vector from master node */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klrou_t ; /* @@ -763,16 +820,25 @@ typedef struct klgfx_s { /* GRAPHICS Device */ graphics_t gfx_specific; klconf_off_t pad0; /* for compatibility with older proms */ klconf_off_t gfx_mfg_nic; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klgfx_t; typedef struct klxthd_s { klinfo_t xthd_info ; klconf_off_t xthd_mfg_nic ; /* MFG NIC string */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klxthd_t ; typedef struct kltpu_s { /* TPU board */ klinfo_t tpu_info ; klconf_off_t tpu_mfg_nic ; /* MFG NIC string */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } kltpu_t ; typedef struct klgsn_s { /* GSN board */ @@ -789,36 +855,64 @@ typedef struct klgsn_s { /* GSN board */ * that as the size to be klmalloced. */ -typedef struct klscsi_s { /* SCSI Controller */ +typedef struct klscsi_s { /* SCSI Bus */ klinfo_t scsi_info ; scsi_t scsi_specific ; unsigned char scsi_numdevs ; klconf_off_t scsi_devinfo[MAX_SCSI_DEVS] ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klscsi_t ; +typedef struct klscctl_s { /* SCSI Controller */ + klinfo_t scsi_info ; + uint type; + uint scsi_buscnt; /* # busses this cntlr */ + void *scsi_bus[2]; /* Pointer to 2 klscsi_t's */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif +} klscctl_t ; + typedef struct klscdev_s { /* SCSI device */ klinfo_t scdev_info ; struct scsidisk_data *scdev_cfg ; /* driver fills up this */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klscdev_t ; typedef struct klttydev_s { /* TTY device */ klinfo_t ttydev_info ; struct terminal_data *ttydev_cfg ; /* driver fills up this */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klttydev_t ; typedef struct klenetdev_s { /* ENET device */ klinfo_t enetdev_info ; struct net_data *enetdev_cfg ; /* driver fills up this */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klenetdev_t ; typedef struct klkbddev_s { /* KBD device */ klinfo_t kbddev_info ; struct keyboard_data *kbddev_cfg ; /* driver fills up this */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klkbddev_t ; typedef struct klmsdev_s { /* mouse device */ klinfo_t msdev_info ; void *msdev_cfg ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klmsdev_t ; #define MAX_FDDI_DEVS 10 /* XXX Is this true */ @@ -827,11 +921,17 @@ typedef struct klfddi_s { /* FDDI */ klinfo_t fddi_info ; fddi_t fddi_specific ; klconf_off_t fddi_devinfo[MAX_FDDI_DEVS] ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klfddi_t ; typedef struct klmio_s { /* MIO */ klinfo_t mio_info ; mio_t mio_specific ; +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klmio_t ; /* @@ -842,6 +942,9 @@ typedef struct klusb_s { klinfo_t usb_info; /* controller info */ void *usb_bus; /* handle to usb_bus_t */ uint64_t usb_controller; /* ptr to controller info */ +#ifdef CONFIG_IA64_SGI_SN2 + unsigned long pad; +#endif } klusb_t ; typedef union klcomp_s { @@ -856,6 +959,7 @@ typedef union klcomp_s { klrou_t kc_rou; klgfx_t kc_gfx; klscsi_t kc_scsi; + klscctl_t kc_scsi_ctl; klscdev_t kc_scsi_dev; klfddi_t kc_fddi; klmio_t kc_mio; @@ -929,26 +1033,38 @@ extern devfs_handle_t nodevertex_xbow_peer_get(devfs_handle_t node_vtx); extern lboard_t *find_gfxpipe(int pipenum); extern void setup_gfxpipe_link(devfs_handle_t vhdl,int pipenum); extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class); +#ifdef CONFIG_IA64_SGI_SN2 +extern lboard_t *find_lboard_module_class(lboard_t *start, geoid_t geoid, + unsigned char brd_class); +#else extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod, unsigned char brd_class); +#endif extern lboard_t *find_nic_lboard(lboard_t *, nic_t); extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t); +#ifdef CONFIG_IA64_SGI_SN2 +extern lboard_t *find_lboard_modslot(lboard_t *start, geoid_t geoid); +extern lboard_t *find_lboard_module(lboard_t *start, geoid_t geoid); +extern lboard_t *get_board_name(nasid_t nasid, geoid_t geoid, slotid_t slot, char *name); +#else extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot); extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod); extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name); +#endif extern int config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**); extern int config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**); extern int config_find_xbow(nasid_t, lboard_t **, klxbow_t**); extern int update_klcfg_cpuinfo(nasid_t, int); extern void board_to_path(lboard_t *brd, char *path); +#ifdef CONFIG_IA64_SGI_SN2 extern moduleid_t get_module_id(nasid_t nasid); +#endif extern void nic_name_convert(char *old_name, char *new_name); extern int module_brds(nasid_t nasid, lboard_t **module_brds, int n); extern lboard_t *brd_from_key(uint64_t key); extern void device_component_canonical_name_get(lboard_t *,klinfo_t *, char *); extern int board_serial_number_get(lboard_t *,char *); -extern int is_master_baseio(nasid_t,moduleid_t,slotid_t); extern nasid_t get_actual_nasid(lboard_t *brd) ; extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int); diff --git a/include/asm-ia64/sn/ksys/elsc.h b/include/asm-ia64/sn/ksys/elsc.h index bfe6430a93d3..40ba043febb6 100644 --- a/include/asm-ia64/sn/ksys/elsc.h +++ b/include/asm-ia64/sn/ksys/elsc.h @@ -9,8 +9,11 @@ #ifndef _ASM_SN_KSYS_ELSC_H #define _ASM_SN_KSYS_ELSC_H +#include <linux/config.h> #include <asm/sn/ksys/l1.h> +#ifdef CONFIG_IA64_SGI_SN1 + #define ELSC_ACP_MAX 86 /* 84+cr+lf */ #define ELSC_LINE_MAX (ELSC_ACP_MAX - 2) @@ -73,7 +76,6 @@ int elsc_power_down(elsc_t *e, int sec); int elsc_power_cycle(elsc_t *e); int elsc_system_reset(elsc_t *e); int elsc_dip_switches(elsc_t *e); -int elsc_nic_get(elsc_t *e, uint64_t *nic, int verbose); int _elsc_hbt(elsc_t *e, int ival, int rdly); @@ -83,6 +85,9 @@ int _elsc_hbt(elsc_t *e, int ival, int rdly); elsc_t *get_elsc(void); +#endif /* CONFIG_IA64_SGI_SN1 */ + + /* * Error codes * diff --git a/include/asm-ia64/sn/ksys/l1.h b/include/asm-ia64/sn/ksys/l1.h index f4b3fe5b80fe..d3f1be065547 100644 --- a/include/asm-ia64/sn/ksys/l1.h +++ b/include/asm-ia64/sn/ksys/l1.h @@ -10,11 +10,15 @@ #ifndef _ASM_SN_KSYS_L1_H #define _ASM_SN_KSYS_L1_H +#include <linux/config.h> #include <asm/sn/vector.h> #include <asm/sn/addrs.h> #include <asm/atomic.h> #include <asm/sn/sv.h> + +#ifdef CONFIG_IA64_SGI_SN1 + #define BRL1_QSIZE 128 /* power of 2 is more efficient */ #define BRL1_BUFSZ 264 /* needs to be large enough * to hold 2 flags, escaped @@ -109,8 +113,6 @@ typedef struct brl1_sch_s { #define BRL1_RESET 7 -#ifndef __ASSEMBLY__ - /* * l1sc_t structure-- tracks protocol state, open subchannels, etc. */ @@ -148,7 +150,6 @@ typedef struct l1sc_s { sc_cq_t garbage_q; /* a place to put unsolicited packets */ sc_cq_t oq[BRL1_OQS]; /* elscuart output queues */ - } l1sc_t; @@ -169,6 +170,7 @@ typedef struct l1sc_s { #define SC_TIMEDOUT (-9) #define SC_NSUBCH (-10) +#endif /* CONFIG_IA64_SGI_SN1 */ /* L1 Target Addresses */ /* @@ -179,21 +181,38 @@ typedef struct l1sc_s { * id (L1 functionality is divided into several independent "tasks" * that can each receive command requests and transmit responses) */ +#ifdef CONFIG_IA64_SGI_SN1 #define L1_ADDR_TYPE_SHFT 28 #define L1_ADDR_TYPE_MASK 0xF0000000 +#else +#define L1_ADDR_TYPE_SHFT 8 +#define L1_ADDR_TYPE_MASK 0xFF00 +#endif /* CONFIG_IA64_SGI_SN1 */ #define L1_ADDR_TYPE_L1 0x00 /* L1 system controller */ #define L1_ADDR_TYPE_L2 0x01 /* L2 system controller */ #define L1_ADDR_TYPE_L3 0x02 /* L3 system controller */ #define L1_ADDR_TYPE_CBRICK 0x03 /* attached C brick */ #define L1_ADDR_TYPE_IOBRICK 0x04 /* attached I/O brick */ +#ifdef CONFIG_IA64_SGI_SN1 #define L1_ADDR_RACK_SHFT 18 #define L1_ADDR_RACK_MASK 0x0FFC0000 #define L1_ADDR_RACK_LOCAL 0x3ff /* local brick's rack */ +#else +#define L1_ADDR_RACK_SHFT 16 +#define L1_ADDR_RACK_MASK 0xFFFF00 +#define L1_ADDR_RACK_LOCAL 0xffff /* local brick's rack */ +#endif /* CONFIG_IA64_SGI_SN1 */ +#ifdef CONFIG_IA64_SGI_SN1 #define L1_ADDR_BAY_SHFT 12 #define L1_ADDR_BAY_MASK 0x0003F000 #define L1_ADDR_BAY_LOCAL 0x3f /* local brick's bay */ +#else +#define L1_ADDR_BAY_SHFT 0 +#define L1_ADDR_BAY_MASK 0xFF +#define L1_ADDR_BAY_LOCAL 0xff /* local brick's bay */ +#endif /* CONFIG_IA64_SGI_SN1 */ #define L1_ADDR_TASK_SHFT 0 #define L1_ADDR_TASK_MASK 0x0000001F @@ -268,13 +287,16 @@ typedef struct l1sc_s { #define L1_REQ_EXEC_CMD 0x0000 /* interpret and execute an ASCII command string */ - /* brick type response codes */ -#define L1_BRICKTYPE_C 0x43 -#define L1_BRICKTYPE_I 0x49 -#define L1_BRICKTYPE_P 0x50 -#define L1_BRICKTYPE_R 0x52 -#define L1_BRICKTYPE_X 0x58 +#define L1_BRICKTYPE_IP45 0x34 /* 4 */ +#define L1_BRICKTYPE_C 0x43 /* C */ +#define L1_BRICKTYPE_I 0x49 /* I */ +#define L1_BRICKTYPE_P 0x50 /* P */ +#define L1_BRICKTYPE_R 0x52 /* R */ +#define L1_BRICKTYPE_X 0x58 /* X */ +#define L1_BRICKTYPE_X2 0x59 /* Y */ +#define L1_BRICKTYPE_N 0x4e /* N */ +#define L1_BRICKTYPE_PX 0x23 /* # */ /* EEPROM codes (for the "read EEPROM" request) */ /* c brick */ @@ -306,7 +328,6 @@ typedef uint32_t l1addr_t; (*(l1addr_t *)(addr) = (l1addr_t)(trb) | \ ((l1addr_t)(tsk) << L1_ADDR_TASK_SHFT)) - #define L1_DISPLAY_LINE_LENGTH 12 /* L1 display characters/line */ #ifdef L1_DISP_2LINES @@ -316,10 +337,12 @@ typedef uint32_t l1addr_t; * to system software */ #endif -#define SC_EVENT_CLASS_MASK ((unsigned short)0xff00) - #define bzero(d, n) memset((d), 0, (n)) +#ifdef CONFIG_IA64_SGI_SN1 + +#define SC_EVENT_CLASS_MASK ((unsigned short)0xff00) + /* public interfaces to L1 system controller */ int sc_open( l1sc_t *sc, uint target ); @@ -348,15 +371,18 @@ extern l1sc_t *get_elsc( void ); #define get_l1sc get_elsc #define get_master_l1sc get_l1sc -int router_module_get( nasid_t nasid, net_vec_t path ); - int iobrick_rack_bay_type_get( l1sc_t *sc, uint *rack, uint *bay, uint *brick_type ); int iobrick_module_get( l1sc_t *sc ); int iobrick_pci_slot_pwr( l1sc_t *sc, int bus, int slot, int up ); int iobrick_pci_bus_pwr( l1sc_t *sc, int bus, int up ); int iobrick_sc_version( l1sc_t *sc, char *result ); +#else +int elsc_display_line(nasid_t nasid, char *line, int lnum); +int iobrick_rack_bay_type_get( nasid_t nasid, uint *rack, + uint *bay, uint *brick_type ); +int iobrick_module_get( nasid_t nasid ); +#endif /* CONFIG_IA64_SGI_SN1 */ -#endif /* !__ASSEMBLY__ */ #endif /* _ASM_SN_KSYS_L1_H */ diff --git a/include/asm-ia64/sn/leds.h b/include/asm-ia64/sn/leds.h index 7e87077d3ee6..040b117f4b6c 100644 --- a/include/asm-ia64/sn/leds.h +++ b/include/asm-ia64/sn/leds.h @@ -5,7 +5,7 @@ * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. - * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved. */ #include <linux/config.h> @@ -15,7 +15,7 @@ #include <asm/sn/pda.h> #ifdef CONFIG_IA64_SGI_SN1 -#define LED0 0xc0000b00100000c0LL /* ZZZ fixme */ +#define LED0 0xc0000b00100000c0LL #define LED_CPU_SHIFT 3 #else #include <asm/sn/sn2/shub.h> @@ -25,7 +25,13 @@ #define LED_CPU_HEARTBEAT 0x01 #define LED_CPU_ACTIVITY 0x02 +#ifdef LED_WAR +#define LED_ALWAYS_SET 0x64 /* SN2 hw workaround: always set 0x60 */ +#define LED_MASK_AUTOTEST 0x9e +#else /* LED_WAR */ +#define LED_ALWAYS_SET 0x00 #define LED_MASK_AUTOTEST 0xfe +#endif /* LED_WAR */ /* * Basic macros for flashing the LEDS on an SGI, SN1. @@ -34,8 +40,14 @@ static __inline__ void set_led_bits(u8 value, u8 mask) { +#if 0 pda.led_state = (pda.led_state & ~mask) | (value & mask); +#ifdef CONFIG_IA64_SGI_SN1 *pda.led_address = (long) pda.led_state; +#else + *pda.led_address = (short) pda.led_state; +#endif +#endif } #endif /* _ASM_IA64_SN_LEDS_H */ diff --git a/include/asm-ia64/sn/module.h b/include/asm-ia64/sn/module.h index 18481374b2a8..fa9bbf4023ac 100644 --- a/include/asm-ia64/sn/module.h +++ b/include/asm-ia64/sn/module.h @@ -13,12 +13,13 @@ extern "C" { #endif +#include <linux/config.h> #include <asm/sn/systeminfo.h> #include <asm/sn/klconfig.h> #include <asm/sn/ksys/elsc.h> #define MODULE_MAX 128 -#define MODULE_MAX_NODES 1 +#define MODULE_MAX_NODES 2 #define MODULE_HIST_CNT 16 #define MAX_MODULE_LEN 16 @@ -32,6 +33,127 @@ extern "C" { #define MODULE_FORMAT_LONG 2 +#ifdef CONFIG_IA64_SGI_SN2 + +/* + * Module id format + * + * 31-16 Rack ID (encoded class, group, number - 16-bit unsigned int) + * 15-8 Brick type (8-bit ascii character) + * 7-0 Bay (brick position in rack (0-63) - 8-bit unsigned int) + * + */ + +/* + * Macros for getting the brick type + */ +#define MODULE_BTYPE_MASK 0xff00 +#define MODULE_BTYPE_SHFT 8 +#define MODULE_GET_BTYPE(_m) (((_m) & MODULE_BTYPE_MASK) >> MODULE_BTYPE_SHFT) +#define MODULE_BT_TO_CHAR(_b) ((char)(_b)) +#define MODULE_GET_BTCHAR(_m) (MODULE_BT_TO_CHAR(MODULE_GET_BTYPE(_m))) + +/* + * Macros for getting the rack ID. + */ +#define MODULE_RACK_MASK 0xffff0000 +#define MODULE_RACK_SHFT 16 +#define MODULE_GET_RACK(_m) (((_m) & MODULE_RACK_MASK) >> MODULE_RACK_SHFT) + +/* + * Macros for getting the brick position + */ +#define MODULE_BPOS_MASK 0x00ff +#define MODULE_BPOS_SHFT 0 +#define MODULE_GET_BPOS(_m) (((_m) & MODULE_BPOS_MASK) >> MODULE_BPOS_SHFT) + +/* + * Macros for constructing moduleid_t's + */ +#define RBT_TO_MODULE(_r, _b, _t) ((_r) << MODULE_RACK_SHFT | \ + (_b) << MODULE_BPOS_SHFT | \ + (_t) << MODULE_BTYPE_SHFT) + +/* + * Macros for encoding and decoding rack IDs + * A rack number consists of three parts: + * class (0==CPU/mixed, 1==I/O), group, number + * + * Rack number is stored just as it is displayed on the screen: + * a 3-decimal-digit number. + */ +#define RACK_CLASS_DVDR 100 +#define RACK_GROUP_DVDR 10 +#define RACK_NUM_DVDR 1 + +#define RACK_CREATE_RACKID(_c, _g, _n) ((_c) * RACK_CLASS_DVDR + \ + (_g) * RACK_GROUP_DVDR + (_n) * RACK_NUM_DVDR) + +#define RACK_GET_CLASS(_r) ((_r) / RACK_CLASS_DVDR) +#define RACK_GET_GROUP(_r) (((_r) - RACK_GET_CLASS(_r) * \ + RACK_CLASS_DVDR) / RACK_GROUP_DVDR) +#define RACK_GET_NUM(_r) (((_r) - RACK_GET_CLASS(_r) * \ + RACK_CLASS_DVDR - RACK_GET_GROUP(_r) * \ + RACK_GROUP_DVDR) / RACK_NUM_DVDR) + +/* + * Macros for encoding and decoding rack IDs + * A rack number consists of three parts: + * class 1 bit, 0==CPU/mixed, 1==I/O + * group 2 bits for CPU/mixed, 3 bits for I/O + * number 3 bits for CPU/mixed, 2 bits for I/O (1 based) + */ +#define RACK_GROUP_BITS(_r) (RACK_GET_CLASS(_r) ? 3 : 2) +#define RACK_NUM_BITS(_r) (RACK_GET_CLASS(_r) ? 2 : 3) + +#define RACK_CLASS_MASK(_r) 0x20 +#define RACK_CLASS_SHFT(_r) 5 +#define RACK_ADD_CLASS(_r, _c) \ + ((_r) |= (_c) << RACK_CLASS_SHFT(_r) & RACK_CLASS_MASK(_r)) + +#define RACK_GROUP_SHFT(_r) RACK_NUM_BITS(_r) +#define RACK_GROUP_MASK(_r) \ + ( (((unsigned)1<<RACK_GROUP_BITS(_r)) - 1) << RACK_GROUP_SHFT(_r) ) +#define RACK_ADD_GROUP(_r, _g) \ + ((_r) |= (_g) << RACK_GROUP_SHFT(_r) & RACK_GROUP_MASK(_r)) + +#define RACK_NUM_SHFT(_r) 0 +#define RACK_NUM_MASK(_r) \ + ( (((unsigned)1<<RACK_NUM_BITS(_r)) - 1) << RACK_NUM_SHFT(_r) ) +#define RACK_ADD_NUM(_r, _n) \ + ((_r) |= ((_n) - 1) << RACK_NUM_SHFT(_r) & RACK_NUM_MASK(_r)) + + +/* + * Brick type definitions + */ +#define MAX_BRICK_TYPES 256 /* brick type is stored as uchar */ + +extern char brick_types[]; + +#define MODULE_CBRICK 0 +#define MODULE_RBRICK 1 +#define MODULE_IBRICK 2 +#define MODULE_KBRICK 3 +#define MODULE_XBRICK 4 +#define MODULE_DBRICK 5 +#define MODULE_PBRICK 6 +#define MODULE_NBRICK 7 +#define MODULE_PEBRICK 8 +#define MODULE_PXBRICK 9 + +/* + * Moduleid_t comparison macros + */ +/* Don't compare the brick type: only the position is significant */ +#define MODULE_CMP(_m1, _m2) (((_m1)&(MODULE_RACK_MASK|MODULE_BPOS_MASK)) -\ + ((_m2)&(MODULE_RACK_MASK|MODULE_BPOS_MASK))) +#define MODULE_MATCH(_m1, _m2) (MODULE_CMP((_m1),(_m2)) == 0) + + +#else +#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) + /* * Module id format * @@ -116,6 +238,9 @@ extern char brick_types[]; #define MODULE_XBRICK 4 #define MODULE_DBRICK 5 #define MODULE_PBRICK 6 +#define MODULE_NBRICK 7 +#define MODULE_PEBRICK 8 +#define MODULE_PXBRICK 9 /* * Moduleid_t comparison macros @@ -125,6 +250,18 @@ extern char brick_types[]; ((_m2)&(MODULE_RACK_MASK|MODULE_BPOS_MASK))) #define MODULE_MATCH(_m1, _m2) (MODULE_CMP((_m1),(_m2)) == 0) +#else + +/* + * Some code that uses this macro will not be conditionally compiled. + */ +#define MODULE_GET_BTCHAR(_m) ('?') +#define MODULE_CMP(_m1, _m2) ((_m1) - (_m2)) +#define MODULE_MATCH(_m1, _m2) (MODULE_CMP((_m1),(_m2)) == 0) + +#endif /* SN1 */ +#endif /* SN2 */ + typedef struct module_s module_t; struct module_s { @@ -134,6 +271,9 @@ struct module_s { /* List of nodes in this module */ cnodeid_t nodes[MODULE_MAX_NODES]; +#ifdef CONFIG_IA64_SGI_SN2 + geoid_t geoid[MODULE_MAX_NODES]; +#endif int nodecnt; /* Number of nodes in array */ /* Fields for Module System Controller */ @@ -141,9 +281,10 @@ struct module_s { int shutdown; /* Shutdown in progress */ struct semaphore thdcnt; /* Threads finished counter */ +#ifdef CONFIG_IA64_SGI_SN1 elsc_t elsc; spinlock_t elsclock; - +#endif time_t intrhist[MODULE_HIST_CNT]; int histptr; @@ -171,7 +312,9 @@ extern int nummodules; extern module_t *module_lookup(moduleid_t id); +#if defined(CONFIG_IA64_SGI_SN1) extern elsc_t *get_elsc(void); +#endif extern int get_kmod_info(cmoduleid_t cmod, module_info_t *mod_info); diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h index b999dbd8451d..f9aa614ddb17 100644 --- a/include/asm-ia64/sn/nodepda.h +++ b/include/asm-ia64/sn/nodepda.h @@ -70,7 +70,11 @@ struct nodepda_s { nasid_t xbow_peer; /* NASID of our peer hub on xbow */ struct semaphore xbow_sema; /* Sema for xbow synchronization */ slotid_t slotdesc; +#ifdef CONFIG_IA64_SGI_SN2 + geoid_t geoid; +#else moduleid_t module_id; /* Module ID (redundant local copy) */ +#endif module_t *module; /* Pointer to containing module */ xwidgetnum_t basew_id; devfs_handle_t basew_xc; @@ -91,7 +95,8 @@ struct nodepda_s { /* * The BTEs on this node are shared by the local cpus */ - bteinfo_t node_bte_info[BTES_PER_NODE]; + bteinfo_t bte_if[BTES_PER_NODE]; /* Virtual Interface */ + char bte_cleanup[5 * L1_CACHE_BYTES] ____cacheline_aligned; #if defined(CONFIG_IA64_SGI_SN1) subnode_pda_t snpda[NUM_SUBNODES]; @@ -122,9 +127,10 @@ struct nodepda_s { typedef struct nodepda_s nodepda_t; #ifdef CONFIG_IA64_SGI_SN2 +#define NR_IVECS 256 struct irqpda_s { int num_irq_used; - char irq_flags[NR_IRQS]; + char irq_flags[NR_IVECS]; }; typedef struct irqpda_s irqpda_t; @@ -147,7 +153,7 @@ typedef struct irqpda_s irqpda_t; * SUBNODEPDA(cnode,sn) -> to access subnode PDA for cnodeid/subnode */ -#define nodepda pda.p_nodepda /* Ptr to this node's PDA */ +#define nodepda pda->p_nodepda /* Ptr to this node's PDA */ #define NODEPDA(cnode) (nodepda->pernode_pdaindr[cnode]) #if defined(CONFIG_IA64_SGI_SN1) @@ -160,7 +166,11 @@ typedef struct irqpda_s irqpda_t; /* * Macros to access data structures inside nodepda */ +#ifdef CONFIG_IA64_SGI_SN2 +#define NODE_MODULEID(cnode) geo_module((NODEPDA(cnode)->geoid)) +#else #define NODE_MODULEID(cnode) (NODEPDA(cnode)->module_id) +#endif #define NODE_SLOTID(cnode) (NODEPDA(cnode)->slotdesc) @@ -174,8 +184,8 @@ typedef struct irqpda_s irqpda_t; * Check if given a compact node id the corresponding node has all the * cpus disabled. */ -#define is_headless_node(cnode) ((cnode == CNODEID_NONE) || \ - (node_data(cnode)->active_cpu_count == 0)) +#define is_headless_node(cnode) 0 /*((cnode == CNODEID_NONE) || \ + (node_data(cnode)->active_cpu_count == 0)) */ /* * Check if given a node vertex handle the corresponding node has all the diff --git a/include/asm-ia64/sn/pci/bridge.h b/include/asm-ia64/sn/pci/bridge.h index 4982e75f0107..9c77bcb26b46 100644 --- a/include/asm-ia64/sn/pci/bridge.h +++ b/include/asm-ia64/sn/pci/bridge.h @@ -12,9 +12,40 @@ /* * bridge.h - header file for bridge chip and bridge portion of xbridge chip + * + * Also including offsets for unique PIC registers. + * The PIC asic is a follow-on to Xbridge and most of it's registers are + * identical to those of Xbridge. PIC is different than Xbridge in that + * it will accept 64 bit register access and that, in some cases, data + * is kept in bits 63:32. PIC registers that are identical to Xbridge + * may be accessed identically to the Xbridge registers, allowing for lots + * of code reuse. Here are the access rules as described in the PIC + * manual: + * + * o Read a word on a DW boundary returns D31:00 of reg. + * o Read a DW on a DW boundary returns D63:00 of reg. + * o Write a word on a DW boundary loads D31:00 of reg. + * o Write a DW on a DW boundary loads D63:00 of reg. + * o No support for word boundary access that is not double word + * aligned. + * + * So we can reuse a lot of bridge_s for PIC. In bridge_s are included + * #define tags and unions for 64 bit access to PIC registers. + * For a detailed PIC register layout see pic.h. */ +#include <linux/config.h> #include <asm/sn/xtalk/xwidget.h> +#ifndef CONFIG_IA64_SGI_SN1 +#include <asm/sn/pci/pic.h> + +extern int io_get_sh_swapper(nasid_t); +#define BRIDGE_REG_GET32(reg) \ + __swab32( *(volatile uint32_t *) (((uint64_t)reg)^4) ) + +#define BRIDGE_REG_SET32(reg) \ + *(volatile uint32_t *) (((uint64_t)reg)^4) +#endif /* CONFIG_IA64_SGI_SN1 */ /* I/O page size */ @@ -36,6 +67,8 @@ #define BRIDGE_ATE_RAM_SIZE (BRIDGE_INTERNAL_ATES<<3) /* 1kB ATE */ #define XBRIDGE_ATE_RAM_SIZE (XBRIDGE_INTERNAL_ATES<<3) /* 8kB ATE */ +#define PIC_WR_REQ_BUFSIZE 256 + #define BRIDGE_CONFIG_BASE 0x20000 /* start of bridge's */ /* map to each device's */ /* config space */ @@ -78,7 +111,502 @@ typedef volatile bridge_ate_t *bridge_ate_p; * Generated from Bridge spec dated 04oct95 */ -#ifdef LITTLE_ENDIAN +#ifndef CONFIG_IA64_SGI_SN1 + +/* + * pic_widget_cfg_s is a local definition of widget_cfg_t but with + * a union of 64bit & 32bit registers, since PIC has 64bit widget + * registers but BRIDGE and XBRIDGE have 32bit. PIC registers that + * have valid bits (ie. not just reserved) in the upper 32bits are + * defined as a union so we can access them as 64bit for PIC and + * as 32bit for BRIDGE and XBRIDGE. + */ +typedef volatile struct pic_widget_cfg_s { + bridgereg_t _b_wid_id; /* 0x000004 */ + bridgereg_t _pad_000000; + + union { + picreg_t _p_wid_stat; /* 0x000008 */ + struct { + bridgereg_t _b_wid_stat; /* 0x00000C */ + bridgereg_t _b_pad_000008; + } _b; + } u_wid_stat; + #define __p_wid_stat_64 u_wid_stat._p_wid_stat + #define __b_wid_stat u_wid_stat._b._b_wid_stat + + bridgereg_t _b_wid_err_upper; /* 0x000014 */ + bridgereg_t _pad_000010; + + union { + picreg_t _p_wid_err_lower; /* 0x000018 */ + struct { + bridgereg_t _b_wid_err_lower; /* 0x00001C */ + bridgereg_t _b_pad_000018; + } _b; + } u_wid_err_lower; + #define __p_wid_err_64 u_wid_err_lower._p_wid_err_lower + #define __b_wid_err_lower u_wid_err_lower._b._b_wid_err_lower + + union { + picreg_t _p_wid_control; /* 0x000020 */ + struct { + bridgereg_t _b_wid_control; /* 0x000024 */ + bridgereg_t _b_pad_000020; + } _b; + } u_wid_control; + #define __p_wid_control_64 u_wid_control._p_wid_control + #define __b_wid_control u_wid_control._b._b_wid_control + + bridgereg_t _b_wid_req_timeout; /* 0x00002C */ + bridgereg_t _pad_000028; + + bridgereg_t _b_wid_int_upper; /* 0x000034 */ + bridgereg_t _pad_000030; + + union { + picreg_t _p_wid_int_lower; /* 0x000038 */ + struct { + bridgereg_t _b_wid_int_lower; /* 0x00003C */ + bridgereg_t _b_pad_000038; + } _b; + } u_wid_int_lower; + #define __p_wid_int_64 u_wid_int_lower._p_wid_int_lower + #define __b_wid_int_lower u_wid_int_lower._b._b_wid_int_lower + + bridgereg_t _b_wid_err_cmdword; /* 0x000044 */ + bridgereg_t _pad_000040; + + bridgereg_t _b_wid_llp; /* 0x00004C */ + bridgereg_t _pad_000048; + + bridgereg_t _b_wid_tflush; /* 0x000054 */ + bridgereg_t _pad_000050; +} pic_widget_cfg_t; + +/* + * BRIDGE, XBRIDGE, PIC register definitions. NOTE: Prior to PIC, registers + * were a 32bit quantity and double word aligned (and only accessable as a + * 32bit word. PIC registers are 64bits and accessable as words or double + * words. PIC registers that have valid bits (ie. not just reserved) in the + * upper 32bits are defined as a union of one 64bit picreg_t and two 32bit + * bridgereg_t so we can access them both ways. + * + * It is generally preferred that hardware registers on the bridge are + * located from C code via this structure. + * + * Generated from Bridge spec dated 04oct95 + */ + +typedef volatile struct bridge_s { + + /* 0x000000-0x00FFFF -- Local Registers */ + + /* 0x000000-0x000057 -- Standard Widget Configuration */ + union { + widget_cfg_t xtalk_widget_def; /* 0x000000 */ + pic_widget_cfg_t local_widget_def; /* 0x000000 */ + } u_wid; + + /* 32bit widget register access via the widget_cfg_t */ + #define b_widget u_wid.xtalk_widget_def + + /* 32bit widget register access via the pic_widget_cfg_t */ + #define b_wid_id u_wid.local_widget_def._b_wid_id + #define b_wid_stat u_wid.local_widget_def.__b_wid_stat + #define b_wid_err_upper u_wid.local_widget_def._b_wid_err_upper + #define b_wid_err_lower u_wid.local_widget_def.__b_wid_err_lower + #define b_wid_control u_wid.local_widget_def.__b_wid_control + #define b_wid_req_timeout u_wid.local_widget_def._b_wid_req_timeout + #define b_wid_int_upper u_wid.local_widget_def._b_wid_int_upper + #define b_wid_int_lower u_wid.local_widget_def.__b_wid_int_lower + #define b_wid_err_cmdword u_wid.local_widget_def._b_wid_err_cmdword + #define b_wid_llp u_wid.local_widget_def._b_wid_llp + #define b_wid_tflush u_wid.local_widget_def._b_wid_tflush + + /* 64bit widget register access via the pic_widget_cfg_t */ + #define p_wid_stat_64 u_wid.local_widget_def.__p_wid_stat_64 + #define p_wid_err_64 u_wid.local_widget_def.__p_wid_err_64 + #define p_wid_control_64 u_wid.local_widget_def.__p_wid_control_64 + #define p_wid_int_64 u_wid.local_widget_def.__p_wid_int_64 + + /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */ + bridgereg_t b_wid_aux_err; /* 0x00005C */ + bridgereg_t _pad_000058; + + bridgereg_t b_wid_resp_upper; /* 0x000064 */ + bridgereg_t _pad_000060; + + union { + picreg_t _p_wid_resp_lower; /* 0x000068 */ + struct { + bridgereg_t _b_wid_resp_lower; /* 0x00006C */ + bridgereg_t _b_pad_000068; + } _b; + } u_wid_resp_lower; + #define p_wid_resp_64 u_wid_resp_lower._p_wid_resp_lower + #define b_wid_resp_lower u_wid_resp_lower._b._b_wid_resp_lower + + bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ + bridgereg_t _pad_000070; + + union { + picreg_t _p_addr_lkerr; /* 0x000078 */ + struct { + bridgereg_t _b_pad_00007C; + bridgereg_t _b_pad_000078; + } _b; + } u_addr_lkerr; + #define p_addr_lkerr_64 u_addr_lkerr._p_addr_lkerr + + /* 0x000080-0x00008F -- PMU */ + bridgereg_t b_dir_map; /* 0x000084 */ + bridgereg_t _pad_000080; + + bridgereg_t _pad_00008C; + bridgereg_t _pad_000088; + + /* 0x000090-0x00009F -- SSRAM */ + bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ + bridgereg_t _pad_000090; + #define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ + #define b_map_fault b_ram_perr_or_map_fault /* Xbridge & PIC */ + + bridgereg_t _pad_00009C; + bridgereg_t _pad_000098; + + /* 0x0000A0-0x0000AF -- Arbitration */ + bridgereg_t b_arb; /* 0x0000A4 */ + bridgereg_t _pad_0000A0; + + bridgereg_t _pad_0000AC; + bridgereg_t _pad_0000A8; + + /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */ + union { + picreg_t _p_ate_parity_err; /* 0x0000B0 */ + struct { + bridgereg_t _b_nic; /* 0x0000B4 */ + bridgereg_t _b_pad_0000B0; + } _b; + } u_ate_parity_err_or_nic; + #define p_ate_parity_err_64 u_ate_parity_err_or_nic._p_ate_parity_err + #define b_nic u_ate_parity_err_or_nic._b._b_nic + + bridgereg_t _pad_0000BC; + bridgereg_t _pad_0000B8; + + /* 0x0000C0-0x0000FF -- PCI/GIO */ + bridgereg_t b_bus_timeout; /* 0x0000C4 */ + bridgereg_t _pad_0000C0; + #define b_pci_bus_timeout b_bus_timeout + + bridgereg_t b_pci_cfg; /* 0x0000CC */ + bridgereg_t _pad_0000C8; + + bridgereg_t b_pci_err_upper; /* 0x0000D4 */ + bridgereg_t _pad_0000D0; + #define b_gio_err_upper b_pci_err_upper + + union { + picreg_t _p_pci_err_lower; /* 0x0000D8 */ + struct { + bridgereg_t _b_pci_err_lower; /* 0x0000DC */ + bridgereg_t _b_pad_0000D8; + } _b; + } u_pci_err_lower; + #define p_pci_err_64 u_pci_err_lower._p_pci_err_lower + #define b_pci_err_lower u_pci_err_lower._b._b_pci_err_lower + #define b_gio_err_lower b_pci_err_lower + + bridgereg_t _pad_0000E0[8]; + + /* 0x000100-0x0001FF -- Interrupt */ + union { + picreg_t _p_int_status; /* 0x000100 */ + struct { + bridgereg_t _b_int_status; /* 0x000104 */ + bridgereg_t _b_pad_000100; + } _b; + } u_int_status; + #define p_int_status_64 u_int_status._p_int_status + #define b_int_status u_int_status._b._b_int_status + + union { + picreg_t _p_int_enable; /* 0x000108 */ + struct { + bridgereg_t _b_int_enable; /* 0x00010C */ + bridgereg_t _b_pad_000108; + } _b; + } u_int_enable; + #define p_int_enable_64 u_int_enable._p_int_enable + #define b_int_enable u_int_enable._b._b_int_enable + + union { + picreg_t _p_int_rst_stat; /* 0x000110 */ + struct { + bridgereg_t _b_int_rst_stat; /* 0x000114 */ + bridgereg_t _b_pad_000110; + } _b; + } u_int_rst_stat; + #define p_int_rst_stat_64 u_int_rst_stat._p_int_rst_stat + #define b_int_rst_stat u_int_rst_stat._b._b_int_rst_stat + + bridgereg_t b_int_mode; /* 0x00011C */ + bridgereg_t _pad_000118; + + bridgereg_t b_int_device; /* 0x000124 */ + bridgereg_t _pad_000120; + + bridgereg_t b_int_host_err; /* 0x00012C */ + bridgereg_t _pad_000128; + + union { + picreg_t _p_int_addr[8]; /* 0x0001{30,,,68} */ + struct { + bridgereg_t addr; /* 0x0001{34,,,6C} */ + bridgereg_t _b_pad; + } _b[8]; + } u_int_addr; + #define p_int_addr_64 u_int_addr._p_int_addr + #define b_int_addr u_int_addr._b + + union { + picreg_t _p_err_int_view; /* 0x000170 */ + struct { + bridgereg_t _b_err_int_view; /* 0x000174 */ + bridgereg_t _b_pad_000170; + } _b; + } u_err_int_view; + #define p_err_int_view_64 u_err_int_view._p_err_int_view + #define b_err_int_view u_err_int_view._b._b_err_int_view + + union { + picreg_t _p_mult_int; /* 0x000178 */ + struct { + bridgereg_t _b_mult_int; /* 0x00017C */ + bridgereg_t _b_pad_000178; + } _b; + } u_mult_int; + #define p_mult_int_64 u_mult_int._p_mult_int + #define b_mult_int u_mult_int._b._b_mult_int + + struct { + bridgereg_t intr; /* 0x0001{84,,,BC} */ + bridgereg_t __pad; + } b_force_always[8]; + + struct { + bridgereg_t intr; /* 0x0001{C4,,,FC} */ + bridgereg_t __pad; + } b_force_pin[8]; + + /* 0x000200-0x0003FF -- Device */ + struct { + bridgereg_t reg; /* 0x0002{04,,,3C} */ + bridgereg_t __pad; + } b_device[8]; + + struct { + bridgereg_t reg; /* 0x0002{44,,,7C} */ + bridgereg_t __pad; + } b_wr_req_buf[8]; + + struct { + bridgereg_t reg; /* 0x0002{84,,,8C} */ + bridgereg_t __pad; + } b_rrb_map[2]; + #define b_even_resp b_rrb_map[0].reg /* 0x000284 */ + #define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ + + bridgereg_t b_resp_status; /* 0x000294 */ + bridgereg_t _pad_000290; + + bridgereg_t b_resp_clear; /* 0x00029C */ + bridgereg_t _pad_000298; + + bridgereg_t _pad_0002A0[24]; + + /* Xbridge/PIC only */ + union { + struct { + picreg_t lower; /* 0x0003{08,,,F8} */ + picreg_t upper; /* 0x0003{00,,,F0} */ + } _p[16]; + struct { + bridgereg_t upper; /* 0x0003{04,,,F4} */ + bridgereg_t _b_pad1; + bridgereg_t lower; /* 0x0003{0C,,,FC} */ + bridgereg_t _b_pad2; + } _b[16]; + } u_buf_addr_match; + #define p_buf_addr_match_64 u_buf_addr_match._p + #define b_buf_addr_match u_buf_addr_match._b + + /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */ + struct { + bridgereg_t flush_w_touch; /* 0x000{404,,,5C4} */ + bridgereg_t __pad1; + bridgereg_t flush_wo_touch; /* 0x000{40C,,,5CC} */ + bridgereg_t __pad2; + bridgereg_t inflight; /* 0x000{414,,,5D4} */ + bridgereg_t __pad3; + bridgereg_t prefetch; /* 0x000{41C,,,5DC} */ + bridgereg_t __pad4; + bridgereg_t total_pci_retry; /* 0x000{424,,,5E4} */ + bridgereg_t __pad5; + bridgereg_t max_pci_retry; /* 0x000{42C,,,5EC} */ + bridgereg_t __pad6; + bridgereg_t max_latency; /* 0x000{434,,,5F4} */ + bridgereg_t __pad7; + bridgereg_t clear_all; /* 0x000{43C,,,5FC} */ + bridgereg_t __pad8; + } b_buf_count[8]; + + /* + * "PCI/X registers that are specific to PIC". See pic.h. + */ + + /* 0x000600-0x0009FF -- PCI/X registers */ + picreg_t p_pcix_bus_err_addr_64; /* 0x000600 */ + picreg_t p_pcix_bus_err_attr_64; /* 0x000608 */ + picreg_t p_pcix_bus_err_data_64; /* 0x000610 */ + picreg_t p_pcix_pio_split_addr_64; /* 0x000618 */ + picreg_t p_pcix_pio_split_attr_64; /* 0x000620 */ + picreg_t p_pcix_dma_req_err_attr_64; /* 0x000628 */ + picreg_t p_pcix_dma_req_err_addr_64; /* 0x000630 */ + picreg_t p_pcix_timeout_64; /* 0x000638 */ + + picreg_t _pad_000600[120]; + + /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */ + struct { + picreg_t p_buf_attr; /* 0X000{A08,,,AF8} */ + picreg_t p_buf_addr; /* 0x000{A00,,,AF0} */ + } p_pcix_read_buf_64[16]; + + struct { + picreg_t p_buf_attr; /* 0x000{B08,,,BE8} */ + picreg_t p_buf_addr; /* 0x000{B00,,,BE0} */ + picreg_t __pad1; /* 0x000{B18,,,BF8} */ + picreg_t p_buf_valid; /* 0x000{B10,,,BF0} */ + } p_pcix_write_buf_64[8]; + + /* + * end "PCI/X registers that are specific to PIC" + */ + + char _pad_000c00[0x010000 - 0x000c00]; + + /* 0x010000-0x011fff -- Internal Address Translation Entry RAM */ + /* + * Xbridge and PIC have 1024 internal ATE's and the Bridge has 128. + * Make enough room for the Xbridge/PIC ATE's and depend on runtime + * checks to limit access to bridge ATE's. + * + * In [X]bridge the internal ATE Ram is writen as double words only, + * but due to internal design issues it is read back as single words. + * i.e: + * b_int_ate_ram[index].hi.rd << 32 | xb_int_ate_ram_lo[index].rd + */ + union { + bridge_ate_t wr; /* write-only */ /* 0x01{0000,,,1FF8} */ + struct { + bridgereg_t rd; /* read-only */ /* 0x01{0004,,,1FFC} */ + bridgereg_t _p_pad; + } hi; + } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; + #define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd + + /* 0x012000-0x013fff -- Internal Address Translation Entry RAM LOW */ + struct { + bridgereg_t rd; /* read-only */ /* 0x01{2004,,,3FFC} */ + bridgereg_t _p_pad; + } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; + + char _pad_014000[0x18000 - 0x014000]; + + /* 0x18000-0x197F8 -- PIC Write Request Ram */ + /* 0x18000 - 0x187F8 */ + picreg_t p_wr_req_lower[PIC_WR_REQ_BUFSIZE]; + /* 0x18800 - 0x18FF8 */ + picreg_t p_wr_req_upper[PIC_WR_REQ_BUFSIZE]; + /* 0x19000 - 0x197F8 */ + picreg_t p_wr_req_parity[PIC_WR_REQ_BUFSIZE]; + + char _pad_019800[0x20000 - 0x019800]; + + /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */ + union { /* make all access sizes available. */ + uchar_t c[0x1000 / 1]; /* 0x02{0000,,,7FFF} */ + uint16_t s[0x1000 / 2]; /* 0x02{0000,,,7FFF} */ + uint32_t l[0x1000 / 4]; /* 0x02{0000,,,7FFF} */ + uint64_t d[0x1000 / 8]; /* 0x02{0000,,,7FFF} */ + union { + uchar_t c[0x100 / 1]; + uint16_t s[0x100 / 2]; + uint32_t l[0x100 / 4]; + uint64_t d[0x100 / 8]; + } f[8]; + } b_type0_cfg_dev[8]; /* 0x02{0000,,,7FFF} */ + + /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */ + union { /* make all access sizes available. */ + uchar_t c[0x1000 / 1]; + uint16_t s[0x1000 / 2]; + uint32_t l[0x1000 / 4]; + uint64_t d[0x1000 / 8]; + union { + uchar_t c[0x100 / 1]; + uint16_t s[0x100 / 2]; + uint32_t l[0x100 / 4]; + uint64_t d[0x100 / 8]; + } f[8]; + } b_type1_cfg; /* 0x028000-0x029000 */ + + char _pad_029000[0x007000]; /* 0x029000-0x030000 */ + + /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */ + union { + uchar_t c[8 / 1]; + uint16_t s[8 / 2]; + uint32_t l[8 / 4]; + uint64_t d[8 / 8]; + } b_pci_iack; /* 0x030000-0x030007 */ + + uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ + + /* 0x080000-0x0FFFFF -- External Address Translation Entry RAM */ + bridge_ate_t b_ext_ate_ram[0x10000]; + + /* 0x100000-0x1FFFFF -- Reserved */ + char _pad_100000[0x200000-0x100000]; + + /* 0x200000-0xBFFFFF -- PCI/GIO Device Spaces */ + union { /* make all access sizes available. */ + uchar_t c[0x100000 / 1]; + uint16_t s[0x100000 / 2]; + uint32_t l[0x100000 / 4]; + uint64_t d[0x100000 / 8]; + } b_devio_raw[10]; + + /* b_devio macro is a bit strange; it reflects the + * fact that the Bridge ASIC provides 2M for the + * first two DevIO windows and 1M for the other six. + */ + #define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] + + /* 0xC00000-0xFFFFFF -- External Flash Proms 1,0 */ + union { /* make all access sizes available. */ + uchar_t c[0x400000 / 1]; /* read-only */ + uint16_t s[0x400000 / 2]; /* read-write */ + uint32_t l[0x400000 / 4]; /* read-only */ + uint64_t d[0x400000 / 8]; /* read-only */ + } b_external_flash; +} bridge_t; + +#else /* CONFIG_IA64_SGI_SN1 */ + typedef volatile struct bridge_s { @@ -311,6 +839,12 @@ typedef volatile struct bridge_s { uint16_t s[0x1000 / 2]; uint32_t l[0x1000 / 4]; uint64_t d[0x1000 / 8]; + union { + uchar_t c[0x100 / 1]; + uint16_t s[0x100 / 2]; + uint32_t l[0x100 / 4]; + uint64_t d[0x100 / 8]; + } f[8]; } b_type1_cfg; /* 0x028000-0x029000 */ char _pad_029000[0x007000]; /* 0x029000-0x030000 */ @@ -354,286 +888,7 @@ typedef volatile struct bridge_s { } b_external_flash; /* 0xC00000 */ } bridge_t; -#else - -/* - * Field formats for Error Command Word and Auxillary Error Command Word - * of bridge. - */ -typedef struct bridge_err_cmdword_s { - union { - uint32_t cmd_word; - struct { - uint32_t didn:4, /* Destination ID */ - sidn:4, /* SOurce ID */ - pactyp:4, /* Packet type */ - tnum:5, /* Trans Number */ - coh:1, /* Coh Transacti */ - ds:2, /* Data size */ - gbr:1, /* GBR enable */ - vbpm:1, /* VBPM message */ - error:1, /* Error occurred */ - barr:1, /* Barrier op */ - rsvd:8; - } berr_st; - } berr_un; -} bridge_err_cmdword_t; - -typedef volatile struct bridge_s { - - /* Local Registers 0x000000-0x00FFFF */ - - /* standard widget configuration 0x000000-0x000057 */ - widget_cfg_t b_widget; /* 0x000000 */ - - /* helper fieldnames for accessing bridge widget */ - -#define b_wid_id b_widget.w_id -#define b_wid_stat b_widget.w_status -#define b_wid_err_upper b_widget.w_err_upper_addr -#define b_wid_err_lower b_widget.w_err_lower_addr -#define b_wid_control b_widget.w_control -#define b_wid_req_timeout b_widget.w_req_timeout -#define b_wid_int_upper b_widget.w_intdest_upper_addr -#define b_wid_int_lower b_widget.w_intdest_lower_addr -#define b_wid_err_cmdword b_widget.w_err_cmd_word -#define b_wid_llp b_widget.w_llp_cfg -#define b_wid_tflush b_widget.w_tflush - - /* bridge-specific widget configuration 0x000058-0x00007F */ - bridgereg_t _pad_000058; - bridgereg_t b_wid_aux_err; /* 0x00005C */ - bridgereg_t _pad_000060; - bridgereg_t b_wid_resp_upper; /* 0x000064 */ - bridgereg_t _pad_000068; - bridgereg_t b_wid_resp_lower; /* 0x00006C */ - bridgereg_t _pad_000070; - bridgereg_t b_wid_tst_pin_ctrl; /* 0x000074 */ - bridgereg_t _pad_000078[2]; - - /* PMU & Map 0x000080-0x00008F */ - bridgereg_t _pad_000080; - bridgereg_t b_dir_map; /* 0x000084 */ - bridgereg_t _pad_000088[2]; - - /* SSRAM 0x000090-0x00009F */ - bridgereg_t _pad_000090; - bridgereg_t b_ram_perr_or_map_fault;/* 0x000094 */ -#define b_ram_perr b_ram_perr_or_map_fault /* Bridge */ -#define b_map_fault b_ram_perr_or_map_fault /* Xbridge */ - bridgereg_t _pad_000098[2]; - - /* Arbitration 0x0000A0-0x0000AF */ - bridgereg_t _pad_0000A0; - bridgereg_t b_arb; /* 0x0000A4 */ - bridgereg_t _pad_0000A8[2]; - - /* Number In A Can 0x0000B0-0x0000BF */ - bridgereg_t _pad_0000B0; - bridgereg_t b_nic; /* 0x0000B4 */ - bridgereg_t _pad_0000B8[2]; - - /* PCI/GIO 0x0000C0-0x0000FF */ - bridgereg_t _pad_0000C0; - bridgereg_t b_bus_timeout; /* 0x0000C4 */ -#define b_pci_bus_timeout b_bus_timeout - - bridgereg_t _pad_0000C8; - bridgereg_t b_pci_cfg; /* 0x0000CC */ - bridgereg_t _pad_0000D0; - bridgereg_t b_pci_err_upper; /* 0x0000D4 */ - bridgereg_t _pad_0000D8; - bridgereg_t b_pci_err_lower; /* 0x0000DC */ - bridgereg_t _pad_0000E0[8]; -#define b_gio_err_lower b_pci_err_lower -#define b_gio_err_upper b_pci_err_upper - - /* Interrupt 0x000100-0x0001FF */ - bridgereg_t _pad_000100; - bridgereg_t b_int_status; /* 0x000104 */ - bridgereg_t _pad_000108; - bridgereg_t b_int_enable; /* 0x00010C */ - bridgereg_t _pad_000110; - bridgereg_t b_int_rst_stat; /* 0x000114 */ - bridgereg_t _pad_000118; - bridgereg_t b_int_mode; /* 0x00011C */ - bridgereg_t _pad_000120; - bridgereg_t b_int_device; /* 0x000124 */ - bridgereg_t _pad_000128; - bridgereg_t b_int_host_err; /* 0x00012C */ - - struct { - bridgereg_t __pad; /* 0x0001{30,,,68} */ - bridgereg_t addr; /* 0x0001{34,,,6C} */ - } b_int_addr[8]; /* 0x000130 */ - - bridgereg_t _pad_000170; - bridgereg_t b_err_int_view; /* 0x000174 */ - bridgereg_t _pad_000178; - bridgereg_t b_mult_int; /* 0x00017c */ - - struct { - bridgereg_t __pad; /* 0x0001{80,,,B8} */ - bridgereg_t intr; /* 0x0001{84,,,BC} */ - } b_force_always[8]; /* 0x000180 */ - - struct { - bridgereg_t __pad; /* 0x0001{C0,,,F8} */ - bridgereg_t intr; /* 0x0001{C4,,,FC} */ - } b_force_pin[8]; /* 0x0001C0 */ - - /* Device 0x000200-0x0003FF */ - struct { - bridgereg_t __pad; /* 0x0002{00,,,38} */ - bridgereg_t reg; /* 0x0002{04,,,3C} */ - } b_device[8]; /* 0x000200 */ - - struct { - bridgereg_t __pad; /* 0x0002{40,,,78} */ - bridgereg_t reg; /* 0x0002{44,,,7C} */ - } b_wr_req_buf[8]; /* 0x000240 */ - - struct { - bridgereg_t __pad; /* 0x0002{80,,,88} */ - bridgereg_t reg; /* 0x0002{84,,,8C} */ - } b_rrb_map[2]; /* 0x000280 */ -#define b_even_resp b_rrb_map[0].reg /* 0x000284 */ -#define b_odd_resp b_rrb_map[1].reg /* 0x00028C */ - - bridgereg_t _pad_000290; - bridgereg_t b_resp_status; /* 0x000294 */ - bridgereg_t _pad_000298; - bridgereg_t b_resp_clear; /* 0x00029C */ - - bridgereg_t _pad_0002A0[24]; - - /* Xbridge only */ - struct { - bridgereg_t __pad1; /* 0x0003{00,,,F0} */ - bridgereg_t upper; /* 0x0003{04,,,F4} */ - bridgereg_t __pad2; /* 0x0003{08,,,F8} */ - bridgereg_t lower; /* 0x0003{0C,,,FC} */ - } b_buf_addr_match[16]; - - /* Performance Monitor Registers (even only) */ - struct { - bridgereg_t __pad1; /* 0x000400,,,5C0 */ - bridgereg_t flush_w_touch; /* 0x000404,,,5C4 */ - bridgereg_t __pad2; /* 0x000408,,,5C8 */ - bridgereg_t flush_wo_touch; /* 0x00040C,,,5CC */ - bridgereg_t __pad3; /* 0x000410,,,5D0 */ - bridgereg_t inflight; /* 0x000414,,,5D4 */ - bridgereg_t __pad4; /* 0x000418,,,5D8 */ - bridgereg_t prefetch; /* 0x00041C,,,5DC */ - bridgereg_t __pad5; /* 0x000420,,,5E0 */ - bridgereg_t total_pci_retry; /* 0x000424,,,5E4 */ - bridgereg_t __pad6; /* 0x000428,,,5E8 */ - bridgereg_t max_pci_retry; /* 0x00042C,,,5EC */ - bridgereg_t __pad7; /* 0x000430,,,5F0 */ - bridgereg_t max_latency; /* 0x000434,,,5F4 */ - bridgereg_t __pad8; /* 0x000438,,,5F8 */ - bridgereg_t clear_all; /* 0x00043C,,,5FC */ - } b_buf_count[8]; - - char _pad_000600[0x010000 - 0x000600]; - - /* - * The Xbridge has 1024 internal ATE's and the Bridge has 128. - * Make enough room for the Xbridge ATE's and depend on runtime - * checks to limit access to bridge ATE's. - */ - - /* Internal Address Translation Entry RAM 0x010000-0x011fff */ - union { - bridge_ate_t wr; /* write-only */ - struct { - bridgereg_t _p_pad; - bridgereg_t rd; /* read-only */ - } hi; - } b_int_ate_ram[XBRIDGE_INTERNAL_ATES]; - -#define b_int_ate_ram_lo(idx) b_int_ate_ram[idx+512].hi.rd - - /* the xbridge read path for internal ates starts at 0x12000. - * I don't believe we ever try to read the ates. - */ - /* Internal Address Translation Entry RAM LOW 0x012000-0x013fff */ - struct { - bridgereg_t _p_pad; - bridgereg_t rd; /* read-only */ - } xb_int_ate_ram_lo[XBRIDGE_INTERNAL_ATES]; - - char _pad_014000[0x20000 - 0x014000]; - - /* PCI Device Configuration Spaces 0x020000-0x027FFF */ - union { /* make all access sizes available. */ - uchar_t c[0x1000 / 1]; - uint16_t s[0x1000 / 2]; - uint32_t l[0x1000 / 4]; - uint64_t d[0x1000 / 8]; - union { - uchar_t c[0x100 / 1]; - uint16_t s[0x100 / 2]; - uint32_t l[0x100 / 4]; - uint64_t d[0x100 / 8]; - } f[8]; - } b_type0_cfg_dev[8]; /* 0x020000 */ - - - /* PCI Type 1 Configuration Space 0x028000-0x028FFF */ - union { /* make all access sizes available. */ - uchar_t c[0x1000 / 1]; - uint16_t s[0x1000 / 2]; - uint32_t l[0x1000 / 4]; - uint64_t d[0x1000 / 8]; - } b_type1_cfg; /* 0x028000-0x029000 */ - - char _pad_029000[0x007000]; /* 0x029000-0x030000 */ - - /* PCI Interrupt Acknowledge Cycle 0x030000 */ - union { - uchar_t c[8 / 1]; - uint16_t s[8 / 2]; - uint32_t l[8 / 4]; - uint64_t d[8 / 8]; - } b_pci_iack; /* 0x030000 */ - - uchar_t _pad_030007[0x04fff8]; /* 0x030008-0x07FFFF */ - - /* External Address Translation Entry RAM 0x080000-0x0FFFFF */ - bridge_ate_t b_ext_ate_ram[0x10000]; - - /* Reserved 0x100000-0x1FFFFF */ - char _pad_100000[0x200000-0x100000]; - - /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */ - union { /* make all access sizes available. */ - uchar_t c[0x100000 / 1]; - uint16_t s[0x100000 / 2]; - uint32_t l[0x100000 / 4]; - uint64_t d[0x100000 / 8]; - } b_devio_raw[10]; /* 0x200000 */ - - /* b_devio macro is a bit strange; it reflects the - * fact that the Bridge ASIC provides 2M for the - * first two DevIO windows and 1M for the other six. - */ -#define b_devio(n) b_devio_raw[((n)<2)?(n*2):(n+2)] - - /* External Flash Proms 1,0 0xC00000-0xFFFFFF */ - union { /* make all access sizes available. */ - uchar_t c[0x400000 / 1]; /* read-only */ - uint16_t s[0x400000 / 2]; /* read-write */ - uint32_t l[0x400000 / 4]; /* read-only */ - uint64_t d[0x400000 / 8]; /* read-only */ - } b_external_flash; /* 0xC00000 */ -} bridge_t; - -#endif - - - - +#endif /* CONFIG_IA64_SGI_SN1 */ #define berr_field berr_un.berr_st @@ -873,7 +1128,12 @@ typedef volatile struct bridge_s { /* end of Performance Monitor Registers */ -/* Byte offset macros for Bridge I/O space */ +/* Byte offset macros for Bridge I/O space. + * + * NOTE: Where applicable please use the PCIBR_xxx or PCIBRIDGE_xxx + * macros (below) as they will handle [X]Bridge and PIC. For example, + * PCIBRIDGE_TYPE0_CFG_DEV0() vs BRIDGE_TYPE0_CFG_DEV0 + */ #define BRIDGE_ATE_RAM 0x00010000 /* Internal Addr Xlat Ram */ @@ -905,7 +1165,55 @@ typedef volatile struct bridge_s { #ifndef __ASSEMBLY__ #define BRIDGE_DEVIO(x) ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB) -#endif /* __ASSEMBLY__ */ + +/* + * The device space macros for PIC are more complicated because the PIC has + * two PCI/X bridges under the same widget. For PIC bus 0, the addresses are + * basically the same as for the [X]Bridge. For PIC bus 1, the addresses are + * offset by 0x800000. Here are two sets of macros. They are + * "PCIBRIDGE_xxx" that return the address based on the supplied bus number + * and also equivalent "PCIBR_xxx" macros that may be used with a + * pcibr_soft_s structure. Both should work with all bridges. + */ +#define PIC_BUS1_OFFSET 0x800000 + +#define PCIBRIDGE_TYPE0_CFG_DEV0(busnum) \ + ((busnum) ? BRIDGE_TYPE0_CFG_DEV0 + PIC_BUS1_OFFSET : \ + BRIDGE_TYPE0_CFG_DEV0) +#define PCIBRIDGE_TYPE1_CFG(busnum) \ + ((busnum) ? BRIDGE_TYPE1_CFG + PIC_BUS1_OFFSET : BRIDGE_TYPE1_CFG) +#define PCIBRIDGE_TYPE0_CFG_DEV(busnum, s) \ + (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\ + (s)*BRIDGE_TYPE0_CFG_SLOT_OFF) +#define PCIBRIDGE_TYPE0_CFG_DEVF(busnum, s, f) \ + (PCIBRIDGE_TYPE0_CFG_DEV0(busnum)+\ + (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\ + (f)*BRIDGE_TYPE0_CFG_FUNC_OFF) +#define PCIBRIDGE_DEVIO0(busnum) ((busnum) ? \ + (BRIDGE_DEVIO0 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO0) +#define PCIBRIDGE_DEVIO1(busnum) ((busnum) ? \ + (BRIDGE_DEVIO1 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO1) +#define PCIBRIDGE_DEVIO2(busnum) ((busnum) ? \ + (BRIDGE_DEVIO2 + PIC_BUS1_OFFSET) : BRIDGE_DEVIO2) +#define PCIBRIDGE_DEVIO(busnum, x) \ + ((x)<=1 ? PCIBRIDGE_DEVIO0(busnum)+(x)*BRIDGE_DEVIO_2MB : \ + PCIBRIDGE_DEVIO2(busnum)+((x)-2)*BRIDGE_DEVIO_1MB) + +#define PCIBR_BRIDGE_DEVIO0(ps) PCIBRIDGE_DEVIO0((ps)->bs_busnum) +#define PCIBR_BRIDGE_DEVIO1(ps) PCIBRIDGE_DEVIO1((ps)->bs_busnum) +#define PCIBR_BRIDGE_DEVIO2(ps) PCIBRIDGE_DEVIO2((ps)->bs_busnum) +#define PCIBR_BRIDGE_DEVIO(ps, s) PCIBRIDGE_DEVIO((ps)->bs_busnum, s) + +#define PCIBR_TYPE1_CFG(ps) PCIBRIDGE_TYPE1_CFG((ps)->bs_busnum) +#define PCIBR_BUS_TYPE0_CFG_DEV0(ps) PCIBR_TYPE0_CFG_DEV(ps, 0) +#define PCIBR_TYPE0_CFG_DEV(ps, s) \ + ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s+1) : \ + PCIBRIDGE_TYPE0_CFG_DEV((ps)->bs_busnum, s)) +#define PCIBR_BUS_TYPE0_CFG_DEVF(ps,s,f) \ + ((IS_PIC_SOFT(ps)) ? PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,(s+1),f) : \ + PCIBRIDGE_TYPE0_CFG_DEVF((ps)->bs_busnum,s,f)) + +#endif /* LANGUAGE_C */ #define BRIDGE_EXTERNAL_FLASH 0x00C00000 /* External Flash PROMS */ @@ -929,6 +1237,17 @@ typedef volatile struct bridge_s { #define XBRIDGE_REV_A 0x1 #define XBRIDGE_REV_B 0x2 +/* macros to determine bridge type. 'wid' == widget identification */ +#define IS_BRIDGE(wid) (XWIDGET_PART_NUM(wid) == BRIDGE_WIDGET_PART_NUM && \ + XWIDGET_MFG_NUM(wid) == BRIDGE_WIDGET_MFGR_NUM) +#define IS_XBRIDGE(wid) (XWIDGET_PART_NUM(wid) == XBRIDGE_WIDGET_PART_NUM && \ + XWIDGET_MFG_NUM(wid) == XBRIDGE_WIDGET_MFGR_NUM) +#define IS_PIC_BUS0(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS0 && \ + XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM) +#define IS_PIC_BUS1(wid) (XWIDGET_PART_NUM(wid) == PIC_WIDGET_PART_NUM_BUS1 && \ + XWIDGET_MFG_NUM(wid) == PIC_WIDGET_MFGR_NUM) +#define IS_PIC_BRIDGE(wid) (IS_PIC_BUS0(wid) || IS_PIC_BUS1(wid)) + /* Part + Rev numbers allows distinction and acscending sequence */ #define BRIDGE_PART_REV_A (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_A) #define BRIDGE_PART_REV_B (BRIDGE_WIDGET_PART_NUM << 4 | BRIDGE_REV_B) @@ -938,7 +1257,8 @@ typedef volatile struct bridge_s { #define XBRIDGE_PART_REV_B (XBRIDGE_WIDGET_PART_NUM << 4 | XBRIDGE_REV_B) /* Bridge widget status register bits definition */ - +#define PIC_STAT_PCIX_SPEED (0x3ull << 34) +#define PIC_STAT_PCIX_ACTIVE (0x1ull << 33) #define BRIDGE_STAT_LLP_REC_CNT (0xFFu << 24) #define BRIDGE_STAT_LLP_TX_CNT (0xFF << 16) #define BRIDGE_STAT_FLASH_SELECT (0x1 << 6) @@ -946,7 +1266,18 @@ typedef volatile struct bridge_s { #define BRIDGE_STAT_PENDING (0x1F << 0) /* Bridge widget control register bits definition */ -#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) +#define PIC_CTRL_NO_SNOOP (0x1ull << 62) +#define PIC_CTRL_RELAX_ORDER (0x1ull << 61) +#define PIC_CTRL_BUS_NUM(x) ((unsigned long long)(x) << 48) +#define PIC_CTRL_BUS_NUM_MASK (PIC_CTRL_BUS_NUM(0xff)) +#define PIC_CTRL_DEV_NUM(x) ((unsigned long long)(x) << 43) +#define PIC_CTRL_DEV_NUM_MASK (PIC_CTRL_DEV_NUM(0x1f)) +#define PIC_CTRL_FUN_NUM(x) ((unsigned long long)(x) << 40) +#define PIC_CTRL_FUN_NUM_MASK (PIC_CTRL_FUN_NUM(0x7)) +#define PIC_CTRL_PAR_EN_REQ (0x1ull << 29) +#define PIC_CTRL_PAR_EN_RESP (0x1ull << 30) +#define PIC_CTRL_PAR_EN_ATE (0x1ull << 31) +#define BRIDGE_CTRL_FLASH_WR_EN (0x1ul << 31) /* bridge only */ #define BRIDGE_CTRL_EN_CLK50 (0x1 << 30) #define BRIDGE_CTRL_EN_CLK40 (0x1 << 29) #define BRIDGE_CTRL_EN_CLK33 (0x1 << 28) @@ -970,6 +1301,8 @@ typedef volatile struct bridge_s { #define BRIDGE_CTRL_CLR_RLLP_CNT (0x1 << 11) #define BRIDGE_CTRL_CLR_TLLP_CNT (0x1 << 10) #define BRIDGE_CTRL_SYS_END (0x1 << 9) +#define BRIDGE_CTRL_PCI_SPEED (0x3 << 4) + #define BRIDGE_CTRL_BUS_SPEED(n) ((n) << 4) #define BRIDGE_CTRL_BUS_SPEED_MASK (BRIDGE_CTRL_BUS_SPEED(0x3)) #define BRIDGE_CTRL_BUS_SPEED_33 0x00 @@ -1023,6 +1356,20 @@ typedef volatile struct bridge_s { #define BRIDGE_BUS_PCI_RETRY_MASK BRIDGE_BUS_PCI_RETRY_CNT(0x3ff) /* Bridge interrupt status register bits definition */ +#define PIC_ISR_PCIX_SPLIT_MSG_PE (0x1ull << 45) +#define PIC_ISR_PCIX_SPLIT_EMSG (0x1ull << 44) +#define PIC_ISR_PCIX_SPLIT_TO (0x1ull << 43) +#define PIC_ISR_PCIX_UNEX_COMP (0x1ull << 42) +#define PIC_ISR_INT_RAM_PERR (0x1ull << 41) +#define PIC_ISR_PCIX_ARB_ERR (0x1ull << 40) +#define PIC_ISR_PCIX_REQ_TOUT (0x1ull << 39) +#define PIC_ISR_PCIX_TABORT (0x1ull << 38) +#define PIC_ISR_PCIX_PERR (0x1ull << 37) +#define PIC_ISR_PCIX_SERR (0x1ull << 36) +#define PIC_ISR_PCIX_MRETRY (0x1ull << 35) +#define PIC_ISR_PCIX_MTOUT (0x1ull << 34) +#define PIC_ISR_PCIX_DA_PARITY (0x1ull << 33) +#define PIC_ISR_PCIX_AD_PARITY (0x1ull << 32) #define BRIDGE_ISR_MULTI_ERR (0x1u << 31) /* bridge only */ #define BRIDGE_ISR_PMU_ESIZE_FAULT (0x1 << 30) /* bridge only */ #define BRIDGE_ISR_PAGE_FAULT (0x1 << 30) /* xbridge only */ @@ -1058,12 +1405,18 @@ typedef volatile struct bridge_s { BRIDGE_ISR_LLP_TCTY) #define BRIDGE_ISR_PCIBUS_PIOERR \ - (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT) + (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT| \ + PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT) #define BRIDGE_ISR_PCIBUS_ERROR \ (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR| \ BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT| \ - BRIDGE_ISR_PCI_PARITY) + BRIDGE_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR| \ + PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY| \ + PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY| \ + PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP| \ + PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG| \ + PIC_ISR_PCIX_SPLIT_MSG_PE) #define BRIDGE_ISR_XTALK_ERROR \ (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\ @@ -1075,20 +1428,39 @@ typedef volatile struct bridge_s { #define BRIDGE_ISR_ERRORS \ (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR| \ BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ - BRIDGE_ISR_PMU_ESIZE_FAULT) + BRIDGE_ISR_PMU_ESIZE_FAULT|PIC_ISR_PCIX_ARB_ERR| \ + PIC_ISR_INT_RAM_PERR) /* * List of Errors which are fatal and kill the sytem */ #define BRIDGE_ISR_ERROR_FATAL \ ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\ - BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY ) + BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY| \ + PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_AD_PARITY| \ + PIC_ISR_PCIX_DA_PARITY| \ + PIC_ISR_INT_RAM_PERR|PIC_ISR_PCIX_SPLIT_MSG_PE ) #define BRIDGE_ISR_ERROR_DUMP \ (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT| \ - BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR) + BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR| \ + PIC_ISR_PCIX_ARB_ERR|PIC_ISR_INT_RAM_PERR) /* Bridge interrupt enable register bits definition */ +#define PIC_IMR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE +#define PIC_IMR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG +#define PIC_IMR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO +#define PIC_IMR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP +#define PIC_IMR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR +#define PIC_IMR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR +#define PIC_IMR_PCIX_REQ_TOUR PIC_ISR_PCIX_REQ_TOUT +#define PIC_IMR_PCIX_TABORT PIC_ISR_PCIX_TABORT +#define PIC_IMR_PCIX_PERR PIC_ISR_PCIX_PERR +#define PIC_IMR_PCIX_SERR PIC_ISR_PCIX_SERR +#define PIC_IMR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY +#define PIC_IMR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT +#define PIC_IMR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY +#define PIC_IMR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY #define BRIDGE_IMR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP #define BRIDGE_IMR_PMU_ESIZE_FAULT BRIDGE_ISR_PMU_ESIZE_FAULT #define BRIDGE_IMR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT @@ -1116,7 +1488,46 @@ typedef volatile struct bridge_s { #define BRIDGE_IMR_INT_MSK BRIDGE_ISR_INT_MSK #define BRIDGE_IMR_INT(x) BRIDGE_ISR_INT(x) -/* Bridge interrupt reset register bits definition */ +/* + * Bridge interrupt reset register bits definition. Note, PIC can + * reset indiviual error interrupts, BRIDGE & XBRIDGE can only do + * groups of them. + */ +#define PIC_IRR_PCIX_SPLIT_MSG_PE PIC_ISR_PCIX_SPLIT_MSG_PE +#define PIC_IRR_PCIX_SPLIT_EMSG PIC_ISR_PCIX_SPLIT_EMSG +#define PIC_IRR_PCIX_SPLIT_TO PIC_ISR_PCIX_SPLIT_TO +#define PIC_IRR_PCIX_UNEX_COMP PIC_ISR_PCIX_UNEX_COMP +#define PIC_IRR_INT_RAM_PERR PIC_ISR_INT_RAM_PERR +#define PIC_IRR_PCIX_ARB_ERR PIC_ISR_PCIX_ARB_ERR +#define PIC_IRR_PCIX_REQ_TOUT PIC_ISR_PCIX_REQ_TOUT +#define PIC_IRR_PCIX_TABORT PIC_ISR_PCIX_TABORT +#define PIC_IRR_PCIX_PERR PIC_ISR_PCIX_PERR +#define PIC_IRR_PCIX_SERR PIC_ISR_PCIX_SERR +#define PIC_IRR_PCIX_MRETRY PIC_ISR_PCIX_MRETRY +#define PIC_IRR_PCIX_MTOUT PIC_ISR_PCIX_MTOUT +#define PIC_IRR_PCIX_DA_PARITY PIC_ISR_PCIX_DA_PARITY +#define PIC_IRR_PCIX_AD_PARITY PIC_ISR_PCIX_AD_PARITY +#define PIC_IRR_PAGE_FAULT BRIDGE_ISR_PAGE_FAULT +#define PIC_IRR_UNEXP_RESP BRIDGE_ISR_UNEXP_RESP +#define PIC_IRR_BAD_XRESP_PKT BRIDGE_ISR_BAD_XRESP_PKT +#define PIC_IRR_BAD_XREQ_PKT BRIDGE_ISR_BAD_XREQ_PKT +#define PIC_IRR_RESP_XTLK_ERR BRIDGE_ISR_RESP_XTLK_ERR +#define PIC_IRR_REQ_XTLK_ERR BRIDGE_ISR_REQ_XTLK_ERR +#define PIC_IRR_INVLD_ADDR BRIDGE_ISR_INVLD_ADDR +#define PIC_IRR_UNSUPPORTED_XOP BRIDGE_ISR_UNSUPPORTED_XOP +#define PIC_IRR_XREQ_FIFO_OFLOW BRIDGE_ISR_XREQ_FIFO_OFLOW +#define PIC_IRR_LLP_REC_SNERR BRIDGE_ISR_LLP_REC_SNERR +#define PIC_IRR_LLP_REC_CBERR BRIDGE_ISR_LLP_REC_CBERR +#define PIC_IRR_LLP_RCTY BRIDGE_ISR_LLP_RCTY +#define PIC_IRR_LLP_TX_RETRY BRIDGE_ISR_LLP_TX_RETRY +#define PIC_IRR_LLP_TCTY BRIDGE_ISR_LLP_TCTY +#define PIC_IRR_PCI_ABORT BRIDGE_ISR_PCI_ABORT +#define PIC_IRR_PCI_PARITY BRIDGE_ISR_PCI_PARITY +#define PIC_IRR_PCI_SERR BRIDGE_ISR_PCI_SERR +#define PIC_IRR_PCI_PERR BRIDGE_ISR_PCI_PERR +#define PIC_IRR_PCI_MST_TIMEOUT BRIDGE_ISR_PCI_MST_TIMEOUT +#define PIC_IRR_PCI_RETRY_CNT BRIDGE_ISR_PCI_RETRY_CNT +#define PIC_IRR_XREAD_REQ_TIMEOUT BRIDGE_ISR_XREAD_REQ_TIMEOUT #define BRIDGE_IRR_MULTI_CLR (0x1 << 6) #define BRIDGE_IRR_CRP_GRP_CLR (0x1 << 5) #define BRIDGE_IRR_RESP_BUF_GRP_CLR (0x1 << 4) @@ -1153,6 +1564,21 @@ typedef volatile struct bridge_s { #define BRIDGE_IRR_GIO_GRP (BRIDGE_ISR_GIO_B_ENBL_ERR | \ BRIDGE_ISR_GIO_MST_TIMEOUT) +#define PIC_IRR_RAM_GRP PIC_ISR_INT_RAM_PERR + +#define PIC_PCIX_GRP_CLR (PIC_IRR_PCIX_AD_PARITY | \ + PIC_IRR_PCIX_DA_PARITY | \ + PIC_IRR_PCIX_MTOUT | \ + PIC_IRR_PCIX_MRETRY | \ + PIC_IRR_PCIX_SERR | \ + PIC_IRR_PCIX_PERR | \ + PIC_IRR_PCIX_TABORT | \ + PIC_ISR_PCIX_REQ_TOUT | \ + PIC_ISR_PCIX_UNEX_COMP | \ + PIC_ISR_PCIX_SPLIT_TO | \ + PIC_ISR_PCIX_SPLIT_EMSG | \ + PIC_ISR_PCIX_SPLIT_MSG_PE) + /* Bridge INT_DEV register bits definition */ #define BRIDGE_INT_DEV_SHFT(n) ((n)*3) #define BRIDGE_INT_DEV_MASK(n) (0x7 << BRIDGE_INT_DEV_SHFT(n)) @@ -1162,6 +1588,10 @@ typedef volatile struct bridge_s { #define BRIDGE_INT_ADDR_HOST 0x0003FF00 #define BRIDGE_INT_ADDR_FLD 0x000000FF +/* PIC interrupt(x) register bits definition */ +#define PIC_INT_ADDR_FLD 0x00FF000000000000 +#define PIC_INT_ADDR_HOST 0x0000FFFFFFFFFFFF + #define BRIDGE_TMO_PCI_RETRY_HLD_MASK 0x1f0000 #define BRIDGE_TMO_GIO_TIMEOUT_MASK 0x001000 #define BRIDGE_TMO_PCI_RETRY_CNT_MASK 0x0003ff @@ -1239,8 +1669,13 @@ typedef volatile struct bridge_s { /* RRB assignment register */ #define BRIDGE_RRB_EN 0x8 /* after shifting down */ #define BRIDGE_RRB_DEV 0x7 /* after shifting down */ -#define BRIDGE_RRB_VDEV 0x4 /* after shifting down */ -#define BRIDGE_RRB_PDEV 0x3 /* after shifting down */ +#define BRIDGE_RRB_VDEV 0x4 /* after shifting down, 2 virtual channels */ +#define BRIDGE_RRB_PDEV 0x3 /* after shifting down, 8 devices */ + +#define PIC_RRB_EN 0x8 /* after shifting down */ +#define PIC_RRB_DEV 0x7 /* after shifting down */ +#define PIC_RRB_VDEV 0x6 /* after shifting down, 4 virtual channels */ +#define PIC_RRB_PDEV 0x1 /* after shifting down, 4 devices */ /* RRB status register */ #define BRIDGE_RRB_VALID(r) (0x00010000<<(r)) @@ -1249,6 +1684,15 @@ typedef volatile struct bridge_s { /* RRB clear register */ #define BRIDGE_RRB_CLEAR(r) (0x00000001<<(r)) +/* Defines for the virtual channels so we dont hardcode 0-3 within code */ +#define VCHAN0 0 /* virtual channel 0 (ie. the "normal" channel) */ +#define VCHAN1 1 /* virtual channel 1 */ +#define VCHAN2 2 /* virtual channel 2 - PIC only */ +#define VCHAN3 3 /* virtual channel 3 - PIC only */ + +/* PIC: PCI-X Read Buffer Attribute Register (RBAR) */ +#define NUM_RBAR 16 /* number of RBAR registers */ + /* xbox system controller declarations */ #define XBOX_BRIDGE_WID 8 #define FLASH_PROM1_BASE 0xE00000 /* To read the xbox sysctlr status */ @@ -1401,8 +1845,10 @@ typedef union ate_u { #define ATE_SWAP_ON(x) ((x) |= (1 << ATE_SWAPSHIFT)) #define ATE_SWAP_OFF(x) ((x) &= ~(1 << ATE_SWAPSHIFT)) -#define is_xbridge(bridge) \ - (XWIDGET_PART_NUM(bridge->b_wid_id) == XBRIDGE_WIDGET_PART_NUM) +#define is_xbridge(bridge) IS_XBRIDGE(bridge->b_wid_id) +#define is_pic(bridge) IS_PIC_BRIDGE(bridge->b_wid_id) + +/* extern declarations */ #ifndef __ASSEMBLY__ diff --git a/include/asm-ia64/sn/pci/pci_bus_cvlink.h b/include/asm-ia64/sn/pci/pci_bus_cvlink.h index d99ba4b0d4e8..6c4e2dfc2156 100644 --- a/include/asm-ia64/sn/pci/pci_bus_cvlink.h +++ b/include/asm-ia64/sn/pci/pci_bus_cvlink.h @@ -35,30 +35,33 @@ #define MAX_ATE_MAPS 1024 #define SET_PCIA64(dev) \ - (((struct sn1_device_sysdata *)((dev)->sysdata))->isa64) = 1 + (((struct sn_device_sysdata *)((dev)->sysdata))->isa64) = 1 #define IS_PCIA64(dev) (((dev)->dma_mask == 0xffffffffffffffffUL) || \ - (((struct sn1_device_sysdata *)((dev)->sysdata))->isa64)) + (((struct sn_device_sysdata *)((dev)->sysdata))->isa64)) #define IS_PCI32G(dev) ((dev)->dma_mask >= 0xffffffff) #define IS_PCI32L(dev) ((dev)->dma_mask < 0xffffffff) +#define IS_PIC_DEVICE(dev) ((struct sn_device_sysdata *)dev->sysdata)->isPIC + #define PCIDEV_VERTEX(pci_dev) \ - (((struct sn1_device_sysdata *)((pci_dev)->sysdata))->vhdl) + (((struct sn_device_sysdata *)((pci_dev)->sysdata))->vhdl) #define PCIBUS_VERTEX(pci_bus) \ - (((struct sn1_widget_sysdata *)((pci_bus)->sysdata))->vhdl) + (((struct sn_widget_sysdata *)((pci_bus)->sysdata))->vhdl) -struct sn1_widget_sysdata { +struct sn_widget_sysdata { devfs_handle_t vhdl; }; -struct sn1_device_sysdata { +struct sn_device_sysdata { devfs_handle_t vhdl; int isa64; + int isPIC; volatile unsigned int *dma_buf_sync; volatile unsigned int *xbow_buf_sync; }; -struct sn1_dma_maps_s{ +struct sn_dma_maps_s{ struct pcibr_dmamap_s dma_map; dma_addr_t dma_addr; }; diff --git a/include/asm-ia64/sn/pci/pci_defs.h b/include/asm-ia64/sn/pci/pci_defs.h index 963aed2b7050..2df7888e5616 100644 --- a/include/asm-ia64/sn/pci/pci_defs.h +++ b/include/asm-ia64/sn/pci/pci_defs.h @@ -39,7 +39,7 @@ * the PCI spec. */ #define PCI_TYPE1_BUS_MASK 0x00FF0000 -#define PCI_TYPE1_SLOT_MASK 0x0000F100 +#define PCI_TYPE1_SLOT_MASK 0x0000F800 #define PCI_TYPE1_FUNC_MASK 0x00000700 #define PCI_TYPE1_REG_MASK 0x000000FF @@ -68,14 +68,14 @@ /* NOTE: if you are using a C "switch" statement to * differentiate between the Config space registers, be - * aware that PCI_CFG_CLASS_CODE and PCI_CFG_BASE_CLASS + * aware that PCI_CFG_CLASS_CODE and PCI_CFG_PROG_IF * are the same offset. */ #define PCI_CFG_REV_ID 0x08 /* Revision Id (1 byte) */ #define PCI_CFG_CLASS_CODE 0x09 /* Class Code (3 bytes) */ -#define PCI_CFG_BASE_CLASS 0x09 /* Base Class (1 byte) */ +#define PCI_CFG_PROG_IF 0x09 /* Prog Interface (1 byte) */ #define PCI_CFG_SUB_CLASS 0x0A /* Sub Class (1 byte) */ -#define PCI_CFG_PROG_IF 0x0B /* Prog Interface (1 byte) */ +#define PCI_CFG_BASE_CLASS 0x0B /* Base Class (1 byte) */ #define PCI_CFG_CACHE_LINE 0x0C /* Cache line size (1 byte) */ #define PCI_CFG_LATENCY_TIMER 0x0D /* Latency Timer (1 byte) */ @@ -99,11 +99,10 @@ #define PCI_CFG_SUBSYS_ID 0x2E /* Subsystem ID */ #define PCI_EXPANSION_ROM 0x30 /* Expansion Rom Base (4B) */ +#define PCI_CAPABILITIES_PTR 0x34 /* Capabilities Pointer */ #define PCI_INTR_LINE 0x3C /* Interrupt Line (1B) */ #define PCI_INTR_PIN 0x3D /* Interrupt Pin (1B) */ -#define PCI_MIN_GNT 0x3E /* Minimum Grant (1B) */ -#define PCI_MAX_LAT 0x3F /* Maximum Latency (1B) */ #define PCI_CFG_VEND_SPECIFIC 0x40 /* first vendor specific reg */ @@ -126,6 +125,8 @@ #define PCI_CFG_PPB_IOLIMHI 0x32 /* IO Limit Addr bits 16..31 */ #define PCI_CFG_PPB_SUB_VENDOR 0x34 /* Subsystem Vendor ID */ #define PCI_CFG_PPB_SUB_DEVICE 0x36 /* Subsystem Device ID */ +#define PCI_CFG_PPB_ROM_BASE 0x38 /* ROM base address */ +#define PCI_CFG_PPB_INT_LINE 0x3C /* Interrupt Line */ #define PCI_CFG_PPB_INT_PIN 0x3D /* Interrupt Pin */ #define PCI_CFG_PPB_BRIDGE_CTRL 0x3E /* Bridge Control */ /* XXX- these might be DEC 21152 specific */ @@ -165,6 +166,7 @@ #define PCI_STAT_F_BK_BK_CAP 0x0080 /* Fast Back-to-Back Capable */ #define PCI_STAT_UDF_SUPP 0x0040 /* UDF Supported */ #define PCI_STAT_66MHZ_CAP 0x0020 /* 66 MHz Capable */ +#define PCI_STAT_CAP_LIST 0x0010 /* Capabilities List */ /* BIST Register Layout (0x0F) */ #define PCI_BIST_BIST_CAP 0x80 /* BIST Capable */ @@ -173,13 +175,63 @@ #define PCI_BIST_CMPL_OK 0x00 /* 0 value is completion OK */ /* Base Address Register 0x10 */ +#define PCI_BA_IO_CODEMASK 0x3 /* bottom 2 bits encode I/O BAR type */ #define PCI_BA_IO_SPACE 0x1 /* I/O Space Marker */ + +#define PCI_BA_MEM_CODEMASK 0xf /* bottom 4 bits encode MEM BAR type */ #define PCI_BA_MEM_LOCATION 0x6 /* 2 bits for location avail */ #define PCI_BA_MEM_32BIT 0x0 /* Anywhere in 32bit space */ #define PCI_BA_MEM_1MEG 0x2 /* Locate below 1 Meg */ #define PCI_BA_MEM_64BIT 0x4 /* Anywhere in 64bit space */ #define PCI_BA_PREFETCH 0x8 /* Prefetchable, no side effect */ +#define PCI_BA_ROM_CODEMASK 0x1 /* bottom bit control expansion ROM enable */ +#define PCI_BA_ROM_ENABLE 0x1 /* enable expansion ROM */ + +/* Bridge Control Register 0x3e */ +#define PCI_BCTRL_DTO_SERR 0x0800 /* Discard Timer timeout generates SERR on primary bus */ +#define PCI_BCTRL_DTO 0x0400 /* Discard Timer timeout status */ +#define PCI_BCTRL_DTO_SEC 0x0200 /* Secondary Discard Timer: 0 => 2^15 PCI clock cycles, 1 => 2^10 */ +#define PCI_BCTRL_DTO_PRI 0x0100 /* Primary Discard Timer: 0 => 2^15 PCI clock cycles, 1 => 2^10 */ +#define PCI_BCTRL_F_BK_BK_ENABLE 0x0080 /* Enable Fast Back-to-Back on secondary bus */ +#define PCI_BCTRL_RESET_SEC 0x0040 /* Reset Secondary bus */ +#define PCI_BCTRL_MSTR_ABT_MODE 0x0020 /* Master Abort Mode: 0 => do not report Master-Aborts */ +#define PCI_BCTRL_VGA_AF_ENABLE 0x0008 /* Enable VGA Address Forwarding */ +#define PCI_BCTRL_ISA_AF_ENABLE 0x0004 /* Enable ISA Address Forwarding */ +#define PCI_BCTRL_SERR_ENABLE 0x0002 /* Enable forwarding of SERR from secondary bus to primary bus */ +#define PCI_BCTRL_PAR_ERR_RESP 0x0001 /* Enable Parity Error Response reporting on secondary interface */ + +/* + * PCI 2.2 introduces the concept of ``capability lists.'' Capability lists + * provide a flexible mechanism for a device or bridge to advertise one or + * more standardized capabilities such as the presense of a power management + * interface, etc. The presense of a capability list is indicated by + * PCI_STAT_CAP_LIST being non-zero in the PCI_CFG_STATUS register. If + * PCI_STAT_CAP_LIST is set, then PCI_CFG_CAP_PTR is a ``pointer'' into the + * device-specific portion of the configuration header where the first + * capability block is stored. This ``pointer'' is a single byte which + * contains an offset from the beginning of the configuration header. The + * bottom two bits of the pointer are reserved and should be masked off to + * determine the offset. Each capability block contains a capability ID, a + * ``pointer'' to the next capability (another offset where a zero terminates + * the list) and capability-specific data. Each capability block starts with + * the capability ID and the ``next capability pointer.'' All data following + * this are capability-dependent. + */ +#define PCI_CAP_ID 0x00 /* Capability ID (1B) */ +#define PCI_CAP_PTR 0x01 /* Capability ``pointer'' (1B) */ + +/* PCI Capability IDs */ +#define PCI_CAP_PM 0x01 /* PCI Power Management */ +#define PCI_CAP_AGP 0x02 /* Accelerated Graphics Port */ +#define PCI_CAP_VPD 0x03 /* Vital Product Data (VPD) */ +#define PCI_CAP_SID 0x04 /* Slot Identification */ +#define PCI_CAP_MSI 0x05 /* Message Signaled Intr */ +#define PCI_CAP_HS 0x06 /* CompactPCI Hot Swap */ +#define PCI_CAP_PCIX 0x07 /* PCI-X */ +#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ + + /* PIO interface macros */ #ifndef IOC3_EMULATION @@ -210,10 +262,6 @@ extern void pci_write(void * address, int data, int type); #endif /* !IOC3_EMULATION */ /* effects on reads, merges */ -#ifdef CONFIG_SGI_IP22 -#define BYTECOUNT_W_GIO 0xbf400000 -#endif - /* * Definition of address layouts for PCI Config mechanism #1 * XXX- These largely duplicate PCI_TYPE1 constants at the top @@ -240,4 +288,139 @@ extern void pci_write(void * address, int data, int type); #define PCI_IO_MAP_INCR 0x1000 #endif /* CONFIG_SGI_IP32 */ +/* + * Class codes + */ +#define PCI_CFG_CLASS_PRE20 0x00 +#define PCI_CFG_CLASS_STORAGE 0x01 +#define PCI_CFG_CLASS_NETWORK 0x02 +#define PCI_CFG_CLASS_DISPLAY 0x03 +#define PCI_CFG_CLASS_MMEDIA 0x04 +#define PCI_CFG_CLASS_MEMORY 0x05 +#define PCI_CFG_CLASS_BRIDGE 0x06 +#define PCI_CFG_CLASS_COMM 0x07 +#define PCI_CFG_CLASS_BASE 0x08 +#define PCI_CFG_CLASS_INPUT 0x09 +#define PCI_CFG_CLASS_DOCK 0x0A +#define PCI_CFG_CLASS_PROC 0x0B +#define PCI_CFG_CLASS_SERIALBUS 0x0C +#define PCI_CFG_CLASS_OTHER 0xFF + +/* + * Important Subclasses + */ +#define PCI_CFG_SUBCLASS_BRIDGE_HOST 0x00 +#define PCI_CFG_SUBCLASS_BRIDGE_ISA 0x01 +#define PCI_CFG_SUBCLASS_BRIDGE_EISA 0x02 +#define PCI_CFG_SUBCLASS_BRIDGE_MC 0x03 +#define PCI_CFG_SUBCLASS_BRIDGE_PCI 0x04 +#define PCI_CFG_SUBCLASS_BRIDGE_PCMCIA 0x05 +#define PCI_CFG_SUBCLASS_BRIDGE_NUBUS 0x06 +#define PCI_CFG_SUBCLASS_BRIDGE_CARDBUS 0x07 +#define PCI_CFG_SUBCLASS_BRIDGE_OTHER 0x80 + +#ifndef __ASSEMBLY__ + +/* + * PCI config space definition + */ +typedef volatile struct pci_cfg_s { + uint16_t dev_id; + uint16_t vendor_id; + uint16_t status; + uint16_t cmd; + uchar_t class; + uchar_t sub_class; + uchar_t prog_if; + uchar_t rev; + uchar_t bist; + uchar_t hdr_type; + uchar_t lt; + uchar_t line_size; + uint32_t bar[6]; + uint32_t cardbus; + uint16_t subsys_dev_id; + uint16_t subsys_vendor_id; + uint32_t exp_rom; + uint32_t res[2]; + uchar_t max_lat; + uchar_t min_gnt; + uchar_t int_pin; + uchar_t int_line; +} pci_cfg_t; + +/* + * PCI Type 1 config space definition for PCI to PCI Bridges (PPBs) + */ +typedef volatile struct pci_cfg1_s { + uint16_t dev_id; + uint16_t vendor_id; + uint16_t status; + uint16_t cmd; + uchar_t class; + uchar_t sub_class; + uchar_t prog_if; + uchar_t rev; + uchar_t bist; + uchar_t hdr_type; + uchar_t lt; + uchar_t line_size; + uint32_t bar[2]; + uchar_t slt; + uchar_t sub_bus_num; + uchar_t snd_bus_num; + uchar_t pri_bus_num; + uint16_t snd_status; + uchar_t io_limit; + uchar_t io_base; + uint16_t mem_limit; + uint16_t mem_base; + uint16_t pmem_limit; + uint16_t pmem_base; + uint32_t pmem_limit_upper; + uint32_t pmem_base_upper; + uint16_t io_limit_upper; + uint16_t io_base_upper; + uint32_t res; + uint32_t exp_rom; + uint16_t ppb_control; + uchar_t int_pin; + uchar_t int_line; +} pci_cfg1_t; + +/* + * PCI-X Capability + */ +typedef volatile struct cap_pcix_cmd_reg_s { + uint16_t reserved1: 9, + max_split: 3, + max_mem_read_cnt: 2, + enable_relaxed_order: 1, + data_parity_enable: 1; +} cap_pcix_cmd_reg_t; + +typedef volatile struct cap_pcix_stat_reg_s { + uint32_t reserved1: 2, + split_complt_err: 1, + max_cum_read: 3, + max_out_split: 3, + max_mem_read_cnt: 2, + device_complex: 1, + unexpect_split_complt: 1, + split_complt_discard: 1, + mhz133_capable: 1, + bit64_device: 1, + bus_num: 8, + dev_num: 5, + func_num: 3; +} cap_pcix_stat_reg_t; + +typedef volatile struct cap_pcix_type0_s { + cap_pcix_cmd_reg_t pcix_type0_command; + uchar_t pcix_cap_nxt; + uchar_t pcix_cap_id; + cap_pcix_stat_reg_t pcix_type0_status; +} cap_pcix_type0_t; + +#endif /* __ASSEMBLY__ */ #endif /* _ASM_SN_PCI_PCI_DEFS_H */ diff --git a/include/asm-ia64/sn/pci/pciba.h b/include/asm-ia64/sn/pci/pciba.h index e7acd399b6ba..f8b16a2033e9 100644 --- a/include/asm-ia64/sn/pci/pciba.h +++ b/include/asm-ia64/sn/pci/pciba.h @@ -91,6 +91,13 @@ typedef u_int32_t uint32_t; #define PCIIOCDMAALLOC _IOWR(0,1,uint64_t) #define PCIIOCDMAFREE _IOW(0,1,uint64_t) +/* pio cache-mode ioctl defines. current only uncached accelerated */ +#define PCIBA_CACHE_MODE_SET 1 +#define PCIBA_CACHE_MODE_CLEAR 2 +#ifdef PIOMAP_UNC_ACC +#define PCIBA_UNCACHED_ACCEL PIOMAP_UNC_ACC +#endif + /* The parameter for PCIIOCDMAALLOC needs to contain * both the size of the request and the flag values * to be used in setting up the DMA. diff --git a/include/asm-ia64/sn/pci/pcibr.h b/include/asm-ia64/sn/pci/pcibr.h index b834fed50f1a..c29d13c49fb7 100644 --- a/include/asm-ia64/sn/pci/pcibr.h +++ b/include/asm-ia64/sn/pci/pcibr.h @@ -11,6 +11,7 @@ #if defined(__KERNEL__) +#include <linux/config.h> #include <asm/sn/dmamap.h> #include <asm/sn/driver.h> #include <asm/sn/pio.h> @@ -75,6 +76,7 @@ extern int pcibr_attach(devfs_handle_t); */ extern pciio_provider_t pcibr_provider; +extern pciio_provider_t pci_pic_provider; /* ===================================================================== * secondary entry points: pcibr PCI bus provider @@ -182,7 +184,11 @@ extern pcibr_intr_t pcibr_intr_alloc(devfs_handle_t dev, extern void pcibr_intr_free(pcibr_intr_t intr); +#ifdef CONFIG_IA64_SGI_SN1 extern int pcibr_intr_connect(pcibr_intr_t intr); +#else +extern int pcibr_intr_connect(pcibr_intr_t intr, intr_func_t, intr_arg_t); +#endif extern void pcibr_intr_disconnect(pcibr_intr_t intr); @@ -215,9 +221,11 @@ extern void pcibr_config_set(devfs_handle_t conn, extern int pcibr_error_devenable(devfs_handle_t pconn_vhdl, int error_code); +#ifdef PIC_LATER extern pciio_slot_t pcibr_error_extract(devfs_handle_t pcibr_vhdl, pciio_space_t *spacep, iopaddr_t *addrp); +#endif extern int pcibr_wrb_flush(devfs_handle_t pconn_vhdl); extern int pcibr_rrb_check(devfs_handle_t pconn_vhdl, @@ -226,11 +234,13 @@ extern int pcibr_rrb_check(devfs_handle_t pconn_vhdl, int *count_reserved, int *count_pool); +#ifndef CONFIG_IA64_SGI_SN1 extern int pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd, int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2, int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4); +#endif typedef void rrb_alloc_funct_f (devfs_handle_t xconn_vhdl, @@ -340,7 +350,11 @@ extern void pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t); extern void pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong); extern void pcibr_hints_handsoff(devfs_handle_t); +#ifdef CONFIG_IA64_SGI_SN1 typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t); +#else +typedef unsigned pcibr_intr_bits_f(pciio_info_t, pciio_intr_line_t, int); +#endif extern void pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *); extern int pcibr_asic_rev(devfs_handle_t); @@ -414,13 +428,9 @@ struct pcibr_slot_down_resp_s { char resp_l1_msg[L1_QSIZE + 1]; }; -struct pcibr_slot_info_req_s { - int req_slot; - pcibr_slot_info_resp_t req_respp; - int req_size; -}; - struct pcibr_slot_info_resp_s { + short resp_bs_bridge_type; + short resp_bs_bridge_mode; int resp_has_host; char resp_host_slot; devfs_handle_t resp_slot_conn; @@ -438,17 +448,22 @@ struct pcibr_slot_info_resp_s { unsigned resp_bss_d64_flags; iopaddr_t resp_bss_d32_base; unsigned resp_bss_d32_flags; - int resp_bss_ext_ates_active; + atomic_t resp_bss_ext_ates_active; volatile unsigned *resp_bss_cmd_pointer; unsigned resp_bss_cmd_shadow; int resp_bs_rrb_valid; - int resp_bs_rrb_valid_v; + int resp_bs_rrb_valid_v1; + int resp_bs_rrb_valid_v2; + int resp_bs_rrb_valid_v3; int resp_bs_rrb_res; bridgereg_t resp_b_resp; bridgereg_t resp_b_int_device; bridgereg_t resp_b_int_enable; bridgereg_t resp_b_int_host; - +#ifndef CONFIG_IA64_SGI_SN1 + picreg_t resp_p_int_enable; + picreg_t resp_p_int_host; +#endif struct pcibr_slot_func_info_resp_s { int resp_f_status; char resp_f_slot_name[MAXDEVNAME]; @@ -507,6 +522,9 @@ struct pcibr_slot_info_resp_s { #define PCI_SLOT_RRB_ALLOC_ERR 24 /* slot initial rrb alloc error */ #define PCI_SLOT_DRV_ATTACH_ERR 25 /* driver attach error */ #define PCI_SLOT_DRV_DETACH_ERR 26 /* driver detach error */ +/* EFBIG 27 */ +#define PCI_MULTI_FUNC_ERR 28 /* multi-function card error */ +#define PCI_SLOT_RBAR_ALLOC_ERR 29 /* slot PCI-X RBAR alloc error */ /* ERANGE 34 */ /* EUNATCH 42 */ diff --git a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h index c44ff76dce77..183a7e9adfec 100644 --- a/include/asm-ia64/sn/pci/pcibr_private.h +++ b/include/asm-ia64/sn/pci/pcibr_private.h @@ -15,6 +15,7 @@ * should ever peek into this file. */ +#include <linux/config.h> #include <asm/sn/pci/pcibr.h> #include <asm/sn/pci/pciio_private.h> #include <asm/sn/ksys/l1.h> @@ -34,6 +35,68 @@ typedef struct pcibr_intr_list_s *pcibr_intr_list_t; typedef struct pcibr_intr_wrap_s *pcibr_intr_wrap_t; typedef struct pcibr_intr_cbuf_s *pcibr_intr_cbuf_t; +typedef volatile unsigned *cfg_p; +typedef volatile bridgereg_t *reg_p; + +/* + * extern functions + */ +cfg_p pcibr_slot_config_addr(bridge_t *, pciio_slot_t, int); +cfg_p pcibr_func_config_addr(bridge_t *, pciio_bus_t bus, pciio_slot_t, pciio_function_t, int); +unsigned pcibr_slot_config_get(bridge_t *, pciio_slot_t, int); +unsigned pcibr_func_config_get(bridge_t *, pciio_slot_t, pciio_function_t, int); +void pcibr_debug(uint32_t, devfs_handle_t, char *, ...); +void pcibr_slot_config_set(bridge_t *, pciio_slot_t, int, unsigned); +void pcibr_func_config_set(bridge_t *, pciio_slot_t, pciio_function_t, int, + unsigned); +/* + * PCIBR_DEBUG() macro and debug bitmask defines + */ +/* low freqency debug events (ie. initialization, resource allocation,...) */ +#define PCIBR_DEBUG_INIT 0x00000001 /* bridge init */ +#define PCIBR_DEBUG_HINTS 0x00000002 /* bridge hints */ +#define PCIBR_DEBUG_ATTACH 0x00000004 /* bridge attach */ +#define PCIBR_DEBUG_DETACH 0x00000008 /* bridge detach */ +#define PCIBR_DEBUG_ATE 0x00000010 /* bridge ATE allocation */ +#define PCIBR_DEBUG_RRB 0x00000020 /* bridge RRB allocation */ +#define PCIBR_DEBUG_RBAR 0x00000040 /* bridge RBAR allocation */ +#define PCIBR_DEBUG_PROBE 0x00000080 /* bridge device probing */ +#define PCIBR_DEBUG_INTR_ERROR 0x00000100 /* bridge error interrupt */ +#define PCIBR_DEBUG_ERROR_HDLR 0x00000200 /* bridge error handler */ +#define PCIBR_DEBUG_CONFIG 0x00000400 /* device's config space */ +#define PCIBR_DEBUG_BAR 0x00000800 /* device's BAR allocations */ +#define PCIBR_DEBUG_INTR_ALLOC 0x00001000 /* device's intr allocation */ +#define PCIBR_DEBUG_DEV_ATTACH 0x00002000 /* device's attach */ +#define PCIBR_DEBUG_DEV_DETACH 0x00004000 /* device's detach */ +#define PCIBR_DEBUG_HOTPLUG 0x00008000 + +/* high freqency debug events (ie. map allocation, direct translation,...) */ +#define PCIBR_DEBUG_DEVREG 0x04000000 /* bridges device reg sets */ +#define PCIBR_DEBUG_PIOMAP 0x08000000 /* pcibr_piomap */ +#define PCIBR_DEBUG_PIODIR 0x10000000 /* pcibr_piotrans */ +#define PCIBR_DEBUG_DMAMAP 0x20000000 /* pcibr_dmamap */ +#define PCIBR_DEBUG_DMADIR 0x40000000 /* pcibr_dmatrans */ +#define PCIBR_DEBUG_INTR 0x80000000 /* interrupts */ + +extern char *pcibr_debug_module; +extern int pcibr_debug_widget; +extern int pcibr_debug_slot; +extern uint32_t pcibr_debug_mask; + +/* For low frequency events (ie. initialization, resource allocation,...) */ +#define PCIBR_DEBUG_ALWAYS(args) pcibr_debug args ; + +/* XXX: habeck: maybe make PCIBR_DEBUG() always available? Even in non- + * debug kernels? If tracing isn't enabled (i.e pcibr_debug_mask isn't + * set, then the overhead for this macro is just an extra 'if' check. + */ +/* For high frequency events (ie. map allocation, direct translation,...) */ +#if 1 || DEBUG +#define PCIBR_DEBUG(args) PCIBR_DEBUG_ALWAYS(args) +#else /* DEBUG */ +#define PCIBR_DEBUG(args) +#endif /* DEBUG */ + /* * Bridge sets up PIO using this information. */ @@ -100,6 +163,8 @@ struct pcibr_intr_s { #define bi_flags bi_pi.pi_flags /* PCIBR_INTR flags */ #define bi_dev bi_pi.pi_dev /* associated pci card */ #define bi_lines bi_pi.pi_lines /* which PCI interrupt line(s) */ +#define bi_func bi_pi.pi_func /* handler function (when connected) */ +#define bi_arg bi_pi.pi_arg /* handler parameter (when connected) */ #define bi_mustruncpu bi_pi.pi_mustruncpu /* Where we must run. */ #define bi_irq bi_pi.pi_irq /* IRQ assigned. */ #define bi_cpu bi_pi.pi_cpu /* cpu assigned. */ @@ -108,9 +173,43 @@ struct pcibr_intr_s { struct pcibr_intr_cbuf_s bi_ibuf; /* circular buffer of wrap ptrs */ }; + +/* + * PCIBR_INFO_SLOT_GET_EXT returns the external slot number that the card + * resides in. (i.e the slot number silk screened on the back of the I/O + * brick). PCIBR_INFO_SLOT_GET_INT returns the internal slot (or device) + * number used by the pcibr code to represent that external slot (i.e to + * set bit patterns in BRIDGE/PIC registers to represent the device, or to + * offset into an array, or ...). + * + * In BRIDGE and XBRIDGE the external slot and internal device numbering + * are the same. (0->0, 1->1, 2->2,... 7->7) BUT in the PIC the external + * slot number is always 1 greater than the internal device number (1->0, + * 2->1, 3->2, 4->3). This is due to the fact that the PCI-X spec requires + * that the 'bridge' (i.e PIC) be designated as 'device 0', thus external + * slot numbering can't start at zero. + * + * PCIBR_DEVICE_TO_SLOT converts an internal device number to an external + * slot number. NOTE: PCIIO_SLOT_NONE stays as PCIIO_SLOT_NONE. + * + * PCIBR_SLOT_TO_DEVICE converts an external slot number to an internal + * device number. NOTE: PCIIO_SLOT_NONE stays as PCIIO_SLOT_NONE. + */ +#define PCIBR_INFO_SLOT_GET_EXT(info) (((pcibr_info_t)info)->f_slot) +#define PCIBR_INFO_SLOT_GET_INT(info) (((pcibr_info_t)info)->f_dev) + +#define PCIBR_DEVICE_TO_SLOT(pcibr_soft, dev_num) \ + (((dev_num) != PCIIO_SLOT_NONE) ? \ + (IS_PIC_SOFT((pcibr_soft)) ? ((dev_num) + 1) : (dev_num)) : \ + PCIIO_SLOT_NONE) + +#define PCIBR_SLOT_TO_DEVICE(pcibr_soft, slot) \ + (((slot) != PCIIO_SLOT_NONE) ? \ + (IS_PIC_SOFT((pcibr_soft)) ? ((slot) - 1) : (slot)) : \ + PCIIO_SLOT_NONE) + /* - * per-connect point pcibr data, including - * standard pciio data in-line: + * per-connect point pcibr data, including standard pciio data in-line: */ struct pcibr_info_s { struct pciio_info_s f_c; /* MUST BE FIRST. */ @@ -125,15 +224,18 @@ struct pcibr_info_s { #define f_pops f_c.c_pops /* cached provider from c_master */ #define f_efunc f_c.c_efunc /* error handling function */ #define f_einfo f_c.c_einfo /* first parameter for efunc */ -#define f_window f_c.c_window /* state of BASE regs */ -#define f_rbase f_c.c_rbase /* expansion rom base */ -#define f_rsize f_c.c_rsize /* expansion rom size */ -#define f_piospace f_c.c_piospace /* additional I/O spaces allocated */ +#define f_window f_c.c_window /* state of BASE regs */ +#define f_rwindow f_c.c_rwindow /* expansion ROM BASE regs */ +#define f_rbase f_c.c_rbase /* expansion ROM base */ +#define f_rsize f_c.c_rsize /* expansion ROM size */ +#define f_piospace f_c.c_piospace /* additional I/O spaces allocated */ /* pcibr-specific connection state */ int f_ibit[4]; /* Bridge bit for each INTx */ pcibr_piomap_t f_piomap; int f_att_det_error; + pciio_slot_t f_dev; /* which device the card represents */ + cap_pcix_type0_t *f_pcix_cap; /* pointer to the pcix capability */ }; /* ===================================================================== @@ -152,15 +254,91 @@ struct pcibr_intr_list_s { struct pcibr_intr_wrap_s { pcibr_soft_t iw_soft; /* which bridge */ volatile bridgereg_t *iw_stat; /* ptr to b_int_status */ +#ifdef CONFIG_IA64_SGI_SN1 bridgereg_t iw_intr; /* bit in b_int_status */ +#else + bridgereg_t iw_ibit; /* bit in b_int_status */ +#endif pcibr_intr_list_t iw_list; /* ghostbusters! */ int iw_hdlrcnt; /* running handler count */ int iw_shared; /* if Bridge bit is shared */ int iw_connected; /* if already connected */ }; -#define PCIBR_ISR_ERR_START 8 -#define PCIBR_ISR_MAX_ERRS 32 +#define PCIBR_ISR_ERR_START 8 +#define PCIBR_ISR_MAX_ERRS_BRIDGE 32 +#define PCIBR_ISR_MAX_ERRS_PIC 45 +#define PCIBR_ISR_MAX_ERRS PCIBR_ISR_MAX_ERRS_PIC + +/* + * PCI Base Address Register window allocation constants. + * To reduce the size of the internal resource mapping structures, do + * not use the entire PCI bus I/O address space + */ +#define PCIBR_BUS_IO_BASE 0x100000 +#define PCIBR_BUS_IO_MAX 0x0FFFFFFF +#define PCIBR_BUS_IO_PAGE 0x100000 + +#define PCIBR_BUS_SWIN_BASE _PAGESZ +#define PCIBR_BUS_SWIN_MAX 0x000FFFFF +#define PCIBR_BUS_SWIN_PAGE _PAGESZ + +#define PCIBR_BUS_MEM_BASE 0x200000 +#define PCIBR_BUS_MEM_MAX 0x3FFFFFFF +#define PCIBR_BUS_MEM_PAGE 0x100000 + +/* defines for pcibr_soft_s->bs_bridge_type */ +#define PCIBR_BRIDGETYPE_BRIDGE 0 +#define PCIBR_BRIDGETYPE_XBRIDGE 1 +#define PCIBR_BRIDGETYPE_PIC 2 +#define IS_XBRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_XBRIDGE) +#define IS_PIC_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_PIC) +#define IS_BRIDGE_SOFT(ps) (ps->bs_bridge_type == PCIBR_BRIDGETYPE_BRIDGE) +#define IS_XBRIDGE_OR_PIC_SOFT(ps) (IS_XBRIDGE_SOFT(ps) || IS_PIC_SOFT(ps)) + +/* + * Runtime checks for workarounds. + */ +#define PCIBR_WAR_ENABLED(pv, pcibr_soft) \ + ((1 << XWIDGET_PART_REV_NUM_REV(pcibr_soft->bs_rev_num)) & pv) +/* + * Defines for individual WARs. Each is a bitmask of applicable + * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B, etc. + */ +#define PV854697 (~0) /* PIC: write 64bit regs as 64bits. permanent */ +#define PV854827 (~0) /* PIC: fake widget 0xf presence bit. permanent */ +#define PV855271 (~0) /* PIC: use virt chan iff 64-bit device. permanent */ +#define PV855272 (1 << 1) /* PIC: runaway interrupt WAR */ +#define PV856155 (1 << 1) /* PIC: arbitration WAR */ +#define PV856864 (1 << 1) /* PIC: lower timeout to free TNUMs quicker */ +#define PV856866 (1 << 1) /* PIC: avoid rrb's 0/1/8/9. */ +#define PV862253 (1 << 1) /* PIC: don't enable write req RAM parity checking */ +#define PV867308 (3 << 1) /* PIC: make LLP error interrupts FATAL for PIC */ + + +/* defines for pcibr_soft_s->bs_bridge_mode */ +#define PCIBR_BRIDGEMODE_PCI_33 0x0 +#define PCIBR_BRIDGEMODE_PCI_66 0x2 +#define PCIBR_BRIDGEMODE_PCIX_66 0x3 +#define PCIBR_BRIDGEMODE_PCIX_100 0x5 +#define PCIBR_BRIDGEMODE_PCIX_133 0x7 +#define BUSSPEED_MASK 0x6 +#define BUSTYPE_MASK 0x1 + +#define IS_PCI(ps) (!IS_PCIX(ps)) +#define IS_PCIX(ps) ((ps)->bs_bridge_mode & BUSTYPE_MASK) + +#define IS_33MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCI_33) +#define IS_66MHZ(ps) (((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCI_66) || \ + ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_66)) +#define IS_100MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_100) +#define IS_133MHZ(ps) ((ps)->bs_bridge_mode == PCIBR_BRIDGEMODE_PCIX_133) + + +/* Number of PCI slots. NOTE: this works as long as the first slot + * is zero. Otherwise use ((ps->bs_max_slot+1) - ps->bs_min_slot) + */ +#define PCIBR_NUM_SLOTS(ps) (ps->bs_max_slot+1) /* ===================================================================== * Bridge Device State structure @@ -172,7 +350,7 @@ struct pcibr_intr_wrap_s { struct pcibr_soft_s { devfs_handle_t bs_conn; /* xtalk connection point */ devfs_handle_t bs_vhdl; /* vertex owned by pcibr */ - int bs_int_enable; /* Mask of enabled intrs */ + uint64_t bs_int_enable; /* Mask of enabled intrs */ bridge_t *bs_base; /* PIO pointer to Bridge chip */ char *bs_name; /* hw graph name */ xwidgetnum_t bs_xid; /* Bridge's xtalk ID number */ @@ -180,7 +358,11 @@ struct pcibr_soft_s { xwidgetnum_t bs_mxid; /* master's xtalk ID number */ pciio_slot_t bs_first_slot; /* first existing slot */ pciio_slot_t bs_last_slot; /* last existing slot */ - + pciio_slot_t bs_last_reset; /* last slot to reset */ + pciio_slot_t bs_min_slot; /* lowest possible slot */ + pciio_slot_t bs_max_slot; /* highest possible slot */ + pcibr_soft_t bs_peers_soft; /* PICs other bus's soft */ + int bs_busnum; /* PIC has two pci busses */ iopaddr_t bs_dir_xbase; /* xtalk address for 32-bit PCI direct map */ xwidgetnum_t bs_dir_xport; /* xtalk port for 32-bit PCI direct map */ @@ -188,14 +370,23 @@ struct pcibr_soft_s { struct map *bs_int_ate_map; /* rmalloc map for internal ATEs */ struct map *bs_ext_ate_map; /* rmalloc map for external ATEs */ short bs_int_ate_size; /* number of internal ates */ - short bs_xbridge; /* if 1 then xbridge */ - + short bs_bridge_type; /* see defines above */ + short bs_bridge_mode; /* see defines above */ +#ifdef CONFIG_IA64_SGI_SN1 +#define bs_xbridge bs_bridge_type +#endif int bs_rev_num; /* revision number of Bridge */ - unsigned bs_dma_flags; /* revision-implied DMA flags */ + /* bs_dma_flags are the forced dma flags used on all DMAs. Used for + * working around ASIC rev issues and protocol specific requirements + */ + unsigned bs_dma_flags; /* forced DMA flags */ +#ifdef CONFIG_IA64_SGI_SN1 l1sc_t *bs_l1sc; /* io brick l1 system cntr */ +#endif moduleid_t bs_moduleid; /* io brick moduleid */ + short bs_bricktype; /* io brick type */ /* * Lock used primarily to get mutual exclusion while managing any @@ -222,7 +413,8 @@ struct pcibr_soft_s { pciio_slot_t host_slot; devfs_handle_t slot_conn; - int slot_status; + /* PCI Hot-Plug status word */ + int slot_status; /* Potentially several connection points * for this slot. bss_ninfo is how many, @@ -299,24 +491,53 @@ struct pcibr_soft_s { pcibr_intr_bits_f *bs_intr_bits; + /* PIC PCI-X Read Buffer Management : + * bs_pcix_num_funcs: the total number of PCI-X functions + * on the bus + * bs_pcix_split_tot: total number of outstanding split + * transactions requested by all functions on the bus + * bs_pcix_rbar_percent_allowed: the percentage of the + * total number of buffers a function requested that are + * available to it, not including the 1 RBAR guaranteed + * to it. + * bs_pcix_rbar_inuse: number of RBARs in use. + * bs_pcix_rbar_avail: number of RBARs available. NOTE: + * this value can go negative if we oversubscribe the + * RBARs. (i.e. We have 16 RBARs but 17 functions). + */ + int bs_pcix_num_funcs; + int bs_pcix_split_tot; + int bs_pcix_rbar_percent_allowed; + + int bs_pcix_rbar_inuse; + int bs_pcix_rbar_avail; + + /* RRB MANAGEMENT * bs_rrb_fixed: bitmap of slots whose RRB * allocations we should not "automatically" change * bs_rrb_avail: number of RRBs that have not * been allocated or reserved for {even,odd} slots - * bs_rrb_res: number of RRBs reserved for the + * bs_rrb_res: number of RRBs currently reserved for the * use of the index slot number - * bs_rrb_valid: number of RRBs marked valid - * for the indexed slot number; indexes 8-15 - * are for the virtual channels for slots 0-7. + * bs_rrb_res_dflt: number of RRBs reserved at boot + * time for the use of the index slot number + * bs_rrb_valid: number of RRBs currently marked valid + * for the indexed slot/vchan number; array[slot][vchan] + * bs_rrb_valid_dflt: number of RRBs marked valid at boot + * time for the indexed slot/vchan number; array[slot][vchan] */ int bs_rrb_fixed; - int bs_rrb_avail[2]; - int bs_rrb_res[8]; + int bs_rrb_avail[2]; + int bs_rrb_res[8]; int bs_rrb_res_dflt[8]; +#ifdef CONFIG_IA64_SGI_SN1 int bs_rrb_valid[16]; int bs_rrb_valid_dflt[16]; - +#else + int bs_rrb_valid[8][4]; + int bs_rrb_valid_dflt[8][4]; +#endif struct { /* Each Bridge interrupt bit has a single XIO * interrupt channel allocated. @@ -347,35 +568,55 @@ struct pcibr_soft_s { * Note that there is no locking while looking at this data structure. * There should not be any race between bus error code and * error interrupt code.. will look into this if needed. + * + * NOTE: The above discussion of error interrupt processing is + * no longer true. Whether it should again be true, is + * being looked into. */ struct br_errintr_info { int bserr_toutcnt; #ifdef LATER toid_t bserr_toutid; /* Timeout started by errintr */ -#endif - iopaddr_t bserr_addr; /* Address where error occurred */ - bridgereg_t bserr_intstat; /* interrupts active at error time */ +#endif /* LATER */ + iopaddr_t bserr_addr; /* Address where error occured */ + uint64_t bserr_intstat; /* interrupts active at error dump */ } bs_errinfo; /* * PCI Bus Space allocation data structure. - * This info is used to satisfy the callers of pcibr_piospace_alloc - * interface. Most of these users need "large" amounts of PIO - * space (typically in Megabytes), and they generally tend to - * take once and never release.. - * For Now use a simple algorithm to manage it. On allocation, - * Update the _base field to reflect next free address. * - * Freeing does nothing.. So, once allocated, it's gone for good. + * The resource mapping functions rmalloc() and rmfree() are used + * to manage the PCI bus I/O, small window, and memory address + * spaces. + * + * This info is used to assign PCI bus space addresses to cards + * via their BARs and to the callers of the pcibr_piospace_alloc() + * interface. + * + * Users of the pcibr_piospace_alloc() interface, such as the VME + * Universe chip, need PCI bus space that is not acquired by BARs. + * Most of these users need "large" amounts of PIO space (typically + * in Megabytes), and they generally tend to take once and never + * release. */ +#ifdef CONFIG_IA64_SGI_SN1 struct br_pcisp_info { - iopaddr_t pci_io_base; - iopaddr_t pci_io_last; - iopaddr_t pci_swin_base; - iopaddr_t pci_swin_last; - iopaddr_t pci_mem_base; - iopaddr_t pci_mem_last; + iopaddr_t pci_io_base; + iopaddr_t pci_io_last; + iopaddr_t pci_swin_base; + iopaddr_t pci_swin_last; + iopaddr_t pci_mem_base; + iopaddr_t pci_mem_last; } bs_spinfo; +#endif /* CONFIG_IA64_SGI_SN1 */ + struct pciio_win_map_s bs_io_win_map; /* I/O addr space */ + struct pciio_win_map_s bs_swin_map; /* Small window addr space */ + struct pciio_win_map_s bs_mem_win_map; /* Memory addr space */ + + int bs_bus_addr_status; /* Bus space status */ + +#define PCIBR_BUS_ADDR_MEM_FREED 1 /* Reserved PROM mem addr freed */ +#define PCIBR_BUS_ADDR_IO_FREED 2 /* Reserved PROM I/O addr freed */ struct bs_errintr_stat_s { uint32_t bs_errcount_total; @@ -437,13 +678,6 @@ extern int pcibr_prefetch_enable_rev, pcibr_wg_enable_rev; #define pcibr_soft_get(v) ((pcibr_soft_t)hwgraph_fastinfo_get((v))) #define pcibr_soft_set(v,i) (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i))) -/* Use io spin locks. This ensures that all the PIO writes from a particular - * CPU to a particular IO device are synched before the start of the next - * set of PIO operations to the same device. - */ -#define pcibr_lock(pcibr_soft) io_splock(&pcibr_soft->bs_lock) -#define pcibr_unlock(pcibr_soft,s) io_spunlock(&pcibr_soft->bs_lock,s) - /* * mem alloc/free macros */ @@ -455,13 +689,37 @@ extern int pcibr_prefetch_enable_rev, pcibr_wg_enable_rev; #define NEW(ptr) NEWA(ptr,1) #define DEL(ptr) DELA(ptr,1) -typedef volatile unsigned *cfg_p; -typedef volatile bridgereg_t *reg_p; +#ifndef CONFIG_IA64_SGI_SN1 +/* + * Additional PIO spaces per slot are + * recorded in this structure. + */ +struct pciio_piospace_s { + pciio_piospace_t next; /* another space for this device */ + char free; /* 1 if free, 0 if in use */ + pciio_space_t space; /* Which space is in use */ + iopaddr_t start; /* Starting address of the PIO space */ + size_t count; /* size of PIO space */ +}; +#endif /* CONFIG_IA64_SGI_SN1 */ -#define PCIBR_RRB_SLOT_VIRTUAL 8 -#define PCIBR_VALID_SLOT(s) (s < 8) +/* Use io spin locks. This ensures that all the PIO writes from a particular + * CPU to a particular IO device are synched before the start of the next + * set of PIO operations to the same device. + */ +#ifdef PCI_LATER +#define pcibr_lock(pcibr_soft) io_splock(pcibr_soft->bs_lock) +#define pcibr_unlock(pcibr_soft, s) io_spunlock(pcibr_soft->bs_lock,s) +#else +#define pcibr_lock(pcibr_soft) 1 +#define pcibr_unlock(pcibr_soft, s) +#endif /* PCI_LATER */ + +#ifndef CONFIG_IA64_SGI_SN1 +#define PCIBR_VALID_SLOT(ps, s) (s < PCIBR_NUM_SLOTS(ps)) #define PCIBR_D64_BASE_UNSET (0xFFFFFFFFFFFFFFFF) #define PCIBR_D32_BASE_UNSET (0xFFFFFFFF) +#endif #define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev" #define PCIBR_SOFT_LIST 1 diff --git a/include/asm-ia64/sn/pci/pciio.h b/include/asm-ia64/sn/pci/pciio.h index 43e610545424..b48737b2800b 100644 --- a/include/asm-ia64/sn/pci/pciio.h +++ b/include/asm-ia64/sn/pci/pciio.h @@ -13,6 +13,7 @@ * pciio.h -- platform-independent PCI interface */ +#include <linux/config.h> #include <asm/sn/ioerror.h> #include <asm/sn/driver.h> #include <asm/sn/hcl.h> @@ -207,6 +208,9 @@ typedef struct pciio_dmamap_s *pciio_dmamap_t; typedef struct pciio_intr_s *pciio_intr_t; typedef struct pciio_info_s *pciio_info_t; typedef struct pciio_piospace_s *pciio_piospace_t; +typedef struct pciio_win_info_s *pciio_win_info_t; +typedef struct pciio_win_map_s *pciio_win_map_t; +typedef struct pciio_win_alloc_s *pciio_win_alloc_t; /* PIO MANAGEMENT */ @@ -382,8 +386,13 @@ pciio_intr_alloc_f (devfs_handle_t dev, /* which PCI device */ typedef void pciio_intr_free_f (pciio_intr_t intr_hdl); +#ifdef CONFIG_IA64_SGI_SN1 typedef int pciio_intr_connect_f (pciio_intr_t intr_hdl); /* pciio intr resource handle */ +#else +typedef int +pciio_intr_connect_f (pciio_intr_t intr_hdl, intr_func_t intr_func, intr_arg_t intr_arg); /* pciio intr resource handle */ +#endif typedef void pciio_intr_disconnect_f (pciio_intr_t intr_hdl); @@ -627,6 +636,44 @@ pciio_device_detach( devfs_handle_t pcicard, /* vertex created by pciio_device_register */ int drv_flags); + +/* create and initialize empty window mapping resource */ +extern pciio_win_map_t +pciio_device_win_map_new(pciio_win_map_t win_map, /* preallocated win map structure */ + size_t region_size, /* size of region to be tracked */ + size_t page_size); /* allocation page size */ + +/* destroy window mapping resource freeing up ancillary resources */ +extern void +pciio_device_win_map_free(pciio_win_map_t win_map); /* preallocated win map structure */ + +/* populate window mapping with free range of addresses */ +extern void +pciio_device_win_populate(pciio_win_map_t win_map, /* win map */ + iopaddr_t ioaddr, /* base address of free range */ + size_t size); /* size of free range */ + +/* allocate window from mapping resource */ +#ifdef CONFIG_IA64_SGI_SN1 +extern iopaddr_t +pciio_device_win_alloc(pciio_win_map_t win_map, /* win map */ + pciio_win_alloc_t win_alloc, /* opaque allocation cookie */ + size_t size, /* size of allocation */ + size_t align); /* alignment of allocation */ +#else +extern iopaddr_t +pciio_device_win_alloc(pciio_win_map_t win_map, /* win map */ + pciio_win_alloc_t win_alloc, /* opaque allocation cookie */ + size_t start, /* start unit, or 0 */ + size_t size, /* size of allocation */ + size_t align); /* alignment of allocation */ +#endif + +/* free previously allocated window */ +extern void +pciio_device_win_free(pciio_win_alloc_t win_alloc); /* opaque allocation cookie */ + + /* * Generic PCI interface, for use with all PCI providers * and all PCI devices. @@ -644,52 +691,6 @@ extern iopaddr_t pciio_pio_pciaddr_get(pciio_piomap_t pciio_piomap); extern ulong pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap); extern caddr_t pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap); -#ifdef LATER -#ifdef USE_PCI_PIO -extern uint8_t pciio_pio_read8(volatile uint8_t *addr); -extern uint16_t pciio_pio_read16(volatile uint16_t *addr); -extern uint32_t pciio_pio_read32(volatile uint32_t *addr); -extern uint64_t pciio_pio_read64(volatile uint64_t *addr); -extern void pciio_pio_write8(uint8_t val, volatile uint8_t *addr); -extern void pciio_pio_write16(uint16_t val, volatile uint16_t *addr); -extern void pciio_pio_write32(uint32_t val, volatile uint32_t *addr); -extern void pciio_pio_write64(uint64_t val, volatile uint64_t *addr); -#else /* !USE_PCI_PIO */ -__inline uint8_t pciio_pio_read8(volatile uint8_t *addr) -{ - return *addr; -} -__inline uint16_t pciio_pio_read16(volatile uint16_t *addr) -{ - return *addr; -} -__inline uint32_t pciio_pio_read32(volatile uint32_t *addr) -{ - return *addr; -} -__inline uint64_t pciio_pio_read64(volatile uint64_t *addr) -{ - return *addr; -} -__inline void pciio_pio_write8(uint8_t val, volatile uint8_t *addr) -{ - *addr = val; -} -__inline void pciio_pio_write16(uint16_t val, volatile uint16_t *addr) -{ - *addr = val; -} -__inline void pciio_pio_write32(uint32_t val, volatile uint32_t *addr) -{ - *addr = val; -} -__inline void pciio_pio_write64(uint64_t val, volatile uint64_t *addr) -{ - *addr = val; -} -#endif /* USE_PCI_PIO */ -#endif /* LATER */ - /* Generic PCI dma interfaces */ extern devfs_handle_t pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap); @@ -701,8 +702,10 @@ extern pciio_provider_t *pciio_provider_fns_get(devfs_handle_t provider); /* Generic pci slot information access interface */ extern pciio_info_t pciio_info_chk(devfs_handle_t vhdl); extern pciio_info_t pciio_info_get(devfs_handle_t vhdl); +extern pciio_info_t pciio_hostinfo_get(devfs_handle_t vhdl); extern void pciio_info_set(devfs_handle_t vhdl, pciio_info_t widget_info); extern devfs_handle_t pciio_info_dev_get(pciio_info_t pciio_info); +extern devfs_handle_t pciio_info_hostdev_get(pciio_info_t pciio_info); extern pciio_bus_t pciio_info_bus_get(pciio_info_t pciio_info); extern pciio_slot_t pciio_info_slot_get(pciio_info_t pciio_info); extern pciio_function_t pciio_info_function_get(pciio_info_t pciio_info); @@ -718,7 +721,7 @@ extern iopaddr_t pciio_info_bar_base_get(pciio_info_t, int); extern size_t pciio_info_bar_size_get(pciio_info_t, int); extern iopaddr_t pciio_info_rom_base_get(pciio_info_t); extern size_t pciio_info_rom_size_get(pciio_info_t); - +extern int pciio_info_type1_get(pciio_info_t); extern int pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *); extern int pciio_dma_enabled(devfs_handle_t); diff --git a/include/asm-ia64/sn/pci/pciio_private.h b/include/asm-ia64/sn/pci/pciio_private.h index 54cc4e35fefe..57fbd9787152 100644 --- a/include/asm-ia64/sn/pci/pciio_private.h +++ b/include/asm-ia64/sn/pci/pciio_private.h @@ -10,6 +10,7 @@ #define _ASM_SN_PCI_PCIIO_PRIVATE_H #include <asm/sn/pci/pciio.h> +#include <asm/sn/pci/pci_defs.h> /* * pciio_private.h -- private definitions for pciio @@ -49,6 +50,8 @@ struct pciio_intr_s { devfs_handle_t pi_dev; /* associated pci card */ device_desc_t pi_dev_desc; /* override device descriptor */ pciio_intr_line_t pi_lines; /* which interrupt line(s) */ + intr_func_t pi_func; /* handler function (when connected) */ + intr_arg_t pi_arg; /* handler parameter (when connected) */ cpuid_t pi_mustruncpu; /* Where we must run. */ int pi_irq; /* IRQ assigned */ int pi_cpu; /* cpu assigned */ @@ -59,6 +62,39 @@ struct pciio_intr_s { #define PCIIO_INTR_NOTHREAD 2 /* interrupt handler wants to be called at interrupt level */ /* + * Some PCI provider implementations keep track of PCI window Base Address + * Register (BAR) address range assignment via the rmalloc()/rmfree() arena + * management routines. These implementations use the following data + * structure for each allocation address space (e.g. memory, I/O, small + * window, etc.). + * + * The ``page size'' encodes the minimum allocation unit and must be a power + * of 2. The main use of this allocation ``page size'' is to control the + * number of free address ranges that the mapping allocation software will + * need to track. Smaller values will allow more efficient use of the address + * ranges but will result in much larger allocation map structures ... For + * instance, if we want to manage allocations for a 256MB address range, + * choosing a 1MB allocation page size will result in up to 1MB being wasted + * for allocation requests smaller than 1MB. The worst case allocation + * pattern for the allocation software to track would be a pattern of 1MB + * allocated, 1MB free. This results in the need to track up to 128 free + * ranges. + */ +struct pciio_win_map_s { + struct map *wm_map; /* window address map */ + int wm_page_size; /* allocation ``page size'' */ +}; + +/* + * Opaque structure used to keep track of window allocation information. + */ +struct pciio_win_alloc_s { + pciio_win_map_t wa_map; /* window map allocation is from */ + unsigned long wa_base; /* allocation starting page number */ + size_t wa_pages; /* number of pages in allocation */ +}; + +/* * Each PCI Card has one of these. */ @@ -76,17 +112,17 @@ struct pciio_info_s { error_handler_f *c_efunc; /* error handling function */ error_handler_arg_t c_einfo; /* first parameter for efunc */ - struct { /* state of BASE regs */ - pciio_space_t w_space; - iopaddr_t w_base; - size_t w_size; - int w_devio_index; /* DevIO[] register used to - access this window */ - } c_window[6]; - - unsigned c_rbase; /* EXPANSION ROM base addr */ - unsigned c_rsize; /* EXPANSION ROM size (bytes) */ - + struct pciio_win_info_s { /* state of BASE regs */ + pciio_space_t w_space; + iopaddr_t w_base; + size_t w_size; + int w_devio_index; /* DevIO[] register used to + access this window */ + struct pciio_win_alloc_s w_win_alloc; /* window allocation cookie */ + } c_window[PCI_CFG_BASE_ADDRS + 1]; +#define c_rwindow c_window[PCI_CFG_BASE_ADDRS] /* EXPANSION ROM window */ +#define c_rbase c_rwindow.w_base /* EXPANSION ROM base addr */ +#define c_rsize c_rwindow.w_size /* EXPANSION ROM size (bytes) */ pciio_piospace_t c_piospace; /* additional I/O spaces allocated */ }; diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h index c7f433de0b47..20c7772d7427 100644 --- a/include/asm-ia64/sn/pda.h +++ b/include/asm-ia64/sn/pda.h @@ -10,6 +10,7 @@ #include <linux/config.h> #include <linux/cache.h> +#include <asm/percpu.h> #include <asm/system.h> #include <asm/processor.h> #include <asm/page.h> @@ -25,7 +26,14 @@ * all SN per-cpu data structures. */ - +#ifdef BUS_INT_WAR +#define POLL_ENTRIES 50 +typedef struct { + int irq; + int interval; + short tick; +} sn_poll_entry_t; +#endif typedef struct pda_s { @@ -38,11 +46,15 @@ typedef struct pda_s { struct subnodepda_s *p_subnodepda; /* Pointer to CPU subnode PDA */ /* - * Support for blinking SN LEDs + * Support for SN LEDs */ - long *led_address; +#ifdef CONFIG_IA64_SGI_SN1 + volatile long *led_address; +#else + volatile short *led_address; +#endif u8 led_state; - char hb_state; /* supports blinking heartbeat leds */ + u8 hb_state; /* supports blinking heartbeat leds */ unsigned int hb_count; unsigned int idle_flag; @@ -52,8 +64,15 @@ typedef struct pda_s { #endif volatile unsigned long *bedrock_rev_id; volatile unsigned long *pio_write_status_addr; + volatile unsigned long *pio_shub_war_cam_addr; + volatile unsigned long *mem_write_status_addr; - bteinfo_t *cpubte[BTES_PER_NODE]; + bteinfo_t *cpu_bte_if[BTES_PER_NODE]; /* cpu interface order */ + +#ifdef BUS_INT_WAR + sn_poll_entry_t pda_poll_entries[POLL_ENTRIES]; + int pda_poll_entry_count; +#endif } pda_t; @@ -71,10 +90,11 @@ typedef struct pda_s { * size of the cpu_data area dont change cache layout. Should we align to 32, 64, 128 * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later. */ -#define CPU_DATA_END CACHE_ALIGN((long)&(((struct cpuinfo_ia64*)0)->platform_specific)) -#define PDAADDR (PERCPU_ADDR+CPU_DATA_END) +DECLARE_PER_CPU(struct pda_s, pda_percpu); + +#define pda (&__get_cpu_var(pda_percpu)) -#define pda (*((pda_t *) PDAADDR)) +#define pdacpu(cpu) (&per_cpu(pda_percpu, cpu)) #endif /* _ASM_IA64_SN_PDA_H */ diff --git a/include/asm-ia64/sn/sgi.h b/include/asm-ia64/sn/sgi.h index 8e8d3d4dd875..cb716f0c6d2c 100644 --- a/include/asm-ia64/sn/sgi.h +++ b/include/asm-ia64/sn/sgi.h @@ -18,82 +18,6 @@ #include <linux/mm.h> #include <linux/devfs_fs_kernel.h> -// This devfs stuff needs a better home ..... - -struct directory_type -{ - struct devfs_entry *first; - struct devfs_entry *last; - unsigned int num_removable; -}; - -struct file_type -{ - unsigned long size; -}; - -struct device_type -{ - unsigned short major; - unsigned short minor; -}; - -struct fcb_type /* File, char, block type */ -{ - uid_t default_uid; - gid_t default_gid; - void *ops; - union - { - struct file_type file; - struct device_type device; - } - u; - unsigned char auto_owner:1; - unsigned char aopen_notify:1; - unsigned char removable:1; /* Belongs in device_type, but save space */ - unsigned char open:1; /* Not entirely correct */ -}; - -struct symlink_type -{ - unsigned int length; /* Not including the NULL-termimator */ - char *linkname; /* This is NULL-terminated */ -}; - -struct fifo_type -{ - uid_t uid; - gid_t gid; -}; - -struct devfs_entry -{ - void *info; - union - { - struct directory_type dir; - struct fcb_type fcb; - struct symlink_type symlink; - struct fifo_type fifo; - } - u; - struct devfs_entry *prev; /* Previous entry in the parent directory */ - struct devfs_entry *next; /* Next entry in the parent directory */ - struct devfs_entry *parent; /* The parent directory */ - struct devfs_entry *slave; /* Another entry to unregister */ - struct devfs_inode *first_inode; - struct devfs_inode *last_inode; - umode_t mode; - unsigned short namelen; /* I think 64k+ filenames are a way off... */ - unsigned char registered:1; - unsigned char show_unreg:1; - unsigned char hide:1; - unsigned char no_persistence /*:1*/; - char name[1]; /* This is just a dummy: the allocated array is - bigger. This is NULL-terminated */ -}; - typedef int64_t __psint_t; /* needed by klgraph.c */ typedef enum { B_FALSE, B_TRUE } boolean_t; @@ -223,6 +147,31 @@ mutex_spinlock(spinlock_t *sem) { #define cpu_enabled(cpu) (1) #endif +/* print_register() defs */ + +/* + * register values + * map between numeric values and symbolic values + */ +struct reg_values { + unsigned long long rv_value; + char *rv_name; +}; + +/* + * register descriptors are used for formatted prints of register values + * rd_mask and rd_shift must be defined, other entries may be null + */ +struct reg_desc { + unsigned long long rd_mask; /* mask to extract field */ + int rd_shift; /* shift for extracted value, - >>, + << */ + char *rd_name; /* field name */ + char *rd_format; /* format to print field */ + struct reg_values *rd_values; /* symbolic names of values */ +}; + +extern void print_register(unsigned long long, struct reg_desc *); + #include <asm/sn/hack.h> /* for now */ #endif /* _ASM_IA64_SN_SGI_H */ diff --git a/include/asm-ia64/sn/sn1/addrs.h b/include/asm-ia64/sn/sn1/addrs.h index a7055a03400b..3f12cb5da8e4 100644 --- a/include/asm-ia64/sn/sn1/addrs.h +++ b/include/asm-ia64/sn/sn1/addrs.h @@ -41,7 +41,8 @@ * use some new ANSI preprocessor stuff to paste these on where needed. */ -#define CAC_BASE 0xe000000000000000 +#define CACHEABLE_MEM_SPACE 0xe000000000000000 +#define CAC_BASE CACHEABLE_MEM_SPACE #define HSPEC_BASE 0xc0000b0000000000 #define HSPEC_SWIZ_BASE 0xc000030000000000 #define IO_BASE 0xc0000a0000000000 diff --git a/include/asm-ia64/sn/sn1/intr.h b/include/asm-ia64/sn/sn1/intr.h index 8a46d66e20ab..a05b7898c0a6 100644 --- a/include/asm-ia64/sn/sn1/intr.h +++ b/include/asm-ia64/sn/sn1/intr.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: intr.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff --git a/include/asm-ia64/sn/sn1/intr_public.h b/include/asm-ia64/sn/sn1/intr_public.h index d75df99de88c..3d2d1e2d9d4d 100644 --- a/include/asm-ia64/sn/sn1/intr_public.h +++ b/include/asm-ia64/sn/sn1/intr_public.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: intr_public.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff --git a/include/asm-ia64/sn/sn1/mmzone_sn1.h b/include/asm-ia64/sn/sn1/mmzone_sn1.h index 769aa51f1040..5202f5544187 100644 --- a/include/asm-ia64/sn/sn1/mmzone_sn1.h +++ b/include/asm-ia64/sn/sn1/mmzone_sn1.h @@ -98,7 +98,7 @@ typedef signed short cnodeid_t; * absent. Each node consists of a number of possibly discontiguous chunks. */ #define SN1_CHUNKSHIFT 26 /* 64 MB */ -#define SN1_CHUNKSIZE (1UL << SN1_CHUNKSHIFT) +#define PLAT_CHUNKSIZE (1UL << SN1_CHUNKSHIFT) #define PLAT_CHUNKNUM(addr) (((addr) & (PLAT_MAX_PHYS_MEMORY-1)) >> SN1_CHUNKSHIFT) @@ -134,8 +134,8 @@ typedef signed short cnodeid_t; * This macro takes an address of the end of previous allocation, rounds it to a page boundary & * changes the node number. */ -#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) SN1_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnodeid]), \ - (SN1_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT) +#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) __pa(SN1_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnode]), \ + (SN1_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT)) diff --git a/include/asm-ia64/sn/sn1/sn_private.h b/include/asm-ia64/sn/sn1/sn_private.h index a88646e6528a..27ebfe4c8157 100644 --- a/include/asm-ia64/sn/sn1/sn_private.h +++ b/include/asm-ia64/sn/sn1/sn_private.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: sn_private.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive diff --git a/include/asm-ia64/sn/sn1/synergy.h b/include/asm-ia64/sn/sn1/synergy.h index c4bf26cd1458..f99dee05192a 100644 --- a/include/asm-ia64/sn/sn1/synergy.h +++ b/include/asm-ia64/sn/sn1/synergy.h @@ -54,9 +54,6 @@ #define WRITE_LOCAL_SYNERGY_REG(addr, value) __synergy_out(addr, value) -#define HUB_L(_a) *(_a) -#define HUB_S(_a, _d) *(_a) = (_d) - #define HSPEC_SYNERGY0_0 0x04000000 /* Synergy0 Registers */ #define HSPEC_SYNERGY1_0 0x05000000 /* Synergy1 Registers */ #define HS_SYNERGY_STRIDE (HSPEC_SYNERGY1_0 - HSPEC_SYNERGY0_0) diff --git a/include/asm-ia64/sn/sn2/addrs.h b/include/asm-ia64/sn/sn2/addrs.h index e5f31b0776f8..ba12fbd2eed9 100644 --- a/include/asm-ia64/sn/sn2/addrs.h +++ b/include/asm-ia64/sn/sn2/addrs.h @@ -4,7 +4,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2001 Silicon Graphics, Inc. All rights reserved. + * Copyright (c) 2001-2002 Silicon Graphics, Inc. All rights reserved. */ #ifndef _ASM_IA64_SN_SN2_ADDRS_H @@ -53,19 +53,26 @@ typedef union ia64_sn2_pa { /* Regions determined by AS */ #define LOCAL_MMR_SPACE 0xc000008000000000 /* Local MMR space */ +#define LOCAL_PHYS_MMR_SPACE 0x8000008000000000 /* Local PhysicalMMR space */ #define LOCAL_MEM_SPACE 0xc000010000000000 /* Local Memory space */ #define GLOBAL_MMR_SPACE 0xc000000800000000 /* Global MMR space */ +#define GLOBAL_PHYS_MMR_SPACE 0x0000000800000000 /* Global Physical MMR space */ #define GET_SPACE 0xc000001000000000 /* GET space */ #define AMO_SPACE 0xc000002000000000 /* AMO space */ #define CACHEABLE_MEM_SPACE 0xe000003000000000 /* Cacheable memory space */ #define UNCACHED 0xc000000000000000 /* UnCacheable memory space */ +#define UNCACHED_PHYS 0x8000000000000000 /* UnCacheable physical memory space */ + +#define PHYS_MEM_SPACE 0x0000003000000000 /* physical memory space */ /* SN2 address macros */ #define NID_SHFT 38 #define LOCAL_MMR_ADDR(a) (UNCACHED | LOCAL_MMR_SPACE | (a)) +#define LOCAL_MMR_PHYS_ADDR(a) (UNCACHED_PHYS | LOCAL_PHYS_MMR_SPACE | (a)) #define LOCAL_MEM_ADDR(a) (LOCAL_MEM_SPACE | (a)) #define REMOTE_ADDR(n,a) ((((unsigned long)(n))<<NID_SHFT) | (a)) #define GLOBAL_MMR_ADDR(n,a) (UNCACHED | GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a)) +#define GLOBAL_MMR_PHYS_ADDR(n,a) (UNCACHED_PHYS | GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a)) #define GET_ADDR(n,a) (GET_SPACE | REMOTE_ADDR(n,a)) #define AMO_ADDR(n,a) (UNCACHED | AMO_SPACE | REMOTE_ADDR(n,a)) #define GLOBAL_MEM_ADDR(n,a) (CACHEABLE_MEM_SPACE | REMOTE_ADDR(n,a)) @@ -104,9 +111,19 @@ typedef union ia64_sn2_pa { #define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT) #define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ NASID_SHFT) & NASID_BITMASK) +#define PHYS_TO_DMA(x) ( ((x & NASID_MASK) >> 2) | \ + (x & (NODE_ADDRSPACE_SIZE - 1)) ) #define CHANGE_NASID(n,x) ({ia64_sn2_pa_t _v; _v.l = (long) (x); _v.f.nasid = n; _v.p;}) +/* + * Determine if a physical address should be referenced as cached or uncached. + * For now, assume all memory is cached and everything else is noncached. + * (Later, we may need to special case areas of memory to be reference uncached). + */ +#define IS_CACHED_ADDRESS(x) (((x) & PHYS_MEM_SPACE) == PHYS_MEM_SPACE) + + #ifndef __ASSEMBLY__ #define NODE_SWIN_BASE(nasid, widget) \ ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ diff --git a/include/asm-ia64/sn/sn2/arch.h b/include/asm-ia64/sn/sn2/arch.h index 3dafe8e05851..d630ed226f11 100644 --- a/include/asm-ia64/sn/sn2/arch.h +++ b/include/asm-ia64/sn/sn2/arch.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: arch.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -61,6 +61,4 @@ #define TO_SLICE(subn, local) (((subn) << SUBNODE_SHFT) | \ ((local) << LOCALCPU_SHFT)) -typedef u64 mmr_t; - #endif /* _ASM_IA64_SN_SN2_ARCH_H */ diff --git a/include/asm-ia64/sn/sn2/intr.h b/include/asm-ia64/sn/sn2/intr.h index 1fee72e396ce..09cb8319474c 100644 --- a/include/asm-ia64/sn/sn2/intr.h +++ b/include/asm-ia64/sn/sn2/intr.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: intr.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -13,8 +13,8 @@ #define SGI_SHUB_ERROR_VECTOR (0xea) // These two IRQ's are used by partitioning. +#define SGI_XPC_ACTIVATE (0x30) #define SGI_XPC_NOTIFY (0xe7) -#define SGI_XPART_ACTIVATE (0x30) #define IA64_SN2_FIRST_DEVICE_VECTOR (0x31) #define IA64_SN2_LAST_DEVICE_VECTOR (0xe6) @@ -22,4 +22,6 @@ #define SN2_IRQ_RESERVED (0x1) #define SN2_IRQ_CONNECTED (0x2) +#define SN2_IRQ_PER_HUB (2048) + #endif /* _ASM_IA64_SN_SN2_INTR_H */ diff --git a/include/asm-ia64/sn/sn2/mmzone_sn2.h b/include/asm-ia64/sn/sn2/mmzone_sn2.h index 0f5fec8bee96..9acc591629e3 100644 --- a/include/asm-ia64/sn/sn2/mmzone_sn2.h +++ b/include/asm-ia64/sn/sn2/mmzone_sn2.h @@ -103,7 +103,7 @@ typedef signed short cnodeid_t; * absent. Each node consists of a number of possibly contiguous chunks. */ #define SN2_CHUNKSHIFT 25 /* 32 MB */ -#define SN2_CHUNKSIZE (1UL << SN2_CHUNKSHIFT) +#define PLAT_CHUNKSIZE (1UL << SN2_CHUNKSHIFT) #define PLAT_CHUNKNUM(addr) ({unsigned long _p=(unsigned long)(addr); \ (((_p&SN2_NODE_MASK)>>2) | \ (_p&SN2_NODE_OFFSET_MASK)) >>SN2_CHUNKSHIFT;}) @@ -141,8 +141,8 @@ typedef signed short cnodeid_t; * This macro takes an address of the end of previous allocation, rounds it to a page boundary & * changes the node number. */ -#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) SN2_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnodeid]), \ - (SN2_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT) +#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr) __pa(SN2_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnode]), \ + (SN2_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT)) diff --git a/include/asm-ia64/sn/sn2/shubio.h b/include/asm-ia64/sn/sn2/shubio.h index 6d8edac60bb4..51c33b67c9c7 100644 --- a/include/asm-ia64/sn/sn2/shubio.h +++ b/include/asm-ia64/sn/sn2/shubio.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: shubio.h,v 1.1 2002/02/28 17:31:25 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -493,8 +493,8 @@ typedef union ii_iidsr_u { shubreg_t i_rsvd_3 : 4; shubreg_t i_enable : 1; shubreg_t i_rsvd_2 : 3; - shubreg_t i_int_sent : 1; - shubreg_t i_rsvd_1 : 3; + shubreg_t i_int_sent : 2; + shubreg_t i_rsvd_1 : 2; shubreg_t i_pi0_forward_int : 1; shubreg_t i_pi1_forward_int : 1; shubreg_t i_rsvd : 30; @@ -3089,11 +3089,11 @@ typedef union ii_ippr_u { #define IIO_FIRST_PC_ENTRY 12 */ -#define IIO_ICRB_A(_x) (IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x))) -#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET) -#define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET) -#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET) -#define IIO_ICRB_E(_x) (IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET) +#define IIO_ICRB_A(_x) ((u64)(IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))) +#define IIO_ICRB_B(_x) ((u64)((char *)IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)) +#define IIO_ICRB_C(_x) ((u64)((char *)IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)) +#define IIO_ICRB_D(_x) ((u64)((char *)IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)) +#define IIO_ICRB_E(_x) ((u64)((char *)IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)) #define TNUM_TO_WIDGET_DEV(_tnum) (_tnum & 0x7) @@ -3288,12 +3288,9 @@ typedef union ii_ippr_u { #ifndef __ASSEMBLY__ /* - * Easy access macros for CRBs, all 4 registers (A-D) + * Easy access macros for CRBs, all 5 registers (A-E) */ typedef ii_icrb0_a_u_t icrba_t; -#define a_lnetuce ii_icrb0_a_fld_s.ia_ln_uce -#define a_mark ii_icrb0_a_fld_s.ia_mark -#define a_xerr ii_icrb0_a_fld_s.ia_xt_err #define a_sidn ii_icrb0_a_fld_s.ia_sidn #define a_tnum ii_icrb0_a_fld_s.ia_tnum #define a_addr ii_icrb0_a_fld_s.ia_addr @@ -3302,35 +3299,56 @@ typedef ii_icrb0_a_u_t icrba_t; #define a_regvalue ii_icrb0_a_regval typedef ii_icrb0_b_u_t icrbb_t; -#define b_error ii_icrb0_b_fld_s.ib_error -#define b_ecode ii_icrb0_b_fld_s.ib_errcode -#define b_cohtrans ii_icrb0_b_fld_s.ib_ct -#define b_xtsize ii_icrb0_b_fld_s.ib_size -#define b_source ii_icrb0_b_fld_s.ib_source +#define b_use_old ii_icrb0_b_fld_s.ib_use_old #define b_imsgtype ii_icrb0_b_fld_s.ib_imsgtype #define b_imsg ii_icrb0_b_fld_s.ib_imsg #define b_initiator ii_icrb0_b_fld_s.ib_init +#define b_exc ii_icrb0_b_fld_s.ib_exc +#define b_ackcnt ii_icrb0_b_fld_s.ib_ack_cnt +#define b_resp ii_icrb0_b_fld_s.ib_resp +#define b_ack ii_icrb0_b_fld_s.ib_ack +#define b_hold ii_icrb0_b_fld_s.ib_hold +#define b_wb ii_icrb0_b_fld_s.ib_wb +#define b_intvn ii_icrb0_b_fld_s.ib_intvn +#define b_stall_ib ii_icrb0_b_fld_s.ib_stall_ib +#define b_stall_int ii_icrb0_b_fld_s.ib_stall__intr +#define b_stall_bte_0 ii_icrb0_b_fld_s.ib_stall__bte_0 +#define b_stall_bte_1 ii_icrb0_b_fld_s.ib_stall__bte_1 +#define b_error ii_icrb0_b_fld_s.ib_error +#define b_ecode ii_icrb0_b_fld_s.ib_errcode +#define b_lnetuce ii_icrb0_b_fld_s.ib_ln_uce +#define b_mark ii_icrb0_b_fld_s.ib_mark +#define b_xerr ii_icrb0_b_fld_s.ib_xt_err #define b_regvalue ii_icrb0_b_regval typedef ii_icrb0_c_u_t icrbc_t; -#define c_btenum ii_icrb0_c_fld_s.ic_bte_num -#define c_pricnt ii_icrb0_c_fld_s.ic_pr_cnt -#define c_pripsc ii_icrb0_c_fld_s.ic_pr_psc -#define c_bteaddr ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/ -#define c_benable ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/ #define c_suppl ii_icrb0_c_fld_s.ic_suppl #define c_barrop ii_icrb0_c_fld_s.ic_bo #define c_doresp ii_icrb0_c_fld_s.ic_resprqd #define c_gbr ii_icrb0_c_fld_s.ic_gbr +#define c_btenum ii_icrb0_c_fld_s.ic_bte_num +#define c_cohtrans ii_icrb0_c_fld_s.ic_ct +#define c_xtsize ii_icrb0_c_fld_s.ic_size +#define c_source ii_icrb0_c_fld_s.ic_source #define c_regvalue ii_icrb0_c_regval + typedef ii_icrb0_d_u_t icrbd_t; +#define d_sleep ii_icrb0_d_fld_s.id_sleep +#define d_pricnt ii_icrb0_d_fld_s.id_pr_cnt +#define d_pripsc ii_icrb0_d_fld_s.id_pr_psc #define d_bteop ii_icrb0_d_fld_s.id_bte_op -#define icrbd_ctxtvld ii_icrb0_d_fld_s.id_cvld -#define icrbd_toutvld ii_icrb0_d_fld_s.id_tvld -#define icrbd_context ii_icrb0_d_fld_s.id_context +#define d_bteaddr ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ +#define d_benable ii_icrb0_d_fld_s.id_pa_be /* ic_pa_be fld has 2 names*/ #define d_regvalue ii_icrb0_d_regval +typedef ii_icrb0_e_u_t icrbe_t; +#define icrbe_ctxtvld ii_icrb0_e_fld_s.ie_cvld +#define icrbe_toutvld ii_icrb0_e_fld_s.ie_tvld +#define icrbe_context ii_icrb0_e_fld_s.ie_context +#define icrbe_timeout ii_icrb0_e_fld_s.ie_timeout +#define e_regvalue ii_icrb0_e_regval + #endif /* __ASSEMBLY__ */ /* Number of widgets supported by shub */ @@ -3391,15 +3409,15 @@ typedef ii_icrb0_d_u_t icrbd_t; /* IO Interrupt Destination Register */ #define IIO_IIDSR_SENT_SHIFT 28 -#define IIO_IIDSR_SENT_MASK 0x10000000 +#define IIO_IIDSR_SENT_MASK 0x30000000 #define IIO_IIDSR_ENB_SHIFT 24 #define IIO_IIDSR_ENB_MASK 0x01000000 -#define IIO_IIDSR_NODE_SHIFT 8 -#define IIO_IIDSR_NODE_MASK 0x0000ff00 +#define IIO_IIDSR_NODE_SHIFT 9 +#define IIO_IIDSR_NODE_MASK 0x000ff700 #define IIO_IIDSR_PI_ID_SHIFT 8 -#define IIO_IIDSR_PI_ID_MASK 0x00000010 +#define IIO_IIDSR_PI_ID_MASK 0x00000100 #define IIO_IIDSR_LVL_SHIFT 0 -#define IIO_IIDSR_LVL_MASK 0x0000007f +#define IIO_IIDSR_LVL_MASK 0x000000ff /* Xtalk timeout threshhold register (IIO_IXTT) */ #define IXTT_RRSP_TO_SHFT 55 /* read response timeout */ @@ -3570,8 +3588,9 @@ hub_intr_free(hub_intr_t intr_hdl); extern int hub_intr_connect( hub_intr_t intr_hdl, /* xtalk intr resource hndl */ - xtalk_intr_setfunc_t setfunc, - /* func to set intr hw */ + intr_func_t intr_func, /* xtalk intr handler */ + void *intr_arg, /* arg to intr handler */ + xtalk_intr_setfunc_t setfunc, /* func to set intr hw */ void *setfunc_arg); /* arg to setfunc */ extern void diff --git a/include/asm-ia64/sn/sn2/sn_private.h b/include/asm-ia64/sn/sn2/sn_private.h index ba58d5ed28b8..51baf4015dc8 100644 --- a/include/asm-ia64/sn/sn2/sn_private.h +++ b/include/asm-ia64/sn/sn2/sn_private.h @@ -1,4 +1,4 @@ -/* $Id$ +/* $Id: sn_private.h,v 1.1 2002/02/28 17:31:26 marcelo Exp $ * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -27,7 +27,7 @@ extern int check_nasid_equiv(nasid_t, nasid_t); extern nasid_t get_console_nasid(void); extern char get_console_pcislot(void); -extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid); +extern int is_master_baseio_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid); /* memsupport.c */ extern void poison_state_alter_range(__psunsigned_t start, int len, int poison); @@ -43,8 +43,10 @@ extern void set_dir_state_POISONED(paddr_t); extern void set_dir_state_UNOWNED(paddr_t); extern int is_POISONED_dir_state(paddr_t); extern int is_UNOWNED_dir_state(paddr_t); +#ifdef LATER extern void get_dir_ent(paddr_t paddr, int *state, uint64_t *vec_ptr, hubreg_t *elo); +#endif /* intr.c */ extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name); diff --git a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h index b8832a060939..6b6106def193 100644 --- a/include/asm-ia64/sn/sn_cpuid.h +++ b/include/asm-ia64/sn/sn_cpuid.h @@ -121,13 +121,19 @@ #endif /* - * NOTE: id & eid refer to Intels definitions of the LID register - * (id = NASID, eid = slice) + * NOTE: id & eid refer to Intel's definitions of the LID register + * * NOTE: on non-MP systems, only cpuid 0 exists */ -#define id_eid_to_cpu_physical_id(id,eid) (((id)<<8) | (eid)) -#define id_eid_to_cpuid(id,eid) (cpu_logical_id(id_eid_to_cpu_physical_id((id),(eid)))) +#define id_eid_to_cpu_physical_id(id,eid) (((id)<<8) | (eid)) + +#define nasid_slice_to_cpuid(nasid,slice) (cpu_logical_id(nasid_slice_to_cpu_physical_id((nasid),(slice)))) +#ifdef CONFIG_IA64_SGI_SN1 +#define nasid_slice_to_cpu_physical_id(nasid, slice) (((nasid)<<8) | (slice)) +#else +#define nasid_slice_to_cpu_physical_id(nasid, slice) (((slice)<<12) | (nasid)) +#endif /* * The following table/struct is used for managing PTC coherency domains. @@ -190,13 +196,14 @@ extern sn_sapicid_info_t sn_sapicid_info[]; /* indexed by cpuid */ /* * nasid_to_cnodeid - convert a NASID to a cnodeid */ -#define nasid_to_cnodeid(nasid) (local_node_data->physical_node_map[nasid]) +#define nasid_to_cnodeid(nasid) (nasid) /* (local_node_data->physical_node_map[nasid]) */ /* * cnode_slice_to_cpuid - convert a codeid & slice to a cpuid */ -#define cnode_slice_to_cpuid(cnodeid,slice) (id_eid_to_cpuid(cnodeid_to_nasid(cnodeid),(slice))) + +#define cnode_slice_to_cpuid(cnodeid,slice) (nasid_slice_to_cpuid(cnodeid_to_nasid(cnodeid),(slice))) /* diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h index a92e7b1c2355..e1f1b3e4d0a3 100644 --- a/include/asm-ia64/sn/sn_sal.h +++ b/include/asm-ia64/sn/sn_sal.h @@ -12,20 +12,107 @@ */ +#include <linux/config.h> #include <asm/sal.h> #include <asm/sn/sn_cpuid.h> +#include <asm/sn/arch.h> // SGI Specific Calls #define SN_SAL_POD_MODE 0x02000001 #define SN_SAL_SYSTEM_RESET 0x02000002 #define SN_SAL_PROBE 0x02000003 -#define SN_SAL_GET_CONSOLE_NASID 0x02000004 +#define SN_SAL_GET_MASTER_NASID 0x02000004 #define SN_SAL_GET_KLCONFIG_ADDR 0x02000005 #define SN_SAL_LOG_CE 0x02000006 #define SN_SAL_REGISTER_CE 0x02000007 +#define SN_SAL_GET_PARTITION_ADDR 0x02000009 +#define SN_SAL_PRINT_ERROR 0x02000012 +#define SN_SAL_CONSOLE_PUTC 0x02000021 +#define SN_SAL_CONSOLE_GETC 0x02000022 +#define SN_SAL_CONSOLE_PUTS 0x02000023 +#define SN_SAL_CONSOLE_GETS 0x02000024 +#define SN_SAL_CONSOLE_GETS_TIMEOUT 0x02000025 +#define SN_SAL_CONSOLE_POLL 0x02000026 +#define SN_SAL_CONSOLE_INTR 0x02000027 +#define SN_SAL_CONSOLE_PUTB 0x02000028 +#define SN_SAL_SYSCTL_MODID_GET 0x02000031 +#define SN_SAL_SYSCTL_GET 0x02000032 +#define SN_SAL_SYSCTL_IOBRICK_MODULE_GET 0x02000033 +#define SN_SAL_SYSCTL_IO_PORTSPEED_GET 0x02000035 +#define SN_SAL_SYSCTL_SLAB_GET 0x02000036 +#define SN_SAL_BUS_CONFIG 0x02000037 +#define SN_SAL_SYS_SERIAL_GET 0x02000038 +#define SN_SAL_PARTITION_SERIAL_GET 0x02000039 +#define SN_SAL_SYSCTL_PARTITION_GET 0x0200003a +#define SN_SAL_SYSTEM_POWER_DOWN 0x0200003b +#define SN_SAL_GET_MASTER_BASEIO_NASID 0x0200003c +/* + * Service-specific constants + */ +#define SAL_CONSOLE_INTR_IN 0 /* manipulate input interrupts */ +#define SAL_CONSOLE_INTR_OUT 1 /* manipulate output low-water + * interrupts + */ +#define SAL_CONSOLE_INTR_OFF 0 /* turn the interrupt off */ +#define SAL_CONSOLE_INTR_ON 1 /* turn the interrupt on */ + + +/* + * SN_SAL_GET_PARTITION_ADDR return constants + */ +#define SALRET_MORE_PASSES 1 +#define SALRET_OK 0 +#define SALRET_INVALID_ARG -2 +#define SALRET_ERROR -3 + + +/** + * sn_sal_rev_major - get the major SGI SAL revision number + * + * The SGI PROM stores its version in sal_[ab]_rev_(major|minor). + * This routine simply extracts the major value from the + * @ia64_sal_systab structure constructed by ia64_sal_init(). + */ +static inline int +sn_sal_rev_major(void) +{ + struct ia64_sal_systab *systab = efi.sal_systab; + + return (int)systab->sal_b_rev_major; +} + +/** + * sn_sal_rev_minor - get the minor SGI SAL revision number + * + * The SGI PROM stores its version in sal_[ab]_rev_(major|minor). + * This routine simply extracts the minor value from the + * @ia64_sal_systab structure constructed by ia64_sal_init(). + */ +static inline int +sn_sal_rev_minor(void) +{ + struct ia64_sal_systab *systab = efi.sal_systab; + + return (int)systab->sal_b_rev_minor; +} + +/* + * Specify the minimum PROM revsion required for this kernel. + * Note that they're stored in hex format... + */ +#ifdef CONFIG_IA64_SGI_SN1 +#define SN_SAL_MIN_MAJOR 0x0 +#define SN_SAL_MIN_MINOR 0x03 /* SN1 PROMs are stuck at rev 0.03 */ +#elif defined(CONFIG_IA64_SGI_SN2) +#define SN_SAL_MIN_MAJOR 0x0 +#define SN_SAL_MIN_MINOR 0x11 +#else +#error "must specify which PROM revisions this kernel needs" +#endif /* CONFIG_IA64_SGI_SN1 */ + u64 ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr); /* @@ -41,7 +128,7 @@ ia64_sn_get_console_nasid(void) ret_stuff.v0 = (uint64_t)0; ret_stuff.v1 = (uint64_t)0; ret_stuff.v2 = (uint64_t)0; - SAL_CALL(ret_stuff, SN_SAL_GET_CONSOLE_NASID, 0, 0, 0, 0, 0, 0, 0); + SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_NASID, 0, 0, 0, 0, 0, 0, 0); if (ret_stuff.status < 0) return ret_stuff.status; @@ -50,6 +137,28 @@ ia64_sn_get_console_nasid(void) return ret_stuff.v0; } +/* + * Returns the master baseio nasid, if the call fails, return an illegal + * value. + */ +static inline u64 +ia64_sn_get_master_baseio_nasid(void) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + SAL_CALL(ret_stuff, SN_SAL_GET_MASTER_BASEIO_NASID, 0, 0, 0, 0, 0, 0, 0); + + if (ret_stuff.status < 0) + return ret_stuff.status; + + /* Master baseio nasid is in 'v0' */ + return ret_stuff.v0; +} + static inline u64 ia64_sn_get_klconfig_addr(nasid_t nasid) { @@ -57,7 +166,7 @@ ia64_sn_get_klconfig_addr(nasid_t nasid) extern u64 klgraph_addr[]; int cnodeid; - cnodeid = nasid_to_cnodeid(nasid); + cnodeid = 0 /* nasid_to_cnodeid(nasid) */; if (klgraph_addr[cnodeid] == 0) { ret_stuff.status = (uint64_t)0; ret_stuff.v0 = (uint64_t)0; @@ -76,6 +185,245 @@ ia64_sn_get_klconfig_addr(nasid_t nasid) klgraph_addr[cnodeid] = ret_stuff.v0; } return(klgraph_addr[cnodeid]); +} + +/* + * Returns the next console character. + */ +static inline u64 +ia64_sn_console_getc(int *ch) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_GETC, 0, 0, 0, 0, 0, 0, 0); + + /* character is in 'v0' */ + *ch = (int)ret_stuff.v0; + + return ret_stuff.status; +} + +/* + * Sends the given character to the console. + */ +static inline u64 +ia64_sn_console_putc(char ch) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_PUTC, (uint64_t)ch, 0, 0, 0, 0, 0, 0); + + return ret_stuff.status; +} + +/* + * Sends the given buffer to the console. + */ +static inline u64 +ia64_sn_console_putb(char *buf, int len) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_PUTB, (uint64_t)buf, (uint64_t)len, 0, 0, 0, 0, 0); + + return ret_stuff.status; +} + +/* + * Print a platform error record + */ +static inline u64 +ia64_sn_plat_specific_err_print(int (*hook)(const char*, ...), char *rec) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_PRINT_ERROR, (uint64_t)hook, (uint64_t)rec, 0, 0, 0, 0, 0); + return ret_stuff.status; } + +/* + * Check for Platform errors + */ +static inline u64 +ia64_sn_plat_cpei_handler(void) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_LOG_CE, 0, 0, 0, 0, 0, 0, 0); + + return ret_stuff.status; +} + +/* + * Checks for console input. + */ +static inline u64 +ia64_sn_console_check(int *result) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + __SAL_CALL(ret_stuff, SN_SAL_CONSOLE_POLL, 0, 0, 0, 0, 0, 0, 0); + + /* result is in 'v0' */ + *result = (int)ret_stuff.v0; + + return ret_stuff.status; +} + +/* + * Returns the iobrick module Id + */ +static inline u64 +ia64_sn_sysctl_iobrick_module_get(nasid_t nasid, int *result) +{ + struct ia64_sal_retval ret_stuff; + + ret_stuff.status = (uint64_t)0; + ret_stuff.v0 = (uint64_t)0; + ret_stuff.v1 = (uint64_t)0; + ret_stuff.v2 = (uint64_t)0; + SAL_CALL(ret_stuff, SN_SAL_SYSCTL_IOBRICK_MODULE_GET, nasid, 0, 0, 0, 0, 0, 0); + + /* result is in 'v0' */ + *result = (int)ret_stuff.v0; + + return ret_stuff.status; +} + +/** + * ia64_sn_pod_mode - call the SN_SAL_POD_MODE function + * + * SN_SAL_POD_MODE actually takes an argument, but it's always + * 0 when we call it from the kernel, so we don't have to expose + * it to the caller. + */ +static inline u64 +ia64_sn_pod_mode(void) +{ + struct ia64_sal_retval isrv; + SAL_CALL(isrv, SN_SAL_POD_MODE, 0, 0, 0, 0, 0, 0, 0); + if (isrv.status) + return 0; + return isrv.v0; +} + +/* + * Retrieve the system serial number as an ASCII string. + */ +static inline u64 +ia64_sn_sys_serial_get(char *buf) +{ + struct ia64_sal_retval ret_stuff; + SAL_CALL(ret_stuff, SN_SAL_SYS_SERIAL_GET, buf, 0, 0, 0, 0, 0, 0); + return ret_stuff.status; +} + +extern char sn_system_serial_number_string[]; +extern u64 sn_partition_serial_number; + +static inline char * +sn_system_serial_number(void) { + if (sn_system_serial_number_string[0]) { + return(sn_system_serial_number_string); + } else { + ia64_sn_sys_serial_get(sn_system_serial_number_string); + return(sn_system_serial_number_string); + } +} + + +/* + * Returns a unique id number for this system and partition (suitable for + * use with license managers), based in part on the system serial number. + */ +static inline u64 +ia64_sn_partition_serial_get(void) +{ + struct ia64_sal_retval ret_stuff; + SAL_CALL(ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0, 0, 0, 0, 0, 0, 0); + if (ret_stuff.status != 0) + return 0; + return ret_stuff.v0; +} + +static inline u64 +sn_partition_serial_number_val(void) { + if (sn_partition_serial_number) { + return(sn_partition_serial_number); + } else { + return(sn_partition_serial_number = ia64_sn_partition_serial_get()); + } +} + +/* + * Returns the partition id of the nasid passed in as an argument, + * or INVALID_PARTID if the partition id cannot be retrieved. + */ +static inline partid_t +ia64_sn_sysctl_partition_get(nasid_t nasid) +{ + struct ia64_sal_retval ret_stuff; + SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid, + 0, 0, 0, 0, 0, 0); + if (ret_stuff.status != 0) + return INVALID_PARTID; + return ((partid_t)ret_stuff.v0); +} + +#ifdef CONFIG_IA64_SGI_SN2 +/* + * Returns the partition id of the current processor. + */ + +extern partid_t sn_partid; + +static inline partid_t +sn_local_partid(void) { + if (sn_partid < 0) { + return (sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id()))); + } else { + return sn_partid; + } +} + +#endif /* CONFIG_IA64_SGI_SN2 */ + +/* + * Turns off system power. + */ +static inline void +ia64_sn_power_down(void) +{ + struct ia64_sal_retval ret_stuff; + SAL_CALL(ret_stuff, SN_SAL_SYSTEM_POWER_DOWN, 0, 0, 0, 0, 0, 0, 0); + while(1); + /* never returns */ +} + + #endif /* _ASM_IA64_SN_SN_SAL_H */ diff --git a/include/asm-ia64/sn/sndrv.h b/include/asm-ia64/sn/sndrv.h index 10664979659e..ea5f4c5abfbd 100644 --- a/include/asm-ia64/sn/sndrv.h +++ b/include/asm-ia64/sn/sndrv.h @@ -27,6 +27,13 @@ #define SNDRV_SYNERGY_ENABLE 34 #define SNDRV_SYNERGY_FREQ 35 +/* see shubstats_ioctl() */ +#define SNDRV_SHUB_INFOSIZE 40 +#define SNDRV_SHUB_CONFIGURE 41 +#define SNDRV_SHUB_RESETSTATS 42 +#define SNDRV_SHUB_GETSTATS 43 +#define SNDRV_SHUB_GETNASID 44 + /* Devices */ #define SNDRV_UKNOWN_DEVICE -1 #define SNDRV_ROUTER_DEVICE 1 diff --git a/include/asm-ia64/sn/types.h b/include/asm-ia64/sn/types.h index f28b5255c471..acc56951766c 100644 --- a/include/asm-ia64/sn/types.h +++ b/include/asm-ia64/sn/types.h @@ -9,14 +9,21 @@ #ifndef _ASM_IA64_SN_TYPES_H #define _ASM_IA64_SN_TYPES_H +#include <linux/config.h> #include <linux/types.h> typedef unsigned long cpuid_t; typedef unsigned long cpumask_t; typedef signed short nasid_t; /* node id in numa-as-id space */ typedef signed char partid_t; /* partition ID type */ +#ifdef CONFIG_IA64_SGI_SN2 +typedef unsigned int moduleid_t; /* user-visible module number type */ +typedef unsigned int cmoduleid_t; /* kernel compact module id type */ +#else typedef signed short moduleid_t; /* user-visible module number type */ typedef signed short cmoduleid_t; /* kernel compact module id type */ +#endif +typedef signed char slabid_t; typedef unsigned char clusterid_t; /* Clusterid of the cell */ typedef uint64_t __psunsigned_t; diff --git a/include/asm-ia64/sn/vector.h b/include/asm-ia64/sn/vector.h index bba730c55b07..f6db63e3dad0 100644 --- a/include/asm-ia64/sn/vector.h +++ b/include/asm-ia64/sn/vector.h @@ -10,6 +10,7 @@ #define _ASM_IA64_SN_VECTOR_H #include <linux/config.h> +#include <asm/sn/arch.h> #define NET_VEC_NULL ((net_vec_t) 0) #define NET_VEC_BAD ((net_vec_t) -1) diff --git a/include/asm-ia64/sn/xtalk/xbow.h b/include/asm-ia64/sn/xtalk/xbow.h index 49aee311a4ed..a23ba30c2ca3 100644 --- a/include/asm-ia64/sn/xtalk/xbow.h +++ b/include/asm-ia64/sn/xtalk/xbow.h @@ -14,6 +14,7 @@ * xbow.h - header file for crossbow chip and xbow section of xbridge */ +#include <linux/config.h> #include <asm/sn/xtalk/xtalk.h> #include <asm/sn/xtalk/xwidget.h> #include <asm/sn/xtalk/xswitch.h> @@ -42,6 +43,13 @@ #define MAX_PORT_NUM 0x10 /* maximum port number + 1 */ #define XBOW_WIDGET_ID 0 /* xbow is itself widget 0 */ +#define XBOW_HUBLINK_LOW 0xa +#define XBOW_HUBLINK_HIGH 0xb + +#define XBOW_PEER_LINK(link) (link == XBOW_HUBLINK_LOW) ? \ + XBOW_HUBLINK_HIGH : XBOW_HUBLINK_LOW + + #define XBOW_CREDIT 4 #define MAX_XBOW_NAME 16 @@ -384,6 +392,7 @@ typedef struct xbow_cfg_s { #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbridge */ #define XBOW_WIDGET_MFGR_NUM 0x0 #define XXBOW_WIDGET_MFGR_NUM 0x0 +#define PXBOW_WIDGET_PART_NUM 0xd100 /* PIC */ #define XBOW_REV_1_0 0x1 /* xbow rev 1.0 is "1" */ #define XBOW_REV_1_1 0x2 /* xbow rev 1.1 is "2" */ @@ -398,8 +407,22 @@ typedef struct xbow_cfg_s { #define XBOW_WID_ARB_RELOAD_INT 0x3f /* GBR reload interval */ -#define nasid_has_xbridge(nasid) \ - (XWIDGET_PART_NUM(XWIDGET_ID_READ(nasid, 0)) == XXBOW_WIDGET_PART_NUM) +#ifdef CONFIG_IA64_SGI_SN1 +#define nasid_has_xbridge(nasid) \ + (XWIDGET_PART_NUM(XWIDGET_ID_READ(nasid, 0)) == XXBOW_WIDGET_PART_NUM) +#endif + +#define IS_XBRIDGE_XBOW(wid) \ + (XWIDGET_PART_NUM(wid) == XXBOW_WIDGET_PART_NUM && \ + XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) + +#define IS_PIC_XBOW(wid) \ + (XWIDGET_PART_NUM(wid) == PXBOW_WIDGET_PART_NUM && \ + XWIDGET_MFG_NUM(wid) == XXBOW_WIDGET_MFGR_NUM) + +#define XBOW_WAR_ENABLED(pv, widid) ((1 << XWIDGET_REV_NUM(widid)) & pv) +#define PV854827 (~0) /* PIC: fake widget 0xf presence bit. permanent */ +#define PV863579 (1 << 1) /* PIC: PIO to PIC register */ #ifndef __ASSEMBLY__ diff --git a/include/asm-ia64/sn/xtalk/xtalk.h b/include/asm-ia64/sn/xtalk/xtalk.h index 95ab7af95f9c..14b1680f13d0 100644 --- a/include/asm-ia64/sn/xtalk/xtalk.h +++ b/include/asm-ia64/sn/xtalk/xtalk.h @@ -8,6 +8,7 @@ */ #ifndef _ASM_SN_XTALK_XTALK_H #define _ASM_SN_XTALK_XTALK_H +#include <linux/config.h> /* * xtalk.h -- platform-independent crosstalk interface @@ -202,10 +203,19 @@ xtalk_intr_alloc_f (devfs_handle_t dev, /* which crosstalk device */ typedef void xtalk_intr_free_f (xtalk_intr_t intr_hdl); +#ifdef CONFIG_IA64_SGI_SN1 typedef int xtalk_intr_connect_f (xtalk_intr_t intr_hdl, /* xtalk intr resource handle */ xtalk_intr_setfunc_f *setfunc, /* func to set intr hw */ void *setfunc_arg); /* arg to setfunc */ +#else +typedef int +xtalk_intr_connect_f (xtalk_intr_t intr_hdl, /* xtalk intr resource handle */ + intr_func_t intr_func, /* xtalk intr handler */ + void *intr_arg, /* arg to intr handler */ + xtalk_intr_setfunc_f *setfunc, /* func to set intr hw */ + void *setfunc_arg); /* arg to setfunc */ +#endif typedef void xtalk_intr_disconnect_f (xtalk_intr_t intr_hdl); @@ -391,8 +401,5 @@ typedef void xtalk_iter_f(devfs_handle_t vhdl); extern void xtalk_iterate(char *prefix, xtalk_iter_f *func); -extern int xtalk_device_powerup(devfs_handle_t, xwidgetnum_t); -extern int xtalk_device_shutdown(devfs_handle_t, xwidgetnum_t); - #endif /* __KERNEL__ */ #endif /* _ASM_SN_XTALK_XTALK_H */ diff --git a/include/asm-ia64/sn/xtalk/xtalk_private.h b/include/asm-ia64/sn/xtalk/xtalk_private.h index 14c024929d27..4f5fcd430119 100644 --- a/include/asm-ia64/sn/xtalk/xtalk_private.h +++ b/include/asm-ia64/sn/xtalk/xtalk_private.h @@ -60,12 +60,12 @@ struct xtalk_intr_s { ((_hwid)->mfg_num == XBOW_WIDGET_MFGR_NUM )) #define xwidget_hwid_is_sn1_xswitch(_hwid) \ - (((_hwid)->part_num == XXBOW_WIDGET_PART_NUM ) && \ + (((_hwid)->part_num == XXBOW_WIDGET_PART_NUM || \ + (_hwid)->part_num == PXBOW_WIDGET_PART_NUM) && \ ((_hwid)->mfg_num == XXBOW_WIDGET_MFGR_NUM )) #define xwidget_hwid_is_xswitch(_hwid) \ - (xwidget_hwid_is_sn0_xswitch(_hwid) || \ - xwidget_hwid_is_sn1_xswitch(_hwid)) + xwidget_hwid_is_sn1_xswitch(_hwid) /* common iograph info for all widgets, * stashed in FASTINFO of widget connection points. diff --git a/include/asm-ia64/sn/xtalk/xwidget.h b/include/asm-ia64/sn/xtalk/xwidget.h index 2331d636eb6a..bea83bb83ba0 100644 --- a/include/asm-ia64/sn/xtalk/xwidget.h +++ b/include/asm-ia64/sn/xtalk/xwidget.h @@ -58,6 +58,7 @@ #define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT) #define XWIDGET_PART_REV_NUM(widgetid) ((XWIDGET_PART_NUM(widgetid) << 4) | \ XWIDGET_REV_NUM(widgetid)) +#define XWIDGET_PART_REV_NUM_REV(partrev) (partrev & 0xf) /* WIDGET_STATUS */ #define WIDGET_LLP_REC_CNT 0xff000000 diff --git a/include/asm-ia64/system.h b/include/asm-ia64/system.h index 34484d0ebd25..d09f11cb14ec 100644 --- a/include/asm-ia64/system.h +++ b/include/asm-ia64/system.h @@ -185,169 +185,6 @@ do { \ (flags & IA64_PSR_I) == 0; \ }) -/* - * Force an unresolved reference if someone tries to use - * ia64_fetch_and_add() with a bad value. - */ -extern unsigned long __bad_size_for_ia64_fetch_and_add (void); -extern unsigned long __bad_increment_for_ia64_fetch_and_add (void); - -#define IA64_FETCHADD(tmp,v,n,sz) \ -({ \ - switch (sz) { \ - case 4: \ - __asm__ __volatile__ ("fetchadd4.rel %0=[%1],%2" \ - : "=r"(tmp) : "r"(v), "i"(n) : "memory"); \ - break; \ - \ - case 8: \ - __asm__ __volatile__ ("fetchadd8.rel %0=[%1],%2" \ - : "=r"(tmp) : "r"(v), "i"(n) : "memory"); \ - break; \ - \ - default: \ - __bad_size_for_ia64_fetch_and_add(); \ - } \ -}) - -#define ia64_fetch_and_add(i,v) \ -({ \ - __u64 _tmp; \ - volatile __typeof__(*(v)) *_v = (v); \ - switch (i) { \ - case -16: IA64_FETCHADD(_tmp, _v, -16, sizeof(*(v))); break; \ - case -8: IA64_FETCHADD(_tmp, _v, -8, sizeof(*(v))); break; \ - case -4: IA64_FETCHADD(_tmp, _v, -4, sizeof(*(v))); break; \ - case -1: IA64_FETCHADD(_tmp, _v, -1, sizeof(*(v))); break; \ - case 1: IA64_FETCHADD(_tmp, _v, 1, sizeof(*(v))); break; \ - case 4: IA64_FETCHADD(_tmp, _v, 4, sizeof(*(v))); break; \ - case 8: IA64_FETCHADD(_tmp, _v, 8, sizeof(*(v))); break; \ - case 16: IA64_FETCHADD(_tmp, _v, 16, sizeof(*(v))); break; \ - default: \ - _tmp = __bad_increment_for_ia64_fetch_and_add(); \ - break; \ - } \ - (__typeof__(*(v))) (_tmp + (i)); /* return new value */ \ -}) - -/* - * This function doesn't exist, so you'll get a linker error if - * something tries to do an invalid xchg(). - */ -extern void __xchg_called_with_bad_pointer (void); - -static __inline__ unsigned long -__xchg (unsigned long x, volatile void *ptr, int size) -{ - unsigned long result; - - switch (size) { - case 1: - __asm__ __volatile ("xchg1 %0=[%1],%2" : "=r" (result) - : "r" (ptr), "r" (x) : "memory"); - return result; - - case 2: - __asm__ __volatile ("xchg2 %0=[%1],%2" : "=r" (result) - : "r" (ptr), "r" (x) : "memory"); - return result; - - case 4: - __asm__ __volatile ("xchg4 %0=[%1],%2" : "=r" (result) - : "r" (ptr), "r" (x) : "memory"); - return result; - - case 8: - __asm__ __volatile ("xchg8 %0=[%1],%2" : "=r" (result) - : "r" (ptr), "r" (x) : "memory"); - return result; - } - __xchg_called_with_bad_pointer(); - return x; -} - -#define xchg(ptr,x) \ - ((__typeof__(*(ptr))) __xchg ((unsigned long) (x), (ptr), sizeof(*(ptr)))) - -/* - * Atomic compare and exchange. Compare OLD with MEM, if identical, - * store NEW in MEM. Return the initial value in MEM. Success is - * indicated by comparing RETURN with OLD. - */ - -#define __HAVE_ARCH_CMPXCHG 1 - -/* - * This function doesn't exist, so you'll get a linker error - * if something tries to do an invalid cmpxchg(). - */ -extern long __cmpxchg_called_with_bad_pointer(void); - -#define ia64_cmpxchg(sem,ptr,old,new,size) \ -({ \ - __typeof__(ptr) _p_ = (ptr); \ - __typeof__(new) _n_ = (new); \ - __u64 _o_, _r_; \ - \ - switch (size) { \ - case 1: _o_ = (__u8 ) (long) (old); break; \ - case 2: _o_ = (__u16) (long) (old); break; \ - case 4: _o_ = (__u32) (long) (old); break; \ - case 8: _o_ = (__u64) (long) (old); break; \ - default: break; \ - } \ - __asm__ __volatile__ ("mov ar.ccv=%0;;" :: "rO"(_o_)); \ - switch (size) { \ - case 1: \ - __asm__ __volatile__ ("cmpxchg1."sem" %0=[%1],%2,ar.ccv" \ - : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ - break; \ - \ - case 2: \ - __asm__ __volatile__ ("cmpxchg2."sem" %0=[%1],%2,ar.ccv" \ - : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ - break; \ - \ - case 4: \ - __asm__ __volatile__ ("cmpxchg4."sem" %0=[%1],%2,ar.ccv" \ - : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ - break; \ - \ - case 8: \ - __asm__ __volatile__ ("cmpxchg8."sem" %0=[%1],%2,ar.ccv" \ - : "=r"(_r_) : "r"(_p_), "r"(_n_) : "memory"); \ - break; \ - \ - default: \ - _r_ = __cmpxchg_called_with_bad_pointer(); \ - break; \ - } \ - (__typeof__(old)) _r_; \ -}) - -#define cmpxchg_acq(ptr,o,n) ia64_cmpxchg("acq", (ptr), (o), (n), sizeof(*(ptr))) -#define cmpxchg_rel(ptr,o,n) ia64_cmpxchg("rel", (ptr), (o), (n), sizeof(*(ptr))) - -/* for compatibility with other platforms: */ -#define cmpxchg(ptr,o,n) cmpxchg_acq(ptr,o,n) - -#ifdef CONFIG_IA64_DEBUG_CMPXCHG -# define CMPXCHG_BUGCHECK_DECL int _cmpxchg_bugcheck_count = 128; -# define CMPXCHG_BUGCHECK(v) \ - do { \ - if (_cmpxchg_bugcheck_count-- <= 0) { \ - void *ip; \ - extern int printk(const char *fmt, ...); \ - asm ("mov %0=ip" : "=r"(ip)); \ - printk("CMPXCHG_BUGCHECK: stuck at %p on word %p\n", ip, (v)); \ - break; \ - } \ - } while (0) -#else /* !CONFIG_IA64_DEBUG_CMPXCHG */ -# define CMPXCHG_BUGCHECK_DECL -# define CMPXCHG_BUGCHECK(v) -#endif /* !CONFIG_IA64_DEBUG_CMPXCHG */ - #ifdef __KERNEL__ #define prepare_to_switch() do { } while(0) @@ -432,6 +269,38 @@ extern void ia64_load_extra (struct task_struct *task); } while (0) #endif +/* + * On IA-64, we don't want to hold the runqueue's lock during the low-level context-switch, + * because that could cause a deadlock. Here is an example by Erich Focht: + * + * Example: + * CPU#0: + * schedule() + * -> spin_lock_irq(&rq->lock) + * -> context_switch() + * -> wrap_mmu_context() + * -> read_lock(&tasklist_lock) + * + * CPU#1: + * sys_wait4() or release_task() or forget_original_parent() + * -> write_lock(&tasklist_lock) + * -> do_notify_parent() + * -> wake_up_parent() + * -> try_to_wake_up() + * -> spin_lock_irq(&parent_rq->lock) + * + * If the parent's rq happens to be on CPU#0, we'll wait for the rq->lock + * of that CPU which will not be released, because there we wait for the + * tasklist_lock to become available. + */ +#define prepare_arch_switch(rq, next) \ +do { \ + spin_lock(&(next)->switch_lock); \ + spin_unlock(&(rq)->lock); \ +} while (0) +#define finish_arch_switch(rq, prev) spin_unlock_irq(&(prev)->switch_lock) +#define task_running(rq, p) ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock)) + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/asm-ia64/thread_info.h b/include/asm-ia64/thread_info.h index 3cc16a00e5d8..23399d0d5310 100644 --- a/include/asm-ia64/thread_info.h +++ b/include/asm-ia64/thread_info.h @@ -30,6 +30,7 @@ struct thread_info { __u32 cpu; /* current CPU */ mm_segment_t addr_limit; /* user-level address space limit */ __s32 preempt_count; /* 0=premptable, <0=BUG; will also serve as bh-counter */ + struct restart_block restart_block; }; #define INIT_THREAD_SIZE /* tell sched.h not to declare the thread_union */ @@ -42,6 +43,9 @@ struct thread_info { .cpu = 0, \ .addr_limit = KERNEL_DS, \ .preempt_count = 0, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ } /* how to get the thread information struct from C */ diff --git a/include/asm-ia64/tlbflush.h b/include/asm-ia64/tlbflush.h index a6ab64b738a8..21ca04115809 100644 --- a/include/asm-ia64/tlbflush.h +++ b/include/asm-ia64/tlbflush.h @@ -22,29 +22,44 @@ * Flush everything (kernel mapping may also have changed due to * vmalloc/vfree). */ -extern void __flush_tlb_all (void); +extern void local_flush_tlb_all (void); #ifdef CONFIG_SMP extern void smp_flush_tlb_all (void); + extern void smp_flush_tlb_mm (struct mm_struct *mm); # define flush_tlb_all() smp_flush_tlb_all() #else -# define flush_tlb_all() __flush_tlb_all() +# define flush_tlb_all() local_flush_tlb_all() #endif +static inline void +local_finish_flush_tlb_mm (struct mm_struct *mm) +{ + if (mm == current->active_mm) + activate_context(mm); +} + /* - * Flush a specified user mapping + * Flush a specified user mapping. This is called, e.g., as a result of fork() and + * exit(). fork() ends up here because the copy-on-write mechanism needs to write-protect + * the PTEs of the parent task. */ static inline void flush_tlb_mm (struct mm_struct *mm) { - if (mm) { - mm->context = 0; - if (mm == current->active_mm) { - /* This is called, e.g., as a result of exec(). */ - get_new_mmu_context(mm); - reload_context(mm); - } - } + if (!mm) + return; + + mm->context = 0; + + if (atomic_read(&mm->mm_users) == 0) + return; /* happens as a result of exit_mmap() */ + +#ifdef CONFIG_SMP + smp_flush_tlb_mm(mm); +#else + local_finish_flush_tlb_mm(mm); +#endif } extern void flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end); diff --git a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h index afad108b0d0a..ea993f51f702 100644 --- a/include/asm-ia64/unistd.h +++ b/include/asm-ia64/unistd.h @@ -114,18 +114,18 @@ /* 1122 was __NR_old_fstat */ #define __NR_vhangup 1123 #define __NR_lchown 1124 -#define __NR_vm86 1125 +#define __NR_remap_file_pages 1125 #define __NR_wait4 1126 #define __NR_sysinfo 1127 #define __NR_clone 1128 #define __NR_setdomainname 1129 #define __NR_uname 1130 #define __NR_adjtimex 1131 -#define __NR_create_module 1132 +/* 1132 was __NR_create_module */ #define __NR_init_module 1133 #define __NR_delete_module 1134 -#define __NR_get_kernel_syms 1135 -#define __NR_query_module 1136 +/* 1135 was __NR_get_kernel_syms */ +/* 1136 was __NR_query_module */ #define __NR_quotactl 1137 #define __NR_bdflush 1138 #define __NR_sysfs 1139 @@ -222,7 +222,7 @@ #define __NR_futex 1230 #define __NR_sched_setaffinity 1231 #define __NR_sched_getaffinity 1232 -/* 1233 currently unused */ +#define __NR_set_tid_address 1233 #define __NR_alloc_hugepages 1234 #define __NR_free_hugepages 1235 #define __NR_exit_group 1236 @@ -235,7 +235,8 @@ #define __NR_epoll_create 1243 #define __NR_epoll_ctl 1244 #define __NR_epoll_wait 1245 -#define __NR_semtimedop 1246 +#define __NR_restart_syscall 1246 +#define __NR_semtimedop 1247 #if !defined(__ASSEMBLY__) && !defined(ASSEMBLER) diff --git a/include/asm-m68k/dma-mapping.h b/include/asm-m68k/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-m68k/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-m68knommu/dma-mapping.h b/include/asm-m68knommu/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-m68knommu/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-mips/dma-mapping.h b/include/asm-mips/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-mips/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-mips64/dma-mapping.h b/include/asm-mips64/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-mips64/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-ppc/dma-mapping.h b/include/asm-ppc/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-ppc/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-ppc64/dma-mapping.h b/include/asm-ppc64/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-ppc64/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-s390/dma-mapping.h b/include/asm-s390/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-s390/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-s390x/dma-mapping.h b/include/asm-s390x/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-s390x/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-sh/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-sparc/dma-mapping.h b/include/asm-sparc/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-sparc/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-sparc/fbio.h b/include/asm-sparc/fbio.h index a4b6afecc129..68834d38c444 100644 --- a/include/asm-sparc/fbio.h +++ b/include/asm-sparc/fbio.h @@ -90,23 +90,6 @@ struct fbgattr { #define FBIOSVIDEO _IOW('F', 7, int) #define FBIOGVIDEO _IOR('F', 8, int) -/* Cursor position */ -struct fbcurpos { -#ifdef __KERNEL__ - short fbx, fby; -#else - short x, y; -#endif -}; - -/* Cursor operations */ -#define FB_CUR_SETCUR 0x01 /* Enable/disable cursor display */ -#define FB_CUR_SETPOS 0x02 /* set cursor position */ -#define FB_CUR_SETHOT 0x04 /* set cursor hotspot */ -#define FB_CUR_SETCMAP 0x08 /* set color map for the cursor */ -#define FB_CUR_SETSHAPE 0x10 /* set shape */ -#define FB_CUR_SETALL 0x1F /* all of the above */ - struct fbcursor { short set; /* what to set, choose from the list above */ short enable; /* cursor on/off */ diff --git a/include/asm-sparc64/compat.h b/include/asm-sparc64/compat.h index 4c50ab0098f6..36fcfd6ced5f 100644 --- a/include/asm-sparc64/compat.h +++ b/include/asm-sparc64/compat.h @@ -5,9 +5,32 @@ */ #include <linux/types.h> +#define COMPAT_USER_HZ 100 + typedef u32 compat_size_t; typedef s32 compat_ssize_t; typedef s32 compat_time_t; +typedef s32 compat_clock_t; + +struct compat_stat { + __kernel_dev_t32 st_dev; + __kernel_ino_t32 st_ino; + __kernel_mode_t32 st_mode; + s16 st_nlink; + __kernel_uid_t32 st_uid; + __kernel_gid_t32 st_gid; + __kernel_dev_t32 st_rdev; + __kernel_off_t32 st_size; + compat_time_t st_atime; + u32 __unused1; + compat_time_t st_mtime; + u32 __unused2; + compat_time_t st_ctime; + u32 __unused3; + __kernel_off_t32 st_blksize; + __kernel_off_t32 st_blocks; + u32 __unused4[2]; +}; struct compat_timespec { compat_time_t tv_sec; diff --git a/include/asm-sparc64/dma-mapping.h b/include/asm-sparc64/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-sparc64/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-sparc64/fbio.h b/include/asm-sparc64/fbio.h index 3f5f3c81fee6..f21477bcfafc 100644 --- a/include/asm-sparc64/fbio.h +++ b/include/asm-sparc64/fbio.h @@ -93,23 +93,6 @@ struct fbgattr { #define FBIOSVIDEO _IOW('F', 7, int) #define FBIOGVIDEO _IOR('F', 8, int) -/* Cursor position */ -struct fbcurpos { -#ifdef __KERNEL__ - short fbx, fby; -#else - short x, y; -#endif -}; - -/* Cursor operations */ -#define FB_CUR_SETCUR 0x01 /* Enable/disable cursor display */ -#define FB_CUR_SETPOS 0x02 /* set cursor position */ -#define FB_CUR_SETHOT 0x04 /* set cursor hotspot */ -#define FB_CUR_SETCMAP 0x08 /* set color map for the cursor */ -#define FB_CUR_SETSHAPE 0x10 /* set shape */ -#define FB_CUR_SETALL 0x1F /* all of the above */ - struct fbcursor { short set; /* what to set, choose from the list above */ short enable; /* cursor on/off */ diff --git a/include/asm-sparc64/io.h b/include/asm-sparc64/io.h index 58a8ae58100a..4cf6e15170f0 100644 --- a/include/asm-sparc64/io.h +++ b/include/asm-sparc64/io.h @@ -304,6 +304,17 @@ static __inline__ u32 _sbus_readl(unsigned long addr) return ret; } +static __inline__ u64 _sbus_readq(unsigned long addr) +{ + u64 ret; + + __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* sbus_readq */" + : "=r" (ret) + : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); + + return ret; +} + static __inline__ void _sbus_writeb(u8 b, unsigned long addr) { __asm__ __volatile__("stba\t%r0, [%1] %2\t/* sbus_writeb */" @@ -325,12 +336,21 @@ static __inline__ void _sbus_writel(u32 l, unsigned long addr) : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); } +static __inline__ void _sbus_writeq(u64 l, unsigned long addr) +{ + __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* sbus_writeq */" + : /* no outputs */ + : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); +} + #define sbus_readb(__addr) (_sbus_readb((unsigned long)(__addr))) #define sbus_readw(__addr) (_sbus_readw((unsigned long)(__addr))) #define sbus_readl(__addr) (_sbus_readl((unsigned long)(__addr))) +#define sbus_readq(__addr) (_sbus_readq((unsigned long)(__addr))) #define sbus_writeb(__b, __addr) (_sbus_writeb((__b), (unsigned long)(__addr))) #define sbus_writew(__w, __addr) (_sbus_writew((__w), (unsigned long)(__addr))) #define sbus_writel(__l, __addr) (_sbus_writel((__l), (unsigned long)(__addr))) +#define sbus_writeq(__l, __addr) (_sbus_writeq((__l), (unsigned long)(__addr))) static inline void *_sbus_memset_io(unsigned long dst, int c, __kernel_size_t n) { diff --git a/include/asm-sparc64/posix_types.h b/include/asm-sparc64/posix_types.h index b459b4ad7a9f..dee9441f02d7 100644 --- a/include/asm-sparc64/posix_types.h +++ b/include/asm-sparc64/posix_types.h @@ -49,7 +49,6 @@ typedef struct { /* Now 32bit compatibility types */ typedef int __kernel_ptrdiff_t32; -typedef int __kernel_clock_t32; typedef int __kernel_pid_t32; typedef unsigned short __kernel_ipc_pid_t32; typedef unsigned short __kernel_uid_t32; diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h index 55eae0ac2162..af72b9e39911 100644 --- a/include/asm-sparc64/processor.h +++ b/include/asm-sparc64/processor.h @@ -18,7 +18,6 @@ #include <asm/a.out.h> #include <asm/pstate.h> #include <asm/ptrace.h> -#include <asm/signal.h> #include <asm/segment.h> #include <asm/page.h> #include <asm/delay.h> @@ -93,6 +92,8 @@ struct thread_struct { #ifndef __ASSEMBLY__ +#include <linux/types.h> + /* Return saved PC of a blocked thread. */ struct task_struct; extern unsigned long thread_saved_pc(struct task_struct *); diff --git a/include/asm-sparc64/siginfo.h b/include/asm-sparc64/siginfo.h index f4bb94656634..5104c270ca25 100644 --- a/include/asm-sparc64/siginfo.h +++ b/include/asm-sparc64/siginfo.h @@ -13,6 +13,8 @@ #ifdef __KERNEL__ +#include <asm/compat.h> + typedef union sigval32 { int sival_int; u32 sival_ptr; @@ -50,8 +52,8 @@ typedef struct siginfo32 { __kernel_pid_t32 _pid; /* which child */ unsigned int _uid; /* sender's uid */ int _status; /* exit code */ - __kernel_clock_t32 _utime; - __kernel_clock_t32 _stime; + compat_clock_t _utime; + compat_clock_t _stime; } _sigchld; /* SIGILL, SIGFPE, SIGSEGV, SIGBUS, SIGEMT */ diff --git a/include/asm-sparc64/stat.h b/include/asm-sparc64/stat.h index a1d8dc8acfcd..cc5b698a209a 100644 --- a/include/asm-sparc64/stat.h +++ b/include/asm-sparc64/stat.h @@ -3,28 +3,6 @@ #define _SPARC64_STAT_H #include <linux/types.h> -#include <linux/compat.h> -#include <linux/time.h> - -struct stat32 { - __kernel_dev_t32 st_dev; - __kernel_ino_t32 st_ino; - __kernel_mode_t32 st_mode; - short st_nlink; - __kernel_uid_t32 st_uid; - __kernel_gid_t32 st_gid; - __kernel_dev_t32 st_rdev; - __kernel_off_t32 st_size; - compat_time_t st_atime; - unsigned int __unused1; - compat_time_t st_mtime; - unsigned int __unused2; - compat_time_t st_ctime; - unsigned int __unused3; - __kernel_off_t32 st_blksize; - __kernel_off_t32 st_blocks; - unsigned int __unused4[2]; -}; struct stat { dev_t st_dev; diff --git a/include/asm-um/dma-mapping.h b/include/asm-um/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-um/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-v850/current.h b/include/asm-v850/current.h index 1d470a9b0bbd..30aae5673770 100644 --- a/include/asm-v850/current.h +++ b/include/asm-v850/current.h @@ -14,8 +14,11 @@ #ifndef __V850_CURRENT_H__ #define __V850_CURRENT_H__ +#ifndef __ASSEMBLY__ /* <linux/thread_info.h> is not asm-safe. */ +#include <linux/thread_info.h> +#endif + #include <asm/macrology.h> -#include <asm/thread_info.h> /* Register used to hold the current task pointer while in the kernel. diff --git a/include/asm-v850/dma-mapping.h b/include/asm-v850/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-v850/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-v850/elf.h b/include/asm-v850/elf.h index ee518cb6707d..0e42ae4ed529 100644 --- a/include/asm-v850/elf.h +++ b/include/asm-v850/elf.h @@ -22,6 +22,31 @@ typedef struct user_fpu_struct elf_fpregset_t; #define elf_check_arch(x) \ ((x)->e_machine == EM_V850 || (x)->e_machine == EM_CYGNUS_V850) + +/* v850 relocation types. */ +#define R_V850_NONE 0 +#define R_V850_9_PCREL 1 +#define R_V850_22_PCREL 2 +#define R_V850_HI16_S 3 +#define R_V850_HI16 4 +#define R_V850_LO16 5 +#define R_V850_32 6 +#define R_V850_16 7 +#define R_V850_8 8 +#define R_V850_SDA_16_16_OFFSET 9 /* For ld.b, st.b, set1, clr1, + not1, tst1, movea, movhi */ +#define R_V850_SDA_15_16_OFFSET 10 /* For ld.w, ld.h, ld.hu, st.w, st.h */ +#define R_V850_ZDA_16_16_OFFSET 11 /* For ld.b, st.b, set1, clr1, + not1, tst1, movea, movhi */ +#define R_V850_ZDA_15_16_OFFSET 12 /* For ld.w, ld.h, ld.hu, st.w, st.h */ +#define R_V850_TDA_6_8_OFFSET 13 /* For sst.w, sld.w */ +#define R_V850_TDA_7_8_OFFSET 14 /* For sst.h, sld.h */ +#define R_V850_TDA_7_7_OFFSET 15 /* For sst.b, sld.b */ +#define R_V850_TDA_16_16_OFFSET 16 /* For set1, clr1, not1, tst1, + movea, movhi */ +#define R_V850_NUM 17 + + /* * These are used to set parameters in the core dumps. */ diff --git a/include/asm-v850/mmu_context.h b/include/asm-v850/mmu_context.h index cfc839054a4d..2acc89920d05 100644 --- a/include/asm-v850/mmu_context.h +++ b/include/asm-v850/mmu_context.h @@ -1,8 +1,6 @@ #ifndef __V850_MMU_CONTEXT_H__ #define __V850_MMU_CONTEXT_H__ -#include <linux/sched.h> - #define destroy_context(mm) ((void)0) #define init_new_context(tsk,mm) 0 #define switch_mm(prev,next,tsk,cpu) ((void)0) diff --git a/include/asm-v850/processor.h b/include/asm-v850/processor.h index 714b384412c6..978a1e1720f2 100644 --- a/include/asm-v850/processor.h +++ b/include/asm-v850/processor.h @@ -15,9 +15,11 @@ #define __V850_PROCESSOR_H__ #include <linux/config.h> +#ifndef __ASSEMBLY__ /* <linux/thread_info.h> is not asm-safe. */ +#include <linux/thread_info.h> +#endif #include <asm/ptrace.h> -#include <asm/thread_info.h> #include <asm/entry.h> /* Some code expects `segment' stuff to be defined here. */ diff --git a/include/asm-v850/thread_info.h b/include/asm-v850/thread_info.h index be925c583037..3e20d565d5bd 100644 --- a/include/asm-v850/thread_info.h +++ b/include/asm-v850/thread_info.h @@ -31,15 +31,19 @@ struct thread_info { unsigned long flags; /* low level flags */ int cpu; /* cpu we're on */ int preempt_count; + struct restart_block restart_block; }; -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .exec_domain = &default_exec_domain, \ - .flags = 0, \ - .cpu = 0, \ - .preempt_count = 1 \ +#define INIT_THREAD_INFO(tsk) \ +{ \ + .task = &tsk, \ + .exec_domain = &default_exec_domain, \ + .flags = 0, \ + .cpu = 0, \ + .preempt_count = 1, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ } #define init_thread_info (init_thread_union.thread_info) @@ -67,8 +71,6 @@ struct thread_info { #define TI_FLAGS 8 #define TI_CPU 12 #define TI_PREEMPT 16 -#define TI_SOFTIRQ 20 -#define TI_HARDIRQ 24 #define PREEMPT_ACTIVE 0x4000000 diff --git a/include/asm-v850/uaccess.h b/include/asm-v850/uaccess.h index 201dd9b328d0..1db90103b7ed 100644 --- a/include/asm-v850/uaccess.h +++ b/include/asm-v850/uaccess.h @@ -4,7 +4,9 @@ /* * User space memory access functions */ -#include <linux/sched.h> + +#include <linux/errno.h> +#include <linux/string.h> #include <asm/segment.h> #include <asm/machdep.h> diff --git a/include/asm-v850/unistd.h b/include/asm-v850/unistd.h index 93939f4124d9..8eb57aef6db5 100644 --- a/include/asm-v850/unistd.h +++ b/include/asm-v850/unistd.h @@ -16,6 +16,7 @@ #include <asm/clinkage.h> +#define __NR_restart_syscall 0 #define __NR_exit 1 #define __NR_fork 2 #define __NR_read 3 diff --git a/include/asm-x86_64/bitops.h b/include/asm-x86_64/bitops.h index 4ea5626d2e84..72e575a68a33 100644 --- a/include/asm-x86_64/bitops.h +++ b/include/asm-x86_64/bitops.h @@ -89,7 +89,7 @@ static __inline__ void __clear_bit(int nr, volatile void * addr) /** * __change_bit - Toggle a bit in memory - * @nr: the bit to set + * @nr: the bit to change * @addr: the address to start counting from * * Unlike change_bit(), this function is non-atomic and may be reordered. @@ -106,7 +106,7 @@ static __inline__ void __change_bit(int nr, volatile void * addr) /** * change_bit - Toggle a bit in memory - * @nr: Bit to clear + * @nr: Bit to change * @addr: Address to start counting from * * change_bit() is atomic and may not be reordered. @@ -162,7 +162,7 @@ static __inline__ int __test_and_set_bit(int nr, volatile void * addr) /** * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to set + * @nr: Bit to clear * @addr: Address to count from * * This operation is atomic and cannot be reordered. @@ -181,7 +181,7 @@ static __inline__ int test_and_clear_bit(int nr, volatile void * addr) /** * __test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to set + * @nr: Bit to clear * @addr: Address to count from * * This operation is non-atomic and can be reordered. @@ -213,7 +213,7 @@ static __inline__ int __test_and_change_bit(int nr, volatile void * addr) /** * test_and_change_bit - Change a bit and return its new value - * @nr: Bit to set + * @nr: Bit to change * @addr: Address to count from * * This operation is atomic and cannot be reordered. @@ -260,6 +260,8 @@ static __inline__ int variable_test_bit(int nr, volatile void * addr) constant_test_bit((nr),(addr)) : \ variable_test_bit((nr),(addr))) +#undef ADDR + /** * find_first_zero_bit - find the first zero bit in a memory region * @addr: The address to start the search at diff --git a/include/asm-x86_64/calling.h b/include/asm-x86_64/calling.h index 9afea8132051..8bbf1971fd7b 100644 --- a/include/asm-x86_64/calling.h +++ b/include/asm-x86_64/calling.h @@ -29,6 +29,7 @@ #define RSP 152 #define SS 160 #define ARGOFFSET R11 +#define SWFRAME ORIG_RAX .macro SAVE_ARGS addskip=0,norcx=0 subq $9*8+\addskip,%rsp @@ -47,8 +48,11 @@ .endm #define ARG_SKIP 9*8 - .macro RESTORE_ARGS skiprax=0,addskip=0,skiprcx=0 + .macro RESTORE_ARGS skiprax=0,addskip=0,skiprcx=0,skipr11=0 + .if \skipr11 + .else movq (%rsp),%r11 + .endif movq 1*8(%rsp),%r10 movq 2*8(%rsp),%r9 movq 3*8(%rsp),%r8 diff --git a/include/asm-x86_64/compat.h b/include/asm-x86_64/compat.h new file mode 100644 index 000000000000..47e4aa499cc2 --- /dev/null +++ b/include/asm-x86_64/compat.h @@ -0,0 +1,57 @@ +#ifndef _ASM_X86_64_COMPAT_H +#define _ASM_X86_64_COMPAT_H +/* + * Architecture specific compatibility types + */ +#include <linux/types.h> + +#define COMPAT_USER_HZ 100 + +typedef u32 compat_size_t; +typedef s32 compat_ssize_t; +typedef s32 compat_time_t; +typedef s32 compat_suseconds_t; +typedef s32 compat_clock_t; +typedef s32 compat_pid_t; +typedef u16 compat_uid_t; +typedef u16 compat_gid_t; +typedef u16 compat_mode_t; +typedef u32 compat_ino_t; +typedef u16 compat_dev_t; +typedef s32 compat_off_t; +typedef u16 compat_nlink_t; + +struct compat_timespec { + compat_time_t tv_sec; + s32 tv_nsec; +}; + +struct compat_timeval { + compat_time_t tv_sec; + s32 tv_usec; +}; + +struct compat_stat { + compat_dev_t st_dev; + u16 __pad1; + compat_ino_t st_ino; + compat_mode_t st_mode; + compat_nlink_t st_nlink; + compat_uid_t st_uid; + compat_gid_t st_gid; + compat_dev_t st_rdev; + u16 __pad2; + u32 st_size; + u32 st_blksize; + u32 st_blocks; + u32 st_atime; + u32 st_atime_nsec; + u32 st_mtime; + u32 st_mtime_nsec; + u32 st_ctime; + u32 st_ctime_nsec; + u32 __unused4; + u32 __unused5; +}; + +#endif /* _ASM_X86_64_COMPAT_H */ diff --git a/include/asm-x86_64/desc.h b/include/asm-x86_64/desc.h index e5353cd3555b..f5775b7ddde5 100644 --- a/include/asm-x86_64/desc.h +++ b/include/asm-x86_64/desc.h @@ -165,31 +165,14 @@ static inline void set_ldt_desc(unsigned cpu, void *addr, int size) # error update this code. #endif - -static inline u64 load_TLS(struct thread_struct *t, int cpu) +static inline void load_TLS(struct thread_struct *t, unsigned int cpu) { - u64 *p, old, new, change; - union u { - struct desc_struct d; - u64 i; - }; - change = 0; - - /* check assembly! */ -#define C(i) \ - p = ((u64 *)cpu_gdt_table[cpu]) + GDT_ENTRY_TLS_MIN + i; \ - old = *p; \ - new = t->tls_array[i]; \ - change |= old - new; \ - *p = new; - - C(0); C(1); C(2); - return change; + u64 *gdt = (u64 *)(cpu_gdt_table[cpu] + GDT_ENTRY_TLS_MIN); + gdt[0] = t->tls_array[0]; + gdt[1] = t->tls_array[1]; + gdt[2] = t->tls_array[2]; } -#undef C - - /* * load one particular LDT into the current CPU */ diff --git a/include/asm-x86_64/dma-mapping.h b/include/asm-x86_64/dma-mapping.h new file mode 100644 index 000000000000..e7e16901f686 --- /dev/null +++ b/include/asm-x86_64/dma-mapping.h @@ -0,0 +1 @@ +#include <asm-generic/dma-mapping.h> diff --git a/include/asm-x86_64/elf.h b/include/asm-x86_64/elf.h index 52edff4b2756..7d9d5df88456 100644 --- a/include/asm-x86_64/elf.h +++ b/include/asm-x86_64/elf.h @@ -7,6 +7,7 @@ #include <asm/ptrace.h> #include <asm/user.h> +#include <asm/processor.h> typedef unsigned long elf_greg_t; @@ -14,7 +15,6 @@ typedef unsigned long elf_greg_t; typedef elf_greg_t elf_gregset_t[ELF_NGREG]; typedef struct user_i387_struct elf_fpregset_t; -typedef struct user_fxsr_struct elf_fpxregset_t; /* * This is used to ensure we don't load something for the wrong architecture. @@ -123,6 +123,17 @@ typedef struct user_fxsr_struct elf_fpxregset_t; extern void set_personality_64bit(void); #define SET_PERSONALITY(ex, ibcs2) set_personality_64bit() +extern int dump_task_regs (struct task_struct *, elf_gregset_t *); +extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *); + +#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs) +#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs) + +#ifdef CONFIG_SMP +extern void dump_smp_unlazy_fpu(void); +#define ELF_CORE_SYNC dump_smp_unlazy_fpu +#endif + #endif #endif diff --git a/include/asm-x86_64/hardirq.h b/include/asm-x86_64/hardirq.h index 8c34d3adf97a..a9c415b00b89 100644 --- a/include/asm-x86_64/hardirq.h +++ b/include/asm-x86_64/hardirq.h @@ -77,6 +77,9 @@ typedef struct { #define hardirq_endlock() do { } while (0) #define irq_enter() (preempt_count() += HARDIRQ_OFFSET) +#define nmi_enter() (irq_enter()) +#define nmi_exit() (preempt_count() -= HARDIRQ_OFFSET) + #if CONFIG_PREEMPT # define in_atomic() ((preempt_count() & ~PREEMPT_ACTIVE) != kernel_locked()) diff --git a/include/asm-x86_64/i387.h b/include/asm-x86_64/i387.h index 2a0292c00b54..f3d20c00741f 100644 --- a/include/asm-x86_64/i387.h +++ b/include/asm-x86_64/i387.h @@ -43,6 +43,12 @@ static inline int need_signal_i387(struct task_struct *me) save_init_fpu(tsk); \ } while (0) +#define unlazy_current_fpu() do { \ + if (test_thread_flag(TIF_USEDFPU)) \ + save_init_fpu(tsk); \ +} while (0) + + #define clear_fpu(tsk) do { \ if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \ asm volatile("fwait"); \ @@ -65,12 +71,6 @@ extern int set_fpregs(struct task_struct *tsk, struct user_i387_struct *buf); /* - * FPU state for core dumps... - */ -extern int dump_fpu(struct pt_regs *regs, - struct user_i387_struct *fpu); - -/* * i387 state interaction */ #define get_fpu_mxcsr(t) ((t)->thread.i387.fxsave.mxcsr) diff --git a/include/asm-x86_64/ia32.h b/include/asm-x86_64/ia32.h index 23be4a85e415..f257195d1740 100644 --- a/include/asm-x86_64/ia32.h +++ b/include/asm-x86_64/ia32.h @@ -5,29 +5,18 @@ #ifdef CONFIG_IA32_EMULATION +#include <linux/compat.h> + /* * 32 bit structures for IA32 support. */ /* 32bit compatibility types */ -typedef unsigned int __kernel_size_t32; -typedef int __kernel_ssize_t32; -typedef int __kernel_ptrdiff_t32; -typedef int __kernel_time_t32; -typedef int __kernel_clock_t32; -typedef int __kernel_pid_t32; typedef unsigned short __kernel_ipc_pid_t32; -typedef unsigned short __kernel_uid_t32; typedef unsigned __kernel_uid32_t32; -typedef unsigned short __kernel_gid_t32; typedef unsigned __kernel_gid32_t32; -typedef unsigned short __kernel_dev_t32; -typedef unsigned int __kernel_ino_t32; -typedef unsigned short __kernel_mode_t32; typedef unsigned short __kernel_umode_t32; -typedef short __kernel_nlink_t32; typedef int __kernel_daddr_t32; -typedef int __kernel_off_t32; typedef unsigned int __kernel_caddr_t32; typedef long __kernel_loff_t32; typedef __kernel_fsid_t __kernel_fsid_t32; @@ -37,9 +26,9 @@ typedef __kernel_fsid_t __kernel_fsid_t32; struct flock32 { short l_type; short l_whence; - __kernel_off_t32 l_start; - __kernel_off_t32 l_len; - __kernel_pid_t32 l_pid; + compat_off_t l_start; + compat_off_t l_len; + compat_pid_t l_pid; }; @@ -98,30 +87,6 @@ struct ucontext_ia32 { sigset32_t uc_sigmask; /* mask last for extensibility */ }; -struct stat32 { - unsigned short st_dev; - unsigned short __pad1; - unsigned int st_ino; - unsigned short st_mode; - unsigned short st_nlink; - unsigned short st_uid; - unsigned short st_gid; - unsigned short st_rdev; - unsigned short __pad2; - unsigned int st_size; - unsigned int st_blksize; - unsigned int st_blocks; - unsigned int st_atime; - unsigned int __unused1; - unsigned int st_mtime; - unsigned int __unused2; - unsigned int st_ctime; - unsigned int __unused3; - unsigned int __unused4; - unsigned int __unused5; -}; - - /* This matches struct stat64 in glibc2.2, hence the absolutely * insane amounts of padding around dev_t's. */ @@ -146,9 +111,12 @@ struct stat64 { long long st_blocks;/* Number 512-byte blocks allocated. */ - unsigned long long st_atime; - unsigned long long st_mtime; - unsigned long long st_ctime; + unsigned st_atime; + unsigned st_atime_nsec; + unsigned st_mtime; + unsigned st_mtime_nsec; + unsigned st_ctime; + unsigned st_ctime_nsec; unsigned long long st_ino; } __attribute__((packed)); @@ -204,8 +172,8 @@ typedef struct siginfo32 { unsigned int _pid; /* which child */ unsigned int _uid; /* sender's uid */ int _status; /* exit code */ - __kernel_clock_t32 _utime; - __kernel_clock_t32 _stime; + compat_clock_t _utime; + compat_clock_t _stime; } _sigchld; /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ @@ -224,7 +192,7 @@ typedef struct siginfo32 { struct ustat32 { __u32 f_tfree; - __kernel_ino_t32 f_tinode; + compat_ino_t f_tinode; char f_fname[6]; char f_fpack[6]; }; @@ -234,6 +202,8 @@ struct iovec32 { int iov_len; }; +#define IA32_PAGE_OFFSET 0xffff0000 +#define IA32_STACK_TOP IA32_PAGE_OFFSET #endif /* !CONFIG_IA32_SUPPORT */ diff --git a/include/asm-x86_64/ia32_unistd.h b/include/asm-x86_64/ia32_unistd.h index 21ed35ed964a..110e55509c9b 100644 --- a/include/asm-x86_64/ia32_unistd.h +++ b/include/asm-x86_64/ia32_unistd.h @@ -6,6 +6,7 @@ * this is for the kernel only. */ +#define __NR_ia32_restart_syscall 0 #define __NR_ia32_exit 1 #define __NR_ia32_fork 2 #define __NR_ia32_read 3 @@ -259,7 +260,13 @@ #define __NR_ia32_alloc_hugepages 250 #define __NR_ia32_free_hugepages 251 #define __NR_ia32_exit_group 252 +#define __NR_ia32_lookup_dcookie 253 +#define __NR_ia32_sys_epoll_create 254 +#define __NR_ia32_sys_epoll_ctl 255 +#define __NR_ia32_sys_epoll_wait 256 +#define __NR_ia32_remap_file_pages 257 +#define __NR_ia32_set_tid_address 258 -#define IA32_NR_syscalls 260 /* must be > than biggest syscall! */ +#define IA32_NR_syscalls 265 /* must be > than biggest syscall! */ #endif /* _ASM_X86_64_IA32_UNISTD_H_ */ diff --git a/include/asm-x86_64/ide.h b/include/asm-x86_64/ide.h index ac0d00e0d535..b2234e42ef5b 100644 --- a/include/asm-x86_64/ide.h +++ b/include/asm-x86_64/ide.h @@ -70,6 +70,7 @@ static __inline__ void ide_init_default_hwifs(void) int index; for(index = 0; index < MAX_HWIFS; index++) { + memset(&hw, 0, sizeof hw); ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL); hw.irq = ide_default_irq(ide_default_io_base(index)); ide_register_hw(&hw, NULL); diff --git a/include/asm-x86_64/io.h b/include/asm-x86_64/io.h index 8171bdd9f0d5..aabef395f935 100644 --- a/include/asm-x86_64/io.h +++ b/include/asm-x86_64/io.h @@ -178,19 +178,23 @@ extern void iounmap(void *addr); #define readb(addr) (*(volatile unsigned char *) __io_virt(addr)) #define readw(addr) (*(volatile unsigned short *) __io_virt(addr)) #define readl(addr) (*(volatile unsigned int *) __io_virt(addr)) +#define readq(addr) (*(volatile unsigned long *) __io_virt(addr)) #define __raw_readb readb #define __raw_readw readw #define __raw_readl readl +#define __raw_readq readq #define writeb(b,addr) (*(volatile unsigned char *) __io_virt(addr) = (b)) #define writew(b,addr) (*(volatile unsigned short *) __io_virt(addr) = (b)) #define writel(b,addr) (*(volatile unsigned int *) __io_virt(addr) = (b)) +#define writeq(b,addr) (*(volatile unsigned long *) __io_virt(addr) = (b)) #define __raw_writeb writeb #define __raw_writew writew #define __raw_writel writel +#define __raw_writeq writeq -void *memcpy_fromio(void*,void*,unsigned); -void *memcpy_toio(void*,void*,unsigned); +void *memcpy_fromio(void*,const void*,unsigned); +void *memcpy_toio(void*,const void*,unsigned); #define memset_io(a,b,c) memset(__io_virt(a),(b),(c)) /* @@ -215,7 +219,7 @@ void *memcpy_toio(void*,void*,unsigned); /* - * Again, i386 does not require mem IO specific function. + * Again, x86-64 does not require mem IO specific function. */ #define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),__io_virt(b),(c),(d)) diff --git a/include/asm-x86_64/io_apic.h b/include/asm-x86_64/io_apic.h index 8cee542f40f4..2975afd3f3e5 100644 --- a/include/asm-x86_64/io_apic.h +++ b/include/asm-x86_64/io_apic.h @@ -155,6 +155,8 @@ extern int io_apic_get_redir_entries (int ioapic); extern int io_apic_set_pci_routing (int ioapic, int pin, int irq); #endif +extern int sis_apic_bug; /* dummy */ + #else /* !CONFIG_X86_IO_APIC */ #define io_apic_assign_pci_irqs 0 diff --git a/include/asm-x86_64/mmu_context.h b/include/asm-x86_64/mmu_context.h index 118366346669..3a0c29d2e02b 100644 --- a/include/asm-x86_64/mmu_context.h +++ b/include/asm-x86_64/mmu_context.h @@ -12,8 +12,8 @@ /* * possibly do the LDT unload here? */ -#define destroy_context(mm) do { } while(0) int init_new_context(struct task_struct *tsk, struct mm_struct *mm); +void destroy_context(struct mm_struct *mm); #ifdef CONFIG_SMP diff --git a/include/asm-x86_64/module.h b/include/asm-x86_64/module.h index 874d34fcef68..67f8f69fa7b1 100644 --- a/include/asm-x86_64/module.h +++ b/include/asm-x86_64/module.h @@ -1,15 +1,10 @@ #ifndef _ASM_X8664_MODULE_H #define _ASM_X8664_MODULE_H -/* - * This file contains the x8664 architecture specific module code. - * Modules need to be mapped near the kernel code to allow 32bit relocations. - */ +struct mod_arch_specific {}; -extern void *module_map(unsigned long); -extern void module_unmap(void *); - -#define module_arch_init(x) (0) -#define arch_init_modules(x) do { } while (0) +#define Elf_Shdr Elf64_Shdr +#define Elf_Sym Elf64_Sym +#define Elf_Ehdr Elf64_Ehdr #endif diff --git a/include/asm-x86_64/mtrr.h b/include/asm-x86_64/mtrr.h index b165cefe7997..96a97091c0f7 100644 --- a/include/asm-x86_64/mtrr.h +++ b/include/asm-x86_64/mtrr.h @@ -30,16 +30,16 @@ struct mtrr_sentry { - __u64 base; /* Base address */ - __u32 size; /* Size of region */ + unsigned long base; /* Base address */ + unsigned int size; /* Size of region */ unsigned int type; /* Type of region */ }; struct mtrr_gentry { - __u64 base; /* Base address */ - __u32 size; /* Size of region */ + unsigned long base; /* Base address */ unsigned int regnum; /* Register number */ + unsigned int size; /* Size of region */ unsigned int type; /* Type of region */ }; @@ -65,49 +65,44 @@ struct mtrr_gentry #define MTRR_TYPE_WRBACK 6 #define MTRR_NUM_TYPES 7 -#ifdef MTRR_NEED_STRINGS -static char *mtrr_strings[MTRR_NUM_TYPES] = -{ - "uncachable", /* 0 */ - "write-combining", /* 1 */ - "?", /* 2 */ - "?", /* 3 */ - "write-through", /* 4 */ - "write-protect", /* 5 */ - "write-back", /* 6 */ -}; -#endif - #ifdef __KERNEL__ +extern char *mtrr_strings[MTRR_NUM_TYPES]; + /* The following functions are for use by other drivers */ -#ifdef CONFIG_MTRR -extern int mtrr_add (__u64 base, __u32 size, unsigned int type, char increment); -extern int mtrr_add_page (__u64 base, __u32 size, unsigned int type, char increment); -extern int mtrr_del (int reg, __u64 base, __u32 size); -extern int mtrr_del_page (int reg, __u64 base, __u32 size); -#else -static __inline__ int mtrr_add (__u64 base, __u32 size, +# ifdef CONFIG_MTRR +extern int mtrr_add (unsigned long base, unsigned long size, + unsigned int type, char increment); +extern int mtrr_add_page (unsigned long base, unsigned long size, + unsigned int type, char increment); +extern int mtrr_del (int reg, unsigned long base, unsigned long size); +extern int mtrr_del_page (int reg, unsigned long base, unsigned long size); +extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); +# else +static __inline__ int mtrr_add (unsigned long base, unsigned long size, unsigned int type, char increment) { return -ENODEV; } -static __inline__ int mtrr_add_page (__u64 base, __u32 size, +static __inline__ int mtrr_add_page (unsigned long base, unsigned long size, unsigned int type, char increment) { return -ENODEV; } -static __inline__ int mtrr_del (int reg, __u64 base, __u32 size) +static __inline__ int mtrr_del (int reg, unsigned long base, + unsigned long size) { return -ENODEV; } -static __inline__ int mtrr_del_page (int reg, __u64 base, __u32 size) +static __inline__ int mtrr_del_page (int reg, unsigned long base, + unsigned long size) { return -ENODEV; } -#endif -extern void mtrr_init_cpu(int cpu); +static __inline__ void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) {;} + +# endif #endif diff --git a/include/asm-x86_64/page.h b/include/asm-x86_64/page.h index 368bf5cc4bf4..41a2b59d9d7d 100644 --- a/include/asm-x86_64/page.h +++ b/include/asm-x86_64/page.h @@ -16,6 +16,11 @@ #define LARGE_PAGE_MASK (~(LARGE_PAGE_SIZE-1)) #define LARGE_PAGE_SIZE (1UL << PMD_SHIFT) +#define HPAGE_SHIFT PMD_SHIFT +#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT) +#define HPAGE_MASK (~(HPAGE_SIZE - 1)) +#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) + #ifdef __KERNEL__ #ifndef __ASSEMBLY__ diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h index 9147e8ca66f0..fd60629f3386 100644 --- a/include/asm-x86_64/pgtable.h +++ b/include/asm-x86_64/pgtable.h @@ -23,6 +23,7 @@ extern pgd_t level3_ident_pgt[512]; extern pmd_t level2_kernel_pgt[512]; extern pml4_t init_level4_pgt[]; extern pgd_t boot_vmalloc_pgt[]; +extern unsigned long __supported_pte_mask; #define swapper_pg_dir NULL @@ -97,7 +98,7 @@ static inline void set_pml4(pml4_t *dst, pml4_t val) } #define pgd_page(pgd) \ -((unsigned long) __va(pgd_val(pgd) & PAGE_MASK)) +((unsigned long) __va(pgd_val(pgd) & PHYSICAL_PAGE_MASK)) #define ptep_get_and_clear(xp) __pte(xchg(&(xp)->pte, 0)) #define pte_same(a, b) ((a).pte == (b).pte) @@ -159,46 +160,53 @@ static inline void set_pml4(pml4_t *dst, pml4_t val) #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED) +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX) +#define PAGE_SHARED_EXEC __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED) +#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX) +#define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED) +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX) +#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED) #define __PAGE_KERNEL \ + (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX) +#define __PAGE_KERNEL_EXECUTABLE \ (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED) #define __PAGE_KERNEL_NOCACHE \ - (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_PCD | _PAGE_ACCESSED) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_PCD | _PAGE_ACCESSED | _PAGE_NX) #define __PAGE_KERNEL_RO \ - (_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED) + (_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX) #define __PAGE_KERNEL_VSYSCALL \ (_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED) #define __PAGE_KERNEL_LARGE \ - (_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_PSE) + (_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_PSE | _PAGE_NX) #define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL) #define PAGE_KERNEL MAKE_GLOBAL(__PAGE_KERNEL) +#define PAGE_KERNEL_EXECUTABLE MAKE_GLOBAL(__PAGE_KERNEL_EXECUTABLE) #define PAGE_KERNEL_RO MAKE_GLOBAL(__PAGE_KERNEL_RO) #define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE) #define PAGE_KERNEL_VSYSCALL MAKE_GLOBAL(__PAGE_KERNEL_VSYSCALL) #define PAGE_KERNEL_LARGE MAKE_GLOBAL(__PAGE_KERNEL_LARGE) +/* xwr */ #define __P000 PAGE_NONE #define __P001 PAGE_READONLY #define __P010 PAGE_COPY #define __P011 PAGE_COPY -#define __P100 PAGE_READONLY -#define __P101 PAGE_READONLY -#define __P110 PAGE_COPY -#define __P111 PAGE_COPY +#define __P100 PAGE_READONLY_EXEC +#define __P101 PAGE_READONLY_EXEC +#define __P110 PAGE_COPY_EXEC +#define __P111 PAGE_COPY_EXEC #define __S000 PAGE_NONE #define __S001 PAGE_READONLY #define __S010 PAGE_SHARED #define __S011 PAGE_SHARED -#define __S100 PAGE_READONLY -#define __S101 PAGE_READONLY -#define __S110 PAGE_SHARED -#define __S111 PAGE_SHARED +#define __S100 PAGE_READONLY_EXEC +#define __S101 PAGE_READONLY_EXEC +#define __S110 PAGE_SHARED_EXEC +#define __S111 PAGE_SHARED_EXEC static inline unsigned long pgd_bad(pgd_t pgd) { @@ -220,11 +228,12 @@ static inline unsigned long pgd_bad(pgd_t pgd) static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot) { pte_t pte; - pte_val(pte) = (page_nr << PAGE_SHIFT) | pgprot_val(pgprot); + pte_val(pte) = (page_nr << PAGE_SHIFT); + pte_val(pte) |= pgprot_val(pgprot); + pte_val(pte) &= __supported_pte_mask; return pte; } - /* * The following only work if pte_present() is true. * Undefined behaviour if not.. @@ -304,10 +313,6 @@ static inline pgd_t *current_pgd_offset_k(unsigned long address) return __pgd_offset_k((pgd_t *)__va(addr), address); } -#if 0 /* disabled because of confusing/wrong naming. */ -#define __pgd_offset(address) pgd_index(address) -#endif - #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) /* PMD - Level 2 access */ diff --git a/include/asm-x86_64/processor.h b/include/asm-x86_64/processor.h index c918c56459a6..075a49ff9ba4 100644 --- a/include/asm-x86_64/processor.h +++ b/include/asm-x86_64/processor.h @@ -68,6 +68,7 @@ struct cpuinfo_x86 { #define X86_VENDOR_CENTAUR 5 #define X86_VENDOR_RISE 6 #define X86_VENDOR_TRANSMETA 7 +#define X86_VENDOR_NUM 8 #define X86_VENDOR_UNKNOWN 0xff extern struct cpuinfo_x86 boot_cpu_data; @@ -256,7 +257,7 @@ static inline void clear_in_cr4 (unsigned long mask) * space during mmap's. */ #define TASK_UNMAPPED_32 0x40000000 -#define TASK_UNMAPPED_64 (TASK_SIZE/3) +#define TASK_UNMAPPED_64 PAGE_ALIGN(TASK_SIZE/3) #define TASK_UNMAPPED_BASE \ (test_thread_flag(TIF_IA32) ? TASK_UNMAPPED_32 : TASK_UNMAPPED_64) @@ -337,8 +338,8 @@ struct thread_struct { #define EXCEPTION_STKSZ 1024 #define start_thread(regs,new_rip,new_rsp) do { \ - __asm__("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \ - wrmsrl(MSR_KERNEL_GS_BASE, 0); \ + asm volatile("movl %0,%%fs; movl %0,%%es; movl %0,%%ds": :"r" (0)); \ + load_gs_index(0); \ (regs)->rip = (new_rip); \ (regs)->rsp = (new_rsp); \ write_pda(oldrsp, (new_rsp)); \ @@ -358,7 +359,7 @@ extern void release_thread(struct task_struct *); */ extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); -extern void release_segments(struct mm_struct * mm); +static inline void release_segments(struct mm_struct *mm) { } /* * Return saved PC of a blocked thread. @@ -389,4 +390,31 @@ extern inline void rep_nop(void) #define cpu_relax() rep_nop() +/* + * NSC/Cyrix CPU configuration register indexes + */ +#define CX86_CCR0 0xc0 +#define CX86_CCR1 0xc1 +#define CX86_CCR2 0xc2 +#define CX86_CCR3 0xc3 +#define CX86_CCR4 0xe8 +#define CX86_CCR5 0xe9 +#define CX86_CCR6 0xea +#define CX86_CCR7 0xeb +#define CX86_DIR0 0xfe +#define CX86_DIR1 0xff +#define CX86_ARR_BASE 0xc4 +#define CX86_RCR_BASE 0xdc + +/* + * NSC/Cyrix CPU indexed register access macros + */ + +#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); }) + +#define setCx86(reg, data) do { \ + outb((reg), 0x22); \ + outb((data), 0x23); \ +} while (0) + #endif /* __ASM_X86_64_PROCESSOR_H */ diff --git a/include/asm-x86_64/scatterlist.h b/include/asm-x86_64/scatterlist.h index b8d12898a7fc..01d85d962c54 100644 --- a/include/asm-x86_64/scatterlist.h +++ b/include/asm-x86_64/scatterlist.h @@ -4,8 +4,8 @@ struct scatterlist { struct page *page; unsigned int offset; - dma_addr_t dma_address; unsigned int length; + dma_addr_t dma_address; }; #define ISA_DMA_THRESHOLD (0x00ffffff) diff --git a/include/asm-x86_64/socket32.h b/include/asm-x86_64/socket32.h index 58a5ed609398..c22075144ca7 100644 --- a/include/asm-x86_64/socket32.h +++ b/include/asm-x86_64/socket32.h @@ -1,6 +1,8 @@ #ifndef SOCKET32_H #define SOCKET32_H 1 +#include <linux/compat.h> + /* XXX This really belongs in some header file... -DaveM */ #define MAX_SOCK_ADDR 128 /* 108 for Unix domain - 16 for IP, 16 for IPX, @@ -11,14 +13,14 @@ struct msghdr32 { u32 msg_name; int msg_namelen; u32 msg_iov; - __kernel_size_t32 msg_iovlen; + compat_size_t msg_iovlen; u32 msg_control; - __kernel_size_t32 msg_controllen; + compat_size_t msg_controllen; unsigned msg_flags; }; struct cmsghdr32 { - __kernel_size_t32 cmsg_len; + compat_size_t cmsg_len; int cmsg_level; int cmsg_type; }; diff --git a/include/asm-x86_64/suspend.h b/include/asm-x86_64/suspend.h index 9f065f8fe33d..e5e4fb753746 100644 --- a/include/asm-x86_64/suspend.h +++ b/include/asm-x86_64/suspend.h @@ -1,6 +1,67 @@ -#ifndef SUSPEND_H -#define SUSPEND_H 1 +/* + * Copyright 2001-2002 Pavel Machek <pavel@suse.cz> + * Based on code + * Copyright 2001 Patrick Mochel <mochel@osdl.org> + */ +#include <asm/desc.h> +#include <asm/i387.h> -/* dummy for now */ +static inline void +arch_prepare_suspend(void) +{ +} +/* image of the saved processor state */ +struct saved_context { + u16 ds, es, fs, gs, ss; + unsigned long gs_base, fs_base; + unsigned long cr0, cr2, cr3, cr4; + u16 gdt_pad; + u16 gdt_limit; + unsigned long gdt_base; + u16 idt_pad; + u16 idt_limit; + unsigned long idt_base; + u16 ldt; + u16 tss; + unsigned long tr; + unsigned long safety; + unsigned long return_address; + unsigned long eflags; +} __attribute__((packed)); + +/* We'll access these from assembly, so we'd better have them outside struct */ +extern unsigned long saved_context_eax, saved_context_ebx, saved_context_ecx, saved_context_edx; +extern unsigned long saved_context_esp, saved_context_ebp, saved_context_esi, saved_context_edi; +extern unsigned long saved_context_r08, saved_context_r09, saved_context_r10, saved_context_r11; +extern unsigned long saved_context_r12, saved_context_r13, saved_context_r14, saved_context_r15; +extern unsigned long saved_context_eflags; + + +#define loaddebug(thread,register) \ + __asm__("movq %0,%%db" #register \ + : /* no output */ \ + :"r" ((thread)->debugreg[register])) + +extern void fix_processor_context(void); +extern void do_magic(int resume); + +#ifdef CONFIG_ACPI_SLEEP +extern unsigned long saved_eip; +extern unsigned long saved_esp; +extern unsigned long saved_ebp; +extern unsigned long saved_ebx; +extern unsigned long saved_esi; +extern unsigned long saved_edi; + +static inline void acpi_save_register_state(unsigned long return_point) +{ + /* FIXME: This is probably no longer correct: we need to save all caller-saved registers */ +} + +#define acpi_restore_register_state() do {} while (0) + +/* routines for saving/restoring kernel state */ +extern int acpi_save_state_mem(void); +extern int acpi_save_state_disk(void); #endif diff --git a/include/asm-x86_64/system.h b/include/asm-x86_64/system.h index da9563a84cda..f1281d48dc93 100644 --- a/include/asm-x86_64/system.h +++ b/include/asm-x86_64/system.h @@ -19,8 +19,25 @@ #define __PUSH(x) "pushq %%" __STR(x) "\n\t" #define __POP(x) "popq %%" __STR(x) "\n\t" -/* frame pointer must be last for get_wchan */ +struct save_context_frame { + unsigned long rbp; + unsigned long rbx; + unsigned long rcx; + unsigned long rdx; + unsigned long rsi; + unsigned long rdi; + unsigned long rax; + unsigned long r15; + unsigned long r14; + unsigned long r13; + unsigned long r12; + unsigned long r11; + unsigned long r10; + unsigned long r9; + unsigned long r8; +}; +/* frame pointer must be last for get_wchan */ /* It would be more efficient to let the compiler clobber most of these registers. Clobbering all is not possible because that lets reload freak out. Even just clobbering six generates wrong code with gcc 3.1 for me so do it this way for now. @@ -44,10 +61,11 @@ asm volatile(SAVE_CONTEXT \ "movq %%rsp,%[prevrsp]\n\t" \ "movq %[nextrsp],%%rsp\n\t" \ - "movq $1f,%[prevrip]\n\t" \ + "movq $thread_return,%[prevrip]\n\t" \ "pushq %[nextrip]\n\t" \ "jmp __switch_to\n\t" \ - "1:\n\t" \ + ".globl thread_return\n" \ + "thread_return:\n\t" \ RESTORE_CONTEXT \ :[prevrsp] "=m" (prev->thread.rsp), \ [prevrip] "=m" (prev->thread.rip) \ @@ -88,25 +106,31 @@ extern void load_gs_index(unsigned); * Clear and set 'TS' bit respectively */ #define clts() __asm__ __volatile__ ("clts") -#define read_cr0() ({ \ - unsigned long __dummy; \ - __asm__( \ - "movq %%cr0,%0\n\t" \ - :"=r" (__dummy)); \ - __dummy; \ -}) -#define write_cr0(x) \ - __asm__("movq %0,%%cr0": :"r" (x)); - -#define read_cr4() ({ \ - unsigned long __dummy; \ - __asm__( \ - "movq %%cr4,%0\n\t" \ - :"=r" (__dummy)); \ - __dummy; \ -}) -#define write_cr4(x) \ - __asm__("movq %0,%%cr4": :"r" (x)); + +static inline unsigned long read_cr0(void) +{ + unsigned long cr0; + asm volatile("movq %%cr0,%0" : "=r" (cr0)); + return cr0; +} + +static inline void write_cr0(unsigned long val) +{ + asm volatile("movq %0,%%cr0" :: "r" (val)); +} + +static inline unsigned long read_cr4(void) +{ + unsigned long cr4; + asm("movq %%cr4,%0" : "=r" (cr4)); + return cr4; +} + +static inline void write_cr4(unsigned long val) +{ + asm volatile("movq %0,%%cr4" :: "r" (val)); +} + #define stts() write_cr0(8 | read_cr0()) #define wbinvd() \ @@ -210,7 +234,6 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\ (unsigned long)(n),sizeof(*(ptr)))) - #ifdef CONFIG_SMP #define smp_mb() mb() #define smp_rmb() rmb() diff --git a/include/asm-x86_64/thread_info.h b/include/asm-x86_64/thread_info.h index 7d8f6d855119..69cac4da715d 100644 --- a/include/asm-x86_64/thread_info.h +++ b/include/asm-x86_64/thread_info.h @@ -29,6 +29,7 @@ struct thread_info { int preempt_count; mm_segment_t addr_limit; + struct restart_block restart_block; }; #endif @@ -46,6 +47,9 @@ struct thread_info { .cpu = 0, \ .preempt_count = 1, \ .addr_limit = KERNEL_DS, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ } #define init_thread_info (init_thread_union.thread_info) diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h index e0fc3815d8c1..2377301d8453 100644 --- a/include/asm-x86_64/unistd.h +++ b/include/asm-x86_64/unistd.h @@ -399,15 +399,15 @@ __SYSCALL(__NR_iopl, stub_iopl) __SYSCALL(__NR_ioperm, sys_ioperm) #define __NR_create_module 174 -__SYSCALL(__NR_create_module, sys_create_module) +__SYSCALL(__NR_create_module, sys_ni_syscall) #define __NR_init_module 175 __SYSCALL(__NR_init_module, sys_init_module) #define __NR_delete_module 176 __SYSCALL(__NR_delete_module, sys_delete_module) #define __NR_get_kernel_syms 177 -__SYSCALL(__NR_get_kernel_syms, sys_get_kernel_syms) +__SYSCALL(__NR_get_kernel_syms, sys_ni_syscall) #define __NR_query_module 178 -__SYSCALL(__NR_query_module, sys_query_module) +__SYSCALL(__NR_query_module, sys_ni_syscall) #define __NR_quotactl 179 __SYSCALL(__NR_quotactl, sys_quotactl) @@ -426,7 +426,8 @@ __SYSCALL(__NR_afs_syscall, sys_ni_syscall) #define __NR_tuxcall 184 /* reserved for tux */ __SYSCALL(__NR_tuxcall, sys_ni_syscall) -/* 165 currently unused */ +#define __NR_security 185 +__SYSCALL(__NR_security, sys_ni_syscall) #define __NR_gettid 186 __SYSCALL(__NR_gettid, sys_gettid) @@ -483,8 +484,24 @@ __SYSCALL(__NR_io_cancel, sys_io_cancel) __SYSCALL(__NR_get_thread_area, sys_get_thread_area) #define __NR_lookup_dcookie 212 __SYSCALL(__NR_lookup_dcookie, sys_lookup_dcookie) - -#define __NR_syscall_max __NR_lookup_dcookie +#define __NR_epoll_create 213 +__SYSCALL(__NR_epoll_create, sys_epoll_create) +#define __NR_epoll_ctl 214 +__SYSCALL(__NR_epoll_ctl, sys_epoll_ctl) +#define __NR_epoll_wait 215 +__SYSCALL(__NR_epoll_wait, sys_epoll_wait) +#define __NR_remap_file_pages 216 +__SYSCALL(__NR_remap_file_pages, sys_remap_file_pages) +#define __NR_getdents64 217 +__SYSCALL(__NR_getdents64, sys_getdents64) +#define __NR_set_tid_address 218 +__SYSCALL(__NR_set_tid_address, sys_set_tid_address) +#define __NR_restart_syscall 219 +__SYSCALL(__NR_restart_syscall, sys_restart_syscall) +#define __NR_semtimedop 220 +__SYSCALL(__NR_semtimedop, sys_semtimedop) + +#define __NR_syscall_max __NR_semtimedop #ifndef __NO_STUBS /* user-visible error numbers are in the range -1 - -4095 */ @@ -605,7 +622,7 @@ static inline pid_t setsid(void) return sys_setsid(); } -extern ssize_t sys_write(unsigned int, char *, size_t); +long sys_write(int fd, const char *buf, size_t size); static inline ssize_t write(unsigned int fd, char * buf, size_t count) { return sys_write(fd, buf, count); @@ -651,7 +668,7 @@ extern inline long exit(int error_code) } struct rusage; -asmlinkage long sys_wait4(pid_t pid,unsigned int * stat_addr, +long sys_wait4(pid_t pid,unsigned int * stat_addr, int options, struct rusage * ru); static inline pid_t waitpid(int pid, int * wait_stat, int flags) { diff --git a/include/linux/amigaffs.h b/include/linux/amigaffs.h index 4c8df68e48e2..bde160f417fd 100644 --- a/include/linux/amigaffs.h +++ b/include/linux/amigaffs.h @@ -28,7 +28,7 @@ affs_set_blocksize(struct super_block *sb, int size) static inline struct buffer_head * affs_bread(struct super_block *sb, int block) { - pr_debug(KERN_DEBUG "affs_bread: %d\n", block); + pr_debug("affs_bread: %d\n", block); if (block >= AFFS_SB(sb)->s_reserved && block < AFFS_SB(sb)->s_partition_size) return sb_bread(sb, block); return NULL; @@ -36,7 +36,7 @@ affs_bread(struct super_block *sb, int block) static inline struct buffer_head * affs_getblk(struct super_block *sb, int block) { - pr_debug(KERN_DEBUG "affs_getblk: %d\n", block); + pr_debug("affs_getblk: %d\n", block); if (block >= AFFS_SB(sb)->s_reserved && block < AFFS_SB(sb)->s_partition_size) return sb_getblk(sb, block); return NULL; @@ -45,7 +45,7 @@ static inline struct buffer_head * affs_getzeroblk(struct super_block *sb, int block) { struct buffer_head *bh; - pr_debug(KERN_DEBUG "affs_getzeroblk: %d\n", block); + pr_debug("affs_getzeroblk: %d\n", block); if (block >= AFFS_SB(sb)->s_reserved && block < AFFS_SB(sb)->s_partition_size) { bh = sb_getblk(sb, block); lock_buffer(bh); @@ -60,7 +60,7 @@ static inline struct buffer_head * affs_getemptyblk(struct super_block *sb, int block) { struct buffer_head *bh; - pr_debug(KERN_DEBUG "affs_getemptyblk: %d\n", block); + pr_debug("affs_getemptyblk: %d\n", block); if (block >= AFFS_SB(sb)->s_reserved && block < AFFS_SB(sb)->s_partition_size) { bh = sb_getblk(sb, block); wait_on_buffer(bh); @@ -73,7 +73,7 @@ static inline void affs_brelse(struct buffer_head *bh) { if (bh) - pr_debug(KERN_DEBUG "affs_brelse: %ld\n", bh->b_blocknr); + pr_debug("affs_brelse: %ld\n", bh->b_blocknr); brelse(bh); } diff --git a/include/linux/buffer_head.h b/include/linux/buffer_head.h index e9d6251fa168..7fc917c13f32 100644 --- a/include/linux/buffer_head.h +++ b/include/linux/buffer_head.h @@ -22,6 +22,7 @@ enum bh_state_bits { BH_New, /* Disk mapping was newly created by get_block */ BH_Async_Read, /* Is under end_buffer_async_read I/O */ BH_Async_Write, /* Is under end_buffer_async_write I/O */ + BH_Delay, /* Buffer is not yet allocated on disk */ BH_Boundary, /* Block is followed by a discontiguity */ BH_PrivateStart,/* not a state bit, but the first bit available @@ -105,6 +106,7 @@ BUFFER_FNS(Mapped, mapped) BUFFER_FNS(New, new) BUFFER_FNS(Async_Read, async_read) BUFFER_FNS(Async_Write, async_write) +BUFFER_FNS(Delay, delay); BUFFER_FNS(Boundary, boundary) #define bh_offset(bh) ((unsigned long)(bh)->b_data & ~PAGE_MASK) diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h new file mode 100644 index 000000000000..9d88549ff2fc --- /dev/null +++ b/include/linux/dma-mapping.h @@ -0,0 +1,17 @@ +#ifndef _ASM_LINUX_DMA_MAPPING_H +#define _ASM_LINUX_DMA_MAPPING_H + +/* These definitions mirror those in pci.h, so they can be used + * interchangeably with their PCI_ counterparts */ +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, + DMA_NONE = 3, +}; + +#include <asm/dma-mapping.h> + +#endif + + diff --git a/include/linux/elf.h b/include/linux/elf.h index f5702e3c7c20..2745227ff929 100644 --- a/include/linux/elf.h +++ b/include/linux/elf.h @@ -90,6 +90,9 @@ typedef __s64 Elf64_Sxword; */ #define EM_ALPHA 0x9026 +/* Bogus old v850 magic number, used by old tools. */ +#define EM_CYGNUS_V850 0x9080 + /* * This is the old interim value for S/390 architecture */ @@ -448,6 +451,27 @@ typedef struct { /* Keep this the last entry. */ #define R_390_NUM 27 +/* x86-64 relocation types */ +#define R_X86_64_NONE 0 /* No reloc */ +#define R_X86_64_64 1 /* Direct 64 bit */ +#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ +#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ +#define R_X86_64_PLT32 4 /* 32 bit PLT address */ +#define R_X86_64_COPY 5 /* Copy symbol at runtime */ +#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ +#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ +#define R_X86_64_RELATIVE 8 /* Adjust by program base */ +#define R_X86_64_GOTPCREL 9 /* 32 bit signed pc relative + offset to GOT */ +#define R_X86_64_32 10 /* Direct 32 bit zero extended */ +#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ +#define R_X86_64_16 12 /* Direct 16 bit zero extended */ +#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ +#define R_X86_64_8 14 /* Direct 8 bit sign extended */ +#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ + +#define R_X86_64_NUM 16 + /* s390 relocations defined by the ABIs */ #define R_390_NONE 0 /* No reloc. */ #define R_390_8 1 /* Direct 8 bit. */ diff --git a/include/linux/ext3_fs_i.h b/include/linux/ext3_fs_i.h index ec11e1ab01c5..02021676dd74 100644 --- a/include/linux/ext3_fs_i.h +++ b/include/linux/ext3_fs_i.h @@ -32,9 +32,30 @@ struct ext3_inode_info { __u32 i_file_acl; __u32 i_dir_acl; __u32 i_dtime; + + /* + * i_block_group is the number of the block group which contains + * this file's inode. Constant across the lifetime of the inode, + * it is ued for making block allocation decisions - we try to + * place a file's data blocks near its inode block, and new inodes + * near to their parent directory's inode. + */ __u32 i_block_group; __u32 i_state; /* Dynamic state flags for ext3 */ + + /* + * i_next_alloc_block is the logical (file-relative) number of the + * most-recently-allocated block in this file. Yes, it is misnamed. + * We use this for detecting linearly ascending allocation requests. + */ __u32 i_next_alloc_block; + + /* + * i_next_alloc_goal is the *physical* companion to i_next_alloc_block. + * it the the physical block number of the block which was most-recently + * allocated to this file. This give us the goal (target) for the next + * allocation when we detect linearly ascending requests. + */ __u32 i_next_alloc_goal; #ifdef EXT3_PREALLOCATE __u32 i_prealloc_block; diff --git a/include/linux/fb.h b/include/linux/fb.h index 0281509b85c8..23dd4c02ddec 100644 --- a/include/linux/fb.h +++ b/include/linux/fb.h @@ -412,9 +412,11 @@ struct fb_info { #define fb_readb sbus_readb #define fb_readw sbus_readw #define fb_readl sbus_readl +#define fb_readq sbus_readq #define fb_writeb sbus_writeb #define fb_writew sbus_writew #define fb_writel sbus_writel +#define fb_writeq sbus_writeq #define fb_memset sbus_memset_io #elif defined(__i386__) || defined(__alpha__) || defined(__x86_64__) || defined(__hppa__) diff --git a/include/linux/gfp.h b/include/linux/gfp.h index 8e093813e4f7..54bf03eaf3e7 100644 --- a/include/linux/gfp.h +++ b/include/linux/gfp.h @@ -18,6 +18,7 @@ #define __GFP_HIGHIO 0x80 /* Can start high mem physical IO? */ #define __GFP_FS 0x100 /* Can call down to low-level FS? */ #define __GFP_COLD 0x200 /* Cache-cold page required */ +#define __GFP_NOWARN 0x400 /* Suppress page allocation failure warning */ #define GFP_NOHIGHIO ( __GFP_WAIT | __GFP_IO) #define GFP_NOIO ( __GFP_WAIT) diff --git a/include/linux/init_task.h b/include/linux/init_task.h index d9b8c5d9b55c..77bc3a1340ac 100644 --- a/include/linux/init_task.h +++ b/include/linux/init_task.h @@ -63,7 +63,7 @@ .prio = MAX_PRIO-20, \ .static_prio = MAX_PRIO-20, \ .policy = SCHED_NORMAL, \ - .cpus_allowed = -1, \ + .cpus_allowed = ~0UL, \ .mm = NULL, \ .active_mm = &init_mm, \ .run_list = LIST_HEAD_INIT(tsk.run_list), \ diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h index f286bf9aeefd..14ce2049de71 100644 --- a/include/linux/mmzone.h +++ b/include/linux/mmzone.h @@ -193,16 +193,6 @@ typedef struct pglist_data { extern int numnodes; extern struct pglist_data *pgdat_list; -static inline int -memclass(struct zone *pgzone, struct zone *classzone) -{ - if (pgzone->zone_pgdat != classzone->zone_pgdat) - return 0; - if (pgzone > classzone) - return 0; - return 1; -} - void get_zone_counts(unsigned long *active, unsigned long *inactive); void build_all_zonelists(void); void wakeup_kswapd(struct zone *zone); @@ -335,11 +325,6 @@ static inline unsigned int num_online_memblks(void) #define num_online_memblks() 1 #endif /* CONFIG_DISCONTIGMEM || CONFIG_NUMA */ - - -#define MAP_ALIGN(x) ((((x) % sizeof(struct page)) == 0) ? (x) : ((x) + \ - sizeof(struct page) - ((x) % sizeof(struct page)))) - #endif /* !__ASSEMBLY__ */ #endif /* __KERNEL__ */ #endif /* _LINUX_MMZONE_H */ diff --git a/include/linux/nfs4.h b/include/linux/nfs4.h index 36e71c8ed51e..7c0d596db02f 100644 --- a/include/linux/nfs4.h +++ b/include/linux/nfs4.h @@ -203,6 +203,9 @@ enum open_delegation_type4 { enum { NFSPROC4_CLNT_NULL = 0, /* Unused */ NFSPROC4_CLNT_COMPOUND, /* Soon to be unused */ + NFSPROC4_CLNT_READ, + NFSPROC4_CLNT_WRITE, + NFSPROC4_CLNT_COMMIT, }; #endif diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h index 2673e32cc4ba..bc44563921f7 100644 --- a/include/linux/nfs_fs.h +++ b/include/linux/nfs_fs.h @@ -222,7 +222,7 @@ loff_t page_offset(struct page *page) static inline loff_t req_offset(struct nfs_page *req) { - return ((loff_t)req->wb_index) << PAGE_CACHE_SHIFT; + return (((loff_t)req->wb_index) << PAGE_CACHE_SHIFT) + req->wb_offset; } /* @@ -295,8 +295,7 @@ extern int nfs_writepage(struct page *page, struct writeback_control *wbc); extern int nfs_writepages(struct address_space *, struct writeback_control *); extern int nfs_flush_incompatible(struct file *file, struct page *page); extern int nfs_updatepage(struct file *, struct page *, unsigned int, unsigned int); -extern void nfs_writeback_done(struct rpc_task *task, int stable, - unsigned int arg_count, unsigned int res_count); +extern void nfs_writeback_done(struct rpc_task *task); extern void nfs_writedata_release(struct rpc_task *task); #if defined(CONFIG_NFS_V3) || defined(CONFIG_NFS_V4) @@ -369,7 +368,7 @@ extern int nfs_readpage(struct file *, struct page *); extern int nfs_readpages(struct file *, struct address_space *, struct list_head *, unsigned); extern int nfs_pagein_list(struct list_head *, int); -extern void nfs_readpage_result(struct rpc_task *, unsigned int count, int eof); +extern void nfs_readpage_result(struct rpc_task *); extern void nfs_readdata_release(struct rpc_task *); /* diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h index af914e160fc6..2b96e1e5aa97 100644 --- a/include/linux/nfs_xdr.h +++ b/include/linux/nfs_xdr.h @@ -35,6 +35,7 @@ struct nfs_fattr { struct timespec atime; struct timespec mtime; struct timespec ctime; + __u32 bitmap[2]; /* NFSv4 returned attribute bitmap */ __u64 change_attr; /* NFSv4 change attribute */ __u64 pre_change_attr;/* pre-op NFSv4 change attribute */ unsigned long timestamp; @@ -346,12 +347,6 @@ struct nfs4_close { u32 cl_seqid; /* request */ }; -struct nfs4_commit { - u64 co_start; /* request */ - u32 co_len; /* request */ - struct nfs_writeverf * co_verifier; /* response */ -}; - struct nfs4_create { u32 cr_ftype; /* request */ union { /* request */ @@ -422,15 +417,6 @@ struct nfs4_putfh { struct nfs_fh * pf_fhandle; /* request */ }; -struct nfs4_read { - u64 rd_offset; /* request */ - u32 rd_length; /* request */ - u32 *rd_eof; /* response */ - u32 *rd_bytes_read; /* response */ - struct page ** rd_pages; /* zero-copy data */ - unsigned int rd_pgbase; /* zero-copy data */ -}; - struct nfs4_readdir { u64 rd_cookie; /* request */ nfs4_verifier rd_req_verifier; /* request */ @@ -476,22 +462,11 @@ struct nfs4_setclientid { struct nfs4_client * sc_state; /* response */ }; -struct nfs4_write { - u64 wr_offset; /* request */ - u32 wr_stable_how; /* request */ - u32 wr_len; /* request */ - u32 * wr_bytes_written; /* response */ - struct nfs_writeverf * wr_verf; /* response */ - struct page ** wr_pages; /* zero-copy data */ - unsigned int wr_pgbase; /* zero-copy data */ -}; - struct nfs4_op { u32 opnum; union { struct nfs4_access access; struct nfs4_close close; - struct nfs4_commit commit; struct nfs4_create create; struct nfs4_getattr getattr; struct nfs4_getfh getfh; @@ -500,7 +475,6 @@ struct nfs4_op { struct nfs4_open open; struct nfs4_open_confirm open_confirm; struct nfs4_putfh putfh; - struct nfs4_read read; struct nfs4_readdir readdir; struct nfs4_readlink readlink; struct nfs4_remove remove; @@ -509,7 +483,6 @@ struct nfs4_op { struct nfs4_setattr setattr; struct nfs4_setclientid setclientid; struct nfs4_client * setclientid_confirm; - struct nfs4_write write; } u; }; @@ -548,20 +521,11 @@ struct nfs_read_data { struct nfs_fattr fattr; /* fattr storage */ struct list_head pages; /* Coalesced read requests */ struct page *pagevec[NFS_READ_MAXIOV]; - union { - struct { - struct nfs_readargs args; - struct nfs_readres res; - } v3; /* also v2 */ + struct nfs_readargs args; + struct nfs_readres res; #ifdef CONFIG_NFS_V4 - struct { - struct nfs4_compound compound; - struct nfs4_op ops[3]; - u32 res_count; - u32 res_eof; - } v4; + unsigned long timestamp; /* For lease renewal */ #endif - } u; }; struct nfs_write_data { @@ -572,21 +536,11 @@ struct nfs_write_data { struct nfs_writeverf verf; struct list_head pages; /* Coalesced requests we wish to flush */ struct page *pagevec[NFS_WRITE_MAXIOV]; - union { - struct { - struct nfs_writeargs args; /* argument struct */ - struct nfs_writeres res; /* result struct */ - } v3; + struct nfs_writeargs args; /* argument struct */ + struct nfs_writeres res; /* result struct */ #ifdef CONFIG_NFS_V4 - struct { - struct nfs4_compound compound; - struct nfs4_op ops[3]; - u32 arg_count; - u32 arg_stable; - u32 res_count; - } v4; + unsigned long timestamp; /* For lease renewal */ #endif - } u; }; /* diff --git a/include/linux/pci.h b/include/linux/pci.h index 557b17d959c1..3fa241545729 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -558,8 +558,16 @@ void pcibios_fixup_pbus_ranges(struct pci_bus *, struct pbus_set_ranges_data *); /* Generic PCI functions used internally */ int pci_bus_exists(const struct list_head *list, int nr); -struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); -struct pci_bus *pci_alloc_primary_bus(int bus); +struct pci_bus *pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata); +static inline struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata) +{ + return pci_scan_bus_parented(NULL, bus, ops, sysdata); +} +struct pci_bus *pci_alloc_primary_bus_parented(struct device * parent, int bus); +static inline struct pci_bus *pci_alloc_primary_bus(int bus) +{ + return pci_alloc_primary_bus_parented(NULL, bus); +} struct pci_dev *pci_scan_slot(struct pci_dev *temp); int pci_proc_attach_device(struct pci_dev *dev); int pci_proc_detach_device(struct pci_dev *dev); @@ -826,5 +834,92 @@ extern int pci_pci_problems; #define PCIPCI_VIAETBF 8 #define PCIPCI_VSFX 16 +#include <linux/dma-mapping.h> + +/* If you define PCI_NEW_DMA_COMPAT_API it means you support the new DMA API + * and you want the pci_ DMA API to be implemented using it. + */ +#if defined(PCI_NEW_DMA_COMPAT_API) && defined(CONFIG_PCI) + +/* note pci_set_dma_mask isn't here, since it's a public function + * exported from drivers/pci, use dma_supported instead */ + +static inline int +pci_dma_supported(struct pci_dev *hwdev, u64 mask) +{ + return dma_supported(&hwdev->dev, mask); +} + +static inline void * +pci_alloc_consistent(struct pci_dev *hwdev, size_t size, + dma_addr_t *dma_handle) +{ + return dma_alloc_coherent(&hwdev->dev, size, dma_handle); +} + +static inline void +pci_free_consistent(struct pci_dev *hwdev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + dma_free_coherent(&hwdev->dev, size, vaddr, dma_handle); +} + +static inline dma_addr_t +pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction) +{ + return dma_map_single(&hwdev->dev, ptr, size, (enum dma_data_direction)direction); +} + +static inline void +pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, + size_t size, int direction) +{ + dma_unmap_single(&hwdev->dev, dma_addr, size, (enum dma_data_direction)direction); +} + +static inline dma_addr_t +pci_map_page(struct pci_dev *hwdev, struct page *page, + unsigned long offset, size_t size, int direction) +{ + return dma_map_page(&hwdev->dev, page, offset, size, (enum dma_data_direction)direction); +} + +static inline void +pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address, + size_t size, int direction) +{ + dma_unmap_page(&hwdev->dev, dma_address, size, (enum dma_data_direction)direction); +} + +static inline int +pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, + int nents, int direction) +{ + return dma_map_sg(&hwdev->dev, sg, nents, (enum dma_data_direction)direction); +} + +static inline void +pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, + int nents, int direction) +{ + dma_unmap_sg(&hwdev->dev, sg, nents, (enum dma_data_direction)direction); +} + +static inline void +pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle, + size_t size, int direction) +{ + dma_sync_single(&hwdev->dev, dma_handle, size, (enum dma_data_direction)direction); +} + +static inline void +pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg, + int nelems, int direction) +{ + dma_sync_sg(&hwdev->dev, sg, nelems, (enum dma_data_direction)direction); +} + +#endif + #endif /* __KERNEL__ */ #endif /* LINUX_PCI_H */ diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 4f90ff1ccbe8..1befa5e1830b 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -410,6 +410,7 @@ #define PCI_DEVICE_ID_AMD_8111_IDE 0x7469 #define PCI_DEVICE_ID_AMD_8111_AUDIO 0x746d #define PCI_DEVICE_ID_AMD_8151_0 0x7454 +#define PCI_DEVICE_ID_AMD_8131_APIC 0x7450 #define PCI_VENDOR_ID_TRIDENT 0x1023 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX 0x2000 diff --git a/include/linux/sched.h b/include/linux/sched.h index d0726cb87145..7c3bbfc255ed 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -419,13 +419,12 @@ do { if (atomic_dec_and_test(&(tsk)->usage)) __put_task_struct(tsk); } while(0) #define PF_MEMALLOC 0x00000800 /* Allocating memory */ #define PF_MEMDIE 0x00001000 /* Killed for out-of-memory */ #define PF_FLUSHER 0x00002000 /* responsible for disk writeback */ -#define PF_NOWARN 0x00004000 /* debug: don't warn if alloc fails */ -#define PF_FREEZE 0x00008000 /* this task should be frozen for suspend */ -#define PF_IOTHREAD 0x00010000 /* this thread is needed for doing I/O to swap */ -#define PF_FROZEN 0x00020000 /* frozen for system suspend */ -#define PF_FSTRANS 0x00040000 /* inside a filesystem transaction */ -#define PF_KSWAPD 0x00080000 /* I am kswapd */ +#define PF_FREEZE 0x00004000 /* this task should be frozen for suspend */ +#define PF_IOTHREAD 0x00008000 /* this thread is needed for doing I/O to swap */ +#define PF_FROZEN 0x00010000 /* frozen for system suspend */ +#define PF_FSTRANS 0x00020000 /* inside a filesystem transaction */ +#define PF_KSWAPD 0x00040000 /* I am kswapd */ /* * Ptrace flags diff --git a/include/linux/slab.h b/include/linux/slab.h index 3a5a6d576f93..997bc710bfb0 100644 --- a/include/linux/slab.h +++ b/include/linux/slab.h @@ -23,7 +23,7 @@ typedef struct kmem_cache_s kmem_cache_t; #define SLAB_KERNEL GFP_KERNEL #define SLAB_DMA GFP_DMA -#define SLAB_LEVEL_MASK (__GFP_WAIT|__GFP_HIGH|__GFP_IO|__GFP_HIGHIO|__GFP_FS) +#define SLAB_LEVEL_MASK (__GFP_WAIT|__GFP_HIGH|__GFP_IO|__GFP_HIGHIO|__GFP_FS|__GFP_COLD|__GFP_NOWARN) #define SLAB_NO_GROW 0x00001000UL /* don't grow a cache */ /* flags to pass to kmem_cache_create(). diff --git a/include/linux/swap.h b/include/linux/swap.h index c635f392d6c1..9ab02098aad5 100644 --- a/include/linux/swap.h +++ b/include/linux/swap.h @@ -7,6 +7,7 @@ #include <linux/linkage.h> #include <linux/mmzone.h> #include <linux/list.h> +#include <linux/sched.h> #include <asm/atomic.h> #include <asm/page.h> @@ -14,6 +15,11 @@ #define SWAP_FLAG_PRIO_MASK 0x7fff #define SWAP_FLAG_PRIO_SHIFT 0 +static inline int current_is_kswapd(void) +{ + return current->flags & PF_KSWAPD; +} + /* * MAX_SWAPFILES defines the maximum number of swaptypes: things which can * be swapped to. The swap type and the offset into that swap type are diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h index 8b014e109f20..137609a3cf0a 100644 --- a/include/scsi/scsi.h +++ b/include/scsi/scsi.h @@ -99,6 +99,8 @@ extern const unsigned char scsi_command_size[8]; #define READ_16 0x88 #define WRITE_16 0x8a #define SERVICE_ACTION_IN 0x9e +/* values for service action in */ +#define SAI_READ_CAPACITY_16 0x10 /* |