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authorAndrew Morton <akpm@osdl.org>2004-01-19 05:06:19 -0800
committerLinus Torvalds <torvalds@home.osdl.org>2004-01-19 05:06:19 -0800
commitb58f2e6f01c7e57aa1d96a5e7ed56cd7b84d0709 (patch)
treed3f15f8971d88aa11c6b6344ae2f986fb98f77cb /include
parenta5ab05a59369fe16e18c5063848e62c9c8025ac8 (diff)
[PATCH] cpu_sibling_map fix
From: "Nakajima, Jun" <jun.nakajima@intel.com> Restore the HT detection algorithm. Make the processor package mapping subarch-specific so that it can reflect the APIC ID info provided by BIOS if required.
Diffstat (limited to 'include')
-rw-r--r--include/asm-i386/genapic.h2
-rw-r--r--include/asm-i386/mach-bigsmp/mach_apic.h5
-rw-r--r--include/asm-i386/mach-default/mach_apic.h5
-rw-r--r--include/asm-i386/mach-es7000/mach_apic.h5
-rw-r--r--include/asm-i386/mach-generic/mach_apic.h1
-rw-r--r--include/asm-i386/mach-numaq/mach_apic.h6
-rw-r--r--include/asm-i386/mach-summit/mach_apic.h11
-rw-r--r--include/asm-i386/mach-visws/mach_apic.h6
8 files changed, 41 insertions, 0 deletions
diff --git a/include/asm-i386/genapic.h b/include/asm-i386/genapic.h
index 76465ccbbdf8..7a165f27c880 100644
--- a/include/asm-i386/genapic.h
+++ b/include/asm-i386/genapic.h
@@ -45,6 +45,7 @@ struct genapic {
void (*setup_portio_remap)(void);
int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
void (*enable_apic_mode)(void);
+ u32 (*phys_pkg_id)(u32 cpuid_apic, int index_msb);
/* mpparse */
void (*mpc_oem_bus_info)(struct mpc_config_bus *, char *,
@@ -105,6 +106,7 @@ struct genapic {
APICFUNC(send_IPI_allbutself), \
APICFUNC(send_IPI_all), \
APICFUNC(enable_apic_mode), \
+ APICFUNC(phys_pkg_id), \
}
extern struct genapic *genapic;
diff --git a/include/asm-i386/mach-bigsmp/mach_apic.h b/include/asm-i386/mach-bigsmp/mach_apic.h
index 0e9855144660..12980e389c65 100644
--- a/include/asm-i386/mach-bigsmp/mach_apic.h
+++ b/include/asm-i386/mach-bigsmp/mach_apic.h
@@ -173,4 +173,9 @@ static inline unsigned int cpu_mask_to_apicid(cpumask_const_t cpumask)
return apicid;
}
+static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
+{
+ return cpuid_apic >> index_msb;
+}
+
#endif /* __ASM_MACH_APIC_H */
diff --git a/include/asm-i386/mach-default/mach_apic.h b/include/asm-i386/mach-default/mach_apic.h
index 1d427aadfa41..5111b015f710 100644
--- a/include/asm-i386/mach-default/mach_apic.h
+++ b/include/asm-i386/mach-default/mach_apic.h
@@ -127,4 +127,9 @@ static inline void enable_apic_mode(void)
{
}
+static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
+{
+ return cpuid_apic >> index_msb;
+}
+
#endif /* __ASM_MACH_APIC_H */
diff --git a/include/asm-i386/mach-es7000/mach_apic.h b/include/asm-i386/mach-es7000/mach_apic.h
index e15b73c7e113..72e87d081af6 100644
--- a/include/asm-i386/mach-es7000/mach_apic.h
+++ b/include/asm-i386/mach-es7000/mach_apic.h
@@ -192,4 +192,9 @@ static inline unsigned int cpu_mask_to_apicid(cpumask_const_t cpumask)
return apicid;
}
+static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
+{
+ return cpuid_apic >> index_msb;
+}
+
#endif /* __ASM_MACH_APIC_H */
diff --git a/include/asm-i386/mach-generic/mach_apic.h b/include/asm-i386/mach-generic/mach_apic.h
index 21f0e75f1b25..ed349c793beb 100644
--- a/include/asm-i386/mach-generic/mach_apic.h
+++ b/include/asm-i386/mach-generic/mach_apic.h
@@ -27,5 +27,6 @@
#define check_apicid_used (genapic->check_apicid_used)
#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
#define enable_apic_mode (genapic->enable_apic_mode)
+#define phys_pkg_id (genapic->phys_pkg_id)
#endif /* __ASM_MACH_APIC_H */
diff --git a/include/asm-i386/mach-numaq/mach_apic.h b/include/asm-i386/mach-numaq/mach_apic.h
index 814ee9aa2521..743bb69aa275 100644
--- a/include/asm-i386/mach-numaq/mach_apic.h
+++ b/include/asm-i386/mach-numaq/mach_apic.h
@@ -141,4 +141,10 @@ static inline unsigned int cpu_mask_to_apicid(cpumask_const_t cpumask)
return (int) 0xF;
}
+/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
+static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
+{
+ return cpuid_apic >> index_msb;
+}
+
#endif /* __ASM_MACH_APIC_H */
diff --git a/include/asm-i386/mach-summit/mach_apic.h b/include/asm-i386/mach-summit/mach_apic.h
index a10b4591737e..accca8fcc970 100644
--- a/include/asm-i386/mach-summit/mach_apic.h
+++ b/include/asm-i386/mach-summit/mach_apic.h
@@ -173,4 +173,15 @@ static inline unsigned int cpu_mask_to_apicid(cpumask_const_t cpumask)
return apicid;
}
+/* cpuid returns the value latched in the HW at reset, not the APIC ID
+ * register's value. For any box whose BIOS changes APIC IDs, like
+ * clustered APIC systems, we must use hard_smp_processor_id.
+ *
+ * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
+ */
+static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
+{
+ return hard_smp_processor_id() >> index_msb;
+}
+
#endif /* __ASM_MACH_APIC_H */
diff --git a/include/asm-i386/mach-visws/mach_apic.h b/include/asm-i386/mach-visws/mach_apic.h
index 9a0208496458..3ec402a3a96a 100644
--- a/include/asm-i386/mach-visws/mach_apic.h
+++ b/include/asm-i386/mach-visws/mach_apic.h
@@ -88,4 +88,10 @@ static inline unsigned int cpu_mask_to_apicid(cpumask_const_t cpumask)
{
return cpus_coerce_const(cpumask);
}
+
+static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
+{
+ return cpuid_apic >> index_msb;
+}
+
#endif /* __ASM_MACH_APIC_H */