Merge bk://are.twiddle.net/axp-2.5

into home.transmeta.com:/home/torvalds/v2.5/linux

3 files changed, 30 insertions, 50 deletions

diff --git a/include/asm-alpha/core_irongate.h b/include/asm-alpha/core_irongate.h
index 4a4e6fa4c0e8..9b9a49feb51b 100644
--- a/include/asm-alpha/core_irongate.h
+++ b/include/asm-alpha/core_irongate.h
@@ -50,13 +50,14 @@ typedef struct {
 
 	igcsr32 bacsr10;		/* 0x40 - base address chip selects */
 	igcsr32 bacsr32;		/* 0x44 - base address chip selects */
-	igcsr32 bacsr54;		/* 0x48 - base address chip selects */
+	igcsr32 bacsr54_eccms761;	/* 0x48 - 751: base addr. chip selects
+						  761: ECC, mode/status */
 
 	igcsr32 rsrvd2[1];		/* 0x4C-0x4F reserved */
 
 	igcsr32 drammap;		/* 0x50 - address mapping control */
 	igcsr32 dramtm;			/* 0x54 - timing, driver strength */
-	igcsr32 dramms;			/* 0x58 - ECC, mode/status */
+	igcsr32 dramms;			/* 0x58 - DRAM mode/status */
 
 	igcsr32 rsrvd3[1];		/* 0x5C-0x5F reserved */
 
@@ -73,7 +74,10 @@ typedef struct {
 	igcsr32 pciarb;			/* 0x84 - PCI arbitration control */
 	igcsr32 pcicfg;			/* 0x88 - PCI config status */
 
-	igcsr32 rsrvd6[5];		/* 0x8C-0x9F reserved */
+	igcsr32 rsrvd6[4];		/* 0x8C-0x9B reserved */
+
+	igcsr32 pci_mem;		/* 0x9C - PCI top of memory,
+						  761 only */
 
 	/* AGP (bus 1) control registers */
 	igcsr32 agpcap;			/* 0xA0 - AGP Capability Identifier */
@@ -102,6 +106,7 @@ typedef struct {
 
 } Irongate1;
 
+extern igcsr32 *IronECC;
 
 /*
  * Memory spaces:
diff --git a/include/asm-alpha/elf.h b/include/asm-alpha/elf.h
index 9513f35aa8a1..033597e3e0ab 100644
--- a/include/asm-alpha/elf.h
+++ b/include/asm-alpha/elf.h
@@ -52,53 +52,25 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 
 #define ELF_PLAT_INIT(_r)       _r->r0 = 0
 
-/* Use the same format as the OSF/1 procfs interface.  The register
-   layout is sane.  However, since dump_thread() creates the funky
-   layout that ECOFF coredumps want, we need to undo that layout here.
-   Eventually, it would be nice if the ECOFF core-dump had to do the
-   translation, then ELF_CORE_COPY_REGS() would become trivial and
-   faster.  */
-
-#define ELF_CORE_COPY_REGS(_dest,_regs)					\
-{									\
-	extern void dump_thread(struct pt_regs *, struct user *);	\
-	struct user _dump;						\
-									\
-	dump_thread(_regs, &_dump);					\
-	_dest[ 0] = _dump.regs[EF_V0];					\
-	_dest[ 1] = _dump.regs[EF_T0];					\
-	_dest[ 2] = _dump.regs[EF_T1];					\
-	_dest[ 3] = _dump.regs[EF_T2];					\
-	_dest[ 4] = _dump.regs[EF_T3];					\
-	_dest[ 5] = _dump.regs[EF_T4];					\
-	_dest[ 6] = _dump.regs[EF_T5];					\
-	_dest[ 7] = _dump.regs[EF_T6];					\
-	_dest[ 8] = _dump.regs[EF_T7];					\
-	_dest[ 9] = _dump.regs[EF_S0];					\
-	_dest[10] = _dump.regs[EF_S1];					\
-	_dest[11] = _dump.regs[EF_S2];					\
-	_dest[12] = _dump.regs[EF_S3];					\
-	_dest[13] = _dump.regs[EF_S4];					\
-	_dest[14] = _dump.regs[EF_S5];					\
-	_dest[15] = _dump.regs[EF_S6];					\
-	_dest[16] = _dump.regs[EF_A0];					\
-	_dest[17] = _dump.regs[EF_A1];					\
-	_dest[18] = _dump.regs[EF_A2];					\
-	_dest[19] = _dump.regs[EF_A3];					\
-	_dest[20] = _dump.regs[EF_A4];					\
-	_dest[21] = _dump.regs[EF_A5];					\
-	_dest[22] = _dump.regs[EF_T8];					\
-	_dest[23] = _dump.regs[EF_T9];					\
-	_dest[24] = _dump.regs[EF_T10];					\
-	_dest[25] = _dump.regs[EF_T11];					\
-	_dest[26] = _dump.regs[EF_RA];					\
-	_dest[27] = _dump.regs[EF_T12];					\
-	_dest[28] = _dump.regs[EF_AT];					\
-	_dest[29] = _dump.regs[EF_GP];					\
-	_dest[30] = _dump.regs[EF_SP];					\
-	_dest[31] = _dump.regs[EF_PC];	/* store PC here */		\
-	_dest[32] = _dump.regs[EF_PS];					\
-}
+/* The registers are layed out in pt_regs for PAL and syscall
+   convenience.  Re-order them for the linear elf_gregset_t.  */
+
+extern void dump_elf_thread(elf_greg_t *dest, struct pt_regs *pt,
+			    struct thread_info *ti);
+#define ELF_CORE_COPY_REGS(DEST, REGS) \
+	dump_elf_thread(DEST, REGS, current_thread_info());
+
+/* Similar, but for a thread other than current.  */
+
+extern int dump_elf_task(elf_greg_t *dest, struct task_struct *task);
+#define ELF_CORE_COPY_TASK_REGS(TASK, DEST) \
+	dump_elf_task(*(DEST), TASK)
+
+/* Similar, but for the FP registers.  */
+
+extern int dump_elf_task_fp(elf_fpreg_t *dest, struct task_struct *task);
+#define ELF_CORE_COPY_FPREGS(TASK, DEST) \
+	dump_elf_task_fp(*(DEST), TASK)
 
 /* This yields a mask that user programs can use to figure out what
    instruction set this CPU supports.  This is trivial on Alpha, 
diff --git a/include/asm-alpha/topology.h b/include/asm-alpha/topology.h
index fe77fb5b4105..742b68802fd0 100644
--- a/include/asm-alpha/topology.h
+++ b/include/asm-alpha/topology.h
@@ -43,6 +43,9 @@ static inline int node_to_cpumask(int node)
 # define node_to_memblk(node)		(node)
 # define memblk_to_node(memblk)	(memblk)
 
+/* Cross-node load balancing interval. */
+# define NODE_BALANCE_RATE 10
+
 #else /* CONFIG_NUMA */
 # include <asm-generic/topology.h>
 #endif /* !CONFIG_NUMA */