v2.5.1.8 -> v2.5.1.9

- Russell King: large ARM update
- Adam Richter et al: more kdev_t updates

131 files changed, 5533 insertions, 2332 deletions

diff --git a/include/asm-arm/arch-adifcc/adi_evb.h b/include/asm-arm/arch-adifcc/adi_evb.h
new file mode 100644
index 000000000000..f4b74c6fcf9a
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/adi_evb.h
@@ -0,0 +1,19 @@
+/*
+ * linux/include/asm/arch-80200fcc/adi_evb.h
+ *
+ * ADI 80200FCC evaluation board definitions
+ *
+ * Author: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright (C) 2001 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#define ADI_EVB__RAMBASE	0xa0000000
+#define ADI_EVB__UART		0x00400000    /* UART */
+#define ADI_EVB_7SEG_1		0x00500000    /* 7-Segment */
+
diff --git a/include/asm-arm/arch-adifcc/dma.h b/include/asm-arm/arch-adifcc/dma.h
new file mode 100644
index 000000000000..19aa1dbc3be7
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/dma.h
@@ -0,0 +1,18 @@
+/*
+ * linux/include/asm-arm/arch-80200fcc/dma.h
+ *
+ * Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS		0xffffffff
+
+/* No DMA */
+#define MAX_DMA_CHANNELS	0
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-adifcc/hardware.h b/include/asm-arm/arch-adifcc/hardware.h
new file mode 100644
index 000000000000..9eeb3cb507da
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/hardware.h
@@ -0,0 +1,27 @@
+/*
+ * linux/include/asm-arm/arch-adifcc/hardware.h
+ *
+ * Hardware definitions for ADI based systems
+ *
+ * Author: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright (C) 2000-2001 MontaVista Software Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/config.h>
+
+#define PCIO_BASE	0
+
+#if defined(CONFIG_ARCH_ADI_EVB)
+#include "adi_evb.h"
+#endif
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-adifcc/io.h b/include/asm-arm/arch-adifcc/io.h
new file mode 100644
index 000000000000..bdcaec08bddf
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/io.h
@@ -0,0 +1,22 @@
+/*
+ * linux/include/asm-arm/arch-adifcc/io.h
+ *
+ * Author: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright (C) 2001  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)			(PCIO_BASE + (a))
+#define __mem_pci(a)		((unsigned long)(a))
+#define __mem_isa(a)		((unsigned long)(a))
+
+#endif
diff --git a/include/asm-arm/arch-adifcc/irq.h b/include/asm-arm/arch-adifcc/irq.h
new file mode 100644
index 000000000000..9477252c7971
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/irq.h
@@ -0,0 +1,13 @@
+/*
+ *  linux/include/asm-arm/arch-adifcc/irq.h
+ *
+ *  Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define fixup_irq(irq)  (irq)
+
+
diff --git a/include/asm-arm/arch-adifcc/irqs.h b/include/asm-arm/arch-adifcc/irqs.h
new file mode 100644
index 000000000000..fc390753716a
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/irqs.h
@@ -0,0 +1,28 @@
+/*
+ * linux/include/asm-arm/arch-80200fcc/irqs.h
+ *
+ * Author:	Deepak Saxena <dsaxena@mvista.com>
+ * Copyright:	(C) 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define IRQ_XS80200_BCU		0	/* Bus Control Unit */
+#define IRQ_XS80200_PMU		1	/* Performance Monitoring Unit */
+#define IRQ_XS80200_EXTIRQ	2	/* external IRQ signal */
+#define IRQ_XS80200_EXTFIQ	3	/* external IRQ signal */
+
+#define NR_XS80200_IRQS		4
+#define NR_IRQS			NR_XS80200_IRQS
+
+#define	IRQ_XSCALE_PMU		IRQ_XS80200_PMU
+
+#ifdef CONFIG_XSCALE_ADI_EVB
+
+/* Interrupts available on the ADI Eval Board */
+
+#endif
+
+
diff --git a/include/asm-arm/arch-adifcc/memory.h b/include/asm-arm/arch-adifcc/memory.h
new file mode 100644
index 000000000000..bb0307809a40
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/memory.h
@@ -0,0 +1,57 @@
+/*
+ * linux/include/asm-arm/arch-adifcc/memory.h
+ *
+ * Copyright (c) 2001 MontaVista Software, Inc.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE	(0xc0000000UL)
+#define TASK_SIZE_26	(0x04000000UL)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
+
+/*
+ * Page offset: 3GB
+ */
+#define PAGE_OFFSET	(0xc0000000UL)
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET	(0xC0000000UL)
+
+/*
+ * physical vs virtual ram conversion
+ */
+#define __virt_to_phys__is_a_macro
+#define __phys_to_virt__is_a_macro
+#define __virt_to_phys(x)	((x) - PAGE_OFFSET + PHYS_OFFSET)
+#define __phys_to_virt(x)	((x) - PHYS_OFFSET + PAGE_OFFSET)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *		address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *		to an address that the kernel can use.
+ *
+ * These are dummies for now.
+ */
+#define __virt_to_bus__is_a_macro
+#define __bus_to_virt__is_a_macro
+#define __virt_to_bus(x)	 __virt_to_phys(x)
+#define __bus_to_virt(x)	 __phys_to_virt(x)
+
+#define	PHYS_TO_NID(x)		0
+
+#endif
diff --git a/include/asm-arm/arch-adifcc/param.h b/include/asm-arm/arch-adifcc/param.h
new file mode 100644
index 000000000000..e825e31e0252
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/param.h
@@ -0,0 +1,3 @@
+/*
+ * linux/include/asm-arm/arch-adifcc/param.h
+ */
diff --git a/include/asm-arm/arch-adifcc/serial.h b/include/asm-arm/arch-adifcc/serial.h
new file mode 100644
index 000000000000..e7555e6ab12b
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/serial.h
@@ -0,0 +1,36 @@
+/*
+ * include/asm-arm/arch-adifcc/serial.h
+ *
+ * Author: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright (c) 2001 MontaVista Software, Inc.
+ */
+
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD ( 1852000 / 16 )
+
+/* Standard COM flags */
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+
+#ifdef CONFIG_ARCH_ADI_EVB
+
+#define RS_TABLE_SIZE 1
+
+/*
+ * One serial port, int goes to FIQ, so we run in polled mode
+ */
+#define STD_SERIAL_PORT_DEFNS			\
+       /* UART CLK      PORT        IRQ        FLAGS        */			\
+	{ 0, BASE_BAUD, 0xff400000, 0,  STD_COM_FLAGS }  /* ttyS0 */
+
+#define EXTRA_SERIAL_PORT_DEFNS
+
+#endif
+
diff --git a/include/asm-arm/arch-adifcc/system.h b/include/asm-arm/arch-adifcc/system.h
new file mode 100644
index 000000000000..a600254530de
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/system.h
@@ -0,0 +1,29 @@
+/*
+ * linux/include/asm-arm/arch-adifcc/system.h
+ *
+ * Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+static inline void arch_idle(void)
+{
+#if 0
+	if (!hlt_counter)
+		cpu_do_idle(0);
+#endif
+}
+
+
+static inline void arch_reset(char mode)
+{
+	if ( 1 && mode == 's') {
+		/* Jump into ROM at address 0 */
+		cpu_reset(0);
+	} else {
+		/* Use on-chip reset capability */
+	}
+}
+
diff --git a/include/asm-arm/arch-adifcc/time.h b/include/asm-arm/arch-adifcc/time.h
new file mode 100644
index 000000000000..75e1c7eb77bc
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/time.h
@@ -0,0 +1,9 @@
+/*
+ * linux/include/asm-arm/arch-adifcc/time.h
+ *
+ */
+
+/*
+ * No on board timer, implemenation @ arch/arm/kernel/xscale-time.c
+ */
+
diff --git a/include/asm-arm/arch-adifcc/timex.h b/include/asm-arm/arch-adifcc/timex.h
new file mode 100644
index 000000000000..d994c8abecd5
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/timex.h
@@ -0,0 +1,10 @@
+/*
+ * linux/include/asm-arm/arch-adifcc/timex.h
+ *
+ * XScale architecture timex specifications
+ */
+
+/* This is for a timer based on the XS80200's PMU counter */
+
+#define CLOCK_TICK_RATE 600000000 /* Underlying HZ */
+
diff --git a/include/asm-arm/arch-adifcc/uncompress.h b/include/asm-arm/arch-adifcc/uncompress.h
new file mode 100644
index 000000000000..792b4e17aa86
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/uncompress.h
@@ -0,0 +1,35 @@
+/*
+ * linux/include/asm-arm/arch-adifcc/uncompress.h
+ *
+ * Author: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright (c) 2001 MontaVista Software, Inc.
+ *
+ */
+
+#define UART_BASE    ((volatile unsigned char *)0x00400000)
+
+static __inline__ void putc(char c)
+{
+	while ((UART_BASE[5] & 0x60) != 0x60);
+	UART_BASE[0] = c;
+}
+
+/*
+ * This does not append a newline
+ */
+static void puts(const char *s)
+{
+	while (*s) {
+		putc(*s);
+		if (*s == '\n')
+			putc('\r');
+		s++;
+	}
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-adifcc/vmalloc.h b/include/asm-arm/arch-adifcc/vmalloc.h
new file mode 100644
index 000000000000..0bcc35c827b3
--- /dev/null
+++ b/include/asm-arm/arch-adifcc/vmalloc.h
@@ -0,0 +1,16 @@
+/*
+ * linux/include/asm-arm/arch-adifcc/vmalloc.h
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET	  (8*1024*1024)
+#define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       (0xe8000000)
diff --git a/include/asm-arm/arch-anakin/io.h b/include/asm-arm/arch-anakin/io.h
index f535f6cbab4f..5b0f4d8e511c 100644
--- a/include/asm-arm/arch-anakin/io.h
+++ b/include/asm-arm/arch-anakin/io.h
@@ -17,12 +17,7 @@
 
 #define IO_SPACE_LIMIT		0xffffffff
 
-#define __io(a)			a
-#define __arch_getw(a)		(*(volatile unsigned short *) (a))
-#define __arch_putw(b, a)	(*(volatile unsigned short *) (a) = (b))
-
-#define iomem_valid_addr(i, s)	1
-#define iomem_to_phys(i)	i
+#define __io(a)			(a)
 
 /*
  * We don't support ins[lb]/outs[lb].  Make them fault.
diff --git a/include/asm-arm/arch-anakin/time.h b/include/asm-arm/arch-anakin/time.h
index 97717b5860e1..88d1c6efee1e 100644
--- a/include/asm-arm/arch-anakin/time.h
+++ b/include/asm-arm/arch-anakin/time.h
@@ -20,8 +20,7 @@ anakin_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 	do_timer(regs);
 }
 
-static inline void
-setup_timer(void)
+void __init time_init(void)
 {
 	timer_irq.handler = anakin_timer_interrupt;
 	timer_irq.flags = SA_INTERRUPT;
diff --git a/include/asm-arm/arch-arc/io.h b/include/asm-arm/arch-arc/io.h
index e874501c84fa..11c9ce687ab4 100644
--- a/include/asm-arm/arch-arc/io.h
+++ b/include/asm-arm/arch-arc/io.h
@@ -249,4 +249,10 @@ DECLARE_IO(int,l,"")
 /* the following macro is depreciated */
 #define ioaddr(port)			__ioaddr((port))
 
+/*
+ * No ioremap support here.
+ */
+#define __arch_ioremap(c,s,f)	((void *)(c))
+#define __arch_iounmap(c)	do { }  while (0)
+
 #endif
diff --git a/include/asm-arm/arch-arc/irq.h b/include/asm-arm/arch-arc/irq.h
index 40424ea5bddd..4951c6995168 100644
--- a/include/asm-arm/arch-arc/irq.h
+++ b/include/asm-arm/arch-arc/irq.h
@@ -6,143 +6,5 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- *  Changelog:
- *   24-09-1996	RMK	Created
- *   10-10-1996	RMK	Brought up to date with arch-sa110eval
- *   22-10-1996	RMK	Changed interrupt numbers & uses new inb/outb macros
- *   11-01-1998	RMK	Added mask_and_ack_irq
- *   22-08-1998	RMK	Restructured IRQ routines
  */
-#include <linux/config.h>
-#include <asm/hardware/ioc.h>
-#include <asm/io.h>
-
-#ifdef CONFIG_ARCH_ARC
-#define a_clf()	clf()
-#define a_stf()	stf()
-#else
-#define a_clf()	do { } while (0)
-#define a_stf()	do { } while (0)
-#endif
-
 #define fixup_irq(x) (x)
-
-static void arc_mask_irq_ack_a(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << irq;
-	a_clf();
-	val = ioc_readb(IOC_IRQMASKA);
-	ioc_writeb(val & ~mask, IOC_IRQMASKA);
-	ioc_writeb(mask, IOC_IRQCLRA);
-	a_stf();
-}
-
-static void arc_mask_irq_a(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << irq;
-	a_clf();
-	val = ioc_readb(IOC_IRQMASKA);
-	ioc_writeb(val & ~mask, IOC_IRQMASKA);
-	a_stf();
-}
-
-static void arc_unmask_irq_a(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << irq;
-	a_clf();
-	val = ioc_readb(IOC_IRQMASKA);
-	ioc_writeb(val | mask, IOC_IRQMASKA);
-	a_stf();
-}
-
-static void arc_mask_irq_b(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = ioc_readb(IOC_IRQMASKB);
-	ioc_writeb(val & ~mask, IOC_IRQMASKB);
-}
-
-static void arc_unmask_irq_b(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = ioc_readb(IOC_IRQMASKB);
-	ioc_writeb(val | mask, IOC_IRQMASKB);
-}
-
-static void arc_mask_irq_fiq(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = ioc_readb(IOC_FIQMASK);
-	ioc_writeb(val & ~mask, IOC_FIQMASK);
-}
-
-static void arc_unmask_irq_fiq(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = ioc_readb(IOC_FIQMASK);
-	ioc_writeb(val | mask, IOC_FIQMASK);
-}
-
-static __inline__ void irq_init_irq(void)
-{
-	int irq;
-
-	ioc_writeb(0, IOC_IRQMASKA);
-	ioc_writeb(0, IOC_IRQMASKB);
-	ioc_writeb(0, IOC_FIQMASK);
-
-	for (irq = 0; irq < NR_IRQS; irq++) {
-		switch (irq) {
-		case 0 ... 6:
-			irq_desc[irq].probe_ok = 1;
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = arc_mask_irq_ack_a;
-			irq_desc[irq].mask     = arc_mask_irq_a;
-			irq_desc[irq].unmask   = arc_unmask_irq_a;
-			break;
-
-		case 7:
-			irq_desc[irq].noautoenable = 1;
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = arc_mask_irq_ack_a;
-			irq_desc[irq].mask     = arc_mask_irq_a;
-			irq_desc[irq].unmask   = arc_unmask_irq_a;
-			break;
-
-		case 9 ... 15:
-			irq_desc[irq].probe_ok = 1;
-		case 8:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = arc_mask_irq_b;
-			irq_desc[irq].mask     = arc_mask_irq_b;
-			irq_desc[irq].unmask   = arc_unmask_irq_b;
-			break;
-
-		case 64 ... 72:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = arc_mask_irq_fiq;
-			irq_desc[irq].mask     = arc_mask_irq_fiq;
-			irq_desc[irq].unmask   = arc_unmask_irq_fiq;
-			break;
-		}
-	}
-
-	irq_desc[IRQ_KEYBOARDTX].noautoenable = 1;
-
-	init_FIQ();
-}
diff --git a/include/asm-arm/arch-arc/time.h b/include/asm-arm/arch-arc/time.h
index ef13a0466c96..394bb5388614 100644
--- a/include/asm-arm/arch-arc/time.h
+++ b/include/asm-arm/arch-arc/time.h
@@ -24,7 +24,7 @@ static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 /*
  * Set up timer interrupt.
  */
-static inline void setup_timer(void)
+void __init time_init(void)
 {
 	ioctime_init();
 
diff --git a/include/asm-arm/arch-cl7500/irq.h b/include/asm-arm/arch-cl7500/irq.h
index 393efaddba37..4b286331f3f8 100644
--- a/include/asm-arm/arch-cl7500/irq.h
+++ b/include/asm-arm/arch-cl7500/irq.h
@@ -30,198 +30,3 @@ static inline int fixup_irq(unsigned int irq)
 
 	return irq;
 }
-
-static void cl7500_mask_irq_ack_a(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << irq;
-	val = iomd_readb(IOMD_IRQMASKA);
-	iomd_writeb(val & ~mask, IOMD_IRQMASKA);
-	iomd_writeb(mask, IOMD_IRQCLRA);
-}
-
-static void cl7500_mask_irq_a(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << irq;
-	val = iomd_readb(IOMD_IRQMASKA);
-	iomd_writeb(val & ~mask, IOMD_IRQMASKA);
-}
-
-static void cl7500_unmask_irq_a(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << irq;
-	val = iomd_readb(IOMD_IRQMASKA);
-	iomd_writeb(val | mask, IOMD_IRQMASKA);
-}
-
-static void cl7500_mask_irq_b(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_IRQMASKB);
-	iomd_writeb(val & ~mask, IOMD_IRQMASKB);
-}
-
-static void cl7500_unmask_irq_b(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_IRQMASKB);
-	iomd_writeb(val | mask, IOMD_IRQMASKB);
-}
-
-static void cl7500_mask_irq_c(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_IRQMASKC);
-	iomd_writeb(val & ~mask, IOMD_IRQMASKC);
-}
-
-static void cl7500_unmask_irq_c(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_IRQMASKC);
-	iomd_writeb(val | mask, IOMD_IRQMASKC);
-}
-
-
-static void cl7500_mask_irq_d(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_IRQMASKD);
-	iomd_writeb(val & ~mask, IOMD_IRQMASKD);
-}
-
-static void cl7500_unmask_irq_d(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_IRQMASKD);
-	iomd_writeb(val | mask, IOMD_IRQMASKD);
-}
-
-static void cl7500_mask_irq_dma(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_DMAMASK);
-	iomd_writeb(val & ~mask, IOMD_DMAMASK);
-}
-
-static void cl7500_unmask_irq_dma(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_DMAMASK);
-	iomd_writeb(val | mask, IOMD_DMAMASK);
-}
-
-static void cl7500_mask_irq_fiq(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_FIQMASK);
-	iomd_writeb(val & ~mask, IOMD_FIQMASK);
-}
-
-static void cl7500_unmask_irq_fiq(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_FIQMASK);
-	iomd_writeb(val | mask, IOMD_FIQMASK);
-}
-
-static void no_action(int cpl, void *dev_id, struct pt_regs *regs)
-{
-}
-
-static struct irqaction irq_isa = { no_action, 0, 0, "isa", NULL, NULL };
-
-static __inline__ void irq_init_irq(void)
-{
-	int irq;
-
-	iomd_writeb(0, IOMD_IRQMASKA);
-	iomd_writeb(0, IOMD_IRQMASKB);
-	iomd_writeb(0, IOMD_FIQMASK);
-	iomd_writeb(0, IOMD_DMAMASK);
-
-	for (irq = 0; irq < NR_IRQS; irq++) {
-		switch (irq) {
-		case 0 ... 6:
-			irq_desc[irq].probe_ok = 1;
-		case 7:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = cl7500_mask_irq_ack_a;
-			irq_desc[irq].mask     = cl7500_mask_irq_a;
-			irq_desc[irq].unmask   = cl7500_unmask_irq_a;
-			break;
-
-		case 9 ... 15:
-			irq_desc[irq].probe_ok = 1;
-		case 8:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = cl7500_mask_irq_b;
-			irq_desc[irq].mask     = cl7500_mask_irq_b;
-			irq_desc[irq].unmask   = cl7500_unmask_irq_b;
-			break;
-
-		case 16 ... 22:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = cl7500_mask_irq_dma;
-			irq_desc[irq].mask     = cl7500_mask_irq_dma;
-			irq_desc[irq].unmask   = cl7500_unmask_irq_dma;
-			break;
-
-		case 24 ... 31:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = cl7500_mask_irq_c;
-			irq_desc[irq].mask     = cl7500_mask_irq_c;
-			irq_desc[irq].unmask   = cl7500_unmask_irq_c;
-			break;
-
-		case 40 ... 47:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = cl7500_mask_irq_d;
-			irq_desc[irq].mask     = cl7500_mask_irq_d;
-			irq_desc[irq].unmask   = cl7500_unmask_irq_d;
-			break;
-
-		case 48 ... 55:
-			irq_desc[irq].valid      = 1;
-			irq_desc[irq].probe_ok   = 1;
-			irq_desc[irq].mask_ack   = no_action;
-			irq_desc[irq].mask       = no_action;
-			irq_desc[irq].unmask     = no_action;
-			break;
-
-		case 64 ... 72:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = cl7500_mask_irq_fiq;
-			irq_desc[irq].mask     = cl7500_mask_irq_fiq;
-			irq_desc[irq].unmask   = cl7500_unmask_irq_fiq;
-			break;
-		}
-	}
-
-	setup_arm_irq(IRQ_ISA, &irq_isa);
-}
diff --git a/include/asm-arm/arch-cl7500/keyboard.h b/include/asm-arm/arch-cl7500/keyboard.h
index 55815c4cbe40..660b31a0e0ae 100644
--- a/include/asm-arm/arch-cl7500/keyboard.h
+++ b/include/asm-arm/arch-cl7500/keyboard.h
@@ -6,6 +6,7 @@
  *
  * Copyright (C) 1998-2001 Russell King
  */
+#include <asm/irq.h>
 #define NR_SCANCODES 128
 
 extern int ps2kbd_init_hw(void);
diff --git a/include/asm-arm/arch-cl7500/time.h b/include/asm-arm/arch-cl7500/time.h
index 107763e9c6bd..a63ea1e75dc4 100644
--- a/include/asm-arm/arch-cl7500/time.h
+++ b/include/asm-arm/arch-cl7500/time.h
@@ -9,6 +9,8 @@
  *  04-Dec-1997	RMK	Updated for new arch/arm/time.c
  */
 
+extern void ioctime_init(void);
+
 static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
 	do_timer(regs);
@@ -29,9 +31,8 @@ static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 /*
  * Set up timer interrupt.
  */
-static inline void setup_timer(void)
+void __init time_init(void)
 {
-	extern void ioctime_init(void);
 	ioctime_init();
 
 	timer_irq.handler = timer_interrupt;
diff --git a/include/asm-arm/arch-clps711x/autcpu12.h b/include/asm-arm/arch-clps711x/autcpu12.h
new file mode 100644
index 000000000000..1588a365f610
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/autcpu12.h
@@ -0,0 +1,78 @@
+/*
+ * AUTCPU12 specific defines
+ *
+ * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_AUTCPU12_H
+#define __ASM_ARCH_AUTCPU12_H
+
+/*
+ * The CS8900A ethernet chip has its I/O registers wired to chip select 2
+ * (nCS2). This is the mapping for it.
+ */
+#define AUTCPU12_PHYS_CS8900A		CS2_PHYS_BASE		/* physical */
+#define AUTCPU12_VIRT_CS8900A		(0xfe000000)		/* virtual */
+
+/*
+ * The flash bank is wired to chip select 0
+ */
+#define AUTCPU12_PHYS_FLASH		CS0_PHYS_BASE		/* physical */
+
+/* offset for device specific information structure */
+#define AUTCPU12_LCDINFO_OFFS		(0x00010000)	
+/*
+* Videomemory is the internal SRAM (CS 6)	
+*/
+#define AUTCPU12_PHYS_VIDEO		CS6_PHYS_BASE
+#define AUTCPU12_VIRT_VIDEO		(0xfd000000)
+
+/*
+* All special IO's are tied to CS1
+*/
+#define AUTCPU12_PHYS_CHAR_LCD         	CS1_PHYS_BASE +0x00000000  /* physical */
+
+#define AUTCPU12_PHYS_NVRAM            	CS1_PHYS_BASE +0x02000000  /* physical */
+
+#define AUTCPU12_PHYS_CSAUX1           	CS1_PHYS_BASE +0x04000000  /* physical */
+
+#define AUTCPU12_PHYS_SMC              	CS1_PHYS_BASE +0x06000000  /* physical */
+
+#define AUTCPU12_PHYS_CAN              	CS1_PHYS_BASE +0x08000000  /* physical */
+
+#define AUTCPU12_PHYS_TOUCH            	CS1_PHYS_BASE +0x0A000000  /* physical */
+
+#define AUTCPU12_PHYS_IO               	CS1_PHYS_BASE +0x0C000000  /* physical */
+
+#define AUTCPU12_PHYS_LPT              	CS1_PHYS_BASE +0x0E000000  /* physical */
+
+/* 
+* defines for smartmedia card access 
+*/
+#define AUTCPU12_SMC_RDY		(1<<2)
+#define AUTCPU12_SMC_ALE		(1<<3)
+#define AUTCPU12_SMC_CLE  		(1<<4)
+#define AUTCPU12_SMC_PORT_OFFSET	PBDR
+#define AUTCPU12_SMC_SELECT_OFFSET 	0x10
+/*
+* defines for lcd contrast 
+*/
+#define AUTCPU12_DPOT_PORT_OFFSET	PEDR
+#define	AUTCPU12_DPOT_CS		(1<<0)
+#define AUTCPU12_DPOT_CLK    		(1<<1)
+#define	AUTCPU12_DPOT_UD		(1<<2)
+
+#endif
diff --git a/include/asm-arm/arch-clps711x/dma.h b/include/asm-arm/arch-clps711x/dma.h
new file mode 100644
index 000000000000..3c4c5c843252
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/dma.h
@@ -0,0 +1,28 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/dma.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS		0xffffffff
+
+#define MAX_DMA_CHANNELS	0
+
+#endif /* _ASM_ARCH_DMA_H */
+
diff --git a/include/asm-arm/arch-clps711x/hardware.h b/include/asm-arm/arch-clps711x/hardware.h
new file mode 100644
index 000000000000..3140431421ec
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/hardware.h
@@ -0,0 +1,179 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/hardware.h
+ *
+ *  This file contains the hardware definitions of the Prospector P720T.
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/config.h>
+
+#define CLPS7111_VIRT_BASE	0xff000000
+#define CLPS7111_BASE		CLPS7111_VIRT_BASE
+
+/*
+ * The physical addresses that the external chip select signals map to is
+ * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
+ * processors.  CONFIG_EP72XX_BOOT_ROM is only available if these
+ * processors are in use.
+ */
+#ifndef CONFIG_EP72XX_ROM_BOOT
+#define CS0_PHYS_BASE		(0x00000000)
+#define CS1_PHYS_BASE		(0x10000000)
+#define CS2_PHYS_BASE		(0x20000000)
+#define CS3_PHYS_BASE		(0x30000000)
+#define CS4_PHYS_BASE		(0x40000000)
+#define CS5_PHYS_BASE		(0x50000000)
+#define CS6_PHYS_BASE		(0x60000000)
+#define CS7_PHYS_BASE		(0x70000000)
+#else
+#define CS0_PHYS_BASE		(0x70000000)
+#define CS1_PHYS_BASE		(0x60000000)
+#define CS2_PHYS_BASE		(0x50000000)
+#define CS3_PHYS_BASE		(0x40000000)
+#define CS4_PHYS_BASE		(0x30000000)
+#define CS5_PHYS_BASE		(0x20000000)
+#define CS6_PHYS_BASE		(0x10000000)
+#define CS7_PHYS_BASE		(0x00000000)
+#endif
+
+#if defined (CONFIG_ARCH_EP7211)
+
+#define EP7211_VIRT_BASE	CLPS7111_VIRT_BASE
+#define EP7211_BASE		CLPS7111_VIRT_BASE
+#include <asm/hardware/ep7211.h>
+
+#elif defined (CONFIG_ARCH_EP7212)
+
+#define EP7212_VIRT_BASE	CLPS7111_VIRT_BASE
+#define EP7212_BASE		CLPS7111_VIRT_BASE
+#include <asm/hardware/ep7212.h>
+
+
+#endif
+
+#define SYSPLD_VIRT_BASE	0xfe000000
+#define SYSPLD_BASE		SYSPLD_VIRT_BASE
+
+#ifndef __ASSEMBLER__
+
+#define PCIO_BASE		IO_BASE
+
+#endif
+
+
+#if  defined (CONFIG_ARCH_AUTCPU12)
+
+#define  CS89712_VIRT_BASE	CLPS7111_VIRT_BASE
+#define  CS89712_BASE		CLPS7111_VIRT_BASE
+
+#include <asm/hardware/clps7111.h>
+#include <asm/hardware/ep7212.h>
+#include <asm/hardware/cs89712.h>
+
+#endif
+
+
+#if defined (CONFIG_ARCH_CDB89712)
+
+#include <asm/hardware/clps7111.h>
+#include <asm/hardware/ep7212.h>
+#include <asm/hardware/cs89712.h>
+
+/* dynamic ioremap() areas */
+#define FLASH_START      0x00000000
+#define FLASH_SIZE       0x800000
+#define FLASH_WIDTH      4
+
+#define SRAM_START       0x60000000
+#define SRAM_SIZE        0xc000
+#define SRAM_WIDTH       4
+
+#define BOOTROM_START    0x70000000
+#define BOOTROM_SIZE     0x80
+#define BOOTROM_WIDTH    4
+
+
+/* static cdb89712_map_io() areas */
+#define REGISTER_START   0x80000000
+#define REGISTER_SIZE    0x4000
+#define REGISTER_BASE    0xff000000
+
+#define ETHER_START      0x20000000
+#define ETHER_SIZE       0x1000
+#define ETHER_BASE       0xfe000000
+
+#endif
+
+
+#if defined (CONFIG_ARCH_EDB7211)
+
+/*
+ * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) 
+ * and repeat across it. This is the mapping for it.
+ *
+ * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This 
+ * was cause for much consternation and headscratching. This should probably
+ * be made a compile/run time kernel option.
+ */
+#define EP7211_PHYS_EXTKBD		CS3_PHYS_BASE	/* physical */
+
+#define EP7211_VIRT_EXTKBD		(0xfd000000)	/* virtual */
+
+
+/*
+ * The CS8900A ethernet chip has its I/O registers wired to chip select 2 
+ * (nCS2). This is the mapping for it.
+ *
+ * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This 
+ * was cause for much consternation and headscratching. This should probably
+ * be made a compile/run time kernel option.
+ */
+#define EP7211_PHYS_CS8900A		CS2_PHYS_BASE	/* physical */
+
+#define EP7211_VIRT_CS8900A		(0xfc000000)	/* virtual */
+
+
+/*
+ * The two flash banks are wired to chip selects 0 and 1. This is the mapping
+ * for them.
+ *
+ * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
+ * in jumpered boot mode.
+ */
+#define EP7211_PHYS_FLASH1		CS0_PHYS_BASE	/* physical */
+#define EP7211_PHYS_FLASH2		CS1_PHYS_BASE	/* physical */
+
+#define EP7211_VIRT_FLASH1		(0xfa000000)	/* virtual */
+#define EP7211_VIRT_FLASH2		(0xfb000000)	/* virtual */
+
+#endif /* CONFIG_ARCH_EDB7211 */
+
+
+/*
+ * Relevant bits in port D, which controls power to the various parts of
+ * the LCD on the EDB7211.
+ */
+#define EDB_PD1_LCD_DC_DC_EN	(1<<1)
+#define EDB_PD2_LCDEN		(1<<2)
+#define EDB_PD3_LCDBL		(1<<3)
+
+
+#endif
+
diff --git a/include/asm-arm/arch-clps711x/io.h b/include/asm-arm/arch-clps711x/io.h
new file mode 100644
index 000000000000..fa205d49feb8
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/io.h
@@ -0,0 +1,37 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/io.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)			((a))
+#define __mem_pci(a)		((unsigned long)(a))
+#define __mem_isa(a)		((unsigned long)(a))
+
+/*
+ * We don't support ins[lb]/outs[lb].  Make them fault.
+ */
+#define __raw_readsb(p,d,l)	do { *(int *)0 = 0; } while (0)
+#define __raw_readsl(p,d,l)	do { *(int *)0 = 0; } while (0)
+#define __raw_writesb(p,d,l)	do { *(int *)0 = 0; } while (0)
+#define __raw_writesl(p,d,l)	do { *(int *)0 = 0; } while (0)
+
+#endif
diff --git a/include/asm-arm/arch-clps711x/irq.h b/include/asm-arm/arch-clps711x/irq.h
new file mode 100644
index 000000000000..7dde5e3f7096
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/irq.h
@@ -0,0 +1,20 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/irq.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define fixup_irq(i)	(i)
diff --git a/include/asm-arm/arch-clps711x/irqs.h b/include/asm-arm/arch-clps711x/irqs.h
new file mode 100644
index 000000000000..76025dc87637
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/irqs.h
@@ -0,0 +1,53 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/irqs.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Interrupts from INTSR1
+ */
+#define IRQ_CSINT			4
+#define IRQ_EINT1			5
+#define IRQ_EINT2			6
+#define IRQ_EINT3			7
+#define IRQ_TC1OI			8
+#define IRQ_TC2OI			9
+#define IRQ_RTCMI			10
+#define IRQ_TINT			11
+#define IRQ_UTXINT1			12
+#define IRQ_URXINT1			13
+#define IRQ_UMSINT			14
+#define IRQ_SSEOTI			15
+
+#define INT1_IRQS			(0x0000fff0)
+#define INT1_ACK_IRQS			(0x00004f10)
+
+/*
+ * Interrupts from INTSR2
+ */
+#define IRQ_KBDINT			(16+0)	/* bit 0 */
+#define IRQ_SS2RX			(16+1)	/* bit 1 */
+#define IRQ_SS2TX			(16+2)	/* bit 2 */
+#define IRQ_UTXINT2			(16+12)	/* bit 12 */
+#define IRQ_URXINT2			(16+13)	/* bit 13 */
+
+#define INT2_IRQS			(0x30070000)
+#define INT2_ACK_IRQS			(0x00010000)
+
+#define NR_IRQS                         30
+
diff --git a/include/asm-arm/arch-clps711x/keyboard.h b/include/asm-arm/arch-clps711x/keyboard.h
new file mode 100644
index 000000000000..30ab2199f714
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/keyboard.h
@@ -0,0 +1,26 @@
+/*
+ * linux/include/asm-arm/arch-clps711x/keyboard.h
+ *
+ * Copyright (C) 1998-2001 Russell King
+ */
+#include <asm/mach-types.h>
+
+#define NR_SCANCODES 128
+
+#define kbd_disable_irq()	do { } while (0)
+#define kbd_enable_irq()	do { } while (0)
+
+/*
+ * EDB7211 keyboard driver
+ */
+extern void edb7211_kbd_init_hw(void);
+extern void clps711x_kbd_init_hw(void);
+
+static inline void kbd_init_hw(void)
+{
+	if (machine_is_edb7211())
+		edb7211_kbd_init_hw();
+
+	if (machine_is_autcpu12())
+		clps711x_kbd_init_hw();
+}
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
new file mode 100644
index 000000000000..043ee9a9baec
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -0,0 +1,204 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/mmu.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE	(0xc0000000UL)
+#define TASK_SIZE_26	(0x04000000UL)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
+
+/*
+ * Page offset: 3GB
+ */
+#define PAGE_OFFSET	(0xc0000000UL)
+#define PHYS_OFFSET	(0xc0000000UL)
+
+/*
+ * On integrator, the dram is contiguous
+ */
+#define __virt_to_phys__is_a_macro
+#define __virt_to_phys(vpage) ((vpage) - PAGE_OFFSET + PHYS_OFFSET)
+#define __phys_to_virt__is_a_macro
+#define __phys_to_virt(ppage) ((ppage) + PAGE_OFFSET - PHYS_OFFSET)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+
+#if defined(CONFIG_ARCH_CDB89712)
+
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x)	(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x)	(x)
+
+#elif defined (CONFIG_ARCH_AUTCPU12)
+
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x)	(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x)	(x)
+
+#else
+
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x)	((x) - PAGE_OFFSET)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x)	((x) + PAGE_OFFSET)
+
+#endif
+
+
+/*
+ * Like the SA1100, the EDB7211 has a large gap between physical RAM
+ * banks.  In 2.2, the Psion (CL-PS7110) port added custom support for
+ * discontiguous physical memory.  In 2.4, we can use the standard
+ * Linux NUMA support.
+ *
+ * This is not necessary for EP7211 implementations with only one used
+ * memory bank.  For those systems, simply undefine CONFIG_DISCONTIGMEM.
+ */
+
+#ifdef CONFIG_ARCH_EDB7211
+
+#ifdef CONFIG_DISCONTIGMEM
+/*
+ * Because of the wide memory address space between physical RAM banks on the 
+ * SA1100, it's much more convenient to use Linux's NUMA support to implement
+ * our memory map representation.  Assuming all memory nodes have equal access 
+ * characteristics, we then have generic discontigous memory support.
+ *
+ * Of course, all this isn't mandatory for SA1100 implementations with only
+ * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
+ *
+ * The nodes are matched with the physical memory bank addresses which are 
+ * incidentally the same as virtual addresses.
+ * 
+ * 	node 0:  0xc0000000 - 0xc7ffffff
+ * 	node 1:  0xc8000000 - 0xcfffffff
+ * 	node 2:  0xd0000000 - 0xd7ffffff
+ * 	node 3:  0xd8000000 - 0xdfffffff
+ */
+
+#define NR_NODES	4
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) \
+		(((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
+
+/*
+ * Given a physical address, convert it to a node id.
+ */
+#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr))
+
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr) \
+			NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
+
+/*
+ * Given a kaddr, LOCAL_MAR_NR finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+#define LOCAL_MAP_NR(kaddr) \
+	(((unsigned long)(kaddr)-LOCAL_BASE_ADDR((kaddr))) >> PAGE_SHIFT)
+
+/*
+ * Given a kaddr, virt_to_page returns a pointer to the corresponding 
+ * mem_map entry.
+ */
+#define virt_to_page(kaddr) \
+	(ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
+
+/*
+ * VALID_PAGE returns a non-zero value if given page pointer is valid.
+ * This assumes all node's mem_maps are stored within the node they refer to.
+ */
+#define VALID_PAGE(page) \
+({ unsigned int node = KVADDR_TO_NID(page); \
+   ( (node < NR_NODES) && \
+     ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \
+})
+
+/*
+ * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
+ * uses only one of the two banks (bank #1).  However, even within
+ * bank #1, memory is discontiguous.
+ *
+ * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
+ * them, so we use 24 for the node max shift to get 16MB node sizes.
+ */
+#define NODE_MAX_MEM_SHIFT	24
+#define NODE_MAX_MEM_SIZE	(1<<NODE_MAX_MEM_SHIFT)
+
+/*
+ * Given a mem_map_t, LOCAL_MAP_BASE finds the owning node for the
+ * physical page and returns the kaddr for the mem_map of that node.
+ */
+#define LOCAL_MAP_BASE(page) \
+			NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(page)))
+
+/*
+ * Given a kaddr, LOCAL_BASE_ADDR finds the owning node of the memory
+ * and returns the kaddr corresponding to first physical page in the
+ * node's mem_map.
+ */
+#define LOCAL_BASE_ADDR(kaddr)	((unsigned long)(kaddr) & ~(NODE_MAX_MEM_SIZE-1))
+
+/* 
+ * With discontigmem, the conceptual mem_map array starts from PAGE_OFFSET.
+ * Given a kaddr, MAP_NR returns the appropriate global mem_map index so 
+ * it matches the corresponding node's local mem_map.
+ */
+#define MAP_NR(kaddr)	(LOCAL_MAP_NR((kaddr)) + \
+		(((unsigned long)ADDR_TO_MAPBASE((kaddr)) - PAGE_OFFSET) / \
+		sizeof(mem_map_t)))
+
+#else
+
+#define PHYS_TO_NID(addr)	(0)
+
+#endif /* CONFIG_DISCONTIGMEM */
+
+#endif	/* CONFIG_ARCH_EDB7211 */
+
+#ifndef PHYS_TO_NID
+#define PHYS_TO_NID(addr)	(0)
+#endif
+
+#endif
+
diff --git a/include/asm-arm/arch-clps711x/param.h b/include/asm-arm/arch-clps711x/param.h
new file mode 100644
index 000000000000..c46e69ad6071
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/param.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/param.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define HZ 100
diff --git a/include/asm-arm/arch-clps711x/syspld.h b/include/asm-arm/arch-clps711x/syspld.h
new file mode 100644
index 000000000000..960578a22a8e
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/syspld.h
@@ -0,0 +1,121 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/syspld.h
+ *
+ *  System Control PLD register definitions.
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSPLD_H
+#define __ASM_ARCH_SYSPLD_H
+
+#define SYSPLD_PHYS_BASE	(0x10000000)
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+#define SYSPLD_REG(type,off)	(*(volatile type *)(SYSPLD_BASE + off))
+#else
+#define SYSPLD_REG(type,off)	(off)
+#endif
+
+#define PLD_INT		SYSPLD_REG(u32, 0x000000)
+#define PLD_INT_PENIRQ		(1 << 5)
+#define PLD_INT_UCB_IRQ		(1 << 1)
+#define PLD_INT_KBD_ATN		(1 << 0)	/* EINT1 */
+
+#define PLD_PWR		SYSPLD_REG(u32, 0x000004)
+#define PLD_PWR_EXT		(1 << 5)
+#define PLD_PWR_MODE		(1 << 4)	/* 1 = PWM, 0 = PFM */
+#define PLD_S4_ON		(1 << 3)	/* LCD bias voltage enable */
+#define PLD_S3_ON		(1 << 2)	/* LCD backlight enable */
+#define PLD_S2_ON		(1 << 1)	/* LCD 3V3 supply enable */
+#define PLD_S1_ON		(1 << 0)	/* LCD 3V supply enable */
+
+#define PLD_KBD		SYSPLD_REG(u32, 0x000008)
+#define PLD_KBD_WAKE		(1 << 1)
+#define PLD_KBD_EN		(1 << 0)
+
+#define PLD_SPI		SYSPLD_REG(u32, 0x00000c)
+#define PLD_SPI_EN		(1 << 0)
+
+#define PLD_IO		SYSPLD_REG(u32, 0x000010)
+#define PLD_IO_BOOTSEL		(1 << 6)	/* boot sel switch */
+#define PLD_IO_USER		(1 << 5)	/* user defined switch */
+#define PLD_IO_LED3		(1 << 4)
+#define PLD_IO_LED2		(1 << 3)
+#define PLD_IO_LED1		(1 << 2)
+#define PLD_IO_LED0		(1 << 1)
+#define PLD_IO_LEDEN		(1 << 0)
+
+#define PLD_IRDA	SYSPLD_REG(u32, 0x000014)
+#define PLD_IRDA_EN		(1 << 0)
+
+#define PLD_COM2	SYSPLD_REG(u32, 0x000018)
+#define PLD_COM2_EN		(1 << 0)
+
+#define PLD_COM1	SYSPLD_REG(u32, 0x00001c)
+#define PLD_COM1_EN		(1 << 0)
+
+#define PLD_AUD		SYSPLD_REG(u32, 0x000020)
+#define PLD_AUD_DIV1		(1 << 6)
+#define PLD_AUD_DIV0		(1 << 5)
+#define PLD_AUD_CLK_SEL1	(1 << 4)
+#define PLD_AUD_CLK_SEL0	(1 << 3)
+#define PLD_AUD_MIC_PWR		(1 << 2)
+#define PLD_AUD_MIC_GAIN	(1 << 1)
+#define PLD_AUD_CODEC_EN	(1 << 0)
+
+#define PLD_CF		SYSPLD_REG(u32, 0x000024)
+#define PLD_CF2_SLEEP		(1 << 5)
+#define PLD_CF1_SLEEP		(1 << 4)
+#define PLD_CF2_nPDREQ		(1 << 3)
+#define PLD_CF1_nPDREQ		(1 << 2)
+#define PLD_CF2_nIRQ		(1 << 1)
+#define PLD_CF1_nIRQ		(1 << 0)
+
+#define PLD_SDC		SYSPLD_REG(u32, 0x000028)
+#define PLD_SDC_INT_EN		(1 << 2)
+#define PLD_SDC_WP		(1 << 1)
+#define PLD_SDC_CD		(1 << 0)
+
+#define PLD_FPGA	SYSPLD_REG(u32, 0x00002c)
+
+#define PLD_CODEC	SYSPLD_REG(u32, 0x400000)
+#define PLD_CODEC_IRQ3		(1 << 4)
+#define PLD_CODEC_IRQ2		(1 << 3)
+#define PLD_CODEC_IRQ1		(1 << 2)
+#define PLD_CODEC_EN		(1 << 0)
+
+#define PLD_BRITE	SYSPLD_REG(u32, 0x400004)
+#define PLD_BRITE_UP		(1 << 1)
+#define PLD_BRITE_DN		(1 << 0)
+
+#define PLD_LCDEN	SYSPLD_REG(u32, 0x400008)
+#define PLD_LCDEN_EN		(1 << 0)
+
+#define PLD_ID		SYSPLD_REG(u32, 0x40000c)
+
+#define PLD_TCH		SYSPLD_REG(u32, 0x400010)
+#define PLD_TCH_PENIRQ		(1 << 1)
+#define PLD_TCH_EN		(1 << 0)
+
+#define PLD_GPIO	SYSPLD_REG(u32, 0x400014)
+#define PLD_GPIO2		(1 << 2)
+#define PLD_GPIO1		(1 << 1)
+#define PLD_GPIO0		(1 << 0)
+
+#endif
diff --git a/include/asm-arm/arch-clps711x/system.h b/include/asm-arm/arch-clps711x/system.h
new file mode 100644
index 000000000000..6255973ebb84
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/system.h
@@ -0,0 +1,38 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/system.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/hardware/clps7111.h>
+
+static void arch_idle(void)
+{
+	clps_writel(1, HALT);
+	__asm__ __volatile__(
+	"mov	r0, r0
+	mov	r0, r0");
+}
+
+static inline void arch_reset(char mode)
+{
+	cpu_reset(0);
+}
+
+#endif
diff --git a/include/asm-arm/arch-clps711x/time.h b/include/asm-arm/arch-clps711x/time.h
new file mode 100644
index 000000000000..d6040c294439
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/time.h
@@ -0,0 +1,43 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/time.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <asm/leds.h>
+#include <asm/hardware/clps7111.h>
+
+extern void clps711x_setup_timer(void);
+
+/*
+ * IRQ handler for the timer
+ */
+static void p720t_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	do_leds();
+	do_timer(regs);
+	do_profile(regs);
+}
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+void __init time_init(void)
+{
+	clps711x_setup_timer();
+	timer_irq.handler = p720t_timer_interrupt;
+	setup_arm_irq(IRQ_TC2OI, &timer_irq);
+}
diff --git a/include/asm-arm/arch-clps711x/timex.h b/include/asm-arm/arch-clps711x/timex.h
new file mode 100644
index 000000000000..dcbb381da3dd
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/timex.h
@@ -0,0 +1,23 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/timex.h
+ *
+ *  Prospector 720T architecture timex specifications
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE 512000
diff --git a/include/asm-arm/arch-clps711x/uncompress.h b/include/asm-arm/arch-clps711x/uncompress.h
new file mode 100644
index 000000000000..152fef0ee4ed
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/uncompress.h
@@ -0,0 +1,67 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/uncompress.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/config.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/hardware/clps7111.h>
+
+#undef CLPS7111_BASE
+#define CLPS7111_BASE CLPS7111_PHYS_BASE
+
+#define barrier()		__asm__ __volatile__("": : :"memory")
+#define __raw_readl(p)		(*(unsigned long *)(p))
+#define __raw_writel(v,p)	(*(unsigned long *)(p) = (v))
+
+#ifdef CONFIG_DEBUG_CLPS711X_UART2
+#define SYSFLGx	SYSFLG2
+#define UARTDRx	UARTDR2
+#else
+#define SYSFLGx	SYSFLG1
+#define UARTDRx	UARTDR1
+#endif
+
+/*
+ * This does not append a newline
+ */
+static void puts(const char *s)
+{
+	char c;
+
+	while ((c = *s++) != '\0') {
+		while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
+			barrier();
+		clps_writel(c, UARTDRx);
+
+		if (c == '\n') {
+			while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
+				barrier();
+			clps_writel('\r', UARTDRx);
+		}
+	}
+	while (clps_readl(SYSFLGx) & SYSFLG_UBUSY)
+		barrier();
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-clps711x/vmalloc.h b/include/asm-arm/arch-clps711x/vmalloc.h
new file mode 100644
index 000000000000..5d8324ac39b7
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/vmalloc.h
@@ -0,0 +1,32 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/vmalloc.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET	  (8*1024*1024)
+#define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-ebsa110/io.h b/include/asm-arm/arch-ebsa110/io.h
index cf83e8bc7c72..ff7221d68205 100644
--- a/include/asm-arm/arch-ebsa110/io.h
+++ b/include/asm-arm/arch-ebsa110/io.h
@@ -15,12 +15,6 @@
 
 #define IO_SPACE_LIMIT 0xffff
 
-/*
- * Generic virtual read/write
- */
-#define __arch_getw(a)		(*(volatile unsigned short *)(a))
-#define __arch_putw(v,a)	(*(volatile unsigned short *)(a) = (v))
-
 u8  __inb(int port);
 u16 __inw(int port);
 u32 __inl(int port);
@@ -53,7 +47,7 @@ void __writel(u32 val, void *addr);
 #define writew(v,b)		__writew(v,b)
 #define writel(v,b)		__writel(v,b)
 
-#define __arch_ioremap(off,sz,c)	((void *)(off))
-#define __arch_iounmap(virt)		do { } while (0)
+#define __arch_ioremap(cookie,sz,c)	((void *)(cookie))
+#define __arch_iounmap(cookie)		do { } while (0)
 
 #endif
diff --git a/include/asm-arm/arch-ebsa110/time.h b/include/asm-arm/arch-ebsa110/time.h
index 53b354720e55..b1bab596e9dc 100644
--- a/include/asm-arm/arch-ebsa110/time.h
+++ b/include/asm-arm/arch-ebsa110/time.h
@@ -33,7 +33,7 @@ static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 /*
  * Set up timer interrupt.
  */
-static inline void setup_timer(void)
+void __init time_init(void)
 {
 	ebsa110_setup_timer();
 
diff --git a/include/asm-arm/arch-ebsa110/vmalloc.h b/include/asm-arm/arch-ebsa110/vmalloc.h
index 78c71c2db213..da319920a2ad 100644
--- a/include/asm-arm/arch-ebsa110/vmalloc.h
+++ b/include/asm-arm/arch-ebsa110/vmalloc.h
@@ -19,4 +19,4 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
-#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+#define VMALLOC_END       (PAGE_OFFSET + 0x1f000000)
diff --git a/include/asm-arm/arch-ebsa285/io.h b/include/asm-arm/arch-ebsa285/io.h
index a0591a8c562b..aac50402bc1b 100644
--- a/include/asm-arm/arch-ebsa285/io.h
+++ b/include/asm-arm/arch-ebsa285/io.h
@@ -42,13 +42,4 @@ static inline unsigned long ___mem_isa(unsigned long a)
 #define __mem_isa(a)		___mem_isa((unsigned long)(a))
 #endif
 
-/*
- * Generic virtual read/write
- */
-#define __arch_getw(a)		(*(volatile unsigned short *)(a))
-#define __arch_putw(v,a)	(*(volatile unsigned short *)(a) = (v))
-
-#define iomem_valid_addr(iomem,sz)	(1)
-#define iomem_to_phys(iomem)		(iomem)
-
 #endif
diff --git a/include/asm-arm/arch-ebsa285/time.h b/include/asm-arm/arch-ebsa285/time.h
index e70657d67aa3..111bf6e306d8 100644
--- a/include/asm-arm/arch-ebsa285/time.h
+++ b/include/asm-arm/arch-ebsa285/time.h
@@ -199,7 +199,7 @@ static void timer1_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 /*
  * Set up timer interrupt.
  */
-static inline void setup_timer(void)
+void __init time_init(void)
 {
 	int irq;
 
diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h
index 823c6d79401c..c66b7fa88da8 100644
--- a/include/asm-arm/arch-ebsa285/vmalloc.h
+++ b/include/asm-arm/arch-ebsa285/vmalloc.h
@@ -6,6 +6,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/config.h>
+
 /*
  * Just any arbitrary offset to the start of the vmalloc VM area: the
  * current 8MB value just means that there will be a 8MB "hole" after the
@@ -17,4 +19,9 @@
 #define VMALLOC_OFFSET	  (8*1024*1024)
 #define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
+
+#ifdef CONFIG_ARCH_FOOTBRIDGE
+#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
+#else
 #define VMALLOC_END       (PAGE_OFFSET + 0x20000000)
+#endif
diff --git a/include/asm-arm/arch-epxa10db/ether00.h b/include/asm-arm/arch-epxa10db/ether00.h
new file mode 100644
index 000000000000..29a458320094
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/ether00.h
@@ -0,0 +1,482 @@
+#ifndef __ETHER00_H
+#define __ETHER00_H
+
+
+
+/*
+ * Register definitions for the Ethernet MAC
+ */
+
+/*
+ * Copyright (c) Altera Corporation 2000.
+ * All rights reserved.
+ */
+
+/*
+*	Structures for the DMA controller
+*/
+typedef struct fda_desc
+	{
+	struct fda_desc *	FDNext;
+	long				FDSystem;
+	long				FDStat;
+	short				FDLength;
+	short				FDCtl;
+	}FDA_DESC;
+
+typedef struct buf_desc
+	{
+	char *	BuffData;
+	short	BuffLength;
+	char	BDStat;
+	char	BDCtl;
+	}BUF_DESC;
+
+/*
+*	Control masks for the DMA controller
+*/
+#define FDCTL_BDCOUNT_MSK						(0x1F)
+#define FDCTL_BDCOUNT_OFST						(0)
+#define FDCTL_FRMOPT_MSK						(0x7C00)
+#define FDCTL_FRMOPT_OFST						(10)
+#define	FDCTL_COWNSFD_MSK						(0x8000)
+#define	FDCTL_COWNSFD_OFST						(15)
+
+#define BDCTL_RXBDSEQN_MSK						(0x7F)
+#define BDCTL_RXBDSEQN_OFST						(0)
+#define	BDCTL_COWNSBD_MSK						(0x80)
+#define	BDCTL_COWNSBD_OFST						(7)
+
+#define FDNEXT_EOL_MSK							(0x1)
+#define FDNEXT_EOL_OFST							(0)
+#define FDNEXT_EOL_POINTER_MSK					(0xFFFFFFF0)
+#define FDNEXT_EOL_POINTER_OFST					(4)
+
+#define ETHER_ARC_SIZE         (21)
+
+/*
+*	Regsiter definitions and masks
+*/
+#define ETHER_DMA_CTL(base)							(ETHER00_TYPE (base + 0x100))
+#define ETHER_DMA_CTL_DMBURST_OFST				(2)
+#define ETHER_DMA_CTL_DMBURST_MSK				(0x1FC)
+#define ETHER_DMA_CTL_POWRMGMNT_OFST			(11)
+#define ETHER_DMA_CTL_POWRMGMNT_MSK				(0x1000)
+#define ETHER_DMA_CTL_TXBIGE_OFST				(14)
+#define ETHER_DMA_CTL_TXBIGE_MSK				(0x4000)
+#define ETHER_DMA_CTL_RXBIGE_OFST				(15)
+#define ETHER_DMA_CTL_RXBIGE_MSK				(0x8000)
+#define ETHER_DMA_CTL_TXWAKEUP_OFST				(16)
+#define ETHER_DMA_CTL_TXWAKEUP_MSK				(0x10000)
+#define ETHER_DMA_CTL_SWINTREQ_OFST				(17)
+#define ETHER_DMA_CTL_SWINTREQ_MSK				(0x20000)
+#define ETHER_DMA_CTL_INTMASK_OFST				(18)
+#define ETHER_DMA_CTL_INTMASK_MSK				(0x40000)
+#define ETHER_DMA_CTL_M66ENSTAT_OFST			(19)
+#define ETHER_DMA_CTL_M66ENSTAT_MSK				(0x80000)
+#define ETHER_DMA_CTL_RMTXINIT_OFST				(20)
+#define ETHER_DMA_CTL_RMTXINIT_MSK				(0x100000)
+#define ETHER_DMA_CTL_RMRXINIT_OFST				(21)
+#define ETHER_DMA_CTL_RMRXINIT_MSK				(0x200000)
+#define ETHER_DMA_CTL_RXALIGN_OFST				(22)
+#define ETHER_DMA_CTL_RXALIGN_MSK				(0xC00000)
+#define ETHER_DMA_CTL_RMSWRQ_OFST				(24)
+#define ETHER_DMA_CTL_RMSWRQ_MSK				(0x1000000)
+#define ETHER_DMA_CTL_RMEMBANK_OFST				(25)
+#define ETHER_DMA_CTL_RMEMBANK_MSK				(0x2000000)
+
+#define ETHER_TXFRMPTR(base)							(ETHER00_TYPE (base + 0x104))
+
+#define ETHER_TXTHRSH(base)							(ETHER00_TYPE (base + 0x308))
+
+#define ETHER_TXPOLLCTR(base)							(ETHER00_TYPE (base + 0x30c))
+
+#define	ETHER_BLFRMPTR(base)							(ETHER00_TYPE (base + 0x110))
+#define ETHER_BLFFRMPTR_EOL_OFST				(0)
+#define ETHER_BLFFRMPTR_EOL_MSK					(0x1)
+#define ETHER_BLFFRMPTR_ADDRESS_OFST			(4)
+#define ETHER_BLFFRMPTR_ADDRESS_MSK				(0xFFFFFFF0)
+
+#define ETHER_RXFRAGSIZE(base)						(ETHER00_TYPE (base + 0x114))
+#define	ETHER_RXFRAGSIZE_MINFRAG_OFST			(2)
+#define	ETHER_RXFRAGSIZE_MINFRAG_MSK			(0xFFC)
+#define	ETHER_RXFRAGSIZE_ENPACK_OFST			(15)
+#define	ETHER_RXFRAGSIZE_ENPACK_MSK				(0x8000)
+
+#define ETHER_INT_EN(base)							(ETHER00_TYPE (base + 0x118))
+#define ETHER_INT_EN_FDAEXEN_OFST				(0)
+#define ETHER_INT_EN_FDAEXEN_MSK				(0x1)
+#define ETHER_INT_EN_BLEXEN_OFST				(1)
+#define ETHER_INT_EN_BLEXN_MSK					(0x2)
+#define ETHER_INT_EN_STARGABTEN_OFST			(2)
+#define ETHER_INT_EN_STARGABTEN_MSK				(0x4)
+#define ETHER_INT_EN_RTARGABTEN_OFST			(3)
+#define ETHER_INT_EN_RTARGABTEN_MSK				(0x8)
+#define ETHER_INT_EN_RMASABTEN_OFST				(4)
+#define ETHER_INT_EN_RMASABTEN_MSK				(0x10)
+#define ETHER_INT_EN_SSYSERREN_OFST				(5)
+#define ETHER_INT_EN_SSYSERREN_MSK				(0x20)
+#define ETHER_INT_EN_DPARERREN_OFST				(6)
+#define ETHER_INT_EN_DPARERREN_MSK				(0x40)
+#define ETHER_INT_EN_EARNOTEN_OFST				(7)
+#define ETHER_INT_EN_EARNOTEN_MSK				(0x80)
+#define ETHER_INT_EN_DPARDEN_OFST				(8)
+#define ETHER_INT_EN_DPARDEN_MSK				(0x100)
+#define ETHER_INT_EN_DMPARERREN_OFST			(9)
+#define ETHER_INT_EN_DMPARERREN_MSK				(0x200)
+#define ETHER_INT_EN_TXCTLCMPEN_OFST			(10)
+#define ETHER_INT_EN_TXCTLCMPEN_MSK				(0x400)
+#define ETHER_INT_EN_NRABTEN_OFST				(11)
+#define ETHER_INT_EN_NRABTEN_MSK				(0x800)
+
+#define	ETHER_FDA_BAS(base)							(ETHER00_TYPE (base + 0x11C))
+#define ETHER_FDA_BAS_ADDRESS_OFST				(4)
+#define ETHER_FDA_BAS_ADDRESS_MSK				(0xFFFFFFF0)
+
+#define ETHER_FDA_LIM(base)							(ETHER00_TYPE (base + 0x120))
+#define ETHER_FDA_LIM_COUNT_OFST				(4)
+#define ETHER_FDA_LIM_COUNT_MSK					(0xFFF0)
+
+#define ETHER_INT_SRC(base)							(ETHER00_TYPE (base + 0x124))
+#define ETHER_INT_SRC_INTMACTX_OFST				(0)
+#define ETHER_INT_SRC_INTMACTX_MSK				(0x1)
+#define ETHER_INT_SRC_INTMACRX_OFST				(1)
+#define ETHER_INT_SRC_INTMACRX_MSK				(0x2)
+#define ETHER_INT_SRC_INTSBUS_OFST				(2)
+#define ETHER_INT_SRC_INTSBUS_MSK				(0x4)
+#define ETHER_INT_SRC_INTFDAEX_OFST				(3)
+#define ETHER_INT_SRC_INTFDAEX_MSK				(0x8)
+#define ETHER_INT_SRC_INTBLEX_OFST				(4)
+#define ETHER_INT_SRC_INTBLEX_MSK				(0x10)
+#define ETHER_INT_SRC_SWINT_OFST				(5)
+#define ETHER_INT_SRC_SWINT_MSK					(0x20)
+#define ETHER_INT_SRC_INTEARNOT_OFST			(6)
+#define ETHER_INT_SRC_INTEARNOT_MSK				(0x40)
+#define ETHER_INT_SRC_DMPARERR_OFST				(7)
+#define ETHER_INT_SRC_DMPARERR_MSK				(0x80)
+#define ETHER_INT_SRC_INTEXBD_OFST				(8)
+#define ETHER_INT_SRC_INTEXBD_MSK				(0x100)
+#define ETHER_INT_SRC_INTTXCTLCMP_OFST			(9)
+#define ETHER_INT_SRC_INTTXCTLCMP_MSK			(0x200)
+#define ETHER_INT_SRC_INTNRABT_OFST				(10)
+#define ETHER_INT_SRC_INTNRABT_MSK				(0x400)
+#define ETHER_INT_SRC_FDAEX_OFST				(11)
+#define ETHER_INT_SRC_FDAEX_MSK					(0x800)
+#define ETHER_INT_SRC_BLEX_OFST					(12)
+#define ETHER_INT_SRC_BLEX_MSK					(0x1000)
+#define ETHER_INT_SRC_DMPARERRSTAT_OFST			(13)
+#define ETHER_INT_SRC_DMPARERRSTAT_MSK			(0x2000)
+#define ETHER_INT_SRC_NRABT_OFST				(14)
+#define ETHER_INT_SRC_NRABT_MSK					(0x4000)
+#define ETHER_INT_SRC_INTLINK_OFST				(15)
+#define ETHER_INT_SRC_INTLINK_MSK				(0x8000)
+#define ETHER_INT_SRC_INTEXDEFER_OFST			(16)
+#define ETHER_INT_SRC_INTEXDEFER_MSK			(0x10000)
+#define ETHER_INT_SRC_INTRMON_OFST				(17)
+#define ETHER_INT_SRC_INTRMON_MSK				(0x20000)
+#define ETHER_INT_SRC_IRQ_MSK					(0x83FF)
+
+#define ETHER_PAUSECNT(base)							(ETHER00_TYPE (base + 0x40))
+#define ETHER_PAUSECNT_COUNT_OFST				(0)
+#define ETHER_PAUSECNT_COUNT_MSK				(0xFFFF)
+
+#define ETHER_REMPAUCNT(base)							(ETHER00_TYPE (base + 0x44))
+#define ETHER_REMPAUCNT_COUNT_OFST				(0)
+#define ETHER_REMPAUCNT_COUNT_MSK				(0xFFFF)
+
+#define ETHER_TXCONFRMSTAT(base)						(ETHER00_TYPE (base + 0x348))
+#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST	(0)
+#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK	(0x3FFFFF)
+
+#define ETHER_MAC_CTL(base)							(ETHER00_TYPE (base + 0))
+#define ETHER_MAC_CTL_HALTREQ_OFST				(0)
+#define ETHER_MAC_CTL_HALTREQ_MSK				(0x1)
+#define ETHER_MAC_CTL_HALTIMM_OFST				(1)
+#define ETHER_MAC_CTL_HALTIMM_MSK				(0x2)
+#define ETHER_MAC_CTL_RESET_OFST				(2)
+#define ETHER_MAC_CTL_RESET_MSK					(0x4)
+#define ETHER_MAC_CTL_FULLDUP_OFST				(3)
+#define ETHER_MAC_CTL_FULLDUP_MSK				(0x8)
+#define ETHER_MAC_CTL_MACLOOP_OFST				(4)
+#define ETHER_MAC_CTL_MACLOOP_MSK				(0x10)
+#define ETHER_MAC_CTL_CONN_OFST					(5)
+#define ETHER_MAC_CTL_CONN_MSK					(0x60)
+#define ETHER_MAC_CTL_LOOP10_OFST				(7)
+#define ETHER_MAC_CTL_LOOP10_MSK				(0x80)
+#define ETHER_MAC_CTL_LNKCHG_OFST				(8)
+#define ETHER_MAC_CTL_LNKCHG_MSK				(0x100)
+#define ETHER_MAC_CTL_MISSROLL_OFST				(10)
+#define ETHER_MAC_CTL_MISSROLL_MSK				(0x400)
+#define ETHER_MAC_CTL_ENMISSROLL_OFST			(13)
+#define ETHER_MAC_CTL_ENMISSROLL_MSK			(0x2000)
+#define ETHER_MAC_CTL_LINK10_OFST				(15)
+#define ETHER_MAC_CTL_LINK10_MSK				(0x8000)
+
+#define ETHER_ARC_CTL(base)							(ETHER00_TYPE (base + 0x4))
+#define	ETHER_ARC_CTL_STATIONACC_OFST			(0)
+#define	ETHER_ARC_CTL_STATIONACC_MSK			(0x1)
+#define	ETHER_ARC_CTL_GROUPACC_OFST				(1)
+#define	ETHER_ARC_CTL_GROUPACC_MSK				(0x2)
+#define	ETHER_ARC_CTL_BROADACC_OFST				(2)
+#define	ETHER_ARC_CTL_BROADACC_MSK				(0x4)
+#define	ETHER_ARC_CTL_NEGARC_OFST				(3)
+#define	ETHER_ARC_CTL_NEGARC_MSK				(0x8)
+#define	ETHER_ARC_CTL_COMPEN_OFST				(4)
+#define	ETHER_ARC_CTL_COMPEN_MSK				(0x10)
+
+#define ETHER_TX_CTL(base)							(ETHER00_TYPE (base + 0x8))
+#define ETHER_TX_CTL_TXEN_OFST					(0)
+#define ETHER_TX_CTL_TXEN_MSK					(0x1)
+#define ETHER_TX_CTL_TXHALT_OFST				(1)
+#define ETHER_TX_CTL_TXHALT_MSK					(0x2)
+#define ETHER_TX_CTL_NOPAD_OFST					(2)
+#define ETHER_TX_CTL_NOPAD_MSK					(0x4)
+#define ETHER_TX_CTL_NOCRC_OFST					(3)
+#define ETHER_TX_CTL_NOCRC_MSK					(0x8)
+#define ETHER_TX_CTL_FBACK_OFST					(4)
+#define ETHER_TX_CTL_FBACK_MSK					(0x10)
+#define ETHER_TX_CTL_NOEXDEF_OFST				(5)
+#define ETHER_TX_CTL_NOEXDEF_MSK				(0x20)
+#define ETHER_TX_CTL_SDPAUSE_OFST				(6)
+#define ETHER_TX_CTL_SDPAUSE_MSK				(0x40)
+#define ETHER_TX_CTL_MII10_OFST					(7)
+#define ETHER_TX_CTL_MII10_MSK					(0x80)
+#define ETHER_TX_CTL_ENUNDER_OFST				(8)
+#define ETHER_TX_CTL_ENUNDER_MSK				(0x100)
+#define ETHER_TX_CTL_ENEXDEFER_OFST				(9)
+#define ETHER_TX_CTL_ENEXDEFER_MSK				(0x200)
+#define ETHER_TX_CTL_ENLCARR_OFST				(10)
+#define ETHER_TX_CTL_ENLCARR_MSK				(0x400)
+#define ETHER_TX_CTL_ENEXCOLL_OFST				(11)
+#define ETHER_TX_CTL_ENEXCOLL_MSK				(0x800)
+#define ETHER_TX_CTL_ENLATECOLL_OFST				(12)
+#define ETHER_TX_CTL_ENLATECOLL_MSK				(0x1000)
+#define ETHER_TX_CTL_ENTXPAR_OFST				(13)
+#define ETHER_TX_CTL_ENTXPAR_MSK				(0x2000)
+#define ETHER_TX_CTL_ENCOMP_OFST				(14)
+#define ETHER_TX_CTL_ENCOMP_MSK					(0x4000)
+
+#define ETHER_TX_STAT(base)							(ETHER00_TYPE (base + 0xc))
+#define ETHER_TX_STAT_TXCOLL_OFST				(0)
+#define ETHER_TX_STAT_TXCOLL_MSK				(0xF)
+#define ETHER_TX_STAT_EXCOLL_OFST				(4)
+#define ETHER_TX_STAT_EXCOLL_MSK				(0x10)
+#define ETHER_TX_STAT_TXDEFER_OFST				(5)
+#define ETHER_TX_STAT_TXDEFER_MSK				(0x20)
+#define ETHER_TX_STAT_PAUSED_OFST				(6)
+#define ETHER_TX_STAT_PAUSED_MSK				(0x40)
+#define ETHER_TX_STAT_INTTX_OFST				(7)
+#define ETHER_TX_STAT_INTTX_MSK					(0x80)
+#define ETHER_TX_STAT_UNDER_OFST				(8)
+#define ETHER_TX_STAT_UNDER_MSK					(0x100)
+#define ETHER_TX_STAT_EXDEFER_OFST				(9)
+#define ETHER_TX_STAT_EXDEFER_MSK				(0x200)
+#define ETHER_TX_STAT_LCARR_OFST				(10)
+#define ETHER_TX_STAT_LCARR_MSK					(0x400)
+#define ETHER_TX_STAT_TX10STAT_OFST				(11)
+#define ETHER_TX_STAT_TX10STAT_MSK				(0x800)
+#define ETHER_TX_STAT_LATECOLL_OFST				(12)
+#define ETHER_TX_STAT_LATECOLL_MSK				(0x1000)
+#define ETHER_TX_STAT_TXPAR_OFST				(13)
+#define ETHER_TX_STAT_TXPAR_MSK					(0x2000)
+#define ETHER_TX_STAT_COMP_OFST					(14)
+#define ETHER_TX_STAT_COMP_MSK					(0x4000)
+#define ETHER_TX_STAT_TXHALTED_OFST				(15)
+#define ETHER_TX_STAT_TXHALTED_MSK				(0x8000)
+#define ETHER_TX_STAT_SQERR_OFST				(16)
+#define ETHER_TX_STAT_SQERR_MSK					(0x10000)
+#define ETHER_TX_STAT_TXMCAST_OFST				(17)
+#define ETHER_TX_STAT_TXMCAST_MSK				(0x20000)
+#define ETHER_TX_STAT_TXBCAST_OFST				(18)
+#define ETHER_TX_STAT_TXBCAST_MSK				(0x40000)
+#define ETHER_TX_STAT_VLAN_OFST					(19)
+#define ETHER_TX_STAT_VLAN_MSK					(0x80000)
+#define ETHER_TX_STAT_MACC_OFST					(20)
+#define ETHER_TX_STAT_MACC_MSK					(0x100000)
+#define ETHER_TX_STAT_TXPAUSE_OFST				(21)
+#define ETHER_TX_STAT_TXPAUSE_MSK				(0x200000)
+
+#define ETHER_RX_CTL(base)							(ETHER00_TYPE (base + 0x10))
+#define ETHER_RX_CTL_RXEN_OFST					(0)
+#define ETHER_RX_CTL_RXEN_MSK					(0x1)
+#define ETHER_RX_CTL_RXHALT_OFST				(1)
+#define ETHER_RX_CTL_RXHALT_MSK					(0x2)
+#define ETHER_RX_CTL_LONGEN_OFST				(2)
+#define ETHER_RX_CTL_LONGEN_MSK					(0x4)
+#define ETHER_RX_CTL_SHORTEN_OFST				(3)
+#define ETHER_RX_CTL_SHORTEN_MSK				(0x8)
+#define ETHER_RX_CTL_STRIPCRC_OFST				(4)
+#define ETHER_RX_CTL_STRIPCRC_MSK				(0x10)
+#define ETHER_RX_CTL_PASSCTL_OFST				(5)
+#define ETHER_RX_CTL_PASSCTL_MSK				(0x20)
+#define ETHER_RX_CTL_IGNORECRC_OFST				(6)
+#define ETHER_RX_CTL_IGNORECRC_MSK				(0x40)
+#define ETHER_RX_CTL_ENALIGN_OFST				(8)
+#define ETHER_RX_CTL_ENALIGN_MSK				(0x100)
+#define ETHER_RX_CTL_ENCRCERR_OFST				(9)
+#define ETHER_RX_CTL_ENCRCERR_MSK				(0x200)
+#define ETHER_RX_CTL_ENOVER_OFST				(10)
+#define ETHER_RX_CTL_ENOVER_MSK					(0x400)
+#define ETHER_RX_CTL_ENLONGERR_OFST				(11)
+#define ETHER_RX_CTL_ENLONGERR_MSK				(0x800)
+#define ETHER_RX_CTL_ENRXPAR_OFST				(13)
+#define ETHER_RX_CTL_ENRXPAR_MSK				(0x2000)
+#define ETHER_RX_CTL_ENGOOD_OFST				(14)
+#define ETHER_RX_CTL_ENGOOD_MSK					(0x4000)
+
+#define ETHER_RX_STAT(base)							(ETHER00_TYPE (base + 0x14))
+#define ETHER_RX_STAT_LENERR_OFST				(4)
+#define ETHER_RX_STAT_LENERR_MSK				(0x10)
+#define ETHER_RX_STAT_CTLRECD_OFST				(5)
+#define ETHER_RX_STAT_CTLRECD_MSK				(0x20)
+#define ETHER_RX_STAT_INTRX_OFST				(6)
+#define ETHER_RX_STAT_INTRX_MSK					(0x40)
+#define ETHER_RX_STAT_RX10STAT_OFST				(7)
+#define ETHER_RX_STAT_RX10STAT_MSK				(0x80)
+#define ETHER_RX_STAT_ALIGNERR_OFST				(8)
+#define ETHER_RX_STAT_ALIGNERR_MSK				(0x100)
+#define ETHER_RX_STAT_CRCERR_OFST				(9)
+#define ETHER_RX_STAT_CRCERR_MSK				(0x200)
+#define ETHER_RX_STAT_OVERFLOW_OFST				(10)
+#define ETHER_RX_STAT_OVERFLOW_MSK				(0x400)
+#define ETHER_RX_STAT_LONGERR_OFST				(11)
+#define ETHER_RX_STAT_LONGERR_MSK				(0x800)
+#define ETHER_RX_STAT_RXPAR_OFST				(13)
+#define ETHER_RX_STAT_RXPAR_MSK					(0x2000)
+#define ETHER_RX_STAT_GOOD_OFST					(14)
+#define ETHER_RX_STAT_GOOD_MSK					(0x4000)
+#define ETHER_RX_STAT_RXHALTED_OFST				(15)
+#define ETHER_RX_STAT_RXHALTED_MSK				(0x8000)
+#define ETHER_RX_STAT_RXMCAST_OFST				(17)
+#define ETHER_RX_STAT_RXMCAST_MSK				(0x10000)
+#define ETHER_RX_STAT_RXBCAST_OFST				(18)
+#define ETHER_RX_STAT_RXBCAST_MSK				(0x20000)
+#define ETHER_RX_STAT_RXVLAN_OFST				(19)
+#define ETHER_RX_STAT_RXVLAN_MSK				(0x40000)
+#define ETHER_RX_STAT_RXPAUSE_OFST				(20)
+#define ETHER_RX_STAT_RXPAUSE_MSK				(0x80000)
+#define ETHER_RX_STAT_ARCSTATUS_OFST				(21)
+#define ETHER_RX_STAT_ARCSTATUS_MSK				(0xF00000)
+#define ETHER_RX_STAT_ARCENT_OFST				(25)
+#define ETHER_RX_STAT_ARCENT_MSK				(0x1F000000)
+
+#define ETHER_MD_DATA(base)							(ETHER00_TYPE (base + 0x18))
+
+#define ETHER_MD_CA(base)								(ETHER00_TYPE (base + 0x1c))
+#define ETHER_MD_CA_ADDR_OFST					(0)
+#define ETHER_MD_CA_ADDR_MSK					(0x1F)
+#define ETHER_MD_CA_PHY_OFST					(5)
+#define ETHER_MD_CA_PHY_MSK					(0x3E0)
+#define ETHER_MD_CA_WR_OFST					(10)
+#define ETHER_MD_CA_WR_MSK					(0x400)
+#define ETHER_MD_CA_BUSY_OFST					(11)
+#define ETHER_MD_CA_BUSY_MSK					(0x800)
+#define ETHER_MD_CA_PRESUPP_OFST				(12)
+#define ETHER_MD_CA_PRESUPP_MSK					(0x1000)
+
+#define ETHER_ARC_ADR(base)	      (ETHER00_TYPE (base + 0x160))
+#define ETHER_ARC_ADR_ARC_LOC_OFST				(2)
+#define ETHER_ARC_ADR_ARC_LOC_MSK				(0xFFC)
+
+#define ETHER_ARC_DATA(base)  (ETHER00_TYPE (base + 0x364))
+
+#define ETHER_ARC_ENA(base)   (ETHER00_TYPE (base + 0x28))
+#define ETHER_ARC_ENA_MSK					(0x1FFFFF)
+
+#define ETHER_PROM_CTL(base)							(ETHER00_TYPE (base + 0x2c))
+#define ETHER_PROM_CTL_PROM_ADDR_OFST			(0)
+#define ETHER_PROM_CTL_PROM_ADDR_MSK			(0x3F)
+#define ETHER_PROM_CTL_OPCODE_OFST				(13)
+#define ETHER_PROM_CTL_OPCODE_MSK				(0x6000)
+#define ETHER_PROM_CTL_OPCODE_READ_MSK			(0x4000)
+#define ETHER_PROM_CTL_OPCODE_WRITE_MSK			(0x2000)
+#define ETHER_PROM_CTL_OPCODE_ERASE_MSK			(0x6000)
+#define ETHER_PROM_CTL_ENABLE_MSK				(0x0030)
+#define ETHER_PROM_CTL_DISABLE_MSK				(0x0000)
+#define ETHER_PROM_CTL_BUSY_OFST				(15)
+#define ETHER_PROM_CTL_BUSY_MSK					(0x8000)
+
+#define ETHER_PROM_DATA(base)							(ETHER00_TYPE (base + 0x30))
+
+#define ETHER_MISS_CNT(base)							(ETHER00_TYPE (base + 0x3c))
+#define ETHER_MISS_CNT_COUNT_OFST				(0)
+#define ETHER_MISS_CNT_COUNT_MSK				(0xFFFF)
+
+#define ETHER_CNTDATA(base)							(ETHER00_TYPE (base + 0x80))
+
+#define ETHER_CNTACC(base)							(ETHER00_TYPE (base + 0x84))
+#define ETHER_CNTACC_ADDR_OFST					(0)
+#define ETHER_CNTACC_ADDR_MSK					(0xFF)
+#define ETHER_CNTACC_WRRDN_OFST					(8)
+#define ETHER_CNTACC_WRRDN_MSK					(0x100)
+#define ETHER_CNTACC_CLEAR_OFST					(9)
+#define ETHER_CNTACC_CLEAR_MSK					(0x200)
+
+#define ETHER_TXRMINTEN(base)							(ETHER00_TYPE (base + 0x88))
+#define ETHER_TXRMINTEN_MSK						(0x3FFFFFFF)
+
+#define ETHER_RXRMINTEN(base)							(ETHER00_TYPE (base + 0x8C))
+#define ETHER_RXRMINTEN_MSK						(0xFFFFFF)
+
+/*
+*	RMON Registers
+*/
+#define		RMON_COLLISION0						0x0
+#define		RMON_COLLISION1						0x1
+#define		RMON_COLLISION2						0x2
+#define		RMON_COLLISION3						0x3
+#define		RMON_COLLISION4						0x4
+#define		RMON_COLLISION5						0x5
+#define		RMON_COLLISION6						0x6
+#define		RMON_COLLISION7						0x7
+#define		RMON_COLLISION8						0x8
+#define		RMON_COLLISION9						0x9
+#define		RMON_COLLISION10					0xa
+#define		RMON_COLLISION11					0xb
+#define		RMON_COLLISION12					0xc
+#define		RMON_COLLISION13					0xd
+#define		RMON_COLLISION14					0xe
+#define		RMON_COLLISION15					0xf
+#define		RMON_COLLISION16					0x10
+#define		RMON_FRAMES_WITH_DEFERRED_XMISSIONS	0x11
+#define		RMON_LATE_COLLISIONS				0x12
+#define		RMON_FRAMES_LOST_DUE_TO_MAC_XMIT	0x13
+#define		RMON_CARRIER_SENSE_ERRORS			0x14
+#define		RMON_FRAMES_WITH_EXCESSIVE_DEFERAL	0x15
+#define		RMON_UNICAST_FRAMES_TRANSMITTED_OK	0x16
+#define		RMON_MULTICAST_FRAMES_XMITTED_OK	0x17
+#define		RMON_BROADCAST_FRAMES_XMITTED_OK	0x18
+#define		RMON_SQE_TEST_ERRORS				0x19
+#define		RMON_PAUSE_MACCTRL_FRAMES_XMITTED	0x1A
+#define		RMON_MACCTRL_FRAMES_XMITTED			0x1B
+#define		RMON_VLAN_FRAMES_XMITTED			0x1C
+#define		RMON_OCTETS_XMITTED_OK				0x1D
+#define		RMON_OCTETS_XMITTED_OK_HI			0x1E
+
+#define		RMON_RX_PACKET_SIZES0				0x40
+#define		RMON_RX_PACKET_SIZES1				0x41
+#define		RMON_RX_PACKET_SIZES2				0x42
+#define		RMON_RX_PACKET_SIZES3				0x43
+#define		RMON_RX_PACKET_SIZES4				0x44
+#define		RMON_RX_PACKET_SIZES5				0x45
+#define		RMON_RX_PACKET_SIZES6				0x46
+#define		RMON_RX_PACKET_SIZES7				0x47
+#define		RMON_FRAME_CHECK_SEQUENCE_ERRORS	0x48
+#define		RMON_ALIGNMENT_ERRORS				0x49
+#define		RMON_FRAGMENTS						0x4A
+#define		RMON_JABBERS						0x4B
+#define		RMON_FRAMES_LOST_TO_INTMACRCVERR	0x4C
+#define		RMON_UNICAST_FRAMES_RCVD_OK			0x4D
+#define		RMON_MULTICAST_FRAMES_RCVD_OK		0x4E
+#define		RMON_BROADCAST_FRAMES_RCVD_OK		0x4F
+#define		RMON_IN_RANGE_LENGTH_ERRORS			0x50
+#define		RMON_OUT_OF_RANGE_LENGTH_ERRORS		0x51
+#define		RMON_VLAN_FRAMES_RCVD				0x52
+#define		RMON_PAUSE_MAC_CTRL_FRAMES_RCVD		0x53
+#define		RMON_MAC_CTRL_FRAMES_RCVD			0x54
+#define		RMON_OCTETS_RCVD_OK					0x55
+#define		RMON_OCTETS_RCVD_OK_HI				0x56
+#define		RMON_OCTETS_RCVD_OTHER				0x57
+#define		RMON_OCTETS_RCVD_OTHER_HI			0x58
+
+#endif /* __ETHER00_H */
diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h
index f0c16e3f190c..b93a52571f25 100644
--- a/include/asm-arm/arch-epxa10db/io.h
+++ b/include/asm-arm/arch-epxa10db/io.h
@@ -26,8 +26,6 @@
 /*
  * Generic virtual read/write
  */
-#define __arch_getw(a)		(*(volatile unsigned short *)(a))
-#define __arch_putw(v,a)	(*(volatile unsigned short *)(a) = (v))
 /*#define outsw   __arch_writesw
 #define outsl   __arch_writesl
 #define outsb   __arch_writesb
@@ -36,20 +34,6 @@
 #define insl    __arch_readsl*/
 
 #define __io(a)			(a)
-#if 0
-#define __mem_pci(a)		((unsigned long)(a))
-#define __mem_isa(a)		(PCI_MEMORY_VADDR + (unsigned long)(a))
-/*
- * Validate the pci memory address for ioremap.
- */
-#define iomem_valid_addr(iomem,size)	\
-	((iomem) > 0 && (iomem) + (size) <= 0x20000000)
-
-/*
- * Convert PCI memory space to a CPU physical address
- */
-#define iomem_to_phys(iomem)	((iomem) + PHYS_PCI_MEM_BASE)
-
-#endif
+#define __mem_pci(a)            (a) 
 
 #endif
diff --git a/include/asm-arm/arch-epxa10db/tdkphy.h b/include/asm-arm/arch-epxa10db/tdkphy.h
new file mode 100644
index 000000000000..5e107bd4e109
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/tdkphy.h
@@ -0,0 +1,209 @@
+/*
+ *  linux/drivers/tdkphy.h
+ *
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __TDKPHY_H
+#define __TDKPHY_H
+
+/*
+ * Register definitions for the TDK 78Q2120 PHY 
+ * which is on the Camelot board
+ */
+
+/*
+ * Copyright (c) Altera Corporation 2000.
+ * All rights reserved.
+ */
+#define PHY_CONTROL                                                                                     (0)
+#define PHY_CONTROL_COLT_MSK                                                            (0x80)
+#define PHY_CONTROL_COLT_OFST                                                           (7)
+#define PHY_CONTROL_DUPLEX_MSK                                                          (0x100)
+#define PHY_CONTROL_DUPLEX_OFST                                                         (8)
+#define PHY_CONTROL_RANEG_MSK                                                           (0x200)
+#define PHY_CONTROL_RANEG_OFST                                                          (9)
+#define PHY_CONTROL_ISO_MSK                                                                     (0x400)
+#define PHY_CONTROL_ISO_OFST                                                            (10)
+#define PHY_CONTROL_PWRDN_MSK                                                           (0x800)
+#define PHY_CONTROL_PWRDN_OFST                                                          (11)
+#define PHY_CONTROL_ANEGEN_MSK                                                          (0x1000)
+#define PHY_CONTROL_ANEGEN_OFST                                                         (12)
+#define PHY_CONTROL_SPEEDSL_MSK                                                         (0x2000)
+#define PHY_CONTROL_SPEEDSL_OFST                                                        (13)
+#define PHY_CONTROL_LOOPBK_MSK                                                          (0x4000)
+#define PHY_CONTROL_LOOPBK_OFST                                                         (14)
+#define PHY_CONTROL_RESET_MSK                                                           (0x8000)
+#define PHY_CONTROL_RESET_OFST                                                          (15)
+
+#define PHY_STATUS                                                                                      (1)
+#define PHY_STATUS_ETXD_MSK                                                                     (0x1)
+#define PHY_STATUS_EXTD_OFST                                                            (0)
+#define PHY_STATUS_JAB_MSK                                                                      (0x2)
+#define PHY_STATUS_JAB_OFST                                                                     (1)
+#define PHY_STATUS_LINK_MSK                                                                     (0x4)
+#define PHY_STATUS_LINK_OFST                                                            (2)
+#define PHY_STATUS_ANEGA_MSK                                                            (0x8)
+#define PHY_STATUS_ANEGA_OFST                                                           (3)
+#define PHY_STATUS_RFAULT_MSK                                                           (0x10)
+#define PHY_STATUS_RFAULT_OFST                                                          (4)
+#define PHY_STATUS_ANEGC_MSK                                                            (0x20)
+#define PHY_STATUS_ANEGC_OFST                                                           (5)
+#define PHY_STATUS_10T_H_MSK                                                            (0x800)
+#define PHY_STATUS_10T_H_OFST                                                           (11)
+#define PHY_STATUS_10T_F_MSK                                                            (0x1000)
+#define PHY_STATUS_10T_F_OFST                                                           (12)
+#define PHY_STATUS_100_X_H_MSK                                                          (0x2000)
+#define PHY_STATUS_100_X_H_OFST                                                         (13)
+#define PHY_STATUS_100_X_F_MSK                                                          (0x4000)
+#define PHY_STATUS_100_X_F_OFST                                                         (14)
+#define PHY_STATUS_100T4_MSK                                                            (0x8000)
+#define PHY_STATUS_100T4_OFST                                                           (15)
+
+#define PHY_ID1                                                                                         (2)
+#define PHY_ID1_OUI_MSK                                                                         (0xFFFF)
+#define PHY_ID1_OUI_OFST                                                                        (0)
+
+#define PHY_ID2                                                                                         (3)
+#define PHY_ID2_RN_MSK                                                                          (0xF)
+#define PHY_ID2_RN_OFST                                                                         (0)
+#define PHY_ID2_MN_MSK                                                                          (0x3F0)
+#define PHY_ID2_MN_OFST                                                                         (4)
+#define PHY_ID2_OUI_MSK                                                                         (0xFC00)
+#define PHY_ID2_OUI_OFST                                                                        (10)
+
+#define PHY_AUTO_NEG_ADVERTISEMENT                                                      (4)
+#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_MSK                         (0x1F)
+#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_OFST                        (0)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A0_MSK                                       (0x20)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A0_OFST                                      (5)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A1_MSK                                       (0x40)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A1_OFST                                      (6)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A2_MSK                                       (0x80)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A2_OFST                                      (7)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A3_MSK                                       (0x100)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A3_OFST                                      (8)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A4_MSK                                       (0x200)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A4_OFST                                      (9)
+#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_MSK                                      (0x1FE0)
+#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_OFST                                     (5)
+#define PHY_AUTO_NEG_ADVERTISEMENT_RF_MSK                                       (0x2000)
+#define PHY_AUTO_NEG_ADVERTISEMENT_RF_OFST                                      (13)
+#define PHY_AUTO_NEG_ADVERTISEMENT_RSVD_MSK                                     (0x4000)
+#define PHY_AUTO_NEG_ADVERTISEMENT_RVSD_OFST                            (14)
+#define PHY_AUTO_NEG_ADVERTISEMENT_NP_MSK                                       (0x8000)
+#define PHY_AUTO_NEG_ADVERTISEMENT_NP_OFST                                      (15)
+
+#define PHY_AUTO_NEG_LINK_PARTNER                                                       (5)
+#define PHY_AUTO_NEG_LINK_PARTNER_S4_MSK                                        (0x1F)
+#define PHY_AUTO_NEG_LINK_PARTNER_S4_OFST                                       (0)
+#define PHY_AUTO_NEG_LINK_PARTNER_A7_MSK                                        (0x1FE0)
+#define PHY_AUTO_NEG_LINK_PARTNER_A7_OFST                                       (5)
+#define PHY_AUTO_NEG_LINK_PARTNER_RF_MSK                                        (0x2000)
+#define PHY_AUTO_NEG_LINK_PARTNER_RF_OFST                                       (13)
+#define PHY_AUTO_NEG_LINK_PARTNER_ACK_MSK                                       (0x4000)
+#define PHY_AUTO_NEG_LINK_PARTNER_ACK_OFST                                      (14)
+#define PHY_AUTO_NEG_LINK_PARTNER_NP_MSK                                        (0x8000)
+#define PHY_AUTO_NEG_LINK_PARTNER_NP_OFST                                       (15)
+
+#define PHY_AUTO_NEG_EXPANSION                                                          (6)
+#define PHY_AUTO_NEG_EXPANSION_LPANEGA_MSK                                      (0x1)
+#define PHY_AUTO_NEG_EXPANSION_LPANEGA_OFST                                     (0)
+#define PHY_AUTO_NEG_EXPANSION_PRX_MSK                                          (0x2)
+#define PHY_AUTO_NEG_EXPANSION_PRX_OFST                                         (1)
+#define PHY_AUTO_NEG_EXPANSION_NPA_MSK                                          (0x4)
+#define PHY_AUTO_NEG_EXPANSION_NPA_OFST                                         (2)
+#define PHY_AUTO_NEG_EXPANSION_LPNPA_MSK                                        (0x8)
+#define PHY_AUTO_NEG_EXPANSION_LPNPA_OFST                                       (3)
+#define PHY_AUTO_NEG_EXPANSION_PDF_MSK                                          (0x10)
+#define PHY_AUTO_NEG_EXPANSION_PDF_OFST                                         (4)
+
+#define PHY_VENDOR_SPECIFIC                                                                     (16)
+#define PHY_VENDOR_SPECIFIC_RXCC_MSK                                            (0x1)
+#define PHY_VENDOR_SPECIFIC_RXCC_OFST                                           (0)
+#define PHY_VENDOR_SPECIFIC_PCSBP_MSK                                           (0x2)
+#define PHY_VENDOR_SPECIFIC_PCSBP_OFST                                          (1)
+#define PHY_VENDOR_SPECIFIC_RVSPOL_MSK                                          (0x10)
+#define PHY_VENDOR_SPECIFIC_RVSPOL_OFST                                         (4)
+#define PHY_VENDOR_SPECIFIC_APOL_MSK                                            (0x20)  
+#define PHY_VENDOR_SPECIFIC_APOL_OFST                                           (5)
+#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_MSK                                       (0x40)
+#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_OFST                                      (6)
+#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_MSK                                       (0x80)
+#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_OFST                                      (7)
+#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_MSK                                       (0x100)
+#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_OFST                                      (8)
+#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_MSK                                       (0x200)
+#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_OFST                                      (9)
+#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_MSK       (0x400)
+#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_OFST      (10)
+#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_MSK           (0x800)
+#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_OFST          (11)
+#define PHY_VENDOR_SPECIFIC_TXHIM_MSK                                           (0x1000)
+#define PHY_VENDOR_SPECIFIC_TXHIM_OFST                                          (12)
+#define PHY_VENDOR_SPECIFIC_INT_LEVEL_MSK                                       (0x4000)
+#define PHY_VENDOR_SPECIFIC_INT_LEVEL_OFST                                      (14)
+#define PHY_VENDOR_SPECIFIC_RPTR_MSK                                            (0x8000)
+#define PHY_VENDOR_SPECIFIC_RPTR_OFST                                           (15)
+
+#define PHY_IRQ_CONTROL                                                                         (17)
+#define PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK                                       (0x1)
+#define PHY_IRQ_CONTROL_ANEG_COMP_INT_OFST                                      (0)
+#define PHY_IRQ_CONTROL_RFAULT_INT_MSK                                          (0x2)
+#define PHY_IRQ_CONTROL_RFAULT_INT_OFST                                         (1)
+#define PHY_IRQ_CONTROL_LS_CHG_INT_MSK                                          (0x4)
+#define PHY_IRQ_CONTROL_LS_CHG_INT_OFST                                         (2)
+#define PHY_IRQ_CONTROL_LP_ACK_INT_MSK                                          (0x8)
+#define PHY_IRQ_CONTROL_LP_ACK_INT_OFST                                         (3)
+#define PHY_IRQ_CONTROL_PDF_INT_MSK                                                     (0x10)
+#define PHY_IRQ_CONTROL_PDF_INT_OFST                                            (4)
+#define PHY_IRQ_CONTROL_PRX_INT_MSK                                                     (0x20)
+#define PHY_IRQ_CONTROL_PRX_INT_OFST                                            (5)
+#define PHY_IRQ_CONTROL_RXER_INT_MSK                                            (0x40)
+#define PHY_IRQ_CONTROL_RXER_INT_OFST                                           (6)
+#define PHY_IRQ_CONTROL_JABBER_INT_MSK                                          (0x80)
+#define PHY_IRQ_CONTROL_JABBER_INT_OFST                                         (7)
+#define PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK                                        (0x100)
+#define PHY_IRQ_CONTROL_ANEG_COMP_IE_OFST                                       (8)
+#define PHY_IRQ_CONTROL_RFAULT_IE_MSK                                           (0x200)
+#define PHY_IRQ_CONTROL_RFAULT_IE_OFST                                          (9)
+#define PHY_IRQ_CONTROL_LS_CHG_IE_MSK                                           (0x400)
+#define PHY_IRQ_CONTROL_LS_CHG_IE_OFST                                          (10)
+#define PHY_IRQ_CONTROL_LP_ACK_IE_MSK                                           (0x800)
+#define PHY_IRQ_CONTROL_LP_ACK_IE_OFST                                          (11)
+#define PHY_IRQ_CONTROL_PDF_IE_MSK                                                      (0x1000)
+#define PHY_IRQ_CONTROL_PDF_IE_OFST                                                     (12)
+#define PHY_IRQ_CONTROL_PRX_IE_MSK                                                      (0x2000)
+#define PHY_IRQ_CONTROL_PRX_IE_OFST                                                     (13)
+#define PHY_IRQ_CONTROL_RXER_IE_MSK                                                     (0x4000)
+#define PHY_IRQ_CONTROL_RXER_IE_OFST                                            (14)
+#define PHY_IRQ_CONTROL_JABBER_IE_MSK                                           (0x8000)
+#define PHY_IRQ_CONTROL_JABBER_IE_OFST                                          (15)
+
+#define PHY_DIAGNOSTIC                                                                          (18)
+#define PHY_DIAGNOSTIC_RX_LOCK_MSK                                                      (0x100)
+#define PHY_DIAGNOSTIC_RX_LOCK_OFST                                                     (8)
+#define PHY_DIAGNOSTIC_RX_PASS_MSK                                                      (0x200)
+#define PHY_DIAGNOSTIC_RX_PASS_OFST                                                     (9)
+#define PHY_DIAGNOSTIC_RATE_MSK                                                         (0x400)
+#define PHY_DIAGNOSTIC_RATE_OFST                                                        (10)
+#define PHY_DIAGNOSTIC_DPLX_MSK                                                         (0x800)
+#define PHY_DIAGNOSTIC_DPLX_OFST                                                        (11)
+#define PHY_DIAGNOSTIC_ANEGF_MSK                                                        (0x1000)
+#define PHY_DIAGNOSTIC_ANEGF_OFST                                                       (12)
+
+#endif /* __TDKPHY_H */
diff --git a/include/asm-arm/arch-epxa10db/time.h b/include/asm-arm/arch-epxa10db/time.h
index ae7223429cca..b18453053e9b 100644
--- a/include/asm-arm/arch-epxa10db/time.h
+++ b/include/asm-arm/arch-epxa10db/time.h
@@ -42,20 +42,17 @@ static void excalibur_timer_interrupt(int irq, void *dev_id, struct pt_regs *reg
 /*
  * Set up timer interrupt, and return the current time in seconds.
  */
-extern __inline__ void setup_timer(void)
+void __init time_init(void)
 {
-
-
 	timer_irq.handler = excalibur_timer_interrupt;
 
-
 	/* 
 	 * Make irqs happen for the system timer
 	 */
 	setup_arm_irq(IRQ_TIMER0, &timer_irq);
 
 	/* Start the timer */
-	*TIMER0_LIMIT(IO_ADDRESS(EXC_TIMER00_BASE))=(unsigned int)(EXC_AHB2_CLK_FREQUENCY/50);
+	*TIMER0_LIMIT(IO_ADDRESS(EXC_TIMER00_BASE))=(unsigned int)(EXC_AHB2_CLK_FREQUENCY/200);
 	*TIMER0_PRESCALE(IO_ADDRESS(EXC_TIMER00_BASE))=1;
 	*TIMER0_CR(IO_ADDRESS(EXC_TIMER00_BASE))=TIMER0_CR_IE_MSK | TIMER0_CR_S_MSK;
 }
diff --git a/include/asm-arm/arch-integrator/io.h b/include/asm-arm/arch-integrator/io.h
index 607147a34b33..c94b789570f6 100644
--- a/include/asm-arm/arch-integrator/io.h
+++ b/include/asm-arm/arch-integrator/io.h
@@ -26,20 +26,4 @@
 #define __mem_pci(a)		((unsigned long)(a))
 #define __mem_isa(a)		(PCI_MEMORY_VADDR + (unsigned long)(a))
 
-/*
- * Generic virtual read/write
- */
-#define __arch_getw(a)		(*(volatile unsigned short *)(a))
-#define __arch_putw(v,a)	(*(volatile unsigned short *)(a) = (v))
-
-/*
- * Validate the pci memory address for ioremap.
- */
-#define iomem_valid_addr(iomem,size)	(1)
-
-/*
- * Convert PCI memory space to a CPU physical address
- */
-#define iomem_to_phys(iomem)	(iomem)
-
 #endif
diff --git a/include/asm-arm/arch-integrator/time.h b/include/asm-arm/arch-integrator/time.h
index 878ed34e242d..40b48370c692 100644
--- a/include/asm-arm/arch-integrator/time.h
+++ b/include/asm-arm/arch-integrator/time.h
@@ -113,7 +113,7 @@ static void integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *re
 /*
  * Set up timer interrupt, and return the current time in seconds.
  */
-static inline void setup_timer(void)
+void __init time_init(void)
 {
 	volatile TimerStruct_t *timer0 = (volatile TimerStruct_t *)TIMER0_VA_BASE;
 	volatile TimerStruct_t *timer1 = (volatile TimerStruct_t *)TIMER1_VA_BASE;
diff --git a/include/asm-arm/arch-iop310/dma.h b/include/asm-arm/arch-iop310/dma.h
new file mode 100644
index 000000000000..b7086571d121
--- /dev/null
+++ b/include/asm-arm/arch-iop310/dma.h
@@ -0,0 +1,109 @@
+/*
+ * linux/include/asm-arm/arch-iop80310/dma.h
+ *
+ *  Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IOP310_DMA_H_
+#define _IOP310_DMA_H_
+
+/* 2 DMA on primary PCI and 1 on secondary for 80310 */
+#define MAX_IOP310_DMA_CHANNEL   3
+#define MAX_DMA_DESC        	64	/*128 */
+
+/*
+ * Make the generic DMA bits go away since we don't use it
+ */
+#define MAX_DMA_CHANNELS	0
+
+#define MAX_DMA_ADDRESS		0xffffffff
+
+#define IOP310_DMA_P0      	0
+#define IOP310_DMA_P1		1
+#define IOP310_DMA_S0      	2
+
+#define DMA_MOD_READ        	0x0001
+#define DMA_MOD_WRITE		0x0002
+#define DMA_MOD_CACHED		0x0004
+#define DMA_MOD_NONCACHED	0x0008
+
+
+#define DMA_DESC_DONE   	0x0010
+#define DMA_INCOMPLETE  	0x0020
+#define DMA_HOLD		0x0040
+#define DMA_END_CHAIN		0x0080
+#define DMA_COMPLETE		0x0100
+#define DMA_NOTIFY		0x0200
+#define DMA_NEW_HEAD		0x0400
+
+#define DMA_USER_MASK	(DMA_NOTIFY | DMA_INCOMPLETE | \
+						 DMA_HOLD | DMA_COMPLETE)
+
+#define DMA_DCR_DAC		0x00000020	/* Dual Addr Cycle Enab */
+#define DMA_DCR_IE		0x00000010	/* Interrupt Enable */
+#define DMA_DCR_PCI_IOR		0x00000002	/* I/O Read */
+#define DMA_DCR_PCI_IOW		0x00000003	/* I/O Write */
+#define DMA_DCR_PCI_MR		0x00000006	/* Memory Read */
+#define DMA_DCR_PCI_MW		0x00000007	/* Memory Write */
+#define DMA_DCR_PCI_CR		0x0000000A	/* Configuration Read */
+#define DMA_DCR_PCI_CW		0x0000000B	/* Configuration Write */
+#define DMA_DCR_PCI_MRM		0x0000000C	/* Memory Read Multiple */
+#define DMA_DCR_PCI_MRL		0x0000000E	/* Memory Read Line */
+#define DMA_DCR_PCI_MWI		0x0000000F	/* Mem Write and Inval */
+
+#define DMA_USER_CMD_IE		0x00000001	/* user request int */
+#define DMA_USER_END_CHAIN	0x00000002	/* end of sgl chain flag */
+
+/* ATU defines */
+#define     IOP310_ATUCR_PRIM_OUT_ENAB  /* Configuration   */      0x00000002
+#define     IOP310_ATUCR_DIR_ADDR_ENAB  /* Configuration   */      0x00000080
+
+
+typedef void (*dma_callback_t) (void *buf_context);
+/*
+ * DMA Descriptor
+ */
+typedef struct _dma_desc
+{
+	u32 NDAR;					/* next descriptor adress */
+	u32 PDAR;					/* PCI address */
+	u32 PUADR;					/* upper PCI address */
+	u32 LADR;					/* local address */
+	u32 BC;						/* byte count */
+	u32 DC;						/* descriptor control */
+} dma_desc_t;
+
+typedef struct _dma_sgl
+{
+	dma_desc_t dma_desc;		/* DMA descriptor pointer */
+	u32 status;					/* descriptor status */
+	void *data;					/* local virt */
+	struct _dma_sgl *next;		/* next descriptor */
+} dma_sgl_t;
+
+/* dma sgl head */
+typedef struct _dma_head
+{
+	u32 total;					/* total elements in SGL */
+	u32 status;					/* status of sgl */
+	u32 mode;					/* read or write mode */
+	dma_sgl_t *list;			/* pointer to list */
+	dma_callback_t callback;	/* callback function */
+} dma_head_t;
+
+/* function prototypes */
+int dma_request(dmach_t, const char *);
+int dma_queue_buffer(dmach_t, dma_head_t *);
+int dma_suspend(dmach_t);
+int dma_resume(dmach_t);
+int dma_flush_all(dmach_t);
+void dma_free(dmach_t);
+void dma_set_irq_threshold(dmach_t, int);
+dma_sgl_t *dma_get_buffer(dmach_t, int);
+void dma_return_buffer(dmach_t, dma_sgl_t *);
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-iop310/hardware.h b/include/asm-arm/arch-iop310/hardware.h
new file mode 100644
index 000000000000..4fb2bcbb112f
--- /dev/null
+++ b/include/asm-arm/arch-iop310/hardware.h
@@ -0,0 +1,38 @@
+/*
+ * linux/include/asm-arm/arch-iop80310/hardware.h
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/config.h>
+
+/*
+ * Note about PCI IO space mappings
+ *
+ * To make IO space accesses efficient, we store virtual addresses in
+ * the IO resources.
+ *
+ * The PCI IO space is located at virtual 0xfe000000 from physical
+ * 0x90000000.  The PCI BARs must be programmed with physical addresses,
+ * but when we read them, we convert them to virtual addresses.  See
+ * arch/arm/mach-iop310/iop310-pci.c
+ */
+
+#define pcibios_assign_all_busses() 1
+
+/*
+ * these are the values for the secondary PCI bus on the 80312 chip.  I will
+ * have to do some fixup in the bus/dev fixup code
+ */
+#define PCIBIOS_MIN_IO      0
+#define PCIBIOS_MIN_MEM     0x88000000
+
+// Generic chipset bits
+#include "iop310.h"
+
+// Board specific
+#if defined(CONFIG_ARCH_IQ80310)
+#include "iq80310.h"
+#endif
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop310/ide.h b/include/asm-arm/arch-iop310/ide.h
new file mode 100644
index 000000000000..e0a6dec8236a
--- /dev/null
+++ b/include/asm-arm/arch-iop310/ide.h
@@ -0,0 +1,51 @@
+/*
+ * include/asm-arm/arch-iop310/ide.h
+ *
+ * Generic IDE functions for IOP310 systems
+ *
+ * Author: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ *
+ * 09/26/2001 - Sharon Baartmans
+ * 	Fixed so it actually works.
+ */
+
+#ifndef _ASM_ARCH_IDE_H_
+#define _ASM_ARCH_IDE_H_
+
+/*
+ * Set up a hw structure for a specified data port, control port and IRQ.
+ * This should follow whatever the default interface uses.
+ */
+static __inline__ void
+ide_init_hwif_ports(hw_regs_t *hw, int data_port, int ctrl_port, int *irq)
+{
+	ide_ioreg_t reg;
+	int i;
+	int regincr = 1;
+
+	memset(hw, 0, sizeof(*hw));
+
+	reg = (ide_ioreg_t)data_port;
+
+	for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
+		hw->io_ports[i] = reg;
+		reg += regincr;
+	}
+
+	hw->io_ports[IDE_CONTROL_OFFSET] = (ide_ioreg_t) ctrl_port;
+
+	if (irq) *irq = 0;
+}
+
+/*
+ * This registers the standard ports for this architecture with the IDE
+ * driver.
+ */
+static __inline__ void ide_init_default_hwifs(void)
+{
+	/* There are no standard ports */
+}
+
+#endif
diff --git a/include/asm-arm/arch-iop310/io.h b/include/asm-arm/arch-iop310/io.h
new file mode 100644
index 000000000000..6b5c92936a55
--- /dev/null
+++ b/include/asm-arm/arch-iop310/io.h
@@ -0,0 +1,20 @@
+/*
+ * linux/include/asm-arm/arch-iop310/io.h
+ *
+ *  Copyright (C) 2001  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(p)			((p))
+#define __mem_pci(a)		((unsigned long)(a))
+#define __mem_isa(a)		((unsigned long)(a))
+
+#endif
diff --git a/include/asm-arm/arch-iop310/iop310.h b/include/asm-arm/arch-iop310/iop310.h
new file mode 100644
index 000000000000..d2445fdf76ff
--- /dev/null
+++ b/include/asm-arm/arch-iop310/iop310.h
@@ -0,0 +1,247 @@
+/*
+ * linux/include/asm/arch-iop310/iop310.h
+ *
+ * Intel IOP310 Compainion Chip definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IOP310_HW_H_
+#define _IOP310_HW_H_
+
+/*
+ * IOP310 I/O and Mem space regions for PCI autoconfiguration
+ */
+#define IOP310_PCISEC_LOWER_IO		0x90010000
+#define IOP310_PCISEC_UPPER_IO		0x9001ffff
+#define IOP310_PCISEC_LOWER_MEM		0x88000000
+#define IOP310_PCISEC_UPPER_MEM		0x8bffffff
+
+#define IOP310_PCIPRI_LOWER_IO		0x90000000
+#define IOP310_PCIPRI_UPPER_IO		0x9000ffff
+#define IOP310_PCIPRI_LOWER_MEM		0x80000000
+#define IOP310_PCIPRI_UPPER_MEM		0x83ffffff
+
+#define IOP310_PCI_WINDOW_SIZE		64 * 0x100000
+
+/*
+ * IOP310 chipset registers
+ */
+#define IOP310_VIRT_MEM_BASE 0xe8001000  /* chip virtual mem address*/
+#define IOP310_PHY_MEM_BASE  0x00001000  /* chip physical memory address */
+#define IOP310_REG_ADDR(reg) (IOP310_VIRT_MEM_BASE | IOP310_PHY_MEM_BASE | (reg))
+
+/* PCI-to-PCI Bridge Unit 0x00001000 through 0x000010FF */
+#define IOP310_VIDR    (volatile u16 *)IOP310_REG_ADDR(0x00001000)
+#define IOP310_DIDR    (volatile u16 *)IOP310_REG_ADDR(0x00001002)
+#define IOP310_PCR     (volatile u16 *)IOP310_REG_ADDR(0x00001004)
+#define IOP310_PSR     (volatile u16 *)IOP310_REG_ADDR(0x00001006)
+#define IOP310_RIDR    (volatile u8  *)IOP310_REG_ADDR(0x00001008)
+#define IOP310_CCR     (volatile u32 *)IOP310_REG_ADDR(0x00001009)
+#define IOP310_CLSR    (volatile u8  *)IOP310_REG_ADDR(0x0000100C)
+#define IOP310_PLTR    (volatile u8  *)IOP310_REG_ADDR(0x0000100D)
+#define IOP310_HTR     (volatile u8  *)IOP310_REG_ADDR(0x0000100E)
+/* Reserved 0x0000100F through  0x00001017 */
+#define IOP310_PBNR    (volatile u8  *)IOP310_REG_ADDR(0x00001018)
+#define IOP310_SBNR    (volatile u8  *)IOP310_REG_ADDR(0x00001019)
+#define IOP310_SUBBNR  (volatile u8  *)IOP310_REG_ADDR(0x0000101A)
+#define IOP310_SLTR    (volatile u8  *)IOP310_REG_ADDR(0x0000101B)
+#define IOP310_IOBR    (volatile u8  *)IOP310_REG_ADDR(0x0000101C)
+#define IOP310_IOLR    (volatile u8  *)IOP310_REG_ADDR(0x0000101D)
+#define IOP310_SSR     (volatile u16 *)IOP310_REG_ADDR(0x0000101E)
+#define IOP310_MBR     (volatile u16 *)IOP310_REG_ADDR(0x00001020)
+#define IOP310_MLR     (volatile u16 *)IOP310_REG_ADDR(0x00001022)
+#define IOP310_PMBR    (volatile u16 *)IOP310_REG_ADDR(0x00001024)
+#define IOP310_PMLR    (volatile u16 *)IOP310_REG_ADDR(0x00001026)
+/* Reserved 0x00001028 through 0x00001033 */
+#define IOP310_CAPR    (volatile u8  *)IOP310_REG_ADDR(0x00001034)
+/* Reserved 0x00001035 through 0x0000103D */
+#define IOP310_BCR     (volatile u16 *)IOP310_REG_ADDR(0x0000103E)
+#define IOP310_EBCR    (volatile u16 *)IOP310_REG_ADDR(0x00001040)
+#define IOP310_SISR    (volatile u16 *)IOP310_REG_ADDR(0x00001042)
+#define IOP310_PBISR   (volatile u32 *)IOP310_REG_ADDR(0x00001044)
+#define IOP310_SBISR   (volatile u32 *)IOP310_REG_ADDR(0x00001048)
+#define IOP310_SACR    (volatile u32 *)IOP310_REG_ADDR(0x0000104C)
+#define IOP310_PIRSR   (volatile u32 *)IOP310_REG_ADDR(0x00001050)
+#define IOP310_SIOBR   (volatile u8  *)IOP310_REG_ADDR(0x00001054)
+#define IOP310_SIOLR   (volatile u8  *)IOP310_REG_ADDR(0x00001055)
+#define IOP310_SCDR    (volatile u8  *)IOP310_REG_ADDR(0x00001056)
+
+#define IOP310_SMBR    (volatile u16 *)IOP310_REG_ADDR(0x00001058)
+#define IOP310_SMLR    (volatile u16 *)IOP310_REG_ADDR(0x0000105A)
+#define IOP310_SDER    (volatile u16 *)IOP310_REG_ADDR(0x0000105C)
+#define IOP310_QCR     (volatile u16 *)IOP310_REG_ADDR(0x0000105E)
+#define IOP310_CAPID   (volatile u8  *)IOP310_REG_ADDR(0x00001068)
+#define IOP310_NIPTR   (volatile u8  *)IOP310_REG_ADDR(0x00001069)
+#define IOP310_PMCR    (volatile u16 *)IOP310_REG_ADDR(0x0000106A)
+#define IOP310_PMCSR   (volatile u16 *)IOP310_REG_ADDR(0x0000106C)
+#define IOP310_PMCSRBSE (volatile u8 *)IOP310_REG_ADDR(0x0000106E)
+/* Reserved 0x00001064 through 0x000010FFH */
+
+/* Performance monitoring unit  0x00001100 through 0x000011FF*/
+#define IOP310_PMONGTMR    (volatile u32 *)IOP310_REG_ADDR(0x00001100)
+#define IOP310_PMONESR     (volatile u32 *)IOP310_REG_ADDR(0x00001104)
+#define IOP310_PMONEMISR   (volatile u32 *)IOP310_REG_ADDR(0x00001108)
+#define IOP310_PMONGTSR    (volatile u32 *)IOP310_REG_ADDR(0x00001110)
+#define IOP310_PMONPECR1   (volatile u32 *)IOP310_REG_ADDR(0x00001114)
+#define IOP310_PMONPECR2   (volatile u32 *)IOP310_REG_ADDR(0x00001118)
+#define IOP310_PMONPECR3   (volatile u32 *)IOP310_REG_ADDR(0x0000111C)
+#define IOP310_PMONPECR4   (volatile u32 *)IOP310_REG_ADDR(0x00001120)
+#define IOP310_PMONPECR5   (volatile u32 *)IOP310_REG_ADDR(0x00001124)
+#define IOP310_PMONPECR6   (volatile u32 *)IOP310_REG_ADDR(0x00001128)
+#define IOP310_PMONPECR7   (volatile u32 *)IOP310_REG_ADDR(0x0000112C)
+#define IOP310_PMONPECR8   (volatile u32 *)IOP310_REG_ADDR(0x00001130)
+#define IOP310_PMONPECR9   (volatile u32 *)IOP310_REG_ADDR(0x00001134)
+#define IOP310_PMONPECR10  (volatile u32 *)IOP310_REG_ADDR(0x00001138)
+#define IOP310_PMONPECR11  (volatile u32 *)IOP310_REG_ADDR(0x0000113C)
+#define IOP310_PMONPECR12  (volatile u32 *)IOP310_REG_ADDR(0x00001140)
+#define IOP310_PMONPECR13  (volatile u32 *)IOP310_REG_ADDR(0x00001144)
+#define IOP310_PMONPECR14  (volatile u32 *)IOP310_REG_ADDR(0x00001148)
+
+/* Address Translation Unit 0x00001200 through 0x000012FF */
+#define IOP310_ATUVID     (volatile u16 *)IOP310_REG_ADDR(0x00001200)
+#define IOP310_ATUDID     (volatile u16 *)IOP310_REG_ADDR(0x00001202)
+#define IOP310_PATUCMD    (volatile u16 *)IOP310_REG_ADDR(0x00001204)
+#define IOP310_PATUSR     (volatile u16 *)IOP310_REG_ADDR(0x00001206)
+#define IOP310_ATURID     (volatile u8  *)IOP310_REG_ADDR(0x00001208)
+#define IOP310_ATUCCR     (volatile u32 *)IOP310_REG_ADDR(0x00001209)
+#define IOP310_ATUCLSR    (volatile u8  *)IOP310_REG_ADDR(0x0000120C)
+#define IOP310_ATULT      (volatile u8  *)IOP310_REG_ADDR(0x0000120D)
+#define IOP310_ATUHTR     (volatile u8  *)IOP310_REG_ADDR(0x0000120E)
+
+#define IOP310_PIABAR     (volatile u32 *)IOP310_REG_ADDR(0x00001210)
+/* Reserved 0x00001214 through 0x0000122B */
+#define IOP310_ASVIR      (volatile u16 *)IOP310_REG_ADDR(0x0000122C)
+#define IOP310_ASIR       (volatile u16 *)IOP310_REG_ADDR(0x0000122E)
+#define IOP310_ERBAR      (volatile u32 *)IOP310_REG_ADDR(0x00001230)
+#define IOP310_ATUCAPPTR  (volatile u8  *)IOP310_REG_ADDR(0x00001234)
+/* Reserved 0x00001235 through 0x0000123B */
+#define IOP310_ATUILR     (volatile u8  *)IOP310_REG_ADDR(0x0000123C)
+#define IOP310_ATUIPR     (volatile u8  *)IOP310_REG_ADDR(0x0000123D)
+#define IOP310_ATUMGNT    (volatile u8  *)IOP310_REG_ADDR(0x0000123E)
+#define IOP310_ATUMLAT    (volatile u8  *)IOP310_REG_ADDR(0x0000123F)
+#define IOP310_PIALR      (volatile u32 *)IOP310_REG_ADDR(0x00001240)
+#define IOP310_PIATVR     (volatile u32 *)IOP310_REG_ADDR(0x00001244)
+#define IOP310_SIABAR     (volatile u32 *)IOP310_REG_ADDR(0x00001248)
+#define IOP310_SIALR      (volatile u32 *)IOP310_REG_ADDR(0x0000124C)
+#define IOP310_SIATVR     (volatile u32 *)IOP310_REG_ADDR(0x00001250)
+#define IOP310_POMWVR     (volatile u32 *)IOP310_REG_ADDR(0x00001254)
+/* Reserved 0x00001258 through 0x0000125B */
+#define IOP310_POIOWVR    (volatile u32 *)IOP310_REG_ADDR(0x0000125C)
+#define IOP310_PODWVR     (volatile u32 *)IOP310_REG_ADDR(0x00001260)
+#define IOP310_POUDR      (volatile u32 *)IOP310_REG_ADDR(0x00001264)
+#define IOP310_SOMWVR     (volatile u32 *)IOP310_REG_ADDR(0x00001268)
+#define IOP310_SOIOWVR    (volatile u32 *)IOP310_REG_ADDR(0x0000126C)
+/* Reserved 0x00001270 through 0x00001273*/
+#define IOP310_ERLR       (volatile u32 *)IOP310_REG_ADDR(0x00001274)
+#define IOP310_ERTVR      (volatile u32 *)IOP310_REG_ADDR(0x00001278)
+/* Reserved 0x00001279 through 0x0000127C*/
+#define IOP310_ATUCAPID   (volatile u8  *)IOP310_REG_ADDR(0x00001280)
+#define IOP310_ATUNIPTR   (volatile u8  *)IOP310_REG_ADDR(0x00001281)
+#define IOP310_APMCR      (volatile u16 *)IOP310_REG_ADDR(0x00001282)
+#define IOP310_APMCSR     (volatile u16 *)IOP310_REG_ADDR(0x00001284)
+/* Reserved 0x00001286 through 0x00001287 */
+#define IOP310_ATUCR      (volatile u32 *)IOP310_REG_ADDR(0x00001288)
+/* Reserved 0x00001289  through 0x0000128C*/
+#define IOP310_PATUISR    (volatile u32 *)IOP310_REG_ADDR(0x00001290)
+#define IOP310_SATUISR    (volatile u32 *)IOP310_REG_ADDR(0x00001294)
+#define IOP310_SATUCMD    (volatile u16 *)IOP310_REG_ADDR(0x00001298)
+#define IOP310_SATUSR     (volatile u16 *)IOP310_REG_ADDR(0x0000129A)
+#define IOP310_SODWVR     (volatile u32 *)IOP310_REG_ADDR(0x0000129C)
+#define IOP310_SOUDR      (volatile u32 *)IOP310_REG_ADDR(0x000012A0)
+#define IOP310_POCCAR     (volatile u32 *)IOP310_REG_ADDR(0x000012A4)
+#define IOP310_SOCCAR     (volatile u32 *)IOP310_REG_ADDR(0x000012A8)
+#define IOP310_POCCDR     (volatile u32 *)IOP310_REG_ADDR(0x000012AC)
+#define IOP310_SOCCDR     (volatile u32 *)IOP310_REG_ADDR(0x000012B0)
+#define IOP310_PAQCR      (volatile u32 *)IOP310_REG_ADDR(0x000012B4)
+#define IOP310_SAQCR      (volatile u32 *)IOP310_REG_ADDR(0x000012B8)
+#define IOP310_PATUIMR    (volatile u32 *)IOP310_REG_ADDR(0x000012BC)
+#define IOP310_SATUIMR    (volatile u32 *)IOP310_REG_ADDR(0x000012C0)
+/* Reserved 0x000012C4 through 0x000012FF */
+/* Messaging Unit 0x00001300 through 0x000013FF */
+#define IOP310_MUIMR0       (volatile u32 *)IOP310_REG_ADDR(0x00001310)
+#define IOP310_MUIMR1       (volatile u32 *)IOP310_REG_ADDR(0x00001314)
+#define IOP310_MUOMR0       (volatile u32 *)IOP310_REG_ADDR(0x00001318)
+#define IOP310_MUOMR1       (volatile u32 *)IOP310_REG_ADDR(0x0000131C)
+#define IOP310_MUIDR        (volatile u32 *)IOP310_REG_ADDR(0x00001320)
+#define IOP310_MUIISR       (volatile u32 *)IOP310_REG_ADDR(0x00001324)
+#define IOP310_MUIIMR       (volatile u32 *)IOP310_REG_ADDR(0x00001328)
+#define IOP310_MUODR        (volatile u32 *)IOP310_REG_ADDR(0x0000132C)
+#define IOP310_MUOISR       (volatile u32 *)IOP310_REG_ADDR(0x00001330)
+#define IOP310_MUOIMR       (volatile u32 *)IOP310_REG_ADDR(0x00001334)
+#define IOP310_MUMUCR       (volatile u32 *)IOP310_REG_ADDR(0x00001350)
+#define IOP310_MUQBAR       (volatile u32 *)IOP310_REG_ADDR(0x00001354)
+#define IOP310_MUIFHPR      (volatile u32 *)IOP310_REG_ADDR(0x00001360)
+#define IOP310_MUIFTPR      (volatile u32 *)IOP310_REG_ADDR(0x00001364)
+#define IOP310_MUIPHPR      (volatile u32 *)IOP310_REG_ADDR(0x00001368)
+#define IOP310_MUIPTPR      (volatile u32 *)IOP310_REG_ADDR(0x0000136C)
+#define IOP310_MUOFHPR      (volatile u32 *)IOP310_REG_ADDR(0x00001370)
+#define IOP310_MUOFTPR      (volatile u32 *)IOP310_REG_ADDR(0x00001374)
+#define IOP310_MUOPHPR      (volatile u32 *)IOP310_REG_ADDR(0x00001378)
+#define IOP310_MUOPTPR      (volatile u32 *)IOP310_REG_ADDR(0x0000137C)
+#define IOP310_MUIAR        (volatile u32 *)IOP310_REG_ADDR(0x00001380)
+/* DMA Controller 0x00001400 through 0x000014FF */
+#define IOP310_DMA0CCR     (volatile u32 *)IOP310_REG_ADDR(0x00001400)
+#define IOP310_DMA0CSR     (volatile u32 *)IOP310_REG_ADDR(0x00001404)
+/* Reserved 0x001408 through 0x00140B */
+#define IOP310_DMA0DAR     (volatile u32 *)IOP310_REG_ADDR(0x0000140C)
+#define IOP310_DMA0NDAR    (volatile u32 *)IOP310_REG_ADDR(0x00001410)
+#define IOP310_DMA0PADR    (volatile u32 *)IOP310_REG_ADDR(0x00001414)
+#define IOP310_DMA0PUADR   (volatile u32 *)IOP310_REG_ADDR(0x00001418)
+#define IOP310_DMA0LADR    (volatile u32 *)IOP310_REG_ADDR(0x0000141C)
+#define IOP310_DMA0BCR     (volatile u32 *)IOP310_REG_ADDR(0x00001420)
+#define IOP310_DMA0DCR     (volatile u32 *)IOP310_REG_ADDR(0x00001424)
+/* Reserved 0x00001428 through 0x0000143F */
+#define IOP310_DMA1CCR     (volatile u32 *)IOP310_REG_ADDR(0x00001440)
+#define IOP310_DMA1CSR     (volatile u32 *)IOP310_REG_ADDR(0x00001444)
+/* Reserved 0x00001448 through 0x0000144B */
+#define IOP310_DMA1DAR     (volatile u32 *)IOP310_REG_ADDR(0x0000144C)
+#define IOP310_DMA1NDAR    (volatile u32 *)IOP310_REG_ADDR(0x00001450)
+#define IOP310_DMA1PADR    (volatile u32 *)IOP310_REG_ADDR(0x00001454)
+#define IOP310_DMA1PUADR   (volatile u32 *)IOP310_REG_ADDR(0x00001458)
+#define IOP310_DMA1LADR    (volatile u32 *)IOP310_REG_ADDR(0x0000145C)
+#define IOP310_DMA1BCR     (volatile u32 *)IOP310_REG_ADDR(0x00001460)
+#define IOP310_DMA1DCR     (volatile u32 *)IOP310_REG_ADDR(0x00001464)
+/* Reserved 0x00001468 through 0x0000147F */
+#define IOP310_DMA2CCR     (volatile u32 *)IOP310_REG_ADDR(0x00001480)
+#define IOP310_DMA2CSR     (volatile u32 *)IOP310_REG_ADDR(0x00001484)
+/* Reserved 0x00001488 through 0x0000148B */
+#define IOP310_DMA2DAR     (volatile u32 *)IOP310_REG_ADDR(0x0000148C)
+#define IOP310_DMA2NDAR    (volatile u32 *)IOP310_REG_ADDR(0x00001490)
+#define IOP310_DMA2PADR    (volatile u32 *)IOP310_REG_ADDR(0x00001494)
+#define IOP310_DMA2PUADR   (volatile u32 *)IOP310_REG_ADDR(0x00001498)
+#define IOP310_DMA2LADR    (volatile u32 *)IOP310_REG_ADDR(0x0000149C)
+#define IOP310_DMA2BCR     (volatile u32 *)IOP310_REG_ADDR(0x000014A0)
+#define IOP310_DMA2DCR     (volatile u32 *)IOP310_REG_ADDR(0x000014A4)
+
+/* Memory controller 0x00001500 through 0x0015FF */
+
+/* core interface unit 0x00001640 - 0x0000167F */
+#define IOP310_CIUISR     (volatile u32 *)IOP310_REG_ADDR(0x00001644)
+
+/* PCI and Peripheral Interrupt Controller 0x00001700 - 0x0000171B */
+#define IOP310_IRQISR     (volatile u32 *)IOP310_REG_ADDR(0x00001700)
+#define IOP310_FIQ2ISR    (volatile u32 *)IOP310_REG_ADDR(0x00001704)
+#define IOP310_FIQ1ISR    (volatile u32 *)IOP310_REG_ADDR(0x00001708)
+#define IOP310_PDIDR      (volatile u32 *)IOP310_REG_ADDR(0x00001710)
+
+/* AAU registers. DJ 0x00001800 - 0x00001838 */
+#define IOP310_AAUACR    (volatile u32 *)IOP310_REG_ADDR(0x00001800)
+#define IOP310_AAUASR    (volatile u32 *)IOP310_REG_ADDR(0x00001804)
+#define IOP310_AAUADAR   (volatile u32 *)IOP310_REG_ADDR(0x00001808)
+#define IOP310_AAUANDAR  (volatile u32 *)IOP310_REG_ADDR(0x0000180C)
+#define IOP310_AAUSAR1   (volatile u32 *)IOP310_REG_ADDR(0x00001810)
+#define IOP310_AAUSAR2   (volatile u32 *)IOP310_REG_ADDR(0x00001814)
+#define IOP310_AAUSAR3   (volatile u32 *)IOP310_REG_ADDR(0x00001818)
+#define IOP310_AAUSAR4   (volatile u32 *)IOP310_REG_ADDR(0x0000181C)
+#define IOP310_AAUDAR    (volatile u32 *)IOP310_REG_ADDR(0x00001820)
+#define IOP310_AAUABCR   (volatile u32 *)IOP310_REG_ADDR(0x00001824)
+#define IOP310_AAUADCR   (volatile u32 *)IOP310_REG_ADDR(0x00001828)
+#define IOP310_AAUSAR5   (volatile u32 *)IOP310_REG_ADDR(0x0000182C)
+#define IOP310_AAUSAR6   (volatile u32 *)IOP310_REG_ADDR(0x00001830)
+#define IOP310_AAUSAR7   (volatile u32 *)IOP310_REG_ADDR(0x00001834)
+#define IOP310_AAUSAR8   (volatile u32 *)IOP310_REG_ADDR(0x00001838)
+
+#endif // _IOP310_HW_H_
diff --git a/include/asm-arm/arch-iop310/iq80310.h b/include/asm-arm/arch-iop310/iq80310.h
new file mode 100644
index 000000000000..85dbda84c6ba
--- /dev/null
+++ b/include/asm-arm/arch-iop310/iq80310.h
@@ -0,0 +1,30 @@
+/*
+ * linux/include/asm/arch-iop80310/iq80310.h
+ *
+ * Intel IQ-80310 evaluation board registers
+ */
+
+#ifndef _IQ80310_H_
+#define _IQ80310_H_
+
+#define IQ80310_RAMBASE      0xa0000000
+#define IQ80310_UART1        0xfe800000    /* UART #1 */
+#define IQ80310_UART2        0xfe810000    /* UART #2 */
+#define IQ80310_INT_STAT     0xfe820000    /* Interrupt (XINT3#) Status */
+#define IQ80310_BOARD_REV    0xfe830000    /* Board revision register */
+#define IQ80310_CPLD_REV     0xfe840000    /* CPLD revision register */
+#define IQ80310_7SEG_1       0xfe840000    /* 7-Segment MSB */
+#define IQ80310_7SEG_0       0xfe850000    /* 7-Segment LSB (WO) */
+#define IQ80310_PCI_INT_STAT 0xfe850000    /* PCI Interrupt  Status */
+#define IQ80310_INT_MASK     0xfe860000    /* Interrupt (XINT3#) Mask */
+#define IQ80310_BACKPLANE    0xfe870000    /* Backplane Detect */
+#define IQ80310_TIMER_LA0    0xfe880000    /* Timer LA0 */
+#define IQ80310_TIMER_LA1    0xfe890000    /* Timer LA1 */
+#define IQ80310_TIMER_LA2    0xfe8a0000    /* Timer LA2 */
+#define IQ80310_TIMER_LA3    0xfe8b0000    /* Timer LA3 */
+#define IQ80310_TIMER_EN     0xfe8c0000    /* Timer Enable */
+#define IQ80310_ROTARY_SW    0xfe8d0000    /* Rotary Switch */
+#define IQ80310_JTAG         0xfe8e0000    /* JTAG Port Access */
+#define IQ80310_BATT_STAT    0xfe8f0000    /* Battery Status */
+
+#endif	// _IQ80310_H_
diff --git a/include/asm-arm/arch-iop310/irq.h b/include/asm-arm/arch-iop310/irq.h
new file mode 100644
index 000000000000..33c0866c1275
--- /dev/null
+++ b/include/asm-arm/arch-iop310/irq.h
@@ -0,0 +1,13 @@
+/*
+ *  linux/include/asm-arm/arch-iop80310/irq.h
+ *
+ *  Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define fixup_irq(irq)  (irq)
+
+
diff --git a/include/asm-arm/arch-iop310/irqs.h b/include/asm-arm/arch-iop310/irqs.h
new file mode 100644
index 000000000000..6b671853c122
--- /dev/null
+++ b/include/asm-arm/arch-iop310/irqs.h
@@ -0,0 +1,80 @@
+/*
+ * linux/include/asm-arm/arch-iop310/irqs.h
+ *
+ * Author:	Nicolas Pitre
+ * Copyright:	(C) 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * 06/13/01: Added 80310 on-chip interrupt sources <dsaxena@mvista.com>
+ *
+ */
+
+
+/*
+ * XS80200 specific IRQs
+ */
+#define IRQ_XS80200_BCU		0	/* Bus Control Unit */
+#define IRQ_XS80200_PMU		1	/* Performance Monitoring Unit */
+#define IRQ_XS80200_EXTIRQ	2	/* external IRQ signal */
+#define IRQ_XS80200_EXTFIQ	3	/* external IRQ signal */
+
+#define NR_XS80200_IRQS		4
+
+#define XSCALE_PMU_IRQ		IRQ_XS80200_PMU
+
+/*
+ * IOP80310 chipset interrupts
+ */
+#define IOP310_IRQ_OFS		NR_XS80200_IRQS
+#define IOP310_IRQ(x)		(IOP310_IRQ_OFS + (x))
+
+/*
+ * On FIQ1ISR register
+ */
+#define IRQ_IOP310_DMA0		IOP310_IRQ(0)	/* DMA Channel 0 */
+#define IRQ_IOP310_DMA1		IOP310_IRQ(1)	/* DMA Channel 1 */
+#define IRQ_IOP310_DMA2		IOP310_IRQ(2)	/* DMA Channel 2 */
+#define IRQ_IOP310_PMON		IOP310_IRQ(3)	/* Bus performance Unit */
+#define IRQ_IOP310_AAU		IOP310_IRQ(4)	/* Application Accelator Unit */
+
+/*
+ * On FIQ2ISR register
+ */
+#define IRQ_IOP310_I2C		IOP310_IRQ(5)	/* I2C unit */
+#define IRQ_IOP310_MU		IOP310_IRQ(6)	/* messaging unit */
+
+#define NR_IOP310_IRQS		(IOP310_IRQ(6) + 1)
+
+#define NR_IRQS			NR_IOP310_IRQS
+
+
+/*
+ * Interrupts available on the Cyclone IQ80310 board
+ */
+#ifdef CONFIG_ARCH_IQ80310
+
+#define IQ80310_IRQ_OFS		NR_IOP310_IRQS
+#define IQ80310_IRQ(y)		((IQ80310_IRQ_OFS) + (y))
+
+#define IRQ_IQ80310_TIMER	IQ80310_IRQ(0)	/* Timer Interrupt */
+#define IRQ_IQ80310_I82559	IQ80310_IRQ(1)	/* I82559 Ethernet Interrupt */
+#define IRQ_IQ80310_UART1	IQ80310_IRQ(2)	/* UART1 Interrupt */
+#define IRQ_IQ80310_UART2	IQ80310_IRQ(3)	/* UART2 Interrupt */
+#define IRQ_IQ80310_INTD	IQ80310_IRQ(4)	/* PCI INTD */
+
+
+/*
+ * ONLY AVAILABLE ON REV F OR NEWER BOARDS!
+ */
+#define	IRQ_IQ80310_INTA	IQ80310_IRQ(5)	/* PCI INTA */
+#define	IRQ_IQ80310_INTB	IQ80310_IRQ(6)	/* PCI INTB */
+#define	IRQ_IQ80310_INTC	IQ80310_IRQ(7)	/* PCI INTC */
+
+#undef	NR_IRQS
+#define NR_IRQS			(IQ80310_IRQ(7) + 1)
+
+#endif // CONFIG_ARCH_IQ80310
+
diff --git a/include/asm-arm/arch-iop310/memory.h b/include/asm-arm/arch-iop310/memory.h
new file mode 100644
index 000000000000..64c078981659
--- /dev/null
+++ b/include/asm-arm/arch-iop310/memory.h
@@ -0,0 +1,58 @@
+/*
+ * linux/include/asm-arm/arch-iop80310/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+
+/*
+ * Task size: 3GB
+ */
+#define TASK_SIZE	(0xc0000000UL)
+#define TASK_SIZE_26	(0x04000000UL)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
+
+/*
+ * Page offset: 3GB
+ */
+#define PAGE_OFFSET	(0xc0000000UL)
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET	(0xa0000000UL)
+
+/*
+ * physical vs virtual ram conversion
+ */
+#define __virt_to_phys__is_a_macro
+#define __phys_to_virt__is_a_macro
+#define __virt_to_phys(x)	((x) - PAGE_OFFSET + PHYS_OFFSET)
+#define __phys_to_virt(x)	((x) - PHYS_OFFSET + PAGE_OFFSET)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *		address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *		to an address that the kernel can use.
+ */
+#define __virt_to_bus__is_a_macro
+#define __bus_to_virt__is_a_macro
+#define __virt_to_bus(x)	(((__virt_to_phys(x)) & ~(*IOP310_SIATVR)) | ((*IOP310_SIABAR) & 0xfffffff0))
+#define __bus_to_virt(x)    (__phys_to_virt(((x) & ~(*IOP310_SIALR)) | ( *IOP310_SIATVR)))
+
+#define PHYS_TO_NID(x)		0
+
+/* boot mem allocate global pointer for MU circular queues QBAR */
+#ifdef CONFIG_IOP310_MU
+extern void *mu_mem;
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-iop310/param.h b/include/asm-arm/arch-iop310/param.h
new file mode 100644
index 000000000000..dded3a1de4e9
--- /dev/null
+++ b/include/asm-arm/arch-iop310/param.h
@@ -0,0 +1,3 @@
+/*
+ * linux/include/asm-arm/arch-iop80310/param.h
+ */
diff --git a/include/asm-arm/arch-iop310/pmon.h b/include/asm-arm/arch-iop310/pmon.h
new file mode 100644
index 000000000000..7f93c1054c35
--- /dev/null
+++ b/include/asm-arm/arch-iop310/pmon.h
@@ -0,0 +1,50 @@
+/*
+ * Definitions for XScale 80312 PMON
+ * (C) 2001 Intel Corporation
+ * Author: Chen Chen(chen.chen@intel.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IOP310_PMON_H_
+#define _IOP310_PMON_H_
+
+/*
+ *  Different modes for Event Select Register for intel 80312
+ */
+
+#define IOP310_PMON_MODE0                0x00000000
+#define IOP310_PMON_MODE1                0x00000001
+#define IOP310_PMON_MODE2                0x00000002
+#define IOP310_PMON_MODE3                0x00000003
+#define IOP310_PMON_MODE4                0x00000004
+#define IOP310_PMON_MODE5                0x00000005
+#define IOP310_PMON_MODE6                0x00000006
+#define IOP310_PMON_MODE7                0x00000007
+
+typedef struct _iop310_pmon_result
+{
+	u32 timestamp;			/* Global Time Stamp Register */
+	u32 timestamp_overflow;		/* Time Stamp overflow count */
+	u32 event_count[14];		/* Programmable Event Counter
+					   Registers 1-14 */
+	u32 event_overflow[14];		/* Overflow counter for PECR1-14 */
+} iop310_pmon_res_t;
+
+/* function prototypes */
+
+/* Claim IQ80312 PMON for usage */
+int iop310_pmon_claim(void);
+
+/* Start IQ80312 PMON */
+int iop310_pmon_start(int, int);
+
+/* Stop Performance Monitor Unit */
+int iop310_pmon_stop(iop310_pmon_res_t *);
+
+/* Release IQ80312 PMON */
+int iop310_pmon_release(int);
+
+#endif
diff --git a/include/asm-arm/arch-iop310/serial.h b/include/asm-arm/arch-iop310/serial.h
new file mode 100644
index 000000000000..b25a5e5e9517
--- /dev/null
+++ b/include/asm-arm/arch-iop310/serial.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-arm/arch-iop310/serial.h
+ */
+
+
+/*
+ * This assumes you have a 1.8432 MHz clock for your UART.
+ *
+ * It'd be nice if someone built a serial card with a 24.576 MHz
+ * clock, since the 16550A is capable of handling a top speed of 1.5
+ * megabits/second; but this requires the faster clock.
+ */
+#define BASE_BAUD ( 1843200 / 16 )
+
+/* Standard COM flags */
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+
+#ifdef CONFIG_ARCH_IQ80310
+
+#define IRQ_UART1	IRQ_IQ80310_UART1
+#define IRQ_UART2	IRQ_IQ80310_UART2
+
+#define RS_TABLE_SIZE 2
+
+#define STD_SERIAL_PORT_DEFNS			\
+       /* UART CLK      PORT        IRQ        FLAGS        */			\
+	{ 0, BASE_BAUD, 0xfe810000, IRQ_UART2, STD_COM_FLAGS },  /* ttyS0 */	\
+	{ 0, BASE_BAUD, 0xfe800000, IRQ_UART1, STD_COM_FLAGS }  /* ttyS1 */
+
+#endif // CONFIG_ARCH_IQ80310
+
+
+#define EXTRA_SERIAL_PORT_DEFNS
+
diff --git a/include/asm-arm/arch-iop310/system.h b/include/asm-arm/arch-iop310/system.h
new file mode 100644
index 000000000000..c5ba7427a5af
--- /dev/null
+++ b/include/asm-arm/arch-iop310/system.h
@@ -0,0 +1,30 @@
+/*
+ * linux/include/asm-arm/arch-iop80310/system.h
+ *
+ *  Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+static inline void arch_idle(void)
+{
+	if (!hlt_counter)
+	{
+		cpu_do_idle(0);
+	}
+}
+
+
+static inline void arch_reset(char mode)
+{
+	if ( 1 && mode == 's') {
+		/* Jump into ROM at address 0 */
+		cpu_reset(0);
+	} else {
+		/* No on-chip reset capability */
+		cpu_reset(0);
+	}
+}
+
diff --git a/include/asm-arm/arch-iop310/time.h b/include/asm-arm/arch-iop310/time.h
new file mode 100644
index 000000000000..b58ac84f954e
--- /dev/null
+++ b/include/asm-arm/arch-iop310/time.h
@@ -0,0 +1,12 @@
+/*
+ * linux/include/asm-arm/arch-iop80310/time.h
+ *
+ * Author:  Nicolas Pitre
+ * Copyright:   (C) 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
diff --git a/include/asm-arm/arch-iop310/timex.h b/include/asm-arm/arch-iop310/timex.h
new file mode 100644
index 000000000000..8a085715ad07
--- /dev/null
+++ b/include/asm-arm/arch-iop310/timex.h
@@ -0,0 +1,23 @@
+/*
+ * linux/include/asm-arm/arch-iop80310/timex.h
+ *
+ * IOP310 architecture timex specifications
+ */
+
+
+
+#ifdef CONFIG_ARCH_IQ80310
+
+#ifndef CONFIG_XSCALE_PMU_TIMER
+/* This is for the on-board timer */
+#define CLOCK_TICK_RATE 33000000 /* Underlying HZ */
+#else
+/* This is for the underlying xs80200 PMU clock. We run the core @ 733MHz */
+#define CLOCK_TICK_RATE	733000000
+#endif
+
+#else
+
+#error "No IOP310 timex information for this architecture"
+
+#endif
diff --git a/include/asm-arm/arch-iop310/uncompress.h b/include/asm-arm/arch-iop310/uncompress.h
new file mode 100644
index 000000000000..40300833cdfb
--- /dev/null
+++ b/include/asm-arm/arch-iop310/uncompress.h
@@ -0,0 +1,33 @@
+/*
+ *  linux/include/asm-arm/arch-iop80310/uncompress.h
+ */
+
+#ifdef CONFIG_ARCH_IQ80310
+#define UART1_BASE    ((volatile unsigned char *)0xfe800000)
+#define UART2_BASE    ((volatile unsigned char *)0xfe810000)
+#endif
+
+static __inline__ void putc(char c)
+{
+	while ((UART2_BASE[5] & 0x60) != 0x60);
+	UART2_BASE[0] = c;
+}
+
+/*
+ * This does not append a newline
+ */
+static void puts(const char *s)
+{
+	while (*s) {
+		putc(*s);
+		if (*s == '\n')
+			putc('\r');
+		s++;
+	}
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop310/vmalloc.h b/include/asm-arm/arch-iop310/vmalloc.h
new file mode 100644
index 000000000000..07c8ee703750
--- /dev/null
+++ b/include/asm-arm/arch-iop310/vmalloc.h
@@ -0,0 +1,16 @@
+/*
+ * linux/include/asm-arm/arch-iop310/vmalloc.h
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET	  (8*1024*1024)
+#define VMALLOC_START	  (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       (0xe8000000)
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
index 50762b011d2d..91dfdf3cce59 100644
--- a/include/asm-arm/arch-l7200/io.h
+++ b/include/asm-arm/arch-l7200/io.h
@@ -73,6 +73,4 @@ static inline void __arch_putw(unsigned int value, unsigned long a)
 #define outw(v,p)		outw_t(v,p)
 #define outl(v,p)		outl_t(v,p)
 
-#define __arch_ioremap		__ioremap
-
 #endif
diff --git a/include/asm-arm/arch-l7200/irq.h b/include/asm-arm/arch-l7200/irq.h
index 7763e2150e18..c605a8c28698 100644
--- a/include/asm-arm/arch-l7200/irq.h
+++ b/include/asm-arm/arch-l7200/irq.h
@@ -9,60 +9,4 @@
  *   04-15-2000 RS      Made dependent on hardware.h
  *   05-05-2000 SJH     Complete rewrite
  */
-
-#include <asm/arch/hardware.h>
-
-/*
- * IRQ base register
- */
-#define	IRQ_BASE	(IO_BASE_2 + 0x1000)
-
-/* 
- * Normal IRQ registers
- */
-#define IRQ_STATUS	(*(volatile unsigned long *) (IRQ_BASE + 0x000))
-#define IRQ_RAWSTATUS	(*(volatile unsigned long *) (IRQ_BASE + 0x004))
-#define IRQ_ENABLE	(*(volatile unsigned long *) (IRQ_BASE + 0x008))
-#define IRQ_ENABLECLEAR	(*(volatile unsigned long *) (IRQ_BASE + 0x00c))
-#define IRQ_SOFT	(*(volatile unsigned long *) (IRQ_BASE + 0x010))
-#define IRQ_SOURCESEL	(*(volatile unsigned long *) (IRQ_BASE + 0x018))
-
-/* 
- * Fast IRQ registers
- */
-#define FIQ_STATUS	(*(volatile unsigned long *) (IRQ_BASE + 0x100))
-#define FIQ_RAWSTATUS	(*(volatile unsigned long *) (IRQ_BASE + 0x104))
-#define FIQ_ENABLE	(*(volatile unsigned long *) (IRQ_BASE + 0x108))
-#define FIQ_ENABLECLEAR	(*(volatile unsigned long *) (IRQ_BASE + 0x10c))
-#define FIQ_SOFT	(*(volatile unsigned long *) (IRQ_BASE + 0x110))
-#define FIQ_SOURCESEL	(*(volatile unsigned long *) (IRQ_BASE + 0x118))
-
 #define fixup_irq(x) (x)
-
-static void l7200_mask_irq(unsigned int irq)
-{
-	IRQ_ENABLECLEAR = 1 << irq;
-}
-
-static void l7200_unmask_irq(unsigned int irq)
-{
-	IRQ_ENABLE = 1 << irq;
-}
- 
-static __inline__ void irq_init_irq(void)
-{
-	int irq;
-
-	IRQ_ENABLECLEAR = 0xffffffff;	/* clear all interrupt enables */
-	FIQ_ENABLECLEAR = 0xffffffff;	/* clear all fast interrupt enables */
-
-	for (irq = 0; irq < NR_IRQS; irq++) {
-		irq_desc[irq].valid	= 1;
-		irq_desc[irq].probe_ok	= 1;
-		irq_desc[irq].mask_ack	= l7200_mask_irq;
-		irq_desc[irq].mask	= l7200_mask_irq;
-		irq_desc[irq].unmask	= l7200_unmask_irq;
-	}
-
-	init_FIQ();
-}
diff --git a/include/asm-arm/arch-l7200/keyboard.h b/include/asm-arm/arch-l7200/keyboard.h
index 5e41f270c051..6628bd38181b 100644
--- a/include/asm-arm/arch-l7200/keyboard.h
+++ b/include/asm-arm/arch-l7200/keyboard.h
@@ -17,6 +17,8 @@
 
 #include <asm/irq.h>
 
+#error This needs fixing --rmk
+
 /*
  * Layout of L7200 keyboard registers
  */
diff --git a/include/asm-arm/arch-l7200/time.h b/include/asm-arm/arch-l7200/time.h
index 6806aa7c42df..27a872c63f01 100644
--- a/include/asm-arm/arch-l7200/time.h
+++ b/include/asm-arm/arch-l7200/time.h
@@ -52,7 +52,7 @@ static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 /*
  * Set up RTC timer interrupt, and return the current time in seconds.
  */
-static inline void setup_timer(void)
+void __init time_init(void)
 {
 	RTC_RTCC = 0;				/* Clear interrupt */
 
diff --git a/include/asm-arm/arch-nexuspci/io.h b/include/asm-arm/arch-nexuspci/io.h
index 20a360744b2b..8afa61e6acba 100644
--- a/include/asm-arm/arch-nexuspci/io.h
+++ b/include/asm-arm/arch-nexuspci/io.h
@@ -37,12 +37,6 @@ static inline unsigned long ___mem_isa(unsigned long a)
 #endif
 
 /*
- * Generic virtual read/write
- */
-#define __arch_getw(a)		(*(volatile unsigned short *)(a))
-#define __arch_putw(v,a)	(*(volatile unsigned short *)(a) = (v))
-
-/*
  * ioremap support - validate a PCI memory address,
  * and convert a PCI memory address to a physical
  * address for the page tables.
@@ -51,4 +45,15 @@ static inline unsigned long ___mem_isa(unsigned long a)
 	((iomem) < 0x80000000 && (iomem) + (sz) <= 0x80000000)
 #define iomem_to_phys(iomem)	((iomem) + PLX_MEM_START)
 
+#define __arch_ioremap(off,sz,nocache)				\
+ ({								\
+	unsigned long _off = (off), _size = (sz);		\
+	void *_ret = (void *)0;					\
+	if (iomem_valid_addr(_off, _size))			\
+		_ret = __ioremap(iomem_to_phys(_off),_size,0);	\
+	_ret;							\
+ })
+
+#define __arch_iounmap __iounmap
+
 #endif
diff --git a/include/asm-arm/arch-nexuspci/irq.h b/include/asm-arm/arch-nexuspci/irq.h
index 292ed47b8948..4690e88438bb 100644
--- a/include/asm-arm/arch-nexuspci/irq.h
+++ b/include/asm-arm/arch-nexuspci/irq.h
@@ -10,60 +10,5 @@
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
-
-#include <asm/io.h>
-
 #define fixup_irq(x) (x)
 
-extern unsigned long soft_irq_mask;
-
-static const unsigned char irq_cmd[] =
-{
-	INTCONT_IRQ_DUART,
-	INTCONT_IRQ_PLX,
-	INTCONT_IRQ_D,
-	INTCONT_IRQ_C,
-	INTCONT_IRQ_B,
-	INTCONT_IRQ_A,
-	INTCONT_IRQ_SYSERR
-};
-
-static void ftvpci_mask_irq(unsigned int irq)
-{
-	__raw_writel(irq_cmd[irq], INTCONT_BASE);
-	soft_irq_mask &= ~(1<<irq);
-}
-
-static void ftvpci_unmask_irq(unsigned int irq)
-{
-	soft_irq_mask |= (1<<irq);
-	__raw_writel(irq_cmd[irq] | 1, INTCONT_BASE);
-}
- 
-static __inline__ void irq_init_irq(void)
-{
-	unsigned int i;
-
-	/* Mask all FIQs */
-	__raw_writel(INTCONT_FIQ_PLX, INTCONT_BASE);
-	__raw_writel(INTCONT_FIQ_D, INTCONT_BASE);
-	__raw_writel(INTCONT_FIQ_C, INTCONT_BASE);
-	__raw_writel(INTCONT_FIQ_B, INTCONT_BASE);
-	__raw_writel(INTCONT_FIQ_A, INTCONT_BASE);
-	__raw_writel(INTCONT_FIQ_SYSERR, INTCONT_BASE);
-
-	/* Disable all interrupts initially. */
-	for (i = 0; i < NR_IRQS; i++) {
-		if (i >= FIRST_IRQ && i <= LAST_IRQ) {
-			irq_desc[i].valid	= 1;
-			irq_desc[i].probe_ok	= 1;
-			irq_desc[i].mask_ack	= ftvpci_mask_irq;
-			irq_desc[i].mask	= ftvpci_mask_irq;
-			irq_desc[i].unmask	= ftvpci_unmask_irq;
-			ftvpci_mask_irq(i);
-		} else {
-			irq_desc[i].valid	= 0;
-			irq_desc[i].probe_ok	= 0;
-		}	
-	}		
-}
diff --git a/include/asm-arm/arch-nexuspci/time.h b/include/asm-arm/arch-nexuspci/time.h
index 19eae054f184..ba453c17637e 100644
--- a/include/asm-arm/arch-nexuspci/time.h
+++ b/include/asm-arm/arch-nexuspci/time.h
@@ -43,7 +43,7 @@ static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 	do_timer(regs);	
 }
 
-static inline void setup_timer(void)
+void __init time_init(void)
 {
 	int tick = 3686400 / 16 / 2 / 100;
 
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
index 19def7bfff6b..cb39453f5c9f 100644
--- a/include/asm-arm/arch-rpc/io.h
+++ b/include/asm-arm/arch-rpc/io.h
@@ -241,4 +241,10 @@ DECLARE_IO(int,l,"")
 /* the following macro is depreciated */
 #define ioaddr(port)			__ioaddr((port))
 
+#define insb(p,d,l)	__raw_readsb(__ioaddr(p),d,l)
+#define insw(p,d,l)	__raw_readsw(__ioaddr(p),d,l)
+
+#define outsb(p,d,l)	__raw_writesb(__ioaddr(p),d,l)
+#define outsw(p,d,l)	__raw_writesw(__ioaddr(p),d,l)
+
 #endif
diff --git a/include/asm-arm/arch-rpc/irq.h b/include/asm-arm/arch-rpc/irq.h
index 93c2ffa7f8ed..4446afbb29a4 100644
--- a/include/asm-arm/arch-rpc/irq.h
+++ b/include/asm-arm/arch-rpc/irq.h
@@ -11,142 +11,4 @@
  *   10-10-1996	RMK	Brought up to date with arch-sa110eval
  *   22-08-1998	RMK	Restructured IRQ routines
  */
-#include <asm/hardware/iomd.h>
-#include <asm/io.h>
-
 #define fixup_irq(x) (x)
-
-static void rpc_mask_irq_ack_a(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << irq;
-	val = iomd_readb(IOMD_IRQMASKA);
-	iomd_writeb(val & ~mask, IOMD_IRQMASKA);
-	iomd_writeb(mask, IOMD_IRQCLRA);
-}
-
-static void rpc_mask_irq_a(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << irq;
-	val = iomd_readb(IOMD_IRQMASKA);
-	iomd_writeb(val & ~mask, IOMD_IRQMASKA);
-}
-
-static void rpc_unmask_irq_a(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << irq;
-	val = iomd_readb(IOMD_IRQMASKA);
-	iomd_writeb(val | mask, IOMD_IRQMASKA);
-}
-
-static void rpc_mask_irq_b(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_IRQMASKB);
-	iomd_writeb(val & ~mask, IOMD_IRQMASKB);
-}
-
-static void rpc_unmask_irq_b(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_IRQMASKB);
-	iomd_writeb(val | mask, IOMD_IRQMASKB);
-}
-
-static void rpc_mask_irq_dma(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_DMAMASK);
-	iomd_writeb(val & ~mask, IOMD_DMAMASK);
-}
-
-static void rpc_unmask_irq_dma(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_DMAMASK);
-	iomd_writeb(val | mask, IOMD_DMAMASK);
-}
-
-static void rpc_mask_irq_fiq(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_FIQMASK);
-	iomd_writeb(val & ~mask, IOMD_FIQMASK);
-}
-
-static void rpc_unmask_irq_fiq(unsigned int irq)
-{
-	unsigned int val, mask;
-
-	mask = 1 << (irq & 7);
-	val = iomd_readb(IOMD_FIQMASK);
-	iomd_writeb(val | mask, IOMD_FIQMASK);
-}
-
-static __inline__ void irq_init_irq(void)
-{
-	int irq;
-
-	iomd_writeb(0, IOMD_IRQMASKA);
-	iomd_writeb(0, IOMD_IRQMASKB);
-	iomd_writeb(0, IOMD_FIQMASK);
-	iomd_writeb(0, IOMD_DMAMASK);
-
-	for (irq = 0; irq < NR_IRQS; irq++) {
-		switch (irq) {
-		case 0 ... 6:
-			irq_desc[irq].probe_ok = 1;
-		case 7:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = rpc_mask_irq_ack_a;
-			irq_desc[irq].mask     = rpc_mask_irq_a;
-			irq_desc[irq].unmask   = rpc_unmask_irq_a;
-			break;
-
-		case 9 ... 15:
-			irq_desc[irq].probe_ok = 1;
-		case 8:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = rpc_mask_irq_b;
-			irq_desc[irq].mask     = rpc_mask_irq_b;
-			irq_desc[irq].unmask   = rpc_unmask_irq_b;
-			break;
-
-		case 16 ... 19:
-		case 21:
-			irq_desc[irq].noautoenable = 1;
-		case 20:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = rpc_mask_irq_dma;
-			irq_desc[irq].mask     = rpc_mask_irq_dma;
-			irq_desc[irq].unmask   = rpc_unmask_irq_dma;
-			break;
-
-		case 64 ... 71:
-			irq_desc[irq].valid    = 1;
-			irq_desc[irq].mask_ack = rpc_mask_irq_fiq;
-			irq_desc[irq].mask     = rpc_mask_irq_fiq;
-			irq_desc[irq].unmask   = rpc_unmask_irq_fiq;
-			break;
-		}
-	}
-
-	irq_desc[IRQ_KEYBOARDTX].noautoenable = 1;
-
-	init_FIQ();
-}
diff --git a/include/asm-arm/arch-rpc/time.h b/include/asm-arm/arch-rpc/time.h
index e564892a28eb..4fa255bc6fc7 100644
--- a/include/asm-arm/arch-rpc/time.h
+++ b/include/asm-arm/arch-rpc/time.h
@@ -24,7 +24,7 @@ static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 /*
  * Set up timer interrupt.
  */
-static inline void setup_timer(void)
+void __init time_init(void)
 {
 	ioctime_init();
 
diff --git a/include/asm-arm/arch-sa1100/SA-1111.h b/include/asm-arm/arch-sa1100/SA-1111.h
index d25b59b560e6..c38f60915cb6 100644
--- a/include/asm-arm/arch-sa1100/SA-1111.h
+++ b/include/asm-arm/arch-sa1100/SA-1111.h
@@ -1,647 +1,5 @@
 /*
- * linux/include/asm/arch/SA-1111.h
- *
- * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
- *
- * This file contains definitions for the SA-1111 Companion Chip.
- * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
- *
+ * Moved to new location
  */
-
-#ifndef _ASM_ARCH_SA1111
-#define _ASM_ARCH_SA1111
-
-#include <asm/arch/bitfield.h>
-
-/*
- * Macro that calculates real address for registers in the SA-1111
- */
-
-#define _SA1111( x )    ((x) + SA1111_BASE)
-
-/*
- * 26 bits of the SA-1110 address bus are available to the SA-1111.
- * Use these when feeding target addresses to the DMA engines.
- */
-
-#define SA1111_ADDR_WIDTH	(26)
-#define SA1111_ADDR_MASK	((1<<SA1111_ADDR_WIDTH)-1)
-#define SA1111_DMA_ADDR(x)	((x)&SA1111_ADDR_MASK)
-
-/*
- * Don't ask the (SAC) DMA engines to move less than this amount.
- */
-
-#define SA1111_SAC_DMA_MIN_XFER	(0x800)
-
-/*
- * SA1111 register definitions.
- */
-#define __CCREG(x)	__REGP(SA1111_VBASE + (x))
-
-/* System Bus Interface (SBI)
- *
- * Registers
- *    SKCR	Control Register
- *    SMCR	Shared Memory Controller Register
- *    SKID	ID Register
- */
-
-#define _SBI_SKCR	_SA1111(0x0000)
-#define _SBI_SMCR	_SA1111(0x0004)
-#define _SBI_SKID	_SA1111(0x0008)
-
-#if LANGUAGE == C
-
-#define SBI_SKCR	__CCREG(0x0000)
-#define SBI_SMCR	__CCREG(0x0004)
-#define SBI_SKID	__CCREG(0x0008)
-
-#endif  /* LANGUAGE == C */
-
-#define SKCR_PLL_BYPASS	(1<<0)
-#define SKCR_RCLKEN	(1<<1)
-#define SKCR_SLEEP	(1<<2)
-#define SKCR_DOZE	(1<<3)
-#define SKCR_VCO_OFF	(1<<4)
-#define SKCR_SCANTSTEN	(1<<5)
-#define SKCR_CLKTSTEN	(1<<6)
-#define SKCR_RDYEN	(1<<7)
-#define SKCR_SELAC	(1<<8)
-#define SKCR_OPPC	(1<<9)
-#define SKCR_PLLTSTEN	(1<<10)
-#define SKCR_USBIOTSTEN	(1<<11)
-/*
- * Don't believe the specs!  Take them, throw them outside.  Leave them
- * there for a week.  Spit on them.  Walk on them.  Stamp on them.
- * Pour gasoline over them and finally burn them.  Now think about coding.
- *  - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
- *  - The Feb 2001 errata (278260-010) says that the previous errata
- *    (278260-009) is wrong, and its bit actually 12, fixed in spec
- *    278242-003.
- *  - The SA1111 manual (278242) says bit 12, but 0 to enable.
- *  - Reality is bit 13, 1 to enable.
- *      -- rmk
- */
-#define SKCR_OE_EN	(1<<13)
-
-#define SMCR_DTIM	(1<<0)
-#define SMCR_MBGE	(1<<1)
-#define SMCR_DRAC_0	(1<<2)
-#define SMCR_DRAC_1	(1<<3)
-#define SMCR_DRAC_2	(1<<4)
-#define SMCR_DRAC	Fld(3, 2)
-#define SMCR_CLAT	(1<<5)
-
-#define SKID_SIREV_MASK	(0x000000f0)
-#define SKID_MTREV_MASK (0x0000000f)
-#define SKID_ID_MASK	(0xffffff00)
-#define SKID_SA1111_ID	(0x690cc200)
-
-/*
- * System Controller
- *
- * Registers
- *    SKPCR	Power Control Register
- *    SKCDR	Clock Divider Register
- *    SKAUD	Audio Clock Divider Register
- *    SKPMC	PS/2 Mouse Clock Divider Register
- *    SKPTC	PS/2 Track Pad Clock Divider Register
- *    SKPEN0	PWM0 Enable Register
- *    SKPWM0	PWM0 Clock Register
- *    SKPEN1	PWM1 Enable Register
- *    SKPWM1	PWM1 Clock Register
- */
-
-#define _SKPCR		_SA1111(0x0200)
-#define _SKCDR		_SA1111(0x0204)
-#define _SKAUD		_SA1111(0x0208)
-#define _SKPMC		_SA1111(0x020c)
-#define _SKPTC		_SA1111(0x0210)
-#define _SKPEN0		_SA1111(0x0214)
-#define _SKPWM0		_SA1111(0x0218)
-#define _SKPEN1		_SA1111(0x021c)
-#define _SKPWM1		_SA1111(0x0220)
-
-#if LANGUAGE == C
-
-#define SKPCR		__CCREG(0x0200)
-#define SKCDR		__CCREG(0x0204)
-#define SKAUD		__CCREG(0x0208)
-#define SKPMC		__CCREG(0x020c)
-#define SKPTC		__CCREG(0x0210)
-#define SKPEN0		__CCREG(0x0214)
-#define SKPWM0		__CCREG(0x0218)
-#define SKPEN1		__CCREG(0x021c)
-#define SKPWM1		__CCREG(0x0220)
-
-#endif  /* LANGUAGE == C */
-
-#define SKPCR_UCLKEN	(1<<0)
-#define SKPCR_ACCLKEN	(1<<1)
-#define SKPCR_I2SCLKEN	(1<<2)
-#define SKPCR_L3CLKEN	(1<<3)
-#define SKPCR_SCLKEN	(1<<4)
-#define SKPCR_PMCLKEN	(1<<5)
-#define SKPCR_PTCLKEN	(1<<6)
-#define SKPCR_DCLKEN	(1<<7)
-#define SKPCR_PWMCLKEN	(1<<8)
-
-/*
- * USB Host controller
- */
-#define _USB_OHCI_OP_BASE	_SA1111( 0x400 )
-#define _USB_STATUS		_SA1111( 0x518 )
-#define _USB_RESET		_SA1111( 0x51c )
-#define _USB_INTERRUPTEST	_SA1111( 0x520 )
-
-#define _USB_EXTENT		(_USB_INTERRUPTEST - _USB_OHCI_OP_BASE + 4)
-
-#if LANGUAGE == C
-
-#define USB_OHCI_OP_BASE	__CCREG(0x0400)
-#define USB_STATUS		__CCREG(0x0518)
-#define USB_RESET		__CCREG(0x051c)
-#define USB_INTERRUPTEST	__CCReG(0x0520)
-
-#endif  /* LANGUAGE == C */
-
-#define USB_RESET_FORCEIFRESET	(1 << 0)
-#define USB_RESET_FORCEHCRESET	(1 << 1)
-#define USB_RESET_CLKGENRESET	(1 << 2)
-#define USB_RESET_SIMSCALEDOWN	(1 << 3)
-#define USB_RESET_USBINTTEST	(1 << 4)
-#define USB_RESET_SLEEPSTBYEN	(1 << 5)
-#define USB_RESET_PWRSENSELOW	(1 << 6)
-#define USB_RESET_PWRCTRLLOW	(1 << 7)
-
-/*
- * Serial Audio Controller
- *
- * Registers
- *    SACR0             Serial Audio Common Control Register
- *    SACR1             Serial Audio Alternate Mode (I2C/MSB) Control Register
- *    SACR2             Serial Audio AC-link Control Register
- *    SASR0             Serial Audio I2S/MSB Interface & FIFO Status Register
- *    SASR1             Serial Audio AC-link Interface & FIFO Status Register
- *    SASCR             Serial Audio Status Clear Register
- *    L3_CAR            L3 Control Bus Address Register
- *    L3_CDR            L3 Control Bus Data Register
- *    ACCAR             AC-link Command Address Register
- *    ACCDR             AC-link Command Data Register
- *    ACSAR             AC-link Status Address Register
- *    ACSDR             AC-link Status Data Register
- *    SADTCS            Serial Audio DMA Transmit Control/Status Register
- *    SADTSA            Serial Audio DMA Transmit Buffer Start Address A
- *    SADTCA            Serial Audio DMA Transmit Buffer Count Register A
- *    SADTSB            Serial Audio DMA Transmit Buffer Start Address B
- *    SADTCB            Serial Audio DMA Transmit Buffer Count Register B
- *    SADRCS            Serial Audio DMA Receive Control/Status Register
- *    SADRSA            Serial Audio DMA Receive Buffer Start Address A
- *    SADRCA            Serial Audio DMA Receive Buffer Count Register A
- *    SADRSB            Serial Audio DMA Receive Buffer Start Address B
- *    SADRCB            Serial Audio DMA Receive Buffer Count Register B
- *    SAITR             Serial Audio Interrupt Test Register
- *    SADR              Serial Audio Data Register (16 x 32-bit)
- */
-
-#define _SACR0          _SA1111( 0x0600 )
-#define _SACR1          _SA1111( 0x0604 )
-#define _SACR2          _SA1111( 0x0608 )
-#define _SASR0          _SA1111( 0x060c )
-#define _SASR1          _SA1111( 0x0610 )
-#define _SASCR          _SA1111( 0x0618 )
-#define _L3_CAR         _SA1111( 0x061c )
-#define _L3_CDR         _SA1111( 0x0620 )
-#define _ACCAR          _SA1111( 0x0624 )
-#define _ACCDR          _SA1111( 0x0628 )
-#define _ACSAR          _SA1111( 0x062c )
-#define _ACSDR          _SA1111( 0x0630 )
-#define _SADTCS         _SA1111( 0x0634 )
-#define _SADTSA         _SA1111( 0x0638 )
-#define _SADTCA         _SA1111( 0x063c )
-#define _SADTSB         _SA1111( 0x0640 )
-#define _SADTCB         _SA1111( 0x0644 )
-#define _SADRCS         _SA1111( 0x0648 )
-#define _SADRSA         _SA1111( 0x064c )
-#define _SADRCA         _SA1111( 0x0650 )
-#define _SADRSB         _SA1111( 0x0654 )
-#define _SADRCB         _SA1111( 0x0658 )
-#define _SAITR          _SA1111( 0x065c )
-#define _SADR           _SA1111( 0x0680 )
-
-#if LANGUAGE == C
-
-#define SACR0		__CCREG(0x0600)
-#define SACR1		__CCREG(0x0604)
-#define SACR2		__CCREG(0x0608)
-#define SASR0		__CCREG(0x060c)
-#define SASR1		__CCREG(0x0610)
-#define SASCR		__CCREG(0x0618)
-#define L3_CAR		__CCREG(0x061c)
-#define L3_CDR		__CCREG(0x0620)
-#define ACCAR		__CCREG(0x0624)
-#define ACCDR		__CCREG(0x0628)
-#define ACSAR		__CCREG(0x062c)
-#define ACSDR		__CCREG(0x0630)
-#define SADTCS		__CCREG(0x0634)
-#define SADTSA		__CCREG(0x0638)
-#define SADTCA		__CCREG(0x063c)
-#define SADTSB		__CCREG(0x0640)
-#define SADTCB		__CCREG(0x0644)
-#define SADRCS		__CCREG(0x0648)
-#define SADRSA		__CCREG(0x064c)
-#define SADRCA		__CCREG(0x0650)
-#define SADRSB		__CCREG(0x0654)
-#define SADRCB		__CCREG(0x0658)
-#define SAITR		__CCREG(0x065c)
-#define SADR		__CCREG(0x0680)
-
-#endif  /* LANGUAGE == C */
-
-#define SACR0_ENB	(1<<0)
-#define SACR0_BCKD	(1<<2)
-#define SACR0_RST	(1<<3)
-
-#define SACR1_AMSL	(1<<0)
-#define SACR1_L3EN	(1<<1)
-#define SACR1_L3MB	(1<<2)
-#define SACR1_DREC	(1<<3)
-#define SACR1_DRPL	(1<<4)
-#define SACR1_ENLBF	(1<<5)
-
-#define SACR2_TS3V	(1<<0)
-#define SACR2_TS4V	(1<<1)
-#define SACR2_WKUP	(1<<2)
-#define SACR2_DREC	(1<<3)
-#define SACR2_DRPL	(1<<4)
-#define SACR2_ENLBF	(1<<5)
-#define SACR2_RESET	(1<<6)
-
-#define SASR0_TNF	(1<<0)
-#define SASR0_RNE	(1<<1)
-#define SASR0_BSY	(1<<2)
-#define SASR0_TFS	(1<<3)
-#define SASR0_RFS	(1<<4)
-#define SASR0_TUR	(1<<5)
-#define SASR0_ROR	(1<<6)
-#define SASR0_L3WD	(1<<16)
-#define SASR0_L3RD	(1<<17)
-
-#define SASR1_TNF	(1<<0)
-#define SASR1_RNE	(1<<1)
-#define SASR1_BSY	(1<<2)
-#define SASR1_TFS	(1<<3)
-#define SASR1_RFS	(1<<4)
-#define SASR1_TUR	(1<<5)
-#define SASR1_ROR	(1<<6)
-#define SASR1_CADT	(1<<16)
-#define SASR1_SADR	(1<<17)
-#define SASR1_RSTO	(1<<18)
-#define SASR1_CLPM	(1<<19)
-#define SASR1_CRDY	(1<<20)
-#define SASR1_RS3V	(1<<21)
-#define SASR1_RS4V	(1<<22)
-
-#define SASCR_TUR	(1<<5)
-#define SASCR_ROR	(1<<6)
-#define SASCR_DTS	(1<<16)
-#define SASCR_RDD	(1<<17)
-#define SASCR_STO	(1<<18)
-
-#define SADTCS_TDEN	(1<<0)
-#define SADTCS_TDIE	(1<<1)
-#define SADTCS_TDBDA	(1<<3)
-#define SADTCS_TDSTA	(1<<4)
-#define SADTCS_TDBDB	(1<<5)
-#define SADTCS_TDSTB	(1<<6)
-#define SADTCS_TBIU	(1<<7)
-
-#define SADRCS_RDEN	(1<<0)
-#define SADRCS_RDIE	(1<<1)
-#define SADRCS_RDBDA	(1<<3)
-#define SADRCS_RDSTA	(1<<4)
-#define SADRCS_RDBDB	(1<<5)
-#define SADRCS_RDSTB	(1<<6)
-#define SADRCS_RBIU	(1<<7)
-
-#define SAD_CS_DEN	(1<<0)
-#define SAD_CS_DIE	(1<<1)	/* Not functional on metal 1 */
-#define SAD_CS_DBDA	(1<<3)	/* Not functional on metal 1 */
-#define SAD_CS_DSTA	(1<<4)
-#define SAD_CS_DBDB	(1<<5)	/* Not functional on metal 1 */
-#define SAD_CS_DSTB	(1<<6)
-#define SAD_CS_BIU	(1<<7)	/* Not functional on metal 1 */
-
-#define SAITR_TFS	(1<<0)
-#define SAITR_RFS	(1<<1)
-#define SAITR_TUR	(1<<2)
-#define SAITR_ROR	(1<<3)
-#define SAITR_CADT	(1<<4)
-#define SAITR_SADR	(1<<5)
-#define SAITR_RSTO	(1<<6)
-#define SAITR_TDBDA	(1<<8)
-#define SAITR_TDBDB	(1<<9)
-#define SAITR_RDBDA	(1<<10)
-#define SAITR_RDBDB	(1<<11)
-
-/*
- * General-Purpose I/O Interface
- *
- * Registers
- *    PA_DDR		GPIO Block A Data Direction
- *    PA_DRR/PA_DWR	GPIO Block A Data Value Register (read/write)
- *    PA_SDR		GPIO Block A Sleep Direction
- *    PA_SSR		GPIO Block A Sleep State
- *    PB_DDR		GPIO Block B Data Direction
- *    PB_DRR/PB_DWR	GPIO Block B Data Value Register (read/write)
- *    PB_SDR		GPIO Block B Sleep Direction
- *    PB_SSR		GPIO Block B Sleep State
- *    PC_DDR		GPIO Block C Data Direction
- *    PC_DRR/PC_DWR	GPIO Block C Data Value Register (read/write)
- *    PC_SDR		GPIO Block C Sleep Direction
- *    PC_SSR		GPIO Block C Sleep State
- */
-
-#define _PA_DDR		_SA1111( 0x1000 )
-#define _PA_DRR		_SA1111( 0x1004 )
-#define _PA_DWR		_SA1111( 0x1004 )
-#define _PA_SDR		_SA1111( 0x1008 )
-#define _PA_SSR		_SA1111( 0x100c )
-#define _PB_DDR		_SA1111( 0x1010 )
-#define _PB_DRR		_SA1111( 0x1014 )
-#define _PB_DWR		_SA1111( 0x1014 )
-#define _PB_SDR		_SA1111( 0x1018 )
-#define _PB_SSR		_SA1111( 0x101c )
-#define _PC_DDR		_SA1111( 0x1020 )
-#define _PC_DRR		_SA1111( 0x1024 )
-#define _PC_DWR		_SA1111( 0x1024 )
-#define _PC_SDR		_SA1111( 0x1028 )
-#define _PC_SSR		_SA1111( 0x102c )
-
-#if LANGUAGE == C
-
-#define PA_DDR		__CCREG(0x1000)
-#define PA_DRR		__CCREG(0x1004)
-#define PA_DWR		__CCREG(0x1004)
-#define PA_SDR		__CCREG(0x1008)
-#define PA_SSR		__CCREG(0x100c)
-#define PB_DDR		__CCREG(0x1010)
-#define PB_DRR		__CCREG(0x1014)
-#define PB_DWR		__CCREG(0x1014)
-#define PB_SDR		__CCREG(0x1018)
-#define PB_SSR		__CCREG(0x101c)
-#define PC_DDR		__CCREG(0x1020)
-#define PC_DRR		__CCREG(0x1024)
-#define PC_DWR		__CCREG(0x1024)
-#define PC_SDR		__CCREG(0x1028)
-#define PC_SSR		__CCREG(0x102c)
-
-#endif  /* LANGUAGE == C */
-
-/*
- * Interrupt Controller
- *
- * Registers
- *    INTTEST0		Test register 0
- *    INTTEST1		Test register 1
- *    INTEN0		Interrupt Enable register 0
- *    INTEN1		Interrupt Enable register 1
- *    INTPOL0		Interrupt Polarity selection 0
- *    INTPOL1		Interrupt Polarity selection 1
- *    INTTSTSEL		Interrupt source selection
- *    INTSTATCLR0	Interrupt Status/Clear 0
- *    INTSTATCLR1	Interrupt Status/Clear 1
- *    INTSET0		Interrupt source set 0
- *    INTSET1		Interrupt source set 1
- *    WAKE_EN0		Wake-up source enable 0
- *    WAKE_EN1		Wake-up source enable 1
- *    WAKE_POL0		Wake-up polarity selection 0
- *    WAKE_POL1		Wake-up polarity selection 1
- */
-
-#define _INTTEST0	_SA1111( 0x1600 )
-#define _INTTEST1	_SA1111( 0x1604 )
-#define _INTEN0		_SA1111( 0x1608 )
-#define _INTEN1		_SA1111( 0x160c )
-#define _INTPOL0	_SA1111( 0x1610 )
-#define _INTPOL1	_SA1111( 0x1614 )
-#define _INTTSTSEL	_SA1111( 0x1618 )
-#define _INTSTATCLR0	_SA1111( 0x161c )
-#define _INTSTATCLR1	_SA1111( 0x1620 )
-#define _INTSET0	_SA1111( 0x1624 )
-#define _INTSET1	_SA1111( 0x1628 )
-#define _WAKE_EN0	_SA1111( 0x162c )
-#define _WAKE_EN1	_SA1111( 0x1630 )
-#define _WAKE_POL0	_SA1111( 0x1634 )
-#define _WAKE_POL1	_SA1111( 0x1638 )
-
-#if LANGUAGE == C
-
-#define INTTEST0	__CCREG(0x1600)
-#define INTTEST1	__CCREG(0x1604)
-#define INTEN0		__CCREG(0x1608)
-#define INTEN1		__CCREG(0x160c)
-#define INTPOL0		__CCREG(0x1610)
-#define INTPOL1		__CCREG(0x1614)
-#define INTTSTSEL	__CCREG(0x1618)
-#define INTSTATCLR0	__CCREG(0x161c)
-#define INTSTATCLR1	__CCREG(0x1620)
-#define INTSET0		__CCREG(0x1624)
-#define INTSET1		__CCREG(0x1628)
-#define WAKE_EN0	__CCREG(0x162c)
-#define WAKE_EN1	__CCREG(0x1630)
-#define WAKE_POL0	__CCREG(0x1634)
-#define WAKE_POL1	__CCREG(0x1638)
-
-#endif  /* LANGUAGE == C */
-
-/*
- * PS/2 Trackpad and Mouse Interfaces
- *
- * Registers   (prefix kbd applies to trackpad interface, mse to mouse)
- *    KBDCR     Control Register
- *    KBDSTAT       Status Register
- *    KBDDATA       Transmit/Receive Data register
- *    KBDCLKDIV     Clock Division Register
- *    KBDPRECNT     Clock Precount Register
- *    KBDTEST1      Test register 1
- *    KBDTEST2      Test register 2
- *    KBDTEST3      Test register 3
- *    KBDTEST4      Test register 4
- *    MSECR
- *    MSESTAT
- *    MSEDATA
- *    MSECLKDIV
- *    MSEPRECNT
- *    MSETEST1
- *    MSETEST2
- *    MSETEST3
- *    MSETEST4
- *
- */
-
-#define _KBD( x )   _SA1111( 0x0A00 )
-#define _MSE( x )   _SA1111( 0x0C00 )
-
-#define _KBDCR	    _SA1111( 0x0A00 )
-#define _KBDSTAT    _SA1111( 0x0A04 )
-#define _KBDDATA    _SA1111( 0x0A08 )
-#define _KBDCLKDIV  _SA1111( 0x0A0C )
-#define _KBDPRECNT  _SA1111( 0x0A10 )
-#define _MSECR	    _SA1111( 0x0C00 )
-#define _MSESTAT    _SA1111( 0x0C04 )
-#define _MSEDATA    _SA1111( 0x0C08 )
-#define _MSECLKDIV  _SA1111( 0x0C0C )
-#define _MSEPRECNT  _SA1111( 0x0C10 )
-
-#if ( LANGUAGE == C )
-
-#define KBDCR		__CCREG(0x0a00)
-#define KBDSTAT		__CCREG(0x0a04)
-#define KBDDATA		__CCREG(0x0a08)
-#define KBDCLKDIV	__CCREG(0x0a0c)
-#define KBDPRECNT	__CCREG(0x0a10)
-#define MSECR		__CCREG(0x0c00)
-#define MSESTAT		__CCREG(0x0c04)
-#define MSEDATA		__CCREG(0x0c08)
-#define MSECLKDIV	__CCREG(0x0c0c)
-#define MSEPRECNT	__CCREG(0x0c10)
-
-#define KBDCR_ENA        0x08
-#define KBDCR_FKD        0x02
-#define KBDCR_FKC        0x01
-
-#define KBDSTAT_TXE      0x80
-#define KBDSTAT_TXB      0x40
-#define KBDSTAT_RXF      0x20
-#define KBDSTAT_RXB      0x10
-#define KBDSTAT_ENA      0x08
-#define KBDSTAT_RXP      0x04
-#define KBDSTAT_KBD      0x02
-#define KBDSTAT_KBC      0x01
-
-#define KBDCLKDIV_DivVal     Fld(4,0)
-
-#define MSECR_ENA        0x08
-#define MSECR_FKD        0x02
-#define MSECR_FKC        0x01
-
-#define MSESTAT_TXE      0x80
-#define MSESTAT_TXB      0x40
-#define MSESTAT_RXF      0x20
-#define MSESTAT_RXB      0x10
-#define MSESTAT_ENA      0x08
-#define MSESTAT_RXP      0x04
-#define MSESTAT_MSD      0x02
-#define MSESTAT_MSC      0x01
-
-#define MSECLKDIV_DivVal     Fld(4,0)
-
-#define KBDTEST1_CD      0x80
-#define KBDTEST1_RC1         0x40
-#define KBDTEST1_MC      0x20
-#define KBDTEST1_C       Fld(2,3)
-#define KBDTEST1_T2      0x40
-#define KBDTEST1_T1      0x20
-#define KBDTEST1_T0      0x10
-#define KBDTEST2_TICBnRES    0x08
-#define KBDTEST2_RKC         0x04
-#define KBDTEST2_RKD         0x02
-#define KBDTEST2_SEL         0x01
-#define KBDTEST3_ms_16       0x80
-#define KBDTEST3_us_64       0x40
-#define KBDTEST3_us_16       0x20
-#define KBDTEST3_DIV8        0x10
-#define KBDTEST3_DIn         0x08
-#define KBDTEST3_CIn         0x04
-#define KBDTEST3_KD      0x02
-#define KBDTEST3_KC      0x01
-#define KBDTEST4_BC12        0x80
-#define KBDTEST4_BC11        0x40
-#define KBDTEST4_TRES        0x20
-#define KBDTEST4_CLKOE       0x10
-#define KBDTEST4_CRES        0x08
-#define KBDTEST4_RXB         0x04
-#define KBDTEST4_TXB         0x02
-#define KBDTEST4_SRX         0x01
-
-#define MSETEST1_CD      0x80
-#define MSETEST1_RC1         0x40
-#define MSETEST1_MC      0x20
-#define MSETEST1_C       Fld(2,3)
-#define MSETEST1_T2      0x40
-#define MSETEST1_T1      0x20
-#define MSETEST1_T0      0x10
-#define MSETEST2_TICBnRES    0x08
-#define MSETEST2_RKC         0x04
-#define MSETEST2_RKD         0x02
-#define MSETEST2_SEL         0x01
-#define MSETEST3_ms_16       0x80
-#define MSETEST3_us_64       0x40
-#define MSETEST3_us_16       0x20
-#define MSETEST3_DIV8        0x10
-#define MSETEST3_DIn         0x08
-#define MSETEST3_CIn         0x04
-#define MSETEST3_KD      0x02
-#define MSETEST3_KC      0x01
-#define MSETEST4_BC12        0x80
-#define MSETEST4_BC11        0x40
-#define MSETEST4_TRES        0x20
-#define MSETEST4_CLKOE       0x10
-#define MSETEST4_CRES        0x08
-#define MSETEST4_RXB         0x04
-#define MSETEST4_TXB         0x02
-#define MSETEST4_SRX         0x01
-
-#endif  /* LANGUAGE == C */
-
-/*
- * PCMCIA Interface
- *
- * Registers
- *    PCSR	Status Register
- *    PCCR	Control Register
- *    PCSSR	Sleep State Register
- */
-
-#define _PCCR		_SA1111( 0x1800 )
-#define _PCSSR		_SA1111( 0x1804 )
-#define _PCSR		_SA1111( 0x1808 )
-
-#if LANGUAGE == C
-
-#define PCCR		__CCREG(0x1800)
-#define PCSSR		__CCREG(0x1804)
-#define PCSR		__CCREG(0x1808)
-
-#endif  /* LANGUAGE == C */
-
-#define PCSR_S0_READY	(1<<0)
-#define PCSR_S1_READY	(1<<1)
-#define PCSR_S0_DETECT	(1<<2)
-#define PCSR_S1_DETECT	(1<<3)
-#define PCSR_S0_VS1	(1<<4)
-#define PCSR_S0_VS2	(1<<5)
-#define PCSR_S1_VS1	(1<<6)
-#define PCSR_S1_VS2	(1<<7)
-#define PCSR_S0_WP	(1<<8)
-#define PCSR_S1_WP	(1<<9)
-#define PCSR_S0_BVD1	(1<<10)
-#define PCSR_S0_BVD2	(1<<11)
-#define PCSR_S1_BVD1	(1<<12)
-#define PCSR_S1_BVD2	(1<<13)
-
-#define PCCR_S0_RST	(1<<0)
-#define PCCR_S1_RST	(1<<1)
-#define PCCR_S0_FLT	(1<<2)
-#define PCCR_S1_FLT	(1<<3)
-#define PCCR_S0_PWAITEN	(1<<4)
-#define PCCR_S1_PWAITEN	(1<<5)
-#define PCCR_S0_PSE	(1<<6)
-#define PCCR_S1_PSE	(1<<7)
-
-#define PCSSR_S0_SLEEP	(1<<0)
-#define PCSSR_S1_SLEEP	(1<<1)
-
-#endif  /* _ASM_ARCH_SA1111 */
+#warning using old SA-1111.h - update to <asm/hardware/sa1111.h>
+#include <asm/hardware/sa1111.h>
diff --git a/include/asm-arm/arch-sa1100/assabet.h b/include/asm-arm/arch-sa1100/assabet.h
index 0292f71049ff..6d13df14a60a 100644
--- a/include/asm-arm/arch-sa1100/assabet.h
+++ b/include/asm-arm/arch-sa1100/assabet.h
@@ -29,19 +29,6 @@
 #define ASSABET_BCR_BASE  0xf1000000
 #define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE))
 
-#define ASSABET_BCR_DB1110 \
-	(ASSABET_BCR_SPK_OFF    | ASSABET_BCR_QMUTE     | \
-	 ASSABET_BCR_LED_GREEN  | ASSABET_BCR_LED_RED   | \
-	 ASSABET_BCR_RS232EN    | ASSABET_BCR_LCD_12RGB | \
-	 ASSABET_BCR_IRDA_MD0)
-
-#define ASSABET_BCR_DB1111 \
-	(ASSABET_BCR_SPK_OFF    | ASSABET_BCR_QMUTE     | \
-	 ASSABET_BCR_LED_GREEN  | ASSABET_BCR_LED_RED   | \
-	 ASSABET_BCR_RS232EN    | ASSABET_BCR_LCD_12RGB | \
-	 ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
-	 ASSABET_BCR_IRDA_MD0   | ASSABET_BCR_CF_RST)
-
 #define ASSABET_BCR_CF_PWR	(1<<0)	/* Compact Flash Power (1 = 3.3v, 0 = off) */
 #define ASSABET_BCR_CF_RST	(1<<1)	/* Compact Flash Reset (1 = power up reset) */
 #define ASSABET_BCR_GFX_RST	(1<<1)	/* Graphics Accelerator Reset (0 = hold reset) */
@@ -69,9 +56,15 @@
 #define ASSABET_BCR_SPK_OFF	(1<<23)	/* 1 = Speaker amplifier power off */
 
 extern unsigned long SCR_value;
-extern unsigned long BCR_value;
-#define ASSABET_BCR_set(x)	ASSABET_BCR = (BCR_value |= (x))
-#define ASSABET_BCR_clear(x)	ASSABET_BCR = (BCR_value &= ~(x))
+
+#ifdef CONFIG_SA1100_ASSABET
+extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
+#else
+#define ASSABET_BCR_frob(x)	do { } while (0)
+#endif
+
+#define ASSABET_BCR_set(x)	ASSABET_BCR_frob((x), (x))
+#define ASSABET_BCR_clear(x)	ASSABET_BCR_frob((x), 0)
 
 #define ASSABET_BSR_BASE	0xf1000000
 #define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE))
@@ -88,38 +81,26 @@ extern unsigned long BCR_value;
 
 /* GPIOs for which the generic definition doesn't say much */
 #define ASSABET_GPIO_RADIO_IRQ		GPIO_GPIO (14)	/* Radio interrupt request  */
-#define ASSABET_GPIO_L3_I2C_SDA		GPIO_GPIO (15)	/* L3 and SMB control ports */
 #define ASSABET_GPIO_PS_MODE_SYNC	GPIO_GPIO (16)	/* Power supply mode/sync   */
-#define ASSABET_GPIO_L3_MODE		GPIO_GPIO (17)	/* L3 mode signal with LED  */
-#define ASSABET_GPIO_L3_I2C_SCL		GPIO_GPIO (18)	/* L3 and I2C control ports */
 #define ASSABET_GPIO_STEREO_64FS_CLK	GPIO_GPIO (19)	/* SSP UDA1341 clock input  */
 #define ASSABET_GPIO_CF_IRQ		GPIO_GPIO (21)	/* CF IRQ   */
 #define ASSABET_GPIO_CF_CD		GPIO_GPIO (22)	/* CF CD */
-#define ASSABET_GPIO_UCB1300_IRQ	GPIO_GPIO (23)	/* UCB GPIO and touchscreen */
 #define ASSABET_GPIO_CF_BVD2		GPIO_GPIO (24)	/* CF BVD */
 #define ASSABET_GPIO_GFX_IRQ		GPIO_GPIO (24)	/* Graphics IRQ */
 #define ASSABET_GPIO_CF_BVD1		GPIO_GPIO (25)	/* CF BVD */
-#define ASSABET_GPIO_NEP_IRQ		GPIO_GPIO (25)	/* Neponset IRQ */
 #define ASSABET_GPIO_BATT_LOW		GPIO_GPIO (26)	/* Low battery */
 #define ASSABET_GPIO_RCLK		GPIO_GPIO (26)	/* CCLK/2  */
 
 #define ASSABET_IRQ_GPIO_CF_IRQ		IRQ_GPIO21
 #define ASSABET_IRQ_GPIO_CF_CD		IRQ_GPIO22
-#define ASSABET_IRQ_GPIO_UCB1300_IRQ	IRQ_GPIO23
 #define ASSABET_IRQ_GPIO_CF_BVD2	IRQ_GPIO24
 #define ASSABET_IRQ_GPIO_CF_BVD1	IRQ_GPIO25
-#define ASSABET_IRQ_GPIO_NEP_IRQ	IRQ_GPIO25
 
 
 /*
  * Neponset definitions: 
  */
 
-#define SA1111_BASE             (0x40000000)
-
-#define NEPONSET_ETHERNET_IRQ	MISC_IRQ0
-#define NEPONSET_USAR_IRQ	MISC_IRQ1
-
 #define NEPONSET_CPLD_BASE      (0x10000000)
 #define Nep_p2v( x )            ((x) - NEPONSET_CPLD_BASE + 0xf3000000)
 #define Nep_v2p( x )            ((x) - 0xf3000000 + NEPONSET_CPLD_BASE)
diff --git a/include/asm-arm/arch-sa1100/dma.h b/include/asm-arm/arch-sa1100/dma.h
index 471c41021d73..8927a3d26172 100644
--- a/include/asm-arm/arch-sa1100/dma.h
+++ b/include/asm-arm/arch-sa1100/dma.h
@@ -28,34 +28,16 @@
  */
 #define MAX_DMA_CHANNELS	0
 
-
 /*
  * The SA1100 has six internal DMA channels.
  */
-#define SA1100_DMA_CHANNELS     6
-
+#define SA1100_DMA_CHANNELS	6
 
 /*
- * The SA-1111 SAC has two DMA channels.
+ * Maximum physical DMA buffer size
  */
-#define SA1111_SAC_DMA_CHANNELS 2
-#define SA1111_SAC_XMT_CHANNEL  0
-#define SA1111_SAC_RCV_CHANNEL  1
-
-
-/*
- * The SA-1111 SAC channels will reside in the same index space as
- * the built-in SA-1100 channels, and will take on the next available
- * identifiers after the 1100.
- */
-#define SA1111_SAC_DMA_BASE     SA1100_DMA_CHANNELS
-
-#ifdef CONFIG_SA1111
-# define MAX_SA1100_DMA_CHANNELS (SA1100_DMA_CHANNELS + SA1111_SAC_DMA_CHANNELS)
-#else
-# define MAX_SA1100_DMA_CHANNELS SA1100_DMA_CHANNELS
-#endif
-
+#define MAX_DMA_SIZE		0x1fff
+#define CUT_DMA_SIZE		0x1000
 
 /*
  * All possible SA1100 devices a DMA channel can be attached to.
@@ -81,29 +63,72 @@ typedef enum {
 	DMA_Ser4SSPRd  = DDAR_Ser4SSPRd    /* Ser. port 4 SSP Read (16 bits) */
 } dma_device_t;
 
+typedef struct {
+	volatile u_long DDAR;
+	volatile u_long SetDCSR;
+	volatile u_long ClrDCSR;
+	volatile u_long RdDCSR;
+	volatile dma_addr_t DBSA;
+	volatile u_long DBTA;
+	volatile dma_addr_t DBSB;
+	volatile u_long DBTB;
+} dma_regs_t;
+
+typedef void (*dma_callback_t)(void *data);
+
+/*
+ * DMA function prototypes
+ */
+
+extern int sa1100_request_dma( dma_device_t device, const char *device_id,
+			       dma_callback_t callback, void *data,
+			       dma_regs_t **regs );
+extern void sa1100_free_dma( dma_regs_t *regs );
+extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size );
+extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs);
+extern void sa1100_reset_dma(dma_regs_t *regs);
+
+/**
+ * 	sa1100_stop_dma - stop DMA in progress
+ * 	@regs: identifier for the channel to use
+ *
+ * 	This stops DMA without clearing buffer pointers. Unlike
+ * 	sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma()
+ * 	or sa1100_get_dma_pos().
+ *
+ * 	The @regs identifier is provided by a successful call to
+ * 	sa1100_request_dma().
+ **/
+
+#define sa1100_stop_dma(regs)	((regs)->ClrDCSR = DCSR_IE|DCSR_RUN)
+
+/**
+ * 	sa1100_resume_dma - resume DMA on a stopped channel
+ * 	@regs: identifier for the channel to use
+ *
+ * 	This resumes DMA on a channel previously stopped with
+ * 	sa1100_stop_dma().
+ *
+ * 	The @regs identifier is provided by a successful call to
+ * 	sa1100_request_dma().
+ **/
+
+#define sa1100_resume_dma(regs)	((regs)->SetDCSR = DCSR_IE|DCSR_RUN)
+
+/**
+ * 	sa1100_clear_dma - clear DMA pointers
+ * 	@regs: identifier for the channel to use
+ *
+ * 	This clear any DMA state so the DMA engine is ready to restart
+ * 	with new buffers through sa1100_start_dma(). Any buffers in flight
+ * 	are discarded.
+ *
+ * 	The @regs identifier is provided by a successful call to
+ * 	sa1100_request_dma().
+ **/
+
+#define sa1100_clear_dma(regs)	((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB)
 
-typedef void (*dma_callback_t)( void *buf_id, int size );
-
-
-/* SA1100 DMA API */
-extern int sa1100_request_dma( dmach_t *channel, const char *device_id,
-			       dma_device_t device );
-extern int sa1100_dma_set_callback( dmach_t channel, dma_callback_t cb );
-extern int sa1100_dma_set_spin( dmach_t channel, dma_addr_t addr, int size );
-extern int sa1100_dma_queue_buffer( dmach_t channel, void *buf_id,
-				    dma_addr_t data, int size );
-extern int sa1100_dma_get_current( dmach_t channel, void **buf_id, dma_addr_t *addr );
-extern int sa1100_dma_stop( dmach_t channel );
-extern int sa1100_dma_resume( dmach_t channel );
-extern int sa1100_dma_flush_all( dmach_t channel );
-extern void sa1100_free_dma( dmach_t channel );
-extern int sa1100_dma_sleep( dmach_t channel );
-extern int sa1100_dma_wakeup( dmach_t channel );
-
-/* Sa1111 DMA interface (all but registration uses the above) */
-extern int sa1111_sac_request_dma( dmach_t *channel, const char *device_id,
-				   unsigned int direction );
-extern int sa1111_check_dma_bug( dma_addr_t addr );
 
 #ifdef CONFIG_SA1111
 static inline void
diff --git a/include/asm-arm/arch-sa1100/flexanet.h b/include/asm-arm/arch-sa1100/flexanet.h
index f0b8d42f2278..6dc79190ca8f 100644
--- a/include/asm-arm/arch-sa1100/flexanet.h
+++ b/include/asm-arm/arch-sa1100/flexanet.h
@@ -1,5 +1,5 @@
 /*
- * linux/include/asm-arm/arch-sa1100/flexanet.h
+ * include/asm-arm/arch-sa1100/flexanet.h
  *
  * Created 2001/05/04 by Jordi Colomer <jco@ict.es>
  *
@@ -11,39 +11,79 @@
 #error "include <asm/hardware.h> instead"
 #endif
 
-
 /* Board Control Register (virtual address) */
-#define BCR_PHYS  0x10000000
-#define BCR_VIRT  0xf0000000
-#define BCR (*(volatile unsigned int *)(BCR_VIRT))
+#define FHH_BCR_PHYS  0x10000000
+#define FHH_BCR_VIRT  0xf0000000
+#define FHH_BCR (*(volatile unsigned int *)(FHH_BCR_VIRT))
 
 /* Power-up value */
-#define BCR_POWERUP	0x00000000
+#define FHH_BCR_POWERUP	0x00000000
 
 /* Mandatory bits */
-#define BCR_LED_GREEN	(1<<0)	/* General-purpose green LED (1 = on) */
-#define BCR_GUI_NRST	(1<<4)	/* GUI board reset (0 = reset) */
-
-/* Board Status Register (virtual address) */
-#define BSR_BASE  BCR_BASE
-#define BSR (*(volatile unsigned int *)(BSR_BASE))
-
+#define FHH_BCR_LED_GREEN  (1<<0)  /* General-purpose green LED (1 = on) */
+#define FHH_BCR_SPARE_1    (1<<1)  /* Not defined */
+#define FHH_BCR_CF1_RST    (1<<2)  /* Compact Flash Slot #1 Reset (1 = reset) */
+#define FHH_BCR_CF2_RST    (1<<3)  /* Compact Flash Slot #2 Reset (1 = reset) */
+#define FHH_BCR_GUI_NRST   (1<<4)  /* GUI board reset (0 = reset) */
+#define FHH_BCR_RTS1       (1<<5)  /* RS232 RTS for UART-1 */
+#define FHH_BCR_RTS3       (1<<6)  /* RS232 RTS for UART-3 */
+#define FHH_BCR_XCDBG0     (1<<7)  /* Not defined. Wired to XPLA3 for debug */
+
+/* BCR extension, only required by L3-bus in some audio codecs */
+#define FHH_BCR_L3MOD      (1<<8)  /* L3-bus MODE signal */
+#define FHH_BCR_L3DAT      (1<<9)  /* L3-bus DATA signal */
+#define FHH_BCR_L3CLK      (1<<10) /* L3-bus CLK signal */
+#define FHH_BCR_SPARE_11   (1<<11) /* Not defined */
+#define FHH_BCR_SPARE_12   (1<<12) /* Not defined */
+#define FHH_BCR_SPARE_13   (1<<13) /* Not defined */
+#define FHH_BCR_SPARE_14   (1<<14) /* Not defined */
+#define FHH_BCR_SPARE_15   (1<<15) /* Not defined */
+
+ /* Board Status Register (virtual address) */
+#define FHH_BSR_BASE  FHH_BCR_VIRT
+#define FHH_BSR (*(volatile unsigned int *)(FHH_BSR_BASE))
+
+#define FHH_BSR_CTS1       (1<<0)  /* RS232 CTS for UART-1 */
+#define FHH_BSR_CTS3       (1<<1)  /* RS232 CTS for UART-3 */
+#define FHH_BSR_DSR1       (1<<2)  /* RS232 DSR for UART-1 */
+#define FHH_BSR_DSR3       (1<<3)  /* RS232 DSR for UART-3 */
+#define FHH_BSR_ID0        (1<<4)  /* Board identification */
+#define FHH_BSR_ID1        (1<<5)
+#define FHH_BSR_CFG0       (1<<6)  /* Board configuration options */
+#define FHH_BSR_CFG1       (1<<7)
 
 #ifndef __ASSEMBLY__
-extern unsigned long BCR_value;	/* Image of the BCR */
-#define BCR_set( x )	BCR = (BCR_value |= (x))
-#define BCR_clear( x )	BCR = (BCR_value &= ~(x))
+extern unsigned long flexanet_BCR;	/* Image of the BCR */
+#define FLEXANET_BCR_set( x )    FHH_BCR = (flexanet_BCR |= (x))
+#define FLEXANET_BCR_clear( x )  FHH_BCR = (flexanet_BCR &= ~(x))
 #endif
 
-
 /* GPIOs for which the generic definition doesn't say much */
-#define GPIO_GUI_IRQ		GPIO_GPIO (23)	/* IRQ from GUI board (i.e., UCB1300) */
-#define GPIO_ETH_IRQ		GPIO_GPIO (24)	/* IRQ from Ethernet controller */
-#define GPIO_LED_RED		GPIO_GPIO (26)	/* General-purpose red LED */
+#define GPIO_CF1_NCD       GPIO_GPIO (14)  /* Card Detect from CF slot #1 */
+#define GPIO_CF2_NCD       GPIO_GPIO (15)  /* Card Detect from CF slot #2 */
+#define GPIO_CF1_IRQ       GPIO_GPIO (16)  /* IRQ from CF slot #1 */
+#define GPIO_CF2_IRQ       GPIO_GPIO (17)  /* IRQ from CF slot #2 */
+#define GPIO_APP_IRQ       GPIO_GPIO (18)  /* Extra IRQ from application bus */
+#define GPIO_RADIO_REF     GPIO_GPIO (20)  /* Ref. clock for UART3 (Radio) */
+#define GPIO_CF1_BVD1      GPIO_GPIO (21)  /* BVD1 from CF slot #1 */
+#define GPIO_CF2_BVD1      GPIO_GPIO (22)  /* BVD1 from CF slot #2 */
+#define GPIO_GUI_IRQ       GPIO_GPIO (23)  /* IRQ from GUI board (i.e., UCB1300) */
+#define GPIO_ETH_IRQ       GPIO_GPIO (24)  /* IRQ from Ethernet controller */
+#define GPIO_INTIP_IRQ     GPIO_GPIO (25)  /* Measurement IRQ (INTIP) */
+#define GPIO_LED_RED       GPIO_GPIO (26)  /* General-purpose red LED */
 
 /* IRQ sources from GPIOs */
-#define IRQ_GPIO_GUI		IRQ_GPIO23
-#define IRQ_GPIO_ETH		IRQ_GPIO24
+#define IRQ_GPIO_CF1_CD    IRQ_GPIO14
+#define IRQ_GPIO_CF2_CD    IRQ_GPIO15
+#define IRQ_GPIO_CF1_IRQ   IRQ_GPIO16
+#define IRQ_GPIO_CF2_IRQ   IRQ_GPIO17
+#define IRQ_GPIO_APP       IRQ_GPIO18
+#define IRQ_GPIO_CF1_BVD1  IRQ_GPIO21
+#define IRQ_GPIO_CF2_BVD1  IRQ_GPIO22
+#define IRQ_GPIO_GUI       IRQ_GPIO23
+#define IRQ_GPIO_ETH       IRQ_GPIO24
+#define IRQ_GPIO_INTIP     IRQ_GPIO25
+
 
 /* On-Board Ethernet */
 #define _FHH_ETH_IOBASE		0x18000000	/* I/O base (physical addr) */
@@ -58,14 +98,3 @@ extern unsigned long BCR_value;	/* Image of the BCR */
 #define FHH_ETH_MMBASE		FHH_ETH_p2v(_FHH_ETH_MMBASE)
 
 
-/* Types of GUI */
-#ifndef __ASSEMBLY__
-extern unsigned long GUI_type;
-#endif
-
-#define FHH_GUI_ERROR		0xFFFFFFFF
-#define FHH_GUI_NONE		0x0000000F
-#define FHH_GUI_TYPE_0		0
-#define FHH_GUI_TYPE_1		1
-#define FHH_GUI_TYPE_2		2
-
diff --git a/include/asm-arm/arch-sa1100/graphicsmaster.h b/include/asm-arm/arch-sa1100/graphicsmaster.h
index 289bc255d5db..ae45791739ce 100644
--- a/include/asm-arm/arch-sa1100/graphicsmaster.h
+++ b/include/asm-arm/arch-sa1100/graphicsmaster.h
@@ -62,5 +62,3 @@
 #endif
 
 #define	SA1111_BASE	(0x18000000)
-
-#include "SA-1111.h"
diff --git a/include/asm-arm/arch-sa1100/h3600.h b/include/asm-arm/arch-sa1100/h3600.h
index 1ae5b77ed66c..d0fc9198c9eb 100644
--- a/include/asm-arm/arch-sa1100/h3600.h
+++ b/include/asm-arm/arch-sa1100/h3600.h
@@ -1,81 +1,138 @@
 /*
-*
-* Definitions for H3600 Handheld Computer
-*
-* Copyright 2000 Compaq Computer Corporation.
-*
-* Use consistent with the GNU GPL is permitted,
-* provided that this copyright notice is
-* preserved in its entirety in all copies and derived works.
-*
-* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
-* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
-* FITNESS FOR ANY PARTICULAR PURPOSE.
-*
-* Author: Jamey Hicks.
-*
-*/
+ *
+ * Definitions for H3600 Handheld Computer
+ *
+ * Copyright 2000 Compaq Computer Corporation.
+ *
+ * Use consistent with the GNU GPL is permitted,
+ * provided that this copyright notice is
+ * preserved in its entirety in all copies and derived works.
+ *
+ * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+ * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+ * FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ * Author: Jamey Hicks.
+ *
+ * History:
+ *
+ * 2001-10-??   Andrew Christian   Added support for iPAQ H3800
+ *
+ */
 
 #ifndef _INCLUDE_H3600_H_
 #define _INCLUDE_H3600_H_
 
-#define GPIO_H3600_NPOWER_BUTTON	GPIO_GPIO (0)
-#define GPIO_H3600_ACTION_BUTTON	GPIO_GPIO (18)
+/* generalized support for H3xxx series Compaq Pocket PC's */
+#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800())
+
+/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */
+#define H3600_EGPIO_VIRT     0xf0000000
+#define H3600_BANK_2_VIRT    0xf1000000
+#define H3600_BANK_4_VIRT    0xf3800000
+
+/*
+   Machine-independent GPIO definitions
+   --- these are common across all current iPAQ platforms
+*/
+
+#define GPIO_H3600_NPOWER_BUTTON	GPIO_GPIO (0)   /* Also known as the "off button"  */
+#define GPIO_H3600_MICROCONTROLLER	GPIO_GPIO (1)   /* From ASIC2 on H3800 */
 
-#define GPIO_H3600_PCMCIA_CD0		GPIO_GPIO (17)
 #define GPIO_H3600_PCMCIA_CD1		GPIO_GPIO (10)
-#define GPIO_H3600_PCMCIA_IRQ0		GPIO_GPIO (21)
 #define GPIO_H3600_PCMCIA_IRQ1		GPIO_GPIO (11)
 
-/* audio sample rate clock generator */
-#define GPIO_H3600_CLK_SET0		GPIO_GPIO (12)
-#define GPIO_H3600_CLK_SET1		GPIO_GPIO (13)
-
 /* UDA1341 L3 Interface */
 #define GPIO_H3600_L3_DATA		GPIO_GPIO (14)
-#define GPIO_H3600_L3_CLOCK		GPIO_GPIO (16)
 #define GPIO_H3600_L3_MODE		GPIO_GPIO (15)
+#define GPIO_H3600_L3_CLOCK		GPIO_GPIO (16)
 
-#define GPIO_H3600_OPT_LOCK		GPIO_GPIO (22)
-#define GPIO_H3600_OPT_IRQ		GPIO_GPIO (24)
-#define GPIO_H3600_OPT_DET		GPIO_GPIO (27)
+#define GPIO_H3600_PCMCIA_CD0		GPIO_GPIO (17)
+#define GPIO_H3600_SYS_CLK		GPIO_GPIO (19)
+#define GPIO_H3600_PCMCIA_IRQ0		GPIO_GPIO (21)
 
 #define GPIO_H3600_COM_DCD		GPIO_GPIO (23)
+#define GPIO_H3600_OPT_IRQ		GPIO_GPIO (24)
 #define GPIO_H3600_COM_CTS		GPIO_GPIO (25)
 #define GPIO_H3600_COM_RTS		GPIO_GPIO (26)
 
 #define IRQ_GPIO_H3600_NPOWER_BUTTON    IRQ_GPIO0
-#define IRQ_GPIO_H3600_ACTION_BUTTON    IRQ_GPIO18
-#define IRQ_GPIO_H3600_PCMCIA_CD0	IRQ_GPIO17
+#define IRQ_GPIO_H3600_MICROCONTROLLER  IRQ_GPIO1
 #define IRQ_GPIO_H3600_PCMCIA_CD1	IRQ_GPIO10
-#define IRQ_GPIO_H3600_PCMCIA_IRQ0	IRQ_GPIO21
 #define IRQ_GPIO_H3600_PCMCIA_IRQ1	IRQ_GPIO11
-#define IRQ_GPIO_H3600_OPT_IRQ		IRQ_GPIO24
-#define IRQ_GPIO_H3600_OPT_DET		IRQ_GPIO27
+#define IRQ_GPIO_H3600_PCMCIA_CD0	IRQ_GPIO17
+#define IRQ_GPIO_H3600_PCMCIA_IRQ0	IRQ_GPIO21
 #define IRQ_GPIO_H3600_COM_DCD          IRQ_GPIO23
+#define IRQ_GPIO_H3600_OPT_IRQ		IRQ_GPIO24
 #define IRQ_GPIO_H3600_COM_CTS          IRQ_GPIO25
 
-#define EGPIO_H3600_VPP_ON		(1 << 0)
-#define EGPIO_H3600_CARD_RESET		(1 << 1)  /* reset the attached pcmcia/compactflash card.  active high. */
-#define EGPIO_H3600_OPT_RESET		(1 << 2)  /* reset the attached option pack.  active high. */
-#define EGPIO_H3600_CODEC_NRESET	(1 << 3)  /* reset the onboard UDA1341.  active low. */
-#define EGPIO_H3600_OPT_NVRAM_ON	(1 << 4)  /* apply power to optionpack nvram, active high. */
-#define EGPIO_H3600_OPT_ON		(1 << 5)  /* full power to option pack.  active high. */
-#define EGPIO_H3600_LCD_ON       	(1 << 6)  /* enable 3.3V to LCD.  active high. */
-#define EGPIO_H3600_RS232_ON		(1 << 7)  /* UART3 transceiver force on.  Active high. */
-#define EGPIO_H3600_LCD_PCI		(1 << 8)  /* LCD control IC enable.  active high. */
-#define EGPIO_H3600_IR_ON		(1 << 9)  /* apply power to IR module.  active high. */
-#define EGPIO_H3600_AUD_AMP_ON		(1 << 10) /* apply power to audio power amp.  active high. */
-#define EGPIO_H3600_AUD_PWR_ON		(1 << 11) /* apply poewr to reset of audio circuit.  active high. */
-#define EGPIO_H3600_QMUTE		(1 << 12) /* mute control for onboard UDA1341.  active high. */
-#define EGPIO_H3600_IR_FSEL		(1 << 13) /* IR speed select: 1->fast, 0->slow */
-#define EGPIO_H3600_LCD_5V_ON		(1 << 14) /* enable 5V to LCD. active high. */
-#define EGPIO_H3600_LVDD_ON		(1 << 15) /* enable 9V and -6.5V to LCD. */
 
 #ifndef __ASSEMBLY__
-#define H3600_EGPIO	(*(volatile int *)0xf0000000)
-extern void clr_h3600_egpio(unsigned long x);
-extern void set_h3600_egpio(unsigned long x);
-#endif
+enum ipaq_model {
+	IPAQ_H3100,
+	IPAQ_H3600,
+	IPAQ_H3800
+};
+
+enum ipaq_egpio_type {
+	IPAQ_EGPIO_LCD_ON,        /* Power to the LCD panel */
+	IPAQ_EGPIO_CODEC_NRESET,  /* Clear to reset the audio codec (remember to return high) */
+	IPAQ_EGPIO_AUDIO_ON,      /* Audio power */
+	IPAQ_EGPIO_QMUTE,         /* Audio muting */
+	IPAQ_EGPIO_OPT_NVRAM_ON,  /* Non-volatile RAM on extension sleeves (SPI interface) */
+	IPAQ_EGPIO_OPT_ON,        /* Power to extension sleeves */
+	IPAQ_EGPIO_CARD_RESET,    /* Reset PCMCIA cards on extension sleeve (???) */
+	IPAQ_EGPIO_OPT_RESET,     /* Reset option pack (???) */
+	IPAQ_EGPIO_IR_ON,         /* IR sensor/emitter power */
+	IPAQ_EGPIO_IR_FSEL,       /* IR speed selection 1->fast, 0->slow */
+	IPAQ_EGPIO_RS232_ON,      /* Maxim RS232 chip power */
+	IPAQ_EGPIO_VPP_ON,        /* Turn on power to flash programming */
+};
+
+struct ipaq_model_ops {
+	enum ipaq_model model;
+	const char     *generic_name;
+	void          (*initialize)(void);
+	void          (*control)(enum ipaq_egpio_type, int);
+	unsigned long (*read)(void);
+};
+
+extern struct ipaq_model_ops ipaq_model_ops;
+
+static __inline__ enum ipaq_model h3600_model( void ) {
+	return ipaq_model_ops.model;
+}
+
+static __inline__ const char * h3600_generic_name( void ) {
+	return ipaq_model_ops.generic_name;
+}
+
+static __inline__ void init_h3600_egpio( void ) {
+	if (ipaq_model_ops.initialize)
+		ipaq_model_ops.initialize();
+}
+
+static __inline__ void assign_h3600_egpio( enum ipaq_egpio_type x, int level ) {
+	if (ipaq_model_ops.control)
+		ipaq_model_ops.control(x,level);
+}
+
+static __inline__ void clr_h3600_egpio( enum ipaq_egpio_type x ) {
+	if (ipaq_model_ops.control)
+		ipaq_model_ops.control(x,0);
+}
+
+static __inline__ void set_h3600_egpio( enum ipaq_egpio_type x ) {
+	if (ipaq_model_ops.control)
+		ipaq_model_ops.control(x,1);
+}
+
+static __inline__ unsigned long read_h3600_egpio( void ) {
+	if (ipaq_model_ops.read)
+		return ipaq_model_ops.read();
+	return 0;
+}
+
+#endif /* ASSEMBLY */
 
-#endif
+#endif /* _INCLUDE_H3600_H_ */
diff --git a/include/asm-arm/arch-sa1100/h3600_gpio.h b/include/asm-arm/arch-sa1100/h3600_gpio.h
new file mode 100644
index 000000000000..6b7e000a52f9
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/h3600_gpio.h
@@ -0,0 +1,540 @@
+/*
+ *
+ * Definitions for H3600 Handheld Computer
+ *
+ * Copyright 2000 Compaq Computer Corporation.
+ *
+ * Use consistent with the GNU GPL is permitted,
+ * provided that this copyright notice is
+ * preserved in its entirety in all copies and derived works.
+ *
+ * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+ * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+ * FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ * Author: Jamey Hicks.
+ *
+ * History:
+ *
+ * 2001-10-??   Andrew Christian   Added support for iPAQ H3800
+ *
+ */
+
+#ifndef _INCLUDE_H3600_GPIO_H_
+#define _INCLUDE_H3600_GPIO_H_
+
+/*
+ * GPIO lines that are common across ALL iPAQ models are in "h3600.h"
+ * This file contains machine-specific definitions
+ */
+
+#define GPIO_H3600_SUSPEND              GPIO_GPIO (0)
+/* GPIO[2:9] used by LCD on H3600/3800, used as GPIO on H3100 */
+#define GPIO_H3100_BT_ON		GPIO_GPIO (2)
+#define GPIO_H3100_GPIO3		GPIO_GPIO (3)
+#define GPIO_H3100_QMUTE		GPIO_GPIO (4)
+#define GPIO_H3100_LCD_3V_ON		GPIO_GPIO (5)
+#define GPIO_H3100_AUD_ON		GPIO_GPIO (6)
+#define GPIO_H3100_AUD_PWR_ON		GPIO_GPIO (7)
+#define GPIO_H3100_IR_ON		GPIO_GPIO (8)
+#define GPIO_H3100_IR_FSEL		GPIO_GPIO (9)
+
+/* for H3600, audio sample rate clock generator */
+#define GPIO_H3600_CLK_SET0		GPIO_GPIO (12)
+#define GPIO_H3600_CLK_SET1		GPIO_GPIO (13)
+
+#define GPIO_H3600_ACTION_BUTTON	GPIO_GPIO (18)
+#define GPIO_H3600_SOFT_RESET           GPIO_GPIO (20)   /* Also known as BATT_FAULT */
+#define GPIO_H3600_OPT_LOCK		GPIO_GPIO (22)
+#define GPIO_H3600_OPT_DET		GPIO_GPIO (27)
+
+/* H3800 specific pins */
+#define GPIO_H3800_AC_IN                GPIO_GPIO (12)
+#define GPIO_H3800_COM_DSR              GPIO_GPIO (13)
+#define GPIO_H3800_MMC_INT              GPIO_GPIO (18)
+#define GPIO_H3800_NOPT_IND             GPIO_GPIO (20)   /* Almost exactly the same as GPIO_H3600_OPT_DET */
+#define GPIO_H3800_OPT_BAT_FAULT        GPIO_GPIO (22)
+#define GPIO_H3800_CLK_OUT              GPIO_GPIO (27)
+
+/****************************************************/
+
+#define IRQ_GPIO_H3600_ACTION_BUTTON    IRQ_GPIO18
+#define IRQ_GPIO_H3600_OPT_DET		IRQ_GPIO27
+
+#define IRQ_GPIO_H3800_MMC_INT          IRQ_GPIO18
+#define IRQ_GPIO_H3800_NOPT_IND         IRQ_GPIO20 /* almost same as OPT_DET */
+
+/* H3100 / 3600 EGPIO pins */
+#define EGPIO_H3600_VPP_ON		(1 << 0)
+#define EGPIO_H3600_CARD_RESET		(1 << 1)   /* reset the attached pcmcia/compactflash card.  active high. */
+#define EGPIO_H3600_OPT_RESET		(1 << 2)   /* reset the attached option pack.  active high. */
+#define EGPIO_H3600_CODEC_NRESET	(1 << 3)   /* reset the onboard UDA1341.  active low. */
+#define EGPIO_H3600_OPT_NVRAM_ON	(1 << 4)   /* apply power to optionpack nvram, active high. */
+#define EGPIO_H3600_OPT_ON		(1 << 5)   /* full power to option pack.  active high. */
+#define EGPIO_H3600_LCD_ON		(1 << 6)   /* enable 3.3V to LCD.  active high. */
+#define EGPIO_H3600_RS232_ON		(1 << 7)   /* UART3 transceiver force on.  Active high. */
+
+/* H3600 only EGPIO pins */
+#define EGPIO_H3600_LCD_PCI		(1 << 8)   /* LCD control IC enable.  active high. */
+#define EGPIO_H3600_IR_ON		(1 << 9)   /* apply power to IR module.  active high. */
+#define EGPIO_H3600_AUD_AMP_ON		(1 << 10)  /* apply power to audio power amp.  active high. */
+#define EGPIO_H3600_AUD_PWR_ON		(1 << 11)  /* apply power to reset of audio circuit.  active high. */
+#define EGPIO_H3600_QMUTE		(1 << 12)  /* mute control for onboard UDA1341.  active high. */
+#define EGPIO_H3600_IR_FSEL		(1 << 13)  /* IR speed select: 1->fast, 0->slow */
+#define EGPIO_H3600_LCD_5V_ON		(1 << 14)  /* enable 5V to LCD. active high. */
+#define EGPIO_H3600_LVDD_ON		(1 << 15)  /* enable 9V and -6.5V to LCD. */
+
+/********************* H3800, ASIC #2 ********************/
+
+#define _H3800_ASIC2_Base            (H3600_EGPIO_VIRT)
+#define H3800_ASIC2_OFFSET(s,x,y)    \
+    (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
+#define H3800_ASIC2_NOFFSET(s,x,n,y) \
+    (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
+
+#define _H3800_ASIC2_GPIO_Base                 0x0000
+#define _H3800_ASIC2_GPIO_Direction            0x0000    /* R/W, 16 bits 1:input, 0:output */
+#define _H3800_ASIC2_GPIO_InterruptType        0x0004    /* R/W, 12 bits 1:edge, 0:level          */
+#define _H3800_ASIC2_GPIO_InterruptEdgeType    0x0008    /* R/W, 12 bits 1:rising, 0:falling */
+#define _H3800_ASIC2_GPIO_InterruptLevelType   0x000C    /* R/W, 12 bits 1:high, 0:low  */
+#define _H3800_ASIC2_GPIO_InterruptClear       0x0010    /* W,   12 bits */
+#define _H3800_ASIC2_GPIO_InterruptFlag        0x0010    /* R,   12 bits - reads int status */
+#define _H3800_ASIC2_GPIO_Data                 0x0014    /* R/W, 16 bits */
+#define _H3800_ASIC2_GPIO_BattFaultOut         0x0018    /* R/W, 16 bit - sets level on batt fault */
+#define _H3800_ASIC2_GPIO_InterruptEnable      0x001c    /* R/W, 12 bits 1:enable interrupt */
+#define _H3800_ASIC2_GPIO_Alternate            0x003c    /* R/W, 12+1 bits - set alternate functions */
+
+#define H3800_ASIC2_GPIO_Direction          H3800_ASIC2_OFFSET( u16, GPIO, Direction )
+#define H3800_ASIC2_GPIO_InterruptType      H3800_ASIC2_OFFSET( u16, GPIO, InterruptType )
+#define H3800_ASIC2_GPIO_InterruptEdgeType  H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType )
+#define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType )
+#define H3800_ASIC2_GPIO_InterruptClear     H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear )
+#define H3800_ASIC2_GPIO_InterruptFlag      H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag )
+#define H3800_ASIC2_GPIO_Data               H3800_ASIC2_OFFSET( u16, GPIO, Data )
+#define H3800_ASIC2_GPIO_BattFaultOut       H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut )
+#define H3800_ASIC2_GPIO_InterruptEnable    H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable )
+#define H3800_ASIC2_GPIO_Alternate          H3800_ASIC2_OFFSET( u16, GPIO, Alternate )
+
+#define GPIO_H3800_ASIC2_IN_Y1_N          (1 << 0)   /* Output: Touchscreen Y1 */
+#define GPIO_H3800_ASIC2_IN_X0            (1 << 1)   /* Output: Touchscreen X0 */
+#define GPIO_H3800_ASIC2_IN_Y0            (1 << 2)   /* Output: Touchscreen Y0 */
+#define GPIO_H3800_ASIC2_IN_X1_N          (1 << 3)   /* Output: Touchscreen X1 */
+#define GPIO_H3800_ASIC2_BT_RST           (1 << 4)   /* Output: Bluetooth reset */
+#define GPIO_H3800_ASIC2_PEN_IRQ          (1 << 5)   /* Input : Pen down        */
+#define GPIO_H3800_ASIC2_SD_DETECT        (1 << 6)   /* Input : SD detect */
+#define GPIO_H3800_ASIC2_EAR_IN_N         (1 << 7)   /* Input : Audio jack plug inserted */
+#define GPIO_H3800_ASIC2_OPT_PCM_RESET    (1 << 8)   /* Output: */
+#define GPIO_H3800_ASIC2_OPT_RESET        (1 << 9)   /* Output: */
+#define GPIO_H3800_ASIC2_USB_DETECT_N     (1 << 10)  /* Input : */
+#define GPIO_H3800_ASIC2_SD_CON_SLT       (1 << 11)  /* Input : */
+
+#define _H3800_ASIC2_KPIO_Base                 0x0200
+#define _H3800_ASIC2_KPIO_Direction            0x0000    /* R/W, 12 bits 1:input, 0:output */
+#define _H3800_ASIC2_KPIO_InterruptType        0x0004    /* R/W, 12 bits 1:edge, 0:level          */
+#define _H3800_ASIC2_KPIO_InterruptEdgeType    0x0008    /* R/W, 12 bits 1:rising, 0:falling */
+#define _H3800_ASIC2_KPIO_InterruptLevelType   0x000C    /* R/W, 12 bits 1:high, 0:low  */
+#define _H3800_ASIC2_KPIO_InterruptClear       0x0010    /* W,   20 bits - 8 special */
+#define _H3800_ASIC2_KPIO_InterruptFlag        0x0010    /* R,   20 bits - 8 special - reads int status */
+#define _H3800_ASIC2_KPIO_Data                 0x0014    /* R/W, 16 bits */
+#define _H3800_ASIC2_KPIO_BattFaultOut         0x0018    /* R/W, 16 bit - sets level on batt fault */
+#define _H3800_ASIC2_KPIO_InterruptEnable      0x001c    /* R/W, 20 bits - 8 special */
+#define _H3800_ASIC2_KPIO_Alternate            0x003c    /* R/W, 6 bits */
+
+#define H3800_ASIC2_KPIO_Direction          H3800_ASIC2_OFFSET( u16, KPIO, Direction )
+#define H3800_ASIC2_KPIO_InterruptType      H3800_ASIC2_OFFSET( u16, KPIO, InterruptType )
+#define H3800_ASIC2_KPIO_InterruptEdgeType  H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType )
+#define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType )
+#define H3800_ASIC2_KPIO_InterruptClear     H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear )
+#define H3800_ASIC2_KPIO_InterruptFlag      H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag )
+#define H3800_ASIC2_KPIO_Data               H3800_ASIC2_OFFSET( u16, KPIO, Data )
+#define H3800_ASIC2_KPIO_BattFaultOut       H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut )
+#define H3800_ASIC2_KPIO_InterruptEnable    H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable )
+#define H3800_ASIC2_KPIO_Alternate          H3800_ASIC2_OFFSET( u16, KPIO, Alternate )
+
+#define H3800_ASIC2_KPIO_SPI_INT        ( 1 << 16 )
+#define H3800_ASIC2_KPIO_OWM_INT        ( 1 << 17 )
+#define H3800_ASIC2_KPIO_ADC_INT        ( 1 << 18 )
+#define H3800_ASIC2_KPIO_UART_0_INT     ( 1 << 19 )
+#define H3800_ASIC2_KPIO_UART_1_INT     ( 1 << 20 )
+#define H3800_ASIC2_KPIO_TIMER_0_INT    ( 1 << 21 )
+#define H3800_ASIC2_KPIO_TIMER_1_INT    ( 1 << 22 )
+#define H3800_ASIC2_KPIO_TIMER_2_INT    ( 1 << 23 )
+
+#define KPIO_H3800_ASIC2_RECORD_BTN_N     (1 << 0)   /* Record button */
+#define KPIO_H3800_ASIC2_KEY_5W1_N        (1 << 1)   /* Keypad */
+#define KPIO_H3800_ASIC2_KEY_5W2_N        (1 << 2)   /* */
+#define KPIO_H3800_ASIC2_KEY_5W3_N        (1 << 3)   /* */
+#define KPIO_H3800_ASIC2_KEY_5W4_N        (1 << 4)   /* */
+#define KPIO_H3800_ASIC2_KEY_5W5_N        (1 << 5)   /* */
+#define KPIO_H3800_ASIC2_KEY_LEFT_N       (1 << 6)   /* */
+#define KPIO_H3800_ASIC2_KEY_RIGHT_N      (1 << 7)   /* */
+#define KPIO_H3800_ASIC2_KEY_AP1_N        (1 << 8)   /* Old "Calendar" */
+#define KPIO_H3800_ASIC2_KEY_AP2_N        (1 << 9)   /* Old "Schedule" */
+#define KPIO_H3800_ASIC2_KEY_AP3_N        (1 << 10)  /* Old "Q"        */
+#define KPIO_H3800_ASIC2_KEY_AP4_N        (1 << 11)  /* Old "Undo"     */
+
+/* Alternate KPIO functions (set by default) */
+#define KPIO_ALT_H3800_ASIC2_KEY_5W1_N        (1 << 1)   /* Action key */
+#define KPIO_ALT_H3800_ASIC2_KEY_5W2_N        (1 << 2)   /* J1 of keypad input */
+#define KPIO_ALT_H3800_ASIC2_KEY_5W3_N        (1 << 3)   /* J2 of keypad input */
+#define KPIO_ALT_H3800_ASIC2_KEY_5W4_N        (1 << 4)   /* J3 of keypad input */
+#define KPIO_ALT_H3800_ASIC2_KEY_5W5_N        (1 << 5)   /* J4 of keypad input */
+
+#define _H3800_ASIC2_SPI_Base                  0x0400
+#define _H3800_ASIC2_SPI_Control               0x0000    /* R/W 8 bits */
+#define _H3800_ASIC2_SPI_Data                  0x0004    /* R/W 8 bits */
+#define _H3800_ASIC2_SPI_ChipSelectDisabled    0x0008    /* W   8 bits */
+
+#define H3800_ASIC2_SPI_Control             H3800_ASIC2_OFFSET( u8, SPI, Control )
+#define H3800_ASIC2_SPI_Data                H3800_ASIC2_OFFSET( u8, SPI, Data )
+#define H3800_ASIC2_SPI_ChipSelectDisabled  H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled )
+
+#define _H3800_ASIC2_PWM_0_Base                0x0600
+#define _H3800_ASIC2_PWM_1_Base                0x0700
+#define _H3800_ASIC2_PWM_TimeBase              0x0000    /* R/W 6 bits */
+#define _H3800_ASIC2_PWM_PeriodTime            0x0004    /* R/W 12 bits */
+#define _H3800_ASIC2_PWM_DutyTime              0x0008    /* R/W 12 bits */
+
+#define H3800_ASIC2_PWM_0_TimeBase          H3800_ASIC2_NOFFSET(  u8, PWM, 0, TimeBase )
+#define H3800_ASIC2_PWM_0_PeriodTime        H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime )
+#define H3800_ASIC2_PWM_0_DutyTime          H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime )
+
+#define H3800_ASIC2_PWM_1_TimeBase          H3800_ASIC2_NOFFSET(  u8, PWM, 1, TimeBase )
+#define H3800_ASIC2_PWM_1_PeriodTime        H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime )
+#define H3800_ASIC2_PWM_1_DutyTime          H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime )
+
+#define H3800_ASIC2_PWM_TIMEBASE_MASK             0xf    /* Low 4 bits sets time base, max = 8 */
+#define H3800_ASIC2_PWM_TIMEBASE_ENABLE    ( 1 << 4 )    /* Enable clock */
+#define H3800_ASIC2_PWM_TIMEBASE_CLEAR     ( 1 << 5 )    /* Clear the PWM */
+
+#define _H3800_ASIC2_LED_0_Base                0x0800
+#define _H3800_ASIC2_LED_1_Base                0x0880
+#define _H3800_ASIC2_LED_2_Base                0x0900
+#define _H3800_ASIC2_LED_TimeBase              0x0000    /* R/W  7 bits */
+#define _H3800_ASIC2_LED_PeriodTime            0x0004    /* R/W 12 bits */
+#define _H3800_ASIC2_LED_DutyTime              0x0008    /* R/W 12 bits */
+#define _H3800_ASIC2_LED_AutoStopCount         0x000c    /* R/W 16 bits */
+
+#define H3800_ASIC2_LED_0_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 0, TimeBase )
+#define H3800_ASIC2_LED_0_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime )
+#define H3800_ASIC2_LED_0_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime )
+#define H3800_ASIC2_LED_0_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock )
+
+#define H3800_ASIC2_LED_1_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 1, TimeBase )
+#define H3800_ASIC2_LED_1_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime )
+#define H3800_ASIC2_LED_1_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime )
+#define H3800_ASIC2_LED_1_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock )
+
+#define H3800_ASIC2_LED_2_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 2, TimeBase )
+#define H3800_ASIC2_LED_2_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime )
+#define H3800_ASIC2_LED_2_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime )
+#define H3800_ASIC2_LED_2_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock )
+
+#define H3800_ASIC2_LED_TIMEBASE_MASK            0x0f    /* Low 4 bits sets time base, max = 13 */
+#define H3800_ASIC2_LED_TIMEBASE_BLINK     ( 1 << 4 )    /* Enable blinking */
+#define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP  ( 1 << 5 )
+#define H3800_ASIC2_LED_TIMEBASE_ALWAYS    ( 1 << 6 )    /* Enable blink always */
+
+#define _H3800_ASIC2_UART_0_Base               0x0A00
+#define _H3800_ASIC2_UART_1_Base               0x0C00
+#define _H3800_ASIC2_UART_Receive              0x0000    /* R    8 bits */
+#define _H3800_ASIC2_UART_Transmit             0x0000    /*   W  8 bits */
+#define _H3800_ASIC2_UART_IntEnable            0x0004    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_IntVerify            0x0008    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_FIFOControl          0x000c    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_LineControl          0x0010    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_ModemStatus          0x0014    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_LineStatus           0x0018    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_ScratchPad           0x001c    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_DivisorLatchL        0x0020    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_DivisorLatchH        0x0024    /* R/W  8 bits */
+
+#define H3800_ASIC2_UART_0_Receive          H3800_ASIC2_NOFFSET(  u8, UART, 0, Receive )
+#define H3800_ASIC2_UART_0_Transmit         H3800_ASIC2_NOFFSET(  u8, UART, 0, Transmit )
+#define H3800_ASIC2_UART_0_IntEnable        H3800_ASIC2_NOFFSET(  u8, UART, 0, IntEnable )
+#define H3800_ASIC2_UART_0_IntVerify        H3800_ASIC2_NOFFSET(  u8, UART, 0, IntVerify )
+#define H3800_ASIC2_UART_0_FIFOControl      H3800_ASIC2_NOFFSET(  u8, UART, 0, FIFOControl )
+#define H3800_ASIC2_UART_0_LineControl      H3800_ASIC2_NOFFSET(  u8, UART, 0, LineControl )
+#define H3800_ASIC2_UART_0_ModemStatus      H3800_ASIC2_NOFFSET(  u8, UART, 0, ModemStatus )
+#define H3800_ASIC2_UART_0_LineStatus       H3800_ASIC2_NOFFSET(  u8, UART, 0, LineStatus )
+#define H3800_ASIC2_UART_0_ScratchPad       H3800_ASIC2_NOFFSET(  u8, UART, 0, ScratchPad )
+#define H3800_ASIC2_UART_0_DivisorLatchL    H3800_ASIC2_NOFFSET(  u8, UART, 0, DivisorLatchL )
+#define H3800_ASIC2_UART_0_DivisorLatchH    H3800_ASIC2_NOFFSET(  u8, UART, 0, DivisorLatchH )
+
+#define H3800_ASIC2_UART_1_Receive          H3800_ASIC2_NOFFSET(  u8, UART, 1, Receive )
+#define H3800_ASIC2_UART_1_Transmit         H3800_ASIC2_NOFFSET(  u8, UART, 1, Transmit )
+#define H3800_ASIC2_UART_1_IntEnable        H3800_ASIC2_NOFFSET(  u8, UART, 1, IntEnable )
+#define H3800_ASIC2_UART_1_IntVerify        H3800_ASIC2_NOFFSET(  u8, UART, 1, IntVerify )
+#define H3800_ASIC2_UART_1_FIFOControl      H3800_ASIC2_NOFFSET(  u8, UART, 1, FIFOControl )
+#define H3800_ASIC2_UART_1_LineControl      H3800_ASIC2_NOFFSET(  u8, UART, 1, LineControl )
+#define H3800_ASIC2_UART_1_ModemStatus      H3800_ASIC2_NOFFSET(  u8, UART, 1, ModemStatus )
+#define H3800_ASIC2_UART_1_LineStatus       H3800_ASIC2_NOFFSET(  u8, UART, 1, LineStatus )
+#define H3800_ASIC2_UART_1_ScratchPad       H3800_ASIC2_NOFFSET(  u8, UART, 1, ScratchPad )
+#define H3800_ASIC2_UART_1_DivisorLatchL    H3800_ASIC2_NOFFSET(  u8, UART, 1, DivisorLatchL )
+#define H3800_ASIC2_UART_1_DivisorLatchH    H3800_ASIC2_NOFFSET(  u8, UART, 1, DivisorLatchH )
+
+#define _H3800_ASIC2_TIMER_Base                0x0E00
+#define _H3800_ASIC2_TIMER_Command             0x0000    /* R/W  8 bits */
+
+#define H3800_ASIC2_TIMER_Command           H3800_ASIC2_OFFSET( u8, Timer, Command )
+
+#define H3800_ASIC2_TIMER_GAT_0            ( 1 << 0 )    /* Gate enable, counter 0 */
+#define H3800_ASIC2_TIMER_GAT_1            ( 1 << 1 )    /* Gate enable, counter 1 */
+#define H3800_ASIC2_TIMER_GAT_2            ( 1 << 2 )    /* Gate enable, counter 2 */
+#define H3800_ASIC2_TIMER_CLK_0            ( 1 << 3 )    /* Clock enable, counter 0 */
+#define H3800_ASIC2_TIMER_CLK_1            ( 1 << 4 )    /* Clock enable, counter 1 */
+#define H3800_ASIC2_TIMER_CLK_2            ( 1 << 5 )    /* Clock enable, counter 2 */
+#define H3800_ASIC2_TIMER_MODE_0           ( 1 << 6 )    /* Mode 0 enable, counter 0 */
+#define H3800_ASIC2_TIMER_MODE_1           ( 1 << 7 )    /* Mode 0 enable, counter 1 */
+
+#define _H3800_ASIC2_CLOCK_Base                0x1000
+#define _H3800_ASIC2_CLOCK_Enable              0x0000    /* R/W  18 bits */
+
+#define H3800_ASIC2_CLOCK_Enable            H3800_ASIC2_OFFSET( u32, CLOCK, Enable )
+
+#define H3800_ASIC2_CLOCK_AUDIO_1              0x0001    /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */
+#define H3800_ASIC2_CLOCK_AUDIO_2              0x0002    /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */
+#define H3800_ASIC2_CLOCK_AUDIO_3              0x0004    /* Enable 5.6 MHz clock for 11 kHZ sample rate */
+#define H3800_ASIC2_CLOCK_AUDIO_4              0x0008    /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */
+#define H3800_ASIC2_CLOCK_ADC              ( 1 << 4 )    /* 1.024 MHz clock to ADC */
+#define H3800_ASIC2_CLOCK_SPI              ( 1 << 5 )    /* 4.096 MHz clock to SPI */
+#define H3800_ASIC2_CLOCK_OWM              ( 1 << 6 )    /* 4.096 MHz clock to OWM */
+#define H3800_ASIC2_CLOCK_PWM              ( 1 << 7 )    /* 2.048 MHz clock to PWM */
+#define H3800_ASIC2_CLOCK_UART_1           ( 1 << 8 )    /* 24.576 MHz clock to UART1 (turn off bit 16) */
+#define H3800_ASIC2_CLOCK_UART_0           ( 1 << 9 )    /* 24.576 MHz clock to UART0 (turn off bit 17) */
+#define H3800_ASIC2_CLOCK_SD_1             ( 1 << 10 )   /* 16.934 MHz to SD */
+#define H3800_ASIC2_CLOCK_SD_2             ( 2 << 10 )   /* 24.576 MHz to SD */
+#define H3800_ASIC2_CLOCK_SD_3             ( 3 << 10 )   /* 33.869 MHz to SD */
+#define H3800_ASIC2_CLOCK_SD_4             ( 4 << 10 )   /* 49.152 MHz to SD */
+#define H3800_ASIC2_CLOCK_EX0              ( 1 << 13 )   /* Enable 32.768 kHz crystal */
+#define H3800_ASIC2_CLOCK_EX1              ( 1 << 14 )   /* Enable 24.576 MHz crystal */
+#define H3800_ASIC2_CLOCK_EX2              ( 1 << 15 )   /* Enable 33.869 MHz crystal */
+#define H3800_ASIC2_CLOCK_SLOW_UART_1      ( 1 << 16 )   /* Enable 3.686 MHz to UART1 (turn off bit 8) */
+#define H3800_ASIC2_CLOCK_SLOW_UART_0      ( 1 << 17 )   /* Enable 3.686 MHz to UART0 (turn off bit 9) */
+
+#define _H3800_ASIC2_ADC_Base                  0x1200
+#define _H3800_ASIC2_ADC_Multiplexer           0x0000    /* R/W 4 bits - low 3 bits set channel */
+#define _H3800_ASIC2_ADC_ControlStatus         0x0004    /* R/W 8 bits */
+#define _H3800_ASIC2_ADC_Data                  0x0008    /* R   10 bits */
+
+#define H3800_ASIC2_ADC_Multiplexer       H3800_ASIC2_OFFSET(  u8, ADC, Multiplexer )
+#define H3800_ASIC2_ADC_ControlStatus     H3800_ASIC2_OFFSET(  u8, ADC, ControlStatus )
+#define H3800_ASIC2_ADC_Data              H3800_ASIC2_OFFSET( u16, ADC, Data )
+
+#define H3600_ASIC2_ADC_MUX_CHANNEL_MASK         0x07    /* Low 3 bits sets channel.  max = 4 */
+#define H3600_ASIC2_ADC_MUX_CLKEN          ( 1 << 3 )    /* Enable clock */
+
+#define H3600_ASIC2_ADC_CSR_ADPS_MASK            0x0f    /* Low 4 bits sets prescale, max = 8 */
+#define H3600_ASIC2_ADC_CSR_FREE_RUN       ( 1 << 4 )
+#define H3600_ASIC2_ADC_CSR_INT_ENABLE     ( 1 << 5 )
+#define H3600_ASIC2_ADC_CSR_START          ( 1 << 6 )    /* Set to start conversion.  Goes to 0 when done */
+#define H3600_ASIC2_ADC_CSR_ENABLE         ( 1 << 7 )    /* 1:power up ADC, 0:power down */
+
+
+#define _H3800_ASIC2_INTR_Base                 0x1600
+#define _H3800_ASIC2_INTR_MaskAndFlag          0x0000    /* R/(W) 8bits */
+#define _H3800_ASIC2_INTR_ClockPrescale        0x0004    /* R/(W) 5bits */
+#define _H3800_ASIC2_INTR_TimerSet             0x0008    /* R/(W) 8bits */
+
+#define H3800_ASIC2_INTR_MaskAndFlag      H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag )
+#define H3800_ASIC2_INTR_ClockPrescale    H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale )
+#define H3800_ASIC2_INTR_TimerSet         H3800_ASIC2_OFFSET( u8, INTR, TimerSet )
+
+#define H3800_ASIC2_INTR_GLOBAL_MASK       ( 1 << 0 )    /* Global interrupt mask */
+#define H3800_ASIC2_INTR_POWER_ON_RESET    ( 1 << 1 )    /* 01: Power on reset (bits 1 & 2 ) */
+#define H3800_ASIC2_INTR_EXTERNAL_RESET    ( 2 << 1 )    /* 10: External reset (bits 1 & 2 ) */
+#define H3800_ASIC2_INTR_MASK_UART_0       ( 1 << 4 )
+#define H3800_ASIC2_INTR_MASK_UART_1       ( 1 << 5 )
+#define H3800_ASIC2_INTR_MASK_TIMER        ( 1 << 6 )
+#define H3800_ASIC2_INTR_MASK_OWM          ( 1 << 7 )
+
+#define H3800_ASIC2_INTR_CLOCK_PRESCALE          0x0f    /* 4 bits, max 14 */
+#define H3800_ASIC2_INTR_SET               ( 1 << 4 )    /* Time base enable */
+
+
+#define _H3800_ASIC2_OWM_Base                  0x1800
+#define _H3800_ASIC2_OWM_Command               0x0000    /* R/W 4 bits command register */
+#define _H3800_ASIC2_OWM_Data                  0x0004    /* R/W 8 bits, transmit / receive buffer */
+#define _H3800_ASIC2_OWM_Interrupt             0x0008    /* R/W Command register */
+#define _H3800_ASIC2_OWM_InterruptEnable       0x000c    /* R/W Command register */
+#define _H3800_ASIC2_OWM_ClockDivisor          0x0010    /* R/W 5 bits of divisor and pre-scale */
+
+#define H3800_ASIC2_OWM_Command            H3800_ASIC2_OFFSET( u8, OWM, Command )
+#define H3800_ASIC2_OWM_Data               H3800_ASIC2_OFFSET( u8, OWM, Data )
+#define H3800_ASIC2_OWM_Interrupt          H3800_ASIC2_OFFSET( u8, OWM, Interrupt )
+#define H3800_ASIC2_OWM_InterruptEnable    H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable )
+#define H3800_ASIC2_OWM_ClockDivisor       H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor )
+
+#define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 )    /* Set to force reset on 1-wire bus */
+#define H3800_ASIC2_OWM_CMD_SRA            ( 1 << 1 )    /* Set to switch to Search ROM accelerator mode */
+#define H3800_ASIC2_OWM_CMD_DQ_OUTPUT      ( 1 << 2 )    /* Write only - forces bus low */
+#define H3800_ASIC2_OWM_CMD_DQ_INPUT       ( 1 << 3 )    /* Read only - reflects state of bus */
+
+#define H3800_ASIC2_OWM_INT_PD             ( 1 << 0 )    /* Presence detect */
+#define H3800_ASIC2_OWM_INT_PDR            ( 1 << 1 )    /* Presence detect result */
+#define H3800_ASIC2_OWM_INT_TBE            ( 1 << 2 )    /* Transmit buffer empty */
+#define H3800_ASIC2_OWM_INT_TEMT           ( 1 << 3 )    /* Transmit shift register empty */
+#define H3800_ASIC2_OWM_INT_RBF            ( 1 << 4 )    /* Receive buffer full */
+
+#define H3800_ASIC2_OWM_INTEN_EPD          ( 1 << 0 )    /* Enable receive buffer full interrupt */
+#define H3800_ASIC2_OWM_INTEN_IAS          ( 1 << 1 )    /* Enable transmit shift register empty interrupt */
+#define H3800_ASIC2_OWM_INTEN_ETBE         ( 1 << 2 )    /* Enable transmit buffer empty interrupt */
+#define H3800_ASIC2_OWM_INTEN_ETMT         ( 1 << 3 )    /* INTR active state */
+#define H3800_ASIC2_OWM_INTEN_ERBF         ( 1 << 4 )    /* Enable presence detect interrupt */
+
+#define _H3800_ASIC2_FlashCtl_Base             0x1A00
+
+/****************************************************/
+/* H3800, ASIC #1
+ * This ASIC is accesed through ASIC #2, and
+ * mapped into the 1c00 - 1f00 region
+ */
+
+#define H3800_ASIC1_OFFSET(s,x,y)   \
+     (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1))))
+
+#define _H3800_ASIC1_MMC_Base             0x1c00
+
+#define _H3800_ASIC1_MMC_StartStopClock     0x00    /* R/W 8bit                                  */
+#define _H3800_ASIC1_MMC_Status             0x02    /* R   See below, default 0x0040             */
+#define _H3800_ASIC1_MMC_ClockRate          0x04    /* R/W 8bit, low 3 bits are clock divisor    */
+#define _H3800_ASIC1_MMC_SPIRegister        0x08    /* R/W 8bit, see below                       */
+#define _H3800_ASIC1_MMC_CmdDataCont        0x0a    /* R/W 8bit, write to start MMC adapter      */
+#define _H3800_ASIC1_MMC_ResponseTimeout    0x0c    /* R/W 8bit, clocks before response timeout  */
+#define _H3800_ASIC1_MMC_ReadTimeout        0x0e    /* R/W 16bit, clocks before received data timeout */
+#define _H3800_ASIC1_MMC_BlockLength        0x10    /* R/W 10bit */
+#define _H3800_ASIC1_MMC_NumOfBlocks        0x12    /* R/W 16bit, in block mode, number of blocks  */
+#define _H3800_ASIC1_MMC_InterruptMask      0x1a    /* R/W 8bit */
+#define _H3800_ASIC1_MMC_CommandNumber      0x1c    /* R/W 6 bits */
+#define _H3800_ASIC1_MMC_ArgumentH          0x1e    /* R/W 16 bits  */
+#define _H3800_ASIC1_MMC_ArgumentL          0x20    /* R/W 16 bits */
+#define _H3800_ASIC1_MMC_ResFifo            0x22    /* R   8 x 16 bits - contains response FIFO */
+#define _H3800_ASIC1_MMC_BufferPartFull     0x28    /* R/W 8 bits */
+
+#define H3800_ASIC1_MMC_StartStopClock    H3800_ASIC1_OFFSET(  u8, MMC, StartStopClock )
+#define H3800_ASIC1_MMC_Status            H3800_ASIC1_OFFSET( u16, MMC, Status )
+#define H3800_ASIC1_MMC_ClockRate         H3800_ASIC1_OFFSET(  u8, MMC, ClockRate )
+#define H3800_ASIC1_MMC_SPIRegister       H3800_ASIC1_OFFSET(  u8, MMC, SPIRegister )
+#define H3800_ASIC1_MMC_CmdDataCont       H3800_ASIC1_OFFSET(  u8, MMC, CmdDataCont )
+#define H3800_ASIC1_MMC_ResponseTimeout   H3800_ASIC1_OFFSET(  u8, MMC, ResponseTimeout )
+#define H3800_ASIC1_MMC_ReadTimeout       H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout )
+#define H3800_ASIC1_MMC_BlockLength       H3800_ASIC1_OFFSET( u16, MMC, BlockLength )
+#define H3800_ASIC1_MMC_NumOfBlocks       H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks )
+#define H3800_ASIC1_MMC_InterruptMask     H3800_ASIC1_OFFSET(  u8, MMC, InterruptMask )
+#define H3800_ASIC1_MMC_CommandNumber     H3800_ASIC1_OFFSET(  u8, MMC, CommandNumber )
+#define H3800_ASIC1_MMC_ArgumentH         H3800_ASIC1_OFFSET( u16, MMC, ArgumentH )
+#define H3800_ASIC1_MMC_ArgumentL         H3800_ASIC1_OFFSET( u16, MMC, ArgumentL )
+#define H3800_ASIC1_MMC_ResFifo           H3800_ASIC1_OFFSET( u16, MMC, ResFifo )
+#define H3800_ASIC1_MMC_BufferPartFull    H3800_ASIC1_OFFSET(  u8, MMC, BufferPartFull )
+
+#define H3800_ASIC1_MMC_STOP_CLOCK                   (1 << 0)   /* Write to "StartStopClock" register */
+#define H3800_ASIC1_MMC_START_CLOCK                  (1 << 1)
+
+#define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT          (1 << 0)
+#define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT      (1 << 1)
+#define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR       (1 << 2)
+#define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR        (1 << 3)
+#define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR        (1 << 4)  /* SPI data token error received */
+#define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR    (1 << 5)
+#define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY            (1 << 6)
+#define H3800_ASIC1_MMC_STATUS_FIFO_FULL             (1 << 7)
+#define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE          (1 << 8)  /* MultiMediaCard clock stopped */
+#define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE    (1 << 11) /* Write operation, indicates transfer finished */
+#define H3800_ASIC1_MMC_STATUS_END_PROGRAM           (1 << 12) /* End write and read operations */
+#define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE  (1 << 13) /* End command response */
+
+#define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE           (1 << 0)  /* Enables SPI mode */
+#define H3800_ASIC1_MMC_SPI_REG_CRC_ON               (1 << 1)  /* 1:turn on CRC    */
+#define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE        (1 << 2)  /* 1:turn on SPI CS */
+#define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK      0x38      /* Bits 3,4,5 are the SPI CS relative address */
+
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE  0x00
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1           0x01
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2           0x02
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3           0x03
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE         (1 << 2)  /* This command contains a data transfer */
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE               (1 << 3)  /* This data transfer is a write */
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE         (1 << 4)  /* This data transfer is in stream mode */
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT            (1 << 5)  /* Busy signal expected after current cmd */
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE          (1 << 6)  /* Enables the 80 bits for initializing card */
+
+#define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE       (1 << 0)
+#define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE             (1 << 1)
+#define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE     (1 << 2)
+#define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY             (1 << 3)
+
+#define H3800_ASIC1_MMC_BUFFER_PART_FULL                  (1 << 0)
+
+/********* GPIO **********/
+
+#define _H3800_ASIC1_GPIO_Base        0x1e00
+
+#define _H3800_ASIC1_GPIO_Mask          0x30    /* R/W 0:don't mask, 1:mask interrupt */
+#define _H3800_ASIC1_GPIO_Direction     0x32    /* R/W 0:input, 1:output              */
+#define _H3800_ASIC1_GPIO_Out           0x34    /* R/W 0:output low, 1:output high    */
+#define _H3800_ASIC1_GPIO_TriggerType   0x36    /* R/W 0:level, 1:edge                */
+#define _H3800_ASIC1_GPIO_EdgeTrigger   0x38    /* R/W 0:falling, 1:rising            */
+#define _H3800_ASIC1_GPIO_LevelTrigger  0x3A    /* R/W 0:low, 1:high level detect     */
+#define _H3800_ASIC1_GPIO_LevelStatus   0x3C    /* R/W 0:none, 1:detect               */
+#define _H3800_ASIC1_GPIO_EdgeStatus    0x3E    /* R/W 0:none, 1:detect               */
+#define _H3800_ASIC1_GPIO_State         0x40    /* R   See masks below  (default 0)         */
+#define _H3800_ASIC1_GPIO_Reset         0x42    /* R/W See masks below  (default 0x04)      */
+#define _H3800_ASIC1_GPIO_SleepMask     0x44    /* R/W 0:don't mask, 1:mask trigger in sleep mode  */
+#define _H3800_ASIC1_GPIO_SleepDir      0x46    /* R/W direction 0:input, 1:ouput in sleep mode    */
+#define _H3800_ASIC1_GPIO_SleepOut      0x48    /* R/W level 0:low, 1:high in sleep mode           */
+#define _H3800_ASIC1_GPIO_Status        0x4A    /* R   Pin status                                  */
+#define _H3800_ASIC1_GPIO_BattFaultDir  0x4C    /* R/W direction 0:input, 1:output in batt_fault   */
+#define _H3800_ASIC1_GPIO_BattFaultOut  0x4E    /* R/W level 0:low, 1:high in batt_fault           */
+
+#define H3800_ASIC1_GPIO_Mask         H3800_ASIC1_OFFSET( u16, GPIO, Mask )
+#define H3800_ASIC1_GPIO_Direction    H3800_ASIC1_OFFSET( u16, GPIO, Direction )
+#define H3800_ASIC1_GPIO_Out          H3800_ASIC1_OFFSET( u16, GPIO, Out )
+#define H3800_ASIC1_GPIO_TriggerType  H3800_ASIC1_OFFSET( u16, GPIO, TriggerType )
+#define H3800_ASIC1_GPIO_EdgeTrigger  H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger )
+#define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger )
+#define H3800_ASIC1_GPIO_LevelStatus  H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus )
+#define H3800_ASIC1_GPIO_EdgeStatus   H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus )
+#define H3800_ASIC1_GPIO_State        H3800_ASIC1_OFFSET(  u8, GPIO, State )
+#define H3800_ASIC1_GPIO_Reset        H3800_ASIC1_OFFSET(  u8, GPIO, Reset )
+#define H3800_ASIC1_GPIO_SleepMask    H3800_ASIC1_OFFSET( u16, GPIO, SleepMask )
+#define H3800_ASIC1_GPIO_SleepDir     H3800_ASIC1_OFFSET( u16, GPIO, SleepDir )
+#define H3800_ASIC1_GPIO_SleepOut     H3800_ASIC1_OFFSET( u16, GPIO, SleepOut )
+#define H3800_ASIC1_GPIO_Status       H3800_ASIC1_OFFSET( u16, GPIO, Status )
+#define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir )
+#define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut )
+
+#define H3800_ASIC1_GPIO_STATE_MASK            (1 << 0)
+#define H3800_ASIC1_GPIO_STATE_DIRECTION       (1 << 1)
+#define H3800_ASIC1_GPIO_STATE_OUT             (1 << 2)
+#define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE    (1 << 3)
+#define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER    (1 << 4)
+#define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER   (1 << 5)
+
+#define H3800_ASIC1_GPIO_RESET_SOFTWARE        (1 << 0)
+#define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP      (1 << 1)
+#define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON    (1 << 2)
+
+/* These are all outputs */
+#define GPIO_H3800_ASIC1_IR_ON_N          (1 << 0)   /* Apply power to the IR Module */
+#define GPIO_H3800_ASIC1_SD_PWR_ON        (1 << 1)   /* Secure Digital power on */
+#define GPIO_H3800_ASIC1_RS232_ON         (1 << 2)   /* Turn on power to the RS232 chip ? */
+#define GPIO_H3800_ASIC1_PULSE_GEN        (1 << 3)   /* Goes to speaker / earphone */
+#define GPIO_H3800_ASIC1_CH_TIMER         (1 << 4)   /* */
+#define GPIO_H3800_ASIC1_LCD_5V_ON        (1 << 5)   /* Enables LCD_5V */
+#define GPIO_H3800_ASIC1_LCD_ON           (1 << 6)   /* Enables LCD_3V */
+#define GPIO_H3800_ASIC1_LCD_PCI          (1 << 7)   /* Connects to PDWN on LCD controller */
+#define GPIO_H3800_ASIC1_VGH_ON           (1 << 8)   /* Drives VGH on the LCD (+9??) */
+#define GPIO_H3800_ASIC1_VGL_ON           (1 << 9)   /* Drivers VGL on the LCD (-6??) */
+#define GPIO_H3800_ASIC1_FL_PWR_ON        (1 << 10)  /* Frontlight power on */
+#define GPIO_H3800_ASIC1_BT_PWR_ON        (1 << 11)  /* Bluetooth power on */
+#define GPIO_H3800_ASIC1_SPK_ON           (1 << 12)  /* */
+#define GPIO_H3800_ASIC1_EAR_ON_N         (1 << 13)  /* */
+#define GPIO_H3800_ASIC1_AUD_PWR_ON       (1 << 14)  /* */
+
+/* Write enable for the flash */
+
+#define _H3800_ASIC1_FlashWP_Base         0x1F00
+#define _H3800_ASIC1_FlashWP_VPP_ON         0x00    /* R   1: write, 0: protect */
+#define H3800_ASIC1_FlashWP_VPP_ON       H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON )
+
+#endif /* _INCLUDE_H3600_GPIO_H_ */
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h
index e29df3d215c5..8ed40e5eff31 100644
--- a/include/asm-arm/arch-sa1100/hardware.h
+++ b/include/asm-arm/arch-sa1100/hardware.h
@@ -60,6 +60,7 @@
    ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
 
 #ifndef __ASSEMBLY__
+#include <asm/types.h>
 
 #if 0
 # define __REG(x)	(*((volatile u32 *)io_p2v(x)))
@@ -93,17 +94,12 @@ typedef struct { volatile u32 offset[4096]; } __regbase;
  * This must be called *before* the corresponding IRQ is registered.
  * Use this instead of directly setting GRER/GFER.
  */
+#define GPIO_NO_EDGES		0
 #define GPIO_FALLING_EDGE       1
 #define GPIO_RISING_EDGE        2
 #define GPIO_BOTH_EDGES         3
 #ifndef __ASSEMBLY__
 extern void set_GPIO_IRQ_edge( int gpio_mask, int edge_mask );
-
-/*
- * Return the current CPU clock frequency in units of 100kHz
- */
-extern unsigned short get_cclk_frequency(void);
-
 #endif
 
 
@@ -145,9 +141,7 @@ extern unsigned short get_cclk_frequency(void);
 #include "empeg.h"
 #endif
 
-#ifdef CONFIG_SA1100_H3600
 #include "h3600.h"
-#endif
 
 #ifdef CONFIG_SA1100_ITSY
 #include "itsy.h"
@@ -185,6 +179,8 @@ extern unsigned short get_cclk_frequency(void);
 #include "adsbitsy.h"
 #endif
 
+#include "system3.h"
+
 #ifdef CONFIG_SA1101
 
 /*
@@ -211,19 +207,4 @@ extern unsigned short get_cclk_frequency(void);
 #include "flexanet.h"
 #endif
 
-#ifdef CONFIG_SA1111
-
-/*
- * The SA1111 is always located at virtual 0xf4000000.
- */
-
-#define SA1111_VBASE		0xf4000000
-
-#define SA1111_p2v( x )         ((x) - SA1111_BASE + SA1111_VBASE)
-#define SA1111_v2p( x )         ((x) - SA1111_VBASE + SA1111_BASE)
-
-#include "SA-1111.h"
-
-#endif
-
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h
index 6b57f9e205e1..c7dea8038ead 100644
--- a/include/asm-arm/arch-sa1100/io.h
+++ b/include/asm-arm/arch-sa1100/io.h
@@ -20,13 +20,4 @@
 #define __mem_pci(a)		((unsigned long)(a))
 #define __mem_isa(a)		((unsigned long)(a))
 
-/*
- * Generic virtual read/write
- */
-#define __arch_getw(a)		(*(volatile unsigned short *)(a))
-#define __arch_putw(v,a)	(*(volatile unsigned short *)(a) = (v))
-
-#define iomem_valid_addr(iomem,sz)	(1)
-#define iomem_to_phys(iomem)		(iomem)
-
 #endif
diff --git a/include/asm-arm/arch-sa1100/irqs.h b/include/asm-arm/arch-sa1100/irqs.h
index 806efb138176..cab7e59b1cd9 100644
--- a/include/asm-arm/arch-sa1100/irqs.h
+++ b/include/asm-arm/arch-sa1100/irqs.h
@@ -4,154 +4,150 @@
  * Copyright (C) 1996 Russell King
  * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus).
  * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation)
+ *
+ * 2001/11/14	RMK	Cleaned up and standardised a lot of the IRQs.
  */
-
 #include <linux/config.h>
 
-#define SA1100_IRQ(x)		(0 + (x))
-
-#define	IRQ_GPIO0		SA1100_IRQ(0)
-#define	IRQ_GPIO1		SA1100_IRQ(1)
-#define	IRQ_GPIO2		SA1100_IRQ(2)
-#define	IRQ_GPIO3		SA1100_IRQ(3)
-#define	IRQ_GPIO4		SA1100_IRQ(4)
-#define	IRQ_GPIO5		SA1100_IRQ(5)
-#define	IRQ_GPIO6		SA1100_IRQ(6)
-#define	IRQ_GPIO7		SA1100_IRQ(7)
-#define	IRQ_GPIO8		SA1100_IRQ(8)
-#define	IRQ_GPIO9		SA1100_IRQ(9)
-#define	IRQ_GPIO10		SA1100_IRQ(10)
-#define	IRQ_GPIO11_27		SA1100_IRQ(11)
-#define	IRQ_LCD  		SA1100_IRQ(12)	/* LCD controller           */
-#define	IRQ_Ser0UDC		SA1100_IRQ(13)	/* Ser. port 0 UDC          */
-#define	IRQ_Ser1SDLC		SA1100_IRQ(14)	/* Ser. port 1 SDLC         */
-#define	IRQ_Ser1UART		SA1100_IRQ(15)	/* Ser. port 1 UART         */
-#define	IRQ_Ser2ICP		SA1100_IRQ(16)	/* Ser. port 2 ICP          */
-#define	IRQ_Ser3UART		SA1100_IRQ(17)	/* Ser. port 3 UART         */
-#define	IRQ_Ser4MCP		SA1100_IRQ(18)	/* Ser. port 4 MCP          */
-#define	IRQ_Ser4SSP		SA1100_IRQ(19)	/* Ser. port 4 SSP          */
-#define	IRQ_DMA0 		SA1100_IRQ(20)	/* DMA controller channel 0 */
-#define	IRQ_DMA1 		SA1100_IRQ(21)	/* DMA controller channel 1 */
-#define	IRQ_DMA2 		SA1100_IRQ(22)	/* DMA controller channel 2 */
-#define	IRQ_DMA3 		SA1100_IRQ(23)	/* DMA controller channel 3 */
-#define	IRQ_DMA4 		SA1100_IRQ(24)	/* DMA controller channel 4 */
-#define	IRQ_DMA5 		SA1100_IRQ(25)	/* DMA controller channel 5 */
-#define	IRQ_OST0 		SA1100_IRQ(26)	/* OS Timer match 0         */
-#define	IRQ_OST1 		SA1100_IRQ(27)	/* OS Timer match 1         */
-#define	IRQ_OST2 		SA1100_IRQ(28)	/* OS Timer match 2         */
-#define	IRQ_OST3 		SA1100_IRQ(29)	/* OS Timer match 3         */
-#define	IRQ_RTC1Hz		SA1100_IRQ(30)	/* RTC 1 Hz clock           */
-#define	IRQ_RTCAlrm		SA1100_IRQ(31)	/* RTC Alarm                */
-
-#define	IRQ_GPIO_11_27(x)	(32 + (x) - 11)
-
-#define	IRQ_GPIO11		IRQ_GPIO_11_27(11)
-#define	IRQ_GPIO12		IRQ_GPIO_11_27(12)
-#define	IRQ_GPIO13		IRQ_GPIO_11_27(13)
-#define	IRQ_GPIO14		IRQ_GPIO_11_27(14)
-#define	IRQ_GPIO15		IRQ_GPIO_11_27(15)
-#define	IRQ_GPIO16		IRQ_GPIO_11_27(16)
-#define	IRQ_GPIO17		IRQ_GPIO_11_27(17)
-#define	IRQ_GPIO18		IRQ_GPIO_11_27(18)
-#define	IRQ_GPIO19		IRQ_GPIO_11_27(19)
-#define	IRQ_GPIO20		IRQ_GPIO_11_27(20)
-#define	IRQ_GPIO21		IRQ_GPIO_11_27(21)
-#define	IRQ_GPIO22		IRQ_GPIO_11_27(22)
-#define	IRQ_GPIO23		IRQ_GPIO_11_27(23)
-#define	IRQ_GPIO24		IRQ_GPIO_11_27(24)
-#define	IRQ_GPIO25		IRQ_GPIO_11_27(25)
-#define	IRQ_GPIO26		IRQ_GPIO_11_27(26)
-#define	IRQ_GPIO27		IRQ_GPIO_11_27(27)
-
-#define SA1100_GPIO_TO_IRQ(i)	(((i) < 11) ? SA1100_IRQ(i) : IRQ_GPIO_11_27(i))
-
-/* To get the GPIO number from an IRQ number */
-#define GPIO_11_27_IRQ(i)	(11 + (i) - 32)
-#define SA1100_IRQ_TO_GPIO(i) 	(((i) < 11) ? (i) : GPIO_11_27_IRQ(i))
-
-#define	NR_IRQS		(IRQ_GPIO27 + 1)
-
-
-#if defined(CONFIG_SA1100_GRAPHICSCLIENT) || defined(CONFIG_SA1100_GRAPHICSMASTER)
-#define ADS_EXT_IRQ(x)	(IRQ_GPIO27 + 1 + (x))
-#undef NR_IRQS
-#define NR_IRQS		(ADS_EXT_IRQ(15) + 1)
-#endif
+#define	IRQ_GPIO0		0
+#define	IRQ_GPIO1		1
+#define	IRQ_GPIO2		2
+#define	IRQ_GPIO3		3
+#define	IRQ_GPIO4		4
+#define	IRQ_GPIO5		5
+#define	IRQ_GPIO6		6
+#define	IRQ_GPIO7		7
+#define	IRQ_GPIO8		8
+#define	IRQ_GPIO9		9
+#define	IRQ_GPIO10		10
+#define	IRQ_GPIO11_27		11
+#define	IRQ_LCD  		12	/* LCD controller           */
+#define	IRQ_Ser0UDC		13	/* Ser. port 0 UDC          */
+#define	IRQ_Ser1SDLC		14	/* Ser. port 1 SDLC         */
+#define	IRQ_Ser1UART		15	/* Ser. port 1 UART         */
+#define	IRQ_Ser2ICP		16	/* Ser. port 2 ICP          */
+#define	IRQ_Ser3UART		17	/* Ser. port 3 UART         */
+#define	IRQ_Ser4MCP		18	/* Ser. port 4 MCP          */
+#define	IRQ_Ser4SSP		19	/* Ser. port 4 SSP          */
+#define	IRQ_DMA0 		20	/* DMA controller channel 0 */
+#define	IRQ_DMA1 		21	/* DMA controller channel 1 */
+#define	IRQ_DMA2 		22	/* DMA controller channel 2 */
+#define	IRQ_DMA3 		23	/* DMA controller channel 3 */
+#define	IRQ_DMA4 		24	/* DMA controller channel 4 */
+#define	IRQ_DMA5 		25	/* DMA controller channel 5 */
+#define	IRQ_OST0 		26	/* OS Timer match 0         */
+#define	IRQ_OST1 		27	/* OS Timer match 1         */
+#define	IRQ_OST2 		28	/* OS Timer match 2         */
+#define	IRQ_OST3 		29	/* OS Timer match 3         */
+#define	IRQ_RTC1Hz		30	/* RTC 1 Hz clock           */
+#define	IRQ_RTCAlrm		31	/* RTC Alarm                */
+
+#define	IRQ_GPIO11		32
+#define	IRQ_GPIO12		33
+#define	IRQ_GPIO13		34
+#define	IRQ_GPIO14		35
+#define	IRQ_GPIO15		36
+#define	IRQ_GPIO16		37
+#define	IRQ_GPIO17		38
+#define	IRQ_GPIO18		39
+#define	IRQ_GPIO19		40
+#define	IRQ_GPIO20		41
+#define	IRQ_GPIO21		42
+#define	IRQ_GPIO22		43
+#define	IRQ_GPIO23		44
+#define	IRQ_GPIO24		45
+#define	IRQ_GPIO25		46
+#define	IRQ_GPIO26		47
+#define	IRQ_GPIO27		48
 
+/*
+ * To get the GPIO number from an IRQ number
+ */
+#define GPIO_11_27_IRQ(i)	((i) - 21)
 
-#if defined(CONFIG_SA1111)
+/*
+ * The next 16 interrupts are for board specific purposes.  Since
+ * the kernel can only run on one machine at a time, we can re-use
+ * these.  If you need more, increase IRQ_BOARD_END, but keep it
+ * within sensible limits.  IRQs 49 to 64 are available.
+ */
+#define IRQ_BOARD_START		49
+#define IRQ_BOARD_END		65
+
+#define IRQ_SA1111_START	(IRQ_BOARD_END)
+#define IRQ_GPAIN0		(IRQ_BOARD_END + 0)
+#define IRQ_GPAIN1		(IRQ_BOARD_END + 1)
+#define IRQ_GPAIN2		(IRQ_BOARD_END + 2)
+#define IRQ_GPAIN3		(IRQ_BOARD_END + 3)
+#define IRQ_GPBIN0		(IRQ_BOARD_END + 4)
+#define IRQ_GPBIN1		(IRQ_BOARD_END + 5)
+#define IRQ_GPBIN2		(IRQ_BOARD_END + 6)
+#define IRQ_GPBIN3		(IRQ_BOARD_END + 7)
+#define IRQ_GPBIN4		(IRQ_BOARD_END + 8)
+#define IRQ_GPBIN5		(IRQ_BOARD_END + 9)
+#define IRQ_GPCIN0		(IRQ_BOARD_END + 10)
+#define IRQ_GPCIN1		(IRQ_BOARD_END + 11)
+#define IRQ_GPCIN2		(IRQ_BOARD_END + 12)
+#define IRQ_GPCIN3		(IRQ_BOARD_END + 13)
+#define IRQ_GPCIN4		(IRQ_BOARD_END + 14)
+#define IRQ_GPCIN5		(IRQ_BOARD_END + 15)
+#define IRQ_GPCIN6		(IRQ_BOARD_END + 16)
+#define IRQ_GPCIN7		(IRQ_BOARD_END + 17)
+#define IRQ_MSTXINT		(IRQ_BOARD_END + 18)
+#define IRQ_MSRXINT		(IRQ_BOARD_END + 19)
+#define IRQ_MSSTOPERRINT	(IRQ_BOARD_END + 20)
+#define IRQ_TPTXINT		(IRQ_BOARD_END + 21)
+#define IRQ_TPRXINT		(IRQ_BOARD_END + 22)
+#define IRQ_TPSTOPERRINT	(IRQ_BOARD_END + 23)
+#define SSPXMTINT		(IRQ_BOARD_END + 24)
+#define SSPRCVINT		(IRQ_BOARD_END + 25)
+#define SSPROR			(IRQ_BOARD_END + 26)
+#define AUDXMTDMADONEA		(IRQ_BOARD_END + 32)
+#define AUDRCVDMADONEA		(IRQ_BOARD_END + 33)
+#define AUDXMTDMADONEB		(IRQ_BOARD_END + 34)
+#define AUDRCVDMADONEB		(IRQ_BOARD_END + 35)
+#define AUDTFSR			(IRQ_BOARD_END + 36)
+#define AUDRFSR			(IRQ_BOARD_END + 37)
+#define AUDTUR			(IRQ_BOARD_END + 38)
+#define AUDROR			(IRQ_BOARD_END + 39)
+#define AUDDTS			(IRQ_BOARD_END + 40)
+#define AUDRDD			(IRQ_BOARD_END + 41)
+#define AUDSTO			(IRQ_BOARD_END + 42)
+#define USBPWR			(IRQ_BOARD_END + 43)
+#define NIRQHCIM		(IRQ_BOARD_END + 44)
+#define IRQHCIBUFFACC		(IRQ_BOARD_END + 45)
+#define IRQHCIRMTWKP		(IRQ_BOARD_END + 46)
+#define NHCIMFCIR		(IRQ_BOARD_END + 47)
+#define USB_PORT_RESUME		(IRQ_BOARD_END + 48)
+#define S0_READY_NINT		(IRQ_BOARD_END + 49)
+#define S1_READY_NINT		(IRQ_BOARD_END + 50)
+#define S0_CD_VALID		(IRQ_BOARD_END + 51)
+#define S1_CD_VALID		(IRQ_BOARD_END + 52)
+#define S0_BVD1_STSCHG		(IRQ_BOARD_END + 53)
+#define S1_BVD1_STSCHG		(IRQ_BOARD_END + 54)
 
-#if defined(CONFIG_SA1100_GRAPHICSMASTER)
-#define	SA1111_IRQ(x)	(ADS_EXT_IRQ(15) + 1 + 1 + (x))
+/*
+ * Figure out the MAX IRQ number.
+ *
+ * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
+ * If graphicsclient or graphicsmaster, we don't have a SA1111.
+ * Otherwise, we have the standard IRQs only.
+ */
+#ifdef CONFIG_SA1111
+#define NR_IRQS			(S1_BVD1_STSCHG + 1)
+#elif defined(CONFIG_SA1100_GRAPHICSCLIENT) || \
+      defined(CONFIG_SA1100_GRAPHICSMASTER)
+#define NR_IRQS			(IRQ_BOARD_END)
 #else
-#define SA1111_IRQ(x)	(IRQ_GPIO27 + 1 + (x))
+#define NR_IRQS			(IRQ_BOARD_START)
 #endif
 
-#define GPAIN0		SA1111_IRQ(0)
-#define GPAIN1		SA1111_IRQ(1)
-#define GPAIN2		SA1111_IRQ(2)
-#define GPAIN3		SA1111_IRQ(3)
-#define GPBIN0		SA1111_IRQ(4)
-#define GPBIN1		SA1111_IRQ(5)
-#define GPBIN2		SA1111_IRQ(6)
-#define GPBIN3		SA1111_IRQ(7)
-#define GPBIN4		SA1111_IRQ(8)
-#define GPBIN5		SA1111_IRQ(9)
-#define GPCIN0		SA1111_IRQ(10)
-#define GPCIN1		SA1111_IRQ(11)
-#define GPCIN2		SA1111_IRQ(12)
-#define GPCIN3		SA1111_IRQ(13)
-#define GPCIN4		SA1111_IRQ(14)
-#define GPCIN5		SA1111_IRQ(15)
-#define GPCIN6		SA1111_IRQ(16)
-#define GPCIN7		SA1111_IRQ(17)
-#define MSTXINT		SA1111_IRQ(18)
-#define MSRXINT		SA1111_IRQ(19)
-#define MSSTOPERRINT	SA1111_IRQ(20)
-#define TPTXINT		SA1111_IRQ(21)
-#define TPRXINT		SA1111_IRQ(22)
-#define TPSTOPERRINT	SA1111_IRQ(23)
-#define SSPXMTINT	SA1111_IRQ(24)
-#define SSPRCVINT	SA1111_IRQ(25)
-#define SSPROR		SA1111_IRQ(26)
-#define AUDXMTDMADONEA	SA1111_IRQ(32)
-#define AUDRCVDMADONEA	SA1111_IRQ(33)
-#define AUDXMTDMADONEB	SA1111_IRQ(34)
-#define AUDRCVDMADONEB	SA1111_IRQ(35)
-#define AUDTFSR		SA1111_IRQ(36)
-#define AUDRFSR		SA1111_IRQ(37)
-#define AUDTUR		SA1111_IRQ(38)
-#define AUDROR		SA1111_IRQ(39)
-#define AUDDTS		SA1111_IRQ(40)
-#define AUDRDD		SA1111_IRQ(41)
-#define AUDSTO		SA1111_IRQ(42)
-#define USBPWR		SA1111_IRQ(43)
-#define NIRQHCIM	SA1111_IRQ(44)
-#define IRQHCIBUFFACC	SA1111_IRQ(45)
-#define IRQHCIRMTWKP	SA1111_IRQ(46)
-#define NHCIMFCIR	SA1111_IRQ(47)
-#define USB_PORT_RESUME	SA1111_IRQ(48)
-#define S0_READY_NINT	SA1111_IRQ(49)
-#define S1_READY_NINT	SA1111_IRQ(50)
-#define S0_CD_VALID	SA1111_IRQ(51)
-#define S1_CD_VALID	SA1111_IRQ(52)
-#define S0_BVD1_STSCHG	SA1111_IRQ(53)
-#define S1_BVD1_STSCHG	SA1111_IRQ(54)
-
-#define SA1111_IRQ_MAX	SA1111_IRQ(54)
-
-#undef NR_IRQS
-#define NR_IRQS		(SA1111_IRQ_MAX + 1)
-
-
-#ifdef CONFIG_ASSABET_NEPONSET
-
-#define MISC_IRQ0	SA1111_IRQ(55)
-#define MISC_IRQ1	SA1111_IRQ(56)
-
-#undef NR_IRQS
-#define NR_IRQS		(SA1111_IRQ_MAX + 3)
-
-#endif  /* CONFIG_ASSABET_NEPONSET */
+/*
+ * Board specific IRQs.  Define them here.
+ * Do not surround them with ifdefs.
+ */
+#define IRQ_NEPONSET_SMC9196	(IRQ_BOARD_START + 0)
+#define IRQ_NEPONSET_USAR	(IRQ_BOARD_START + 1)
 
-#endif  /* CONFIG_SA1111 */
+/* PT Digital Board Interrupts (CONFIG_SA1100_PT_SYSTEM3) */
+#define IRQ_SYSTEM3_SMC9196	(IRQ_BOARD_START + 0)
diff --git a/include/asm-arm/arch-sa1100/keyboard.h b/include/asm-arm/arch-sa1100/keyboard.h
index 7439c09cf7b0..0207ba65ed6e 100644
--- a/include/asm-arm/arch-sa1100/keyboard.h
+++ b/include/asm-arm/arch-sa1100/keyboard.h
@@ -13,7 +13,7 @@
 #define kbd_disable_irq()	do { } while(0);
 #define kbd_enable_irq()	do { } while(0);
 
-extern void sa1111_kbd_init_hw(void);
+extern int sa1111_kbd_init_hw(void);
 extern void gc_kbd_init_hw(void);
 extern void smartio_kbd_init_hw(void);
 extern void cerf_kbd_init_hw(void);
@@ -31,6 +31,11 @@ static inline void kbd_init_hw(void)
 	if (machine_is_cerf())
 		cerf_kbd_init_hw();
 #endif
+#ifdef CONFIG_SA1100_PT_SYSTEM3
+	/* TODO: add system 3 board specific functions here */
+	if (machine_is_pt_system3())
+		sa1111_kbd_init_hw();
+#endif
 }
 
 #endif  /* _SA1100_KEYBOARD_H */
diff --git a/include/asm-arm/arch-sa1100/pcmcia.h b/include/asm-arm/arch-sa1100/pcmcia.h
deleted file mode 100644
index b5c1b56762c2..000000000000
--- a/include/asm-arm/arch-sa1100/pcmcia.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * linux/include/asm/arch/pcmcia.h
- *
- * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
- *
- * This file contains definitions for the low-level SA-1100 kernel PCMCIA
- * interface. Please see linux/Documentation/arm/SA1100/PCMCIA for details.
- */
-
-#ifndef _ASM_ARCH_PCMCIA
-#define _ASM_ARCH_PCMCIA
-
-
-/* Ideally, we'd support up to MAX_SOCK sockets, but the SA-1100 only
- * has support for two. This shows up in lots of hardwired ways, such
- * as the fact that MECR only has enough bits to configure two sockets.
- * Since it's so entrenched in the hardware, limiting the software
- * in this way doesn't seem too terrible.
- */
-#define SA1100_PCMCIA_MAX_SOCK   (2)
-
-
-#ifndef __ASSEMBLY__
-
-struct pcmcia_init {
-  void (*handler)(int irq, void *dev, struct pt_regs *regs);
-};
-
-struct pcmcia_state {
-  unsigned detect: 1,
-            ready: 1,
-             bvd1: 1,
-             bvd2: 1,
-           wrprot: 1,
-            vs_3v: 1,
-            vs_Xv: 1;
-};
-
-struct pcmcia_state_array {
-  unsigned int size;
-  struct pcmcia_state *state;
-};
-
-struct pcmcia_configure {
-  unsigned sock: 8,
-            vcc: 8,
-            vpp: 8,
-         output: 1,
-        speaker: 1,
-          reset: 1;
-};
-
-struct pcmcia_irq_info {
-  unsigned int sock;
-  unsigned int irq;
-};
-
-struct pcmcia_low_level {
-  int (*init)(struct pcmcia_init *);
-  int (*shutdown)(void);
-  int (*socket_state)(struct pcmcia_state_array *);
-  int (*get_irq_info)(struct pcmcia_irq_info *);
-  int (*configure_socket)(const struct pcmcia_configure *);
-};
-
-extern struct pcmcia_low_level *pcmcia_low_level;
-
-#endif  /* __ASSEMBLY__ */
-
-#endif
diff --git a/include/asm-arm/arch-sa1100/shannon.h b/include/asm-arm/arch-sa1100/shannon.h
new file mode 100644
index 000000000000..ec27d6e12140
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/shannon.h
@@ -0,0 +1,43 @@
+#ifndef _INCLUDE_SHANNON_H
+#define _INCLUDE_SHANNON_H
+
+/* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT,
+ * written by <forsyth@vitanuova.com> */
+
+#define SHANNON_GPIO_SPI_FLASH		GPIO_GPIO (0)	/* Output - Driven low, enables SPI to flash */
+#define SHANNON_GPIO_SPI_DSP		GPIO_GPIO (1)	/* Output - Driven low, enables SPI to DSP */
+/* lcd lower = GPIO 2-9 */
+#define SHANNON_GPIO_SPI_OUTPUT		GPIO_GPIO (10)	/* Output - SPI output to DSP */
+#define SHANNON_GPIO_SPI_INPUT		GPIO_GPIO (11)	/* Input  - SPI input from DSP */
+#define SHANNON_GPIO_SPI_CLOCK		GPIO_GPIO (12)	/* Output - Clock for SPI */
+#define SHANNON_GPIO_SPI_FRAME		GPIO_GPIO (13)	/* Output - Frame marker - not used */
+#define SHANNON_GPIO_SPI_RTS		GPIO_GPIO (14)	/* Input  - SPI Ready to Send */
+#define SHANNON_IRQ_GPIO_SPI_RTS	IRQ_GPIO14
+#define SHANNON_GPIO_SPI_CTS		GPIO_GPIO (15)	/* Output - SPI Clear to Send */
+#define SHANNON_GPIO_IRQ_CODEC		GPIO_GPIO (16)	/* in, irq from ucb1200 */
+#define SHANNON_IRQ_GPIO_IRQ_CODEC	IRQ_GPIO16
+#define SHANNON_GPIO_DSP_RESET		GPIO_GPIO (17)	/* Output - Drive low to reset the DSP */
+#define SHANNON_GPIO_CODEC_RESET	GPIO_GPIO (18)	/* Output - Drive low to reset the UCB1x00 */
+#define SHANNON_GPIO_U3_RTS		GPIO_GPIO (19)	/* ?? */
+#define SHANNON_GPIO_U3_CTS		GPIO_GPIO (20)	/* ?? */
+#define SHANNON_GPIO_SENSE_12V		GPIO_GPIO (21)	/* Input, 12v flash unprotect detected */
+#define SHANNON_GPIO_DISP_EN		GPIO_GPIO (22)	/* out */
+/* XXX GPIO 23 unaccounted for */
+#define SHANNON_GPIO_EJECT_0		GPIO_GPIO (24)	/* in */
+#define SHANNON_IRQ_GPIO_EJECT_0	IRQ_GPIO24
+#define SHANNON_GPIO_EJECT_1		GPIO_GPIO (25)	/* in */
+#define SHANNON_IRQ_GPIO_EJECT_1	IRQ_GPIO25
+#define SHANNON_GPIO_RDY_0		GPIO_GPIO (26)	/* in */
+#define SHANNON_IRQ_GPIO_RDY_0		IRQ_GPIO26
+#define SHANNON_GPIO_RDY_1		GPIO_GPIO (27)	/* in */
+#define SHANNON_IRQ_GPIO_RDY_1		IRQ_GPIO27
+
+/* MCP UCB codec GPIO pins... */
+
+#define SHANNON_UCB_GPIO_BACKLIGHT	9
+#define SHANNON_UCB_GPIO_BRIGHT_MASK  	7
+#define SHANNON_UCB_GPIO_BRIGHT		6
+#define SHANNON_UCB_GPIO_CONTRAST_MASK	0x3f
+#define SHANNON_UCB_GPIO_CONTRAST	0
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/system3.h b/include/asm-arm/arch-sa1100/system3.h
new file mode 100644
index 000000000000..11d24a5c1dfa
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/system3.h
@@ -0,0 +1,113 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/system3.h
+ *
+ * Copyright (C) 2001 Stefan Eletzhofer <stefan.eletzhofer@eletztrick.de>
+ *
+ * $Id: system3.h,v 1.2.4.2 2001/12/04 14:58:50 seletz Exp $
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * $Log: system3.h,v $
+ * Revision 1.2.4.2  2001/12/04 14:58:50  seletz
+ * - removed neponset hack
+ * - removed irq definitions (now in irqs.h)
+ *
+ * Revision 1.2.4.1  2001/12/04 12:51:18  seletz
+ * - re-added from linux_2_4_8_ac12_rmk1_np1_pt1
+ *
+ * Revision 1.2.2.2  2001/11/16 13:58:43  seletz
+ * - simplified cpld register access
+ *
+ * Revision 1.2.2.1  2001/10/15 16:17:20  seletz
+ * - first revision
+ *
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#error "include <asm/hardware.h> instead"
+#endif
+
+/* System 3 LCD */
+#define SYS3LCD			SKPEN0
+#define SYS3LCDBACKL	SKPEN1
+#define SYS3LCDBRIGHT	SKPWM0
+#define SYS3LCDCONTR	SKPWM1
+
+#define PT_CPLD_BASE		(0x10000000)
+#define PT_SMC_BASE			(0x18000000)
+#define PT_SA1111_BASE		(0x40000000)
+
+#define SA1111_BASE			PT_SA1111_BASE
+
+#define Ptcpld_p2v( x )	((x) - PT_CPLD_BASE + 0xf3000000)
+#define Ptcpld_v2p( x )	((x) - 0xf3000000 + PT_CPLD_BASE)
+
+#define _PT_SYSID	( PT_CPLD_BASE + 0x00 )
+#define _PT_IRQSR	( PT_CPLD_BASE + 0x24 )
+#define _PT_CTRL0	( PT_CPLD_BASE + 0x90 )
+#define _PT_CTRL1	( PT_CPLD_BASE + 0xA0 )
+#define _PT_CTRL2	( PT_CPLD_BASE + 0xB0 )
+
+#define PT_SYSID	(*((volatile u_char *)Ptcpld_p2v( _PT_SYSID )))
+#define PT_IRQSR	(*((volatile u_char *)Ptcpld_p2v( _PT_IRQSR )))
+#define PT_CTRL0	(*((volatile u_char *)Ptcpld_p2v( _PT_CTRL0 )))
+#define PT_CTRL1	(*((volatile u_char *)Ptcpld_p2v( _PT_CTRL1 )))
+#define PT_CTRL2	(*((volatile u_char *)Ptcpld_p2v( _PT_CTRL2 )))
+
+#define PTCTRL0_set( x )	PT_CTRL0 |= (x)
+#define PTCTRL1_set( x )	PT_CTRL1 |= (x)
+#define PTCTRL2_set( x )	PT_CTRL2 |= (x)
+#define PTCTRL0_clear( x )	PT_CTRL0 &= ~(x)
+#define PTCTRL1_clear( x )	PT_CTRL1 &= ~(x)
+#define PTCTRL2_clear( x )	PT_CTRL2 &= ~(x)
+
+/* System ID register */
+
+/* IRQ Source Register */
+#define PT_IRQ_LAN		( 1<<0 )
+#define PT_IRQ_X		( 1<<1 )
+#define PT_IRQ_SA1111	( 1<<2 )
+#define PT_IRQ_RS1		( 1<<3 )
+#define PT_IRQ_RS1_RING	( 1<<4 )
+#define PT_IRQ_RS1_DCD	( 1<<5 )
+#define PT_IRQ_RS1_DSR	( 1<<6 )
+#define PT_IRQ_RS2		( 1<<7 )
+
+/* FIXME */
+#define PT_IRQ_USAR		( 1<<1 )
+
+/* CTRL 0 */
+#define PT_CTRL0_USBSLAVE	( 1<<0 )
+#define PT_CTRL0_USBHOST	( 1<<1 )
+#define PT_CTRL0_LCD_BL		( 1<<2 )
+#define PT_CTRL0_LAN_EN		( 1<<3 )	/* active low */
+#define PT_CTRL0_IRDA_M(x)	( (((u_char)x)&0x03)<<4 )
+#define PT_CTRL0_IRDA_M0	( 1<<4 )
+#define PT_CTRL0_IRDA_M1	( 1<<5 )
+#define PT_CTRL0_IRDA_FSEL	( 1<<6 )
+#define PT_CTRL0_LCD_EN		( 1<<7 )
+
+#define PT_CTRL0_INIT	( PT_CTRL0_USBSLAVE | PT_CTRL0_USBHOST | \
+						PT_CTRL0_LCD_BL | PT_CTRL0_LAN_EN | PT_CTRL0_LCD_EN )
+
+/* CTRL 1 */
+#define PT_CTRL1_RS3_MUX(x) ( (((u_char)x)&0x03)<<0 )
+#define PT_CTRL1_RS3_MUX0	( 1<<0 )
+#define PT_CTRL1_RS3_MUX1	( 1<<1 )
+#define PT_CTRL1_RS3_RST	( 1<<2 )
+#define PT_CTRL1_RS3_RS485_TERM	( 1<<4 )
+#define PT_CTRL1_X			( 1<<4 )
+#define PT_CTRL1_PCMCIA_A0VPP	( 1<<6 )
+#define PT_CTRL1_PCMCIA_A1VPP	( 1<<7 )
+
+#define PT_RS3_MUX_ALIRS	( 0 )
+#define PT_RS3_MUX_IDATA	( 1 )
+#define PT_RS3_MUX_RADIO	( 2 )
+#define PT_RS3_MUX_RS485	( 3 )
+
+/* CTRL 2 */
+#define PT_CTRL2_RS1_RTS	( 1<<0 )
+#define PT_CTRL2_RS1_DTR	( 1<<1 )
diff --git a/include/asm-arm/arch-sa1100/time.h b/include/asm-arm/arch-sa1100/time.h
index 701a9b94e12d..1f7dd3a84eba 100644
--- a/include/asm-arm/arch-sa1100/time.h
+++ b/include/asm-arm/arch-sa1100/time.h
@@ -10,7 +10,7 @@
  */
 
 
-#define RTC_DEF_DIVIDER		32768 - 1
+#define RTC_DEF_DIVIDER		(32768 - 1)
 #define RTC_DEF_TRIM            0
 
 static unsigned long __init sa1100_get_rtc_time(void)
@@ -63,29 +63,34 @@ static unsigned long sa1100_gettimeoffset (void)
 	return usec;
 }
 
+/*
+ * We will be entered with IRQs enabled.
+ *
+ * Loop until we get ahead of the free running timer.
+ * This ensures an exact clock tick count and time acuracy.
+ * IRQs are disabled inside the loop to ensure coherence between
+ * lost_ticks (updated in do_timer()) and the match reg value, so we
+ * can use do_gettimeofday() from interrupt handlers.
+ */
 static void sa1100_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
-	long flags;
-	int next_match;
+	unsigned int next_match;
+	unsigned long flags;
 
-	/* Loop until we get ahead of the free running timer.
-	 * This ensures an exact clock tick count and time acuracy.
-	 * IRQs are disabled inside the loop to ensure coherence between
-	 * lost_ticks (updated in do_timer()) and the match reg value, so we
-	 * can use do_gettimeofday() from interrupt handlers.
-	 */
 	do {
 		do_leds();
-		do_set_rtc();
-		save_flags_cli( flags );
+		local_irq_save(flags);
 		do_timer(regs);
 		OSSR = OSSR_M0;  /* Clear match on timer 0 */
 		next_match = (OSMR0 += LATCH);
-		restore_flags( flags );
-	} while( (signed long)(next_match - OSCR) <= 0 );
+		local_irq_restore(flags);
+		do_set_rtc();
+	} while ((signed long)(next_match - OSCR) <= 0);
+
+	do_profile(regs);
 }
 
-static inline void setup_timer (void)
+void __init time_init(void)
 {
 	gettimeoffset = sa1100_gettimeoffset;
 	set_rtc = sa1100_set_rtc;
diff --git a/include/asm-arm/arch-shark/io.h b/include/asm-arm/arch-shark/io.h
index fd5ed3856637..61abd02e5610 100644
--- a/include/asm-arm/arch-shark/io.h
+++ b/include/asm-arm/arch-shark/io.h
@@ -11,9 +11,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define iomem_valid_addr(off,sz)	(1)
-#define iomem_to_phys(off)		(off)
-
 #define IO_SPACE_LIMIT 0xffffffff
 
 /*
@@ -182,9 +179,6 @@ DECLARE_IO(long,l,"")
 #define outw(v,p)	(__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
 #define outl(v,p)	(__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
 
-#define __arch_getw(addr)	(*(volatile unsigned short *)(addr))
-#define __arch_putw(b,addr)	(*(volatile unsigned short *)(addr) = (b))
-
 /*
  * Translated address IO functions
  *
diff --git a/include/asm-arm/arch-shark/irq.h b/include/asm-arm/arch-shark/irq.h
index 5618d11fadfd..ec5c9108be4d 100644
--- a/include/asm-arm/arch-shark/irq.h
+++ b/include/asm-arm/arch-shark/irq.h
@@ -7,118 +7,4 @@
  * include/asm-arm/arch-ebsa110/irq.h
  * Copyright (C) 1996-1998 Russell King
  */
-
-#include <asm/io.h>
 #define fixup_irq(x) (x)
-
-/*
- * 8259A PIC functions to handle ISA devices:
- */
-
-/*
- * This contains the irq mask for both 8259A irq controllers,
- * Let through the cascade-interrupt no. 2 (ff-(1<<2)==fb)
- */
-static unsigned char cached_irq_mask[2] = { 0xfb, 0xff };
-
-/*
- * These have to be protected by the irq controller spinlock
- * before being called.
- */
-static void shark_disable_8259A_irq(unsigned int irq)
-{
-	unsigned int mask;
-	if (irq<8) {
-	  mask = 1 << irq;
-	  cached_irq_mask[0] |= mask;
-	} else {
-	  mask = 1 << (irq-8);
-	  cached_irq_mask[1] |= mask;
-	}
-	outb(cached_irq_mask[1],0xA1);
-	outb(cached_irq_mask[0],0x21);
-}
-
-static void shark_enable_8259A_irq(unsigned int irq)
-{
-	unsigned int mask;
-	if (irq<8) {
-	  mask = ~(1 << irq);
-	  cached_irq_mask[0] &= mask;
-	} else {
-	  mask = ~(1 << (irq-8));
-	  cached_irq_mask[1] &= mask;
-	}
-	outb(cached_irq_mask[1],0xA1);
-	outb(cached_irq_mask[0],0x21);
-}
-
-/*
- * Careful! The 8259A is a fragile beast, it pretty
- * much _has_ to be done exactly like this (mask it
- * first, _then_ send the EOI, and the order of EOI
- * to the two 8259s is important!
- */
-static void shark_mask_and_ack_8259A_irq(unsigned int irq)
-{
-        if (irq & 8) {
-                cached_irq_mask[1] |= 1 << (irq-8);
-		inb(0xA1);              /* DUMMY */
-                outb(cached_irq_mask[1],0xA1);
-        } else {
-                cached_irq_mask[0] |= 1 << irq;
-                outb(cached_irq_mask[0],0x21);
-	}
-}
-
-static void bogus_int(int irq, void *dev_id, struct pt_regs *regs)
-{
-	printk("Got interrupt %i!\n",irq);
-}
-
-static struct irqaction cascade;
-
-static __inline__ void irq_init_irq(void)
-{
-	int irq;
-
-	for (irq = 0; irq < NR_IRQS; irq++) {
-		irq_desc[irq].valid	= 1;
-		irq_desc[irq].probe_ok	= 1;
-		irq_desc[irq].mask_ack	= shark_mask_and_ack_8259A_irq;
-		irq_desc[irq].mask	= shark_disable_8259A_irq;
-		irq_desc[irq].unmask	= shark_enable_8259A_irq;
-	}
-
-	/* The PICs are initialized to level triggered and auto eoi!
-	 * If they are set to edge triggered they lose some IRQs,
-	 * if they are set to manual eoi they get locked up after
-	 * a short time
-	 */
-
-	/* init master interrupt controller */
-	outb(0x19, 0x20); /* Start init sequence, level triggered */
-        outb(0x00, 0x21); /* Vector base */
-        outb(0x04, 0x21); /* Cascade (slave) on IRQ2 */
-        outb(0x03, 0x21); /* Select 8086 mode , auto eoi*/
-	outb(0x0A, 0x20);
-	/* init slave interrupt controller */
-        outb(0x19, 0xA0); /* Start init sequence, level triggered */
-        outb(0x08, 0xA1); /* Vector base */
-        outb(0x02, 0xA1); /* Cascade (slave) on IRQ2 */
-        outb(0x03, 0xA1); /* Select 8086 mode, auto eoi */
-	outb(0x0A, 0xA0);
-	outb(cached_irq_mask[1],0xA1);
-	outb(cached_irq_mask[0],0x21);
-	//request_region(0x20,0x2,"pic1");
-	//request_region(0xA0,0x2,"pic2");
-
-	cascade.handler = bogus_int;
-	cascade.flags = 0;
-	cascade.mask = 0;
-	cascade.name = "cascade";
-	cascade.next = NULL;
-	cascade.dev_id = NULL;
-	setup_arm_irq(2,&cascade);
-	
-}
diff --git a/include/asm-arm/arch-shark/time.h b/include/asm-arm/arch-shark/time.h
index 50f781f9d98e..3d5bd8c0ca3f 100644
--- a/include/asm-arm/arch-shark/time.h
+++ b/include/asm-arm/arch-shark/time.h
@@ -46,7 +46,7 @@ static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 /*
  * Set up timer interrupt, and return the current time in seconds.
  */
-static inline void setup_timer(void)
+void __init time_init(void)
 {
         struct rtc_time r_time;
         unsigned long flags;
diff --git a/include/asm-arm/arch-tbox/irq.h b/include/asm-arm/arch-tbox/irq.h
index 3e41df159bdf..dd73ba7957d2 100644
--- a/include/asm-arm/arch-tbox/irq.h
+++ b/include/asm-arm/arch-tbox/irq.h
@@ -10,41 +10,4 @@
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
-
-#include <asm/io.h>
-
 #define fixup_irq(x) (x)
-
-extern unsigned long soft_irq_mask;
-
-static void tbox_mask_irq(unsigned int irq)
-{
-	__raw_writel(0, INTCONT + (irq << 2));
-	soft_irq_mask &= ~(1<<irq);
-}
-
-static void tbox_unmask_irq(unsigned int irq)
-{
-	soft_irq_mask |= (1<<irq);
-	__raw_writel(1, INTCONT + (irq << 2));
-}
- 
-static __inline__ void irq_init_irq(void)
-{
-	unsigned int i;
-
-	/* Disable all interrupts initially. */
-	for (i = 0; i < NR_IRQS; i++) {
-		if (i <= 10 || (i >= 12 && i <= 13)) {
-			irq_desc[i].valid	= 1;
-			irq_desc[i].probe_ok	= 0;
-			irq_desc[i].mask_ack	= tbox_mask_irq;
-			irq_desc[i].mask	= tbox_mask_irq;
-			irq_desc[i].unmask	= tbox_unmask_irq;
-			tbox_mask_irq(i);
-		} else {
-			irq_desc[i].valid	= 0;
-			irq_desc[i].probe_ok	= 0;
-		}
-	}
-}
diff --git a/include/asm-arm/arch-tbox/time.h b/include/asm-arm/arch-tbox/time.h
index 4d31c8ba64c7..fd0dab923422 100644
--- a/include/asm-arm/arch-tbox/time.h
+++ b/include/asm-arm/arch-tbox/time.h
@@ -29,15 +29,8 @@ static void timer_interrupt (int irq, void *dev_id, struct pt_regs *regs)
 	do_timer(regs);
 }
 
-static inline void setup_timer (void)
+void __init time_init(void)
 {
-	/*
-	 * Default the date to 1 Jan 1970 0:0:0
-	 * You will have to run a time daemon to set the
-	 * clock correctly at bootup
-	 */
-	xtime.tv_sec = mktime(1970, 1, 1, 0, 0, 0);
-
 	timer_irq.handler = timer_interrupt;
 	setup_arm_irq(IRQ_TIMER, &timer_irq);
 }
diff --git a/include/asm-arm/arch-tbox/vmalloc.h b/include/asm-arm/arch-tbox/vmalloc.h
index 31fe3e777083..c2e21d5dedd6 100644
--- a/include/asm-arm/arch-tbox/vmalloc.h
+++ b/include/asm-arm/arch-tbox/vmalloc.h
@@ -1,5 +1,5 @@
 /*
- * linux/include/asm-arm/arch-rpc/vmalloc.h
+ * linux/include/asm-arm/arch-tbox/vmalloc.h
  */
 
 /*
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index c3e44c92164b..de5f9ee4d5e5 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -13,3 +13,16 @@
 
 #include <asm/proc/ptrace.h>
 #include <asm/proc/assembler.h>
+
+/*
+ * Endian independent macros for shifting bytes within registers.
+ */
+#ifndef __ARMEB__
+#define pull            lsr
+#define push            lsl
+#define byte(x)         (x*8)
+#else
+#define pull            lsl
+#define push            lsr
+#define byte(x)         ((3-x)*8)
+#endif
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index 17ccfe074dc0..dbb54a4d64bd 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -258,7 +258,7 @@ extern int _find_next_zero_bit_be(void * p, int size, int offset);
 #else
 
 /*
- * These are the little endian, atomic definitions.
+ * These are the big endian, atomic definitions.
  */
 #define set_bit(nr,p)			ATOMIC_BITOP_BE(set_bit,nr,p)
 #define clear_bit(nr,p)			ATOMIC_BITOP_BE(clear_bit,nr,p)
@@ -271,7 +271,7 @@ extern int _find_next_zero_bit_be(void * p, int size, int offset);
 #define find_next_zero_bit(p,sz,off)	_find_next_zero_bit_be(p,sz,off)
 
 /*
- * These are the little endian, non-atomic definitions.
+ * These are the big endian, non-atomic definitions.
  */
 #define __set_bit(nr,p)			NONATOMIC_BITOP_BE(set_bit,nr,p)
 #define __clear_bit(nr,p)		NONATOMIC_BITOP_BE(clear_bit,nr,p)
diff --git a/include/asm-arm/checksum.h b/include/asm-arm/checksum.h
index 342d1cf8448c..aa2e98d1f76f 100644
--- a/include/asm-arm/checksum.h
+++ b/include/asm-arm/checksum.h
@@ -55,25 +55,24 @@ ip_fast_csum(unsigned char * iph, unsigned int ihl)
 	unsigned int sum, tmp1;
 
 	__asm__ __volatile__(
-	"ldr	%0, [%1], #4		@ ip_fast_csum
-	ldr	%3, [%1], #4
-	sub	%2, %2, #5
-	adds	%0, %0, %3
-	ldr	%3, [%1], #4
-	adcs	%0, %0, %3
-	ldr	%3, [%1], #4
-	adcs	%0, %0, %3
-1:	ldr	%3, [%1], #4
-	adcs	%0, %0, %3
-	tst	%2, #15
-	subne	%2, %2, #1
-	bne	1b
-	adc	%0, %0, #0
-	adds	%0, %0, %0, lsl #16
-	addcs	%0, %0, #0x10000
-	mvn	%0, %0
-	mov	%0, %0, lsr #16
-	"
+	"ldr	%0, [%1], #4		@ ip_fast_csum		\n\
+	ldr	%3, [%1], #4					\n\
+	sub	%2, %2, #5					\n\
+	adds	%0, %0, %3					\n\
+	ldr	%3, [%1], #4					\n\
+	adcs	%0, %0, %3					\n\
+	ldr	%3, [%1], #4					\n\
+1:	adcs	%0, %0, %3					\n\
+	ldr	%3, [%1], #4					\n\
+	tst	%2, #15			@ do this carefully	\n\
+	subne	%2, %2, #1		@ without destroying	\n\
+	bne	1b			@ the carry flag	\n\
+	adcs	%0, %0, %3					\n\
+	adc	%0, %0, #0					\n\
+	adds	%0, %0, %0, lsl #16				\n\
+	addcs	%0, %0, #0x10000				\n\
+	mvn	%0, %0						\n\
+	mov	%0, %0, lsr #16"
 	: "=r" (sum), "=r" (iph), "=r" (ihl), "=r" (tmp1)
 	: "1" (iph), "2" (ihl)
 	: "cc");
@@ -87,7 +86,7 @@ static inline unsigned int
 csum_fold(unsigned int sum)
 {
 	__asm__(
-	"adds	%0, %1, %1, lsl #16	@ csum_fold
+	"adds	%0, %1, %1, lsl #16	@ csum_fold		\n\
 	addcs	%0, %0, #0x10000"
 	: "=r" (sum)
 	: "r" (sum)
@@ -100,10 +99,10 @@ csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, unsigned short len,
 		   unsigned int proto, unsigned int sum)
 {
 	__asm__(
-	"adds	%0, %1, %2		@ csum_tcpudp_nofold
-	adcs	%0, %0, %3
-	adcs	%0, %0, %4
-	adcs	%0, %0, %5
+	"adds	%0, %1, %2		@ csum_tcpudp_nofold	\n\
+	adcs	%0, %0, %3					\n\
+	adcs	%0, %0, %4					\n\
+	adcs	%0, %0, %5					\n\
 	adc	%0, %0, #0"
 	: "=&r"(sum)
 	: "r" (sum), "r" (daddr), "r" (saddr), "r" (ntohs(len) << 16), "Ir" (proto << 8)
@@ -119,13 +118,13 @@ csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len,
 		  unsigned int proto, unsigned int sum)
 {
 	__asm__(
-	"adds	%0, %1, %2		@ csum_tcpudp_magic
-	adcs	%0, %0, %3
-	adcs	%0, %0, %4
-	adcs	%0, %0, %5
-	adc	%0, %0, #0
-	adds	%0, %0, %0, lsl #16
-	addcs	%0, %0, #0x10000
+	"adds	%0, %1, %2		@ csum_tcpudp_magic	\n\
+	adcs	%0, %0, %3					\n\
+	adcs	%0, %0, %4					\n\
+	adcs	%0, %0, %5					\n\
+	adc	%0, %0, #0					\n\
+	adds	%0, %0, %0, lsl #16				\n\
+	addcs	%0, %0, #0x10000				\n\
 	mvn	%0, %0"
 	: "=&r"(sum)
 	: "r" (sum), "r" (daddr), "r" (saddr), "r" (ntohs(len)), "Ir" (proto << 8)
diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h
index 5348bb4699b0..c7ce093e2085 100644
--- a/include/asm-arm/cpu-multi32.h
+++ b/include/asm-arm/cpu-multi32.h
@@ -122,6 +122,11 @@ extern struct processor {
 		 */
 		void (*set_pte)(pte_t *ptep, pte_t pte);
 	} pgtable;
+
+	struct {	/* other */
+		void (*clear_user_page)(void *page, unsigned long u_addr);
+		void (*copy_user_page)(void *to, void *from, unsigned long u_addr);
+	} misc;
 } processor;
 
 extern const struct processor arm6_processor_functions;
@@ -155,6 +160,9 @@ extern const struct processor sa110_processor_functions;
 #define cpu_set_pmd(pmdp, pmd)			processor.pgtable.set_pmd(pmdp, pmd)
 #define cpu_set_pte(ptep, pte)			processor.pgtable.set_pte(ptep, pte)
 
+#define cpu_copy_user_page(to,from,uaddr)	processor.misc.copy_user_page(to,from,uaddr)
+#define cpu_clear_user_page(page,uaddr)		processor.misc.clear_user_page(page,uaddr)
+
 #define cpu_switch_mm(pgd,tsk)			cpu_set_pgd(__virt_to_phys((unsigned long)(pgd)))
 
 #define cpu_get_pgd()	\
diff --git a/include/asm-arm/cpu-single.h b/include/asm-arm/cpu-single.h
index 0c561b7037d9..9742554641b7 100644
--- a/include/asm-arm/cpu-single.h
+++ b/include/asm-arm/cpu-single.h
@@ -11,43 +11,40 @@
  * Single CPU
  */
 #ifdef __STDC__
-#define __cpu_fn(name,x)	cpu_##name##x
+#define __catify_fn(name,x)	name##x
 #else
-#define __cpu_fn(name,x)	cpu_/**/name/**/x
+#define __catify_fn(name,x)	name/**/x
 #endif
-#define cpu_fn(name,x)		__cpu_fn(name,x)
+#define __cpu_fn(name,x)	__catify_fn(name,x)
 
 /*
  * If we are supporting multiple CPUs, then we must use a table of
  * function pointers for this lot.  Otherwise, we can optimise the
  * table away.
  */
-#define cpu_data_abort			cpu_fn(CPU_NAME,_data_abort)
-#define cpu_check_bugs			cpu_fn(CPU_NAME,_check_bugs)
-#define cpu_proc_init			cpu_fn(CPU_NAME,_proc_init)
-#define cpu_proc_fin			cpu_fn(CPU_NAME,_proc_fin)
-#define cpu_reset			cpu_fn(CPU_NAME,_reset)
-#define cpu_do_idle			cpu_fn(CPU_NAME,_do_idle)
-
-#define cpu_cache_clean_invalidate_all	cpu_fn(CPU_NAME,_cache_clean_invalidate_all)
-#define cpu_cache_clean_invalidate_range cpu_fn(CPU_NAME,_cache_clean_invalidate_range)
-#define cpu_flush_ram_page		cpu_fn(CPU_NAME,_flush_ram_page)
-
-#define cpu_dcache_invalidate_range	cpu_fn(CPU_NAME,_dcache_invalidate_range)
-#define cpu_dcache_clean_range		cpu_fn(CPU_NAME,_dcache_clean_range)
-#define cpu_dcache_clean_page		cpu_fn(CPU_NAME,_dcache_clean_page)
-#define cpu_dcache_clean_entry		cpu_fn(CPU_NAME,_dcache_clean_entry)
-
-#define cpu_icache_invalidate_range	cpu_fn(CPU_NAME,_icache_invalidate_range)
-#define cpu_icache_invalidate_page	cpu_fn(CPU_NAME,_icache_invalidate_page)
-
-#define cpu_tlb_invalidate_all		cpu_fn(CPU_NAME,_tlb_invalidate_all)
-#define cpu_tlb_invalidate_range	cpu_fn(CPU_NAME,_tlb_invalidate_range)
-#define cpu_tlb_invalidate_page		cpu_fn(CPU_NAME,_tlb_invalidate_page)
-
-#define cpu_set_pgd			cpu_fn(CPU_NAME,_set_pgd)
-#define cpu_set_pmd			cpu_fn(CPU_NAME,_set_pmd)
-#define cpu_set_pte			cpu_fn(CPU_NAME,_set_pte)
+#define cpu_data_abort			__cpu_fn(CPU_ABRT,_abort)
+#define cpu_check_bugs			__cpu_fn(CPU_NAME,_check_bugs)
+#define cpu_proc_init			__cpu_fn(CPU_NAME,_proc_init)
+#define cpu_proc_fin			__cpu_fn(CPU_NAME,_proc_fin)
+#define cpu_reset			__cpu_fn(CPU_NAME,_reset)
+#define cpu_do_idle			__cpu_fn(CPU_NAME,_do_idle)
+#define cpu_cache_clean_invalidate_all	__cpu_fn(CPU_NAME,_cache_clean_invalidate_all)
+#define cpu_cache_clean_invalidate_range __cpu_fn(CPU_NAME,_cache_clean_invalidate_range)
+#define cpu_flush_ram_page		__cpu_fn(CPU_NAME,_flush_ram_page)
+#define cpu_dcache_invalidate_range	__cpu_fn(CPU_NAME,_dcache_invalidate_range)
+#define cpu_dcache_clean_range		__cpu_fn(CPU_NAME,_dcache_clean_range)
+#define cpu_dcache_clean_page		__cpu_fn(CPU_NAME,_dcache_clean_page)
+#define cpu_dcache_clean_entry		__cpu_fn(CPU_NAME,_dcache_clean_entry)
+#define cpu_icache_invalidate_range	__cpu_fn(CPU_NAME,_icache_invalidate_range)
+#define cpu_icache_invalidate_page	__cpu_fn(CPU_NAME,_icache_invalidate_page)
+#define cpu_tlb_invalidate_all		__cpu_fn(CPU_NAME,_tlb_invalidate_all)
+#define cpu_tlb_invalidate_range	__cpu_fn(CPU_NAME,_tlb_invalidate_range)
+#define cpu_tlb_invalidate_page		__cpu_fn(CPU_NAME,_tlb_invalidate_page)
+#define cpu_set_pgd			__cpu_fn(CPU_NAME,_set_pgd)
+#define cpu_set_pmd			__cpu_fn(CPU_NAME,_set_pmd)
+#define cpu_set_pte			__cpu_fn(CPU_NAME,_set_pte)
+#define cpu_copy_user_page		__cpu_fn(MMU_ARCH,_copy_user_page)
+#define cpu_clear_user_page		__cpu_fn(MMU_ARCH,_clear_user_page)
 
 #ifndef __ASSEMBLY__
 
@@ -83,6 +80,10 @@ extern void cpu_tlb_invalidate_page(unsigned long address, int flags);
 extern void cpu_set_pgd(unsigned long pgd_phys);
 extern void cpu_set_pmd(pmd_t *pmdp, pmd_t pmd);
 extern void cpu_set_pte(pte_t *ptep, pte_t pte);
+
+extern void cpu_copy_user_page(void *to, void *from, unsigned long u_addr);
+extern void cpu_clear_user_page(void *page, unsigned long u_addr);
+
 extern volatile void cpu_reset(unsigned long addr);
 
 #define cpu_switch_mm(pgd,tsk) cpu_set_pgd(__virt_to_phys((unsigned long)(pgd)))
diff --git a/include/asm-arm/hardware/clps7111.h b/include/asm-arm/hardware/clps7111.h
index 491dd73bf211..8d3228dc1778 100644
--- a/include/asm-arm/hardware/clps7111.h
+++ b/include/asm-arm/hardware/clps7111.h
@@ -27,8 +27,10 @@
 
 #ifndef __ASSEMBLY__
 #define clps_readb(off)		__raw_readb(CLPS7111_BASE + (off))
+#define clps_readw(off)		__raw_readw(CLPS7111_BASE + (off))
 #define clps_readl(off)		__raw_readl(CLPS7111_BASE + (off))
 #define clps_writeb(val,off)	__raw_writeb(val, CLPS7111_BASE + (off))
+#define clps_writew(val,off)	__raw_writew(val, CLPS7111_BASE + (off))
 #define clps_writel(val,off)	__raw_writel(val, CLPS7111_BASE + (off))
 #endif
 
@@ -48,6 +50,7 @@
 #define INTSR1		(0x0240)
 #define INTMR1		(0x0280)
 #define LCDCON		(0x02c0)
+#define TC1D            (0x0300)
 #define TC2D		(0x0340)
 #define RTCDR		(0x0380)
 #define RTCMR		(0x03c0)
diff --git a/include/asm-arm/hardware/cs89712.h b/include/asm-arm/hardware/cs89712.h
new file mode 100644
index 000000000000..ad99a3e1b802
--- /dev/null
+++ b/include/asm-arm/hardware/cs89712.h
@@ -0,0 +1,49 @@
+/*
+ *  linux/include/asm-arm/hardware/cs89712.h
+ *
+ *  This file contains the hardware definitions of the CS89712
+ *  additional internal registers.
+ *
+ *  Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de>
+ *			
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_HARDWARE_CS89712_H
+#define __ASM_HARDWARE_CS89712_H
+
+/*
+*	CS89712 additional registers
+*/
+                                  
+#define PCDR			0x0002	/* Port C Data register ---------------------------- */
+#define PCDDR			0x0042	/* Port C Data Direction register ------------------ */
+#define SDCONF			0x2300  /* SDRAM Configuration register ---------------------*/
+#define SDRFPR			0x2340  /* SDRAM Refresh period register --------------------*/
+
+#define SDCONF_ACTIVE		(1 << 10)
+#define SDCONF_CLKCTL		(1 << 9)
+#define SDCONF_WIDTH_4		(0 << 7)
+#define SDCONF_WIDTH_8		(1 << 7)
+#define SDCONF_WIDTH_16		(2 << 7)
+#define SDCONF_WIDTH_32		(3 << 7)
+#define SDCONF_SIZE_16		(0 << 5)
+#define SDCONF_SIZE_64		(1 << 5)
+#define SDCONF_SIZE_128		(2 << 5)
+#define SDCONF_SIZE_256		(3 << 5)
+#define SDCONF_CASLAT_2		(2)
+#define SDCONF_CASLAT_3		(3)
+
+#endif /* __ASM_HARDWARE_CS89712_H */
diff --git a/include/asm-arm/hardware/ep7212.h b/include/asm-arm/hardware/ep7212.h
index 16deaf2b3cf2..0e952e747073 100644
--- a/include/asm-arm/hardware/ep7212.h
+++ b/include/asm-arm/hardware/ep7212.h
@@ -23,8 +23,6 @@
 #ifndef __ASM_HARDWARE_EP7212_H
 #define __ASM_HARDWARE_EP7212_H
 
-#include <linux/config.h>
-
 /*
  * define EP7212_BASE to be the base address of the region
  * you want to access.
@@ -49,10 +47,6 @@
 #define INTSR3			0x2240
 #define INTMR3			0x2280
 #define LEDFLSH			0x22c0
-#if defined (CONFIG_ARCH_CDB89712)
-#define SDCONF			0x2300
-#define SDRFPR			0x2340
-#endif
 
 #define DAIR_DAIEN		(1 << 16)
 #define DAIR_ECS		(1 << 17)
@@ -86,19 +80,4 @@
 #define SYSCON3_FASTWAKE	(1 << 8)
 #define SYSCON3_DAIEN		(1 << 9)
 
-#if defined (CONFIG_ARCH_CDB89712)
-#define SDCONF_ACTIVE		(1 << 10)
-#define SDCONF_CLKCTL		(1 << 9)
-#define SDCONF_WIDTH_4		(0 << 7)
-#define SDCONF_WIDTH_8		(1 << 7)
-#define SDCONF_WIDTH_16		(2 << 7)
-#define SDCONF_WIDTH_32		(3 << 7)
-#define SDCONF_SIZE_16		(0 << 5)
-#define SDCONF_SIZE_64		(1 << 5)
-#define SDCONF_SIZE_128		(2 << 5)
-#define SDCONF_SIZE_256		(3 << 5)
-#define SDCONF_CASLAT_2		(2)
-#define SDCONF_CASLAT_3		(3)
-#endif
-
 #endif /* __ASM_HARDWARE_EP7212_H */
diff --git a/include/asm-arm/hardware/ioc.h b/include/asm-arm/hardware/ioc.h
index 644aebdb24a8..b3b46ef65943 100644
--- a/include/asm-arm/hardware/ioc.h
+++ b/include/asm-arm/hardware/ioc.h
@@ -19,8 +19,8 @@
  * We use __raw_base variants here so that we give the compiler the
  * chance to keep IOC_BASE in a register.
  */
-#define ioc_readb(off)		__raw_base_readb(IOC_BASE, (off))
-#define ioc_writeb(val,off)	__raw_base_writeb(val, IOC_BASE, (off))
+#define ioc_readb(off)		__raw_readb(IOC_BASE + (off))
+#define ioc_writeb(val,off)	__raw_writeb(val, IOC_BASE + (off))
 
 #endif
 
diff --git a/include/asm-arm/hardware/iomd.h b/include/asm-arm/hardware/iomd.h
index 91acb77876f8..decb1438c321 100644
--- a/include/asm-arm/hardware/iomd.h
+++ b/include/asm-arm/hardware/iomd.h
@@ -21,10 +21,10 @@
  * We use __raw_base variants here so that we give the compiler the
  * chance to keep IOC_BASE in a register.
  */
-#define iomd_readb(off)		__raw_base_readb(IOMD_BASE, (off))
-#define iomd_readl(off)		__raw_base_readl(IOMD_BASE, (off))
-#define iomd_writeb(val,off)	__raw_base_writeb(val, IOMD_BASE, (off))
-#define iomd_writel(val,off)	__raw_base_writel(val, IOMD_BASE, (off))
+#define iomd_readb(off)		__raw_readb(IOMD_BASE + (off))
+#define iomd_readl(off)		__raw_readl(IOMD_BASE + (off))
+#define iomd_writeb(val,off)	__raw_writeb(val, IOMD_BASE + (off))
+#define iomd_writel(val,off)	__raw_writel(val, IOMD_BASE + (off))
 
 #endif
 
diff --git a/include/asm-arm/hardware/linkup-l1110.h b/include/asm-arm/hardware/linkup-l1110.h
new file mode 100644
index 000000000000..7ec91168a576
--- /dev/null
+++ b/include/asm-arm/hardware/linkup-l1110.h
@@ -0,0 +1,48 @@
+/*
+*
+* Definitions for H3600 Handheld Computer
+*
+* Copyright 2001 Compaq Computer Corporation.
+*
+* Use consistent with the GNU GPL is permitted,
+* provided that this copyright notice is
+* preserved in its entirety in all copies and derived works.
+*
+* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+* FITNESS FOR ANY PARTICULAR PURPOSE.
+*
+* Author: Jamey Hicks.
+*
+*/
+
+/* LinkUp Systems PCCard/CompactFlash Interface for SA-1100 */
+
+/* PC Card Status Register */
+#define LINKUP_PRS_S1	(1 << 0) /* voltage control bits S1-S4 */
+#define LINKUP_PRS_S2	(1 << 1)
+#define LINKUP_PRS_S3	(1 << 2)
+#define LINKUP_PRS_S4	(1 << 3)
+#define LINKUP_PRS_BVD1	(1 << 4)
+#define LINKUP_PRS_BVD2	(1 << 5)
+#define LINKUP_PRS_VS1	(1 << 6)
+#define LINKUP_PRS_VS2	(1 << 7)
+#define LINKUP_PRS_RDY	(1 << 8)
+#define LINKUP_PRS_CD1	(1 << 9)
+#define LINKUP_PRS_CD2	(1 << 10)
+
+/* PC Card Command Register */
+#define LINKUP_PRC_S1	(1 << 0)
+#define LINKUP_PRC_S2	(1 << 1)
+#define LINKUP_PRC_S3	(1 << 2)
+#define LINKUP_PRC_S4	(1 << 3)
+#define LINKUP_PRC_RESET (1 << 4)
+#define LINKUP_PRC_APOE	(1 << 5) /* Auto Power Off Enable: clears S1-S4 when either nCD goes high */
+#define LINKUP_PRC_CFE	(1 << 6) /* CompactFlash mode Enable: addresses A[10:0] only, A[25:11] high */
+#define LINKUP_PRC_SOE	(1 << 7) /* signal output driver enable */
+#define LINKUP_PRC_SSP	(1 << 8) /* sock select polarity: 0 for socket 0, 1 for socket 1 */
+#define LINKUP_PRC_MBZ	(1 << 15) /* must be zero */
+
+struct linkup_l1110 {
+	volatile short prc;
+};
diff --git a/include/asm-arm/hardware/sa1111.h b/include/asm-arm/hardware/sa1111.h
new file mode 100644
index 000000000000..baa862392e04
--- /dev/null
+++ b/include/asm-arm/hardware/sa1111.h
@@ -0,0 +1,678 @@
+/*
+ * linux/include/asm-arm/hardware/SA-1111.h
+ *
+ * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
+ *
+ * This file contains definitions for the SA-1111 Companion Chip.
+ * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
+ *
+ * Macro that calculates real address for registers in the SA-1111
+ */
+
+#ifndef _ASM_ARCH_SA1111
+#define _ASM_ARCH_SA1111
+
+#include <asm/arch/bitfield.h>
+
+/*
+ * The SA1111 is always located at virtual 0xf4000000, and is always
+ * "native" endian.
+ */
+
+#define SA1111_VBASE		0xf4000000
+
+/* Don't use these! */
+#define SA1111_p2v( x )         ((x) - SA1111_BASE + SA1111_VBASE)
+#define SA1111_v2p( x )         ((x) - SA1111_VBASE + SA1111_BASE)
+
+#ifndef __ASSEMBLY__
+
+extern struct resource sa1111_resource;
+#define _SA1111(x)	((x) + sa1111_resource.start)
+#endif
+
+/*
+ * 26 bits of the SA-1110 address bus are available to the SA-1111.
+ * Use these when feeding target addresses to the DMA engines.
+ */
+
+#define SA1111_ADDR_WIDTH	(26)
+#define SA1111_ADDR_MASK	((1<<SA1111_ADDR_WIDTH)-1)
+#define SA1111_DMA_ADDR(x)	((x)&SA1111_ADDR_MASK)
+
+/*
+ * Don't ask the (SAC) DMA engines to move less than this amount.
+ */
+
+#define SA1111_SAC_DMA_MIN_XFER	(0x800)
+
+/*
+ * SA1111 register definitions.
+ */
+#define __CCREG(x)	__REGP(SA1111_VBASE + (x))
+
+/* System Bus Interface (SBI)
+ *
+ * Registers
+ *    SKCR	Control Register
+ *    SMCR	Shared Memory Controller Register
+ *    SKID	ID Register
+ */
+#define SA1111_SKCR	0x0000
+#define SA1111_SMCR	0x0004
+#define SA1111_SKID	0x0008
+
+#define _SBI_SKCR	_SA1111(SA1111_SKCR)
+#define _SBI_SMCR	_SA1111(SA1111_SMCR)
+#define _SBI_SKID	_SA1111(SA1111_SKID)
+
+#if LANGUAGE == C
+
+#define SBI_SKCR	__CCREG(SA1111_SKCR)
+#define SBI_SMCR	__CCREG(SA1111_SMCR)
+#define SBI_SKID	__CCREG(SA1111_SKID)
+
+#endif  /* LANGUAGE == C */
+
+#define SKCR_PLL_BYPASS	(1<<0)
+#define SKCR_RCLKEN	(1<<1)
+#define SKCR_SLEEP	(1<<2)
+#define SKCR_DOZE	(1<<3)
+#define SKCR_VCO_OFF	(1<<4)
+#define SKCR_SCANTSTEN	(1<<5)
+#define SKCR_CLKTSTEN	(1<<6)
+#define SKCR_RDYEN	(1<<7)
+#define SKCR_SELAC	(1<<8)
+#define SKCR_OPPC	(1<<9)
+#define SKCR_PLLTSTEN	(1<<10)
+#define SKCR_USBIOTSTEN	(1<<11)
+/*
+ * Don't believe the specs!  Take them, throw them outside.  Leave them
+ * there for a week.  Spit on them.  Walk on them.  Stamp on them.
+ * Pour gasoline over them and finally burn them.  Now think about coding.
+ *  - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
+ *  - The Feb 2001 errata (278260-010) says that the previous errata
+ *    (278260-009) is wrong, and its bit actually 12, fixed in spec
+ *    278242-003.
+ *  - The SA1111 manual (278242) says bit 12, but 0 to enable.
+ *  - Reality is bit 13, 1 to enable.
+ *      -- rmk
+ */
+#define SKCR_OE_EN	(1<<13)
+
+#define SMCR_DTIM	(1<<0)
+#define SMCR_MBGE	(1<<1)
+#define SMCR_DRAC_0	(1<<2)
+#define SMCR_DRAC_1	(1<<3)
+#define SMCR_DRAC_2	(1<<4)
+#define SMCR_DRAC	Fld(3, 2)
+#define SMCR_CLAT	(1<<5)
+
+#define SKID_SIREV_MASK	(0x000000f0)
+#define SKID_MTREV_MASK (0x0000000f)
+#define SKID_ID_MASK	(0xffffff00)
+#define SKID_SA1111_ID	(0x690cc200)
+
+/*
+ * System Controller
+ *
+ * Registers
+ *    SKPCR	Power Control Register
+ *    SKCDR	Clock Divider Register
+ *    SKAUD	Audio Clock Divider Register
+ *    SKPMC	PS/2 Mouse Clock Divider Register
+ *    SKPTC	PS/2 Track Pad Clock Divider Register
+ *    SKPEN0	PWM0 Enable Register
+ *    SKPWM0	PWM0 Clock Register
+ *    SKPEN1	PWM1 Enable Register
+ *    SKPWM1	PWM1 Clock Register
+ */
+
+#define _SKPCR		_SA1111(0x0200)
+#define _SKCDR		_SA1111(0x0204)
+#define _SKAUD		_SA1111(0x0208)
+#define _SKPMC		_SA1111(0x020c)
+#define _SKPTC		_SA1111(0x0210)
+#define _SKPEN0		_SA1111(0x0214)
+#define _SKPWM0		_SA1111(0x0218)
+#define _SKPEN1		_SA1111(0x021c)
+#define _SKPWM1		_SA1111(0x0220)
+
+#if LANGUAGE == C
+
+#define SKPCR		__CCREG(0x0200)
+#define SKCDR		__CCREG(0x0204)
+#define SKAUD		__CCREG(0x0208)
+#define SKPMC		__CCREG(0x020c)
+#define SKPTC		__CCREG(0x0210)
+#define SKPEN0		__CCREG(0x0214)
+#define SKPWM0		__CCREG(0x0218)
+#define SKPEN1		__CCREG(0x021c)
+#define SKPWM1		__CCREG(0x0220)
+
+#endif  /* LANGUAGE == C */
+
+#define SKPCR_UCLKEN	(1<<0)
+#define SKPCR_ACCLKEN	(1<<1)
+#define SKPCR_I2SCLKEN	(1<<2)
+#define SKPCR_L3CLKEN	(1<<3)
+#define SKPCR_SCLKEN	(1<<4)
+#define SKPCR_PMCLKEN	(1<<5)
+#define SKPCR_PTCLKEN	(1<<6)
+#define SKPCR_DCLKEN	(1<<7)
+#define SKPCR_PWMCLKEN	(1<<8)
+
+/*
+ * USB Host controller
+ */
+#define _USB_OHCI_OP_BASE	_SA1111( 0x400 )
+#define _USB_STATUS		_SA1111( 0x518 )
+#define _USB_RESET		_SA1111( 0x51c )
+#define _USB_INTERRUPTEST	_SA1111( 0x520 )
+
+#define _USB_EXTENT		(_USB_INTERRUPTEST - _USB_OHCI_OP_BASE + 4)
+
+#if LANGUAGE == C
+
+#define USB_OHCI_OP_BASE	__CCREG(0x0400)
+#define USB_STATUS		__CCREG(0x0518)
+#define USB_RESET		__CCREG(0x051c)
+#define USB_INTERRUPTEST	__CCReG(0x0520)
+
+#endif  /* LANGUAGE == C */
+
+#define USB_RESET_FORCEIFRESET	(1 << 0)
+#define USB_RESET_FORCEHCRESET	(1 << 1)
+#define USB_RESET_CLKGENRESET	(1 << 2)
+#define USB_RESET_SIMSCALEDOWN	(1 << 3)
+#define USB_RESET_USBINTTEST	(1 << 4)
+#define USB_RESET_SLEEPSTBYEN	(1 << 5)
+#define USB_RESET_PWRSENSELOW	(1 << 6)
+#define USB_RESET_PWRCTRLLOW	(1 << 7)
+
+/*
+ * Serial Audio Controller
+ *
+ * Registers
+ *    SACR0             Serial Audio Common Control Register
+ *    SACR1             Serial Audio Alternate Mode (I2C/MSB) Control Register
+ *    SACR2             Serial Audio AC-link Control Register
+ *    SASR0             Serial Audio I2S/MSB Interface & FIFO Status Register
+ *    SASR1             Serial Audio AC-link Interface & FIFO Status Register
+ *    SASCR             Serial Audio Status Clear Register
+ *    L3_CAR            L3 Control Bus Address Register
+ *    L3_CDR            L3 Control Bus Data Register
+ *    ACCAR             AC-link Command Address Register
+ *    ACCDR             AC-link Command Data Register
+ *    ACSAR             AC-link Status Address Register
+ *    ACSDR             AC-link Status Data Register
+ *    SADTCS            Serial Audio DMA Transmit Control/Status Register
+ *    SADTSA            Serial Audio DMA Transmit Buffer Start Address A
+ *    SADTCA            Serial Audio DMA Transmit Buffer Count Register A
+ *    SADTSB            Serial Audio DMA Transmit Buffer Start Address B
+ *    SADTCB            Serial Audio DMA Transmit Buffer Count Register B
+ *    SADRCS            Serial Audio DMA Receive Control/Status Register
+ *    SADRSA            Serial Audio DMA Receive Buffer Start Address A
+ *    SADRCA            Serial Audio DMA Receive Buffer Count Register A
+ *    SADRSB            Serial Audio DMA Receive Buffer Start Address B
+ *    SADRCB            Serial Audio DMA Receive Buffer Count Register B
+ *    SAITR             Serial Audio Interrupt Test Register
+ *    SADR              Serial Audio Data Register (16 x 32-bit)
+ */
+
+#define _SACR0          _SA1111( 0x0600 )
+#define _SACR1          _SA1111( 0x0604 )
+#define _SACR2          _SA1111( 0x0608 )
+#define _SASR0          _SA1111( 0x060c )
+#define _SASR1          _SA1111( 0x0610 )
+#define _SASCR          _SA1111( 0x0618 )
+#define _L3_CAR         _SA1111( 0x061c )
+#define _L3_CDR         _SA1111( 0x0620 )
+#define _ACCAR          _SA1111( 0x0624 )
+#define _ACCDR          _SA1111( 0x0628 )
+#define _ACSAR          _SA1111( 0x062c )
+#define _ACSDR          _SA1111( 0x0630 )
+#define _SADTCS         _SA1111( 0x0634 )
+#define _SADTSA         _SA1111( 0x0638 )
+#define _SADTCA         _SA1111( 0x063c )
+#define _SADTSB         _SA1111( 0x0640 )
+#define _SADTCB         _SA1111( 0x0644 )
+#define _SADRCS         _SA1111( 0x0648 )
+#define _SADRSA         _SA1111( 0x064c )
+#define _SADRCA         _SA1111( 0x0650 )
+#define _SADRSB         _SA1111( 0x0654 )
+#define _SADRCB         _SA1111( 0x0658 )
+#define _SAITR          _SA1111( 0x065c )
+#define _SADR           _SA1111( 0x0680 )
+
+#if LANGUAGE == C
+
+#define SACR0		__CCREG(0x0600)
+#define SACR1		__CCREG(0x0604)
+#define SACR2		__CCREG(0x0608)
+#define SASR0		__CCREG(0x060c)
+#define SASR1		__CCREG(0x0610)
+#define SASCR		__CCREG(0x0618)
+#define L3_CAR		__CCREG(0x061c)
+#define L3_CDR		__CCREG(0x0620)
+#define ACCAR		__CCREG(0x0624)
+#define ACCDR		__CCREG(0x0628)
+#define ACSAR		__CCREG(0x062c)
+#define ACSDR		__CCREG(0x0630)
+#define SADTCS		__CCREG(0x0634)
+#define SADTSA		__CCREG(0x0638)
+#define SADTCA		__CCREG(0x063c)
+#define SADTSB		__CCREG(0x0640)
+#define SADTCB		__CCREG(0x0644)
+#define SADRCS		__CCREG(0x0648)
+#define SADRSA		__CCREG(0x064c)
+#define SADRCA		__CCREG(0x0650)
+#define SADRSB		__CCREG(0x0654)
+#define SADRCB		__CCREG(0x0658)
+#define SAITR		__CCREG(0x065c)
+#define SADR		__CCREG(0x0680)
+
+#endif  /* LANGUAGE == C */
+
+#define SACR0_ENB	(1<<0)
+#define SACR0_BCKD	(1<<2)
+#define SACR0_RST	(1<<3)
+
+#define SACR1_AMSL	(1<<0)
+#define SACR1_L3EN	(1<<1)
+#define SACR1_L3MB	(1<<2)
+#define SACR1_DREC	(1<<3)
+#define SACR1_DRPL	(1<<4)
+#define SACR1_ENLBF	(1<<5)
+
+#define SACR2_TS3V	(1<<0)
+#define SACR2_TS4V	(1<<1)
+#define SACR2_WKUP	(1<<2)
+#define SACR2_DREC	(1<<3)
+#define SACR2_DRPL	(1<<4)
+#define SACR2_ENLBF	(1<<5)
+#define SACR2_RESET	(1<<6)
+
+#define SASR0_TNF	(1<<0)
+#define SASR0_RNE	(1<<1)
+#define SASR0_BSY	(1<<2)
+#define SASR0_TFS	(1<<3)
+#define SASR0_RFS	(1<<4)
+#define SASR0_TUR	(1<<5)
+#define SASR0_ROR	(1<<6)
+#define SASR0_L3WD	(1<<16)
+#define SASR0_L3RD	(1<<17)
+
+#define SASR1_TNF	(1<<0)
+#define SASR1_RNE	(1<<1)
+#define SASR1_BSY	(1<<2)
+#define SASR1_TFS	(1<<3)
+#define SASR1_RFS	(1<<4)
+#define SASR1_TUR	(1<<5)
+#define SASR1_ROR	(1<<6)
+#define SASR1_CADT	(1<<16)
+#define SASR1_SADR	(1<<17)
+#define SASR1_RSTO	(1<<18)
+#define SASR1_CLPM	(1<<19)
+#define SASR1_CRDY	(1<<20)
+#define SASR1_RS3V	(1<<21)
+#define SASR1_RS4V	(1<<22)
+
+#define SASCR_TUR	(1<<5)
+#define SASCR_ROR	(1<<6)
+#define SASCR_DTS	(1<<16)
+#define SASCR_RDD	(1<<17)
+#define SASCR_STO	(1<<18)
+
+#define SADTCS_TDEN	(1<<0)
+#define SADTCS_TDIE	(1<<1)
+#define SADTCS_TDBDA	(1<<3)
+#define SADTCS_TDSTA	(1<<4)
+#define SADTCS_TDBDB	(1<<5)
+#define SADTCS_TDSTB	(1<<6)
+#define SADTCS_TBIU	(1<<7)
+
+#define SADRCS_RDEN	(1<<0)
+#define SADRCS_RDIE	(1<<1)
+#define SADRCS_RDBDA	(1<<3)
+#define SADRCS_RDSTA	(1<<4)
+#define SADRCS_RDBDB	(1<<5)
+#define SADRCS_RDSTB	(1<<6)
+#define SADRCS_RBIU	(1<<7)
+
+#define SAD_CS_DEN	(1<<0)
+#define SAD_CS_DIE	(1<<1)	/* Not functional on metal 1 */
+#define SAD_CS_DBDA	(1<<3)	/* Not functional on metal 1 */
+#define SAD_CS_DSTA	(1<<4)
+#define SAD_CS_DBDB	(1<<5)	/* Not functional on metal 1 */
+#define SAD_CS_DSTB	(1<<6)
+#define SAD_CS_BIU	(1<<7)	/* Not functional on metal 1 */
+
+#define SAITR_TFS	(1<<0)
+#define SAITR_RFS	(1<<1)
+#define SAITR_TUR	(1<<2)
+#define SAITR_ROR	(1<<3)
+#define SAITR_CADT	(1<<4)
+#define SAITR_SADR	(1<<5)
+#define SAITR_RSTO	(1<<6)
+#define SAITR_TDBDA	(1<<8)
+#define SAITR_TDBDB	(1<<9)
+#define SAITR_RDBDA	(1<<10)
+#define SAITR_RDBDB	(1<<11)
+
+/*
+ * General-Purpose I/O Interface
+ *
+ * Registers
+ *    PA_DDR		GPIO Block A Data Direction
+ *    PA_DRR/PA_DWR	GPIO Block A Data Value Register (read/write)
+ *    PA_SDR		GPIO Block A Sleep Direction
+ *    PA_SSR		GPIO Block A Sleep State
+ *    PB_DDR		GPIO Block B Data Direction
+ *    PB_DRR/PB_DWR	GPIO Block B Data Value Register (read/write)
+ *    PB_SDR		GPIO Block B Sleep Direction
+ *    PB_SSR		GPIO Block B Sleep State
+ *    PC_DDR		GPIO Block C Data Direction
+ *    PC_DRR/PC_DWR	GPIO Block C Data Value Register (read/write)
+ *    PC_SDR		GPIO Block C Sleep Direction
+ *    PC_SSR		GPIO Block C Sleep State
+ */
+
+#define _PA_DDR		_SA1111( 0x1000 )
+#define _PA_DRR		_SA1111( 0x1004 )
+#define _PA_DWR		_SA1111( 0x1004 )
+#define _PA_SDR		_SA1111( 0x1008 )
+#define _PA_SSR		_SA1111( 0x100c )
+#define _PB_DDR		_SA1111( 0x1010 )
+#define _PB_DRR		_SA1111( 0x1014 )
+#define _PB_DWR		_SA1111( 0x1014 )
+#define _PB_SDR		_SA1111( 0x1018 )
+#define _PB_SSR		_SA1111( 0x101c )
+#define _PC_DDR		_SA1111( 0x1020 )
+#define _PC_DRR		_SA1111( 0x1024 )
+#define _PC_DWR		_SA1111( 0x1024 )
+#define _PC_SDR		_SA1111( 0x1028 )
+#define _PC_SSR		_SA1111( 0x102c )
+
+#if LANGUAGE == C
+
+#define PA_DDR		__CCREG(0x1000)
+#define PA_DRR		__CCREG(0x1004)
+#define PA_DWR		__CCREG(0x1004)
+#define PA_SDR		__CCREG(0x1008)
+#define PA_SSR		__CCREG(0x100c)
+#define PB_DDR		__CCREG(0x1010)
+#define PB_DRR		__CCREG(0x1014)
+#define PB_DWR		__CCREG(0x1014)
+#define PB_SDR		__CCREG(0x1018)
+#define PB_SSR		__CCREG(0x101c)
+#define PC_DDR		__CCREG(0x1020)
+#define PC_DRR		__CCREG(0x1024)
+#define PC_DWR		__CCREG(0x1024)
+#define PC_SDR		__CCREG(0x1028)
+#define PC_SSR		__CCREG(0x102c)
+
+#endif  /* LANGUAGE == C */
+
+/*
+ * Interrupt Controller
+ *
+ * Registers
+ *    INTTEST0		Test register 0
+ *    INTTEST1		Test register 1
+ *    INTEN0		Interrupt Enable register 0
+ *    INTEN1		Interrupt Enable register 1
+ *    INTPOL0		Interrupt Polarity selection 0
+ *    INTPOL1		Interrupt Polarity selection 1
+ *    INTTSTSEL		Interrupt source selection
+ *    INTSTATCLR0	Interrupt Status/Clear 0
+ *    INTSTATCLR1	Interrupt Status/Clear 1
+ *    INTSET0		Interrupt source set 0
+ *    INTSET1		Interrupt source set 1
+ *    WAKE_EN0		Wake-up source enable 0
+ *    WAKE_EN1		Wake-up source enable 1
+ *    WAKE_POL0		Wake-up polarity selection 0
+ *    WAKE_POL1		Wake-up polarity selection 1
+ */
+
+#define SA1111_INTTEST0		0x1600
+#define SA1111_INTTEST1		0x1604
+#define SA1111_INTEN0		0x1608
+#define SA1111_INTEN1		0x160c
+#define SA1111_INTPOL0		0x1610
+#define SA1111_INTPOL1		0x1614
+#define SA1111_INTTSTSEL	0x1618
+#define SA1111_INTSTATCLR0	0x161c
+#define SA1111_INTSTATCLR1	0x1620
+#define SA1111_INTSET0		0x1624
+#define SA1111_INTSET1		0x1628
+#define SA1111_WAKE_EN0		0x162c
+#define SA1111_WAKE_EN1		0x1630
+#define SA1111_WAKE_POL0	0x1634
+#define SA1111_WAKE_POL1	0x1638
+
+#define _INTTEST0	_SA1111(SA1111_INTTEST0)
+#define _INTTEST1	_SA1111(SA1111_INTTEST1)
+#define _INTEN0		_SA1111(SA1111_INTEN0)
+#define _INTEN1		_SA1111(SA1111_INTEN1)
+#define _INTPOL0	_SA1111(SA1111_INTPOL0)
+#define _INTPOL1	_SA1111(SA1111_INTPOL1)
+#define _INTTSTSEL	_SA1111(SA1111_INTTSTSEL)
+#define _INTSTATCLR0	_SA1111(SA1111_INTSTATCLR0)
+#define _INTSTATCLR1	_SA1111(SA1111_INTSTATCLR1)
+#define _INTSET0	_SA1111(SA1111_INTSET0)
+#define _INTSET1	_SA1111(SA1111_INTSET1)
+#define _WAKE_EN0	_SA1111(SA1111_WAKE_EN0)
+#define _WAKE_EN1	_SA1111(SA1111_WAKE_EN1)
+#define _WAKE_POL0	_SA1111(SA1111_WAKE_POL0)
+#define _WAKE_POL1	_SA1111(SA1111_WAKE_POL1)
+
+#if LANGUAGE == C
+
+#define INTTEST0	__CCREG(SA1111_INTTEST0)
+#define INTTEST1	__CCREG(SA1111_INTTEST1)
+#define INTEN0		__CCREG(SA1111_INTEN0)
+#define INTEN1		__CCREG(SA1111_INTEN1)
+#define INTPOL0		__CCREG(SA1111_INTPOL0)
+#define INTPOL1		__CCREG(SA1111_INTPOL1)
+#define INTTSTSEL	__CCREG(SA1111_INTTSTSEL)
+#define INTSTATCLR0	__CCREG(SA1111_INTSTATCLR0)
+#define INTSTATCLR1	__CCREG(SA1111_INTSTATCLR1)
+#define INTSET0		__CCREG(SA1111_INTSET0)
+#define INTSET1		__CCREG(SA1111_INTSET1)
+#define WAKE_EN0	__CCREG(SA1111_WAKE_EN0)
+#define WAKE_EN1	__CCREG(SA1111_WAKE_EN1)
+#define WAKE_POL0	__CCREG(SA1111_WAKE_POL0)
+#define WAKE_POL1	__CCREG(SA1111_WAKE_POL1)
+
+#endif  /* LANGUAGE == C */
+
+/*
+ * PS/2 Trackpad and Mouse Interfaces
+ *
+ * Registers   (prefix kbd applies to trackpad interface, mse to mouse)
+ *    KBDCR     Control Register
+ *    KBDSTAT       Status Register
+ *    KBDDATA       Transmit/Receive Data register
+ *    KBDCLKDIV     Clock Division Register
+ *    KBDPRECNT     Clock Precount Register
+ *    KBDTEST1      Test register 1
+ *    KBDTEST2      Test register 2
+ *    KBDTEST3      Test register 3
+ *    KBDTEST4      Test register 4
+ *    MSECR
+ *    MSESTAT
+ *    MSEDATA
+ *    MSECLKDIV
+ *    MSEPRECNT
+ *    MSETEST1
+ *    MSETEST2
+ *    MSETEST3
+ *    MSETEST4
+ *
+ */
+
+#define _KBD( x )   _SA1111( 0x0A00 )
+#define _MSE( x )   _SA1111( 0x0C00 )
+
+#define _KBDCR	    _SA1111( 0x0A00 )
+#define _KBDSTAT    _SA1111( 0x0A04 )
+#define _KBDDATA    _SA1111( 0x0A08 )
+#define _KBDCLKDIV  _SA1111( 0x0A0C )
+#define _KBDPRECNT  _SA1111( 0x0A10 )
+#define _MSECR	    _SA1111( 0x0C00 )
+#define _MSESTAT    _SA1111( 0x0C04 )
+#define _MSEDATA    _SA1111( 0x0C08 )
+#define _MSECLKDIV  _SA1111( 0x0C0C )
+#define _MSEPRECNT  _SA1111( 0x0C10 )
+
+#if ( LANGUAGE == C )
+
+#define KBDCR		__CCREG(0x0a00)
+#define KBDSTAT		__CCREG(0x0a04)
+#define KBDDATA		__CCREG(0x0a08)
+#define KBDCLKDIV	__CCREG(0x0a0c)
+#define KBDPRECNT	__CCREG(0x0a10)
+#define MSECR		__CCREG(0x0c00)
+#define MSESTAT		__CCREG(0x0c04)
+#define MSEDATA		__CCREG(0x0c08)
+#define MSECLKDIV	__CCREG(0x0c0c)
+#define MSEPRECNT	__CCREG(0x0c10)
+
+#define KBDCR_ENA        0x08
+#define KBDCR_FKD        0x02
+#define KBDCR_FKC        0x01
+
+#define KBDSTAT_TXE      0x80
+#define KBDSTAT_TXB      0x40
+#define KBDSTAT_RXF      0x20
+#define KBDSTAT_RXB      0x10
+#define KBDSTAT_ENA      0x08
+#define KBDSTAT_RXP      0x04
+#define KBDSTAT_KBD      0x02
+#define KBDSTAT_KBC      0x01
+
+#define KBDCLKDIV_DivVal     Fld(4,0)
+
+#define MSECR_ENA        0x08
+#define MSECR_FKD        0x02
+#define MSECR_FKC        0x01
+
+#define MSESTAT_TXE      0x80
+#define MSESTAT_TXB      0x40
+#define MSESTAT_RXF      0x20
+#define MSESTAT_RXB      0x10
+#define MSESTAT_ENA      0x08
+#define MSESTAT_RXP      0x04
+#define MSESTAT_MSD      0x02
+#define MSESTAT_MSC      0x01
+
+#define MSECLKDIV_DivVal     Fld(4,0)
+
+#define KBDTEST1_CD      0x80
+#define KBDTEST1_RC1         0x40
+#define KBDTEST1_MC      0x20
+#define KBDTEST1_C       Fld(2,3)
+#define KBDTEST1_T2      0x40
+#define KBDTEST1_T1      0x20
+#define KBDTEST1_T0      0x10
+#define KBDTEST2_TICBnRES    0x08
+#define KBDTEST2_RKC         0x04
+#define KBDTEST2_RKD         0x02
+#define KBDTEST2_SEL         0x01
+#define KBDTEST3_ms_16       0x80
+#define KBDTEST3_us_64       0x40
+#define KBDTEST3_us_16       0x20
+#define KBDTEST3_DIV8        0x10
+#define KBDTEST3_DIn         0x08
+#define KBDTEST3_CIn         0x04
+#define KBDTEST3_KD      0x02
+#define KBDTEST3_KC      0x01
+#define KBDTEST4_BC12        0x80
+#define KBDTEST4_BC11        0x40
+#define KBDTEST4_TRES        0x20
+#define KBDTEST4_CLKOE       0x10
+#define KBDTEST4_CRES        0x08
+#define KBDTEST4_RXB         0x04
+#define KBDTEST4_TXB         0x02
+#define KBDTEST4_SRX         0x01
+
+#define MSETEST1_CD      0x80
+#define MSETEST1_RC1         0x40
+#define MSETEST1_MC      0x20
+#define MSETEST1_C       Fld(2,3)
+#define MSETEST1_T2      0x40
+#define MSETEST1_T1      0x20
+#define MSETEST1_T0      0x10
+#define MSETEST2_TICBnRES    0x08
+#define MSETEST2_RKC         0x04
+#define MSETEST2_RKD         0x02
+#define MSETEST2_SEL         0x01
+#define MSETEST3_ms_16       0x80
+#define MSETEST3_us_64       0x40
+#define MSETEST3_us_16       0x20
+#define MSETEST3_DIV8        0x10
+#define MSETEST3_DIn         0x08
+#define MSETEST3_CIn         0x04
+#define MSETEST3_KD      0x02
+#define MSETEST3_KC      0x01
+#define MSETEST4_BC12        0x80
+#define MSETEST4_BC11        0x40
+#define MSETEST4_TRES        0x20
+#define MSETEST4_CLKOE       0x10
+#define MSETEST4_CRES        0x08
+#define MSETEST4_RXB         0x04
+#define MSETEST4_TXB         0x02
+#define MSETEST4_SRX         0x01
+
+#endif  /* LANGUAGE == C */
+
+/*
+ * PCMCIA Interface
+ *
+ * Registers
+ *    PCSR	Status Register
+ *    PCCR	Control Register
+ *    PCSSR	Sleep State Register
+ */
+
+#define _PCCR		_SA1111( 0x1800 )
+#define _PCSSR		_SA1111( 0x1804 )
+#define _PCSR		_SA1111( 0x1808 )
+
+#if LANGUAGE == C
+
+#define PCCR		__CCREG(0x1800)
+#define PCSSR		__CCREG(0x1804)
+#define PCSR		__CCREG(0x1808)
+
+#endif  /* LANGUAGE == C */
+
+#define PCSR_S0_READY	(1<<0)
+#define PCSR_S1_READY	(1<<1)
+#define PCSR_S0_DETECT	(1<<2)
+#define PCSR_S1_DETECT	(1<<3)
+#define PCSR_S0_VS1	(1<<4)
+#define PCSR_S0_VS2	(1<<5)
+#define PCSR_S1_VS1	(1<<6)
+#define PCSR_S1_VS2	(1<<7)
+#define PCSR_S0_WP	(1<<8)
+#define PCSR_S1_WP	(1<<9)
+#define PCSR_S0_BVD1	(1<<10)
+#define PCSR_S0_BVD2	(1<<11)
+#define PCSR_S1_BVD1	(1<<12)
+#define PCSR_S1_BVD2	(1<<13)
+
+#define PCCR_S0_RST	(1<<0)
+#define PCCR_S1_RST	(1<<1)
+#define PCCR_S0_FLT	(1<<2)
+#define PCCR_S1_FLT	(1<<3)
+#define PCCR_S0_PWAITEN	(1<<4)
+#define PCCR_S1_PWAITEN	(1<<5)
+#define PCCR_S0_PSE	(1<<6)
+#define PCCR_S1_PSE	(1<<7)
+
+#define PCSSR_S0_SLEEP	(1<<0)
+#define PCSSR_S1_SLEEP	(1<<1)
+
+#endif  /* _ASM_ARCH_SA1111 */
diff --git a/include/asm-arm/hdreg.h b/include/asm-arm/hdreg.h
index 81bc05e16260..a2d301dd5361 100644
--- a/include/asm-arm/hdreg.h
+++ b/include/asm-arm/hdreg.h
@@ -7,7 +7,7 @@
 #ifndef __ASMARM_HDREG_H
 #define __ASMARM_HDREG_H
 
-typedef unsigned long ide_ioreg_t;
+typedef unsigned int ide_ioreg_t;
 
 #endif /* __ASMARM_HDREG_H */
 
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 91e50dc218f0..4782df468d45 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -23,20 +23,14 @@
 #ifdef __KERNEL__
 
 #include <linux/types.h>
+#include <asm/byteorder.h>
 #include <asm/memory.h>
 #include <asm/arch/hardware.h>
 
 /*
- * Generic virtual read/write.  Note that we don't support half-word
- * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
- * to the architecture specific code.
+ * Generic IO read/write.  These perform native-endian accesses.  Note
+ * that some architectures will want to re-define __raw_{read,write}w.
  */
-#define __arch_getb(a)			(*(volatile unsigned char *)(a))
-#define __arch_getl(a)			(*(volatile unsigned int  *)(a))
-
-#define __arch_putb(v,a)		(*(volatile unsigned char *)(a) = (v))
-#define __arch_putl(v,a)		(*(volatile unsigned int  *)(a) = (v))
-
 extern void __raw_writesb(unsigned int addr, void *data, int bytelen);
 extern void __raw_writesw(unsigned int addr, void *data, int wordlen);
 extern void __raw_writesl(unsigned int addr, void *data, int longlen);
@@ -45,116 +39,85 @@ extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
 extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
 extern void __raw_readsl(unsigned int addr, void *data, int longlen);
 
-#define __raw_writeb(v,a)		__arch_putb(v,a)
-#define __raw_writew(v,a)		__arch_putw(v,a)
-#define __raw_writel(v,a)		__arch_putl(v,a)
+#define __raw_writeb(v,a)	(*(volatile unsigned char  *)(a) = (v))
+#define __raw_writew(v,a)	(*(volatile unsigned short *)(a) = (v))
+#define __raw_writel(v,a)	(*(volatile unsigned int   *)(a) = (v))
 
-#define __raw_readb(a)			__arch_getb(a)
-#define __raw_readw(a)			__arch_getw(a)
-#define __raw_readl(a)			__arch_getl(a)
+#define __raw_readb(a)		(*(volatile unsigned char  *)(a))
+#define __raw_readw(a)		(*(volatile unsigned short *)(a))
+#define __raw_readl(a)		(*(volatile unsigned int   *)(a))
 
 /*
- * The compiler seems to be incapable of optimising constants
- * properly.  Spell it out to the compiler in some cases.
- * These are only valid for small values of "off" (< 1<<12)
+ * Bad read/write accesses...
  */
-#define __raw_base_writeb(val,base,off)	__arch_base_putb(val,base,off)
-#define __raw_base_writew(val,base,off)	__arch_base_putw(val,base,off)
-#define __raw_base_writel(val,base,off)	__arch_base_putl(val,base,off)
-
-#define __raw_base_readb(base,off)	__arch_base_getb(base,off)
-#define __raw_base_readw(base,off)	__arch_base_getw(base,off)
-#define __raw_base_readl(base,off)	__arch_base_getl(base,off)
+extern void __readwrite_bug(const char *fn);
 
 /*
  * Now, pick up the machine-defined IO definitions
  */
 #include <asm/arch/io.h>
 
+#ifdef __io_pci
+#warning machine class uses buggy __io_pci
+#endif
+#if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \
+    defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl)
+#warning machine class uses old __arch_putw or __arch_getw
+#endif
+
 /*
- * IO definitions.  We define {out,in,outs,ins}[bwl] if __io is defined
- * by the machine.  Otherwise, these definitions are left for the machine
- * specific header files to pick up.
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The ARM doesn't have special IO access instructions; all IO is memory
+ * mapped.  Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
  *
  * Note that we prevent GCC re-ordering or caching values in expressions
  * by introducing sequence points into the in*() definitions.  Note that
  * __raw_* do not guarantee this behaviour.
  */
 #ifdef __io
-#define outb(v,p)			__raw_writeb(v,__io(p))
-#define outw(v,p)			__raw_writew(v,__io(p))
-#define outl(v,p)			__raw_writel(v,__io(p))
-
-#define inb(p)		({ unsigned int __v = __raw_readb(__io(p)); __v; })
-#define inw(p)		({ unsigned int __v = __raw_readw(__io(p)); __v; })
-#define inl(p)		({ unsigned int __v = __raw_readl(__io(p)); __v; })
+#define outb(v,p)		__raw_writeb(v,__io(p))
+#define outw(v,p)		__raw_writew(cpu_to_le16(v),__io(p))
+#define outl(v,p)		__raw_writel(cpu_to_le32(v),__io(p))
 
-#define outsb(p,d,l)			__raw_writesb(__io(p),d,l)
-#define outsw(p,d,l)			__raw_writesw(__io(p),d,l)
-#define outsl(p,d,l)			__raw_writesl(__io(p),d,l)
-
-#define insb(p,d,l)			__raw_readsb(__io(p),d,l)
-#define insw(p,d,l)			__raw_readsw(__io(p),d,l)
-#define insl(p,d,l)			__raw_readsl(__io(p),d,l)
-#endif
+#define inb(p)	({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)	({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)	({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
 
-#define outb_p(val,port)		outb((val),(port))
-#define outw_p(val,port)		outw((val),(port))
-#define outl_p(val,port)		outl((val),(port))
-#define inb_p(port)			inb((port))
-#define inw_p(port)			inw((port))
-#define inl_p(port)			inl((port))
-
-#define outsb_p(port,from,len)		outsb(port,from,len)
-#define outsw_p(port,from,len)		outsw(port,from,len)
-#define outsl_p(port,from,len)		outsl(port,from,len)
-#define insb_p(port,to,len)		insb(port,to,len)
-#define insw_p(port,to,len)		insw(port,to,len)
-#define insl_p(port,to,len)		insl(port,to,len)
-
-/*
- * ioremap and friends.
- *
- * ioremap takes a PCI memory address, as specified in
- * linux/Documentation/IO-mapping.txt.  If you want a
- * physical address, use __ioremap instead.
- */
-extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags);
-extern void __iounmap(void *addr);
+#define outsb(p,d,l)		__raw_writesb(__io(p),d,l)
+#define outsw(p,d,l)		__raw_writesw(__io(p),d,l)
+#define outsl(p,d,l)		__raw_writesl(__io(p),d,l)
 
-/*
- * Generic ioremap support.
- *
- * Define:
- *  iomem_valid_addr(off,size)
- *  iomem_to_phys(off)
- */
-#ifdef iomem_valid_addr
-#define __arch_ioremap(off,sz,nocache)				\
- ({								\
-	unsigned long _off = (off), _size = (sz);		\
-	void *_ret = (void *)0;					\
-	if (iomem_valid_addr(_off, _size))			\
-		_ret = __ioremap(iomem_to_phys(_off),_size,0);	\
-	_ret;							\
- })
-
-#define __arch_iounmap __iounmap
+#define insb(p,d,l)		__raw_readsb(__io(p),d,l)
+#define insw(p,d,l)		__raw_readsw(__io(p),d,l)
+#define insl(p,d,l)		__raw_readsl(__io(p),d,l)
 #endif
 
-#define ioremap(off,sz)			__arch_ioremap((off),(sz),0)
-#define ioremap_nocache(off,sz)		__arch_ioremap((off),(sz),1)
-#define iounmap(_addr)			__arch_iounmap(_addr)
+#define outb_p(val,port)	outb((val),(port))
+#define outw_p(val,port)	outw((val),(port))
+#define outl_p(val,port)	outl((val),(port))
+#define inb_p(port)		inb((port))
+#define inw_p(port)		inw((port))
+#define inl_p(port)		inl((port))
 
-/*
- * DMA-consistent mapping functions.  These allocate/free a region of
- * uncached, unwrite-buffered mapped memory space for use with DMA
- * devices.  This is the "generic" version.  The PCI specific version
- * is in pci.h
- */
-extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
-extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
-extern void consistent_sync(void *vaddr, size_t size, int rw);
+#define outsb_p(port,from,len)	outsb(port,from,len)
+#define outsw_p(port,from,len)	outsw(port,from,len)
+#define outsl_p(port,from,len)	outsl(port,from,len)
+#define insb_p(port,to,len)	insb(port,to,len)
+#define insw_p(port,to,len)	insw(port,to,len)
+#define insl_p(port,to,len)	insl(port,to,len)
 
 /*
  * String version of IO memory access ops:
@@ -163,29 +126,31 @@ extern void _memcpy_fromio(void *, unsigned long, size_t);
 extern void _memcpy_toio(unsigned long, const void *, size_t);
 extern void _memset_io(unsigned long, int, size_t);
 
-extern void __readwrite_bug(const char *fn);
-
 /*
- * If this architecture has PCI memory IO, then define the read/write
- * macros.  These should only be used with the cookie passed from
- * ioremap.
+ *  Memory access primitives
+ *  ------------------------
+ *
+ * These perform PCI memory accesses via an ioremap region.  They don't
+ * take an address as such, but a cookie.
+ *
+ * Again, this are defined to perform little endian accesses.  See the
+ * IO port primitives for more information.
  */
 #ifdef __mem_pci
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
 
-#define readb(addr) ({ unsigned int __v = __raw_readb(__mem_pci(addr)); __v; })
-#define readw(addr) ({ unsigned int __v = __raw_readw(__mem_pci(addr)); __v; })
-#define readl(addr) ({ unsigned int __v = __raw_readl(__mem_pci(addr)); __v; })
-
-#define writeb(val,addr)		__raw_writeb(val,__mem_pci(addr))
-#define writew(val,addr)		__raw_writew(val,__mem_pci(addr))
-#define writel(val,addr)		__raw_writel(val,__mem_pci(addr))
+#define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
+#define writew(v,c)		__raw_writew(cpu_to_le16(v),__mem_pci(c))
+#define writel(v,c)		__raw_writel(cpu_to_le32(v),__mem_pci(c))
 
-#define memset_io(a,b,c)		_memset_io(__mem_pci(a),(b),(c))
-#define memcpy_fromio(a,b,c)		_memcpy_fromio((a),__mem_pci(b),(c))
-#define memcpy_toio(a,b,c)		_memcpy_toio(__mem_pci(a),(b),(c))
+#define memset_io(c,v,l)	_memset_io(__mem_pci(c),(v),(l))
+#define memcpy_fromio(a,c,l)	_memcpy_fromio((a),__mem_pci(c),(l))
+#define memcpy_toio(c,a,l)	_memcpy_toio(__mem_pci(c),(a),(l))
 
-#define eth_io_copy_and_sum(a,b,c,d) \
-				eth_copy_and_sum((a),__mem_pci(b),(c),(d))
+#define eth_io_copy_and_sum(s,c,l,b) \
+				eth_copy_and_sum((s),__mem_pci(c),(l),(b))
 
 static inline int
 check_signature(unsigned long io_addr, const unsigned char *signature,
@@ -206,28 +171,20 @@ out:
 
 #elif !defined(readb)
 
-#define readb(addr)			(__readwrite_bug("readb"),0)
-#define readw(addr)			(__readwrite_bug("readw"),0)
-#define readl(addr)			(__readwrite_bug("readl"),0)
-#define writeb(v,addr)			__readwrite_bug("writeb")
-#define writew(v,addr)			__readwrite_bug("writew")
-#define writel(v,addr)			__readwrite_bug("writel")
+#define readb(c)			(__readwrite_bug("readb"),0)
+#define readw(c)			(__readwrite_bug("readw"),0)
+#define readl(c)			(__readwrite_bug("readl"),0)
+#define writeb(v,c)			__readwrite_bug("writeb")
+#define writew(v,c)			__readwrite_bug("writew")
+#define writel(v,c)			__readwrite_bug("writel")
 
-#define eth_io_copy_and_sum(a,b,c,d)	__readwrite_bug("eth_io_copy_and_sum")
+#define eth_io_copy_and_sum(s,c,l,b)	__readwrite_bug("eth_io_copy_and_sum")
 
 #define check_signature(io,sig,len)	(0)
 
 #endif	/* __mem_pci */
 
 /*
- * remap a physical address `phys' of size `size' with page protection `prot'
- * into virtual address `from'
- */
-#define io_remap_page_range(from,phys,size,prot) \
-		remap_page_range(from,phys,size,prot)
-
-
-/*
  * If this architecture has ISA IO, then define the isa_read/isa_write
  * macros.
  */
@@ -281,5 +238,51 @@ out:
 #define isa_check_signature(io,sig,len)	(0)
 
 #endif	/* __mem_isa */
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * linux/Documentation/IO-mapping.txt.
+ */
+extern void * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
+extern void __iounmap(void *addr);
+
+#ifndef __arch_ioremap
+#define ioremap(cookie,size)		__ioremap(cookie,size,0,1)
+#define ioremap_nocache(cookie,size)	__ioremap(cookie,size,0,1)
+#define iounmap(cookie)			__iounmap(cookie)
+#else
+#define ioremap(cookie,size)		__arch_ioremap((cookie),(size),0,1)
+#define ioremap_nocache(cookie,size)	__arch_ioremap((cookie),(size),0,1)
+#define iounmap(cookie)			__arch_iounmap(cookie)
+#endif
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+
+/*
+ * FIXME: I'm sure these will need to be changed for DISCONTIG
+ */
+/*
+ * Change "struct page" to physical address.
+ */
+#define page_to_phys(page)	(PHYS_OFFSET + ((page - mem_map) << PAGE_SHIFT))
+#define page_to_bus(page)	(PHYS_OFFSET + ((page - mem_map) << PAGE_SHIFT))
+
+/*
+ * can the hardware map this into one segment or not, given no other
+ * constraints.
+ */
+#define BIOVEC_MERGEABLE(vec1, vec2)	\
+	((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
+
 #endif	/* __KERNEL__ */
 #endif	/* __ASM_ARM_IO_H */
diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h
index f0fb5f4ec0df..53667240886a 100644
--- a/include/asm-arm/mach/pci.h
+++ b/include/asm-arm/mach/pci.h
@@ -7,7 +7,12 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+
+struct pci_sys_data;
+struct pci_bus;
+
 struct hw_pci {
+	/* START OF OLD STUFF */
 	/* Initialise the hardware */
 	void		(*init)(void *);
 
@@ -25,10 +30,55 @@ struct hw_pci {
 
 	/* IRQ mapping */
 	int		(*map_irq)(struct pci_dev *dev, u8 slot, u8 pin);
+
+	/* END OF OLD STUFF */
+
+	/* NEW STUFF */
+	int		nr_controllers;
+	int		(*setup)(int nr, struct pci_sys_data *);
+	struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
+	void		(*preinit)(void);
+	void		(*postinit)(void);
+};
+
+/*
+ * Per-controller structure
+ */
+struct pci_sys_data {
+	int		busnr;		/* primary bus number			*/
+	unsigned long	mem_offset;	/* bus->cpu memory mapping offset	*/
+	unsigned long	io_offset;	/* bus->cpu IO mapping offset		*/
+	struct pci_bus	*bus;		/* PCI bus				*/
+	struct resource *resource[3];	/* Primary PCI bus resources		*/
+					/* Bridge swizzling			*/
+	u8		(*swizzle)(struct pci_dev *, u8 *);
+					/* IRQ mapping				*/
+	int		(*map_irq)(struct pci_dev *, u8, u8);
+	struct hw_pci	*hw;
 };
 
-extern u8 no_swizzle(struct pci_dev *dev, u8 *pin);
-extern void __init dc21285_setup_resources(struct resource **resource);
-extern void __init dc21285_init(void *sysdata);
+/*
+ * This is the standard PCI-PCI bridge swizzling algorithm.
+ */
+u8 pci_std_swizzle(struct pci_dev *dev, u8 *pinp);
+
+/*
+ * PCI controllers
+ */
+extern int iop310_setup(int nr, struct pci_sys_data *);
+extern struct pci_bus *iop310_scan_bus(int nr, struct pci_sys_data *);
+
+extern int dc21285_setup(int nr, struct pci_sys_data *);
+extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
+extern void dc21285_preinit(void);
+extern void dc21285_postinit(void);
+
+extern int via82c505_setup(int nr, struct pci_sys_data *);
+extern struct pci_bus *via82c505_scan_bus(int nr, struct pci_sys_data *);
 extern void __init via82c505_init(void *sysdata);
 
+extern int pci_v3_setup(int nr, struct pci_sys_data *);
+extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *);
+extern void pci_v3_preinit(void);
+extern void pci_v3_postinit(void);
+
diff --git a/include/asm-arm/mach/serial_sa1100.h b/include/asm-arm/mach/serial_sa1100.h
index 2576c11841d6..cac52bb7450b 100644
--- a/include/asm-arm/mach/serial_sa1100.h
+++ b/include/asm-arm/mach/serial_sa1100.h
@@ -18,9 +18,10 @@ struct uart_info;
  */
 struct sa1100_port_fns {
 	void	(*set_mctrl)(struct uart_port *, u_int);
-	int	(*get_mctrl)(struct uart_port *);
+	u_int	(*get_mctrl)(struct uart_port *);
 	void	(*enable_ms)(struct uart_port *);
 	void	(*pm)(struct uart_port *, u_int, u_int);
+	int	(*set_wake)(struct uart_port *, u_int);
 	int	(*open)(struct uart_port *, struct uart_info *);
 	void	(*close)(struct uart_port *, struct uart_info *);
 };
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index bc3bd8275b08..40d2709c804d 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -3,8 +3,8 @@
 
 #include <asm/proc/page.h>
 
-#define PAGE_SIZE       (1UL << PAGE_SHIFT)
-#define PAGE_MASK       (~(PAGE_SIZE-1))
+#define PAGE_SIZE	(1UL << PAGE_SHIFT)
+#define PAGE_MASK	(~(PAGE_SIZE-1))
 
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
@@ -14,8 +14,8 @@
 #define clear_page(page)	memzero((void *)(page), PAGE_SIZE)
 extern void copy_page(void *to, void *from);
 
-#define clear_user_page(page, vaddr)	clear_page(page)
-#define copy_user_page(to, from, vaddr)	copy_page(to, from)
+#define clear_user_page(page, vaddr)	cpu_clear_user_page(page,vaddr)
+#define copy_user_page(to, from, vaddr)	cpu_copy_user_page(to,from,vaddr)
 
 #ifdef STRICT_MM_TYPECHECKS
 /*
@@ -63,11 +63,21 @@ typedef unsigned long pgprot_t;
 
 #ifndef __ASSEMBLY__
 
+#ifdef CONFIG_DEBUG_BUGVERBOSE
 extern void __bug(const char *file, int line, void *data);
 
+/* give file/line information */
 #define BUG()		__bug(__FILE__, __LINE__, NULL)
 #define PAGE_BUG(page)	__bug(__FILE__, __LINE__, page)
 
+#else
+
+/* these just cause an oops */
+#define BUG()		(*(int *)0 = 0)
+#define PAGE_BUG(page)	(*(int *)0 = 0)
+
+#endif
+
 /* Pure 2^n version of get_order */
 static inline int get_order(unsigned long size)
 {
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index bc88160ec936..720957f606d6 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -3,7 +3,14 @@
 
 #ifdef __KERNEL__
 
+#include <linux/mm.h> /* bah! */
+
 #include <asm/arch/hardware.h>
+#include <asm/scatterlist.h>
+#include <asm/page.h>
+#include <asm/io.h>
+
+struct pci_dev;
 
 static inline void pcibios_set_master(struct pci_dev *dev)
 {
@@ -15,10 +22,11 @@ static inline void pcibios_penalize_isa_irq(int irq)
 	/* We don't do dynamic PCI IRQ allocation */
 }
 
-#include <asm/scatterlist.h>
-#include <asm/io.h>
-
-struct pci_dev;
+/* The PCI address space does equal the physical memory
+ * address space.  The networking and block device layers use
+ * this boolean for bounce buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS     (0)
 
 /* Allocate and map kernel buffer using consistent mode DMA for a device.
  * hwdev should be valid struct pci_dev pointer for PCI devices,
@@ -108,8 +116,20 @@ pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int directi
 	int i;
 
 	for (i = 0; i < nents; i++, sg++) {
-		consistent_sync(sg->address, sg->length, direction);
-		sg->dma_address = virt_to_bus(sg->address);
+		char *virt;
+		if (sg->address && sg->page)
+			BUG();
+		else if (!sg->address && !sg->page)
+			BUG();
+
+		if (sg->address) {
+			sg->dma_address = virt_to_bus(sg->address);
+			virt = sg->address;
+		} else {
+			sg->dma_address = page_to_bus(sg->page) + sg->offset;
+			virt = page_address(sg->page) + sg->offset;
+		}
+		consistent_sync(virt, sg->length, direction);
 	}
 
 	return nents;
@@ -151,8 +171,15 @@ pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int d
 {
 	int i;
 
-	for (i = 0; i < nelems; i++, sg++)
-		consistent_sync(sg->address, sg->length, direction);
+	for (i = 0; i < nelems; i++, sg++) {
+		char *virt;
+
+		if (sg->address)
+			virt = sg->address;
+		else
+			virt = page_address(sg->page) + sg->offset;
+		consistent_sync(virt, sg->length, direction);
+	}
 }
 
 /* Return whether the given PCI device DMA address mask can
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 418f738bd958..9123efe107ac 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -12,6 +12,7 @@
 
 #include <linux/config.h>
 #include <asm/arch/memory.h>
+#include <asm/arch/vmalloc.h>
 #include <asm/proc-fns.h>
 
 /*
@@ -177,6 +178,13 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 
 extern void pgtable_cache_init(void);
 
+/*
+ * remap a physical address `phys' of size `size' with page protection `prot'
+ * into virtual address `from'
+ */
+#define io_remap_page_range(from,phys,size,prot) \
+		remap_page_range(from,phys,size,prot)
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _ASMARM_PGTABLE_H */
diff --git a/include/asm-arm/proc-armo/ptrace.h b/include/asm-arm/proc-armo/ptrace.h
index 559a3669395e..79d44f4f71d8 100644
--- a/include/asm-arm/proc-armo/ptrace.h
+++ b/include/asm-arm/proc-armo/ptrace.h
@@ -10,21 +10,21 @@
 #ifndef __ASM_PROC_PTRACE_H
 #define __ASM_PROC_PTRACE_H
 
-#define USR26_MODE	0x00
-#define FIQ26_MODE	0x01
-#define IRQ26_MODE	0x02
-#define SVC26_MODE	0x03
+#define USR26_MODE	0x00000000
+#define FIQ26_MODE	0x00000001
+#define IRQ26_MODE	0x00000002
+#define SVC26_MODE	0x00000003
 #define USR_MODE	USR26_MODE
 #define FIQ_MODE	FIQ26_MODE
 #define IRQ_MODE	IRQ26_MODE
 #define SVC_MODE	SVC26_MODE
-#define MODE_MASK	0x03
-#define F_BIT		(1 << 26)
-#define I_BIT		(1 << 27)
-#define CC_V_BIT	(1 << 28)
-#define CC_C_BIT	(1 << 29)
-#define CC_Z_BIT	(1 << 30)
-#define CC_N_BIT	(1 << 31)
+#define MODE_MASK	0x00000003
+#define PSR_F_BIT	0x04000000
+#define PSR_I_BIT	0x08000000
+#define PSR_V_BIT	0x10000000
+#define PSR_C_BIT	0x20000000
+#define PSR_Z_BIT	0x40000000
+#define PSR_N_BIT	0x80000000
 #define PCMASK		0xfc000003
 
 #ifndef __ASSEMBLY__
@@ -65,13 +65,13 @@ struct pt_regs {
 #define thumb_mode(regs) (0)
 
 #define interrupts_enabled(regs) \
-	(!((regs)->ARM_pc & I_BIT))
+	(!((regs)->ARM_pc & PSR_I_BIT))
 
 #define fast_interrupts_enabled(regs) \
-	(!((regs)->ARM_pc & F_BIT))
+	(!((regs)->ARM_pc & PSR_F_BIT))
 
 #define condition_codes(regs) \
-	((regs)->ARM_pc & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
+	((regs)->ARM_pc & (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT))
 
 /* Are the current registers suitable for user mode?
  * (used to maintain security in signal handlers)
@@ -79,13 +79,13 @@ struct pt_regs {
 static inline int valid_user_regs(struct pt_regs *regs)
 {
 	if (user_mode(regs) &&
-	    (regs->ARM_pc & (F_BIT | I_BIT)) == 0)
+	    (regs->ARM_pc & (PSR_F_BIT | PSR_I_BIT)) == 0)
 		return 1;
 
 	/*
 	 * force it to be something sensible
 	 */
-	regs->ARM_pc &= ~(MODE_MASK | F_BIT | I_BIT);
+	regs->ARM_pc &= ~(MODE_MASK | PSR_F_BIT | PSR_I_BIT);
 
 	return 0;
 }
diff --git a/include/asm-arm/proc-armv/assembler.h b/include/asm-arm/proc-armv/assembler.h
index 6881898f5635..64916c820b33 100644
--- a/include/asm-arm/proc-armv/assembler.h
+++ b/include/asm-arm/proc-armv/assembler.h
@@ -40,7 +40,7 @@
  */
 	.macro	save_and_disable_irqs, oldcpsr, temp
 	mrs	\oldcpsr, cpsr
-	mov	\temp, #I_BIT | MODE_SVC
+	mov	\temp, #PSR_I_BIT | MODE_SVC
 	msr	cpsr_c, \temp
 	.endm
 
diff --git a/include/asm-arm/proc-armv/cache.h b/include/asm-arm/proc-armv/cache.h
index feb02f086815..26989b94167c 100644
--- a/include/asm-arm/proc-armv/cache.h
+++ b/include/asm-arm/proc-armv/cache.h
@@ -44,13 +44,13 @@
 
 #define flush_cache_range(_mm,_start,_end)				\
 	do {								\
-		if ((_mm) == current->mm)				\
+		if ((_mm) == current->active_mm)			\
 			cpu_cache_clean_invalidate_range((_start), (_end), 1); \
 	} while (0)
 
 #define flush_cache_page(_vma,_vmaddr)					\
 	do {								\
-		if ((_vma)->vm_mm == current->mm) {			\
+		if ((_vma)->vm_mm == current->active_mm) {		\
 			cpu_cache_clean_invalidate_range((_vmaddr),	\
 				(_vmaddr) + PAGE_SIZE,			\
 				((_vma)->vm_flags & VM_EXEC));		\
@@ -62,36 +62,68 @@
  * in the cache for this page.  This does not invalidate either I or D caches.
  *
  * Called from:
- * 1. mm/filemap.c:filemap_nopage
- * 2. mm/filemap.c:filemap_nopage
- *    [via do_no_page - ok]
+ *  1. fs/exec.c:put_dirty_page				- ok
+ *     - page came from alloc_page(), so page->mapping = NULL.
+ *     - flush_dcache_page called immediately prior.
+ *
+ *  2. kernel/ptrace.c:access_one_page			- flush_icache_page
+ *     - flush_cache_page takes care of the user space side of the mapping.
+ *     - page is either a page cache page (with page->mapping set, and
+ *       hence page->mapping->i_mmap{,shared} also set) or an anonymous
+ *       page.  I think this is ok.
+ *
+ *  3. kernel/ptrace.c:access_one_page			- bad
+ *     - flush_cache_page takes care of the user space side of the mapping.
+ *     - no apparant cache protection, reading the kernel virtual alias
+ *
+ *  4. mm/filemap.c:filemap_no_page			- ok
+ *     - add_to_page_cache_* clears PG_arch_1.
+ *     - page->mapping != NULL.
+ *     - i_mmap or i_mmap_shared will be non-null if mmap'd
+ *     - called from (8).
  *
- * 3. mm/memory.c:break_cow
- *    [copy_cow_page doesn't do anything to the cache; insufficient cache
- *     handling.  Need to add flush_dcache_page() here]
+ *  5. mm/memory.c:break_cow,do_wp_page			- {copy,clear}_user_page
+ *     - need to ensure that copy_cow_page has pushed all data from the dcache
+ *       to the page.
+ *       - calls
+ *         - clear_user_highpage -> clear_user_page
+ *         - copy_user_highpage -> copy_user_page
  *
- * 4. mm/memory.c:do_swap_page
- *    [read_swap_cache_async doesn't do anything to the cache: insufficient
- *     cache handling.  Need to add flush_dcache_page() here]
+ *  6. mm/memory.c:do_swap_page				- flush_icache_page
+ *     - flush_icache_page called afterwards - if flush_icache_page does the
+ *       same as flush_dcache_page, update_mmu_cache will do the work for us.
+ *     - update_mmu_cache called.
  *
- * 5. mm/memory.c:do_anonymous_page
- *    [zero page, never written by kernel - ok]
+ *  7. mm/memory.c:do_anonymous_page			- {copy,clear}_user_page
+ *     - calls clear_user_highpage.  See (5)
  *
- * 6. mm/memory.c:do_no_page
- *    [we will be calling update_mmu_cache, which will catch on PG_dcache_dirty]
+ *  8. mm/memory.c:do_no_page				- flush_icache_page
+ *     - flush_icache_page called afterwards - if flush_icache_page does the
+ *       same as flush_dcache_page, update_mmu_cache will do the work for us.
+ *     - update_mmu_cache called.
+ *     - When we place a user mapping, we will call update_mmu_cache,
+ *       which will catch PG_arch_1 set.
  *
- * 7. mm/shmem.c:shmem_nopage
- * 8. mm/shmem.c:shmem_nopage
- *    [via do_no_page - ok]
+ *  9. mm/shmem.c:shmem_no_page				- ok
+ *     - shmem_get_page clears PG_arch_1, as does add_to_page_cache (duplicate)
+ *     - page->mapping != NULL.
+ *     - i_mmap or i_mmap_shared will be non-null if mmap'd
+ *     - called from (8).
  *
- * 9. fs/exec.c:put_dirty_page
- *    [we call flush_dcache_page prior to this, which will flush out the
- *     kernel virtual addresses from the dcache - ok]
+ * 10. mm/swapfile.c:try_to_unuse			- bad
+ *     - this looks really dodgy - we're putting pages from the swap cache
+ *       straight into processes, and the only cache handling appears to
+ *       be flush_page_to_ram.
  */
+#define flush_page_to_ram_ok
+#ifdef flush_page_to_ram_ok
+#define flush_page_to_ram(page)	do { } while (0)
+#else
 static __inline__ void flush_page_to_ram(struct page *page)
 {
 	cpu_flush_ram_page(page_address(page));
 }
+#endif
 
 /*
  * D cache only
@@ -101,6 +133,8 @@ static __inline__ void flush_page_to_ram(struct page *page)
 #define clean_dcache_range(_s,_e)	cpu_dcache_clean_range((_s),(_e))
 #define flush_dcache_range(_s,_e)	cpu_cache_clean_invalidate_range((_s),(_e),0)
 
+#define mapping_mapped(map)	((map)->i_mmap || (map)->i_mmap_shared)
+
 /*
  * flush_dcache_page is used when the kernel has written to the page
  * cache page at virtual address page->virtual.
@@ -116,8 +150,7 @@ static __inline__ void flush_page_to_ram(struct page *page)
  */
 static inline void flush_dcache_page(struct page *page)
 {
-	if (page->mapping && !(page->mapping->i_mmap) &&
-	     !(page->mapping->i_mmap_shared))
+	if (page->mapping && !mapping_mapped(page->mapping))
 		set_bit(PG_dcache_dirty, &page->flags);
 	else {
 		unsigned long virt = (unsigned long)page_address(page);
@@ -125,6 +158,30 @@ static inline void flush_dcache_page(struct page *page)
 	}
 }
 
+/*
+ * flush_icache_page makes the kernel page address consistent with the
+ * user space mappings.  The functionality is the same as flush_dcache_page,
+ * except we can do an optimisation and only clean the caches here if
+ * vma->vm_mm == current->active_mm.
+ *
+ * This function is misnamed IMHO.  There are three places where it
+ * is called, each of which is preceded immediately by a call to
+ * flush_page_to_ram:
+ */
+#ifdef flush_page_to_ram_ok
+static inline void flush_icache_page(struct vm_area_struct *vma, struct page *page)
+{
+	if (page->mapping && !mapping_mapped(page->mapping))
+		set_bit(PG_dcache_dirty, &page->flags);
+	else if (vma->vm_mm == current->active_mm) {
+		unsigned long virt = (unsigned long)page_address(page);
+		cpu_cache_clean_invalidate_range(virt, virt + PAGE_SIZE, 0);
+	}
+}
+#else
+#define flush_icache_page(vma,pg)	do { } while (0)
+#endif
+
 #define clean_dcache_entry(_s)		cpu_dcache_clean_entry((unsigned long)(_s))
 
 /*
@@ -143,32 +200,6 @@ static inline void flush_dcache_page(struct page *page)
 	} while (0)
 
 /*
- * This function is misnamed IMHO.  There are three places where it
- * is called, each of which is preceded immediately by a call to
- * flush_page_to_ram:
- *
- *  1. kernel/ptrace.c:access_one_page
- *     called after we have written to the kernel view of a user page.
- *     The user page has been expundged from the cache by flush_cache_page.
- *     [we don't need to do anything here if we add a call to
- *      flush_dcache_page]
- *
- *  2. mm/memory.c:do_swap_page
- *     called after we have (possibly) written to the kernel view of a
- *     user page, which has previously been removed (ie, has been through
- *     the swap cache).
- *     [if the flush_page_to_ram() conditions are satisfied, then ok]
- *
- *  3. mm/memory.c:do_no_page
- *     [if the flush_page_to_ram() conditions are satisfied, then ok]
- *
- * Invalidating the icache at the kernels virtual page isn't really
- * going to do us much good, since we wouldn't have executed any
- * instructions there.
- */
-#define flush_icache_page(vma,pg)	do { } while (0)
-
-/*
  * Old ARM MEMC stuff.  This supports the reversed mapping handling that
  * we have on the older 26-bit machines.  We don't have a MEMC chip, so...
  */
diff --git a/include/asm-arm/proc-armv/pgalloc.h b/include/asm-arm/proc-armv/pgalloc.h
index 6059f64550c0..f5db111e1e78 100644
--- a/include/asm-arm/proc-armv/pgalloc.h
+++ b/include/asm-arm/proc-armv/pgalloc.h
@@ -46,13 +46,12 @@ static inline void pte_free_slow(pte_t *pte)
  * If 'mm' is the init tasks mm, then we are doing a vmalloc, and we
  * need to set stuff up correctly for it.
  */
-#define pmd_populate(mm,pmdp,pte)			\
-	do {						\
-		unsigned long __prot;			\
-		if (mm == &init_mm)			\
-			__prot = _PAGE_KERNEL_TABLE;	\
-		else					\
-			__prot = _PAGE_USER_TABLE;	\
-		set_pmd(pmdp, __mk_pmd(pte, __prot));	\
+#define pmd_populate(mm,pmdp,pte)				\
+	do {							\
+		unsigned long __prot;				\
+		if (mm == &init_mm)				\
+			__prot = _PAGE_KERNEL_TABLE;		\
+		else						\
+			__prot = _PAGE_USER_TABLE;		\
+		set_pmd(pmdp, __mk_pmd(pte, __prot));		\
 	} while (0)
-
diff --git a/include/asm-arm/proc-armv/pgtable.h b/include/asm-arm/proc-armv/pgtable.h
index 7532698e47e7..d0da2c4a8d20 100644
--- a/include/asm-arm/proc-armv/pgtable.h
+++ b/include/asm-arm/proc-armv/pgtable.h
@@ -15,9 +15,6 @@
 #ifndef __ASM_PROC_PGTABLE_H
 #define __ASM_PROC_PGTABLE_H
 
-#include <asm/proc/domain.h>
-#include <asm/arch/vmalloc.h>
-
 /*
  * entries per page directory level: they are two-level, so
  * we don't really have any PMD directory.
@@ -26,27 +23,91 @@
 #define PTRS_PER_PMD		1
 #define PTRS_PER_PGD		4096
 
-/****************
-* PMD functions *
-****************/
-
-/* PMD types (actually level 1 descriptor) */
-#define PMD_TYPE_MASK		0x0003
-#define PMD_TYPE_FAULT		0x0000
-#define PMD_TYPE_TABLE		0x0001
-#define PMD_TYPE_SECT		0x0002
-#define PMD_UPDATABLE		0x0010
-#define PMD_SECT_CACHEABLE	0x0008
-#define PMD_SECT_BUFFERABLE	0x0004
-#define PMD_SECT_AP_WRITE	0x0400
-#define PMD_SECT_AP_READ	0x0800
+/*
+ * Hardware page table definitions.
+ *
+ * + Level 1 descriptor (PMD)
+ *   - common
+ */
+#define PMD_TYPE_MASK		(3 << 0)
+#define PMD_TYPE_FAULT		(0 << 0)
+#define PMD_TYPE_TABLE		(1 << 0)
+#define PMD_TYPE_SECT		(2 << 0)
+#define PMD_UPDATABLE		(1 << 4)
 #define PMD_DOMAIN(x)		((x) << 5)
+#define PMD_PROTECTION		(1 << 9)	/* v5 */
+/*
+ *   - section
+ */
+#define PMD_SECT_BUFFERABLE	(1 << 2)
+#define PMD_SECT_CACHEABLE	(1 << 3)
+#define PMD_SECT_AP_WRITE	(1 << 10)
+#define PMD_SECT_AP_READ	(1 << 11)
+#define PMD_SECT_TEX(x)		((x) << 12)	/* v5 */
+/*
+ *   - coarse table (not used)
+ */
+
+/*
+ * + Level 2 descriptor (PTE)
+ *   - common
+ */
+#define PTE_TYPE_MASK		(3 << 0)
+#define PTE_TYPE_FAULT		(0 << 0)
+#define PTE_TYPE_LARGE		(1 << 0)
+#define PTE_TYPE_SMALL		(2 << 0)
+#define PTE_TYPE_EXT		(3 << 0)	/* v5 */
+#define PTE_BUFFERABLE		(1 << 2)
+#define PTE_CACHEABLE		(1 << 3)
+
+/*
+ *   - extended small page/tiny page
+ */
+#define PTE_EXT_AP_UNO_SRO	(0 << 4)
+#define PTE_EXT_AP_UNO_SRW	(1 << 4)
+#define PTE_EXT_AP_URO_SRW	(2 << 4)
+#define PTE_EXT_AP_URW_SRW	(3 << 4)
+#define PTE_EXT_TEX(x)		((x) << 6)	/* v5 */
+
+/*
+ *   - small page
+ */
+#define PTE_SMALL_AP_UNO_SRO	(0x00 << 4)
+#define PTE_SMALL_AP_UNO_SRW	(0x55 << 4)
+#define PTE_SMALL_AP_URO_SRW	(0xaa << 4)
+#define PTE_SMALL_AP_URW_SRW	(0xff << 4)
+#define PTE_AP_READ		PTE_SMALL_AP_URO_SRW
+#define PTE_AP_WRITE		PTE_SMALL_AP_UNO_SRW
+
+/*
+ * "Linux" PTE definitions.
+ *
+ * We keep two sets of PTEs - the hardware and the linux version.
+ * This allows greater flexibility in the way we map the Linux bits
+ * onto the hardware tables, and allows us to have YOUNG and DIRTY
+ * bits.
+ *
+ * The PTE table pointer refers to the hardware entries; the "Linux"
+ * entries are stored 1024 bytes below.
+ */
+#define L_PTE_PRESENT		(1 << 0)
+#define L_PTE_YOUNG		(1 << 1)
+#define L_PTE_BUFFERABLE	(1 << 2)	/* matches PTE */
+#define L_PTE_CACHEABLE		(1 << 3)	/* matches PTE */
+#define L_PTE_USER		(1 << 4)
+#define L_PTE_WRITE		(1 << 5)
+#define L_PTE_EXEC		(1 << 6)
+#define L_PTE_DIRTY		(1 << 7)
+
+#ifndef __ASSEMBLY__
+
+#include <asm/proc/domain.h>
 
 #define _PAGE_USER_TABLE	(PMD_TYPE_TABLE | PMD_DOMAIN(DOMAIN_USER))
 #define _PAGE_KERNEL_TABLE	(PMD_TYPE_TABLE | PMD_DOMAIN(DOMAIN_KERNEL))
 
 #define pmd_bad(pmd)		(pmd_val(pmd) & 2)
-#define set_pmd(pmdp,pmd)	cpu_set_pmd(pmdp,pmd)
+#define set_pmd(pmdp,pmd)	cpu_set_pmd(pmdp, pmd)
 
 static inline pmd_t __mk_pmd(pte_t *ptep, unsigned long prot)
 {
@@ -75,49 +136,8 @@ static inline unsigned long pmd_page(pmd_t pmd)
 	return __phys_to_virt(ptr);
 }
 
-/****************
-* PTE functions *
-****************/
-
-/* PTE types (actually level 2 descriptor) */
-#define PTE_TYPE_MASK		0x0003
-#define PTE_TYPE_FAULT		0x0000
-#define PTE_TYPE_LARGE		0x0001
-#define PTE_TYPE_SMALL		0x0002
-#define PTE_AP_READ		0x0aa0
-#define PTE_AP_WRITE		0x0550
-#define PTE_CACHEABLE		0x0008
-#define PTE_BUFFERABLE		0x0004
-
 #define set_pte(ptep, pte)	cpu_set_pte(ptep,pte)
 
-/* We now keep two sets of ptes - the physical and the linux version.
- * This gives us many advantages, and allows us greater flexibility.
- *
- * The Linux pte's contain:
- *  bit   meaning
- *   0    page present
- *   1    young
- *   2    bufferable	- matches physical pte
- *   3    cacheable	- matches physical pte
- *   4    user
- *   5    write
- *   6    execute
- *   7    dirty
- *  8-11  unused
- *  12-31 virtual page address
- *
- * These are stored at the pte pointer; the physical PTE is at -1024bytes
- */
-#define L_PTE_PRESENT		(1 << 0)
-#define L_PTE_YOUNG		(1 << 1)
-#define L_PTE_BUFFERABLE	(1 << 2)
-#define L_PTE_CACHEABLE		(1 << 3)
-#define L_PTE_USER		(1 << 4)
-#define L_PTE_WRITE		(1 << 5)
-#define L_PTE_EXEC		(1 << 6)
-#define L_PTE_DIRTY		(1 << 7)
-
 /*
  * The following macros handle the cache and bufferable bits...
  */
@@ -163,4 +183,6 @@ PTE_BIT_FUNC(mkyoung,   |= L_PTE_YOUNG);
  */
 #define pgprot_noncached(prot)	__pgprot(pgprot_val(prot) & ~(L_PTE_CACHEABLE | L_PTE_BUFFERABLE))
 
+#endif /* __ASSEMBLY__ */
+
 #endif /* __ASM_PROC_PGTABLE_H */
diff --git a/include/asm-arm/proc-armv/ptrace.h b/include/asm-arm/proc-armv/ptrace.h
index 190caa1937d5..fcc127811e50 100644
--- a/include/asm-arm/proc-armv/ptrace.h
+++ b/include/asm-arm/proc-armv/ptrace.h
@@ -12,27 +12,51 @@
 
 #include <linux/config.h>
 
-#define USR26_MODE	0x00
-#define FIQ26_MODE	0x01
-#define IRQ26_MODE	0x02
-#define SVC26_MODE	0x03
-#define USR_MODE	0x10
-#define FIQ_MODE	0x11
-#define IRQ_MODE	0x12
-#define SVC_MODE	0x13
-#define ABT_MODE	0x17
-#define UND_MODE	0x1b
-#define SYSTEM_MODE	0x1f
-#define MODE_MASK	0x1f
-#define T_BIT		0x20
-#define F_BIT		0x40
-#define I_BIT		0x80
-#define CC_V_BIT	(1 << 28)
-#define CC_C_BIT	(1 << 29)
-#define CC_Z_BIT	(1 << 30)
-#define CC_N_BIT	(1 << 31)
+/*
+ * PSR bits
+ */
+#define USR26_MODE	0x00000000
+#define FIQ26_MODE	0x00000001
+#define IRQ26_MODE	0x00000002
+#define SVC26_MODE	0x00000003
+#define USR_MODE	0x00000010
+#define FIQ_MODE	0x00000011
+#define IRQ_MODE	0x00000012
+#define SVC_MODE	0x00000013
+#define ABT_MODE	0x00000017
+#define UND_MODE	0x0000001b
+#define SYSTEM_MODE	0x0000001f
+#define MODE32_BIT	0x00000010
+#define MODE_MASK	0x0000001f
+#define PSR_T_BIT	0x00000020
+#define PSR_F_BIT	0x00000040
+#define PSR_I_BIT	0x00000080
+#define PSR_J_BIT	0x01000000
+#define PSR_V_BIT	0x10000000
+#define PSR_C_BIT	0x20000000
+#define PSR_Z_BIT	0x40000000
+#define PSR_N_BIT	0x80000000
 #define PCMASK		0
 
+/*
+ * CR1 bits
+ */
+#define CR1_M		0x00000001	/* MMU			*/
+#define CR1_A		0x00000002	/* Alignment fault	*/
+#define CR1_C		0x00000004	/* Dcache		*/
+#define CR1_W		0x00000008	/* Write buffer		*/
+#define CR1_P		0x00000010	/* Prog32		*/
+#define CR1_D		0x00000020	/* Data32		*/
+#define CR1_L		0x00000040	/* Late abort		*/
+#define CR1_B		0x00000080	/* Big endian		*/
+#define CR1_S		0x00000100	/* System protection	*/
+#define CR1_R		0x00000200	/* ROM protection	*/
+#define CR1_F		0x00000400
+#define CR1_Z		0x00000800	/* BTB enable		*/
+#define CR1_I		0x00001000	/* Icache		*/
+#define CR1_V		0x00002000	/* Vector relocation	*/
+#define CR1_RR		0x00004000	/* Round Robin		*/
+
 #ifndef __ASSEMBLY__
 
 /* this struct defines the way the registers are stored on the
@@ -68,7 +92,7 @@ struct pt_regs {
 
 #ifdef CONFIG_ARM_THUMB
 #define thumb_mode(regs) \
-	(((regs)->ARM_cpsr & T_BIT))
+	(((regs)->ARM_cpsr & PSR_T_BIT))
 #else
 #define thumb_mode(regs) (0)
 #endif
@@ -77,27 +101,27 @@ struct pt_regs {
 	((regs)->ARM_cpsr & MODE_MASK)
 
 #define interrupts_enabled(regs) \
-	(!((regs)->ARM_cpsr & I_BIT))
+	(!((regs)->ARM_cpsr & PSR_I_BIT))
 
 #define fast_interrupts_enabled(regs) \
-	(!((regs)->ARM_cpsr & F_BIT))
+	(!((regs)->ARM_cpsr & PSR_F_BIT))
 
 #define condition_codes(regs) \
-	((regs)->ARM_cpsr & (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT))
+	((regs)->ARM_cpsr & (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT))
 	
 /* Are the current registers suitable for user mode?
  * (used to maintain security in signal handlers)
  */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
-	if ((regs->ARM_cpsr & 0xf) == 0 &&
-	    (regs->ARM_cpsr & (F_BIT|I_BIT)) == 0)
+	if (user_mode(regs) &&
+	    (regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0)
 		return 1;
 
 	/*
 	 * Force CPSR to something logical...
 	 */
-	regs->ARM_cpsr &= (CC_V_BIT|CC_C_BIT|CC_Z_BIT|CC_N_BIT|0x10);
+	regs->ARM_cpsr &= (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT|MODE32_BIT);
 
 	return 0;
 }
diff --git a/include/asm-arm/proc-armv/uaccess.h b/include/asm-arm/proc-armv/uaccess.h
index 74c5e6992396..8053f9d9f86f 100644
--- a/include/asm-arm/proc-armv/uaccess.h
+++ b/include/asm-arm/proc-armv/uaccess.h
@@ -54,6 +54,7 @@ static inline void set_fs (mm_segment_t fs)
 	: "=r" (err)						\
 	: "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
 
+#ifndef __ARMEB__
 #define __put_user_asm_half(x,addr,err)				\
 ({								\
 	unsigned long __temp = (unsigned long)(x);		\
@@ -61,6 +62,15 @@ static inline void set_fs (mm_segment_t fs)
 	__put_user_asm_byte(__temp, __ptr, err);		\
 	__put_user_asm_byte(__temp >> 8, __ptr + 1, err);	\
 })
+#else
+#define __put_user_asm_half(x,addr,err)				\
+({								\
+	unsigned long __temp = (unsigned long)(x);		\
+	unsigned long __ptr  = (unsigned long)(addr);		\
+	__put_user_asm_byte(__temp >> 8, __ptr, err);		\
+	__put_user_asm_byte(__temp, __ptr + 1, err);	\
+})
+#endif
 
 #define __put_user_asm_word(x,addr,err)				\
 	__asm__ __volatile__(					\
@@ -95,6 +105,7 @@ static inline void set_fs (mm_segment_t fs)
 	: "=r" (err), "=&r" (x)					\
 	: "r" (addr), "i" (-EFAULT), "0" (err))
 
+#ifndef __ARMEB__
 #define __get_user_asm_half(x,addr,err)				\
 ({								\
 	unsigned long __b1, __b2, __ptr = (unsigned long)addr;	\
@@ -102,7 +113,15 @@ static inline void set_fs (mm_segment_t fs)
 	__get_user_asm_byte(__b2, __ptr + 1, err);		\
 	(x) = __b1 | (__b2 << 8);				\
 })
-
+#else
+#define __get_user_asm_half(x,addr,err)				\
+({								\
+	unsigned long __b1, __b2;				\
+	__get_user_asm_byte(__b1, addr, err);			\
+	__get_user_asm_byte(__b2, (int)(addr) + 1, err);	\
+	(x) = (__b1 << 8) | __b2;				\
+})
+#endif
 
 #define __get_user_asm_word(x,addr,err)				\
 	__asm__ __volatile__(					\
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index 44f1cd429ee0..1f212216a757 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -26,6 +26,12 @@
 # define MULTI_CPU
 #endif
 
+/*
+ * CPU_NAME - the prefix for CPU related functions
+ * CPU_ABRT - the prefix for the CPU abort decoding function
+ * MMU_ARCH - the prefix for copy_user_page/clear_user_page
+ */
+
 #ifdef CONFIG_CPU_32
 # define CPU_INCLUDE_NAME "asm/cpu-multi32.h"
 # ifdef CONFIG_CPU_ARM610
@@ -33,7 +39,9 @@
 #   undef  MULTI_CPU
 #   define MULTI_CPU
 #  else
-#   define CPU_NAME arm6
+#   define CPU_NAME cpu_arm6
+#   define CPU_ABRT cpu_arm6
+#   define MMU_ARCH armv3
 #  endif
 # endif
 # ifdef CONFIG_CPU_ARM710
@@ -41,7 +49,9 @@
 #   undef  MULTI_CPU
 #   define MULTI_CPU
 #  else
-#   define CPU_NAME arm7
+#   define CPU_NAME cpu_arm7
+#   define CPU_ABRT cpu_arm7
+#   define MMU_ARCH armv3
 #  endif
 # endif
 # ifdef CONFIG_CPU_ARM720T
@@ -49,7 +59,9 @@
 #   undef  MULTI_CPU
 #   define MULTI_CPU
 #  else
-#   define CPU_NAME arm720
+#   define CPU_NAME cpu_arm720
+#   define CPU_ABRT armv4t_late
+#   define MMU_ARCH armv4
 #  endif
 # endif
 # ifdef CONFIG_CPU_ARM920T
@@ -57,7 +69,19 @@
 #   undef  MULTI_CPU
 #   define MULTI_CPU
 #  else
-#   define CPU_NAME arm920
+#   define CPU_NAME cpu_arm920
+#   define CPU_ABRT armv4t_early
+#   define MMU_ARCH armv4
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM922T
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm922
+#   define CPU_ABRT armv4t_early
+#   define MMU_ARCH armv4
 #  endif
 # endif
 # ifdef CONFIG_CPU_ARM926T
@@ -65,7 +89,9 @@
 #   undef  MULTI_CPU
 #   define MULTI_CPU
 #  else
-#   define CPU_NAME arm926
+#   define CPU_NAME cpu_arm926
+#   define CPU_ABRT armv5ej_early
+#   define MMU_ARCH armv4
 #  endif
 # endif
 # ifdef CONFIG_CPU_SA110
@@ -73,7 +99,9 @@
 #   undef  MULTI_CPU
 #   define MULTI_CPU
 #  else
-#   define CPU_NAME sa110
+#   define CPU_NAME cpu_sa110
+#   define CPU_ABRT armv4_early
+#   define MMU_ARCH armv4
 #  endif
 # endif
 # ifdef CONFIG_CPU_SA1100
@@ -81,7 +109,29 @@
 #   undef  MULTI_CPU
 #   define MULTI_CPU
 #  else
-#   define CPU_NAME sa1100
+#   define CPU_NAME cpu_sa1100
+#   define CPU_ABRT armv4_early
+#   define MMU_ARCH armv4_mc
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM1020
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm1020
+#   define CPU_ABRT armv4t_early
+#   define MMU_ARCH armv4
+#  endif
+# endif
+# ifdef CONFIG_CPU_XSCALE
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_xscale
+#   define CPU_ABRT armv4t_early
+#   define MMU_ARCH armv5te
 #  endif
 # endif
 #endif
diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h
index aa0148d9054f..cd4a06d7c49f 100644
--- a/include/asm-arm/processor.h
+++ b/include/asm-arm/processor.h
@@ -68,13 +68,6 @@ struct thread_struct {
 	EXTRA_THREAD_STRUCT
 };
 
-#define INIT_MMAP {					\
-	vm_mm:		&init_mm,			\
-	vm_page_prot:	PAGE_SHARED,			\
-	vm_flags:	VM_READ | VM_WRITE | VM_EXEC,	\
-	vm_avl_height:	1,				\
-}
-
 #define INIT_THREAD  {					\
 	refcount:	ATOMIC_INIT(1),			\
 	EXTRA_THREAD_STRUCT_INIT			\
diff --git a/include/asm-arm/scatterlist.h b/include/asm-arm/scatterlist.h
index ea8d1ab4d417..acf0d18ea46c 100644
--- a/include/asm-arm/scatterlist.h
+++ b/include/asm-arm/scatterlist.h
@@ -5,8 +5,11 @@
 
 struct scatterlist {
 	char		*address;	/* virtual address		 */
+	struct page	*page;		/* Location for highmem page, if any */
+	unsigned int	offset;		/* for highmem, page offset	 */
 	dma_addr_t	dma_address;	/* dma address			 */
 	unsigned int	length;		/* length			 */
+	char		*__address;	/* for set_dma_addr		 */
 };
 
 /*
diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h
index 39d5290f54f8..7b66b95e5451 100644
--- a/include/asm-arm/types.h
+++ b/include/asm-arm/types.h
@@ -44,6 +44,7 @@ typedef unsigned long long u64;
 /* Dma addresses are 32-bits wide.  */
 
 typedef u32 dma_addr_t;
+typedef u32 dma64_addr_t;
 
 #endif /* __KERNEL__ */
 
diff --git a/include/asm-arm/unaligned.h b/include/asm-arm/unaligned.h
index 44aa2e3b1c5b..a5f2abf845cf 100644
--- a/include/asm-arm/unaligned.h
+++ b/include/asm-arm/unaligned.h
@@ -39,24 +39,30 @@ extern int __bug_unaligned_x(void *ptr);
  * out of long long >> 32, or the low word from long long << 32
  */
 
-#define __get_unaligned_2(__p)					\
+#define __get_unaligned_2_le(__p)					\
 	(__p[0] | __p[1] << 8)
 
-#define __get_unaligned_4(__p)					\
+#define __get_unaligned_2_be(__p)					\
+	(__p[0] << 8 | __p[1])
+
+#define __get_unaligned_4_le(__p)					\
 	(__p[0] | __p[1] << 8 | __p[2] << 16 | __p[3] << 24)
 
-#define get_unaligned(ptr)					\
+#define __get_unaligned_4_be(__p)					\
+	(__p[0] << 24 | __p[1] << 16 | __p[2] << 8 | __p[3])
+
+#define __get_unaligned_le(ptr)					\
 	({							\
 		__typeof__(*(ptr)) __v;				\
 		__u8 *__p = (__u8 *)(ptr);			\
 		switch (sizeof(*(ptr))) {			\
 		case 1:	__v = *(ptr);			break;	\
-		case 2: __v = __get_unaligned_2(__p);	break;	\
-		case 4: __v = __get_unaligned_4(__p);	break;	\
+		case 2: __v = __get_unaligned_2_le(__p);	break;	\
+		case 4: __v = __get_unaligned_4_le(__p);	break;	\
 		case 8: {					\
 				unsigned int __v1, __v2;	\
-				__v2 = __get_unaligned_4((__p+4)); \
-				__v1 = __get_unaligned_4(__p);	\
+				__v2 = __get_unaligned_4_le((__p+4)); \
+				__v1 = __get_unaligned_4_le(__p);	\
 				__v = ((unsigned long long)__v2 << 32 | __v1);	\
 			}					\
 			break;					\
@@ -65,44 +71,87 @@ extern int __bug_unaligned_x(void *ptr);
 		__v;						\
 	})
 
+#define __get_unaligned_be(ptr)					\
+	({							\
+		__typeof__(*(ptr)) __v;				\
+		__u8 *__p = (__u8 *)(ptr);			\
+		switch (sizeof(*(ptr))) {			\
+		case 1:	__v = *(ptr);			break;	\
+		case 2: __v = __get_unaligned_2_be(__p);	break;	\
+		case 4: __v = __get_unaligned_4_be(__p);	break;	\
+		case 8: {					\
+				unsigned int __v1, __v2;	\
+				__v2 = __get_unaligned_4_be(__p); \
+				__v1 = __get_unaligned_4_be((__p+4));	\
+				__v = ((unsigned long long)__v2 << 32 | __v1);	\
+			}					\
+			break;					\
+		default: __v = __bug_unaligned_x(__p);	break;	\
+		}						\
+		__v;						\
+	})
 
-static inline void __put_unaligned_2(__u32 __v, register __u8 *__p)
+
+static inline void __put_unaligned_2_le(__u32 __v, register __u8 *__p)
 {
 	*__p++ = __v;
 	*__p++ = __v >> 8;
 }
 
-static inline void __put_unaligned_4(__u32 __v, register __u8 *__p)
+static inline void __put_unaligned_2_be(__u32 __v, register __u8 *__p)
+{
+	*__p++ = __v >> 8;
+	*__p++ = __v;
+}
+
+static inline void __put_unaligned_4_le(__u32 __v, register __u8 *__p)
+{
+	__put_unaligned_2_le(__v >> 16, __p + 2);
+	__put_unaligned_2_le(__v, __p);
+}
+
+static inline void __put_unaligned_4_be(__u32 __v, register __u8 *__p)
 {
-	__put_unaligned_2(__v >> 16, __p + 2);
-	__put_unaligned_2(__v, __p);
+	__put_unaligned_2_be(__v >> 16, __p);
+	__put_unaligned_2_be(__v, __p + 2);
 }
 
-static inline void __put_unaligned_8(const unsigned long long __v, register __u8 *__p)
+static inline void __put_unaligned_8_le(const unsigned long long __v, register __u8 *__p)
 {
 	/*
 	 * tradeoff: 8 bytes of stack for all unaligned puts (2
 	 * instructions), or an extra register in the long long
 	 * case - go for the extra register.
 	 */
-	__put_unaligned_4(__v >> 32, __p+4);
-	__put_unaligned_4(__v, __p);
+	__put_unaligned_4_le(__v >> 32, __p+4);
+	__put_unaligned_4_le(__v, __p);
+}
+
+static inline void __put_unaligned_8_be(const unsigned long long __v, register __u8 *__p)
+{
+	/*
+	 * tradeoff: 8 bytes of stack for all unaligned puts (2
+	 * instructions), or an extra register in the long long
+	 * case - go for the extra register.
+	 */
+	__put_unaligned_4_be(__v >> 32, __p);
+	__put_unaligned_4_be(__v, __p+4);
 }
 
 /*
  * Try to store an unaligned value as efficiently as possible.
  */
-#define put_unaligned(val,ptr)					\
+#define __put_unaligned_le(val,ptr)					\
 	({							\
 		switch (sizeof(*(ptr))) {			\
 		case 1:						\
 			*(ptr) = (val);				\
 			break;					\
-		case 2: __put_unaligned_2((val),(__u8 *)(ptr));	\
+		case 2: __put_unaligned_2_le((val),(__u8 *)(ptr));	\
 			break;					\
-		case 4:	__put_unaligned_4((val),(__u8 *)(ptr));	\
+		case 4:	__put_unaligned_4_le((val),(__u8 *)(ptr));	\
 			break;					\
-		case 8:	__put_unaligned_8((val),(__u8 *)(ptr)); \
+		case 8:	__put_unaligned_8_le((val),(__u8 *)(ptr)); \
 			break;					\
 		default: __bug_unaligned_x(ptr);		\
 			break;					\
@@ -110,5 +159,33 @@ static inline void __put_unaligned_8(const unsigned long long __v, register __u8
 		(void) 0;					\
 	})
 
+#define put_unaligned_be(val,ptr)					\
+	({							\
+		switch (sizeof(*(ptr))) {			\
+		case 1:						\
+			*(ptr) = (val);				\
+			break;					\
+		case 2: __put_unaligned_2_be((val),(__u8 *)(ptr));	\
+			break;					\
+		case 4:	__put_unaligned_4_be((val),(__u8 *)(ptr));	\
+			break;					\
+		case 8:	__put_unaligned_8_be((val),(__u8 *)(ptr)); \
+			break;					\
+		default: __bug_unaligned_x(ptr);		\
+			break;					\
+		}						\
+		(void) 0;					\
+	})
+
+/*
+ * Select endianness
+ */
+#ifndef __ARMEB__
+#define get_unaligned	__get_unaligned_le
+#define put_unaligned	__put_unaligned_le
+#else
+#define get_unaligned	__get_unaligned_be
+#define put_unaligned	__put_unaligned_be
+#endif
 
 #endif
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index 510cac1b8435..674856b862cf 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -240,6 +240,10 @@
 #define __NR_mincore			(__NR_SYSCALL_BASE+219)
 #define __NR_madvise			(__NR_SYSCALL_BASE+220)
 #define __NR_fcntl64			(__NR_SYSCALL_BASE+221)
+					/* 222 for tux */
+#define __NR_security			(__NR_SYSCALL_BASE+223)
+#define __NR_gettid			(__NR_SYSCALL_BASE+224)
+#define __NR_readahead			(__NR_SYSCALL_BASE+225)
 
 /*
  * The following SWIs are ARM private.
@@ -357,6 +361,9 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) {			\
 
 #ifdef __KERNEL_SYSCALLS__
 
+struct rusage;
+asmlinkage long sys_wait4(pid_t pid,unsigned int * stat_addr, int options, struct rusage * ru);
+
 static inline long idle(void)
 {
 	extern long sys_idle(void);
diff --git a/include/asm-arm/vt.h b/include/asm-arm/vt.h
deleted file mode 100644
index 6c3573768b76..000000000000
--- a/include/asm-arm/vt.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _ASMARM_VT_H
-#define _ASMARM_VT_H
-
-#define VT_GETSCRINFO	0x56FD	/* get screen info */
-#define VT_GETPALETTE	0x56FE  /* get palette */
-#define VT_SETPALETTE	0x56FF  /* set palette */
-
-#endif /* _ASMARM_VT_H */
diff --git a/include/linux/tpqic02.h b/include/linux/tpqic02.h
index e7e3cc625bef..2972cb2f827c 100644
--- a/include/linux/tpqic02.h
+++ b/include/linux/tpqic02.h
@@ -587,10 +587,10 @@
  *  |___________________ Reserved for diagnostics during debugging.
  */
 
-#define	TP_REWCLOSE(d)	((MINOR(d)&0x01) == 1)	   		/* rewind bit */
+#define	TP_REWCLOSE(d)	((minor(d)&0x01) == 1)	   		/* rewind bit */
 			   /* rewind is only done if data has been transferred */
-#define	TP_DENS(dev)	((MINOR(dev) >> 1) & 0x07) 	      /* tape density */
-#define TP_UNIT(dev)	((MINOR(dev) >> 4) & 0x07)	       /* unit number */
+#define	TP_DENS(dev)	((minor(dev) >> 1) & 0x07) 	      /* tape density */
+#define TP_UNIT(dev)	((minor(dev) >> 4) & 0x07)	       /* unit number */
 
 /* print excessive diagnostics */
 #define TP_DIAGS(dev)	(QIC02_TAPE_DEBUG & TPQD_DIAGS)